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3045a5f5 KW |
1 | /* |
2 | * LPC32xx built-in touchscreen driver | |
3 | * | |
4 | * Copyright (C) 2010 NXP Semiconductors | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/platform_device.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/input.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/slab.h> | |
5cb727a8 | 25 | #include <linux/of.h> |
3045a5f5 KW |
26 | |
27 | /* | |
28 | * Touchscreen controller register offsets | |
29 | */ | |
30 | #define LPC32XX_TSC_STAT 0x00 | |
31 | #define LPC32XX_TSC_SEL 0x04 | |
32 | #define LPC32XX_TSC_CON 0x08 | |
33 | #define LPC32XX_TSC_FIFO 0x0C | |
34 | #define LPC32XX_TSC_DTR 0x10 | |
35 | #define LPC32XX_TSC_RTR 0x14 | |
36 | #define LPC32XX_TSC_UTR 0x18 | |
37 | #define LPC32XX_TSC_TTR 0x1C | |
38 | #define LPC32XX_TSC_DXP 0x20 | |
39 | #define LPC32XX_TSC_MIN_X 0x24 | |
40 | #define LPC32XX_TSC_MAX_X 0x28 | |
41 | #define LPC32XX_TSC_MIN_Y 0x2C | |
42 | #define LPC32XX_TSC_MAX_Y 0x30 | |
43 | #define LPC32XX_TSC_AUX_UTR 0x34 | |
44 | #define LPC32XX_TSC_AUX_MIN 0x38 | |
45 | #define LPC32XX_TSC_AUX_MAX 0x3C | |
46 | ||
47 | #define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8) | |
48 | #define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7) | |
49 | ||
50 | #define LPC32XX_TSC_SEL_DEFVAL 0x0284 | |
51 | ||
52 | #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11) | |
53 | #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7) | |
54 | #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4) | |
55 | #define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2) | |
56 | #define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0) | |
57 | ||
58 | #define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31) | |
59 | #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16) | |
60 | #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF) | |
61 | ||
62 | #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF | |
63 | ||
64 | #define LPC32XX_TSC_MIN_XY_VAL 0x0 | |
65 | #define LPC32XX_TSC_MAX_XY_VAL 0x3FF | |
66 | ||
67 | #define MOD_NAME "ts-lpc32xx" | |
68 | ||
69 | #define tsc_readl(dev, reg) \ | |
70 | __raw_readl((dev)->tsc_base + (reg)) | |
71 | #define tsc_writel(dev, reg, val) \ | |
72 | __raw_writel((val), (dev)->tsc_base + (reg)) | |
73 | ||
74 | struct lpc32xx_tsc { | |
75 | struct input_dev *dev; | |
76 | void __iomem *tsc_base; | |
77 | int irq; | |
78 | struct clk *clk; | |
79 | }; | |
80 | ||
81 | static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc) | |
82 | { | |
83 | while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) & | |
84 | LPC32XX_TSC_STAT_FIFO_EMPTY)) | |
85 | tsc_readl(tsc, LPC32XX_TSC_FIFO); | |
86 | } | |
87 | ||
88 | static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id) | |
89 | { | |
90 | u32 tmp, rv[4], xs[4], ys[4]; | |
91 | int idx; | |
92 | struct lpc32xx_tsc *tsc = dev_id; | |
93 | struct input_dev *input = tsc->dev; | |
94 | ||
95 | tmp = tsc_readl(tsc, LPC32XX_TSC_STAT); | |
96 | ||
97 | if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) { | |
98 | /* FIFO overflow - throw away samples */ | |
99 | lpc32xx_fifo_clear(tsc); | |
100 | return IRQ_HANDLED; | |
101 | } | |
102 | ||
103 | /* | |
104 | * Gather and normalize 4 samples. Pen-up events may have less | |
105 | * than 4 samples, but its ok to pop 4 and let the last sample | |
106 | * pen status check drop the samples. | |
107 | */ | |
108 | idx = 0; | |
109 | while (idx < 4 && | |
110 | !(tsc_readl(tsc, LPC32XX_TSC_STAT) & | |
111 | LPC32XX_TSC_STAT_FIFO_EMPTY)) { | |
112 | tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO); | |
113 | xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK - | |
114 | LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp); | |
115 | ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK - | |
116 | LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp); | |
117 | rv[idx] = tmp; | |
118 | idx++; | |
119 | } | |
120 | ||
121 | /* Data is only valid if pen is still down in last sample */ | |
122 | if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) { | |
123 | /* Use average of 2nd and 3rd sample for position */ | |
124 | input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2); | |
125 | input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2); | |
126 | input_report_key(input, BTN_TOUCH, 1); | |
127 | } else { | |
128 | input_report_key(input, BTN_TOUCH, 0); | |
129 | } | |
130 | ||
131 | input_sync(input); | |
132 | ||
133 | return IRQ_HANDLED; | |
134 | } | |
135 | ||
136 | static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc) | |
137 | { | |
138 | /* Disable auto mode */ | |
139 | tsc_writel(tsc, LPC32XX_TSC_CON, | |
140 | tsc_readl(tsc, LPC32XX_TSC_CON) & | |
141 | ~LPC32XX_TSC_ADCCON_AUTO_EN); | |
142 | ||
143 | clk_disable(tsc->clk); | |
144 | } | |
145 | ||
146 | static void lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc) | |
147 | { | |
148 | u32 tmp; | |
149 | ||
150 | clk_enable(tsc->clk); | |
151 | ||
152 | tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP; | |
153 | ||
154 | /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */ | |
155 | tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 | | |
156 | LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) | | |
157 | LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10); | |
158 | tsc_writel(tsc, LPC32XX_TSC_CON, tmp); | |
159 | ||
160 | /* These values are all preset */ | |
161 | tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL); | |
162 | tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL); | |
163 | tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL); | |
164 | tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL); | |
165 | tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL); | |
166 | ||
167 | /* Aux support is not used */ | |
168 | tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0); | |
169 | tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0); | |
170 | tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0); | |
171 | ||
172 | /* | |
173 | * Set sample rate to about 240Hz per X/Y pair. A single measurement | |
174 | * consists of 4 pairs which gives about a 60Hz sample rate based on | |
175 | * a stable 32768Hz clock source. Values are in clocks. | |
176 | * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4 | |
177 | */ | |
178 | tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2); | |
179 | tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2); | |
180 | tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10); | |
181 | tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4); | |
182 | tsc_writel(tsc, LPC32XX_TSC_UTR, 88); | |
183 | ||
184 | lpc32xx_fifo_clear(tsc); | |
185 | ||
186 | /* Enable automatic ts event capture */ | |
187 | tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN); | |
188 | } | |
189 | ||
190 | static int lpc32xx_ts_open(struct input_dev *dev) | |
191 | { | |
192 | struct lpc32xx_tsc *tsc = input_get_drvdata(dev); | |
193 | ||
194 | lpc32xx_setup_tsc(tsc); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static void lpc32xx_ts_close(struct input_dev *dev) | |
200 | { | |
201 | struct lpc32xx_tsc *tsc = input_get_drvdata(dev); | |
202 | ||
203 | lpc32xx_stop_tsc(tsc); | |
204 | } | |
205 | ||
5298cc4c | 206 | static int lpc32xx_ts_probe(struct platform_device *pdev) |
3045a5f5 KW |
207 | { |
208 | struct lpc32xx_tsc *tsc; | |
209 | struct input_dev *input; | |
210 | struct resource *res; | |
211 | resource_size_t size; | |
212 | int irq; | |
213 | int error; | |
214 | ||
215 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
216 | if (!res) { | |
217 | dev_err(&pdev->dev, "Can't get memory resource\n"); | |
218 | return -ENOENT; | |
219 | } | |
220 | ||
221 | irq = platform_get_irq(pdev, 0); | |
222 | if (irq < 0) { | |
223 | dev_err(&pdev->dev, "Can't get interrupt resource\n"); | |
224 | return irq; | |
225 | } | |
226 | ||
227 | tsc = kzalloc(sizeof(*tsc), GFP_KERNEL); | |
228 | input = input_allocate_device(); | |
229 | if (!tsc || !input) { | |
230 | dev_err(&pdev->dev, "failed allocating memory\n"); | |
231 | error = -ENOMEM; | |
232 | goto err_free_mem; | |
233 | } | |
234 | ||
235 | tsc->dev = input; | |
236 | tsc->irq = irq; | |
237 | ||
238 | size = resource_size(res); | |
239 | ||
240 | if (!request_mem_region(res->start, size, pdev->name)) { | |
241 | dev_err(&pdev->dev, "TSC registers are not free\n"); | |
242 | error = -EBUSY; | |
243 | goto err_free_mem; | |
244 | } | |
245 | ||
246 | tsc->tsc_base = ioremap(res->start, size); | |
247 | if (!tsc->tsc_base) { | |
248 | dev_err(&pdev->dev, "Can't map memory\n"); | |
249 | error = -ENOMEM; | |
250 | goto err_release_mem; | |
251 | } | |
252 | ||
253 | tsc->clk = clk_get(&pdev->dev, NULL); | |
254 | if (IS_ERR(tsc->clk)) { | |
255 | dev_err(&pdev->dev, "failed getting clock\n"); | |
256 | error = PTR_ERR(tsc->clk); | |
257 | goto err_unmap; | |
258 | } | |
259 | ||
260 | input->name = MOD_NAME; | |
261 | input->phys = "lpc32xx/input0"; | |
262 | input->id.bustype = BUS_HOST; | |
263 | input->id.vendor = 0x0001; | |
264 | input->id.product = 0x0002; | |
265 | input->id.version = 0x0100; | |
266 | input->dev.parent = &pdev->dev; | |
267 | input->open = lpc32xx_ts_open; | |
268 | input->close = lpc32xx_ts_close; | |
269 | ||
270 | input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); | |
271 | input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); | |
272 | input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL, | |
273 | LPC32XX_TSC_MAX_XY_VAL, 0, 0); | |
274 | input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL, | |
275 | LPC32XX_TSC_MAX_XY_VAL, 0, 0); | |
276 | ||
277 | input_set_drvdata(input, tsc); | |
278 | ||
279 | error = request_irq(tsc->irq, lpc32xx_ts_interrupt, | |
ec4665c4 | 280 | 0, pdev->name, tsc); |
3045a5f5 KW |
281 | if (error) { |
282 | dev_err(&pdev->dev, "failed requesting interrupt\n"); | |
283 | goto err_put_clock; | |
284 | } | |
285 | ||
286 | error = input_register_device(input); | |
287 | if (error) { | |
288 | dev_err(&pdev->dev, "failed registering input device\n"); | |
289 | goto err_free_irq; | |
290 | } | |
291 | ||
292 | platform_set_drvdata(pdev, tsc); | |
293 | device_init_wakeup(&pdev->dev, 1); | |
294 | ||
295 | return 0; | |
296 | ||
297 | err_free_irq: | |
298 | free_irq(tsc->irq, tsc); | |
299 | err_put_clock: | |
300 | clk_put(tsc->clk); | |
301 | err_unmap: | |
302 | iounmap(tsc->tsc_base); | |
303 | err_release_mem: | |
304 | release_mem_region(res->start, size); | |
305 | err_free_mem: | |
306 | input_free_device(input); | |
307 | kfree(tsc); | |
308 | ||
309 | return error; | |
310 | } | |
311 | ||
312 | static int __devexit lpc32xx_ts_remove(struct platform_device *pdev) | |
313 | { | |
314 | struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev); | |
315 | struct resource *res; | |
316 | ||
317 | device_init_wakeup(&pdev->dev, 0); | |
318 | free_irq(tsc->irq, tsc); | |
319 | ||
320 | input_unregister_device(tsc->dev); | |
321 | ||
322 | clk_put(tsc->clk); | |
323 | ||
324 | iounmap(tsc->tsc_base); | |
325 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
326 | release_mem_region(res->start, resource_size(res)); | |
327 | ||
328 | kfree(tsc); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | #ifdef CONFIG_PM | |
334 | static int lpc32xx_ts_suspend(struct device *dev) | |
335 | { | |
336 | struct lpc32xx_tsc *tsc = dev_get_drvdata(dev); | |
337 | struct input_dev *input = tsc->dev; | |
338 | ||
339 | /* | |
340 | * Suspend and resume can be called when the device hasn't been | |
341 | * enabled. If there are no users that have the device open, then | |
342 | * avoid calling the TSC stop and start functions as the TSC | |
343 | * isn't yet clocked. | |
344 | */ | |
345 | mutex_lock(&input->mutex); | |
346 | ||
347 | if (input->users) { | |
348 | if (device_may_wakeup(dev)) | |
349 | enable_irq_wake(tsc->irq); | |
350 | else | |
351 | lpc32xx_stop_tsc(tsc); | |
352 | } | |
353 | ||
354 | mutex_unlock(&input->mutex); | |
355 | ||
356 | return 0; | |
357 | } | |
358 | ||
359 | static int lpc32xx_ts_resume(struct device *dev) | |
360 | { | |
361 | struct lpc32xx_tsc *tsc = dev_get_drvdata(dev); | |
362 | struct input_dev *input = tsc->dev; | |
363 | ||
364 | mutex_lock(&input->mutex); | |
365 | ||
366 | if (input->users) { | |
367 | if (device_may_wakeup(dev)) | |
368 | disable_irq_wake(tsc->irq); | |
369 | else | |
370 | lpc32xx_setup_tsc(tsc); | |
371 | } | |
372 | ||
373 | mutex_unlock(&input->mutex); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
378 | static const struct dev_pm_ops lpc32xx_ts_pm_ops = { | |
379 | .suspend = lpc32xx_ts_suspend, | |
380 | .resume = lpc32xx_ts_resume, | |
381 | }; | |
382 | #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops) | |
383 | #else | |
384 | #define LPC32XX_TS_PM_OPS NULL | |
385 | #endif | |
386 | ||
5cb727a8 RS |
387 | #ifdef CONFIG_OF |
388 | static struct of_device_id lpc32xx_tsc_of_match[] = { | |
34604086 | 389 | { .compatible = "nxp,lpc3220-tsc", }, |
5cb727a8 RS |
390 | { }, |
391 | }; | |
392 | MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match); | |
393 | #endif | |
394 | ||
3045a5f5 KW |
395 | static struct platform_driver lpc32xx_ts_driver = { |
396 | .probe = lpc32xx_ts_probe, | |
1cb0aa88 | 397 | .remove = lpc32xx_ts_remove, |
3045a5f5 KW |
398 | .driver = { |
399 | .name = MOD_NAME, | |
400 | .owner = THIS_MODULE, | |
401 | .pm = LPC32XX_TS_PM_OPS, | |
5cb727a8 | 402 | .of_match_table = of_match_ptr(lpc32xx_tsc_of_match), |
3045a5f5 KW |
403 | }, |
404 | }; | |
cdcc96e2 | 405 | module_platform_driver(lpc32xx_ts_driver); |
3045a5f5 KW |
406 | |
407 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com"); | |
408 | MODULE_DESCRIPTION("LPC32XX TSC Driver"); | |
409 | MODULE_LICENSE("GPL"); | |
410 | MODULE_ALIAS("platform:lpc32xx_ts"); |