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Commit | Line | Data |
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ab493a0f OBC |
1 | # IOMMU_API always gets selected by whoever wants it. |
2 | config IOMMU_API | |
3 | bool | |
b10f127e | 4 | |
68255b62 JR |
5 | menuconfig IOMMU_SUPPORT |
6 | bool "IOMMU Hardware Support" | |
7 | default y | |
8 | ---help--- | |
9 | Say Y here if you want to compile device drivers for IO Memory | |
10 | Management Units into the kernel. These devices usually allow to | |
11 | remap DMA requests and/or remap interrupts from other devices on the | |
12 | system. | |
13 | ||
14 | if IOMMU_SUPPORT | |
15 | ||
4e0ee78f HD |
16 | config OF_IOMMU |
17 | def_bool y | |
18 | depends on OF | |
19 | ||
695093e3 VS |
20 | config FSL_PAMU |
21 | bool "Freescale IOMMU support" | |
22 | depends on PPC_E500MC | |
23 | select IOMMU_API | |
24 | select GENERIC_ALLOCATOR | |
25 | help | |
26 | Freescale PAMU support. PAMU is the IOMMU present on Freescale QorIQ platforms. | |
27 | PAMU can authorize memory access, remap the memory address, and remap I/O | |
28 | transaction types. | |
29 | ||
b10f127e OBC |
30 | # MSM IOMMU support |
31 | config MSM_IOMMU | |
32 | bool "MSM IOMMU Support" | |
33 | depends on ARCH_MSM8X60 || ARCH_MSM8960 | |
34 | select IOMMU_API | |
35 | help | |
36 | Support for the IOMMUs found on certain Qualcomm SOCs. | |
37 | These IOMMUs allow virtualization of the address space used by most | |
38 | cores within the multimedia subsystem. | |
39 | ||
40 | If unsure, say N here. | |
41 | ||
42 | config IOMMU_PGTABLES_L2 | |
43 | def_bool y | |
44 | depends on MSM_IOMMU && MMU && SMP && CPU_DCACHE_DISABLE=n | |
29b68415 OBC |
45 | |
46 | # AMD IOMMU support | |
47 | config AMD_IOMMU | |
48 | bool "AMD IOMMU support" | |
49 | select SWIOTLB | |
50 | select PCI_MSI | |
52815b75 JR |
51 | select PCI_ATS |
52 | select PCI_PRI | |
53 | select PCI_PASID | |
29b68415 | 54 | select IOMMU_API |
eb1eb7ae | 55 | depends on X86_64 && PCI && ACPI && X86_IO_APIC |
29b68415 OBC |
56 | ---help--- |
57 | With this option you can enable support for AMD IOMMU hardware in | |
58 | your system. An IOMMU is a hardware component which provides | |
59 | remapping of DMA memory accesses from devices. With an AMD IOMMU you | |
59bf8964 | 60 | can isolate the DMA memory of different devices and protect the |
29b68415 OBC |
61 | system from misbehaving device drivers or hardware. |
62 | ||
63 | You can find out if your system has an AMD IOMMU if you look into | |
64 | your BIOS for an option to enable it or if you have an IVRS ACPI | |
65 | table. | |
66 | ||
67 | config AMD_IOMMU_STATS | |
68 | bool "Export AMD IOMMU statistics to debugfs" | |
69 | depends on AMD_IOMMU | |
70 | select DEBUG_FS | |
71 | ---help--- | |
72 | This option enables code in the AMD IOMMU driver to collect various | |
73 | statistics about whats happening in the driver and exports that | |
74 | information to userspace via debugfs. | |
75 | If unsure, say N. | |
166e9278 | 76 | |
e3c495c7 | 77 | config AMD_IOMMU_V2 |
a446e219 KC |
78 | tristate "AMD IOMMU Version 2 driver" |
79 | depends on AMD_IOMMU && PROFILING | |
8736b2c3 | 80 | select MMU_NOTIFIER |
e3c495c7 JR |
81 | ---help--- |
82 | This option enables support for the AMD IOMMUv2 features of the IOMMU | |
83 | hardware. Select this option if you want to use devices that support | |
59bf8964 | 84 | the PCI PRI and PASID interface. |
e3c495c7 | 85 | |
166e9278 | 86 | # Intel IOMMU support |
d3f13810 SS |
87 | config DMAR_TABLE |
88 | bool | |
89 | ||
90 | config INTEL_IOMMU | |
91 | bool "Support for Intel IOMMU using DMA Remapping Devices" | |
166e9278 OBC |
92 | depends on PCI_MSI && ACPI && (X86 || IA64_GENERIC) |
93 | select IOMMU_API | |
d3f13810 | 94 | select DMAR_TABLE |
166e9278 OBC |
95 | help |
96 | DMA remapping (DMAR) devices support enables independent address | |
97 | translations for Direct Memory Access (DMA) from devices. | |
98 | These DMA remapping devices are reported via ACPI tables | |
99 | and include PCI device scope covered by these DMA | |
100 | remapping devices. | |
101 | ||
d3f13810 | 102 | config INTEL_IOMMU_DEFAULT_ON |
166e9278 | 103 | def_bool y |
d3f13810 SS |
104 | prompt "Enable Intel DMA Remapping Devices by default" |
105 | depends on INTEL_IOMMU | |
166e9278 OBC |
106 | help |
107 | Selecting this option will enable a DMAR device at boot time if | |
108 | one is found. If this option is not selected, DMAR support can | |
109 | be enabled by passing intel_iommu=on to the kernel. | |
110 | ||
d3f13810 | 111 | config INTEL_IOMMU_BROKEN_GFX_WA |
166e9278 | 112 | bool "Workaround broken graphics drivers (going away soon)" |
d3f13810 | 113 | depends on INTEL_IOMMU && BROKEN && X86 |
166e9278 OBC |
114 | ---help--- |
115 | Current Graphics drivers tend to use physical address | |
116 | for DMA and avoid using DMA APIs. Setting this config | |
117 | option permits the IOMMU driver to set a unity map for | |
118 | all the OS-visible memory. Hence the driver can continue | |
119 | to use physical addresses for DMA, at least until this | |
120 | option is removed in the 2.6.32 kernel. | |
121 | ||
d3f13810 | 122 | config INTEL_IOMMU_FLOPPY_WA |
166e9278 | 123 | def_bool y |
d3f13810 | 124 | depends on INTEL_IOMMU && X86 |
166e9278 OBC |
125 | ---help--- |
126 | Floppy disk drivers are known to bypass DMA API calls | |
127 | thereby failing to work when IOMMU is enabled. This | |
128 | workaround will setup a 1:1 mapping for the first | |
129 | 16MiB to make floppy (an ISA device) work. | |
130 | ||
d3f13810 | 131 | config IRQ_REMAP |
a446e219 KC |
132 | bool "Support for Interrupt Remapping" |
133 | depends on X86_64 && X86_IO_APIC && PCI_MSI && ACPI | |
d3f13810 | 134 | select DMAR_TABLE |
166e9278 OBC |
135 | ---help--- |
136 | Supports Interrupt remapping for IO-APIC and MSI devices. | |
137 | To use x2apic mode in the CPU's which support x2APIC enhancements or | |
138 | to support platforms with CPU's having > 8 bit APIC ID, say Y. | |
68255b62 | 139 | |
fcf3a6ef OBC |
140 | # OMAP IOMMU support |
141 | config OMAP_IOMMU | |
142 | bool "OMAP IOMMU Support" | |
ae191589 | 143 | depends on ARCH_OMAP2PLUS |
fcf3a6ef OBC |
144 | select IOMMU_API |
145 | ||
146 | config OMAP_IOVMM | |
7b6d45f1 JR |
147 | tristate "OMAP IO Virtual Memory Manager Support" |
148 | depends on OMAP_IOMMU | |
fcf3a6ef OBC |
149 | |
150 | config OMAP_IOMMU_DEBUG | |
151 | tristate "Export OMAP IOMMU/IOVMM internals in DebugFS" | |
152 | depends on OMAP_IOVMM && DEBUG_FS | |
153 | help | |
154 | Select this to see extensive information about | |
155 | the internal state of OMAP IOMMU/IOVMM in debugfs. | |
156 | ||
157 | Say N unless you know you need this. | |
158 | ||
d53e54b4 HD |
159 | config TEGRA_IOMMU_GART |
160 | bool "Tegra GART IOMMU Support" | |
161 | depends on ARCH_TEGRA_2x_SOC | |
162 | select IOMMU_API | |
163 | help | |
164 | Enables support for remapping discontiguous physical memory | |
165 | shared with the operating system into contiguous I/O virtual | |
166 | space through the GART (Graphics Address Relocation Table) | |
167 | hardware included on Tegra SoCs. | |
168 | ||
7a31f6f4 HD |
169 | config TEGRA_IOMMU_SMMU |
170 | bool "Tegra SMMU IOMMU Support" | |
d300356c | 171 | depends on ARCH_TEGRA && TEGRA_AHB |
7a31f6f4 HD |
172 | select IOMMU_API |
173 | help | |
174 | Enables support for remapping discontiguous physical memory | |
175 | shared with the operating system into contiguous I/O virtual | |
176 | space through the SMMU (System Memory Management Unit) | |
177 | hardware included on Tegra SoCs. | |
178 | ||
2a96536e KC |
179 | config EXYNOS_IOMMU |
180 | bool "Exynos IOMMU Support" | |
181 | depends on ARCH_EXYNOS && EXYNOS_DEV_SYSMMU | |
182 | select IOMMU_API | |
183 | help | |
184 | Support for the IOMMU(System MMU) of Samsung Exynos application | |
185 | processor family. This enables H/W multimedia accellerators to see | |
186 | non-linear physical memory chunks as a linear memory in their | |
187 | address spaces | |
188 | ||
189 | If unsure, say N here. | |
190 | ||
191 | config EXYNOS_IOMMU_DEBUG | |
192 | bool "Debugging log for Exynos IOMMU" | |
193 | depends on EXYNOS_IOMMU | |
194 | help | |
195 | Select this to see the detailed log message that shows what | |
196 | happens in the IOMMU driver | |
197 | ||
198 | Say N unless you need kernel log message for IOMMU debugging | |
199 | ||
c2c460f7 HE |
200 | config SHMOBILE_IPMMU |
201 | bool | |
202 | ||
203 | config SHMOBILE_IPMMU_TLB | |
204 | bool | |
205 | ||
206 | config SHMOBILE_IOMMU | |
207 | bool "IOMMU for Renesas IPMMU/IPMMUI" | |
208 | default n | |
209 | depends on (ARM && ARCH_SHMOBILE) | |
210 | select IOMMU_API | |
211 | select ARM_DMA_USE_IOMMU | |
212 | select SHMOBILE_IPMMU | |
213 | select SHMOBILE_IPMMU_TLB | |
214 | help | |
215 | Support for Renesas IPMMU/IPMMUI. This option enables | |
216 | remapping of DMA memory accesses from all of the IP blocks | |
217 | on the ICB. | |
218 | ||
219 | Warning: Drivers (including userspace drivers of UIO | |
220 | devices) of the IP blocks on the ICB *must* use addresses | |
221 | allocated from the IPMMU (iova) for DMA with this option | |
222 | enabled. | |
223 | ||
224 | If unsure, say N. | |
225 | ||
226 | choice | |
227 | prompt "IPMMU/IPMMUI address space size" | |
228 | default SHMOBILE_IOMMU_ADDRSIZE_2048MB | |
229 | depends on SHMOBILE_IOMMU | |
230 | help | |
231 | This option sets IPMMU/IPMMUI address space size by | |
232 | adjusting the 1st level page table size. The page table size | |
233 | is calculated as follows: | |
234 | ||
235 | page table size = number of page table entries * 4 bytes | |
236 | number of page table entries = address space size / 1 MiB | |
237 | ||
238 | For example, when the address space size is 2048 MiB, the | |
239 | 1st level page table size is 8192 bytes. | |
240 | ||
241 | config SHMOBILE_IOMMU_ADDRSIZE_2048MB | |
242 | bool "2 GiB" | |
243 | ||
244 | config SHMOBILE_IOMMU_ADDRSIZE_1024MB | |
245 | bool "1 GiB" | |
246 | ||
247 | config SHMOBILE_IOMMU_ADDRSIZE_512MB | |
248 | bool "512 MiB" | |
249 | ||
250 | config SHMOBILE_IOMMU_ADDRSIZE_256MB | |
251 | bool "256 MiB" | |
252 | ||
253 | config SHMOBILE_IOMMU_ADDRSIZE_128MB | |
254 | bool "128 MiB" | |
255 | ||
256 | config SHMOBILE_IOMMU_ADDRSIZE_64MB | |
257 | bool "64 MiB" | |
258 | ||
259 | config SHMOBILE_IOMMU_ADDRSIZE_32MB | |
260 | bool "32 MiB" | |
261 | ||
262 | endchoice | |
263 | ||
264 | config SHMOBILE_IOMMU_L1SIZE | |
265 | int | |
266 | default 8192 if SHMOBILE_IOMMU_ADDRSIZE_2048MB | |
267 | default 4096 if SHMOBILE_IOMMU_ADDRSIZE_1024MB | |
268 | default 2048 if SHMOBILE_IOMMU_ADDRSIZE_512MB | |
269 | default 1024 if SHMOBILE_IOMMU_ADDRSIZE_256MB | |
270 | default 512 if SHMOBILE_IOMMU_ADDRSIZE_128MB | |
271 | default 256 if SHMOBILE_IOMMU_ADDRSIZE_64MB | |
272 | default 128 if SHMOBILE_IOMMU_ADDRSIZE_32MB | |
273 | ||
4e13c1ac AK |
274 | config SPAPR_TCE_IOMMU |
275 | bool "sPAPR TCE IOMMU Support" | |
5b25199e | 276 | depends on PPC_POWERNV || PPC_PSERIES |
4e13c1ac AK |
277 | select IOMMU_API |
278 | help | |
279 | Enables bits of IOMMU API required by VFIO. The iommu_ops | |
280 | is not implemented as it is not necessary for VFIO. | |
281 | ||
45ae7cff WD |
282 | config ARM_SMMU |
283 | bool "ARM Ltd. System MMU (SMMU) Support" | |
284 | depends on ARM64 || (ARM_LPAE && OF) | |
285 | select IOMMU_API | |
286 | select ARM_DMA_USE_IOMMU if ARM | |
287 | help | |
288 | Support for implementations of the ARM System MMU architecture | |
289 | versions 1 and 2. The driver supports both v7l and v8l table | |
290 | formats with 4k and 64k page sizes. | |
291 | ||
292 | Say Y here if your SoC includes an IOMMU device implementing | |
293 | the ARM SMMU architecture. | |
294 | ||
68255b62 | 295 | endif # IOMMU_SUPPORT |