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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
b6c02715 | 2 | /* |
5d0d7156 | 3 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 4 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 | 5 | * Leo Duran <leo.duran@amd.com> |
b6c02715 JR |
6 | */ |
7 | ||
101fa037 | 8 | #define pr_fmt(fmt) "AMD-Vi: " fmt |
5f226da1 | 9 | #define dev_fmt(fmt) pr_fmt(fmt) |
101fa037 | 10 | |
72e1dcc4 | 11 | #include <linux/ratelimit.h> |
b6c02715 | 12 | #include <linux/pci.h> |
2bf9a0a1 | 13 | #include <linux/acpi.h> |
9a4d3bf5 | 14 | #include <linux/amba/bus.h> |
0076cd3d | 15 | #include <linux/platform_device.h> |
cb41ed85 | 16 | #include <linux/pci-ats.h> |
a66022c4 | 17 | #include <linux/bitmap.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
7f26508b | 19 | #include <linux/debugfs.h> |
b6c02715 | 20 | #include <linux/scatterlist.h> |
51491367 | 21 | #include <linux/dma-mapping.h> |
fec777c3 | 22 | #include <linux/dma-direct.h> |
be62dbf5 | 23 | #include <linux/dma-iommu.h> |
b6c02715 | 24 | #include <linux/iommu-helper.h> |
815b33fd | 25 | #include <linux/delay.h> |
403f81d8 | 26 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
27 | #include <linux/notifier.h> |
28 | #include <linux/export.h> | |
2b324506 JR |
29 | #include <linux/irq.h> |
30 | #include <linux/msi.h> | |
3b839a57 | 31 | #include <linux/dma-contiguous.h> |
7c71d306 | 32 | #include <linux/irqdomain.h> |
5f6bed50 | 33 | #include <linux/percpu.h> |
307d5851 | 34 | #include <linux/iova.h> |
2b324506 JR |
35 | #include <asm/irq_remapping.h> |
36 | #include <asm/io_apic.h> | |
37 | #include <asm/apic.h> | |
38 | #include <asm/hw_irq.h> | |
17f5b569 | 39 | #include <asm/msidef.h> |
b6c02715 | 40 | #include <asm/proto.h> |
46a7fa27 | 41 | #include <asm/iommu.h> |
1d9b16d1 | 42 | #include <asm/gart.h> |
27c2127a | 43 | #include <asm/dma.h> |
403f81d8 | 44 | |
786dfe49 | 45 | #include "amd_iommu.h" |
ad8694ba | 46 | #include "../irq_remapping.h" |
b6c02715 JR |
47 | |
48 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
49 | ||
815b33fd | 50 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 51 | |
307d5851 JR |
52 | /* IO virtual address start page frame number */ |
53 | #define IOVA_START_PFN (1) | |
54 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 55 | |
81cd07b9 JR |
56 | /* Reserved IOVA ranges */ |
57 | #define MSI_RANGE_START (0xfee00000) | |
58 | #define MSI_RANGE_END (0xfeefffff) | |
59 | #define HT_RANGE_START (0xfd00000000ULL) | |
60 | #define HT_RANGE_END (0xffffffffffULL) | |
61 | ||
aa3de9c0 OBC |
62 | /* |
63 | * This bitmap is used to advertise the page sizes our hardware support | |
64 | * to the IOMMU core, which will then use this information to split | |
65 | * physically contiguous memory regions it is mapping into page sizes | |
66 | * that we support. | |
67 | * | |
954e3dd8 | 68 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 69 | */ |
954e3dd8 | 70 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 71 | |
a71730e2 JR |
72 | #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL |
73 | ||
2bc00180 | 74 | static DEFINE_SPINLOCK(pd_bitmap_lock); |
b6c02715 | 75 | |
8fa5f802 | 76 | /* List of all available dev_data structures */ |
779da732 | 77 | static LLIST_HEAD(dev_data_list); |
8fa5f802 | 78 | |
6efed63b JR |
79 | LIST_HEAD(ioapic_map); |
80 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 81 | LIST_HEAD(acpihid_map); |
6efed63b | 82 | |
0feae533 JR |
83 | /* |
84 | * Domain for untranslated devices - only allocated | |
85 | * if iommu=pt passed on kernel cmd line. | |
86 | */ | |
b0119e87 | 87 | const struct iommu_ops amd_iommu_ops; |
26961efe | 88 | |
72e1dcc4 | 89 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 90 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 91 | |
431b2a20 JR |
92 | /* |
93 | * general struct to manage commands send to an IOMMU | |
94 | */ | |
d6449536 | 95 | struct iommu_cmd { |
b6c02715 JR |
96 | u32 data[4]; |
97 | }; | |
98 | ||
05152a04 JR |
99 | struct kmem_cache *amd_iommu_irq_cache; |
100 | ||
04bfdd84 | 101 | static void update_domain(struct protection_domain *domain); |
b6809ee5 | 102 | static void detach_device(struct device *dev); |
19c6978f JR |
103 | static void update_and_flush_device_table(struct protection_domain *domain, |
104 | struct domain_pgtable *pgtable); | |
81cd07b9 | 105 | |
15898bbc JR |
106 | /**************************************************************************** |
107 | * | |
108 | * Helper functions | |
109 | * | |
110 | ****************************************************************************/ | |
111 | ||
2bf9a0a1 | 112 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
113 | { |
114 | struct pci_dev *pdev = to_pci_dev(dev); | |
115 | ||
775c068c | 116 | return pci_dev_id(pdev); |
e3156048 JR |
117 | } |
118 | ||
2bf9a0a1 WZ |
119 | static inline int get_acpihid_device_id(struct device *dev, |
120 | struct acpihid_map_entry **entry) | |
121 | { | |
ae5e6c64 | 122 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2bf9a0a1 WZ |
123 | struct acpihid_map_entry *p; |
124 | ||
ae5e6c64 AS |
125 | if (!adev) |
126 | return -ENODEV; | |
127 | ||
2bf9a0a1 | 128 | list_for_each_entry(p, &acpihid_map, list) { |
ea90228c RR |
129 | if (acpi_dev_hid_uid_match(adev, p->hid, |
130 | p->uid[0] ? p->uid : NULL)) { | |
2bf9a0a1 WZ |
131 | if (entry) |
132 | *entry = p; | |
133 | return p->devid; | |
134 | } | |
135 | } | |
136 | return -EINVAL; | |
137 | } | |
138 | ||
139 | static inline int get_device_id(struct device *dev) | |
140 | { | |
141 | int devid; | |
142 | ||
143 | if (dev_is_pci(dev)) | |
144 | devid = get_pci_device_id(dev); | |
145 | else | |
146 | devid = get_acpihid_device_id(dev, NULL); | |
147 | ||
148 | return devid; | |
149 | } | |
150 | ||
3f4b87b9 JR |
151 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
152 | { | |
153 | return container_of(dom, struct protection_domain, domain); | |
154 | } | |
155 | ||
eb791aa7 JR |
156 | static void amd_iommu_domain_get_pgtable(struct protection_domain *domain, |
157 | struct domain_pgtable *pgtable) | |
158 | { | |
159 | u64 pt_root = atomic64_read(&domain->pt_root); | |
160 | ||
161 | pgtable->root = (u64 *)(pt_root & PAGE_MASK); | |
162 | pgtable->mode = pt_root & 7; /* lowest 3 bits encode pgtable mode */ | |
163 | } | |
164 | ||
70fcd359 JR |
165 | static void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root) |
166 | { | |
167 | atomic64_set(&domain->pt_root, root); | |
168 | } | |
169 | ||
170 | static void amd_iommu_domain_clr_pt_root(struct protection_domain *domain) | |
171 | { | |
172 | amd_iommu_domain_set_pt_root(domain, 0); | |
173 | } | |
174 | ||
175 | static void amd_iommu_domain_set_pgtable(struct protection_domain *domain, | |
176 | u64 *root, int mode) | |
eb791aa7 JR |
177 | { |
178 | u64 pt_root; | |
179 | ||
180 | /* lowest 3 bits encode pgtable mode */ | |
181 | pt_root = mode & 7; | |
182 | pt_root |= (u64)root; | |
183 | ||
70fcd359 | 184 | amd_iommu_domain_set_pt_root(domain, pt_root); |
eb791aa7 JR |
185 | } |
186 | ||
f62dda66 | 187 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
188 | { |
189 | struct iommu_dev_data *dev_data; | |
8fa5f802 JR |
190 | |
191 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
192 | if (!dev_data) | |
193 | return NULL; | |
194 | ||
ab7b2577 | 195 | spin_lock_init(&dev_data->lock); |
f62dda66 | 196 | dev_data->devid = devid; |
30bf2df6 JR |
197 | ratelimit_default_init(&dev_data->rs); |
198 | ||
779da732 | 199 | llist_add(&dev_data->dev_data_list, &dev_data_list); |
8fa5f802 JR |
200 | return dev_data; |
201 | } | |
202 | ||
3b03bb74 JR |
203 | static struct iommu_dev_data *search_dev_data(u16 devid) |
204 | { | |
205 | struct iommu_dev_data *dev_data; | |
779da732 | 206 | struct llist_node *node; |
3b03bb74 | 207 | |
779da732 SAS |
208 | if (llist_empty(&dev_data_list)) |
209 | return NULL; | |
3b03bb74 | 210 | |
779da732 SAS |
211 | node = dev_data_list.first; |
212 | llist_for_each_entry(dev_data, node, dev_data_list) { | |
3b03bb74 | 213 | if (dev_data->devid == devid) |
779da732 | 214 | return dev_data; |
3b03bb74 JR |
215 | } |
216 | ||
779da732 | 217 | return NULL; |
3b03bb74 JR |
218 | } |
219 | ||
3332364e | 220 | static int clone_alias(struct pci_dev *pdev, u16 alias, void *data) |
e3156048 | 221 | { |
3332364e | 222 | u16 devid = pci_dev_id(pdev); |
5ebb1bc2 | 223 | |
3332364e LG |
224 | if (devid == alias) |
225 | return 0; | |
5ebb1bc2 | 226 | |
3332364e LG |
227 | amd_iommu_rlookup_table[alias] = |
228 | amd_iommu_rlookup_table[devid]; | |
229 | memcpy(amd_iommu_dev_table[alias].data, | |
230 | amd_iommu_dev_table[devid].data, | |
231 | sizeof(amd_iommu_dev_table[alias].data)); | |
5ebb1bc2 | 232 | |
3332364e LG |
233 | return 0; |
234 | } | |
e3156048 | 235 | |
3332364e LG |
236 | static void clone_aliases(struct pci_dev *pdev) |
237 | { | |
238 | if (!pdev) | |
239 | return; | |
e3156048 JR |
240 | |
241 | /* | |
3332364e LG |
242 | * The IVRS alias stored in the alias table may not be |
243 | * part of the PCI DMA aliases if it's bus differs | |
244 | * from the original device. | |
e3156048 | 245 | */ |
3332364e | 246 | clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL); |
e3156048 | 247 | |
3332364e LG |
248 | pci_for_each_dma_alias(pdev, clone_alias, NULL); |
249 | } | |
e3156048 | 250 | |
3332364e LG |
251 | static struct pci_dev *setup_aliases(struct device *dev) |
252 | { | |
253 | struct pci_dev *pdev = to_pci_dev(dev); | |
254 | u16 ivrs_alias; | |
255 | ||
256 | /* For ACPI HID devices, there are no aliases */ | |
257 | if (!dev_is_pci(dev)) | |
258 | return NULL; | |
e3156048 JR |
259 | |
260 | /* | |
3332364e LG |
261 | * Add the IVRS alias to the pci aliases if it is on the same |
262 | * bus. The IVRS table may know about a quirk that we don't. | |
e3156048 | 263 | */ |
3332364e LG |
264 | ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)]; |
265 | if (ivrs_alias != pci_dev_id(pdev) && | |
09298542 JS |
266 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) |
267 | pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1); | |
e3156048 | 268 | |
3332364e LG |
269 | clone_aliases(pdev); |
270 | ||
271 | return pdev; | |
e3156048 JR |
272 | } |
273 | ||
3b03bb74 JR |
274 | static struct iommu_dev_data *find_dev_data(u16 devid) |
275 | { | |
276 | struct iommu_dev_data *dev_data; | |
df3f7a6e | 277 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3b03bb74 JR |
278 | |
279 | dev_data = search_dev_data(devid); | |
280 | ||
df3f7a6e | 281 | if (dev_data == NULL) { |
3b03bb74 | 282 | dev_data = alloc_dev_data(devid); |
39ffe395 SAS |
283 | if (!dev_data) |
284 | return NULL; | |
3b03bb74 | 285 | |
df3f7a6e BH |
286 | if (translation_pre_enabled(iommu)) |
287 | dev_data->defer_attach = true; | |
288 | } | |
289 | ||
3b03bb74 JR |
290 | return dev_data; |
291 | } | |
292 | ||
b097d11a WZ |
293 | /* |
294 | * Find or create an IOMMU group for a acpihid device. | |
295 | */ | |
296 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 297 | { |
b097d11a | 298 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 299 | int devid; |
b097d11a WZ |
300 | |
301 | devid = get_acpihid_device_id(dev, &entry); | |
302 | if (devid < 0) | |
303 | return ERR_PTR(devid); | |
304 | ||
305 | list_for_each_entry(p, &acpihid_map, list) { | |
306 | if ((devid == p->devid) && p->group) | |
307 | entry->group = p->group; | |
308 | } | |
309 | ||
310 | if (!entry->group) | |
311 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
312 | else |
313 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
314 | |
315 | return entry->group; | |
657cbb6b JR |
316 | } |
317 | ||
5abcdba4 JR |
318 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
319 | { | |
320 | static const int caps[] = { | |
46277b75 JR |
321 | PCI_EXT_CAP_ID_PRI, |
322 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
323 | }; |
324 | int i, pos; | |
325 | ||
7a441b21 | 326 | if (!pci_ats_supported(pdev)) |
cef74409 GK |
327 | return false; |
328 | ||
7a441b21 | 329 | for (i = 0; i < 2; ++i) { |
5abcdba4 JR |
330 | pos = pci_find_ext_capability(pdev, caps[i]); |
331 | if (pos == 0) | |
332 | return false; | |
333 | } | |
334 | ||
335 | return true; | |
336 | } | |
337 | ||
6a113ddc JR |
338 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
339 | { | |
340 | struct iommu_dev_data *dev_data; | |
341 | ||
05a0542b | 342 | dev_data = dev_iommu_priv_get(&pdev->dev); |
6a113ddc JR |
343 | |
344 | return dev_data->errata & (1 << erratum) ? true : false; | |
345 | } | |
346 | ||
98fc5a69 JR |
347 | /* |
348 | * This function checks if the driver got a valid device from the caller to | |
349 | * avoid dereferencing invalid pointers. | |
350 | */ | |
351 | static bool check_device(struct device *dev) | |
352 | { | |
7aba6cb9 | 353 | int devid; |
98fc5a69 | 354 | |
c0da9b9f | 355 | if (!dev) |
98fc5a69 JR |
356 | return false; |
357 | ||
98fc5a69 | 358 | devid = get_device_id(dev); |
9ee35e4c | 359 | if (devid < 0) |
7aba6cb9 | 360 | return false; |
98fc5a69 JR |
361 | |
362 | /* Out of our scope? */ | |
363 | if (devid > amd_iommu_last_bdf) | |
364 | return false; | |
365 | ||
366 | if (amd_iommu_rlookup_table[devid] == NULL) | |
367 | return false; | |
368 | ||
369 | return true; | |
370 | } | |
371 | ||
eb9c9527 AW |
372 | static int iommu_init_device(struct device *dev) |
373 | { | |
eb9c9527 | 374 | struct iommu_dev_data *dev_data; |
7aba6cb9 | 375 | int devid; |
eb9c9527 | 376 | |
05a0542b | 377 | if (dev_iommu_priv_get(dev)) |
eb9c9527 AW |
378 | return 0; |
379 | ||
7aba6cb9 | 380 | devid = get_device_id(dev); |
9ee35e4c | 381 | if (devid < 0) |
7aba6cb9 WZ |
382 | return devid; |
383 | ||
384 | dev_data = find_dev_data(devid); | |
eb9c9527 AW |
385 | if (!dev_data) |
386 | return -ENOMEM; | |
387 | ||
3332364e | 388 | dev_data->pdev = setup_aliases(dev); |
e3156048 | 389 | |
c12b08eb YZ |
390 | /* |
391 | * By default we use passthrough mode for IOMMUv2 capable device. | |
392 | * But if amd_iommu=force_isolation is set (e.g. to debug DMA to | |
393 | * invalid address), we ignore the capability for the device so | |
394 | * it'll be forced to go into translation mode. | |
395 | */ | |
cc7c8ad9 | 396 | if ((iommu_default_passthrough() || !amd_iommu_force_isolation) && |
c12b08eb | 397 | dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
398 | struct amd_iommu *iommu; |
399 | ||
2bf9a0a1 | 400 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
401 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
402 | } | |
403 | ||
05a0542b | 404 | dev_iommu_priv_set(dev, dev_data); |
066f2e98 | 405 | |
657cbb6b JR |
406 | return 0; |
407 | } | |
408 | ||
26018874 JR |
409 | static void iommu_ignore_device(struct device *dev) |
410 | { | |
7aba6cb9 | 411 | int devid; |
26018874 JR |
412 | |
413 | devid = get_device_id(dev); | |
9ee35e4c | 414 | if (devid < 0) |
7aba6cb9 WZ |
415 | return; |
416 | ||
3332364e | 417 | amd_iommu_rlookup_table[devid] = NULL; |
26018874 | 418 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); |
26018874 | 419 | |
3332364e | 420 | setup_aliases(dev); |
26018874 JR |
421 | } |
422 | ||
dce8d696 | 423 | static void amd_iommu_uninit_device(struct device *dev) |
657cbb6b | 424 | { |
7aba6cb9 | 425 | struct iommu_dev_data *dev_data; |
c1931090 | 426 | |
736c3333 | 427 | dev_data = dev_iommu_priv_get(dev); |
c1931090 AW |
428 | if (!dev_data) |
429 | return; | |
430 | ||
b6809ee5 JR |
431 | if (dev_data->domain) |
432 | detach_device(dev); | |
433 | ||
05a0542b | 434 | dev_iommu_priv_set(dev, NULL); |
aafd8ba0 | 435 | |
8fa5f802 | 436 | /* |
c1931090 AW |
437 | * We keep dev_data around for unplugged devices and reuse it when the |
438 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 439 | */ |
657cbb6b | 440 | } |
b7cc9554 | 441 | |
7f1f1683 AD |
442 | /* |
443 | * Helper function to get the first pte of a large mapping | |
444 | */ | |
445 | static u64 *first_pte_l7(u64 *pte, unsigned long *page_size, | |
446 | unsigned long *count) | |
447 | { | |
448 | unsigned long pte_mask, pg_size, cnt; | |
449 | u64 *fpte; | |
450 | ||
451 | pg_size = PTE_PAGE_SIZE(*pte); | |
452 | cnt = PAGE_SIZE_PTE_COUNT(pg_size); | |
453 | pte_mask = ~((cnt << 3) - 1); | |
454 | fpte = (u64 *)(((unsigned long)pte) & pte_mask); | |
455 | ||
456 | if (page_size) | |
457 | *page_size = pg_size; | |
458 | ||
459 | if (count) | |
460 | *count = cnt; | |
461 | ||
462 | return fpte; | |
463 | } | |
464 | ||
a80dc3e0 JR |
465 | /**************************************************************************** |
466 | * | |
467 | * Interrupt handling functions | |
468 | * | |
469 | ****************************************************************************/ | |
470 | ||
e3e59876 JR |
471 | static void dump_dte_entry(u16 devid) |
472 | { | |
473 | int i; | |
474 | ||
ee6c2868 | 475 | for (i = 0; i < 4; ++i) |
101fa037 | 476 | pr_err("DTE[%d]: %016llx\n", i, |
e3e59876 JR |
477 | amd_iommu_dev_table[devid].data[i]); |
478 | } | |
479 | ||
945b4ac4 JR |
480 | static void dump_command(unsigned long phys_addr) |
481 | { | |
2543a786 | 482 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
483 | int i; |
484 | ||
485 | for (i = 0; i < 4; ++i) | |
101fa037 | 486 | pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); |
945b4ac4 JR |
487 | } |
488 | ||
30bf2df6 JR |
489 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
490 | u64 address, int flags) | |
491 | { | |
492 | struct iommu_dev_data *dev_data = NULL; | |
493 | struct pci_dev *pdev; | |
494 | ||
d5bf0f4f SK |
495 | pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid), |
496 | devid & 0xff); | |
30bf2df6 | 497 | if (pdev) |
05a0542b | 498 | dev_data = dev_iommu_priv_get(&pdev->dev); |
30bf2df6 JR |
499 | |
500 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
5f226da1 | 501 | pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
502 | domain_id, address, flags); |
503 | } else if (printk_ratelimit()) { | |
6f5086a6 | 504 | pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
505 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
506 | domain_id, address, flags); | |
507 | } | |
508 | ||
509 | if (pdev) | |
510 | pci_dev_put(pdev); | |
511 | } | |
512 | ||
a345b23b | 513 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 514 | { |
90ca3859 | 515 | struct device *dev = iommu->iommu.dev; |
e7f63ffc | 516 | int type, devid, pasid, flags, tag; |
3d06fca8 JR |
517 | volatile u32 *event = __evt; |
518 | int count = 0; | |
519 | u64 address; | |
520 | ||
521 | retry: | |
522 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
523 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
ec21f17a SS |
524 | pasid = (event[0] & EVENT_DOMID_MASK_HI) | |
525 | (event[1] & EVENT_DOMID_MASK_LO); | |
3d06fca8 JR |
526 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; |
527 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
528 | ||
529 | if (type == 0) { | |
530 | /* Did we hit the erratum? */ | |
531 | if (++count == LOOP_TIMEOUT) { | |
101fa037 | 532 | pr_err("No event written to event log\n"); |
3d06fca8 JR |
533 | return; |
534 | } | |
535 | udelay(1); | |
536 | goto retry; | |
537 | } | |
90008ee4 | 538 | |
30bf2df6 | 539 | if (type == EVENT_TYPE_IO_FAULT) { |
d64c0486 | 540 | amd_iommu_report_page_fault(devid, pasid, address, flags); |
30bf2df6 | 541 | return; |
30bf2df6 | 542 | } |
90008ee4 JR |
543 | |
544 | switch (type) { | |
545 | case EVENT_TYPE_ILL_DEV: | |
6f5086a6 | 546 | dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 547 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 548 | pasid, address, flags); |
e3e59876 | 549 | dump_dte_entry(devid); |
90008ee4 | 550 | break; |
90008ee4 | 551 | case EVENT_TYPE_DEV_TAB_ERR: |
1a21ee1a | 552 | dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " |
6f5086a6 | 553 | "address=0x%llx flags=0x%04x]\n", |
90ca3859 GH |
554 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
555 | address, flags); | |
90008ee4 JR |
556 | break; |
557 | case EVENT_TYPE_PAGE_TAB_ERR: | |
ec21f17a | 558 | dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 559 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 560 | pasid, address, flags); |
90008ee4 JR |
561 | break; |
562 | case EVENT_TYPE_ILL_CMD: | |
6f5086a6 | 563 | dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); |
945b4ac4 | 564 | dump_command(address); |
90008ee4 JR |
565 | break; |
566 | case EVENT_TYPE_CMD_HARD_ERR: | |
6f5086a6 | 567 | dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", |
d64c0486 | 568 | address, flags); |
90008ee4 JR |
569 | break; |
570 | case EVENT_TYPE_IOTLB_INV_TO: | |
6f5086a6 | 571 | dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n", |
90ca3859 GH |
572 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
573 | address); | |
90008ee4 JR |
574 | break; |
575 | case EVENT_TYPE_INV_DEV_REQ: | |
6f5086a6 | 576 | dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 577 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 578 | pasid, address, flags); |
90008ee4 | 579 | break; |
e7f63ffc | 580 | case EVENT_TYPE_INV_PPR_REQ: |
470eb3b3 | 581 | pasid = PPR_PASID(*((u64 *)__evt)); |
e7f63ffc | 582 | tag = event[1] & 0x03FF; |
c1ddcf1c | 583 | dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n", |
e7f63ffc | 584 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
c1ddcf1c | 585 | pasid, address, flags, tag); |
90008ee4 JR |
586 | break; |
587 | default: | |
1a21ee1a | 588 | dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", |
90ca3859 | 589 | event[0], event[1], event[2], event[3]); |
90008ee4 | 590 | } |
3d06fca8 JR |
591 | |
592 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
593 | } |
594 | ||
595 | static void iommu_poll_events(struct amd_iommu *iommu) | |
596 | { | |
597 | u32 head, tail; | |
90008ee4 JR |
598 | |
599 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
600 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
601 | ||
602 | while (head != tail) { | |
a345b23b | 603 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 604 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
605 | } |
606 | ||
607 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
608 | } |
609 | ||
eee53537 | 610 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
611 | { |
612 | struct amd_iommu_fault fault; | |
72e1dcc4 | 613 | |
72e1dcc4 | 614 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
101fa037 | 615 | pr_err_ratelimited("Unknown PPR request received\n"); |
72e1dcc4 JR |
616 | return; |
617 | } | |
618 | ||
619 | fault.address = raw[1]; | |
620 | fault.pasid = PPR_PASID(raw[0]); | |
621 | fault.device_id = PPR_DEVID(raw[0]); | |
622 | fault.tag = PPR_TAG(raw[0]); | |
623 | fault.flags = PPR_FLAGS(raw[0]); | |
624 | ||
72e1dcc4 JR |
625 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
626 | } | |
627 | ||
628 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
629 | { | |
72e1dcc4 JR |
630 | u32 head, tail; |
631 | ||
632 | if (iommu->ppr_log == NULL) | |
633 | return; | |
634 | ||
72e1dcc4 JR |
635 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
636 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
637 | ||
638 | while (head != tail) { | |
eee53537 JR |
639 | volatile u64 *raw; |
640 | u64 entry[2]; | |
641 | int i; | |
642 | ||
643 | raw = (u64 *)(iommu->ppr_log + head); | |
644 | ||
645 | /* | |
646 | * Hardware bug: Interrupt may arrive before the entry is | |
647 | * written to memory. If this happens we need to wait for the | |
648 | * entry to arrive. | |
649 | */ | |
650 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
651 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
652 | break; | |
653 | udelay(1); | |
654 | } | |
72e1dcc4 | 655 | |
eee53537 JR |
656 | /* Avoid memcpy function-call overhead */ |
657 | entry[0] = raw[0]; | |
658 | entry[1] = raw[1]; | |
72e1dcc4 | 659 | |
eee53537 JR |
660 | /* |
661 | * To detect the hardware bug we need to clear the entry | |
662 | * back to zero. | |
663 | */ | |
664 | raw[0] = raw[1] = 0UL; | |
665 | ||
666 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
667 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
668 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 669 | |
eee53537 JR |
670 | /* Handle PPR entry */ |
671 | iommu_handle_ppr_entry(iommu, entry); | |
672 | ||
eee53537 JR |
673 | /* Refresh ring-buffer information */ |
674 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
675 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
676 | } | |
72e1dcc4 JR |
677 | } |
678 | ||
bd6fcefc SS |
679 | #ifdef CONFIG_IRQ_REMAP |
680 | static int (*iommu_ga_log_notifier)(u32); | |
681 | ||
682 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
683 | { | |
684 | iommu_ga_log_notifier = notifier; | |
685 | ||
686 | return 0; | |
687 | } | |
688 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
689 | ||
690 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
691 | { | |
692 | u32 head, tail, cnt = 0; | |
693 | ||
694 | if (iommu->ga_log == NULL) | |
695 | return; | |
696 | ||
697 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
698 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
699 | ||
700 | while (head != tail) { | |
701 | volatile u64 *raw; | |
702 | u64 log_entry; | |
703 | ||
704 | raw = (u64 *)(iommu->ga_log + head); | |
705 | cnt++; | |
706 | ||
707 | /* Avoid memcpy function-call overhead */ | |
708 | log_entry = *raw; | |
709 | ||
710 | /* Update head pointer of hardware ring-buffer */ | |
711 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
712 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
713 | ||
714 | /* Handle GA entry */ | |
715 | switch (GA_REQ_TYPE(log_entry)) { | |
716 | case GA_GUEST_NR: | |
717 | if (!iommu_ga_log_notifier) | |
718 | break; | |
719 | ||
101fa037 | 720 | pr_debug("%s: devid=%#x, ga_tag=%#x\n", |
bd6fcefc SS |
721 | __func__, GA_DEVID(log_entry), |
722 | GA_TAG(log_entry)); | |
723 | ||
724 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
101fa037 | 725 | pr_err("GA log notifier failed.\n"); |
bd6fcefc SS |
726 | break; |
727 | default: | |
728 | break; | |
729 | } | |
730 | } | |
731 | } | |
732 | #endif /* CONFIG_IRQ_REMAP */ | |
733 | ||
734 | #define AMD_IOMMU_INT_MASK \ | |
735 | (MMIO_STATUS_EVT_INT_MASK | \ | |
736 | MMIO_STATUS_PPR_INT_MASK | \ | |
737 | MMIO_STATUS_GALOG_INT_MASK) | |
738 | ||
72fe00f0 | 739 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 740 | { |
3f398bc7 SS |
741 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
742 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 743 | |
bd6fcefc SS |
744 | while (status & AMD_IOMMU_INT_MASK) { |
745 | /* Enable EVT and PPR and GA interrupts again */ | |
746 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 747 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 748 | |
3f398bc7 | 749 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
101fa037 | 750 | pr_devel("Processing IOMMU Event Log\n"); |
3f398bc7 SS |
751 | iommu_poll_events(iommu); |
752 | } | |
90008ee4 | 753 | |
3f398bc7 | 754 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
101fa037 | 755 | pr_devel("Processing IOMMU PPR Log\n"); |
3f398bc7 SS |
756 | iommu_poll_ppr_log(iommu); |
757 | } | |
90008ee4 | 758 | |
bd6fcefc SS |
759 | #ifdef CONFIG_IRQ_REMAP |
760 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
101fa037 | 761 | pr_devel("Processing IOMMU GA Log\n"); |
bd6fcefc SS |
762 | iommu_poll_ga_log(iommu); |
763 | } | |
764 | #endif | |
765 | ||
3f398bc7 SS |
766 | /* |
767 | * Hardware bug: ERBT1312 | |
768 | * When re-enabling interrupt (by writing 1 | |
769 | * to clear the bit), the hardware might also try to set | |
770 | * the interrupt bit in the event status register. | |
771 | * In this scenario, the bit will be set, and disable | |
772 | * subsequent interrupts. | |
773 | * | |
774 | * Workaround: The IOMMU driver should read back the | |
775 | * status register and check if the interrupt bits are cleared. | |
776 | * If not, driver will need to go through the interrupt handler | |
777 | * again and re-clear the bits | |
778 | */ | |
779 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
780 | } | |
90008ee4 | 781 | return IRQ_HANDLED; |
a80dc3e0 JR |
782 | } |
783 | ||
72fe00f0 JR |
784 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
785 | { | |
786 | return IRQ_WAKE_THREAD; | |
787 | } | |
788 | ||
431b2a20 JR |
789 | /**************************************************************************** |
790 | * | |
791 | * IOMMU command queuing functions | |
792 | * | |
793 | ****************************************************************************/ | |
794 | ||
ac0ea6e9 JR |
795 | static int wait_on_sem(volatile u64 *sem) |
796 | { | |
797 | int i = 0; | |
798 | ||
799 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
800 | udelay(1); | |
801 | i += 1; | |
802 | } | |
803 | ||
804 | if (i == LOOP_TIMEOUT) { | |
101fa037 | 805 | pr_alert("Completion-Wait loop timed out\n"); |
ac0ea6e9 JR |
806 | return -EIO; |
807 | } | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
812 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 813 | struct iommu_cmd *cmd) |
a19ae1ec | 814 | { |
a19ae1ec | 815 | u8 *target; |
a5bbbf37 | 816 | u32 tail; |
ac0ea6e9 JR |
817 | |
818 | /* Copy command to buffer */ | |
a5bbbf37 DV |
819 | tail = iommu->cmd_buf_tail; |
820 | target = iommu->cmd_buf + tail; | |
ac0ea6e9 JR |
821 | memcpy(target, cmd, sizeof(*cmd)); |
822 | ||
a5bbbf37 DV |
823 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
824 | iommu->cmd_buf_tail = tail; | |
825 | ||
ac0ea6e9 | 826 | /* Tell the IOMMU about it */ |
a5bbbf37 | 827 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 828 | } |
a19ae1ec | 829 | |
815b33fd | 830 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 831 | { |
2543a786 TL |
832 | u64 paddr = iommu_virt_to_phys((void *)address); |
833 | ||
815b33fd JR |
834 | WARN_ON(address & 0x7ULL); |
835 | ||
ded46737 | 836 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
837 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
838 | cmd->data[1] = upper_32_bits(paddr); | |
815b33fd | 839 | cmd->data[2] = 1; |
ded46737 JR |
840 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
841 | } | |
842 | ||
94fe79e2 JR |
843 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
844 | { | |
845 | memset(cmd, 0, sizeof(*cmd)); | |
846 | cmd->data[0] = devid; | |
847 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
848 | } | |
849 | ||
11b6402c JR |
850 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
851 | size_t size, u16 domid, int pde) | |
852 | { | |
853 | u64 pages; | |
ae0cbbb1 | 854 | bool s; |
11b6402c JR |
855 | |
856 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 857 | s = false; |
11b6402c JR |
858 | |
859 | if (pages > 1) { | |
860 | /* | |
861 | * If we have to flush more than one page, flush all | |
862 | * TLB entries for this domain | |
863 | */ | |
864 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 865 | s = true; |
11b6402c JR |
866 | } |
867 | ||
868 | address &= PAGE_MASK; | |
869 | ||
870 | memset(cmd, 0, sizeof(*cmd)); | |
871 | cmd->data[1] |= domid; | |
872 | cmd->data[2] = lower_32_bits(address); | |
873 | cmd->data[3] = upper_32_bits(address); | |
874 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
875 | if (s) /* size bit - we flush more than one 4kb page */ | |
876 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 877 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
878 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
879 | } | |
880 | ||
cb41ed85 JR |
881 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
882 | u64 address, size_t size) | |
883 | { | |
884 | u64 pages; | |
ae0cbbb1 | 885 | bool s; |
cb41ed85 JR |
886 | |
887 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 888 | s = false; |
cb41ed85 JR |
889 | |
890 | if (pages > 1) { | |
891 | /* | |
892 | * If we have to flush more than one page, flush all | |
893 | * TLB entries for this domain | |
894 | */ | |
895 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 896 | s = true; |
cb41ed85 JR |
897 | } |
898 | ||
899 | address &= PAGE_MASK; | |
900 | ||
901 | memset(cmd, 0, sizeof(*cmd)); | |
902 | cmd->data[0] = devid; | |
903 | cmd->data[0] |= (qdep & 0xff) << 24; | |
904 | cmd->data[1] = devid; | |
905 | cmd->data[2] = lower_32_bits(address); | |
906 | cmd->data[3] = upper_32_bits(address); | |
907 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
908 | if (s) | |
909 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
910 | } | |
911 | ||
22e266c7 JR |
912 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
913 | u64 address, bool size) | |
914 | { | |
915 | memset(cmd, 0, sizeof(*cmd)); | |
916 | ||
917 | address &= ~(0xfffULL); | |
918 | ||
a919a018 | 919 | cmd->data[0] = pasid; |
22e266c7 JR |
920 | cmd->data[1] = domid; |
921 | cmd->data[2] = lower_32_bits(address); | |
922 | cmd->data[3] = upper_32_bits(address); | |
923 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
925 | if (size) | |
926 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
927 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
928 | } | |
929 | ||
930 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
931 | int qdep, u64 address, bool size) | |
932 | { | |
933 | memset(cmd, 0, sizeof(*cmd)); | |
934 | ||
935 | address &= ~(0xfffULL); | |
936 | ||
937 | cmd->data[0] = devid; | |
e8d2d82d | 938 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
939 | cmd->data[0] |= (qdep & 0xff) << 24; |
940 | cmd->data[1] = devid; | |
e8d2d82d | 941 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
942 | cmd->data[2] = lower_32_bits(address); |
943 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
944 | cmd->data[3] = upper_32_bits(address); | |
945 | if (size) | |
946 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
947 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
948 | } | |
949 | ||
c99afa25 JR |
950 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
951 | int status, int tag, bool gn) | |
952 | { | |
953 | memset(cmd, 0, sizeof(*cmd)); | |
954 | ||
955 | cmd->data[0] = devid; | |
956 | if (gn) { | |
a919a018 | 957 | cmd->data[1] = pasid; |
c99afa25 JR |
958 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
959 | } | |
960 | cmd->data[3] = tag & 0x1ff; | |
961 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
962 | ||
963 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
964 | } | |
965 | ||
58fc7f14 JR |
966 | static void build_inv_all(struct iommu_cmd *cmd) |
967 | { | |
968 | memset(cmd, 0, sizeof(*cmd)); | |
969 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
970 | } |
971 | ||
7ef2798d JR |
972 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
973 | { | |
974 | memset(cmd, 0, sizeof(*cmd)); | |
975 | cmd->data[0] = devid; | |
976 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
977 | } | |
978 | ||
431b2a20 | 979 | /* |
431b2a20 | 980 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 981 | * hardware about the new command. |
431b2a20 | 982 | */ |
4bf5beef JR |
983 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
984 | struct iommu_cmd *cmd, | |
985 | bool sync) | |
a19ae1ec | 986 | { |
23e967e1 | 987 | unsigned int count = 0; |
d334a563 | 988 | u32 left, next_tail; |
a19ae1ec | 989 | |
d334a563 | 990 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 991 | again: |
d334a563 | 992 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 993 | |
432abf68 | 994 | if (left <= 0x20) { |
23e967e1 TL |
995 | /* Skip udelay() the first time around */ |
996 | if (count++) { | |
997 | if (count == LOOP_TIMEOUT) { | |
101fa037 | 998 | pr_err("Command buffer timeout\n"); |
23e967e1 TL |
999 | return -EIO; |
1000 | } | |
da49f6df | 1001 | |
23e967e1 TL |
1002 | udelay(1); |
1003 | } | |
ac0ea6e9 | 1004 | |
23e967e1 TL |
1005 | /* Update head and recheck remaining space */ |
1006 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1007 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1008 | |
1009 | goto again; | |
8d201968 JR |
1010 | } |
1011 | ||
d334a563 | 1012 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1013 | |
23e967e1 | 1014 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1015 | iommu->need_sync = sync; |
ac0ea6e9 | 1016 | |
4bf5beef JR |
1017 | return 0; |
1018 | } | |
1019 | ||
1020 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1021 | struct iommu_cmd *cmd, | |
1022 | bool sync) | |
1023 | { | |
1024 | unsigned long flags; | |
1025 | int ret; | |
1026 | ||
27790398 | 1027 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef | 1028 | ret = __iommu_queue_command_sync(iommu, cmd, sync); |
27790398 | 1029 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1030 | |
4bf5beef | 1031 | return ret; |
8d201968 JR |
1032 | } |
1033 | ||
f1ca1512 JR |
1034 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1035 | { | |
1036 | return iommu_queue_command_sync(iommu, cmd, true); | |
1037 | } | |
1038 | ||
8d201968 JR |
1039 | /* |
1040 | * This function queues a completion wait command into the command | |
1041 | * buffer of an IOMMU | |
1042 | */ | |
a19ae1ec | 1043 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1044 | { |
1045 | struct iommu_cmd cmd; | |
4bf5beef | 1046 | unsigned long flags; |
ac0ea6e9 | 1047 | int ret; |
8d201968 | 1048 | |
09ee17eb | 1049 | if (!iommu->need_sync) |
815b33fd | 1050 | return 0; |
09ee17eb | 1051 | |
a19ae1ec | 1052 | |
4bf5beef JR |
1053 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1054 | ||
27790398 | 1055 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef JR |
1056 | |
1057 | iommu->cmd_sem = 0; | |
1058 | ||
1059 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1060 | if (ret) |
4bf5beef JR |
1061 | goto out_unlock; |
1062 | ||
1063 | ret = wait_on_sem(&iommu->cmd_sem); | |
1064 | ||
1065 | out_unlock: | |
27790398 | 1066 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1067 | |
4bf5beef | 1068 | return ret; |
8d201968 JR |
1069 | } |
1070 | ||
d8c13085 | 1071 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1072 | { |
d8c13085 | 1073 | struct iommu_cmd cmd; |
a19ae1ec | 1074 | |
d8c13085 | 1075 | build_inv_dte(&cmd, devid); |
7e4f88da | 1076 | |
d8c13085 JR |
1077 | return iommu_queue_command(iommu, &cmd); |
1078 | } | |
09ee17eb | 1079 | |
0688a099 | 1080 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1081 | { |
1082 | u32 devid; | |
09ee17eb | 1083 | |
7d0c5cc5 JR |
1084 | for (devid = 0; devid <= 0xffff; ++devid) |
1085 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1086 | |
7d0c5cc5 JR |
1087 | iommu_completion_wait(iommu); |
1088 | } | |
84df8175 | 1089 | |
7d0c5cc5 JR |
1090 | /* |
1091 | * This function uses heavy locking and may disable irqs for some time. But | |
1092 | * this is no issue because it is only called during resume. | |
1093 | */ | |
0688a099 | 1094 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1095 | { |
1096 | u32 dom_id; | |
a19ae1ec | 1097 | |
7d0c5cc5 JR |
1098 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1099 | struct iommu_cmd cmd; | |
1100 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1101 | dom_id, 1); | |
1102 | iommu_queue_command(iommu, &cmd); | |
1103 | } | |
8eed9833 | 1104 | |
7d0c5cc5 | 1105 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1106 | } |
1107 | ||
36b7200f SH |
1108 | static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) |
1109 | { | |
1110 | struct iommu_cmd cmd; | |
1111 | ||
1112 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1113 | dom_id, 1); | |
1114 | iommu_queue_command(iommu, &cmd); | |
1115 | ||
1116 | iommu_completion_wait(iommu); | |
1117 | } | |
1118 | ||
0688a099 | 1119 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1120 | { |
58fc7f14 | 1121 | struct iommu_cmd cmd; |
0518a3a4 | 1122 | |
58fc7f14 | 1123 | build_inv_all(&cmd); |
0518a3a4 | 1124 | |
58fc7f14 JR |
1125 | iommu_queue_command(iommu, &cmd); |
1126 | iommu_completion_wait(iommu); | |
1127 | } | |
1128 | ||
7ef2798d JR |
1129 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1130 | { | |
1131 | struct iommu_cmd cmd; | |
1132 | ||
1133 | build_inv_irt(&cmd, devid); | |
1134 | ||
1135 | iommu_queue_command(iommu, &cmd); | |
1136 | } | |
1137 | ||
0688a099 | 1138 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1139 | { |
1140 | u32 devid; | |
1141 | ||
1142 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1143 | iommu_flush_irt(iommu, devid); | |
1144 | ||
1145 | iommu_completion_wait(iommu); | |
1146 | } | |
1147 | ||
7d0c5cc5 JR |
1148 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1149 | { | |
58fc7f14 | 1150 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1151 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1152 | } else { |
0688a099 JR |
1153 | amd_iommu_flush_dte_all(iommu); |
1154 | amd_iommu_flush_irt_all(iommu); | |
1155 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1156 | } |
1157 | } | |
1158 | ||
431b2a20 | 1159 | /* |
cb41ed85 | 1160 | * Command send function for flushing on-device TLB |
431b2a20 | 1161 | */ |
6c542047 JR |
1162 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1163 | u64 address, size_t size) | |
3fa43655 JR |
1164 | { |
1165 | struct amd_iommu *iommu; | |
b00d3bcf | 1166 | struct iommu_cmd cmd; |
cb41ed85 | 1167 | int qdep; |
3fa43655 | 1168 | |
ea61cddb JR |
1169 | qdep = dev_data->ats.qdep; |
1170 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1171 | |
ea61cddb | 1172 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1173 | |
1174 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1175 | } |
1176 | ||
3332364e LG |
1177 | static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data) |
1178 | { | |
1179 | struct amd_iommu *iommu = data; | |
1180 | ||
1181 | return iommu_flush_dte(iommu, alias); | |
1182 | } | |
1183 | ||
431b2a20 | 1184 | /* |
431b2a20 | 1185 | * Command send function for invalidating a device table entry |
431b2a20 | 1186 | */ |
6c542047 | 1187 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1188 | { |
3fa43655 | 1189 | struct amd_iommu *iommu; |
e25bfb56 | 1190 | u16 alias; |
ee2fa743 | 1191 | int ret; |
a19ae1ec | 1192 | |
6c542047 | 1193 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1194 | |
3332364e LG |
1195 | if (dev_data->pdev) |
1196 | ret = pci_for_each_dma_alias(dev_data->pdev, | |
1197 | device_flush_dte_alias, iommu); | |
1198 | else | |
1199 | ret = iommu_flush_dte(iommu, dev_data->devid); | |
cb41ed85 JR |
1200 | if (ret) |
1201 | return ret; | |
1202 | ||
3332364e LG |
1203 | alias = amd_iommu_alias_table[dev_data->devid]; |
1204 | if (alias != dev_data->devid) { | |
1205 | ret = iommu_flush_dte(iommu, alias); | |
1206 | if (ret) | |
1207 | return ret; | |
1208 | } | |
1209 | ||
ea61cddb | 1210 | if (dev_data->ats.enabled) |
6c542047 | 1211 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1212 | |
ee2fa743 | 1213 | return ret; |
a19ae1ec JR |
1214 | } |
1215 | ||
431b2a20 JR |
1216 | /* |
1217 | * TLB invalidation function which is called from the mapping functions. | |
1218 | * It invalidates a single PTE if the range to flush is within a single | |
1219 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1220 | */ | |
17b124bf JR |
1221 | static void __domain_flush_pages(struct protection_domain *domain, |
1222 | u64 address, size_t size, int pde) | |
a19ae1ec | 1223 | { |
cb41ed85 | 1224 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1225 | struct iommu_cmd cmd; |
1226 | int ret = 0, i; | |
a19ae1ec | 1227 | |
11b6402c | 1228 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1229 | |
6b9376e3 | 1230 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1231 | if (!domain->dev_iommu[i]) |
1232 | continue; | |
1233 | ||
1234 | /* | |
1235 | * Devices of this domain are behind this IOMMU | |
1236 | * We need a TLB flush | |
1237 | */ | |
11b6402c | 1238 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1239 | } |
1240 | ||
cb41ed85 | 1241 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1242 | |
ea61cddb | 1243 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1244 | continue; |
1245 | ||
6c542047 | 1246 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1247 | } |
1248 | ||
11b6402c | 1249 | WARN_ON(ret); |
6de8ad9b JR |
1250 | } |
1251 | ||
17b124bf JR |
1252 | static void domain_flush_pages(struct protection_domain *domain, |
1253 | u64 address, size_t size) | |
6de8ad9b | 1254 | { |
17b124bf | 1255 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1256 | } |
b6c02715 | 1257 | |
42a49f96 | 1258 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1259 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1260 | { |
17b124bf | 1261 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1262 | } |
1263 | ||
17b124bf | 1264 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1265 | { |
17b124bf | 1266 | int i; |
18811f55 | 1267 | |
6b9376e3 | 1268 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1269 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1270 | continue; |
bfd1be18 | 1271 | |
17b124bf JR |
1272 | /* |
1273 | * Devices of this domain are behind this IOMMU | |
1274 | * We need to wait for completion of all commands. | |
1275 | */ | |
1276 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1277 | } |
e394d72a JR |
1278 | } |
1279 | ||
5cd3f2e9 TM |
1280 | /* Flush the not present cache if it exists */ |
1281 | static void domain_flush_np_cache(struct protection_domain *domain, | |
1282 | dma_addr_t iova, size_t size) | |
1283 | { | |
1284 | if (unlikely(amd_iommu_np_cache)) { | |
2a78f996 JR |
1285 | unsigned long flags; |
1286 | ||
1287 | spin_lock_irqsave(&domain->lock, flags); | |
5cd3f2e9 TM |
1288 | domain_flush_pages(domain, iova, size); |
1289 | domain_flush_complete(domain); | |
2a78f996 | 1290 | spin_unlock_irqrestore(&domain->lock, flags); |
5cd3f2e9 TM |
1291 | } |
1292 | } | |
1293 | ||
b00d3bcf | 1294 | |
09b42804 | 1295 | /* |
b00d3bcf | 1296 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1297 | */ |
17b124bf | 1298 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1299 | { |
b00d3bcf | 1300 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1301 | |
b00d3bcf | 1302 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1303 | device_flush_dte(dev_data); |
a345b23b JR |
1304 | } |
1305 | ||
431b2a20 JR |
1306 | /**************************************************************************** |
1307 | * | |
1308 | * The functions below are used the create the page table mappings for | |
1309 | * unity mapped regions. | |
1310 | * | |
1311 | ****************************************************************************/ | |
1312 | ||
ac3a7092 JR |
1313 | static void free_page_list(struct page *freelist) |
1314 | { | |
1315 | while (freelist != NULL) { | |
1316 | unsigned long p = (unsigned long)page_address(freelist); | |
1317 | freelist = freelist->freelist; | |
1318 | free_page(p); | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | static struct page *free_pt_page(unsigned long pt, struct page *freelist) | |
1323 | { | |
1324 | struct page *p = virt_to_page((void *)pt); | |
1325 | ||
1326 | p->freelist = freelist; | |
1327 | ||
1328 | return p; | |
1329 | } | |
1330 | ||
1331 | #define DEFINE_FREE_PT_FN(LVL, FN) \ | |
1332 | static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \ | |
1333 | { \ | |
1334 | unsigned long p; \ | |
1335 | u64 *pt; \ | |
1336 | int i; \ | |
1337 | \ | |
1338 | pt = (u64 *)__pt; \ | |
1339 | \ | |
1340 | for (i = 0; i < 512; ++i) { \ | |
1341 | /* PTE present? */ \ | |
1342 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1343 | continue; \ | |
1344 | \ | |
1345 | /* Large PTE? */ \ | |
1346 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1347 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1348 | continue; \ | |
1349 | \ | |
1350 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1351 | freelist = FN(p, freelist); \ | |
1352 | } \ | |
1353 | \ | |
1354 | return free_pt_page((unsigned long)pt, freelist); \ | |
1355 | } | |
1356 | ||
1357 | DEFINE_FREE_PT_FN(l2, free_pt_page) | |
1358 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1359 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1360 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1361 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1362 | ||
409afa44 JR |
1363 | static struct page *free_sub_pt(unsigned long root, int mode, |
1364 | struct page *freelist) | |
ac3a7092 | 1365 | { |
409afa44 | 1366 | switch (mode) { |
ac3a7092 | 1367 | case PAGE_MODE_NONE: |
69be8852 | 1368 | case PAGE_MODE_7_LEVEL: |
ac3a7092 JR |
1369 | break; |
1370 | case PAGE_MODE_1_LEVEL: | |
1371 | freelist = free_pt_page(root, freelist); | |
1372 | break; | |
1373 | case PAGE_MODE_2_LEVEL: | |
1374 | freelist = free_pt_l2(root, freelist); | |
1375 | break; | |
1376 | case PAGE_MODE_3_LEVEL: | |
1377 | freelist = free_pt_l3(root, freelist); | |
1378 | break; | |
1379 | case PAGE_MODE_4_LEVEL: | |
1380 | freelist = free_pt_l4(root, freelist); | |
1381 | break; | |
1382 | case PAGE_MODE_5_LEVEL: | |
1383 | freelist = free_pt_l5(root, freelist); | |
1384 | break; | |
1385 | case PAGE_MODE_6_LEVEL: | |
1386 | freelist = free_pt_l6(root, freelist); | |
1387 | break; | |
1388 | default: | |
1389 | BUG(); | |
1390 | } | |
1391 | ||
409afa44 JR |
1392 | return freelist; |
1393 | } | |
1394 | ||
1226c370 | 1395 | static void free_pagetable(struct domain_pgtable *pgtable) |
409afa44 | 1396 | { |
409afa44 | 1397 | struct page *freelist = NULL; |
eb791aa7 JR |
1398 | unsigned long root; |
1399 | ||
1226c370 JR |
1400 | if (pgtable->mode == PAGE_MODE_NONE) |
1401 | return; | |
409afa44 | 1402 | |
1226c370 JR |
1403 | BUG_ON(pgtable->mode < PAGE_MODE_NONE || |
1404 | pgtable->mode > PAGE_MODE_6_LEVEL); | |
69be8852 | 1405 | |
1226c370 JR |
1406 | root = (unsigned long)pgtable->root; |
1407 | freelist = free_sub_pt(root, pgtable->mode, freelist); | |
409afa44 | 1408 | |
ac3a7092 JR |
1409 | free_page_list(freelist); |
1410 | } | |
1411 | ||
308973d3 JR |
1412 | /* |
1413 | * This function is used to add another level to an IO page table. Adding | |
1414 | * another level increases the size of the address space by 9 bits to a size up | |
1415 | * to 64 bits. | |
1416 | */ | |
f15d9a99 | 1417 | static bool increase_address_space(struct protection_domain *domain, |
46ac18c3 | 1418 | unsigned long address, |
308973d3 JR |
1419 | gfp_t gfp) |
1420 | { | |
eb791aa7 | 1421 | struct domain_pgtable pgtable; |
754265bc | 1422 | unsigned long flags; |
119b2b2c | 1423 | bool ret = true; |
70fcd359 | 1424 | u64 *pte; |
308973d3 | 1425 | |
754265bc JR |
1426 | spin_lock_irqsave(&domain->lock, flags); |
1427 | ||
eb791aa7 JR |
1428 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
1429 | ||
119b2b2c JR |
1430 | if (address <= PM_LEVEL_SIZE(pgtable.mode)) |
1431 | goto out; | |
1432 | ||
1433 | ret = false; | |
1434 | if (WARN_ON_ONCE(pgtable.mode == PAGE_MODE_6_LEVEL)) | |
754265bc | 1435 | goto out; |
308973d3 JR |
1436 | |
1437 | pte = (void *)get_zeroed_page(gfp); | |
1438 | if (!pte) | |
754265bc | 1439 | goto out; |
308973d3 | 1440 | |
eb791aa7 JR |
1441 | *pte = PM_LEVEL_PDE(pgtable.mode, iommu_virt_to_phys(pgtable.root)); |
1442 | ||
19c6978f JR |
1443 | pgtable.root = pte; |
1444 | pgtable.mode += 1; | |
1445 | update_and_flush_device_table(domain, &pgtable); | |
1446 | domain_flush_complete(domain); | |
eb791aa7 | 1447 | |
19c6978f JR |
1448 | /* |
1449 | * Device Table needs to be updated and flushed before the new root can | |
1450 | * be published. | |
1451 | */ | |
70fcd359 | 1452 | amd_iommu_domain_set_pgtable(domain, pte, pgtable.mode); |
f15d9a99 JR |
1453 | |
1454 | ret = true; | |
308973d3 | 1455 | |
754265bc JR |
1456 | out: |
1457 | spin_unlock_irqrestore(&domain->lock, flags); | |
1458 | ||
f15d9a99 | 1459 | return ret; |
308973d3 JR |
1460 | } |
1461 | ||
1462 | static u64 *alloc_pte(struct protection_domain *domain, | |
1463 | unsigned long address, | |
cbb9d729 | 1464 | unsigned long page_size, |
308973d3 | 1465 | u64 **pte_page, |
f15d9a99 JR |
1466 | gfp_t gfp, |
1467 | bool *updated) | |
308973d3 | 1468 | { |
eb791aa7 | 1469 | struct domain_pgtable pgtable; |
cbb9d729 | 1470 | int level, end_lvl; |
308973d3 | 1471 | u64 *pte, *page; |
cbb9d729 JR |
1472 | |
1473 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 | 1474 | |
eb791aa7 JR |
1475 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
1476 | ||
1477 | while (address > PM_LEVEL_SIZE(pgtable.mode)) { | |
5b8a9a04 JR |
1478 | /* |
1479 | * Return an error if there is no memory to update the | |
1480 | * page-table. | |
1481 | */ | |
119b2b2c | 1482 | if (!increase_address_space(domain, address, gfp)) |
5b8a9a04 JR |
1483 | return NULL; |
1484 | ||
119b2b2c JR |
1485 | /* Read new values to check if update was successful */ |
1486 | amd_iommu_domain_get_pgtable(domain, &pgtable); | |
eb791aa7 JR |
1487 | } |
1488 | ||
308973d3 | 1489 | |
eb791aa7 JR |
1490 | level = pgtable.mode - 1; |
1491 | pte = &pgtable.root[PM_LEVEL_INDEX(level, address)]; | |
cbb9d729 JR |
1492 | address = PAGE_SIZE_ALIGN(address, page_size); |
1493 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1494 | |
1495 | while (level > end_lvl) { | |
7bfa5bd2 | 1496 | u64 __pte, __npte; |
6d568ef9 | 1497 | int pte_level; |
7bfa5bd2 | 1498 | |
6d568ef9 JR |
1499 | __pte = *pte; |
1500 | pte_level = PM_PTE_LEVEL(__pte); | |
7bfa5bd2 | 1501 | |
cc449541 AD |
1502 | /* |
1503 | * If we replace a series of large PTEs, we need | |
1504 | * to tear down all of them. | |
1505 | */ | |
1506 | if (IOMMU_PTE_PRESENT(__pte) && | |
6d568ef9 | 1507 | pte_level == PAGE_MODE_7_LEVEL) { |
cc449541 AD |
1508 | unsigned long count, i; |
1509 | u64 *lpte; | |
1510 | ||
1511 | lpte = first_pte_l7(pte, NULL, &count); | |
1512 | ||
1513 | /* | |
1514 | * Unmap the replicated PTEs that still match the | |
1515 | * original large mapping | |
1516 | */ | |
1517 | for (i = 0; i < count; ++i) | |
1518 | cmpxchg64(&lpte[i], __pte, 0ULL); | |
1519 | ||
f15d9a99 | 1520 | *updated = true; |
cc449541 AD |
1521 | continue; |
1522 | } | |
1523 | ||
1524 | if (!IOMMU_PTE_PRESENT(__pte) || | |
1525 | pte_level == PAGE_MODE_NONE) { | |
308973d3 | 1526 | page = (u64 *)get_zeroed_page(gfp); |
cc449541 | 1527 | |
308973d3 JR |
1528 | if (!page) |
1529 | return NULL; | |
7bfa5bd2 | 1530 | |
2543a786 | 1531 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
7bfa5bd2 | 1532 | |
134414ff | 1533 | /* pte could have been changed somewhere. */ |
9db034d5 | 1534 | if (cmpxchg64(pte, __pte, __npte) != __pte) |
7bfa5bd2 | 1535 | free_page((unsigned long)page); |
6ccb72f8 | 1536 | else if (IOMMU_PTE_PRESENT(__pte)) |
f15d9a99 | 1537 | *updated = true; |
9db034d5 JR |
1538 | |
1539 | continue; | |
308973d3 JR |
1540 | } |
1541 | ||
cbb9d729 | 1542 | /* No level skipping support yet */ |
6d568ef9 | 1543 | if (pte_level != level) |
cbb9d729 JR |
1544 | return NULL; |
1545 | ||
308973d3 JR |
1546 | level -= 1; |
1547 | ||
9db034d5 | 1548 | pte = IOMMU_PTE_PAGE(__pte); |
308973d3 JR |
1549 | |
1550 | if (pte_page && level == end_lvl) | |
1551 | *pte_page = pte; | |
1552 | ||
1553 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1554 | } | |
1555 | ||
1556 | return pte; | |
1557 | } | |
1558 | ||
1559 | /* | |
1560 | * This function checks if there is a PTE for a given dma address. If | |
1561 | * there is one, it returns the pointer to it. | |
1562 | */ | |
3039ca1b JR |
1563 | static u64 *fetch_pte(struct protection_domain *domain, |
1564 | unsigned long address, | |
1565 | unsigned long *page_size) | |
308973d3 | 1566 | { |
eb791aa7 | 1567 | struct domain_pgtable pgtable; |
308973d3 JR |
1568 | int level; |
1569 | u64 *pte; | |
1570 | ||
4674686d | 1571 | *page_size = 0; |
1572 | ||
eb791aa7 JR |
1573 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
1574 | ||
1575 | if (address > PM_LEVEL_SIZE(pgtable.mode)) | |
24cd7723 JR |
1576 | return NULL; |
1577 | ||
eb791aa7 JR |
1578 | level = pgtable.mode - 1; |
1579 | pte = &pgtable.root[PM_LEVEL_INDEX(level, address)]; | |
3039ca1b | 1580 | *page_size = PTE_LEVEL_PAGE_SIZE(level); |
308973d3 | 1581 | |
24cd7723 JR |
1582 | while (level > 0) { |
1583 | ||
1584 | /* Not Present */ | |
308973d3 JR |
1585 | if (!IOMMU_PTE_PRESENT(*pte)) |
1586 | return NULL; | |
1587 | ||
24cd7723 | 1588 | /* Large PTE */ |
3039ca1b JR |
1589 | if (PM_PTE_LEVEL(*pte) == 7 || |
1590 | PM_PTE_LEVEL(*pte) == 0) | |
1591 | break; | |
24cd7723 JR |
1592 | |
1593 | /* No level skipping support yet */ | |
1594 | if (PM_PTE_LEVEL(*pte) != level) | |
1595 | return NULL; | |
1596 | ||
308973d3 JR |
1597 | level -= 1; |
1598 | ||
24cd7723 | 1599 | /* Walk to the next level */ |
3039ca1b JR |
1600 | pte = IOMMU_PTE_PAGE(*pte); |
1601 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1602 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1603 | } | |
1604 | ||
7f1f1683 AD |
1605 | /* |
1606 | * If we have a series of large PTEs, make | |
1607 | * sure to return a pointer to the first one. | |
1608 | */ | |
1609 | if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL) | |
1610 | pte = first_pte_l7(pte, page_size, NULL); | |
308973d3 JR |
1611 | |
1612 | return pte; | |
1613 | } | |
1614 | ||
6f820bb9 JR |
1615 | static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist) |
1616 | { | |
1617 | unsigned long pt; | |
1618 | int mode; | |
1619 | ||
1620 | while (cmpxchg64(pte, pteval, 0) != pteval) { | |
1621 | pr_warn("AMD-Vi: IOMMU pte changed since we read it\n"); | |
1622 | pteval = *pte; | |
1623 | } | |
1624 | ||
1625 | if (!IOMMU_PTE_PRESENT(pteval)) | |
1626 | return freelist; | |
1627 | ||
1628 | pt = (unsigned long)IOMMU_PTE_PAGE(pteval); | |
1629 | mode = IOMMU_PTE_MODE(pteval); | |
1630 | ||
1631 | return free_sub_pt(pt, mode, freelist); | |
1632 | } | |
1633 | ||
431b2a20 JR |
1634 | /* |
1635 | * Generic mapping functions. It maps a physical address into a DMA | |
1636 | * address space. It allocates the page table pages if necessary. | |
1637 | * In the future it can be extended to a generic mapping function | |
1638 | * supporting all features of AMD IOMMU page tables like level skipping | |
1639 | * and full 64 bit address spaces. | |
1640 | */ | |
38e817fe JR |
1641 | static int iommu_map_page(struct protection_domain *dom, |
1642 | unsigned long bus_addr, | |
1643 | unsigned long phys_addr, | |
b911b89b | 1644 | unsigned long page_size, |
abdc5eb3 | 1645 | int prot, |
b911b89b | 1646 | gfp_t gfp) |
bd0e5211 | 1647 | { |
6f820bb9 | 1648 | struct page *freelist = NULL; |
f15d9a99 | 1649 | bool updated = false; |
8bda3092 | 1650 | u64 __pte, *pte; |
f15d9a99 | 1651 | int ret, i, count; |
abdc5eb3 | 1652 | |
d4b03664 JR |
1653 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1654 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1655 | ||
f15d9a99 | 1656 | ret = -EINVAL; |
bad1cac2 | 1657 | if (!(prot & IOMMU_PROT_MASK)) |
f15d9a99 | 1658 | goto out; |
bd0e5211 | 1659 | |
d4b03664 | 1660 | count = PAGE_SIZE_PTE_COUNT(page_size); |
f15d9a99 | 1661 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated); |
cbb9d729 | 1662 | |
f15d9a99 | 1663 | ret = -ENOMEM; |
63eaa75e | 1664 | if (!pte) |
f15d9a99 | 1665 | goto out; |
63eaa75e | 1666 | |
cbb9d729 | 1667 | for (i = 0; i < count; ++i) |
6f820bb9 JR |
1668 | freelist = free_clear_pte(&pte[i], pte[i], freelist); |
1669 | ||
1670 | if (freelist != NULL) | |
f15d9a99 | 1671 | updated = true; |
bd0e5211 | 1672 | |
d4b03664 | 1673 | if (count > 1) { |
2543a786 | 1674 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
07a80a6b | 1675 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
cbb9d729 | 1676 | } else |
4dfc2788 | 1677 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
bd0e5211 | 1678 | |
bd0e5211 JR |
1679 | if (prot & IOMMU_PROT_IR) |
1680 | __pte |= IOMMU_PTE_IR; | |
1681 | if (prot & IOMMU_PROT_IW) | |
1682 | __pte |= IOMMU_PTE_IW; | |
1683 | ||
cbb9d729 JR |
1684 | for (i = 0; i < count; ++i) |
1685 | pte[i] = __pte; | |
bd0e5211 | 1686 | |
f15d9a99 JR |
1687 | ret = 0; |
1688 | ||
1689 | out: | |
2a78f996 JR |
1690 | if (updated) { |
1691 | unsigned long flags; | |
1692 | ||
1693 | spin_lock_irqsave(&dom->lock, flags); | |
119b2b2c JR |
1694 | /* |
1695 | * Flush domain TLB(s) and wait for completion. Any Device-Table | |
1696 | * Updates and flushing already happened in | |
1697 | * increase_address_space(). | |
1698 | */ | |
1699 | domain_flush_tlb_pde(dom); | |
1700 | domain_flush_complete(dom); | |
2a78f996 JR |
1701 | spin_unlock_irqrestore(&dom->lock, flags); |
1702 | } | |
04bfdd84 | 1703 | |
6f820bb9 JR |
1704 | /* Everything flushed out, free pages now */ |
1705 | free_page_list(freelist); | |
1706 | ||
f15d9a99 | 1707 | return ret; |
bd0e5211 JR |
1708 | } |
1709 | ||
24cd7723 JR |
1710 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1711 | unsigned long bus_addr, | |
1712 | unsigned long page_size) | |
eb74ff6c | 1713 | { |
71b390e9 JR |
1714 | unsigned long long unmapped; |
1715 | unsigned long unmap_size; | |
24cd7723 JR |
1716 | u64 *pte; |
1717 | ||
1718 | BUG_ON(!is_power_of_2(page_size)); | |
1719 | ||
1720 | unmapped = 0; | |
eb74ff6c | 1721 | |
24cd7723 JR |
1722 | while (unmapped < page_size) { |
1723 | ||
71b390e9 JR |
1724 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1725 | ||
1726 | if (pte) { | |
1727 | int i, count; | |
1728 | ||
1729 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1730 | for (i = 0; i < count; i++) |
1731 | pte[i] = 0ULL; | |
1732 | } | |
1733 | ||
1734 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1735 | unmapped += unmap_size; | |
1736 | } | |
1737 | ||
60d0ca3c | 1738 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1739 | |
24cd7723 | 1740 | return unmapped; |
eb74ff6c | 1741 | } |
eb74ff6c | 1742 | |
431b2a20 JR |
1743 | /**************************************************************************** |
1744 | * | |
1745 | * The next functions belong to the domain allocation. A domain is | |
1746 | * allocated for every IOMMU as the default domain. If device isolation | |
1747 | * is enabled, every device get its own domain. The most important thing | |
1748 | * about domains is the page table mapping the DMA address space they | |
1749 | * contain. | |
1750 | * | |
1751 | ****************************************************************************/ | |
1752 | ||
ec487d1a JR |
1753 | static u16 domain_id_alloc(void) |
1754 | { | |
ec487d1a JR |
1755 | int id; |
1756 | ||
2bc00180 | 1757 | spin_lock(&pd_bitmap_lock); |
ec487d1a JR |
1758 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); |
1759 | BUG_ON(id == 0); | |
1760 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1761 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1762 | else | |
1763 | id = 0; | |
2bc00180 | 1764 | spin_unlock(&pd_bitmap_lock); |
ec487d1a JR |
1765 | |
1766 | return id; | |
1767 | } | |
1768 | ||
a2acfb75 JR |
1769 | static void domain_id_free(int id) |
1770 | { | |
2bc00180 | 1771 | spin_lock(&pd_bitmap_lock); |
a2acfb75 JR |
1772 | if (id > 0 && id < MAX_DOMAIN_ID) |
1773 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
2bc00180 | 1774 | spin_unlock(&pd_bitmap_lock); |
a2acfb75 | 1775 | } |
a2acfb75 | 1776 | |
b16137b1 JR |
1777 | static void free_gcr3_tbl_level1(u64 *tbl) |
1778 | { | |
1779 | u64 *ptr; | |
1780 | int i; | |
1781 | ||
1782 | for (i = 0; i < 512; ++i) { | |
1783 | if (!(tbl[i] & GCR3_VALID)) | |
1784 | continue; | |
1785 | ||
2543a786 | 1786 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1787 | |
1788 | free_page((unsigned long)ptr); | |
1789 | } | |
1790 | } | |
1791 | ||
1792 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1793 | { | |
1794 | u64 *ptr; | |
1795 | int i; | |
1796 | ||
1797 | for (i = 0; i < 512; ++i) { | |
1798 | if (!(tbl[i] & GCR3_VALID)) | |
1799 | continue; | |
1800 | ||
2543a786 | 1801 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1802 | |
1803 | free_gcr3_tbl_level1(ptr); | |
1804 | } | |
1805 | } | |
1806 | ||
52815b75 JR |
1807 | static void free_gcr3_table(struct protection_domain *domain) |
1808 | { | |
b16137b1 JR |
1809 | if (domain->glx == 2) |
1810 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1811 | else if (domain->glx == 1) | |
1812 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1813 | else |
1814 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1815 | |
52815b75 JR |
1816 | free_page((unsigned long)domain->gcr3_tbl); |
1817 | } | |
1818 | ||
ff18c4e5 | 1819 | static void set_dte_entry(u16 devid, struct protection_domain *domain, |
19c6978f | 1820 | struct domain_pgtable *pgtable, |
ff18c4e5 | 1821 | bool ats, bool ppr) |
b20ac0d4 | 1822 | { |
132bd68f | 1823 | u64 pte_root = 0; |
ee6c2868 | 1824 | u64 flags = 0; |
36b7200f | 1825 | u32 old_domid; |
863c74eb | 1826 | |
19c6978f JR |
1827 | if (pgtable->mode != PAGE_MODE_NONE) |
1828 | pte_root = iommu_virt_to_phys(pgtable->root); | |
eb791aa7 | 1829 | |
19c6978f | 1830 | pte_root |= (pgtable->mode & DEV_ENTRY_MODE_MASK) |
38ddf41b | 1831 | << DEV_ENTRY_MODE_SHIFT; |
07a80a6b | 1832 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
b20ac0d4 | 1833 | |
ee6c2868 JR |
1834 | flags = amd_iommu_dev_table[devid].data[1]; |
1835 | ||
fd7b5535 JR |
1836 | if (ats) |
1837 | flags |= DTE_FLAG_IOTLB; | |
1838 | ||
ff18c4e5 GH |
1839 | if (ppr) { |
1840 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1841 | ||
1842 | if (iommu_feature(iommu, FEATURE_EPHSUP)) | |
1843 | pte_root |= 1ULL << DEV_ENTRY_PPR; | |
1844 | } | |
1845 | ||
52815b75 | 1846 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1847 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1848 | u64 glx = domain->glx; |
1849 | u64 tmp; | |
1850 | ||
1851 | pte_root |= DTE_FLAG_GV; | |
1852 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1853 | ||
1854 | /* First mask out possible old values for GCR3 table */ | |
1855 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1856 | flags &= ~tmp; | |
1857 | ||
1858 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1859 | flags &= ~tmp; | |
1860 | ||
1861 | /* Encode GCR3 table into DTE */ | |
1862 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1863 | pte_root |= tmp; | |
1864 | ||
1865 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1866 | flags |= tmp; | |
1867 | ||
1868 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1869 | flags |= tmp; | |
1870 | } | |
1871 | ||
45a01c42 | 1872 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1873 | flags |= domain->id; |
1874 | ||
36b7200f | 1875 | old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK; |
ee6c2868 JR |
1876 | amd_iommu_dev_table[devid].data[1] = flags; |
1877 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
36b7200f SH |
1878 | |
1879 | /* | |
1880 | * A kdump kernel might be replacing a domain ID that was copied from | |
1881 | * the previous kernel--if so, it needs to flush the translation cache | |
1882 | * entries for the old domain ID that is being overwritten | |
1883 | */ | |
1884 | if (old_domid) { | |
1885 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1886 | ||
1887 | amd_iommu_flush_tlb_domid(iommu, old_domid); | |
1888 | } | |
15898bbc JR |
1889 | } |
1890 | ||
1891 | static void clear_dte_entry(u16 devid) | |
1892 | { | |
15898bbc | 1893 | /* remove entry from the device table seen by the hardware */ |
07a80a6b | 1894 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
cbf3ccd0 | 1895 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc JR |
1896 | |
1897 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1898 | } |
1899 | ||
ec9e79ef JR |
1900 | static void do_attach(struct iommu_dev_data *dev_data, |
1901 | struct protection_domain *domain) | |
7f760ddd | 1902 | { |
19c6978f | 1903 | struct domain_pgtable pgtable; |
7f760ddd | 1904 | struct amd_iommu *iommu; |
ec9e79ef | 1905 | bool ats; |
fd7b5535 | 1906 | |
ec9e79ef JR |
1907 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1908 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1909 | |
1910 | /* Update data structures */ | |
1911 | dev_data->domain = domain; | |
1912 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1913 | |
1914 | /* Do reference counting */ | |
1915 | domain->dev_iommu[iommu->index] += 1; | |
1916 | domain->dev_cnt += 1; | |
1917 | ||
e25bfb56 | 1918 | /* Update device table */ |
19c6978f JR |
1919 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
1920 | set_dte_entry(dev_data->devid, domain, &pgtable, | |
1921 | ats, dev_data->iommu_v2); | |
3332364e | 1922 | clone_aliases(dev_data->pdev); |
e25bfb56 | 1923 | |
6c542047 | 1924 | device_flush_dte(dev_data); |
7f760ddd JR |
1925 | } |
1926 | ||
ec9e79ef | 1927 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1928 | { |
9825bd94 | 1929 | struct protection_domain *domain = dev_data->domain; |
7f760ddd | 1930 | struct amd_iommu *iommu; |
7f760ddd | 1931 | |
ec9e79ef | 1932 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc | 1933 | |
7f760ddd JR |
1934 | /* Update data structures */ |
1935 | dev_data->domain = NULL; | |
1936 | list_del(&dev_data->list); | |
f62dda66 | 1937 | clear_dte_entry(dev_data->devid); |
3332364e | 1938 | clone_aliases(dev_data->pdev); |
15898bbc | 1939 | |
7f760ddd | 1940 | /* Flush the DTE entry */ |
6c542047 | 1941 | device_flush_dte(dev_data); |
9825bd94 SS |
1942 | |
1943 | /* Flush IOTLB */ | |
1944 | domain_flush_tlb_pde(domain); | |
1945 | ||
1946 | /* Wait for the flushes to finish */ | |
1947 | domain_flush_complete(domain); | |
1948 | ||
1949 | /* decrease reference counters - needs to happen after the flushes */ | |
1950 | domain->dev_iommu[iommu->index] -= 1; | |
1951 | domain->dev_cnt -= 1; | |
2b681faf JR |
1952 | } |
1953 | ||
52815b75 JR |
1954 | static void pdev_iommuv2_disable(struct pci_dev *pdev) |
1955 | { | |
1956 | pci_disable_ats(pdev); | |
1957 | pci_disable_pri(pdev); | |
1958 | pci_disable_pasid(pdev); | |
1959 | } | |
1960 | ||
6a113ddc JR |
1961 | /* FIXME: Change generic reset-function to do the same */ |
1962 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1963 | { | |
1964 | u16 control; | |
1965 | int pos; | |
1966 | ||
46277b75 | 1967 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
1968 | if (!pos) |
1969 | return -EINVAL; | |
1970 | ||
46277b75 JR |
1971 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
1972 | control |= PCI_PRI_CTRL_RESET; | |
1973 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
1974 | |
1975 | return 0; | |
1976 | } | |
1977 | ||
52815b75 JR |
1978 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
1979 | { | |
6a113ddc JR |
1980 | bool reset_enable; |
1981 | int reqs, ret; | |
1982 | ||
1983 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1984 | reqs = 32; | |
1985 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
1986 | reqs = 1; | |
1987 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
1988 | |
1989 | /* Only allow access to user-accessible pages */ | |
1990 | ret = pci_enable_pasid(pdev, 0); | |
1991 | if (ret) | |
1992 | goto out_err; | |
1993 | ||
1994 | /* First reset the PRI state of the device */ | |
1995 | ret = pci_reset_pri(pdev); | |
1996 | if (ret) | |
1997 | goto out_err; | |
1998 | ||
6a113ddc JR |
1999 | /* Enable PRI */ |
2000 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2001 | if (ret) |
2002 | goto out_err; | |
2003 | ||
6a113ddc JR |
2004 | if (reset_enable) { |
2005 | ret = pri_reset_while_enabled(pdev); | |
2006 | if (ret) | |
2007 | goto out_err; | |
2008 | } | |
2009 | ||
52815b75 JR |
2010 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2011 | if (ret) | |
2012 | goto out_err; | |
2013 | ||
2014 | return 0; | |
2015 | ||
2016 | out_err: | |
2017 | pci_disable_pri(pdev); | |
2018 | pci_disable_pasid(pdev); | |
2019 | ||
2020 | return ret; | |
2021 | } | |
2022 | ||
407d733e | 2023 | /* |
29a0c415 AMG |
2024 | * If a device is not yet associated with a domain, this function makes the |
2025 | * device visible in the domain | |
407d733e | 2026 | */ |
15898bbc JR |
2027 | static int attach_device(struct device *dev, |
2028 | struct protection_domain *domain) | |
0feae533 | 2029 | { |
ea61cddb | 2030 | struct iommu_dev_data *dev_data; |
57f9842e | 2031 | struct pci_dev *pdev; |
eba6ac60 | 2032 | unsigned long flags; |
15898bbc | 2033 | int ret; |
eba6ac60 | 2034 | |
f6c0bfce JR |
2035 | spin_lock_irqsave(&domain->lock, flags); |
2036 | ||
05a0542b | 2037 | dev_data = dev_iommu_priv_get(dev); |
ea61cddb | 2038 | |
ab7b2577 JR |
2039 | spin_lock(&dev_data->lock); |
2040 | ||
45e528d9 JR |
2041 | ret = -EBUSY; |
2042 | if (dev_data->domain != NULL) | |
2043 | goto out; | |
2044 | ||
2bf9a0a1 WZ |
2045 | if (!dev_is_pci(dev)) |
2046 | goto skip_ats_check; | |
2047 | ||
2048 | pdev = to_pci_dev(dev); | |
52815b75 | 2049 | if (domain->flags & PD_IOMMUV2_MASK) { |
57f9842e JR |
2050 | struct iommu_domain *def_domain = iommu_get_dma_domain(dev); |
2051 | ||
f6c0bfce | 2052 | ret = -EINVAL; |
57f9842e | 2053 | if (def_domain->type != IOMMU_DOMAIN_IDENTITY) |
f6c0bfce | 2054 | goto out; |
52815b75 | 2055 | |
02ca2021 JR |
2056 | if (dev_data->iommu_v2) { |
2057 | if (pdev_iommuv2_enable(pdev) != 0) | |
f6c0bfce | 2058 | goto out; |
52815b75 | 2059 | |
02ca2021 JR |
2060 | dev_data->ats.enabled = true; |
2061 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
83d18bdf | 2062 | dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev); |
02ca2021 | 2063 | } |
52815b75 JR |
2064 | } else if (amd_iommu_iotlb_sup && |
2065 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2066 | dev_data->ats.enabled = true; |
2067 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2068 | } | |
fd7b5535 | 2069 | |
2bf9a0a1 | 2070 | skip_ats_check: |
45e528d9 JR |
2071 | ret = 0; |
2072 | ||
2073 | do_attach(dev_data, domain); | |
b20ac0d4 | 2074 | |
0feae533 JR |
2075 | /* |
2076 | * We might boot into a crash-kernel here. The crashed kernel | |
2077 | * left the caches in the IOMMU dirty. So we have to flush | |
2078 | * here to evict all dirty stuff. | |
2079 | */ | |
17b124bf | 2080 | domain_flush_tlb_pde(domain); |
15898bbc | 2081 | |
0b15e02f | 2082 | domain_flush_complete(domain); |
71f77580 | 2083 | |
f6c0bfce | 2084 | out: |
ab7b2577 | 2085 | spin_unlock(&dev_data->lock); |
24100055 | 2086 | |
3a11905b | 2087 | spin_unlock_irqrestore(&domain->lock, flags); |
7f760ddd | 2088 | |
f6c0bfce | 2089 | return ret; |
355bf553 JR |
2090 | } |
2091 | ||
2092 | /* | |
2093 | * Removes a device from a protection domain (with devtable_lock held) | |
2094 | */ | |
15898bbc | 2095 | static void detach_device(struct device *dev) |
355bf553 | 2096 | { |
52815b75 | 2097 | struct protection_domain *domain; |
ea61cddb | 2098 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2099 | unsigned long flags; |
2100 | ||
05a0542b | 2101 | dev_data = dev_iommu_priv_get(dev); |
52815b75 | 2102 | domain = dev_data->domain; |
ec9e79ef | 2103 | |
f6c0bfce JR |
2104 | spin_lock_irqsave(&domain->lock, flags); |
2105 | ||
ab7b2577 JR |
2106 | spin_lock(&dev_data->lock); |
2107 | ||
ea3fd040 AMG |
2108 | /* |
2109 | * First check if the device is still attached. It might already | |
2110 | * be detached from its domain because the generic | |
2111 | * iommu_detach_group code detached it and we try again here in | |
2112 | * our alias handling. | |
2113 | */ | |
2114 | if (WARN_ON(!dev_data->domain)) | |
f6c0bfce | 2115 | goto out; |
ea3fd040 | 2116 | |
f6c0bfce | 2117 | do_detach(dev_data); |
fd7b5535 | 2118 | |
2bf9a0a1 | 2119 | if (!dev_is_pci(dev)) |
f6c0bfce | 2120 | goto out; |
2bf9a0a1 | 2121 | |
02ca2021 | 2122 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2123 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2124 | else if (dev_data->ats.enabled) | |
ea61cddb | 2125 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2126 | |
2127 | dev_data->ats.enabled = false; | |
f6c0bfce JR |
2128 | |
2129 | out: | |
ab7b2577 JR |
2130 | spin_unlock(&dev_data->lock); |
2131 | ||
f6c0bfce | 2132 | spin_unlock_irqrestore(&domain->lock, flags); |
355bf553 | 2133 | } |
e275a2a0 | 2134 | |
dce8d696 | 2135 | static struct iommu_device *amd_iommu_probe_device(struct device *dev) |
e275a2a0 | 2136 | { |
dce8d696 | 2137 | struct iommu_device *iommu_dev; |
e275a2a0 | 2138 | struct amd_iommu *iommu; |
7aba6cb9 | 2139 | int ret, devid; |
e275a2a0 | 2140 | |
57bd2c24 | 2141 | if (!check_device(dev)) |
dce8d696 | 2142 | return ERR_PTR(-ENODEV); |
e275a2a0 | 2143 | |
aafd8ba0 | 2144 | devid = get_device_id(dev); |
9ee35e4c | 2145 | if (devid < 0) |
dce8d696 | 2146 | return ERR_PTR(devid); |
7aba6cb9 | 2147 | |
aafd8ba0 | 2148 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2149 | |
05a0542b | 2150 | if (dev_iommu_priv_get(dev)) |
dce8d696 JR |
2151 | return &iommu->iommu; |
2152 | ||
aafd8ba0 | 2153 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2154 | if (ret) { |
2155 | if (ret != -ENOTSUPP) | |
5f226da1 | 2156 | dev_err(dev, "Failed to initialize - trying to proceed anyway\n"); |
dce8d696 | 2157 | iommu_dev = ERR_PTR(ret); |
aafd8ba0 | 2158 | iommu_ignore_device(dev); |
dce8d696 JR |
2159 | } else { |
2160 | iommu_dev = &iommu->iommu; | |
aafd8ba0 | 2161 | } |
2c9195e9 | 2162 | |
dce8d696 | 2163 | iommu_completion_wait(iommu); |
2c9195e9 | 2164 | |
dce8d696 JR |
2165 | return iommu_dev; |
2166 | } | |
657cbb6b | 2167 | |
dce8d696 JR |
2168 | static void amd_iommu_probe_finalize(struct device *dev) |
2169 | { | |
2170 | struct iommu_domain *domain; | |
ac1534a5 | 2171 | |
07ee8694 JR |
2172 | /* Domains are initialized for this device - have a look what we ended up with */ |
2173 | domain = iommu_get_domain_for_dev(dev); | |
57f9842e | 2174 | if (domain->type == IOMMU_DOMAIN_DMA) |
be62dbf5 | 2175 | iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0); |
e275a2a0 JR |
2176 | } |
2177 | ||
dce8d696 | 2178 | static void amd_iommu_release_device(struct device *dev) |
8638c491 | 2179 | { |
736c3333 | 2180 | int devid = get_device_id(dev); |
aafd8ba0 | 2181 | struct amd_iommu *iommu; |
aafd8ba0 JR |
2182 | |
2183 | if (!check_device(dev)) | |
2184 | return; | |
2185 | ||
aafd8ba0 JR |
2186 | iommu = amd_iommu_rlookup_table[devid]; |
2187 | ||
dce8d696 | 2188 | amd_iommu_uninit_device(dev); |
aafd8ba0 | 2189 | iommu_completion_wait(iommu); |
8638c491 JR |
2190 | } |
2191 | ||
b097d11a WZ |
2192 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2193 | { | |
2194 | if (dev_is_pci(dev)) | |
2195 | return pci_device_group(dev); | |
2196 | ||
2197 | return acpihid_device_group(dev); | |
2198 | } | |
2199 | ||
be62dbf5 TM |
2200 | static int amd_iommu_domain_get_attr(struct iommu_domain *domain, |
2201 | enum iommu_attr attr, void *data) | |
2202 | { | |
2203 | switch (domain->type) { | |
2204 | case IOMMU_DOMAIN_UNMANAGED: | |
2205 | return -ENODEV; | |
2206 | case IOMMU_DOMAIN_DMA: | |
2207 | switch (attr) { | |
2208 | case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE: | |
2209 | *(int *)data = !amd_iommu_unmap_flush; | |
2210 | return 0; | |
2211 | default: | |
2212 | return -ENODEV; | |
2213 | } | |
2214 | break; | |
2215 | default: | |
2216 | return -EINVAL; | |
2217 | } | |
2218 | } | |
2219 | ||
431b2a20 JR |
2220 | /***************************************************************************** |
2221 | * | |
2222 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2223 | * | |
2224 | *****************************************************************************/ | |
2225 | ||
19c6978f JR |
2226 | static void update_device_table(struct protection_domain *domain, |
2227 | struct domain_pgtable *pgtable) | |
04bfdd84 | 2228 | { |
492667da | 2229 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2230 | |
3254de6b | 2231 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
19c6978f JR |
2232 | set_dte_entry(dev_data->devid, domain, pgtable, |
2233 | dev_data->ats.enabled, dev_data->iommu_v2); | |
3332364e | 2234 | clone_aliases(dev_data->pdev); |
3254de6b | 2235 | } |
04bfdd84 JR |
2236 | } |
2237 | ||
19c6978f JR |
2238 | static void update_and_flush_device_table(struct protection_domain *domain, |
2239 | struct domain_pgtable *pgtable) | |
2240 | { | |
2241 | update_device_table(domain, pgtable); | |
2242 | domain_flush_devices(domain); | |
2243 | } | |
2244 | ||
04bfdd84 JR |
2245 | static void update_domain(struct protection_domain *domain) |
2246 | { | |
19c6978f | 2247 | struct domain_pgtable pgtable; |
17b124bf | 2248 | |
19c6978f JR |
2249 | /* Update device table */ |
2250 | amd_iommu_domain_get_pgtable(domain, &pgtable); | |
2251 | update_and_flush_device_table(domain, &pgtable); | |
2252 | ||
2253 | /* Flush domain TLB(s) and wait for completion */ | |
17b124bf | 2254 | domain_flush_tlb_pde(domain); |
f44a4d7e | 2255 | domain_flush_complete(domain); |
04bfdd84 JR |
2256 | } |
2257 | ||
3a18404c | 2258 | int __init amd_iommu_init_api(void) |
27c2127a | 2259 | { |
460c26d0 | 2260 | int ret, err = 0; |
307d5851 JR |
2261 | |
2262 | ret = iova_cache_get(); | |
2263 | if (ret) | |
2264 | return ret; | |
9a4d3bf5 WZ |
2265 | |
2266 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); | |
2267 | if (err) | |
2268 | return err; | |
2269 | #ifdef CONFIG_ARM_AMBA | |
2270 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2271 | if (err) | |
2272 | return err; | |
2273 | #endif | |
0076cd3d WZ |
2274 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2275 | if (err) | |
2276 | return err; | |
c5b5da9c | 2277 | |
460c26d0 | 2278 | return 0; |
f5325094 JR |
2279 | } |
2280 | ||
6631ee9d JR |
2281 | int __init amd_iommu_init_dma_ops(void) |
2282 | { | |
cc7c8ad9 | 2283 | swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0; |
6631ee9d | 2284 | |
62410eeb | 2285 | if (amd_iommu_unmap_flush) |
101fa037 | 2286 | pr_info("IO/TLB flush on unmap enabled\n"); |
62410eeb | 2287 | else |
101fa037 | 2288 | pr_info("Lazy IO/TLB flushing enabled\n"); |
62410eeb | 2289 | |
6631ee9d | 2290 | return 0; |
c5b5da9c | 2291 | |
6631ee9d | 2292 | } |
6d98cd80 JR |
2293 | |
2294 | /***************************************************************************** | |
2295 | * | |
2296 | * The following functions belong to the exported interface of AMD IOMMU | |
2297 | * | |
2298 | * This interface allows access to lower level functions of the IOMMU | |
2299 | * like protection domain handling and assignement of devices to domains | |
2300 | * which is not possible with the dma_ops interface. | |
2301 | * | |
2302 | *****************************************************************************/ | |
2303 | ||
6d98cd80 JR |
2304 | static void cleanup_domain(struct protection_domain *domain) |
2305 | { | |
9b29d3c6 | 2306 | struct iommu_dev_data *entry; |
6d98cd80 | 2307 | unsigned long flags; |
6d98cd80 | 2308 | |
f6c0bfce | 2309 | spin_lock_irqsave(&domain->lock, flags); |
6d98cd80 | 2310 | |
9b29d3c6 JR |
2311 | while (!list_empty(&domain->dev_list)) { |
2312 | entry = list_first_entry(&domain->dev_list, | |
2313 | struct iommu_dev_data, list); | |
ea3fd040 | 2314 | BUG_ON(!entry->domain); |
f6c0bfce | 2315 | do_detach(entry); |
492667da | 2316 | } |
6d98cd80 | 2317 | |
f6c0bfce | 2318 | spin_unlock_irqrestore(&domain->lock, flags); |
6d98cd80 JR |
2319 | } |
2320 | ||
2650815f JR |
2321 | static void protection_domain_free(struct protection_domain *domain) |
2322 | { | |
75b27745 JR |
2323 | struct domain_pgtable pgtable; |
2324 | ||
2650815f JR |
2325 | if (!domain) |
2326 | return; | |
2327 | ||
2328 | if (domain->id) | |
2329 | domain_id_free(domain->id); | |
2330 | ||
75b27745 | 2331 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
70fcd359 | 2332 | amd_iommu_domain_clr_pt_root(domain); |
75b27745 JR |
2333 | free_pagetable(&pgtable); |
2334 | ||
2650815f JR |
2335 | kfree(domain); |
2336 | } | |
2337 | ||
a71730e2 | 2338 | static int protection_domain_init(struct protection_domain *domain, int mode) |
7a5a566e | 2339 | { |
70fcd359 | 2340 | u64 *pt_root = NULL; |
a71730e2 JR |
2341 | |
2342 | BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL); | |
2343 | ||
7a5a566e | 2344 | spin_lock_init(&domain->lock); |
7a5a566e JR |
2345 | domain->id = domain_id_alloc(); |
2346 | if (!domain->id) | |
2347 | return -ENOMEM; | |
2348 | INIT_LIST_HEAD(&domain->dev_list); | |
2349 | ||
a71730e2 JR |
2350 | if (mode != PAGE_MODE_NONE) { |
2351 | pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2352 | if (!pt_root) | |
2353 | return -ENOMEM; | |
2354 | } | |
2355 | ||
70fcd359 | 2356 | amd_iommu_domain_set_pgtable(domain, pt_root, mode); |
a71730e2 | 2357 | |
7a5a566e JR |
2358 | return 0; |
2359 | } | |
2360 | ||
a71730e2 | 2361 | static struct protection_domain *protection_domain_alloc(int mode) |
c156e347 JR |
2362 | { |
2363 | struct protection_domain *domain; | |
2364 | ||
2365 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2366 | if (!domain) | |
2650815f | 2367 | return NULL; |
c156e347 | 2368 | |
a71730e2 | 2369 | if (protection_domain_init(domain, mode)) |
2650815f JR |
2370 | goto out_err; |
2371 | ||
2372 | return domain; | |
2373 | ||
2374 | out_err: | |
2375 | kfree(domain); | |
2376 | ||
2377 | return NULL; | |
2378 | } | |
2379 | ||
3f4b87b9 | 2380 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2381 | { |
301441a0 JR |
2382 | struct protection_domain *domain; |
2383 | int mode = DEFAULT_PGTABLE_LEVEL; | |
2650815f | 2384 | |
301441a0 JR |
2385 | if (type == IOMMU_DOMAIN_IDENTITY) |
2386 | mode = PAGE_MODE_NONE; | |
c156e347 | 2387 | |
301441a0 JR |
2388 | domain = protection_domain_alloc(mode); |
2389 | if (!domain) | |
0bb6e243 | 2390 | return NULL; |
c156e347 | 2391 | |
301441a0 JR |
2392 | domain->domain.geometry.aperture_start = 0; |
2393 | domain->domain.geometry.aperture_end = ~0ULL; | |
2394 | domain->domain.geometry.force_aperture = true; | |
eb791aa7 | 2395 | |
e1980df3 JR |
2396 | if (type == IOMMU_DOMAIN_DMA && |
2397 | iommu_get_dma_cookie(&domain->domain) == -ENOMEM) | |
2398 | goto free_domain; | |
0ff64f80 | 2399 | |
301441a0 | 2400 | return &domain->domain; |
c156e347 | 2401 | |
301441a0 JR |
2402 | free_domain: |
2403 | protection_domain_free(domain); | |
c156e347 | 2404 | |
301441a0 | 2405 | return NULL; |
c156e347 JR |
2406 | } |
2407 | ||
3f4b87b9 | 2408 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2409 | { |
3f4b87b9 | 2410 | struct protection_domain *domain; |
98383fc3 | 2411 | |
3f4b87b9 JR |
2412 | domain = to_pdomain(dom); |
2413 | ||
98383fc3 JR |
2414 | if (domain->dev_cnt > 0) |
2415 | cleanup_domain(domain); | |
2416 | ||
2417 | BUG_ON(domain->dev_cnt != 0); | |
2418 | ||
cda7005b JR |
2419 | if (!dom) |
2420 | return; | |
98383fc3 | 2421 | |
301441a0 JR |
2422 | if (dom->type == IOMMU_DOMAIN_DMA) |
2423 | iommu_put_dma_cookie(&domain->domain); | |
52815b75 | 2424 | |
301441a0 JR |
2425 | if (domain->flags & PD_IOMMUV2_MASK) |
2426 | free_gcr3_table(domain); | |
cda7005b | 2427 | |
301441a0 | 2428 | protection_domain_free(domain); |
98383fc3 JR |
2429 | } |
2430 | ||
684f2888 JR |
2431 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2432 | struct device *dev) | |
2433 | { | |
05a0542b | 2434 | struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); |
684f2888 | 2435 | struct amd_iommu *iommu; |
7aba6cb9 | 2436 | int devid; |
684f2888 | 2437 | |
98fc5a69 | 2438 | if (!check_device(dev)) |
684f2888 JR |
2439 | return; |
2440 | ||
98fc5a69 | 2441 | devid = get_device_id(dev); |
9ee35e4c | 2442 | if (devid < 0) |
7aba6cb9 | 2443 | return; |
684f2888 | 2444 | |
657cbb6b | 2445 | if (dev_data->domain != NULL) |
15898bbc | 2446 | detach_device(dev); |
684f2888 JR |
2447 | |
2448 | iommu = amd_iommu_rlookup_table[devid]; | |
2449 | if (!iommu) | |
2450 | return; | |
2451 | ||
d98de49a SS |
2452 | #ifdef CONFIG_IRQ_REMAP |
2453 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
2454 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
2455 | dev_data->use_vapic = 0; | |
2456 | #endif | |
2457 | ||
684f2888 JR |
2458 | iommu_completion_wait(iommu); |
2459 | } | |
2460 | ||
01106066 JR |
2461 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2462 | struct device *dev) | |
2463 | { | |
3f4b87b9 | 2464 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 2465 | struct iommu_dev_data *dev_data; |
01106066 | 2466 | struct amd_iommu *iommu; |
15898bbc | 2467 | int ret; |
01106066 | 2468 | |
98fc5a69 | 2469 | if (!check_device(dev)) |
01106066 JR |
2470 | return -EINVAL; |
2471 | ||
05a0542b | 2472 | dev_data = dev_iommu_priv_get(dev); |
be62dbf5 | 2473 | dev_data->defer_attach = false; |
657cbb6b | 2474 | |
f62dda66 | 2475 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2476 | if (!iommu) |
2477 | return -EINVAL; | |
2478 | ||
657cbb6b | 2479 | if (dev_data->domain) |
15898bbc | 2480 | detach_device(dev); |
01106066 | 2481 | |
15898bbc | 2482 | ret = attach_device(dev, domain); |
01106066 | 2483 | |
d98de49a SS |
2484 | #ifdef CONFIG_IRQ_REMAP |
2485 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
2486 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
2487 | dev_data->use_vapic = 1; | |
2488 | else | |
2489 | dev_data->use_vapic = 0; | |
2490 | } | |
2491 | #endif | |
2492 | ||
01106066 JR |
2493 | iommu_completion_wait(iommu); |
2494 | ||
15898bbc | 2495 | return ret; |
01106066 JR |
2496 | } |
2497 | ||
468e2366 | 2498 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
781ca2de TM |
2499 | phys_addr_t paddr, size_t page_size, int iommu_prot, |
2500 | gfp_t gfp) | |
c6229ca6 | 2501 | { |
3f4b87b9 | 2502 | struct protection_domain *domain = to_pdomain(dom); |
eb791aa7 | 2503 | struct domain_pgtable pgtable; |
c6229ca6 JR |
2504 | int prot = 0; |
2505 | int ret; | |
2506 | ||
eb791aa7 JR |
2507 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
2508 | if (pgtable.mode == PAGE_MODE_NONE) | |
132bd68f JR |
2509 | return -EINVAL; |
2510 | ||
c6229ca6 JR |
2511 | if (iommu_prot & IOMMU_READ) |
2512 | prot |= IOMMU_PROT_IR; | |
2513 | if (iommu_prot & IOMMU_WRITE) | |
2514 | prot |= IOMMU_PROT_IW; | |
2515 | ||
3057fb93 | 2516 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp); |
5d214fe6 | 2517 | |
5cd3f2e9 TM |
2518 | domain_flush_np_cache(domain, iova, page_size); |
2519 | ||
795e74f7 | 2520 | return ret; |
c6229ca6 JR |
2521 | } |
2522 | ||
5009065d | 2523 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
56f8af5e WD |
2524 | size_t page_size, |
2525 | struct iommu_iotlb_gather *gather) | |
eb74ff6c | 2526 | { |
3f4b87b9 | 2527 | struct protection_domain *domain = to_pdomain(dom); |
eb791aa7 | 2528 | struct domain_pgtable pgtable; |
eb74ff6c | 2529 | |
eb791aa7 JR |
2530 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
2531 | if (pgtable.mode == PAGE_MODE_NONE) | |
c5611a87 | 2532 | return 0; |
132bd68f | 2533 | |
37ec8eb8 | 2534 | return iommu_unmap_page(domain, iova, page_size); |
eb74ff6c JR |
2535 | } |
2536 | ||
645c4c8d | 2537 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 2538 | dma_addr_t iova) |
645c4c8d | 2539 | { |
3f4b87b9 | 2540 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 2541 | unsigned long offset_mask, pte_pgsize; |
eb791aa7 | 2542 | struct domain_pgtable pgtable; |
f03152bb | 2543 | u64 *pte, __pte; |
645c4c8d | 2544 | |
eb791aa7 JR |
2545 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
2546 | if (pgtable.mode == PAGE_MODE_NONE) | |
132bd68f JR |
2547 | return iova; |
2548 | ||
3039ca1b | 2549 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 2550 | |
a6d41a40 | 2551 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2552 | return 0; |
2553 | ||
b24b1b63 | 2554 | offset_mask = pte_pgsize - 1; |
b3e9b515 | 2555 | __pte = __sme_clr(*pte & PM_ADDR_MASK); |
645c4c8d | 2556 | |
b24b1b63 | 2557 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
2558 | } |
2559 | ||
ab636481 | 2560 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 2561 | { |
80a506b8 JR |
2562 | switch (cap) { |
2563 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 2564 | return true; |
bdddadcb | 2565 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 2566 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
2567 | case IOMMU_CAP_NOEXEC: |
2568 | return false; | |
e84b7cc4 LB |
2569 | default: |
2570 | break; | |
80a506b8 JR |
2571 | } |
2572 | ||
ab636481 | 2573 | return false; |
dbb9fd86 SY |
2574 | } |
2575 | ||
e5b5234a EA |
2576 | static void amd_iommu_get_resv_regions(struct device *dev, |
2577 | struct list_head *head) | |
35cf248f | 2578 | { |
4397f32c | 2579 | struct iommu_resv_region *region; |
35cf248f | 2580 | struct unity_map_entry *entry; |
7aba6cb9 | 2581 | int devid; |
35cf248f JR |
2582 | |
2583 | devid = get_device_id(dev); | |
9ee35e4c | 2584 | if (devid < 0) |
7aba6cb9 | 2585 | return; |
35cf248f JR |
2586 | |
2587 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
8aafaaf2 | 2588 | int type, prot = 0; |
4397f32c | 2589 | size_t length; |
35cf248f JR |
2590 | |
2591 | if (devid < entry->devid_start || devid > entry->devid_end) | |
2592 | continue; | |
2593 | ||
8aafaaf2 | 2594 | type = IOMMU_RESV_DIRECT; |
4397f32c EA |
2595 | length = entry->address_end - entry->address_start; |
2596 | if (entry->prot & IOMMU_PROT_IR) | |
2597 | prot |= IOMMU_READ; | |
2598 | if (entry->prot & IOMMU_PROT_IW) | |
2599 | prot |= IOMMU_WRITE; | |
8aafaaf2 JR |
2600 | if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) |
2601 | /* Exclusion range */ | |
2602 | type = IOMMU_RESV_RESERVED; | |
4397f32c EA |
2603 | |
2604 | region = iommu_alloc_resv_region(entry->address_start, | |
8aafaaf2 | 2605 | length, prot, type); |
35cf248f | 2606 | if (!region) { |
5f226da1 | 2607 | dev_err(dev, "Out of memory allocating dm-regions\n"); |
35cf248f JR |
2608 | return; |
2609 | } | |
35cf248f JR |
2610 | list_add_tail(®ion->list, head); |
2611 | } | |
4397f32c EA |
2612 | |
2613 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
2614 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 2615 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
2616 | if (!region) |
2617 | return; | |
2618 | list_add_tail(®ion->list, head); | |
2619 | ||
2620 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
2621 | HT_RANGE_END - HT_RANGE_START + 1, | |
2622 | 0, IOMMU_RESV_RESERVED); | |
2623 | if (!region) | |
2624 | return; | |
2625 | list_add_tail(®ion->list, head); | |
35cf248f JR |
2626 | } |
2627 | ||
fb1b6955 JR |
2628 | bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
2629 | struct device *dev) | |
df3f7a6e | 2630 | { |
05a0542b | 2631 | struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev); |
fb1b6955 | 2632 | |
df3f7a6e BH |
2633 | return dev_data->defer_attach; |
2634 | } | |
fb1b6955 | 2635 | EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred); |
df3f7a6e | 2636 | |
eb5ecd1a SS |
2637 | static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) |
2638 | { | |
2639 | struct protection_domain *dom = to_pdomain(domain); | |
2a78f996 | 2640 | unsigned long flags; |
eb5ecd1a | 2641 | |
2a78f996 | 2642 | spin_lock_irqsave(&dom->lock, flags); |
eb5ecd1a SS |
2643 | domain_flush_tlb_pde(dom); |
2644 | domain_flush_complete(dom); | |
2a78f996 | 2645 | spin_unlock_irqrestore(&dom->lock, flags); |
eb5ecd1a SS |
2646 | } |
2647 | ||
56f8af5e WD |
2648 | static void amd_iommu_iotlb_sync(struct iommu_domain *domain, |
2649 | struct iommu_iotlb_gather *gather) | |
eb5ecd1a | 2650 | { |
56f8af5e | 2651 | amd_iommu_flush_iotlb_all(domain); |
eb5ecd1a SS |
2652 | } |
2653 | ||
bdf4a7c4 JR |
2654 | static int amd_iommu_def_domain_type(struct device *dev) |
2655 | { | |
2656 | struct iommu_dev_data *dev_data; | |
2657 | ||
05a0542b | 2658 | dev_data = dev_iommu_priv_get(dev); |
bdf4a7c4 JR |
2659 | if (!dev_data) |
2660 | return 0; | |
2661 | ||
7cad5548 JR |
2662 | /* |
2663 | * Do not identity map IOMMUv2 capable devices when memory encryption is | |
2664 | * active, because some of those devices (AMD GPUs) don't have the | |
2665 | * encryption bit in their DMA-mask and require remapping. | |
2666 | */ | |
2667 | if (!mem_encrypt_active() && dev_data->iommu_v2) | |
bdf4a7c4 JR |
2668 | return IOMMU_DOMAIN_IDENTITY; |
2669 | ||
2670 | return 0; | |
2671 | } | |
2672 | ||
b0119e87 | 2673 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 2674 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
2675 | .domain_alloc = amd_iommu_domain_alloc, |
2676 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
2677 | .attach_dev = amd_iommu_attach_device, |
2678 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2679 | .map = amd_iommu_map, |
2680 | .unmap = amd_iommu_unmap, | |
26961efe | 2681 | .iova_to_phys = amd_iommu_iova_to_phys, |
dce8d696 JR |
2682 | .probe_device = amd_iommu_probe_device, |
2683 | .release_device = amd_iommu_release_device, | |
2684 | .probe_finalize = amd_iommu_probe_finalize, | |
b097d11a | 2685 | .device_group = amd_iommu_device_group, |
be62dbf5 | 2686 | .domain_get_attr = amd_iommu_domain_get_attr, |
e5b5234a | 2687 | .get_resv_regions = amd_iommu_get_resv_regions, |
55c2564a | 2688 | .put_resv_regions = generic_iommu_put_resv_regions, |
df3f7a6e | 2689 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 2690 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
eb5ecd1a | 2691 | .flush_iotlb_all = amd_iommu_flush_iotlb_all, |
56f8af5e | 2692 | .iotlb_sync = amd_iommu_iotlb_sync, |
bdf4a7c4 | 2693 | .def_domain_type = amd_iommu_def_domain_type, |
26961efe JR |
2694 | }; |
2695 | ||
0feae533 JR |
2696 | /***************************************************************************** |
2697 | * | |
2698 | * The next functions do a basic initialization of IOMMU for pass through | |
2699 | * mode | |
2700 | * | |
2701 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2702 | * DMA-API translation. | |
2703 | * | |
2704 | *****************************************************************************/ | |
2705 | ||
72e1dcc4 JR |
2706 | /* IOMMUv2 specific functions */ |
2707 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
2708 | { | |
2709 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
2710 | } | |
2711 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
2712 | ||
2713 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
2714 | { | |
2715 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
2716 | } | |
2717 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
2718 | |
2719 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
2720 | { | |
3f4b87b9 | 2721 | struct protection_domain *domain = to_pdomain(dom); |
eb791aa7 | 2722 | struct domain_pgtable pgtable; |
132bd68f JR |
2723 | unsigned long flags; |
2724 | ||
2725 | spin_lock_irqsave(&domain->lock, flags); | |
2726 | ||
eb791aa7 JR |
2727 | /* First save pgtable configuration*/ |
2728 | amd_iommu_domain_get_pgtable(domain, &pgtable); | |
2729 | ||
70fcd359 JR |
2730 | /* Remove page-table from domain */ |
2731 | amd_iommu_domain_clr_pt_root(domain); | |
132bd68f JR |
2732 | |
2733 | /* Make changes visible to IOMMUs */ | |
2734 | update_domain(domain); | |
2735 | ||
2736 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
1226c370 | 2737 | free_pagetable(&pgtable); |
132bd68f JR |
2738 | |
2739 | spin_unlock_irqrestore(&domain->lock, flags); | |
2740 | } | |
2741 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
2742 | |
2743 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
2744 | { | |
3f4b87b9 | 2745 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
2746 | unsigned long flags; |
2747 | int levels, ret; | |
2748 | ||
2749 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
2750 | return -EINVAL; | |
2751 | ||
2752 | /* Number of GCR3 table levels required */ | |
2753 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
2754 | levels += 1; | |
2755 | ||
2756 | if (levels > amd_iommu_max_glx_val) | |
2757 | return -EINVAL; | |
2758 | ||
2759 | spin_lock_irqsave(&domain->lock, flags); | |
2760 | ||
2761 | /* | |
2762 | * Save us all sanity checks whether devices already in the | |
2763 | * domain support IOMMUv2. Just force that the domain has no | |
2764 | * devices attached when it is switched into IOMMUv2 mode. | |
2765 | */ | |
2766 | ret = -EBUSY; | |
2767 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
2768 | goto out; | |
2769 | ||
2770 | ret = -ENOMEM; | |
2771 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
2772 | if (domain->gcr3_tbl == NULL) | |
2773 | goto out; | |
2774 | ||
2775 | domain->glx = levels; | |
2776 | domain->flags |= PD_IOMMUV2_MASK; | |
52815b75 JR |
2777 | |
2778 | update_domain(domain); | |
2779 | ||
2780 | ret = 0; | |
2781 | ||
2782 | out: | |
2783 | spin_unlock_irqrestore(&domain->lock, flags); | |
2784 | ||
2785 | return ret; | |
2786 | } | |
2787 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
2788 | |
2789 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
2790 | u64 address, bool size) | |
2791 | { | |
2792 | struct iommu_dev_data *dev_data; | |
2793 | struct iommu_cmd cmd; | |
2794 | int i, ret; | |
2795 | ||
2796 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
2797 | return -EINVAL; | |
2798 | ||
2799 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
2800 | ||
2801 | /* | |
2802 | * IOMMU TLB needs to be flushed before Device TLB to | |
2803 | * prevent device TLB refill from IOMMU TLB | |
2804 | */ | |
6b9376e3 | 2805 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
2806 | if (domain->dev_iommu[i] == 0) |
2807 | continue; | |
2808 | ||
2809 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
2810 | if (ret != 0) | |
2811 | goto out; | |
2812 | } | |
2813 | ||
2814 | /* Wait until IOMMU TLB flushes are complete */ | |
2815 | domain_flush_complete(domain); | |
2816 | ||
2817 | /* Now flush device TLBs */ | |
2818 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
2819 | struct amd_iommu *iommu; | |
2820 | int qdep; | |
2821 | ||
1c1cc454 JR |
2822 | /* |
2823 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
2824 | * domain. | |
2825 | */ | |
2826 | if (!dev_data->ats.enabled) | |
2827 | continue; | |
22e266c7 JR |
2828 | |
2829 | qdep = dev_data->ats.qdep; | |
2830 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
2831 | ||
2832 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
2833 | qdep, address, size); | |
2834 | ||
2835 | ret = iommu_queue_command(iommu, &cmd); | |
2836 | if (ret != 0) | |
2837 | goto out; | |
2838 | } | |
2839 | ||
2840 | /* Wait until all device TLBs are flushed */ | |
2841 | domain_flush_complete(domain); | |
2842 | ||
2843 | ret = 0; | |
2844 | ||
2845 | out: | |
2846 | ||
2847 | return ret; | |
2848 | } | |
2849 | ||
2850 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
2851 | u64 address) | |
2852 | { | |
2853 | return __flush_pasid(domain, pasid, address, false); | |
2854 | } | |
2855 | ||
2856 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
2857 | u64 address) | |
2858 | { | |
3f4b87b9 | 2859 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
2860 | unsigned long flags; |
2861 | int ret; | |
2862 | ||
2863 | spin_lock_irqsave(&domain->lock, flags); | |
2864 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
2865 | spin_unlock_irqrestore(&domain->lock, flags); | |
2866 | ||
2867 | return ret; | |
2868 | } | |
2869 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
2870 | ||
2871 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
2872 | { | |
2873 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
2874 | true); | |
2875 | } | |
2876 | ||
2877 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
2878 | { | |
3f4b87b9 | 2879 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
2880 | unsigned long flags; |
2881 | int ret; | |
2882 | ||
2883 | spin_lock_irqsave(&domain->lock, flags); | |
2884 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
2885 | spin_unlock_irqrestore(&domain->lock, flags); | |
2886 | ||
2887 | return ret; | |
2888 | } | |
2889 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
2890 | ||
b16137b1 JR |
2891 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
2892 | { | |
2893 | int index; | |
2894 | u64 *pte; | |
2895 | ||
2896 | while (true) { | |
2897 | ||
2898 | index = (pasid >> (9 * level)) & 0x1ff; | |
2899 | pte = &root[index]; | |
2900 | ||
2901 | if (level == 0) | |
2902 | break; | |
2903 | ||
2904 | if (!(*pte & GCR3_VALID)) { | |
2905 | if (!alloc) | |
2906 | return NULL; | |
2907 | ||
2908 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
2909 | if (root == NULL) | |
2910 | return NULL; | |
2911 | ||
2543a786 | 2912 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
2913 | } |
2914 | ||
2543a786 | 2915 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
2916 | |
2917 | level -= 1; | |
2918 | } | |
2919 | ||
2920 | return pte; | |
2921 | } | |
2922 | ||
2923 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
2924 | unsigned long cr3) | |
2925 | { | |
eb791aa7 | 2926 | struct domain_pgtable pgtable; |
b16137b1 JR |
2927 | u64 *pte; |
2928 | ||
eb791aa7 JR |
2929 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
2930 | if (pgtable.mode != PAGE_MODE_NONE) | |
b16137b1 JR |
2931 | return -EINVAL; |
2932 | ||
2933 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
2934 | if (pte == NULL) | |
2935 | return -ENOMEM; | |
2936 | ||
2937 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
2938 | ||
2939 | return __amd_iommu_flush_tlb(domain, pasid); | |
2940 | } | |
2941 | ||
2942 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
2943 | { | |
eb791aa7 | 2944 | struct domain_pgtable pgtable; |
b16137b1 JR |
2945 | u64 *pte; |
2946 | ||
eb791aa7 JR |
2947 | amd_iommu_domain_get_pgtable(domain, &pgtable); |
2948 | if (pgtable.mode != PAGE_MODE_NONE) | |
b16137b1 JR |
2949 | return -EINVAL; |
2950 | ||
2951 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
2952 | if (pte == NULL) | |
2953 | return 0; | |
2954 | ||
2955 | *pte = 0; | |
2956 | ||
2957 | return __amd_iommu_flush_tlb(domain, pasid); | |
2958 | } | |
2959 | ||
2960 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
2961 | unsigned long cr3) | |
2962 | { | |
3f4b87b9 | 2963 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
2964 | unsigned long flags; |
2965 | int ret; | |
2966 | ||
2967 | spin_lock_irqsave(&domain->lock, flags); | |
2968 | ret = __set_gcr3(domain, pasid, cr3); | |
2969 | spin_unlock_irqrestore(&domain->lock, flags); | |
2970 | ||
2971 | return ret; | |
2972 | } | |
2973 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
2974 | ||
2975 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
2976 | { | |
3f4b87b9 | 2977 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
2978 | unsigned long flags; |
2979 | int ret; | |
2980 | ||
2981 | spin_lock_irqsave(&domain->lock, flags); | |
2982 | ret = __clear_gcr3(domain, pasid); | |
2983 | spin_unlock_irqrestore(&domain->lock, flags); | |
2984 | ||
2985 | return ret; | |
2986 | } | |
2987 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
2988 | |
2989 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
2990 | int status, int tag) | |
2991 | { | |
2992 | struct iommu_dev_data *dev_data; | |
2993 | struct amd_iommu *iommu; | |
2994 | struct iommu_cmd cmd; | |
2995 | ||
05a0542b | 2996 | dev_data = dev_iommu_priv_get(&pdev->dev); |
c99afa25 JR |
2997 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2998 | ||
2999 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3000 | tag, dev_data->pri_tlp); | |
3001 | ||
3002 | return iommu_queue_command(iommu, &cmd); | |
3003 | } | |
3004 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3005 | |
3006 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3007 | { | |
3f4b87b9 | 3008 | struct protection_domain *pdomain; |
05a0542b | 3009 | struct iommu_dev_data *dev_data; |
be62dbf5 | 3010 | struct device *dev = &pdev->dev; |
05a0542b | 3011 | struct iommu_domain *io_domain; |
be62dbf5 TM |
3012 | |
3013 | if (!check_device(dev)) | |
3014 | return NULL; | |
f3572db8 | 3015 | |
05a0542b JR |
3016 | dev_data = dev_iommu_priv_get(&pdev->dev); |
3017 | pdomain = dev_data->domain; | |
e1980df3 | 3018 | io_domain = iommu_get_domain_for_dev(dev); |
05a0542b JR |
3019 | |
3020 | if (pdomain == NULL && dev_data->defer_attach) { | |
3021 | dev_data->defer_attach = false; | |
be62dbf5 TM |
3022 | pdomain = to_pdomain(io_domain); |
3023 | attach_device(dev, pdomain); | |
3024 | } | |
e1980df3 | 3025 | |
be62dbf5 TM |
3026 | if (pdomain == NULL) |
3027 | return NULL; | |
f3572db8 | 3028 | |
e1980df3 | 3029 | if (io_domain->type != IOMMU_DOMAIN_DMA) |
f3572db8 JR |
3030 | return NULL; |
3031 | ||
3032 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3033 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3034 | return NULL; |
3035 | ||
3f4b87b9 | 3036 | return &pdomain->domain; |
f3572db8 JR |
3037 | } |
3038 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3039 | |
3040 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3041 | { | |
3042 | struct iommu_dev_data *dev_data; | |
3043 | ||
3044 | if (!amd_iommu_v2_supported()) | |
3045 | return; | |
3046 | ||
05a0542b | 3047 | dev_data = dev_iommu_priv_get(&pdev->dev); |
6a113ddc JR |
3048 | dev_data->errata |= (1 << erratum); |
3049 | } | |
3050 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3051 | |
3052 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3053 | struct amd_iommu_device_info *info) | |
3054 | { | |
3055 | int max_pasids; | |
3056 | int pos; | |
3057 | ||
3058 | if (pdev == NULL || info == NULL) | |
3059 | return -EINVAL; | |
3060 | ||
3061 | if (!amd_iommu_v2_supported()) | |
3062 | return -EINVAL; | |
3063 | ||
3064 | memset(info, 0, sizeof(*info)); | |
3065 | ||
7a441b21 JPB |
3066 | if (pci_ats_supported(pdev)) |
3067 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
52efdb89 JR |
3068 | |
3069 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3070 | if (pos) | |
3071 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3072 | ||
3073 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3074 | if (pos) { | |
3075 | int features; | |
3076 | ||
3077 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3078 | max_pasids = min(max_pasids, (1 << 20)); | |
3079 | ||
3080 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3081 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3082 | ||
3083 | features = pci_pasid_features(pdev); | |
3084 | if (features & PCI_PASID_CAP_EXEC) | |
3085 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3086 | if (features & PCI_PASID_CAP_PRIV) | |
3087 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3088 | } | |
3089 | ||
3090 | return 0; | |
3091 | } | |
3092 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3093 | |
3094 | #ifdef CONFIG_IRQ_REMAP | |
3095 | ||
3096 | /***************************************************************************** | |
3097 | * | |
3098 | * Interrupt Remapping Implementation | |
3099 | * | |
3100 | *****************************************************************************/ | |
3101 | ||
7c71d306 | 3102 | static struct irq_chip amd_ir_chip; |
94c793ac | 3103 | static DEFINE_SPINLOCK(iommu_table_lock); |
7c71d306 | 3104 | |
2b324506 JR |
3105 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
3106 | { | |
3107 | u64 dte; | |
3108 | ||
3109 | dte = amd_iommu_dev_table[devid].data[2]; | |
3110 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
2543a786 | 3111 | dte |= iommu_virt_to_phys(table->table); |
2b324506 JR |
3112 | dte |= DTE_IRQ_REMAP_INTCTL; |
3113 | dte |= DTE_IRQ_TABLE_LEN; | |
3114 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3115 | ||
3116 | amd_iommu_dev_table[devid].data[2] = dte; | |
3117 | } | |
3118 | ||
df42a04b SW |
3119 | static struct irq_remap_table *get_irq_table(u16 devid) |
3120 | { | |
3121 | struct irq_remap_table *table; | |
3122 | ||
3123 | if (WARN_ONCE(!amd_iommu_rlookup_table[devid], | |
3124 | "%s: no iommu for devid %x\n", __func__, devid)) | |
3125 | return NULL; | |
3126 | ||
3127 | table = irq_lookup_table[devid]; | |
3128 | if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid)) | |
3129 | return NULL; | |
3130 | ||
3131 | return table; | |
3132 | } | |
3133 | ||
993ca6e0 SAS |
3134 | static struct irq_remap_table *__alloc_irq_table(void) |
3135 | { | |
3136 | struct irq_remap_table *table; | |
3137 | ||
3138 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
3139 | if (!table) | |
3140 | return NULL; | |
3141 | ||
3142 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); | |
3143 | if (!table->table) { | |
3144 | kfree(table); | |
3145 | return NULL; | |
3146 | } | |
3147 | raw_spin_lock_init(&table->lock); | |
3148 | ||
3149 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
3150 | memset(table->table, 0, | |
3151 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3152 | else | |
3153 | memset(table->table, 0, | |
3154 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
3155 | return table; | |
3156 | } | |
3157 | ||
2fcc1e8a SAS |
3158 | static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, |
3159 | struct irq_remap_table *table) | |
3160 | { | |
3161 | irq_lookup_table[devid] = table; | |
3162 | set_dte_irq_entry(devid, table); | |
3163 | iommu_flush_dte(iommu, devid); | |
3164 | } | |
3165 | ||
3c124435 LG |
3166 | static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias, |
3167 | void *data) | |
3168 | { | |
3169 | struct irq_remap_table *table = data; | |
3170 | ||
3171 | irq_lookup_table[alias] = table; | |
3172 | set_dte_irq_entry(alias, table); | |
3173 | ||
3174 | iommu_flush_dte(amd_iommu_rlookup_table[alias], alias); | |
3175 | ||
3176 | return 0; | |
3177 | } | |
3178 | ||
3179 | static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev) | |
2b324506 JR |
3180 | { |
3181 | struct irq_remap_table *table = NULL; | |
993ca6e0 | 3182 | struct irq_remap_table *new_table = NULL; |
2b324506 JR |
3183 | struct amd_iommu *iommu; |
3184 | unsigned long flags; | |
3185 | u16 alias; | |
3186 | ||
ea6166f4 | 3187 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 JR |
3188 | |
3189 | iommu = amd_iommu_rlookup_table[devid]; | |
3190 | if (!iommu) | |
3191 | goto out_unlock; | |
3192 | ||
3193 | table = irq_lookup_table[devid]; | |
3194 | if (table) | |
09284b9c | 3195 | goto out_unlock; |
2b324506 JR |
3196 | |
3197 | alias = amd_iommu_alias_table[devid]; | |
3198 | table = irq_lookup_table[alias]; | |
3199 | if (table) { | |
2fcc1e8a | 3200 | set_remap_table_entry(iommu, devid, table); |
993ca6e0 | 3201 | goto out_wait; |
2b324506 | 3202 | } |
993ca6e0 | 3203 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 JR |
3204 | |
3205 | /* Nothing there yet, allocate new irq remapping table */ | |
993ca6e0 SAS |
3206 | new_table = __alloc_irq_table(); |
3207 | if (!new_table) | |
3208 | return NULL; | |
197887f0 | 3209 | |
993ca6e0 | 3210 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 | 3211 | |
993ca6e0 SAS |
3212 | table = irq_lookup_table[devid]; |
3213 | if (table) | |
09284b9c | 3214 | goto out_unlock; |
2b324506 | 3215 | |
993ca6e0 SAS |
3216 | table = irq_lookup_table[alias]; |
3217 | if (table) { | |
3218 | set_remap_table_entry(iommu, devid, table); | |
3219 | goto out_wait; | |
2b324506 JR |
3220 | } |
3221 | ||
993ca6e0 SAS |
3222 | table = new_table; |
3223 | new_table = NULL; | |
2b324506 | 3224 | |
3c124435 LG |
3225 | if (pdev) |
3226 | pci_for_each_dma_alias(pdev, set_remap_table_entry_alias, | |
3227 | table); | |
3228 | else | |
3229 | set_remap_table_entry(iommu, devid, table); | |
3230 | ||
2fcc1e8a SAS |
3231 | if (devid != alias) |
3232 | set_remap_table_entry(iommu, alias, table); | |
2b324506 | 3233 | |
993ca6e0 | 3234 | out_wait: |
2b324506 JR |
3235 | iommu_completion_wait(iommu); |
3236 | ||
3237 | out_unlock: | |
ea6166f4 | 3238 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 | 3239 | |
993ca6e0 SAS |
3240 | if (new_table) { |
3241 | kmem_cache_free(amd_iommu_irq_cache, new_table->table); | |
3242 | kfree(new_table); | |
3243 | } | |
2b324506 JR |
3244 | return table; |
3245 | } | |
3246 | ||
3c124435 LG |
3247 | static int alloc_irq_index(u16 devid, int count, bool align, |
3248 | struct pci_dev *pdev) | |
2b324506 JR |
3249 | { |
3250 | struct irq_remap_table *table; | |
37946d95 | 3251 | int index, c, alignment = 1; |
2b324506 | 3252 | unsigned long flags; |
77bdab46 SS |
3253 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3254 | ||
3255 | if (!iommu) | |
3256 | return -ENODEV; | |
2b324506 | 3257 | |
3c124435 | 3258 | table = alloc_irq_table(devid, pdev); |
2b324506 JR |
3259 | if (!table) |
3260 | return -ENODEV; | |
3261 | ||
37946d95 JR |
3262 | if (align) |
3263 | alignment = roundup_pow_of_two(count); | |
3264 | ||
27790398 | 3265 | raw_spin_lock_irqsave(&table->lock, flags); |
2b324506 JR |
3266 | |
3267 | /* Scan table for free entries */ | |
37946d95 | 3268 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 3269 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 3270 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 3271 | c += 1; |
37946d95 JR |
3272 | } else { |
3273 | c = 0; | |
07d1c91b | 3274 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
3275 | continue; |
3276 | } | |
2b324506 JR |
3277 | |
3278 | if (c == count) { | |
2b324506 | 3279 | for (; c != 0; --c) |
77bdab46 | 3280 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3281 | |
3282 | index -= count - 1; | |
2b324506 JR |
3283 | goto out; |
3284 | } | |
07d1c91b AW |
3285 | |
3286 | index++; | |
2b324506 JR |
3287 | } |
3288 | ||
3289 | index = -ENOSPC; | |
3290 | ||
3291 | out: | |
27790398 | 3292 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3293 | |
3294 | return index; | |
3295 | } | |
3296 | ||
b9fc6b56 SS |
3297 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3298 | struct amd_ir_data *data) | |
2b324506 | 3299 | { |
e52d58d5 | 3300 | bool ret; |
2b324506 JR |
3301 | struct irq_remap_table *table; |
3302 | struct amd_iommu *iommu; | |
3303 | unsigned long flags; | |
880ac60e | 3304 | struct irte_ga *entry; |
2b324506 JR |
3305 | |
3306 | iommu = amd_iommu_rlookup_table[devid]; | |
3307 | if (iommu == NULL) | |
3308 | return -EINVAL; | |
3309 | ||
df42a04b | 3310 | table = get_irq_table(devid); |
2b324506 JR |
3311 | if (!table) |
3312 | return -ENOMEM; | |
3313 | ||
27790398 | 3314 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e SS |
3315 | |
3316 | entry = (struct irte_ga *)table->table; | |
3317 | entry = &entry[index]; | |
e52d58d5 SS |
3318 | |
3319 | ret = cmpxchg_double(&entry->lo.val, &entry->hi.val, | |
3320 | entry->lo.val, entry->hi.val, | |
3321 | irte->lo.val, irte->hi.val); | |
3322 | /* | |
3323 | * We use cmpxchg16 to atomically update the 128-bit IRTE, | |
3324 | * and it cannot be updated by the hardware or other processors | |
3325 | * behind us, so the return value of cmpxchg16 should be the | |
3326 | * same as the old value. | |
3327 | */ | |
3328 | WARN_ON(!ret); | |
3329 | ||
b9fc6b56 SS |
3330 | if (data) |
3331 | data->ref = entry; | |
880ac60e | 3332 | |
27790398 | 3333 | raw_spin_unlock_irqrestore(&table->lock, flags); |
880ac60e SS |
3334 | |
3335 | iommu_flush_irt(iommu, devid); | |
3336 | iommu_completion_wait(iommu); | |
3337 | ||
3338 | return 0; | |
3339 | } | |
3340 | ||
3341 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3342 | { |
3343 | struct irq_remap_table *table; | |
3344 | struct amd_iommu *iommu; | |
3345 | unsigned long flags; | |
3346 | ||
3347 | iommu = amd_iommu_rlookup_table[devid]; | |
3348 | if (iommu == NULL) | |
3349 | return -EINVAL; | |
3350 | ||
df42a04b | 3351 | table = get_irq_table(devid); |
2b324506 JR |
3352 | if (!table) |
3353 | return -ENOMEM; | |
3354 | ||
27790398 | 3355 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e | 3356 | table->table[index] = irte->val; |
27790398 | 3357 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3358 | |
3359 | iommu_flush_irt(iommu, devid); | |
3360 | iommu_completion_wait(iommu); | |
3361 | ||
3362 | return 0; | |
3363 | } | |
3364 | ||
3365 | static void free_irte(u16 devid, int index) | |
3366 | { | |
3367 | struct irq_remap_table *table; | |
3368 | struct amd_iommu *iommu; | |
3369 | unsigned long flags; | |
3370 | ||
3371 | iommu = amd_iommu_rlookup_table[devid]; | |
3372 | if (iommu == NULL) | |
3373 | return; | |
3374 | ||
df42a04b | 3375 | table = get_irq_table(devid); |
2b324506 JR |
3376 | if (!table) |
3377 | return; | |
3378 | ||
27790398 | 3379 | raw_spin_lock_irqsave(&table->lock, flags); |
77bdab46 | 3380 | iommu->irte_ops->clear_allocated(table, index); |
27790398 | 3381 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3382 | |
3383 | iommu_flush_irt(iommu, devid); | |
3384 | iommu_completion_wait(iommu); | |
3385 | } | |
3386 | ||
880ac60e SS |
3387 | static void irte_prepare(void *entry, |
3388 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3389 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3390 | { |
3391 | union irte *irte = (union irte *) entry; | |
3392 | ||
3393 | irte->val = 0; | |
3394 | irte->fields.vector = vector; | |
3395 | irte->fields.int_type = delivery_mode; | |
3396 | irte->fields.destination = dest_apicid; | |
3397 | irte->fields.dm = dest_mode; | |
3398 | irte->fields.valid = 1; | |
3399 | } | |
3400 | ||
3401 | static void irte_ga_prepare(void *entry, | |
3402 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3403 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3404 | { |
3405 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3406 | ||
3407 | irte->lo.val = 0; | |
3408 | irte->hi.val = 0; | |
880ac60e SS |
3409 | irte->lo.fields_remap.int_type = delivery_mode; |
3410 | irte->lo.fields_remap.dm = dest_mode; | |
3411 | irte->hi.fields.vector = vector; | |
90fcffd9 SS |
3412 | irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); |
3413 | irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); | |
880ac60e SS |
3414 | irte->lo.fields_remap.valid = 1; |
3415 | } | |
3416 | ||
3417 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3418 | { | |
3419 | union irte *irte = (union irte *) entry; | |
3420 | ||
3421 | irte->fields.valid = 1; | |
3422 | modify_irte(devid, index, irte); | |
3423 | } | |
3424 | ||
3425 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3426 | { | |
3427 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3428 | ||
3429 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3430 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3431 | } |
3432 | ||
3433 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3434 | { | |
3435 | union irte *irte = (union irte *) entry; | |
3436 | ||
3437 | irte->fields.valid = 0; | |
3438 | modify_irte(devid, index, irte); | |
3439 | } | |
3440 | ||
3441 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3442 | { | |
3443 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3444 | ||
3445 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3446 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3447 | } |
3448 | ||
3449 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3450 | u8 vector, u32 dest_apicid) | |
3451 | { | |
3452 | union irte *irte = (union irte *) entry; | |
3453 | ||
3454 | irte->fields.vector = vector; | |
3455 | irte->fields.destination = dest_apicid; | |
3456 | modify_irte(devid, index, irte); | |
3457 | } | |
3458 | ||
3459 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3460 | u8 vector, u32 dest_apicid) | |
3461 | { | |
3462 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3463 | ||
01ee04ba | 3464 | if (!irte->lo.fields_remap.guest_mode) { |
d98de49a | 3465 | irte->hi.fields.vector = vector; |
90fcffd9 SS |
3466 | irte->lo.fields_remap.destination = |
3467 | APICID_TO_IRTE_DEST_LO(dest_apicid); | |
3468 | irte->hi.fields.destination = | |
3469 | APICID_TO_IRTE_DEST_HI(dest_apicid); | |
d98de49a SS |
3470 | modify_irte_ga(devid, index, irte, NULL); |
3471 | } | |
880ac60e SS |
3472 | } |
3473 | ||
77bdab46 | 3474 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3475 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3476 | { | |
3477 | table->table[index] = IRTE_ALLOCATED; | |
3478 | } | |
3479 | ||
3480 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3481 | { | |
3482 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3483 | struct irte_ga *irte = &ptr[index]; | |
3484 | ||
3485 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3486 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3487 | irte->hi.fields.vector = 0xff; | |
3488 | } | |
3489 | ||
3490 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3491 | { | |
3492 | union irte *ptr = (union irte *)table->table; | |
3493 | union irte *irte = &ptr[index]; | |
3494 | ||
3495 | return irte->val != 0; | |
3496 | } | |
3497 | ||
3498 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3499 | { | |
3500 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3501 | struct irte_ga *irte = &ptr[index]; | |
3502 | ||
3503 | return irte->hi.fields.vector != 0; | |
3504 | } | |
3505 | ||
3506 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3507 | { | |
3508 | table->table[index] = 0; | |
3509 | } | |
3510 | ||
3511 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3512 | { | |
3513 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3514 | struct irte_ga *irte = &ptr[index]; | |
3515 | ||
3516 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3517 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3518 | } | |
3519 | ||
7c71d306 | 3520 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3521 | { |
7c71d306 | 3522 | int devid = -1; |
5527de74 | 3523 | |
7c71d306 JL |
3524 | switch (info->type) { |
3525 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3526 | devid = get_ioapic_devid(info->ioapic_id); | |
3527 | break; | |
3528 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3529 | devid = get_hpet_devid(info->hpet_id); | |
3530 | break; | |
3531 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3532 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3533 | devid = get_device_id(&info->msi_dev->dev); | |
3534 | break; | |
3535 | default: | |
3536 | BUG_ON(1); | |
3537 | break; | |
3538 | } | |
5527de74 | 3539 | |
7c71d306 JL |
3540 | return devid; |
3541 | } | |
5527de74 | 3542 | |
7c71d306 JL |
3543 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3544 | { | |
3545 | struct amd_iommu *iommu; | |
3546 | int devid; | |
5527de74 | 3547 | |
7c71d306 JL |
3548 | if (!info) |
3549 | return NULL; | |
5527de74 | 3550 | |
7c71d306 JL |
3551 | devid = get_devid(info); |
3552 | if (devid >= 0) { | |
3553 | iommu = amd_iommu_rlookup_table[devid]; | |
3554 | if (iommu) | |
3555 | return iommu->ir_domain; | |
3556 | } | |
5527de74 | 3557 | |
7c71d306 | 3558 | return NULL; |
5527de74 JR |
3559 | } |
3560 | ||
7c71d306 | 3561 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3562 | { |
7c71d306 JL |
3563 | struct amd_iommu *iommu; |
3564 | int devid; | |
5527de74 | 3565 | |
7c71d306 JL |
3566 | if (!info) |
3567 | return NULL; | |
5527de74 | 3568 | |
7c71d306 JL |
3569 | switch (info->type) { |
3570 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3571 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3572 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 3573 | if (devid < 0) |
7aba6cb9 WZ |
3574 | return NULL; |
3575 | ||
1fb260bc DC |
3576 | iommu = amd_iommu_rlookup_table[devid]; |
3577 | if (iommu) | |
3578 | return iommu->msi_domain; | |
7c71d306 JL |
3579 | break; |
3580 | default: | |
3581 | break; | |
3582 | } | |
5527de74 | 3583 | |
7c71d306 JL |
3584 | return NULL; |
3585 | } | |
5527de74 | 3586 | |
6b474b82 | 3587 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3588 | .prepare = amd_iommu_prepare, |
3589 | .enable = amd_iommu_enable, | |
3590 | .disable = amd_iommu_disable, | |
3591 | .reenable = amd_iommu_reenable, | |
3592 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3593 | .get_ir_irq_domain = get_ir_irq_domain, |
3594 | .get_irq_domain = get_irq_domain, | |
3595 | }; | |
5527de74 | 3596 | |
7c71d306 JL |
3597 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3598 | struct irq_cfg *irq_cfg, | |
3599 | struct irq_alloc_info *info, | |
3600 | int devid, int index, int sub_handle) | |
3601 | { | |
3602 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3603 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 3604 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
3605 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3606 | ||
3607 | if (!iommu) | |
3608 | return; | |
5527de74 | 3609 | |
7c71d306 JL |
3610 | data->irq_2_irte.devid = devid; |
3611 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
3612 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
3613 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 3614 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
3615 | |
3616 | switch (info->type) { | |
3617 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3618 | /* Setup IOAPIC entry */ | |
3619 | entry = info->ioapic_entry; | |
3620 | info->ioapic_entry = NULL; | |
3621 | memset(entry, 0, sizeof(*entry)); | |
3622 | entry->vector = index; | |
3623 | entry->mask = 0; | |
3624 | entry->trigger = info->ioapic_trigger; | |
3625 | entry->polarity = info->ioapic_polarity; | |
3626 | /* Mask level triggered irqs. */ | |
3627 | if (info->ioapic_trigger) | |
3628 | entry->mask = 1; | |
3629 | break; | |
5527de74 | 3630 | |
7c71d306 JL |
3631 | case X86_IRQ_ALLOC_TYPE_HPET: |
3632 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3633 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3634 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3635 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3636 | msg->data = irte_info->index; | |
3637 | break; | |
5527de74 | 3638 | |
7c71d306 JL |
3639 | default: |
3640 | BUG_ON(1); | |
3641 | break; | |
3642 | } | |
5527de74 JR |
3643 | } |
3644 | ||
880ac60e SS |
3645 | struct amd_irte_ops irte_32_ops = { |
3646 | .prepare = irte_prepare, | |
3647 | .activate = irte_activate, | |
3648 | .deactivate = irte_deactivate, | |
3649 | .set_affinity = irte_set_affinity, | |
3650 | .set_allocated = irte_set_allocated, | |
3651 | .is_allocated = irte_is_allocated, | |
3652 | .clear_allocated = irte_clear_allocated, | |
3653 | }; | |
3654 | ||
3655 | struct amd_irte_ops irte_128_ops = { | |
3656 | .prepare = irte_ga_prepare, | |
3657 | .activate = irte_ga_activate, | |
3658 | .deactivate = irte_ga_deactivate, | |
3659 | .set_affinity = irte_ga_set_affinity, | |
3660 | .set_allocated = irte_ga_set_allocated, | |
3661 | .is_allocated = irte_ga_is_allocated, | |
3662 | .clear_allocated = irte_ga_clear_allocated, | |
3663 | }; | |
3664 | ||
7c71d306 JL |
3665 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3666 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3667 | { |
7c71d306 JL |
3668 | struct irq_alloc_info *info = arg; |
3669 | struct irq_data *irq_data; | |
77bdab46 | 3670 | struct amd_ir_data *data = NULL; |
5527de74 | 3671 | struct irq_cfg *cfg; |
7c71d306 | 3672 | int i, ret, devid; |
29d049be | 3673 | int index; |
5527de74 | 3674 | |
7c71d306 JL |
3675 | if (!info) |
3676 | return -EINVAL; | |
3677 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
3678 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
3679 | return -EINVAL; |
3680 | ||
7c71d306 JL |
3681 | /* |
3682 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3683 | * to support multiple MSI interrupts. | |
3684 | */ | |
3685 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
3686 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 3687 | |
7c71d306 JL |
3688 | devid = get_devid(info); |
3689 | if (devid < 0) | |
3690 | return -EINVAL; | |
5527de74 | 3691 | |
7c71d306 JL |
3692 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3693 | if (ret < 0) | |
3694 | return ret; | |
0b4d48cb | 3695 | |
7c71d306 | 3696 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
fde65dd3 SAS |
3697 | struct irq_remap_table *table; |
3698 | struct amd_iommu *iommu; | |
3699 | ||
3c124435 | 3700 | table = alloc_irq_table(devid, NULL); |
fde65dd3 SAS |
3701 | if (table) { |
3702 | if (!table->min_index) { | |
3703 | /* | |
3704 | * Keep the first 32 indexes free for IOAPIC | |
3705 | * interrupts. | |
3706 | */ | |
3707 | table->min_index = 32; | |
3708 | iommu = amd_iommu_rlookup_table[devid]; | |
3709 | for (i = 0; i < 32; ++i) | |
3710 | iommu->irte_ops->set_allocated(table, i); | |
3711 | } | |
3712 | WARN_ON(table->min_index != 32); | |
7c71d306 | 3713 | index = info->ioapic_pin; |
fde65dd3 | 3714 | } else { |
29d049be | 3715 | index = -ENOMEM; |
fde65dd3 | 3716 | } |
3c124435 LG |
3717 | } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI || |
3718 | info->type == X86_IRQ_ALLOC_TYPE_MSIX) { | |
53b9ec3f JR |
3719 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
3720 | ||
3c124435 LG |
3721 | index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev); |
3722 | } else { | |
3723 | index = alloc_irq_index(devid, nr_irqs, false, NULL); | |
7c71d306 | 3724 | } |
3c124435 | 3725 | |
7c71d306 JL |
3726 | if (index < 0) { |
3727 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 3728 | ret = index; |
7c71d306 JL |
3729 | goto out_free_parent; |
3730 | } | |
0b4d48cb | 3731 | |
7c71d306 JL |
3732 | for (i = 0; i < nr_irqs; i++) { |
3733 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3734 | cfg = irqd_cfg(irq_data); | |
3735 | if (!irq_data || !cfg) { | |
3736 | ret = -EINVAL; | |
3737 | goto out_free_data; | |
3738 | } | |
0b4d48cb | 3739 | |
a130e69f JR |
3740 | ret = -ENOMEM; |
3741 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3742 | if (!data) | |
3743 | goto out_free_data; | |
3744 | ||
77bdab46 SS |
3745 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3746 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
3747 | else | |
3748 | data->entry = kzalloc(sizeof(struct irte_ga), | |
3749 | GFP_KERNEL); | |
3750 | if (!data->entry) { | |
3751 | kfree(data); | |
3752 | goto out_free_data; | |
3753 | } | |
3754 | ||
7c71d306 JL |
3755 | irq_data->hwirq = (devid << 16) + i; |
3756 | irq_data->chip_data = data; | |
3757 | irq_data->chip = &amd_ir_chip; | |
3758 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
3759 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
3760 | } | |
a130e69f | 3761 | |
7c71d306 | 3762 | return 0; |
0b4d48cb | 3763 | |
7c71d306 JL |
3764 | out_free_data: |
3765 | for (i--; i >= 0; i--) { | |
3766 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3767 | if (irq_data) | |
3768 | kfree(irq_data->chip_data); | |
3769 | } | |
3770 | for (i = 0; i < nr_irqs; i++) | |
3771 | free_irte(devid, index + i); | |
3772 | out_free_parent: | |
3773 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3774 | return ret; | |
0b4d48cb JR |
3775 | } |
3776 | ||
7c71d306 JL |
3777 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
3778 | unsigned int nr_irqs) | |
0b4d48cb | 3779 | { |
7c71d306 JL |
3780 | struct irq_2_irte *irte_info; |
3781 | struct irq_data *irq_data; | |
3782 | struct amd_ir_data *data; | |
3783 | int i; | |
0b4d48cb | 3784 | |
7c71d306 JL |
3785 | for (i = 0; i < nr_irqs; i++) { |
3786 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3787 | if (irq_data && irq_data->chip_data) { | |
3788 | data = irq_data->chip_data; | |
3789 | irte_info = &data->irq_2_irte; | |
3790 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 3791 | kfree(data->entry); |
7c71d306 JL |
3792 | kfree(data); |
3793 | } | |
3794 | } | |
3795 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3796 | } | |
0b4d48cb | 3797 | |
5ba204a1 TG |
3798 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
3799 | struct amd_ir_data *ir_data, | |
3800 | struct irq_2_irte *irte_info, | |
3801 | struct irq_cfg *cfg); | |
3802 | ||
72491643 | 3803 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 3804 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
3805 | { |
3806 | struct amd_ir_data *data = irq_data->chip_data; | |
3807 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 3808 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
5ba204a1 | 3809 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 3810 | |
5ba204a1 TG |
3811 | if (!iommu) |
3812 | return 0; | |
3813 | ||
3814 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
3815 | irte_info->index); | |
3816 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 3817 | return 0; |
0b4d48cb JR |
3818 | } |
3819 | ||
7c71d306 JL |
3820 | static void irq_remapping_deactivate(struct irq_domain *domain, |
3821 | struct irq_data *irq_data) | |
0b4d48cb | 3822 | { |
7c71d306 JL |
3823 | struct amd_ir_data *data = irq_data->chip_data; |
3824 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 3825 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 3826 | |
77bdab46 SS |
3827 | if (iommu) |
3828 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
3829 | irte_info->index); | |
7c71d306 | 3830 | } |
0b4d48cb | 3831 | |
e2f9d45f | 3832 | static const struct irq_domain_ops amd_ir_domain_ops = { |
7c71d306 JL |
3833 | .alloc = irq_remapping_alloc, |
3834 | .free = irq_remapping_free, | |
3835 | .activate = irq_remapping_activate, | |
3836 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 3837 | }; |
0b4d48cb | 3838 | |
b9c6ff94 SS |
3839 | int amd_iommu_activate_guest_mode(void *data) |
3840 | { | |
3841 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
3842 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
e97685ab | 3843 | u64 valid; |
b9c6ff94 SS |
3844 | |
3845 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
3846 | !entry || entry->lo.fields_vapic.guest_mode) | |
3847 | return 0; | |
3848 | ||
e97685ab SS |
3849 | valid = entry->lo.fields_vapic.valid; |
3850 | ||
b9c6ff94 SS |
3851 | entry->lo.val = 0; |
3852 | entry->hi.val = 0; | |
3853 | ||
e97685ab | 3854 | entry->lo.fields_vapic.valid = valid; |
b9c6ff94 SS |
3855 | entry->lo.fields_vapic.guest_mode = 1; |
3856 | entry->lo.fields_vapic.ga_log_intr = 1; | |
3857 | entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr; | |
3858 | entry->hi.fields.vector = ir_data->ga_vector; | |
3859 | entry->lo.fields_vapic.ga_tag = ir_data->ga_tag; | |
3860 | ||
3861 | return modify_irte_ga(ir_data->irq_2_irte.devid, | |
730ad0ed | 3862 | ir_data->irq_2_irte.index, entry, ir_data); |
b9c6ff94 SS |
3863 | } |
3864 | EXPORT_SYMBOL(amd_iommu_activate_guest_mode); | |
3865 | ||
3866 | int amd_iommu_deactivate_guest_mode(void *data) | |
3867 | { | |
3868 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
3869 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
3870 | struct irq_cfg *cfg = ir_data->cfg; | |
14c4acc5 | 3871 | u64 valid; |
b9c6ff94 SS |
3872 | |
3873 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
3874 | !entry || !entry->lo.fields_vapic.guest_mode) | |
3875 | return 0; | |
3876 | ||
14c4acc5 JM |
3877 | valid = entry->lo.fields_remap.valid; |
3878 | ||
b9c6ff94 SS |
3879 | entry->lo.val = 0; |
3880 | entry->hi.val = 0; | |
3881 | ||
26e495f3 | 3882 | entry->lo.fields_remap.valid = valid; |
b9c6ff94 SS |
3883 | entry->lo.fields_remap.dm = apic->irq_dest_mode; |
3884 | entry->lo.fields_remap.int_type = apic->irq_delivery_mode; | |
3885 | entry->hi.fields.vector = cfg->vector; | |
3886 | entry->lo.fields_remap.destination = | |
3887 | APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); | |
3888 | entry->hi.fields.destination = | |
3889 | APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); | |
3890 | ||
3891 | return modify_irte_ga(ir_data->irq_2_irte.devid, | |
730ad0ed | 3892 | ir_data->irq_2_irte.index, entry, ir_data); |
b9c6ff94 SS |
3893 | } |
3894 | EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); | |
3895 | ||
b9fc6b56 SS |
3896 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
3897 | { | |
b9c6ff94 | 3898 | int ret; |
b9fc6b56 SS |
3899 | struct amd_iommu *iommu; |
3900 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
3901 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
3902 | struct amd_ir_data *ir_data = data->chip_data; | |
b9fc6b56 | 3903 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; |
d98de49a SS |
3904 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
3905 | ||
3906 | /* Note: | |
3907 | * This device has never been set up for guest mode. | |
3908 | * we should not modify the IRTE | |
3909 | */ | |
3910 | if (!dev_data || !dev_data->use_vapic) | |
3911 | return 0; | |
b9fc6b56 | 3912 | |
b9c6ff94 | 3913 | ir_data->cfg = irqd_cfg(data); |
b9fc6b56 SS |
3914 | pi_data->ir_data = ir_data; |
3915 | ||
3916 | /* Note: | |
3917 | * SVM tries to set up for VAPIC mode, but we are in | |
3918 | * legacy mode. So, we force legacy mode instead. | |
3919 | */ | |
3920 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
101fa037 | 3921 | pr_debug("%s: Fall back to using intr legacy remap\n", |
b9fc6b56 SS |
3922 | __func__); |
3923 | pi_data->is_guest_mode = false; | |
3924 | } | |
3925 | ||
3926 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
3927 | if (iommu == NULL) | |
3928 | return -EINVAL; | |
3929 | ||
3930 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
3931 | if (pi_data->is_guest_mode) { | |
b9c6ff94 SS |
3932 | ir_data->ga_root_ptr = (pi_data->base >> 12); |
3933 | ir_data->ga_vector = vcpu_pi_info->vector; | |
3934 | ir_data->ga_tag = pi_data->ga_tag; | |
3935 | ret = amd_iommu_activate_guest_mode(ir_data); | |
3936 | if (!ret) | |
3937 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
b9fc6b56 | 3938 | } else { |
b9c6ff94 | 3939 | ret = amd_iommu_deactivate_guest_mode(ir_data); |
b9fc6b56 SS |
3940 | |
3941 | /* | |
3942 | * This communicates the ga_tag back to the caller | |
3943 | * so that it can do all the necessary clean up. | |
3944 | */ | |
b9c6ff94 SS |
3945 | if (!ret) |
3946 | ir_data->cached_ga_tag = 0; | |
b9fc6b56 SS |
3947 | } |
3948 | ||
b9c6ff94 | 3949 | return ret; |
b9fc6b56 SS |
3950 | } |
3951 | ||
5ba204a1 TG |
3952 | |
3953 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
3954 | struct amd_ir_data *ir_data, | |
3955 | struct irq_2_irte *irte_info, | |
3956 | struct irq_cfg *cfg) | |
3957 | { | |
3958 | ||
3959 | /* | |
3960 | * Atomically updates the IRTE with the new destination, vector | |
3961 | * and flushes the interrupt entry cache. | |
3962 | */ | |
3963 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
3964 | irte_info->index, cfg->vector, | |
3965 | cfg->dest_apicid); | |
3966 | } | |
3967 | ||
7c71d306 JL |
3968 | static int amd_ir_set_affinity(struct irq_data *data, |
3969 | const struct cpumask *mask, bool force) | |
3970 | { | |
3971 | struct amd_ir_data *ir_data = data->chip_data; | |
3972 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
3973 | struct irq_cfg *cfg = irqd_cfg(data); | |
3974 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 3975 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 3976 | int ret; |
0b4d48cb | 3977 | |
77bdab46 SS |
3978 | if (!iommu) |
3979 | return -ENODEV; | |
3980 | ||
7c71d306 JL |
3981 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
3982 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
3983 | return ret; | |
0b4d48cb | 3984 | |
5ba204a1 | 3985 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
3986 | /* |
3987 | * After this point, all the interrupts will start arriving | |
3988 | * at the new destination. So, time to cleanup the previous | |
3989 | * vector allocation. | |
3990 | */ | |
c6c2002b | 3991 | send_cleanup_vector(cfg); |
7c71d306 JL |
3992 | |
3993 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
3994 | } |
3995 | ||
7c71d306 | 3996 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 3997 | { |
7c71d306 | 3998 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 3999 | |
7c71d306 JL |
4000 | *msg = ir_data->msi_entry; |
4001 | } | |
d976195c | 4002 | |
7c71d306 | 4003 | static struct irq_chip amd_ir_chip = { |
290be194 | 4004 | .name = "AMD-IR", |
8a2b7d14 | 4005 | .irq_ack = apic_ack_irq, |
290be194 TG |
4006 | .irq_set_affinity = amd_ir_set_affinity, |
4007 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4008 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 4009 | }; |
d976195c | 4010 | |
7c71d306 JL |
4011 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4012 | { | |
3e49a818 TG |
4013 | struct fwnode_handle *fn; |
4014 | ||
4015 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4016 | if (!fn) | |
4017 | return -ENOMEM; | |
4018 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
e3beca48 TG |
4019 | if (!iommu->ir_domain) { |
4020 | irq_domain_free_fwnode(fn); | |
7c71d306 | 4021 | return -ENOMEM; |
e3beca48 | 4022 | } |
d976195c | 4023 | |
7c71d306 | 4024 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
4025 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
4026 | "AMD-IR-MSI", | |
4027 | iommu->index); | |
d976195c JR |
4028 | return 0; |
4029 | } | |
8dbea3fd SS |
4030 | |
4031 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4032 | { | |
4033 | unsigned long flags; | |
4034 | struct amd_iommu *iommu; | |
4fde541c | 4035 | struct irq_remap_table *table; |
8dbea3fd SS |
4036 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; |
4037 | int devid = ir_data->irq_2_irte.devid; | |
4038 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4039 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4040 | ||
4041 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4042 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4043 | return 0; | |
4044 | ||
4045 | iommu = amd_iommu_rlookup_table[devid]; | |
4046 | if (!iommu) | |
4047 | return -ENODEV; | |
4048 | ||
4fde541c SAS |
4049 | table = get_irq_table(devid); |
4050 | if (!table) | |
8dbea3fd SS |
4051 | return -ENODEV; |
4052 | ||
4fde541c | 4053 | raw_spin_lock_irqsave(&table->lock, flags); |
8dbea3fd SS |
4054 | |
4055 | if (ref->lo.fields_vapic.guest_mode) { | |
90fcffd9 SS |
4056 | if (cpu >= 0) { |
4057 | ref->lo.fields_vapic.destination = | |
4058 | APICID_TO_IRTE_DEST_LO(cpu); | |
4059 | ref->hi.fields.destination = | |
4060 | APICID_TO_IRTE_DEST_HI(cpu); | |
4061 | } | |
8dbea3fd SS |
4062 | ref->lo.fields_vapic.is_run = is_run; |
4063 | barrier(); | |
4064 | } | |
4065 | ||
4fde541c | 4066 | raw_spin_unlock_irqrestore(&table->lock, flags); |
8dbea3fd SS |
4067 | |
4068 | iommu_flush_irt(iommu, devid); | |
4069 | iommu_completion_wait(iommu); | |
4070 | return 0; | |
4071 | } | |
4072 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4073 | #endif |