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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
2b324506 JR |
37 | #include <asm/irq_remapping.h> |
38 | #include <asm/io_apic.h> | |
39 | #include <asm/apic.h> | |
40 | #include <asm/hw_irq.h> | |
17f5b569 | 41 | #include <asm/msidef.h> |
b6c02715 | 42 | #include <asm/proto.h> |
46a7fa27 | 43 | #include <asm/iommu.h> |
1d9b16d1 | 44 | #include <asm/gart.h> |
27c2127a | 45 | #include <asm/dma.h> |
403f81d8 JR |
46 | |
47 | #include "amd_iommu_proto.h" | |
48 | #include "amd_iommu_types.h" | |
6b474b82 | 49 | #include "irq_remapping.h" |
b6c02715 JR |
50 | |
51 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
52 | ||
815b33fd | 53 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 54 | |
aa3de9c0 OBC |
55 | /* |
56 | * This bitmap is used to advertise the page sizes our hardware support | |
57 | * to the IOMMU core, which will then use this information to split | |
58 | * physically contiguous memory regions it is mapping into page sizes | |
59 | * that we support. | |
60 | * | |
954e3dd8 | 61 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 62 | */ |
954e3dd8 | 63 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 64 | |
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
6efed63b JR |
75 | LIST_HEAD(ioapic_map); |
76 | LIST_HEAD(hpet_map); | |
77 | ||
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
82 | static struct protection_domain *pt_domain; | |
83 | ||
b22f6434 | 84 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 85 | |
72e1dcc4 | 86 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 87 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 88 | |
ac1534a5 JR |
89 | static struct dma_map_ops amd_iommu_dma_ops; |
90 | ||
50917e26 JR |
91 | /* |
92 | * This struct contains device specific data for the IOMMU | |
93 | */ | |
94 | struct iommu_dev_data { | |
95 | struct list_head list; /* For domain->dev_list */ | |
96 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 97 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
98 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
99 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
100 | u16 devid; /* PCI Device ID */ |
101 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
102 | bool passthrough; /* Default for device is pt_domain */ | |
103 | struct { | |
104 | bool enabled; | |
105 | int qdep; | |
106 | } ats; /* ATS state */ | |
107 | bool pri_tlp; /* PASID TLB required for | |
108 | PPR completions */ | |
109 | u32 errata; /* Bitmap for errata to apply */ | |
110 | }; | |
111 | ||
431b2a20 JR |
112 | /* |
113 | * general struct to manage commands send to an IOMMU | |
114 | */ | |
d6449536 | 115 | struct iommu_cmd { |
b6c02715 JR |
116 | u32 data[4]; |
117 | }; | |
118 | ||
05152a04 JR |
119 | struct kmem_cache *amd_iommu_irq_cache; |
120 | ||
04bfdd84 | 121 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 122 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 123 | |
15898bbc JR |
124 | /**************************************************************************** |
125 | * | |
126 | * Helper functions | |
127 | * | |
128 | ****************************************************************************/ | |
129 | ||
3f4b87b9 JR |
130 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
131 | { | |
132 | return container_of(dom, struct protection_domain, domain); | |
133 | } | |
134 | ||
f62dda66 | 135 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
136 | { |
137 | struct iommu_dev_data *dev_data; | |
138 | unsigned long flags; | |
139 | ||
140 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
141 | if (!dev_data) | |
142 | return NULL; | |
143 | ||
f251e187 JR |
144 | INIT_LIST_HEAD(&dev_data->alias_list); |
145 | ||
f62dda66 | 146 | dev_data->devid = devid; |
8fa5f802 JR |
147 | |
148 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
149 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
150 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
151 | ||
152 | return dev_data; | |
153 | } | |
154 | ||
155 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
156 | { | |
157 | unsigned long flags; | |
158 | ||
159 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
160 | list_del(&dev_data->dev_data_list); | |
161 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
162 | ||
163 | kfree(dev_data); | |
164 | } | |
165 | ||
3b03bb74 JR |
166 | static struct iommu_dev_data *search_dev_data(u16 devid) |
167 | { | |
168 | struct iommu_dev_data *dev_data; | |
169 | unsigned long flags; | |
170 | ||
171 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
172 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
173 | if (dev_data->devid == devid) | |
174 | goto out_unlock; | |
175 | } | |
176 | ||
177 | dev_data = NULL; | |
178 | ||
179 | out_unlock: | |
180 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
181 | ||
182 | return dev_data; | |
183 | } | |
184 | ||
185 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
186 | { | |
187 | struct iommu_dev_data *dev_data; | |
188 | ||
189 | dev_data = search_dev_data(devid); | |
190 | ||
191 | if (dev_data == NULL) | |
192 | dev_data = alloc_dev_data(devid); | |
193 | ||
194 | return dev_data; | |
195 | } | |
196 | ||
15898bbc JR |
197 | static inline u16 get_device_id(struct device *dev) |
198 | { | |
199 | struct pci_dev *pdev = to_pci_dev(dev); | |
200 | ||
6f2729ba | 201 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
202 | } |
203 | ||
657cbb6b JR |
204 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
205 | { | |
206 | return dev->archdata.iommu; | |
207 | } | |
208 | ||
5abcdba4 JR |
209 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
210 | { | |
211 | static const int caps[] = { | |
212 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
213 | PCI_EXT_CAP_ID_PRI, |
214 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
215 | }; |
216 | int i, pos; | |
217 | ||
218 | for (i = 0; i < 3; ++i) { | |
219 | pos = pci_find_ext_capability(pdev, caps[i]); | |
220 | if (pos == 0) | |
221 | return false; | |
222 | } | |
223 | ||
224 | return true; | |
225 | } | |
226 | ||
6a113ddc JR |
227 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
228 | { | |
229 | struct iommu_dev_data *dev_data; | |
230 | ||
231 | dev_data = get_dev_data(&pdev->dev); | |
232 | ||
233 | return dev_data->errata & (1 << erratum) ? true : false; | |
234 | } | |
235 | ||
71c70984 JR |
236 | /* |
237 | * In this function the list of preallocated protection domains is traversed to | |
238 | * find the domain for a specific device | |
239 | */ | |
240 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
241 | { | |
242 | struct dma_ops_domain *entry, *ret = NULL; | |
243 | unsigned long flags; | |
244 | u16 alias = amd_iommu_alias_table[devid]; | |
245 | ||
246 | if (list_empty(&iommu_pd_list)) | |
247 | return NULL; | |
248 | ||
249 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
250 | ||
251 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
252 | if (entry->target_dev == devid || | |
253 | entry->target_dev == alias) { | |
254 | ret = entry; | |
255 | break; | |
256 | } | |
257 | } | |
258 | ||
259 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
260 | ||
261 | return ret; | |
262 | } | |
263 | ||
98fc5a69 JR |
264 | /* |
265 | * This function checks if the driver got a valid device from the caller to | |
266 | * avoid dereferencing invalid pointers. | |
267 | */ | |
268 | static bool check_device(struct device *dev) | |
269 | { | |
270 | u16 devid; | |
271 | ||
272 | if (!dev || !dev->dma_mask) | |
273 | return false; | |
274 | ||
b82a2272 YW |
275 | /* No PCI device */ |
276 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
277 | return false; |
278 | ||
279 | devid = get_device_id(dev); | |
280 | ||
281 | /* Out of our scope? */ | |
282 | if (devid > amd_iommu_last_bdf) | |
283 | return false; | |
284 | ||
285 | if (amd_iommu_rlookup_table[devid] == NULL) | |
286 | return false; | |
287 | ||
288 | return true; | |
289 | } | |
290 | ||
25b11ce2 | 291 | static void init_iommu_group(struct device *dev) |
2851db21 | 292 | { |
2851db21 | 293 | struct iommu_group *group; |
2851db21 | 294 | |
65d5352f | 295 | group = iommu_group_get_for_dev(dev); |
25b11ce2 AW |
296 | if (!IS_ERR(group)) |
297 | iommu_group_put(group); | |
eb9c9527 AW |
298 | } |
299 | ||
c1931090 AW |
300 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
301 | { | |
302 | *(u16 *)data = alias; | |
303 | return 0; | |
304 | } | |
305 | ||
306 | static u16 get_alias(struct device *dev) | |
307 | { | |
308 | struct pci_dev *pdev = to_pci_dev(dev); | |
309 | u16 devid, ivrs_alias, pci_alias; | |
310 | ||
311 | devid = get_device_id(dev); | |
312 | ivrs_alias = amd_iommu_alias_table[devid]; | |
313 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
314 | ||
315 | if (ivrs_alias == pci_alias) | |
316 | return ivrs_alias; | |
317 | ||
318 | /* | |
319 | * DMA alias showdown | |
320 | * | |
321 | * The IVRS is fairly reliable in telling us about aliases, but it | |
322 | * can't know about every screwy device. If we don't have an IVRS | |
323 | * reported alias, use the PCI reported alias. In that case we may | |
324 | * still need to initialize the rlookup and dev_table entries if the | |
325 | * alias is to a non-existent device. | |
326 | */ | |
327 | if (ivrs_alias == devid) { | |
328 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
329 | amd_iommu_rlookup_table[pci_alias] = | |
330 | amd_iommu_rlookup_table[devid]; | |
331 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
332 | amd_iommu_dev_table[devid].data, | |
333 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
334 | } | |
335 | ||
336 | return pci_alias; | |
337 | } | |
338 | ||
339 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
340 | "for device %s[%04x:%04x], kernel reported alias " | |
341 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
342 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
343 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
344 | PCI_FUNC(pci_alias)); | |
345 | ||
346 | /* | |
347 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
348 | * bus, then the IVRS table may know about a quirk that we don't. | |
349 | */ | |
350 | if (pci_alias == devid && | |
351 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
352 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
353 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
354 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
355 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
356 | dev_name(dev)); | |
357 | } | |
358 | ||
359 | return ivrs_alias; | |
360 | } | |
361 | ||
eb9c9527 AW |
362 | static int iommu_init_device(struct device *dev) |
363 | { | |
364 | struct pci_dev *pdev = to_pci_dev(dev); | |
365 | struct iommu_dev_data *dev_data; | |
366 | u16 alias; | |
eb9c9527 AW |
367 | |
368 | if (dev->archdata.iommu) | |
369 | return 0; | |
370 | ||
371 | dev_data = find_dev_data(get_device_id(dev)); | |
372 | if (!dev_data) | |
373 | return -ENOMEM; | |
374 | ||
c1931090 AW |
375 | alias = get_alias(dev); |
376 | ||
eb9c9527 AW |
377 | if (alias != dev_data->devid) { |
378 | struct iommu_dev_data *alias_data; | |
379 | ||
380 | alias_data = find_dev_data(alias); | |
381 | if (alias_data == NULL) { | |
382 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
383 | dev_name(dev)); | |
384 | free_dev_data(dev_data); | |
385 | return -ENOTSUPP; | |
386 | } | |
387 | dev_data->alias_data = alias_data; | |
eb9c9527 | 388 | |
f251e187 JR |
389 | /* Add device to the alias_list */ |
390 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 391 | } |
9dcd6130 | 392 | |
5abcdba4 JR |
393 | if (pci_iommuv2_capable(pdev)) { |
394 | struct amd_iommu *iommu; | |
395 | ||
396 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
397 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
398 | } | |
399 | ||
657cbb6b JR |
400 | dev->archdata.iommu = dev_data; |
401 | ||
066f2e98 AW |
402 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
403 | dev); | |
404 | ||
657cbb6b JR |
405 | return 0; |
406 | } | |
407 | ||
26018874 JR |
408 | static void iommu_ignore_device(struct device *dev) |
409 | { | |
410 | u16 devid, alias; | |
411 | ||
412 | devid = get_device_id(dev); | |
413 | alias = amd_iommu_alias_table[devid]; | |
414 | ||
415 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
416 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
417 | ||
418 | amd_iommu_rlookup_table[devid] = NULL; | |
419 | amd_iommu_rlookup_table[alias] = NULL; | |
420 | } | |
421 | ||
657cbb6b JR |
422 | static void iommu_uninit_device(struct device *dev) |
423 | { | |
c1931090 AW |
424 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
425 | ||
426 | if (!dev_data) | |
427 | return; | |
428 | ||
066f2e98 AW |
429 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
430 | dev); | |
431 | ||
9dcd6130 AW |
432 | iommu_group_remove_device(dev); |
433 | ||
c1931090 AW |
434 | /* Unlink from alias, it may change if another device is re-plugged */ |
435 | dev_data->alias_data = NULL; | |
436 | ||
8fa5f802 | 437 | /* |
c1931090 AW |
438 | * We keep dev_data around for unplugged devices and reuse it when the |
439 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 440 | */ |
657cbb6b | 441 | } |
b7cc9554 JR |
442 | |
443 | void __init amd_iommu_uninit_devices(void) | |
444 | { | |
8fa5f802 | 445 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
446 | struct pci_dev *pdev = NULL; |
447 | ||
448 | for_each_pci_dev(pdev) { | |
449 | ||
450 | if (!check_device(&pdev->dev)) | |
451 | continue; | |
452 | ||
453 | iommu_uninit_device(&pdev->dev); | |
454 | } | |
8fa5f802 JR |
455 | |
456 | /* Free all of our dev_data structures */ | |
457 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
458 | free_dev_data(dev_data); | |
b7cc9554 JR |
459 | } |
460 | ||
461 | int __init amd_iommu_init_devices(void) | |
462 | { | |
463 | struct pci_dev *pdev = NULL; | |
464 | int ret = 0; | |
465 | ||
466 | for_each_pci_dev(pdev) { | |
467 | ||
468 | if (!check_device(&pdev->dev)) | |
469 | continue; | |
470 | ||
471 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
472 | if (ret == -ENOTSUPP) |
473 | iommu_ignore_device(&pdev->dev); | |
474 | else if (ret) | |
b7cc9554 JR |
475 | goto out_free; |
476 | } | |
477 | ||
25b11ce2 AW |
478 | /* |
479 | * Initialize IOMMU groups only after iommu_init_device() has | |
480 | * had a chance to populate any IVRS defined aliases. | |
481 | */ | |
482 | for_each_pci_dev(pdev) { | |
483 | if (check_device(&pdev->dev)) | |
484 | init_iommu_group(&pdev->dev); | |
485 | } | |
486 | ||
b7cc9554 JR |
487 | return 0; |
488 | ||
489 | out_free: | |
490 | ||
491 | amd_iommu_uninit_devices(); | |
492 | ||
493 | return ret; | |
494 | } | |
7f26508b JR |
495 | #ifdef CONFIG_AMD_IOMMU_STATS |
496 | ||
497 | /* | |
498 | * Initialization code for statistics collection | |
499 | */ | |
500 | ||
da49f6df | 501 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 502 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 503 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 504 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 505 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 506 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 507 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 508 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 509 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 510 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 511 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 512 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
513 | DECLARE_STATS_COUNTER(complete_ppr); |
514 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
515 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
516 | DECLARE_STATS_COUNTER(pri_requests); | |
517 | ||
7f26508b | 518 | static struct dentry *stats_dir; |
7f26508b JR |
519 | static struct dentry *de_fflush; |
520 | ||
521 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
522 | { | |
523 | if (stats_dir == NULL) | |
524 | return; | |
525 | ||
526 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
527 | &cnt->value); | |
528 | } | |
529 | ||
530 | static void amd_iommu_stats_init(void) | |
531 | { | |
532 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
533 | if (stats_dir == NULL) | |
534 | return; | |
535 | ||
7f26508b | 536 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 537 | &amd_iommu_unmap_flush); |
da49f6df JR |
538 | |
539 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 540 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 541 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 542 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 543 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 544 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 545 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 546 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 547 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 548 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 549 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 550 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
551 | amd_iommu_stats_add(&complete_ppr); |
552 | amd_iommu_stats_add(&invalidate_iotlb); | |
553 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
554 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
555 | } |
556 | ||
557 | #endif | |
558 | ||
a80dc3e0 JR |
559 | /**************************************************************************** |
560 | * | |
561 | * Interrupt handling functions | |
562 | * | |
563 | ****************************************************************************/ | |
564 | ||
e3e59876 JR |
565 | static void dump_dte_entry(u16 devid) |
566 | { | |
567 | int i; | |
568 | ||
ee6c2868 JR |
569 | for (i = 0; i < 4; ++i) |
570 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
571 | amd_iommu_dev_table[devid].data[i]); |
572 | } | |
573 | ||
945b4ac4 JR |
574 | static void dump_command(unsigned long phys_addr) |
575 | { | |
576 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
577 | int i; | |
578 | ||
579 | for (i = 0; i < 4; ++i) | |
580 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
581 | } | |
582 | ||
a345b23b | 583 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 584 | { |
3d06fca8 JR |
585 | int type, devid, domid, flags; |
586 | volatile u32 *event = __evt; | |
587 | int count = 0; | |
588 | u64 address; | |
589 | ||
590 | retry: | |
591 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
592 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
593 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
594 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
595 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
596 | ||
597 | if (type == 0) { | |
598 | /* Did we hit the erratum? */ | |
599 | if (++count == LOOP_TIMEOUT) { | |
600 | pr_err("AMD-Vi: No event written to event log\n"); | |
601 | return; | |
602 | } | |
603 | udelay(1); | |
604 | goto retry; | |
605 | } | |
90008ee4 | 606 | |
4c6f40d4 | 607 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
608 | |
609 | switch (type) { | |
610 | case EVENT_TYPE_ILL_DEV: | |
611 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
612 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 613 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 614 | address, flags); |
e3e59876 | 615 | dump_dte_entry(devid); |
90008ee4 JR |
616 | break; |
617 | case EVENT_TYPE_IO_FAULT: | |
618 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
619 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 620 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
621 | domid, address, flags); |
622 | break; | |
623 | case EVENT_TYPE_DEV_TAB_ERR: | |
624 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
625 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 626 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
627 | address, flags); |
628 | break; | |
629 | case EVENT_TYPE_PAGE_TAB_ERR: | |
630 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
631 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 632 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
633 | domid, address, flags); |
634 | break; | |
635 | case EVENT_TYPE_ILL_CMD: | |
636 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 637 | dump_command(address); |
90008ee4 JR |
638 | break; |
639 | case EVENT_TYPE_CMD_HARD_ERR: | |
640 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
641 | "flags=0x%04x]\n", address, flags); | |
642 | break; | |
643 | case EVENT_TYPE_IOTLB_INV_TO: | |
644 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
645 | "address=0x%016llx]\n", | |
c5081cd7 | 646 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
647 | address); |
648 | break; | |
649 | case EVENT_TYPE_INV_DEV_REQ: | |
650 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
651 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 652 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
653 | address, flags); |
654 | break; | |
655 | default: | |
656 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
657 | } | |
3d06fca8 JR |
658 | |
659 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
660 | } |
661 | ||
662 | static void iommu_poll_events(struct amd_iommu *iommu) | |
663 | { | |
664 | u32 head, tail; | |
90008ee4 JR |
665 | |
666 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
667 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
668 | ||
669 | while (head != tail) { | |
a345b23b | 670 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
671 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
672 | } | |
673 | ||
674 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
675 | } |
676 | ||
eee53537 | 677 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
678 | { |
679 | struct amd_iommu_fault fault; | |
72e1dcc4 | 680 | |
399be2f5 JR |
681 | INC_STATS_COUNTER(pri_requests); |
682 | ||
72e1dcc4 JR |
683 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
684 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
685 | return; | |
686 | } | |
687 | ||
688 | fault.address = raw[1]; | |
689 | fault.pasid = PPR_PASID(raw[0]); | |
690 | fault.device_id = PPR_DEVID(raw[0]); | |
691 | fault.tag = PPR_TAG(raw[0]); | |
692 | fault.flags = PPR_FLAGS(raw[0]); | |
693 | ||
72e1dcc4 JR |
694 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
695 | } | |
696 | ||
697 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
698 | { | |
72e1dcc4 JR |
699 | u32 head, tail; |
700 | ||
701 | if (iommu->ppr_log == NULL) | |
702 | return; | |
703 | ||
72e1dcc4 JR |
704 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
705 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
706 | ||
707 | while (head != tail) { | |
eee53537 JR |
708 | volatile u64 *raw; |
709 | u64 entry[2]; | |
710 | int i; | |
711 | ||
712 | raw = (u64 *)(iommu->ppr_log + head); | |
713 | ||
714 | /* | |
715 | * Hardware bug: Interrupt may arrive before the entry is | |
716 | * written to memory. If this happens we need to wait for the | |
717 | * entry to arrive. | |
718 | */ | |
719 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
720 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
721 | break; | |
722 | udelay(1); | |
723 | } | |
72e1dcc4 | 724 | |
eee53537 JR |
725 | /* Avoid memcpy function-call overhead */ |
726 | entry[0] = raw[0]; | |
727 | entry[1] = raw[1]; | |
72e1dcc4 | 728 | |
eee53537 JR |
729 | /* |
730 | * To detect the hardware bug we need to clear the entry | |
731 | * back to zero. | |
732 | */ | |
733 | raw[0] = raw[1] = 0UL; | |
734 | ||
735 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
736 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
737 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 738 | |
eee53537 JR |
739 | /* Handle PPR entry */ |
740 | iommu_handle_ppr_entry(iommu, entry); | |
741 | ||
eee53537 JR |
742 | /* Refresh ring-buffer information */ |
743 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
744 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
745 | } | |
72e1dcc4 JR |
746 | } |
747 | ||
72fe00f0 | 748 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 749 | { |
3f398bc7 SS |
750 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
751 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 752 | |
3f398bc7 SS |
753 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
754 | /* Enable EVT and PPR interrupts again */ | |
755 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
756 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 757 | |
3f398bc7 SS |
758 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
759 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
760 | iommu_poll_events(iommu); | |
761 | } | |
90008ee4 | 762 | |
3f398bc7 SS |
763 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
764 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
765 | iommu_poll_ppr_log(iommu); | |
766 | } | |
90008ee4 | 767 | |
3f398bc7 SS |
768 | /* |
769 | * Hardware bug: ERBT1312 | |
770 | * When re-enabling interrupt (by writing 1 | |
771 | * to clear the bit), the hardware might also try to set | |
772 | * the interrupt bit in the event status register. | |
773 | * In this scenario, the bit will be set, and disable | |
774 | * subsequent interrupts. | |
775 | * | |
776 | * Workaround: The IOMMU driver should read back the | |
777 | * status register and check if the interrupt bits are cleared. | |
778 | * If not, driver will need to go through the interrupt handler | |
779 | * again and re-clear the bits | |
780 | */ | |
781 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
782 | } | |
90008ee4 | 783 | return IRQ_HANDLED; |
a80dc3e0 JR |
784 | } |
785 | ||
72fe00f0 JR |
786 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
787 | { | |
788 | return IRQ_WAKE_THREAD; | |
789 | } | |
790 | ||
431b2a20 JR |
791 | /**************************************************************************** |
792 | * | |
793 | * IOMMU command queuing functions | |
794 | * | |
795 | ****************************************************************************/ | |
796 | ||
ac0ea6e9 JR |
797 | static int wait_on_sem(volatile u64 *sem) |
798 | { | |
799 | int i = 0; | |
800 | ||
801 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
802 | udelay(1); | |
803 | i += 1; | |
804 | } | |
805 | ||
806 | if (i == LOOP_TIMEOUT) { | |
807 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
808 | return -EIO; | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
815 | struct iommu_cmd *cmd, | |
816 | u32 tail) | |
a19ae1ec | 817 | { |
a19ae1ec JR |
818 | u8 *target; |
819 | ||
8a7c5ef3 | 820 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
821 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
822 | ||
823 | /* Copy command to buffer */ | |
824 | memcpy(target, cmd, sizeof(*cmd)); | |
825 | ||
826 | /* Tell the IOMMU about it */ | |
a19ae1ec | 827 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 828 | } |
a19ae1ec | 829 | |
815b33fd | 830 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 831 | { |
815b33fd JR |
832 | WARN_ON(address & 0x7ULL); |
833 | ||
ded46737 | 834 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
835 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
836 | cmd->data[1] = upper_32_bits(__pa(address)); | |
837 | cmd->data[2] = 1; | |
ded46737 JR |
838 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
839 | } | |
840 | ||
94fe79e2 JR |
841 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
842 | { | |
843 | memset(cmd, 0, sizeof(*cmd)); | |
844 | cmd->data[0] = devid; | |
845 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
846 | } | |
847 | ||
11b6402c JR |
848 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
849 | size_t size, u16 domid, int pde) | |
850 | { | |
851 | u64 pages; | |
ae0cbbb1 | 852 | bool s; |
11b6402c JR |
853 | |
854 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 855 | s = false; |
11b6402c JR |
856 | |
857 | if (pages > 1) { | |
858 | /* | |
859 | * If we have to flush more than one page, flush all | |
860 | * TLB entries for this domain | |
861 | */ | |
862 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 863 | s = true; |
11b6402c JR |
864 | } |
865 | ||
866 | address &= PAGE_MASK; | |
867 | ||
868 | memset(cmd, 0, sizeof(*cmd)); | |
869 | cmd->data[1] |= domid; | |
870 | cmd->data[2] = lower_32_bits(address); | |
871 | cmd->data[3] = upper_32_bits(address); | |
872 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
873 | if (s) /* size bit - we flush more than one 4kb page */ | |
874 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 875 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
876 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
877 | } | |
878 | ||
cb41ed85 JR |
879 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
880 | u64 address, size_t size) | |
881 | { | |
882 | u64 pages; | |
ae0cbbb1 | 883 | bool s; |
cb41ed85 JR |
884 | |
885 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 886 | s = false; |
cb41ed85 JR |
887 | |
888 | if (pages > 1) { | |
889 | /* | |
890 | * If we have to flush more than one page, flush all | |
891 | * TLB entries for this domain | |
892 | */ | |
893 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 894 | s = true; |
cb41ed85 JR |
895 | } |
896 | ||
897 | address &= PAGE_MASK; | |
898 | ||
899 | memset(cmd, 0, sizeof(*cmd)); | |
900 | cmd->data[0] = devid; | |
901 | cmd->data[0] |= (qdep & 0xff) << 24; | |
902 | cmd->data[1] = devid; | |
903 | cmd->data[2] = lower_32_bits(address); | |
904 | cmd->data[3] = upper_32_bits(address); | |
905 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
906 | if (s) | |
907 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
908 | } | |
909 | ||
22e266c7 JR |
910 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
911 | u64 address, bool size) | |
912 | { | |
913 | memset(cmd, 0, sizeof(*cmd)); | |
914 | ||
915 | address &= ~(0xfffULL); | |
916 | ||
a919a018 | 917 | cmd->data[0] = pasid; |
22e266c7 JR |
918 | cmd->data[1] = domid; |
919 | cmd->data[2] = lower_32_bits(address); | |
920 | cmd->data[3] = upper_32_bits(address); | |
921 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
922 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
923 | if (size) | |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
925 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
926 | } | |
927 | ||
928 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
929 | int qdep, u64 address, bool size) | |
930 | { | |
931 | memset(cmd, 0, sizeof(*cmd)); | |
932 | ||
933 | address &= ~(0xfffULL); | |
934 | ||
935 | cmd->data[0] = devid; | |
e8d2d82d | 936 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
937 | cmd->data[0] |= (qdep & 0xff) << 24; |
938 | cmd->data[1] = devid; | |
e8d2d82d | 939 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
940 | cmd->data[2] = lower_32_bits(address); |
941 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
942 | cmd->data[3] = upper_32_bits(address); | |
943 | if (size) | |
944 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
945 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
946 | } | |
947 | ||
c99afa25 JR |
948 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
949 | int status, int tag, bool gn) | |
950 | { | |
951 | memset(cmd, 0, sizeof(*cmd)); | |
952 | ||
953 | cmd->data[0] = devid; | |
954 | if (gn) { | |
a919a018 | 955 | cmd->data[1] = pasid; |
c99afa25 JR |
956 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
957 | } | |
958 | cmd->data[3] = tag & 0x1ff; | |
959 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
960 | ||
961 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
962 | } | |
963 | ||
58fc7f14 JR |
964 | static void build_inv_all(struct iommu_cmd *cmd) |
965 | { | |
966 | memset(cmd, 0, sizeof(*cmd)); | |
967 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
968 | } |
969 | ||
7ef2798d JR |
970 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
971 | { | |
972 | memset(cmd, 0, sizeof(*cmd)); | |
973 | cmd->data[0] = devid; | |
974 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
975 | } | |
976 | ||
431b2a20 | 977 | /* |
431b2a20 | 978 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 979 | * hardware about the new command. |
431b2a20 | 980 | */ |
f1ca1512 JR |
981 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
982 | struct iommu_cmd *cmd, | |
983 | bool sync) | |
a19ae1ec | 984 | { |
ac0ea6e9 | 985 | u32 left, tail, head, next_tail; |
a19ae1ec | 986 | unsigned long flags; |
a19ae1ec | 987 | |
549c90dc | 988 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
989 | |
990 | again: | |
a19ae1ec | 991 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 992 | |
ac0ea6e9 JR |
993 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
994 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
995 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
996 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 997 | |
ac0ea6e9 JR |
998 | if (left <= 2) { |
999 | struct iommu_cmd sync_cmd; | |
1000 | volatile u64 sem = 0; | |
1001 | int ret; | |
8d201968 | 1002 | |
ac0ea6e9 JR |
1003 | build_completion_wait(&sync_cmd, (u64)&sem); |
1004 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1005 | |
ac0ea6e9 JR |
1006 | spin_unlock_irqrestore(&iommu->lock, flags); |
1007 | ||
1008 | if ((ret = wait_on_sem(&sem)) != 0) | |
1009 | return ret; | |
1010 | ||
1011 | goto again; | |
8d201968 JR |
1012 | } |
1013 | ||
ac0ea6e9 JR |
1014 | copy_cmd_to_buffer(iommu, cmd, tail); |
1015 | ||
1016 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1017 | iommu->need_sync = sync; |
ac0ea6e9 | 1018 | |
a19ae1ec | 1019 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1020 | |
815b33fd | 1021 | return 0; |
8d201968 JR |
1022 | } |
1023 | ||
f1ca1512 JR |
1024 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1025 | { | |
1026 | return iommu_queue_command_sync(iommu, cmd, true); | |
1027 | } | |
1028 | ||
8d201968 JR |
1029 | /* |
1030 | * This function queues a completion wait command into the command | |
1031 | * buffer of an IOMMU | |
1032 | */ | |
a19ae1ec | 1033 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1034 | { |
1035 | struct iommu_cmd cmd; | |
815b33fd | 1036 | volatile u64 sem = 0; |
ac0ea6e9 | 1037 | int ret; |
8d201968 | 1038 | |
09ee17eb | 1039 | if (!iommu->need_sync) |
815b33fd | 1040 | return 0; |
09ee17eb | 1041 | |
815b33fd | 1042 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1043 | |
f1ca1512 | 1044 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1045 | if (ret) |
815b33fd | 1046 | return ret; |
8d201968 | 1047 | |
ac0ea6e9 | 1048 | return wait_on_sem(&sem); |
8d201968 JR |
1049 | } |
1050 | ||
d8c13085 | 1051 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1052 | { |
d8c13085 | 1053 | struct iommu_cmd cmd; |
a19ae1ec | 1054 | |
d8c13085 | 1055 | build_inv_dte(&cmd, devid); |
7e4f88da | 1056 | |
d8c13085 JR |
1057 | return iommu_queue_command(iommu, &cmd); |
1058 | } | |
09ee17eb | 1059 | |
7d0c5cc5 JR |
1060 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1061 | { | |
1062 | u32 devid; | |
09ee17eb | 1063 | |
7d0c5cc5 JR |
1064 | for (devid = 0; devid <= 0xffff; ++devid) |
1065 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1066 | |
7d0c5cc5 JR |
1067 | iommu_completion_wait(iommu); |
1068 | } | |
84df8175 | 1069 | |
7d0c5cc5 JR |
1070 | /* |
1071 | * This function uses heavy locking and may disable irqs for some time. But | |
1072 | * this is no issue because it is only called during resume. | |
1073 | */ | |
1074 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1075 | { | |
1076 | u32 dom_id; | |
a19ae1ec | 1077 | |
7d0c5cc5 JR |
1078 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1079 | struct iommu_cmd cmd; | |
1080 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1081 | dom_id, 1); | |
1082 | iommu_queue_command(iommu, &cmd); | |
1083 | } | |
8eed9833 | 1084 | |
7d0c5cc5 | 1085 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1086 | } |
1087 | ||
58fc7f14 | 1088 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1089 | { |
58fc7f14 | 1090 | struct iommu_cmd cmd; |
0518a3a4 | 1091 | |
58fc7f14 | 1092 | build_inv_all(&cmd); |
0518a3a4 | 1093 | |
58fc7f14 JR |
1094 | iommu_queue_command(iommu, &cmd); |
1095 | iommu_completion_wait(iommu); | |
1096 | } | |
1097 | ||
7ef2798d JR |
1098 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1099 | { | |
1100 | struct iommu_cmd cmd; | |
1101 | ||
1102 | build_inv_irt(&cmd, devid); | |
1103 | ||
1104 | iommu_queue_command(iommu, &cmd); | |
1105 | } | |
1106 | ||
1107 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1108 | { | |
1109 | u32 devid; | |
1110 | ||
1111 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1112 | iommu_flush_irt(iommu, devid); | |
1113 | ||
1114 | iommu_completion_wait(iommu); | |
1115 | } | |
1116 | ||
7d0c5cc5 JR |
1117 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1118 | { | |
58fc7f14 JR |
1119 | if (iommu_feature(iommu, FEATURE_IA)) { |
1120 | iommu_flush_all(iommu); | |
1121 | } else { | |
1122 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1123 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1124 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1125 | } |
1126 | } | |
1127 | ||
431b2a20 | 1128 | /* |
cb41ed85 | 1129 | * Command send function for flushing on-device TLB |
431b2a20 | 1130 | */ |
6c542047 JR |
1131 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1132 | u64 address, size_t size) | |
3fa43655 JR |
1133 | { |
1134 | struct amd_iommu *iommu; | |
b00d3bcf | 1135 | struct iommu_cmd cmd; |
cb41ed85 | 1136 | int qdep; |
3fa43655 | 1137 | |
ea61cddb JR |
1138 | qdep = dev_data->ats.qdep; |
1139 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1140 | |
ea61cddb | 1141 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1142 | |
1143 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1144 | } |
1145 | ||
431b2a20 | 1146 | /* |
431b2a20 | 1147 | * Command send function for invalidating a device table entry |
431b2a20 | 1148 | */ |
6c542047 | 1149 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1150 | { |
3fa43655 | 1151 | struct amd_iommu *iommu; |
ee2fa743 | 1152 | int ret; |
a19ae1ec | 1153 | |
6c542047 | 1154 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1155 | |
f62dda66 | 1156 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1157 | if (ret) |
1158 | return ret; | |
1159 | ||
ea61cddb | 1160 | if (dev_data->ats.enabled) |
6c542047 | 1161 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1162 | |
ee2fa743 | 1163 | return ret; |
a19ae1ec JR |
1164 | } |
1165 | ||
431b2a20 JR |
1166 | /* |
1167 | * TLB invalidation function which is called from the mapping functions. | |
1168 | * It invalidates a single PTE if the range to flush is within a single | |
1169 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1170 | */ | |
17b124bf JR |
1171 | static void __domain_flush_pages(struct protection_domain *domain, |
1172 | u64 address, size_t size, int pde) | |
a19ae1ec | 1173 | { |
cb41ed85 | 1174 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1175 | struct iommu_cmd cmd; |
1176 | int ret = 0, i; | |
a19ae1ec | 1177 | |
11b6402c | 1178 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1179 | |
6de8ad9b JR |
1180 | for (i = 0; i < amd_iommus_present; ++i) { |
1181 | if (!domain->dev_iommu[i]) | |
1182 | continue; | |
1183 | ||
1184 | /* | |
1185 | * Devices of this domain are behind this IOMMU | |
1186 | * We need a TLB flush | |
1187 | */ | |
11b6402c | 1188 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1189 | } |
1190 | ||
cb41ed85 | 1191 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1192 | |
ea61cddb | 1193 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1194 | continue; |
1195 | ||
6c542047 | 1196 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1197 | } |
1198 | ||
11b6402c | 1199 | WARN_ON(ret); |
6de8ad9b JR |
1200 | } |
1201 | ||
17b124bf JR |
1202 | static void domain_flush_pages(struct protection_domain *domain, |
1203 | u64 address, size_t size) | |
6de8ad9b | 1204 | { |
17b124bf | 1205 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1206 | } |
b6c02715 | 1207 | |
1c655773 | 1208 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1209 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1210 | { |
17b124bf | 1211 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1212 | } |
1213 | ||
42a49f96 | 1214 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1215 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1216 | { |
17b124bf | 1217 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1218 | } |
1219 | ||
17b124bf | 1220 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1221 | { |
17b124bf | 1222 | int i; |
18811f55 | 1223 | |
17b124bf JR |
1224 | for (i = 0; i < amd_iommus_present; ++i) { |
1225 | if (!domain->dev_iommu[i]) | |
1226 | continue; | |
bfd1be18 | 1227 | |
17b124bf JR |
1228 | /* |
1229 | * Devices of this domain are behind this IOMMU | |
1230 | * We need to wait for completion of all commands. | |
1231 | */ | |
1232 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1233 | } |
e394d72a JR |
1234 | } |
1235 | ||
b00d3bcf | 1236 | |
09b42804 | 1237 | /* |
b00d3bcf | 1238 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1239 | */ |
17b124bf | 1240 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1241 | { |
b00d3bcf | 1242 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1243 | |
b00d3bcf | 1244 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1245 | device_flush_dte(dev_data); |
a345b23b JR |
1246 | } |
1247 | ||
431b2a20 JR |
1248 | /**************************************************************************** |
1249 | * | |
1250 | * The functions below are used the create the page table mappings for | |
1251 | * unity mapped regions. | |
1252 | * | |
1253 | ****************************************************************************/ | |
1254 | ||
308973d3 JR |
1255 | /* |
1256 | * This function is used to add another level to an IO page table. Adding | |
1257 | * another level increases the size of the address space by 9 bits to a size up | |
1258 | * to 64 bits. | |
1259 | */ | |
1260 | static bool increase_address_space(struct protection_domain *domain, | |
1261 | gfp_t gfp) | |
1262 | { | |
1263 | u64 *pte; | |
1264 | ||
1265 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1266 | /* address space already 64 bit large */ | |
1267 | return false; | |
1268 | ||
1269 | pte = (void *)get_zeroed_page(gfp); | |
1270 | if (!pte) | |
1271 | return false; | |
1272 | ||
1273 | *pte = PM_LEVEL_PDE(domain->mode, | |
1274 | virt_to_phys(domain->pt_root)); | |
1275 | domain->pt_root = pte; | |
1276 | domain->mode += 1; | |
1277 | domain->updated = true; | |
1278 | ||
1279 | return true; | |
1280 | } | |
1281 | ||
1282 | static u64 *alloc_pte(struct protection_domain *domain, | |
1283 | unsigned long address, | |
cbb9d729 | 1284 | unsigned long page_size, |
308973d3 JR |
1285 | u64 **pte_page, |
1286 | gfp_t gfp) | |
1287 | { | |
cbb9d729 | 1288 | int level, end_lvl; |
308973d3 | 1289 | u64 *pte, *page; |
cbb9d729 JR |
1290 | |
1291 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1292 | |
1293 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1294 | increase_address_space(domain, gfp); | |
1295 | ||
cbb9d729 JR |
1296 | level = domain->mode - 1; |
1297 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1298 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1299 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1300 | |
1301 | while (level > end_lvl) { | |
1302 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1303 | page = (u64 *)get_zeroed_page(gfp); | |
1304 | if (!page) | |
1305 | return NULL; | |
1306 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1307 | } | |
1308 | ||
cbb9d729 JR |
1309 | /* No level skipping support yet */ |
1310 | if (PM_PTE_LEVEL(*pte) != level) | |
1311 | return NULL; | |
1312 | ||
308973d3 JR |
1313 | level -= 1; |
1314 | ||
1315 | pte = IOMMU_PTE_PAGE(*pte); | |
1316 | ||
1317 | if (pte_page && level == end_lvl) | |
1318 | *pte_page = pte; | |
1319 | ||
1320 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1321 | } | |
1322 | ||
1323 | return pte; | |
1324 | } | |
1325 | ||
1326 | /* | |
1327 | * This function checks if there is a PTE for a given dma address. If | |
1328 | * there is one, it returns the pointer to it. | |
1329 | */ | |
3039ca1b JR |
1330 | static u64 *fetch_pte(struct protection_domain *domain, |
1331 | unsigned long address, | |
1332 | unsigned long *page_size) | |
308973d3 JR |
1333 | { |
1334 | int level; | |
1335 | u64 *pte; | |
1336 | ||
24cd7723 JR |
1337 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1338 | return NULL; | |
1339 | ||
3039ca1b JR |
1340 | level = domain->mode - 1; |
1341 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1342 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1343 | |
24cd7723 JR |
1344 | while (level > 0) { |
1345 | ||
1346 | /* Not Present */ | |
308973d3 JR |
1347 | if (!IOMMU_PTE_PRESENT(*pte)) |
1348 | return NULL; | |
1349 | ||
24cd7723 | 1350 | /* Large PTE */ |
3039ca1b JR |
1351 | if (PM_PTE_LEVEL(*pte) == 7 || |
1352 | PM_PTE_LEVEL(*pte) == 0) | |
1353 | break; | |
24cd7723 JR |
1354 | |
1355 | /* No level skipping support yet */ | |
1356 | if (PM_PTE_LEVEL(*pte) != level) | |
1357 | return NULL; | |
1358 | ||
308973d3 JR |
1359 | level -= 1; |
1360 | ||
24cd7723 | 1361 | /* Walk to the next level */ |
3039ca1b JR |
1362 | pte = IOMMU_PTE_PAGE(*pte); |
1363 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1364 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1365 | } | |
1366 | ||
1367 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1368 | unsigned long pte_mask; | |
1369 | ||
1370 | /* | |
1371 | * If we have a series of large PTEs, make | |
1372 | * sure to return a pointer to the first one. | |
1373 | */ | |
1374 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1375 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1376 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1377 | } |
1378 | ||
1379 | return pte; | |
1380 | } | |
1381 | ||
431b2a20 JR |
1382 | /* |
1383 | * Generic mapping functions. It maps a physical address into a DMA | |
1384 | * address space. It allocates the page table pages if necessary. | |
1385 | * In the future it can be extended to a generic mapping function | |
1386 | * supporting all features of AMD IOMMU page tables like level skipping | |
1387 | * and full 64 bit address spaces. | |
1388 | */ | |
38e817fe JR |
1389 | static int iommu_map_page(struct protection_domain *dom, |
1390 | unsigned long bus_addr, | |
1391 | unsigned long phys_addr, | |
abdc5eb3 | 1392 | int prot, |
cbb9d729 | 1393 | unsigned long page_size) |
bd0e5211 | 1394 | { |
8bda3092 | 1395 | u64 __pte, *pte; |
cbb9d729 | 1396 | int i, count; |
abdc5eb3 | 1397 | |
d4b03664 JR |
1398 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1399 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1400 | ||
bad1cac2 | 1401 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1402 | return -EINVAL; |
1403 | ||
d4b03664 JR |
1404 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1405 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1406 | |
63eaa75e ML |
1407 | if (!pte) |
1408 | return -ENOMEM; | |
1409 | ||
cbb9d729 JR |
1410 | for (i = 0; i < count; ++i) |
1411 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1412 | return -EBUSY; | |
bd0e5211 | 1413 | |
d4b03664 | 1414 | if (count > 1) { |
cbb9d729 JR |
1415 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1416 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1417 | } else | |
1418 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1419 | |
bd0e5211 JR |
1420 | if (prot & IOMMU_PROT_IR) |
1421 | __pte |= IOMMU_PTE_IR; | |
1422 | if (prot & IOMMU_PROT_IW) | |
1423 | __pte |= IOMMU_PTE_IW; | |
1424 | ||
cbb9d729 JR |
1425 | for (i = 0; i < count; ++i) |
1426 | pte[i] = __pte; | |
bd0e5211 | 1427 | |
04bfdd84 JR |
1428 | update_domain(dom); |
1429 | ||
bd0e5211 JR |
1430 | return 0; |
1431 | } | |
1432 | ||
24cd7723 JR |
1433 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1434 | unsigned long bus_addr, | |
1435 | unsigned long page_size) | |
eb74ff6c | 1436 | { |
71b390e9 JR |
1437 | unsigned long long unmapped; |
1438 | unsigned long unmap_size; | |
24cd7723 JR |
1439 | u64 *pte; |
1440 | ||
1441 | BUG_ON(!is_power_of_2(page_size)); | |
1442 | ||
1443 | unmapped = 0; | |
eb74ff6c | 1444 | |
24cd7723 JR |
1445 | while (unmapped < page_size) { |
1446 | ||
71b390e9 JR |
1447 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1448 | ||
1449 | if (pte) { | |
1450 | int i, count; | |
1451 | ||
1452 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1453 | for (i = 0; i < count; i++) |
1454 | pte[i] = 0ULL; | |
1455 | } | |
1456 | ||
1457 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1458 | unmapped += unmap_size; | |
1459 | } | |
1460 | ||
60d0ca3c | 1461 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1462 | |
24cd7723 | 1463 | return unmapped; |
eb74ff6c | 1464 | } |
eb74ff6c | 1465 | |
431b2a20 JR |
1466 | /* |
1467 | * This function checks if a specific unity mapping entry is needed for | |
1468 | * this specific IOMMU. | |
1469 | */ | |
bd0e5211 JR |
1470 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1471 | struct unity_map_entry *entry) | |
1472 | { | |
1473 | u16 bdf, i; | |
1474 | ||
1475 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1476 | bdf = amd_iommu_alias_table[i]; | |
1477 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1478 | return 1; | |
1479 | } | |
1480 | ||
1481 | return 0; | |
1482 | } | |
1483 | ||
431b2a20 JR |
1484 | /* |
1485 | * This function actually applies the mapping to the page table of the | |
1486 | * dma_ops domain. | |
1487 | */ | |
bd0e5211 JR |
1488 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1489 | struct unity_map_entry *e) | |
1490 | { | |
1491 | u64 addr; | |
1492 | int ret; | |
1493 | ||
1494 | for (addr = e->address_start; addr < e->address_end; | |
1495 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1496 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1497 | PAGE_SIZE); |
bd0e5211 JR |
1498 | if (ret) |
1499 | return ret; | |
1500 | /* | |
1501 | * if unity mapping is in aperture range mark the page | |
1502 | * as allocated in the aperture | |
1503 | */ | |
1504 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1505 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1506 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1507 | } |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
171e7b37 JR |
1512 | /* |
1513 | * Init the unity mappings for a specific IOMMU in the system | |
1514 | * | |
1515 | * Basically iterates over all unity mapping entries and applies them to | |
1516 | * the default domain DMA of that IOMMU if necessary. | |
1517 | */ | |
1518 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1519 | { | |
1520 | struct unity_map_entry *entry; | |
1521 | int ret; | |
1522 | ||
1523 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1524 | if (!iommu_for_unity_map(iommu, entry)) | |
1525 | continue; | |
1526 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1527 | if (ret) | |
1528 | return ret; | |
1529 | } | |
1530 | ||
1531 | return 0; | |
1532 | } | |
1533 | ||
431b2a20 JR |
1534 | /* |
1535 | * Inits the unity mappings required for a specific device | |
1536 | */ | |
bd0e5211 JR |
1537 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1538 | u16 devid) | |
1539 | { | |
1540 | struct unity_map_entry *e; | |
1541 | int ret; | |
1542 | ||
1543 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1544 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1545 | continue; | |
1546 | ret = dma_ops_unity_map(dma_dom, e); | |
1547 | if (ret) | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
431b2a20 JR |
1554 | /**************************************************************************** |
1555 | * | |
1556 | * The next functions belong to the address allocator for the dma_ops | |
1557 | * interface functions. They work like the allocators in the other IOMMU | |
1558 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1559 | * the aperture. Maybe it could be enhanced in the future to a more | |
1560 | * efficient allocator. | |
1561 | * | |
1562 | ****************************************************************************/ | |
d3086444 | 1563 | |
431b2a20 | 1564 | /* |
384de729 | 1565 | * The address allocator core functions. |
431b2a20 JR |
1566 | * |
1567 | * called with domain->lock held | |
1568 | */ | |
384de729 | 1569 | |
171e7b37 JR |
1570 | /* |
1571 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1572 | * ranges. | |
1573 | */ | |
1574 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1575 | unsigned long start_page, | |
1576 | unsigned int pages) | |
1577 | { | |
1578 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1579 | ||
1580 | if (start_page + pages > last_page) | |
1581 | pages = last_page - start_page; | |
1582 | ||
1583 | for (i = start_page; i < start_page + pages; ++i) { | |
1584 | int index = i / APERTURE_RANGE_PAGES; | |
1585 | int page = i % APERTURE_RANGE_PAGES; | |
1586 | __set_bit(page, dom->aperture[index]->bitmap); | |
1587 | } | |
1588 | } | |
1589 | ||
9cabe89b JR |
1590 | /* |
1591 | * This function is used to add a new aperture range to an existing | |
1592 | * aperture in case of dma_ops domain allocation or address allocation | |
1593 | * failure. | |
1594 | */ | |
576175c2 | 1595 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1596 | bool populate, gfp_t gfp) |
1597 | { | |
1598 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1599 | struct amd_iommu *iommu; |
5d7c94c3 | 1600 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1601 | |
f5e9705c JR |
1602 | #ifdef CONFIG_IOMMU_STRESS |
1603 | populate = false; | |
1604 | #endif | |
1605 | ||
9cabe89b JR |
1606 | if (index >= APERTURE_MAX_RANGES) |
1607 | return -ENOMEM; | |
1608 | ||
1609 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1610 | if (!dma_dom->aperture[index]) | |
1611 | return -ENOMEM; | |
1612 | ||
1613 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1614 | if (!dma_dom->aperture[index]->bitmap) | |
1615 | goto out_free; | |
1616 | ||
1617 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1618 | ||
1619 | if (populate) { | |
1620 | unsigned long address = dma_dom->aperture_size; | |
1621 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1622 | u64 *pte, *pte_page; | |
1623 | ||
1624 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1625 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1626 | &pte_page, gfp); |
1627 | if (!pte) | |
1628 | goto out_free; | |
1629 | ||
1630 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1631 | ||
1632 | address += APERTURE_RANGE_SIZE / 64; | |
1633 | } | |
1634 | } | |
1635 | ||
17f5b569 | 1636 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1637 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1638 | ||
17f5b569 JR |
1639 | /* Reserve address range used for MSI messages */ |
1640 | if (old_size < MSI_ADDR_BASE_LO && | |
1641 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1642 | unsigned long spage; | |
1643 | int pages; | |
1644 | ||
1645 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1646 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1647 | ||
1648 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1649 | } | |
1650 | ||
b595076a | 1651 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1652 | for_each_iommu(iommu) { |
1653 | if (iommu->exclusion_start && | |
1654 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1655 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1656 | unsigned long startpage; | |
1657 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1658 | iommu->exclusion_length, | |
1659 | PAGE_SIZE); | |
1660 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1661 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1662 | } | |
00cd122a JR |
1663 | } |
1664 | ||
1665 | /* | |
1666 | * Check for areas already mapped as present in the new aperture | |
1667 | * range and mark those pages as reserved in the allocator. Such | |
1668 | * mappings may already exist as a result of requested unity | |
1669 | * mappings for devices. | |
1670 | */ | |
1671 | for (i = dma_dom->aperture[index]->offset; | |
1672 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1673 | i += pte_pgsize) { |
3039ca1b | 1674 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1675 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1676 | continue; | |
1677 | ||
5d7c94c3 JR |
1678 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1679 | pte_pgsize >> 12); | |
00cd122a JR |
1680 | } |
1681 | ||
04bfdd84 JR |
1682 | update_domain(&dma_dom->domain); |
1683 | ||
9cabe89b JR |
1684 | return 0; |
1685 | ||
1686 | out_free: | |
04bfdd84 JR |
1687 | update_domain(&dma_dom->domain); |
1688 | ||
9cabe89b JR |
1689 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1690 | ||
1691 | kfree(dma_dom->aperture[index]); | |
1692 | dma_dom->aperture[index] = NULL; | |
1693 | ||
1694 | return -ENOMEM; | |
1695 | } | |
1696 | ||
384de729 JR |
1697 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1698 | struct dma_ops_domain *dom, | |
1699 | unsigned int pages, | |
1700 | unsigned long align_mask, | |
1701 | u64 dma_mask, | |
1702 | unsigned long start) | |
1703 | { | |
803b8cb4 | 1704 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1705 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1706 | int i = start >> APERTURE_RANGE_SHIFT; | |
1707 | unsigned long boundary_size; | |
1708 | unsigned long address = -1; | |
1709 | unsigned long limit; | |
1710 | ||
803b8cb4 JR |
1711 | next_bit >>= PAGE_SHIFT; |
1712 | ||
384de729 JR |
1713 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1714 | PAGE_SIZE) >> PAGE_SHIFT; | |
1715 | ||
1716 | for (;i < max_index; ++i) { | |
1717 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1718 | ||
1719 | if (dom->aperture[i]->offset >= dma_mask) | |
1720 | break; | |
1721 | ||
1722 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1723 | dma_mask >> PAGE_SHIFT); | |
1724 | ||
1725 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1726 | limit, next_bit, pages, 0, | |
1727 | boundary_size, align_mask); | |
1728 | if (address != -1) { | |
1729 | address = dom->aperture[i]->offset + | |
1730 | (address << PAGE_SHIFT); | |
803b8cb4 | 1731 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1732 | break; |
1733 | } | |
1734 | ||
1735 | next_bit = 0; | |
1736 | } | |
1737 | ||
1738 | return address; | |
1739 | } | |
1740 | ||
d3086444 JR |
1741 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1742 | struct dma_ops_domain *dom, | |
6d4f343f | 1743 | unsigned int pages, |
832a90c3 JR |
1744 | unsigned long align_mask, |
1745 | u64 dma_mask) | |
d3086444 | 1746 | { |
d3086444 | 1747 | unsigned long address; |
d3086444 | 1748 | |
fe16f088 JR |
1749 | #ifdef CONFIG_IOMMU_STRESS |
1750 | dom->next_address = 0; | |
1751 | dom->need_flush = true; | |
1752 | #endif | |
d3086444 | 1753 | |
384de729 | 1754 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1755 | dma_mask, dom->next_address); |
d3086444 | 1756 | |
1c655773 | 1757 | if (address == -1) { |
803b8cb4 | 1758 | dom->next_address = 0; |
384de729 JR |
1759 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1760 | dma_mask, 0); | |
1c655773 JR |
1761 | dom->need_flush = true; |
1762 | } | |
d3086444 | 1763 | |
384de729 | 1764 | if (unlikely(address == -1)) |
8fd524b3 | 1765 | address = DMA_ERROR_CODE; |
d3086444 JR |
1766 | |
1767 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1768 | ||
1769 | return address; | |
1770 | } | |
1771 | ||
431b2a20 JR |
1772 | /* |
1773 | * The address free function. | |
1774 | * | |
1775 | * called with domain->lock held | |
1776 | */ | |
d3086444 JR |
1777 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1778 | unsigned long address, | |
1779 | unsigned int pages) | |
1780 | { | |
384de729 JR |
1781 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1782 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1783 | |
384de729 JR |
1784 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1785 | ||
47bccd6b JR |
1786 | #ifdef CONFIG_IOMMU_STRESS |
1787 | if (i < 4) | |
1788 | return; | |
1789 | #endif | |
80be308d | 1790 | |
803b8cb4 | 1791 | if (address >= dom->next_address) |
80be308d | 1792 | dom->need_flush = true; |
384de729 JR |
1793 | |
1794 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1795 | |
a66022c4 | 1796 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1797 | |
d3086444 JR |
1798 | } |
1799 | ||
431b2a20 JR |
1800 | /**************************************************************************** |
1801 | * | |
1802 | * The next functions belong to the domain allocation. A domain is | |
1803 | * allocated for every IOMMU as the default domain. If device isolation | |
1804 | * is enabled, every device get its own domain. The most important thing | |
1805 | * about domains is the page table mapping the DMA address space they | |
1806 | * contain. | |
1807 | * | |
1808 | ****************************************************************************/ | |
1809 | ||
aeb26f55 JR |
1810 | /* |
1811 | * This function adds a protection domain to the global protection domain list | |
1812 | */ | |
1813 | static void add_domain_to_list(struct protection_domain *domain) | |
1814 | { | |
1815 | unsigned long flags; | |
1816 | ||
1817 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1818 | list_add(&domain->list, &amd_iommu_pd_list); | |
1819 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1820 | } | |
1821 | ||
1822 | /* | |
1823 | * This function removes a protection domain to the global | |
1824 | * protection domain list | |
1825 | */ | |
1826 | static void del_domain_from_list(struct protection_domain *domain) | |
1827 | { | |
1828 | unsigned long flags; | |
1829 | ||
1830 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1831 | list_del(&domain->list); | |
1832 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1833 | } | |
1834 | ||
ec487d1a JR |
1835 | static u16 domain_id_alloc(void) |
1836 | { | |
1837 | unsigned long flags; | |
1838 | int id; | |
1839 | ||
1840 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1841 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1842 | BUG_ON(id == 0); | |
1843 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1844 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1845 | else | |
1846 | id = 0; | |
1847 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1848 | ||
1849 | return id; | |
1850 | } | |
1851 | ||
a2acfb75 JR |
1852 | static void domain_id_free(int id) |
1853 | { | |
1854 | unsigned long flags; | |
1855 | ||
1856 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1857 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1858 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1859 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1860 | } | |
a2acfb75 | 1861 | |
5c34c403 JR |
1862 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1863 | static void free_pt_##LVL (unsigned long __pt) \ | |
1864 | { \ | |
1865 | unsigned long p; \ | |
1866 | u64 *pt; \ | |
1867 | int i; \ | |
1868 | \ | |
1869 | pt = (u64 *)__pt; \ | |
1870 | \ | |
1871 | for (i = 0; i < 512; ++i) { \ | |
1872 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1873 | continue; \ | |
1874 | \ | |
1875 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1876 | FN(p); \ | |
1877 | } \ | |
1878 | free_page((unsigned long)pt); \ | |
1879 | } | |
1880 | ||
1881 | DEFINE_FREE_PT_FN(l2, free_page) | |
1882 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1883 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1884 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1885 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1886 | ||
86db2e5d | 1887 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1888 | { |
5c34c403 | 1889 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1890 | |
5c34c403 JR |
1891 | switch (domain->mode) { |
1892 | case PAGE_MODE_NONE: | |
1893 | break; | |
1894 | case PAGE_MODE_1_LEVEL: | |
1895 | free_page(root); | |
1896 | break; | |
1897 | case PAGE_MODE_2_LEVEL: | |
1898 | free_pt_l2(root); | |
1899 | break; | |
1900 | case PAGE_MODE_3_LEVEL: | |
1901 | free_pt_l3(root); | |
1902 | break; | |
1903 | case PAGE_MODE_4_LEVEL: | |
1904 | free_pt_l4(root); | |
1905 | break; | |
1906 | case PAGE_MODE_5_LEVEL: | |
1907 | free_pt_l5(root); | |
1908 | break; | |
1909 | case PAGE_MODE_6_LEVEL: | |
1910 | free_pt_l6(root); | |
1911 | break; | |
1912 | default: | |
1913 | BUG(); | |
ec487d1a | 1914 | } |
ec487d1a JR |
1915 | } |
1916 | ||
b16137b1 JR |
1917 | static void free_gcr3_tbl_level1(u64 *tbl) |
1918 | { | |
1919 | u64 *ptr; | |
1920 | int i; | |
1921 | ||
1922 | for (i = 0; i < 512; ++i) { | |
1923 | if (!(tbl[i] & GCR3_VALID)) | |
1924 | continue; | |
1925 | ||
1926 | ptr = __va(tbl[i] & PAGE_MASK); | |
1927 | ||
1928 | free_page((unsigned long)ptr); | |
1929 | } | |
1930 | } | |
1931 | ||
1932 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1933 | { | |
1934 | u64 *ptr; | |
1935 | int i; | |
1936 | ||
1937 | for (i = 0; i < 512; ++i) { | |
1938 | if (!(tbl[i] & GCR3_VALID)) | |
1939 | continue; | |
1940 | ||
1941 | ptr = __va(tbl[i] & PAGE_MASK); | |
1942 | ||
1943 | free_gcr3_tbl_level1(ptr); | |
1944 | } | |
1945 | } | |
1946 | ||
52815b75 JR |
1947 | static void free_gcr3_table(struct protection_domain *domain) |
1948 | { | |
b16137b1 JR |
1949 | if (domain->glx == 2) |
1950 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1951 | else if (domain->glx == 1) | |
1952 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1953 | else if (domain->glx != 0) | |
1954 | BUG(); | |
1955 | ||
52815b75 JR |
1956 | free_page((unsigned long)domain->gcr3_tbl); |
1957 | } | |
1958 | ||
431b2a20 JR |
1959 | /* |
1960 | * Free a domain, only used if something went wrong in the | |
1961 | * allocation path and we need to free an already allocated page table | |
1962 | */ | |
ec487d1a JR |
1963 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1964 | { | |
384de729 JR |
1965 | int i; |
1966 | ||
ec487d1a JR |
1967 | if (!dom) |
1968 | return; | |
1969 | ||
aeb26f55 JR |
1970 | del_domain_from_list(&dom->domain); |
1971 | ||
86db2e5d | 1972 | free_pagetable(&dom->domain); |
ec487d1a | 1973 | |
384de729 JR |
1974 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1975 | if (!dom->aperture[i]) | |
1976 | continue; | |
1977 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1978 | kfree(dom->aperture[i]); | |
1979 | } | |
ec487d1a JR |
1980 | |
1981 | kfree(dom); | |
1982 | } | |
1983 | ||
431b2a20 JR |
1984 | /* |
1985 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1986 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1987 | * structures required for the dma_ops interface |
1988 | */ | |
87a64d52 | 1989 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1990 | { |
1991 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1992 | |
1993 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1994 | if (!dma_dom) | |
1995 | return NULL; | |
1996 | ||
1997 | spin_lock_init(&dma_dom->domain.lock); | |
1998 | ||
1999 | dma_dom->domain.id = domain_id_alloc(); | |
2000 | if (dma_dom->domain.id == 0) | |
2001 | goto free_dma_dom; | |
7c392cbe | 2002 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 2003 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2004 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2005 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2006 | dma_dom->domain.priv = dma_dom; |
2007 | if (!dma_dom->domain.pt_root) | |
2008 | goto free_dma_dom; | |
ec487d1a | 2009 | |
1c655773 | 2010 | dma_dom->need_flush = false; |
bd60b735 | 2011 | dma_dom->target_dev = 0xffff; |
1c655773 | 2012 | |
aeb26f55 JR |
2013 | add_domain_to_list(&dma_dom->domain); |
2014 | ||
576175c2 | 2015 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2016 | goto free_dma_dom; |
ec487d1a | 2017 | |
431b2a20 | 2018 | /* |
ec487d1a JR |
2019 | * mark the first page as allocated so we never return 0 as |
2020 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2021 | */ |
384de729 | 2022 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 2023 | dma_dom->next_address = 0; |
ec487d1a | 2024 | |
ec487d1a JR |
2025 | |
2026 | return dma_dom; | |
2027 | ||
2028 | free_dma_dom: | |
2029 | dma_ops_domain_free(dma_dom); | |
2030 | ||
2031 | return NULL; | |
2032 | } | |
2033 | ||
5b28df6f JR |
2034 | /* |
2035 | * little helper function to check whether a given protection domain is a | |
2036 | * dma_ops domain | |
2037 | */ | |
2038 | static bool dma_ops_domain(struct protection_domain *domain) | |
2039 | { | |
2040 | return domain->flags & PD_DMA_OPS_MASK; | |
2041 | } | |
2042 | ||
fd7b5535 | 2043 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2044 | { |
132bd68f | 2045 | u64 pte_root = 0; |
ee6c2868 | 2046 | u64 flags = 0; |
863c74eb | 2047 | |
132bd68f JR |
2048 | if (domain->mode != PAGE_MODE_NONE) |
2049 | pte_root = virt_to_phys(domain->pt_root); | |
2050 | ||
38ddf41b JR |
2051 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2052 | << DEV_ENTRY_MODE_SHIFT; | |
2053 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2054 | |
ee6c2868 JR |
2055 | flags = amd_iommu_dev_table[devid].data[1]; |
2056 | ||
fd7b5535 JR |
2057 | if (ats) |
2058 | flags |= DTE_FLAG_IOTLB; | |
2059 | ||
52815b75 JR |
2060 | if (domain->flags & PD_IOMMUV2_MASK) { |
2061 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2062 | u64 glx = domain->glx; | |
2063 | u64 tmp; | |
2064 | ||
2065 | pte_root |= DTE_FLAG_GV; | |
2066 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2067 | ||
2068 | /* First mask out possible old values for GCR3 table */ | |
2069 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2070 | flags &= ~tmp; | |
2071 | ||
2072 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2073 | flags &= ~tmp; | |
2074 | ||
2075 | /* Encode GCR3 table into DTE */ | |
2076 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2077 | pte_root |= tmp; | |
2078 | ||
2079 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2080 | flags |= tmp; | |
2081 | ||
2082 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2083 | flags |= tmp; | |
2084 | } | |
2085 | ||
ee6c2868 JR |
2086 | flags &= ~(0xffffUL); |
2087 | flags |= domain->id; | |
2088 | ||
2089 | amd_iommu_dev_table[devid].data[1] = flags; | |
2090 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2091 | } |
2092 | ||
2093 | static void clear_dte_entry(u16 devid) | |
2094 | { | |
15898bbc JR |
2095 | /* remove entry from the device table seen by the hardware */ |
2096 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2097 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2098 | |
2099 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2100 | } |
2101 | ||
ec9e79ef JR |
2102 | static void do_attach(struct iommu_dev_data *dev_data, |
2103 | struct protection_domain *domain) | |
7f760ddd | 2104 | { |
7f760ddd | 2105 | struct amd_iommu *iommu; |
ec9e79ef | 2106 | bool ats; |
fd7b5535 | 2107 | |
ec9e79ef JR |
2108 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2109 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2110 | |
2111 | /* Update data structures */ | |
2112 | dev_data->domain = domain; | |
2113 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2114 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2115 | |
2116 | /* Do reference counting */ | |
2117 | domain->dev_iommu[iommu->index] += 1; | |
2118 | domain->dev_cnt += 1; | |
2119 | ||
2120 | /* Flush the DTE entry */ | |
6c542047 | 2121 | device_flush_dte(dev_data); |
7f760ddd JR |
2122 | } |
2123 | ||
ec9e79ef | 2124 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2125 | { |
7f760ddd | 2126 | struct amd_iommu *iommu; |
7f760ddd | 2127 | |
ec9e79ef | 2128 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2129 | |
2130 | /* decrease reference counters */ | |
7f760ddd JR |
2131 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2132 | dev_data->domain->dev_cnt -= 1; | |
2133 | ||
2134 | /* Update data structures */ | |
2135 | dev_data->domain = NULL; | |
2136 | list_del(&dev_data->list); | |
f62dda66 | 2137 | clear_dte_entry(dev_data->devid); |
15898bbc | 2138 | |
7f760ddd | 2139 | /* Flush the DTE entry */ |
6c542047 | 2140 | device_flush_dte(dev_data); |
2b681faf JR |
2141 | } |
2142 | ||
2143 | /* | |
2144 | * If a device is not yet associated with a domain, this function does | |
2145 | * assigns it visible for the hardware | |
2146 | */ | |
ec9e79ef | 2147 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2148 | struct protection_domain *domain) |
2b681faf | 2149 | { |
397111ab | 2150 | struct iommu_dev_data *head, *entry; |
84fe6c19 | 2151 | int ret; |
657cbb6b | 2152 | |
2b681faf JR |
2153 | /* lock domain */ |
2154 | spin_lock(&domain->lock); | |
2155 | ||
397111ab | 2156 | head = dev_data; |
15898bbc | 2157 | |
397111ab JR |
2158 | if (head->alias_data != NULL) |
2159 | head = head->alias_data; | |
eba6ac60 | 2160 | |
397111ab | 2161 | /* Now we have the root of the alias group, if any */ |
15898bbc | 2162 | |
397111ab JR |
2163 | ret = -EBUSY; |
2164 | if (head->domain != NULL) | |
2165 | goto out_unlock; | |
15898bbc | 2166 | |
397111ab JR |
2167 | /* Attach alias group root */ |
2168 | do_attach(head, domain); | |
eba6ac60 | 2169 | |
397111ab JR |
2170 | /* Attach other devices in the alias group */ |
2171 | list_for_each_entry(entry, &head->alias_list, alias_list) | |
2172 | do_attach(entry, domain); | |
24100055 | 2173 | |
84fe6c19 JL |
2174 | ret = 0; |
2175 | ||
2176 | out_unlock: | |
2177 | ||
eba6ac60 JR |
2178 | /* ready */ |
2179 | spin_unlock(&domain->lock); | |
15898bbc | 2180 | |
84fe6c19 | 2181 | return ret; |
0feae533 | 2182 | } |
b20ac0d4 | 2183 | |
52815b75 JR |
2184 | |
2185 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2186 | { | |
2187 | pci_disable_ats(pdev); | |
2188 | pci_disable_pri(pdev); | |
2189 | pci_disable_pasid(pdev); | |
2190 | } | |
2191 | ||
6a113ddc JR |
2192 | /* FIXME: Change generic reset-function to do the same */ |
2193 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2194 | { | |
2195 | u16 control; | |
2196 | int pos; | |
2197 | ||
46277b75 | 2198 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2199 | if (!pos) |
2200 | return -EINVAL; | |
2201 | ||
46277b75 JR |
2202 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2203 | control |= PCI_PRI_CTRL_RESET; | |
2204 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2205 | |
2206 | return 0; | |
2207 | } | |
2208 | ||
52815b75 JR |
2209 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2210 | { | |
6a113ddc JR |
2211 | bool reset_enable; |
2212 | int reqs, ret; | |
2213 | ||
2214 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2215 | reqs = 32; | |
2216 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2217 | reqs = 1; | |
2218 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2219 | |
2220 | /* Only allow access to user-accessible pages */ | |
2221 | ret = pci_enable_pasid(pdev, 0); | |
2222 | if (ret) | |
2223 | goto out_err; | |
2224 | ||
2225 | /* First reset the PRI state of the device */ | |
2226 | ret = pci_reset_pri(pdev); | |
2227 | if (ret) | |
2228 | goto out_err; | |
2229 | ||
6a113ddc JR |
2230 | /* Enable PRI */ |
2231 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2232 | if (ret) |
2233 | goto out_err; | |
2234 | ||
6a113ddc JR |
2235 | if (reset_enable) { |
2236 | ret = pri_reset_while_enabled(pdev); | |
2237 | if (ret) | |
2238 | goto out_err; | |
2239 | } | |
2240 | ||
52815b75 JR |
2241 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2242 | if (ret) | |
2243 | goto out_err; | |
2244 | ||
2245 | return 0; | |
2246 | ||
2247 | out_err: | |
2248 | pci_disable_pri(pdev); | |
2249 | pci_disable_pasid(pdev); | |
2250 | ||
2251 | return ret; | |
2252 | } | |
2253 | ||
c99afa25 | 2254 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2255 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2256 | |
98f1ad25 | 2257 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2258 | { |
a3b93121 | 2259 | u16 status; |
c99afa25 JR |
2260 | int pos; |
2261 | ||
46277b75 | 2262 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2263 | if (!pos) |
2264 | return false; | |
2265 | ||
a3b93121 | 2266 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2267 | |
a3b93121 | 2268 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2269 | } |
2270 | ||
407d733e | 2271 | /* |
df805abb | 2272 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2273 | * assigns it visible for the hardware |
2274 | */ | |
15898bbc JR |
2275 | static int attach_device(struct device *dev, |
2276 | struct protection_domain *domain) | |
0feae533 | 2277 | { |
fd7b5535 | 2278 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2279 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2280 | unsigned long flags; |
15898bbc | 2281 | int ret; |
eba6ac60 | 2282 | |
ea61cddb JR |
2283 | dev_data = get_dev_data(dev); |
2284 | ||
52815b75 JR |
2285 | if (domain->flags & PD_IOMMUV2_MASK) { |
2286 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2287 | return -EINVAL; | |
2288 | ||
2289 | if (pdev_iommuv2_enable(pdev) != 0) | |
2290 | return -EINVAL; | |
2291 | ||
2292 | dev_data->ats.enabled = true; | |
2293 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2294 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2295 | } else if (amd_iommu_iotlb_sup && |
2296 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2297 | dev_data->ats.enabled = true; |
2298 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2299 | } | |
fd7b5535 | 2300 | |
eba6ac60 | 2301 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2302 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2303 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2304 | ||
0feae533 JR |
2305 | /* |
2306 | * We might boot into a crash-kernel here. The crashed kernel | |
2307 | * left the caches in the IOMMU dirty. So we have to flush | |
2308 | * here to evict all dirty stuff. | |
2309 | */ | |
17b124bf | 2310 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2311 | |
2312 | return ret; | |
b20ac0d4 JR |
2313 | } |
2314 | ||
355bf553 JR |
2315 | /* |
2316 | * Removes a device from a protection domain (unlocked) | |
2317 | */ | |
ec9e79ef | 2318 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2319 | { |
397111ab | 2320 | struct iommu_dev_data *head, *entry; |
2ca76279 | 2321 | struct protection_domain *domain; |
7c392cbe | 2322 | unsigned long flags; |
c4596114 | 2323 | |
7f760ddd | 2324 | BUG_ON(!dev_data->domain); |
355bf553 | 2325 | |
2ca76279 JR |
2326 | domain = dev_data->domain; |
2327 | ||
2328 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2329 | |
397111ab JR |
2330 | head = dev_data; |
2331 | if (head->alias_data != NULL) | |
2332 | head = head->alias_data; | |
71f77580 | 2333 | |
397111ab JR |
2334 | list_for_each_entry(entry, &head->alias_list, alias_list) |
2335 | do_detach(entry); | |
24100055 | 2336 | |
397111ab | 2337 | do_detach(head); |
7f760ddd | 2338 | |
2ca76279 | 2339 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2340 | |
2341 | /* | |
2342 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2343 | * passthrough domain if it is detached from any other domain. |
2344 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2345 | */ |
5abcdba4 | 2346 | if (dev_data->passthrough && |
d3ad9373 | 2347 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2348 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2349 | } |
2350 | ||
2351 | /* | |
2352 | * Removes a device from a protection domain (with devtable_lock held) | |
2353 | */ | |
15898bbc | 2354 | static void detach_device(struct device *dev) |
355bf553 | 2355 | { |
52815b75 | 2356 | struct protection_domain *domain; |
ea61cddb | 2357 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2358 | unsigned long flags; |
2359 | ||
ec9e79ef | 2360 | dev_data = get_dev_data(dev); |
52815b75 | 2361 | domain = dev_data->domain; |
ec9e79ef | 2362 | |
355bf553 JR |
2363 | /* lock device table */ |
2364 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2365 | __detach_device(dev_data); |
355bf553 | 2366 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2367 | |
52815b75 JR |
2368 | if (domain->flags & PD_IOMMUV2_MASK) |
2369 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2370 | else if (dev_data->ats.enabled) | |
ea61cddb | 2371 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2372 | |
2373 | dev_data->ats.enabled = false; | |
355bf553 | 2374 | } |
e275a2a0 | 2375 | |
15898bbc JR |
2376 | /* |
2377 | * Find out the protection domain structure for a given PCI device. This | |
2378 | * will give us the pointer to the page table root for example. | |
2379 | */ | |
2380 | static struct protection_domain *domain_for_device(struct device *dev) | |
2381 | { | |
71f77580 | 2382 | struct iommu_dev_data *dev_data; |
2b02b091 | 2383 | struct protection_domain *dom = NULL; |
15898bbc | 2384 | unsigned long flags; |
15898bbc | 2385 | |
657cbb6b | 2386 | dev_data = get_dev_data(dev); |
15898bbc | 2387 | |
2b02b091 JR |
2388 | if (dev_data->domain) |
2389 | return dev_data->domain; | |
15898bbc | 2390 | |
71f77580 JR |
2391 | if (dev_data->alias_data != NULL) { |
2392 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2393 | |
2394 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2395 | if (alias_data->domain != NULL) { | |
2396 | __attach_device(dev_data, alias_data->domain); | |
2397 | dom = alias_data->domain; | |
2398 | } | |
2399 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2400 | } | |
15898bbc JR |
2401 | |
2402 | return dom; | |
2403 | } | |
2404 | ||
e275a2a0 JR |
2405 | static int device_change_notifier(struct notifier_block *nb, |
2406 | unsigned long action, void *data) | |
2407 | { | |
e275a2a0 | 2408 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2409 | struct protection_domain *domain; |
2410 | struct iommu_dev_data *dev_data; | |
2411 | struct device *dev = data; | |
e275a2a0 | 2412 | struct amd_iommu *iommu; |
1ac4cbbc | 2413 | unsigned long flags; |
5abcdba4 | 2414 | u16 devid; |
e275a2a0 | 2415 | |
98fc5a69 JR |
2416 | if (!check_device(dev)) |
2417 | return 0; | |
e275a2a0 | 2418 | |
5abcdba4 JR |
2419 | devid = get_device_id(dev); |
2420 | iommu = amd_iommu_rlookup_table[devid]; | |
2421 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2422 | |
2423 | switch (action) { | |
1ac4cbbc | 2424 | case BUS_NOTIFY_ADD_DEVICE: |
657cbb6b JR |
2425 | |
2426 | iommu_init_device(dev); | |
25b11ce2 | 2427 | init_iommu_group(dev); |
657cbb6b | 2428 | |
2c9195e9 JR |
2429 | /* |
2430 | * dev_data is still NULL and | |
2431 | * got initialized in iommu_init_device | |
2432 | */ | |
2433 | dev_data = get_dev_data(dev); | |
2434 | ||
2435 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2436 | dev_data->passthrough = true; | |
2437 | attach_device(dev, pt_domain); | |
2438 | break; | |
2439 | } | |
2440 | ||
657cbb6b JR |
2441 | domain = domain_for_device(dev); |
2442 | ||
1ac4cbbc JR |
2443 | /* allocate a protection domain if a device is added */ |
2444 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2445 | if (!dma_domain) { |
2446 | dma_domain = dma_ops_domain_alloc(); | |
2447 | if (!dma_domain) | |
2448 | goto out; | |
2449 | dma_domain->target_dev = devid; | |
2450 | ||
2451 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2452 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2453 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2454 | } | |
ac1534a5 | 2455 | |
2c9195e9 | 2456 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2457 | |
e275a2a0 | 2458 | break; |
6c5cc801 | 2459 | case BUS_NOTIFY_REMOVED_DEVICE: |
657cbb6b JR |
2460 | |
2461 | iommu_uninit_device(dev); | |
2462 | ||
e275a2a0 JR |
2463 | default: |
2464 | goto out; | |
2465 | } | |
2466 | ||
e275a2a0 JR |
2467 | iommu_completion_wait(iommu); |
2468 | ||
2469 | out: | |
2470 | return 0; | |
2471 | } | |
2472 | ||
b25ae679 | 2473 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2474 | .notifier_call = device_change_notifier, |
2475 | }; | |
355bf553 | 2476 | |
8638c491 JR |
2477 | void amd_iommu_init_notifier(void) |
2478 | { | |
2479 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2480 | } | |
2481 | ||
431b2a20 JR |
2482 | /***************************************************************************** |
2483 | * | |
2484 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2485 | * | |
2486 | *****************************************************************************/ | |
2487 | ||
2488 | /* | |
2489 | * In the dma_ops path we only have the struct device. This function | |
2490 | * finds the corresponding IOMMU, the protection domain and the | |
2491 | * requestor id for a given device. | |
2492 | * If the device is not yet associated with a domain this is also done | |
2493 | * in this function. | |
2494 | */ | |
94f6d190 | 2495 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2496 | { |
94f6d190 | 2497 | struct protection_domain *domain; |
063071df | 2498 | struct iommu_domain *io_domain; |
b20ac0d4 | 2499 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2500 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2501 | |
f99c0f1c | 2502 | if (!check_device(dev)) |
94f6d190 | 2503 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2504 | |
063071df JR |
2505 | io_domain = iommu_get_domain_for_dev(dev); |
2506 | if (io_domain) { | |
2507 | domain = to_pdomain(io_domain); | |
2508 | return domain; | |
2509 | } | |
2510 | ||
94f6d190 JR |
2511 | domain = domain_for_device(dev); |
2512 | if (domain != NULL && !dma_ops_domain(domain)) | |
2513 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2514 | |
94f6d190 JR |
2515 | if (domain != NULL) |
2516 | return domain; | |
b20ac0d4 | 2517 | |
df805abb | 2518 | /* Device not bound yet - bind it */ |
94f6d190 | 2519 | dma_dom = find_protection_domain(devid); |
15898bbc | 2520 | if (!dma_dom) |
94f6d190 JR |
2521 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2522 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2523 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2524 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2525 | |
94f6d190 | 2526 | return &dma_dom->domain; |
b20ac0d4 JR |
2527 | } |
2528 | ||
04bfdd84 JR |
2529 | static void update_device_table(struct protection_domain *domain) |
2530 | { | |
492667da | 2531 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2532 | |
ea61cddb JR |
2533 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2534 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2535 | } |
2536 | ||
2537 | static void update_domain(struct protection_domain *domain) | |
2538 | { | |
2539 | if (!domain->updated) | |
2540 | return; | |
2541 | ||
2542 | update_device_table(domain); | |
17b124bf JR |
2543 | |
2544 | domain_flush_devices(domain); | |
2545 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2546 | |
2547 | domain->updated = false; | |
2548 | } | |
2549 | ||
8bda3092 JR |
2550 | /* |
2551 | * This function fetches the PTE for a given address in the aperture | |
2552 | */ | |
2553 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2554 | unsigned long address) | |
2555 | { | |
384de729 | 2556 | struct aperture_range *aperture; |
8bda3092 JR |
2557 | u64 *pte, *pte_page; |
2558 | ||
384de729 JR |
2559 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2560 | if (!aperture) | |
2561 | return NULL; | |
2562 | ||
2563 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2564 | if (!pte) { |
cbb9d729 | 2565 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2566 | GFP_ATOMIC); |
384de729 JR |
2567 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2568 | } else | |
8c8c143c | 2569 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2570 | |
04bfdd84 | 2571 | update_domain(&dom->domain); |
8bda3092 JR |
2572 | |
2573 | return pte; | |
2574 | } | |
2575 | ||
431b2a20 JR |
2576 | /* |
2577 | * This is the generic map function. It maps one 4kb page at paddr to | |
2578 | * the given address in the DMA address space for the domain. | |
2579 | */ | |
680525e0 | 2580 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2581 | unsigned long address, |
2582 | phys_addr_t paddr, | |
2583 | int direction) | |
2584 | { | |
2585 | u64 *pte, __pte; | |
2586 | ||
2587 | WARN_ON(address > dom->aperture_size); | |
2588 | ||
2589 | paddr &= PAGE_MASK; | |
2590 | ||
8bda3092 | 2591 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2592 | if (!pte) |
8fd524b3 | 2593 | return DMA_ERROR_CODE; |
cb76c322 JR |
2594 | |
2595 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2596 | ||
2597 | if (direction == DMA_TO_DEVICE) | |
2598 | __pte |= IOMMU_PTE_IR; | |
2599 | else if (direction == DMA_FROM_DEVICE) | |
2600 | __pte |= IOMMU_PTE_IW; | |
2601 | else if (direction == DMA_BIDIRECTIONAL) | |
2602 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2603 | ||
2604 | WARN_ON(*pte); | |
2605 | ||
2606 | *pte = __pte; | |
2607 | ||
2608 | return (dma_addr_t)address; | |
2609 | } | |
2610 | ||
431b2a20 JR |
2611 | /* |
2612 | * The generic unmapping function for on page in the DMA address space. | |
2613 | */ | |
680525e0 | 2614 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2615 | unsigned long address) |
2616 | { | |
384de729 | 2617 | struct aperture_range *aperture; |
cb76c322 JR |
2618 | u64 *pte; |
2619 | ||
2620 | if (address >= dom->aperture_size) | |
2621 | return; | |
2622 | ||
384de729 JR |
2623 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2624 | if (!aperture) | |
2625 | return; | |
2626 | ||
2627 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2628 | if (!pte) | |
2629 | return; | |
cb76c322 | 2630 | |
8c8c143c | 2631 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2632 | |
2633 | WARN_ON(!*pte); | |
2634 | ||
2635 | *pte = 0ULL; | |
2636 | } | |
2637 | ||
431b2a20 JR |
2638 | /* |
2639 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2640 | * contiguous memory region into DMA address space. It is used by all |
2641 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2642 | * Must be called with the domain lock held. |
2643 | */ | |
cb76c322 | 2644 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2645 | struct dma_ops_domain *dma_dom, |
2646 | phys_addr_t paddr, | |
2647 | size_t size, | |
6d4f343f | 2648 | int dir, |
832a90c3 JR |
2649 | bool align, |
2650 | u64 dma_mask) | |
cb76c322 JR |
2651 | { |
2652 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2653 | dma_addr_t address, start, ret; |
cb76c322 | 2654 | unsigned int pages; |
6d4f343f | 2655 | unsigned long align_mask = 0; |
cb76c322 JR |
2656 | int i; |
2657 | ||
e3c449f5 | 2658 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2659 | paddr &= PAGE_MASK; |
2660 | ||
8ecaf8f1 JR |
2661 | INC_STATS_COUNTER(total_map_requests); |
2662 | ||
c1858976 JR |
2663 | if (pages > 1) |
2664 | INC_STATS_COUNTER(cross_page); | |
2665 | ||
6d4f343f JR |
2666 | if (align) |
2667 | align_mask = (1UL << get_order(size)) - 1; | |
2668 | ||
11b83888 | 2669 | retry: |
832a90c3 JR |
2670 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2671 | dma_mask); | |
8fd524b3 | 2672 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2673 | /* |
2674 | * setting next_address here will let the address | |
2675 | * allocator only scan the new allocated range in the | |
2676 | * first run. This is a small optimization. | |
2677 | */ | |
2678 | dma_dom->next_address = dma_dom->aperture_size; | |
2679 | ||
576175c2 | 2680 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2681 | goto out; |
2682 | ||
2683 | /* | |
af901ca1 | 2684 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2685 | * allocation again |
2686 | */ | |
2687 | goto retry; | |
2688 | } | |
cb76c322 JR |
2689 | |
2690 | start = address; | |
2691 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2692 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2693 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2694 | goto out_unmap; |
2695 | ||
cb76c322 JR |
2696 | paddr += PAGE_SIZE; |
2697 | start += PAGE_SIZE; | |
2698 | } | |
2699 | address += offset; | |
2700 | ||
5774f7c5 JR |
2701 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2702 | ||
afa9fdc2 | 2703 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2704 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2705 | dma_dom->need_flush = false; |
318afd41 | 2706 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2707 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2708 | |
cb76c322 JR |
2709 | out: |
2710 | return address; | |
53812c11 JR |
2711 | |
2712 | out_unmap: | |
2713 | ||
2714 | for (--i; i >= 0; --i) { | |
2715 | start -= PAGE_SIZE; | |
680525e0 | 2716 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2717 | } |
2718 | ||
2719 | dma_ops_free_addresses(dma_dom, address, pages); | |
2720 | ||
8fd524b3 | 2721 | return DMA_ERROR_CODE; |
cb76c322 JR |
2722 | } |
2723 | ||
431b2a20 JR |
2724 | /* |
2725 | * Does the reverse of the __map_single function. Must be called with | |
2726 | * the domain lock held too | |
2727 | */ | |
cd8c82e8 | 2728 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2729 | dma_addr_t dma_addr, |
2730 | size_t size, | |
2731 | int dir) | |
2732 | { | |
04e0463e | 2733 | dma_addr_t flush_addr; |
cb76c322 JR |
2734 | dma_addr_t i, start; |
2735 | unsigned int pages; | |
2736 | ||
8fd524b3 | 2737 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2738 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2739 | return; |
2740 | ||
04e0463e | 2741 | flush_addr = dma_addr; |
e3c449f5 | 2742 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2743 | dma_addr &= PAGE_MASK; |
2744 | start = dma_addr; | |
2745 | ||
2746 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2747 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2748 | start += PAGE_SIZE; |
2749 | } | |
2750 | ||
5774f7c5 JR |
2751 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2752 | ||
cb76c322 | 2753 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2754 | |
80be308d | 2755 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2756 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2757 | dma_dom->need_flush = false; |
2758 | } | |
cb76c322 JR |
2759 | } |
2760 | ||
431b2a20 JR |
2761 | /* |
2762 | * The exported map_single function for dma_ops. | |
2763 | */ | |
51491367 FT |
2764 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2765 | unsigned long offset, size_t size, | |
2766 | enum dma_data_direction dir, | |
2767 | struct dma_attrs *attrs) | |
4da70b9e JR |
2768 | { |
2769 | unsigned long flags; | |
4da70b9e | 2770 | struct protection_domain *domain; |
4da70b9e | 2771 | dma_addr_t addr; |
832a90c3 | 2772 | u64 dma_mask; |
51491367 | 2773 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2774 | |
0f2a86f2 JR |
2775 | INC_STATS_COUNTER(cnt_map_single); |
2776 | ||
94f6d190 JR |
2777 | domain = get_domain(dev); |
2778 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2779 | return (dma_addr_t)paddr; |
94f6d190 JR |
2780 | else if (IS_ERR(domain)) |
2781 | return DMA_ERROR_CODE; | |
4da70b9e | 2782 | |
f99c0f1c JR |
2783 | dma_mask = *dev->dma_mask; |
2784 | ||
4da70b9e | 2785 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2786 | |
cd8c82e8 | 2787 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2788 | dma_mask); |
8fd524b3 | 2789 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2790 | goto out; |
2791 | ||
17b124bf | 2792 | domain_flush_complete(domain); |
4da70b9e JR |
2793 | |
2794 | out: | |
2795 | spin_unlock_irqrestore(&domain->lock, flags); | |
2796 | ||
2797 | return addr; | |
2798 | } | |
2799 | ||
431b2a20 JR |
2800 | /* |
2801 | * The exported unmap_single function for dma_ops. | |
2802 | */ | |
51491367 FT |
2803 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2804 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2805 | { |
2806 | unsigned long flags; | |
4da70b9e | 2807 | struct protection_domain *domain; |
4da70b9e | 2808 | |
146a6917 JR |
2809 | INC_STATS_COUNTER(cnt_unmap_single); |
2810 | ||
94f6d190 JR |
2811 | domain = get_domain(dev); |
2812 | if (IS_ERR(domain)) | |
5b28df6f JR |
2813 | return; |
2814 | ||
4da70b9e JR |
2815 | spin_lock_irqsave(&domain->lock, flags); |
2816 | ||
cd8c82e8 | 2817 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2818 | |
17b124bf | 2819 | domain_flush_complete(domain); |
4da70b9e JR |
2820 | |
2821 | spin_unlock_irqrestore(&domain->lock, flags); | |
2822 | } | |
2823 | ||
431b2a20 JR |
2824 | /* |
2825 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2826 | * lists). | |
2827 | */ | |
65b050ad | 2828 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2829 | int nelems, enum dma_data_direction dir, |
2830 | struct dma_attrs *attrs) | |
65b050ad JR |
2831 | { |
2832 | unsigned long flags; | |
65b050ad | 2833 | struct protection_domain *domain; |
65b050ad JR |
2834 | int i; |
2835 | struct scatterlist *s; | |
2836 | phys_addr_t paddr; | |
2837 | int mapped_elems = 0; | |
832a90c3 | 2838 | u64 dma_mask; |
65b050ad | 2839 | |
d03f067a JR |
2840 | INC_STATS_COUNTER(cnt_map_sg); |
2841 | ||
94f6d190 | 2842 | domain = get_domain(dev); |
a0e191b2 | 2843 | if (IS_ERR(domain)) |
94f6d190 | 2844 | return 0; |
dbcc112e | 2845 | |
832a90c3 | 2846 | dma_mask = *dev->dma_mask; |
65b050ad | 2847 | |
65b050ad JR |
2848 | spin_lock_irqsave(&domain->lock, flags); |
2849 | ||
2850 | for_each_sg(sglist, s, nelems, i) { | |
2851 | paddr = sg_phys(s); | |
2852 | ||
cd8c82e8 | 2853 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2854 | paddr, s->length, dir, false, |
2855 | dma_mask); | |
65b050ad JR |
2856 | |
2857 | if (s->dma_address) { | |
2858 | s->dma_length = s->length; | |
2859 | mapped_elems++; | |
2860 | } else | |
2861 | goto unmap; | |
65b050ad JR |
2862 | } |
2863 | ||
17b124bf | 2864 | domain_flush_complete(domain); |
65b050ad JR |
2865 | |
2866 | out: | |
2867 | spin_unlock_irqrestore(&domain->lock, flags); | |
2868 | ||
2869 | return mapped_elems; | |
2870 | unmap: | |
2871 | for_each_sg(sglist, s, mapped_elems, i) { | |
2872 | if (s->dma_address) | |
cd8c82e8 | 2873 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2874 | s->dma_length, dir); |
2875 | s->dma_address = s->dma_length = 0; | |
2876 | } | |
2877 | ||
2878 | mapped_elems = 0; | |
2879 | ||
2880 | goto out; | |
2881 | } | |
2882 | ||
431b2a20 JR |
2883 | /* |
2884 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2885 | * lists). | |
2886 | */ | |
65b050ad | 2887 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2888 | int nelems, enum dma_data_direction dir, |
2889 | struct dma_attrs *attrs) | |
65b050ad JR |
2890 | { |
2891 | unsigned long flags; | |
65b050ad JR |
2892 | struct protection_domain *domain; |
2893 | struct scatterlist *s; | |
65b050ad JR |
2894 | int i; |
2895 | ||
55877a6b JR |
2896 | INC_STATS_COUNTER(cnt_unmap_sg); |
2897 | ||
94f6d190 JR |
2898 | domain = get_domain(dev); |
2899 | if (IS_ERR(domain)) | |
5b28df6f JR |
2900 | return; |
2901 | ||
65b050ad JR |
2902 | spin_lock_irqsave(&domain->lock, flags); |
2903 | ||
2904 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2905 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2906 | s->dma_length, dir); |
65b050ad JR |
2907 | s->dma_address = s->dma_length = 0; |
2908 | } | |
2909 | ||
17b124bf | 2910 | domain_flush_complete(domain); |
65b050ad JR |
2911 | |
2912 | spin_unlock_irqrestore(&domain->lock, flags); | |
2913 | } | |
2914 | ||
431b2a20 JR |
2915 | /* |
2916 | * The exported alloc_coherent function for dma_ops. | |
2917 | */ | |
5d8b53cf | 2918 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2919 | dma_addr_t *dma_addr, gfp_t flag, |
2920 | struct dma_attrs *attrs) | |
5d8b53cf | 2921 | { |
832a90c3 | 2922 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2923 | struct protection_domain *domain; |
2924 | unsigned long flags; | |
2925 | struct page *page; | |
5d8b53cf | 2926 | |
c8f0fb36 JR |
2927 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2928 | ||
94f6d190 JR |
2929 | domain = get_domain(dev); |
2930 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2931 | page = alloc_pages(flag, get_order(size)); |
2932 | *dma_addr = page_to_phys(page); | |
2933 | return page_address(page); | |
94f6d190 JR |
2934 | } else if (IS_ERR(domain)) |
2935 | return NULL; | |
5d8b53cf | 2936 | |
3b839a57 | 2937 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2938 | dma_mask = dev->coherent_dma_mask; |
2939 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 2940 | |
3b839a57 JR |
2941 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2942 | if (!page) { | |
2943 | if (!(flag & __GFP_WAIT)) | |
2944 | return NULL; | |
5d8b53cf | 2945 | |
3b839a57 JR |
2946 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2947 | get_order(size)); | |
2948 | if (!page) | |
2949 | return NULL; | |
2950 | } | |
5d8b53cf | 2951 | |
832a90c3 JR |
2952 | if (!dma_mask) |
2953 | dma_mask = *dev->dma_mask; | |
2954 | ||
5d8b53cf JR |
2955 | spin_lock_irqsave(&domain->lock, flags); |
2956 | ||
3b839a57 | 2957 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2958 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2959 | |
8fd524b3 | 2960 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2961 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2962 | goto out_free; |
367d04c4 | 2963 | } |
5d8b53cf | 2964 | |
17b124bf | 2965 | domain_flush_complete(domain); |
5d8b53cf | 2966 | |
5d8b53cf JR |
2967 | spin_unlock_irqrestore(&domain->lock, flags); |
2968 | ||
3b839a57 | 2969 | return page_address(page); |
5b28df6f JR |
2970 | |
2971 | out_free: | |
2972 | ||
3b839a57 JR |
2973 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2974 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2975 | |
2976 | return NULL; | |
5d8b53cf JR |
2977 | } |
2978 | ||
431b2a20 JR |
2979 | /* |
2980 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2981 | */ |
5d8b53cf | 2982 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2983 | void *virt_addr, dma_addr_t dma_addr, |
2984 | struct dma_attrs *attrs) | |
5d8b53cf | 2985 | { |
5d8b53cf | 2986 | struct protection_domain *domain; |
3b839a57 JR |
2987 | unsigned long flags; |
2988 | struct page *page; | |
5d8b53cf | 2989 | |
5d31ee7e JR |
2990 | INC_STATS_COUNTER(cnt_free_coherent); |
2991 | ||
3b839a57 JR |
2992 | page = virt_to_page(virt_addr); |
2993 | size = PAGE_ALIGN(size); | |
2994 | ||
94f6d190 JR |
2995 | domain = get_domain(dev); |
2996 | if (IS_ERR(domain)) | |
5b28df6f JR |
2997 | goto free_mem; |
2998 | ||
5d8b53cf JR |
2999 | spin_lock_irqsave(&domain->lock, flags); |
3000 | ||
cd8c82e8 | 3001 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 3002 | |
17b124bf | 3003 | domain_flush_complete(domain); |
5d8b53cf JR |
3004 | |
3005 | spin_unlock_irqrestore(&domain->lock, flags); | |
3006 | ||
3007 | free_mem: | |
3b839a57 JR |
3008 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
3009 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
3010 | } |
3011 | ||
b39ba6ad JR |
3012 | /* |
3013 | * This function is called by the DMA layer to find out if we can handle a | |
3014 | * particular device. It is part of the dma_ops. | |
3015 | */ | |
3016 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
3017 | { | |
420aef8a | 3018 | return check_device(dev); |
b39ba6ad JR |
3019 | } |
3020 | ||
c432f3df | 3021 | /* |
431b2a20 JR |
3022 | * The function for pre-allocating protection domains. |
3023 | * | |
c432f3df JR |
3024 | * If the driver core informs the DMA layer if a driver grabs a device |
3025 | * we don't need to preallocate the protection domains anymore. | |
3026 | * For now we have to. | |
3027 | */ | |
943bc7e1 | 3028 | static void __init prealloc_protection_domains(void) |
c432f3df | 3029 | { |
5abcdba4 | 3030 | struct iommu_dev_data *dev_data; |
c432f3df | 3031 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3032 | struct pci_dev *dev = NULL; |
98fc5a69 | 3033 | u16 devid; |
c432f3df | 3034 | |
d18c69d3 | 3035 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3036 | |
3037 | /* Do we handle this device? */ | |
3038 | if (!check_device(&dev->dev)) | |
c432f3df | 3039 | continue; |
98fc5a69 | 3040 | |
5abcdba4 JR |
3041 | dev_data = get_dev_data(&dev->dev); |
3042 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3043 | /* Make sure passthrough domain is allocated */ | |
3044 | alloc_passthrough_domain(); | |
3045 | dev_data->passthrough = true; | |
3046 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3047 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3048 | dev_name(&dev->dev)); |
3049 | } | |
3050 | ||
98fc5a69 | 3051 | /* Is there already any domain for it? */ |
15898bbc | 3052 | if (domain_for_device(&dev->dev)) |
c432f3df | 3053 | continue; |
98fc5a69 JR |
3054 | |
3055 | devid = get_device_id(&dev->dev); | |
3056 | ||
87a64d52 | 3057 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3058 | if (!dma_dom) |
3059 | continue; | |
3060 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3061 | dma_dom->target_dev = devid; |
3062 | ||
15898bbc | 3063 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3064 | |
bd60b735 | 3065 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3066 | } |
3067 | } | |
3068 | ||
160c1d8e | 3069 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3070 | .alloc = alloc_coherent, |
3071 | .free = free_coherent, | |
51491367 FT |
3072 | .map_page = map_page, |
3073 | .unmap_page = unmap_page, | |
6631ee9d JR |
3074 | .map_sg = map_sg, |
3075 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3076 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3077 | }; |
3078 | ||
27c2127a JR |
3079 | static unsigned device_dma_ops_init(void) |
3080 | { | |
5abcdba4 | 3081 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3082 | struct pci_dev *pdev = NULL; |
3083 | unsigned unhandled = 0; | |
3084 | ||
3085 | for_each_pci_dev(pdev) { | |
3086 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3087 | |
3088 | iommu_ignore_device(&pdev->dev); | |
3089 | ||
27c2127a JR |
3090 | unhandled += 1; |
3091 | continue; | |
3092 | } | |
3093 | ||
5abcdba4 JR |
3094 | dev_data = get_dev_data(&pdev->dev); |
3095 | ||
3096 | if (!dev_data->passthrough) | |
3097 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3098 | else | |
3099 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3100 | } |
3101 | ||
3102 | return unhandled; | |
3103 | } | |
3104 | ||
431b2a20 JR |
3105 | /* |
3106 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3107 | */ | |
f5325094 JR |
3108 | |
3109 | void __init amd_iommu_init_api(void) | |
3110 | { | |
2cc21c42 | 3111 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3112 | } |
3113 | ||
6631ee9d JR |
3114 | int __init amd_iommu_init_dma_ops(void) |
3115 | { | |
3116 | struct amd_iommu *iommu; | |
27c2127a | 3117 | int ret, unhandled; |
6631ee9d | 3118 | |
431b2a20 JR |
3119 | /* |
3120 | * first allocate a default protection domain for every IOMMU we | |
3121 | * found in the system. Devices not assigned to any other | |
3122 | * protection domain will be assigned to the default one. | |
3123 | */ | |
3bd22172 | 3124 | for_each_iommu(iommu) { |
87a64d52 | 3125 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3126 | if (iommu->default_dom == NULL) |
3127 | return -ENOMEM; | |
e2dc14a2 | 3128 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3129 | ret = iommu_init_unity_mappings(iommu); |
3130 | if (ret) | |
3131 | goto free_domains; | |
3132 | } | |
3133 | ||
431b2a20 | 3134 | /* |
8793abeb | 3135 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3136 | */ |
8793abeb | 3137 | prealloc_protection_domains(); |
6631ee9d JR |
3138 | |
3139 | iommu_detected = 1; | |
75f1cdf1 | 3140 | swiotlb = 0; |
6631ee9d | 3141 | |
431b2a20 | 3142 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3143 | unhandled = device_dma_ops_init(); |
3144 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3145 | /* There are unhandled devices - initialize swiotlb for them */ | |
3146 | swiotlb = 1; | |
3147 | } | |
6631ee9d | 3148 | |
7f26508b JR |
3149 | amd_iommu_stats_init(); |
3150 | ||
62410eeb JR |
3151 | if (amd_iommu_unmap_flush) |
3152 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3153 | else | |
3154 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3155 | ||
6631ee9d JR |
3156 | return 0; |
3157 | ||
3158 | free_domains: | |
3159 | ||
3bd22172 | 3160 | for_each_iommu(iommu) { |
91457df7 | 3161 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3162 | } |
3163 | ||
3164 | return ret; | |
3165 | } | |
6d98cd80 JR |
3166 | |
3167 | /***************************************************************************** | |
3168 | * | |
3169 | * The following functions belong to the exported interface of AMD IOMMU | |
3170 | * | |
3171 | * This interface allows access to lower level functions of the IOMMU | |
3172 | * like protection domain handling and assignement of devices to domains | |
3173 | * which is not possible with the dma_ops interface. | |
3174 | * | |
3175 | *****************************************************************************/ | |
3176 | ||
6d98cd80 JR |
3177 | static void cleanup_domain(struct protection_domain *domain) |
3178 | { | |
9b29d3c6 | 3179 | struct iommu_dev_data *entry; |
6d98cd80 | 3180 | unsigned long flags; |
6d98cd80 JR |
3181 | |
3182 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3183 | ||
9b29d3c6 JR |
3184 | while (!list_empty(&domain->dev_list)) { |
3185 | entry = list_first_entry(&domain->dev_list, | |
3186 | struct iommu_dev_data, list); | |
3187 | __detach_device(entry); | |
492667da | 3188 | } |
6d98cd80 JR |
3189 | |
3190 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3191 | } | |
3192 | ||
2650815f JR |
3193 | static void protection_domain_free(struct protection_domain *domain) |
3194 | { | |
3195 | if (!domain) | |
3196 | return; | |
3197 | ||
aeb26f55 JR |
3198 | del_domain_from_list(domain); |
3199 | ||
2650815f JR |
3200 | if (domain->id) |
3201 | domain_id_free(domain->id); | |
3202 | ||
3203 | kfree(domain); | |
3204 | } | |
3205 | ||
3206 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3207 | { |
3208 | struct protection_domain *domain; | |
3209 | ||
3210 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3211 | if (!domain) | |
2650815f | 3212 | return NULL; |
c156e347 JR |
3213 | |
3214 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3215 | mutex_init(&domain->api_lock); |
c156e347 JR |
3216 | domain->id = domain_id_alloc(); |
3217 | if (!domain->id) | |
2650815f | 3218 | goto out_err; |
7c392cbe | 3219 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3220 | |
aeb26f55 JR |
3221 | add_domain_to_list(domain); |
3222 | ||
2650815f JR |
3223 | return domain; |
3224 | ||
3225 | out_err: | |
3226 | kfree(domain); | |
3227 | ||
3228 | return NULL; | |
3229 | } | |
3230 | ||
5abcdba4 JR |
3231 | static int __init alloc_passthrough_domain(void) |
3232 | { | |
3233 | if (pt_domain != NULL) | |
3234 | return 0; | |
3235 | ||
3236 | /* allocate passthrough domain */ | |
3237 | pt_domain = protection_domain_alloc(); | |
3238 | if (!pt_domain) | |
3239 | return -ENOMEM; | |
3240 | ||
3241 | pt_domain->mode = PAGE_MODE_NONE; | |
3242 | ||
3243 | return 0; | |
3244 | } | |
3f4b87b9 JR |
3245 | |
3246 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
2650815f | 3247 | { |
3f4b87b9 | 3248 | struct protection_domain *pdomain; |
2650815f | 3249 | |
3f4b87b9 JR |
3250 | /* We only support unmanaged domains for now */ |
3251 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
3252 | return NULL; | |
2650815f | 3253 | |
3f4b87b9 JR |
3254 | pdomain = protection_domain_alloc(); |
3255 | if (!pdomain) | |
c156e347 JR |
3256 | goto out_free; |
3257 | ||
3f4b87b9 JR |
3258 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3259 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3260 | if (!pdomain->pt_root) | |
3261 | goto out_free; | |
c156e347 | 3262 | |
3f4b87b9 JR |
3263 | pdomain->domain.geometry.aperture_start = 0; |
3264 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3265 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3266 | |
3f4b87b9 | 3267 | return &pdomain->domain; |
c156e347 JR |
3268 | |
3269 | out_free: | |
3f4b87b9 | 3270 | protection_domain_free(pdomain); |
c156e347 | 3271 | |
3f4b87b9 | 3272 | return NULL; |
c156e347 JR |
3273 | } |
3274 | ||
3f4b87b9 | 3275 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3276 | { |
3f4b87b9 | 3277 | struct protection_domain *domain; |
98383fc3 | 3278 | |
3f4b87b9 | 3279 | if (!dom) |
98383fc3 JR |
3280 | return; |
3281 | ||
3f4b87b9 JR |
3282 | domain = to_pdomain(dom); |
3283 | ||
98383fc3 JR |
3284 | if (domain->dev_cnt > 0) |
3285 | cleanup_domain(domain); | |
3286 | ||
3287 | BUG_ON(domain->dev_cnt != 0); | |
3288 | ||
132bd68f JR |
3289 | if (domain->mode != PAGE_MODE_NONE) |
3290 | free_pagetable(domain); | |
98383fc3 | 3291 | |
52815b75 JR |
3292 | if (domain->flags & PD_IOMMUV2_MASK) |
3293 | free_gcr3_table(domain); | |
3294 | ||
8b408fe4 | 3295 | protection_domain_free(domain); |
98383fc3 JR |
3296 | } |
3297 | ||
684f2888 JR |
3298 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3299 | struct device *dev) | |
3300 | { | |
657cbb6b | 3301 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3302 | struct amd_iommu *iommu; |
684f2888 JR |
3303 | u16 devid; |
3304 | ||
98fc5a69 | 3305 | if (!check_device(dev)) |
684f2888 JR |
3306 | return; |
3307 | ||
98fc5a69 | 3308 | devid = get_device_id(dev); |
684f2888 | 3309 | |
657cbb6b | 3310 | if (dev_data->domain != NULL) |
15898bbc | 3311 | detach_device(dev); |
684f2888 JR |
3312 | |
3313 | iommu = amd_iommu_rlookup_table[devid]; | |
3314 | if (!iommu) | |
3315 | return; | |
3316 | ||
684f2888 JR |
3317 | iommu_completion_wait(iommu); |
3318 | } | |
3319 | ||
01106066 JR |
3320 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3321 | struct device *dev) | |
3322 | { | |
3f4b87b9 | 3323 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3324 | struct iommu_dev_data *dev_data; |
01106066 | 3325 | struct amd_iommu *iommu; |
15898bbc | 3326 | int ret; |
01106066 | 3327 | |
98fc5a69 | 3328 | if (!check_device(dev)) |
01106066 JR |
3329 | return -EINVAL; |
3330 | ||
657cbb6b JR |
3331 | dev_data = dev->archdata.iommu; |
3332 | ||
f62dda66 | 3333 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3334 | if (!iommu) |
3335 | return -EINVAL; | |
3336 | ||
657cbb6b | 3337 | if (dev_data->domain) |
15898bbc | 3338 | detach_device(dev); |
01106066 | 3339 | |
15898bbc | 3340 | ret = attach_device(dev, domain); |
01106066 JR |
3341 | |
3342 | iommu_completion_wait(iommu); | |
3343 | ||
15898bbc | 3344 | return ret; |
01106066 JR |
3345 | } |
3346 | ||
468e2366 | 3347 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3348 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3349 | { |
3f4b87b9 | 3350 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3351 | int prot = 0; |
3352 | int ret; | |
3353 | ||
132bd68f JR |
3354 | if (domain->mode == PAGE_MODE_NONE) |
3355 | return -EINVAL; | |
3356 | ||
c6229ca6 JR |
3357 | if (iommu_prot & IOMMU_READ) |
3358 | prot |= IOMMU_PROT_IR; | |
3359 | if (iommu_prot & IOMMU_WRITE) | |
3360 | prot |= IOMMU_PROT_IW; | |
3361 | ||
5d214fe6 | 3362 | mutex_lock(&domain->api_lock); |
795e74f7 | 3363 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3364 | mutex_unlock(&domain->api_lock); |
3365 | ||
795e74f7 | 3366 | return ret; |
c6229ca6 JR |
3367 | } |
3368 | ||
5009065d OBC |
3369 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3370 | size_t page_size) | |
eb74ff6c | 3371 | { |
3f4b87b9 | 3372 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3373 | size_t unmap_size; |
eb74ff6c | 3374 | |
132bd68f JR |
3375 | if (domain->mode == PAGE_MODE_NONE) |
3376 | return -EINVAL; | |
3377 | ||
5d214fe6 | 3378 | mutex_lock(&domain->api_lock); |
468e2366 | 3379 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3380 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3381 | |
17b124bf | 3382 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3383 | |
5009065d | 3384 | return unmap_size; |
eb74ff6c JR |
3385 | } |
3386 | ||
645c4c8d | 3387 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3388 | dma_addr_t iova) |
645c4c8d | 3389 | { |
3f4b87b9 | 3390 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3391 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3392 | u64 *pte, __pte; |
645c4c8d | 3393 | |
132bd68f JR |
3394 | if (domain->mode == PAGE_MODE_NONE) |
3395 | return iova; | |
3396 | ||
3039ca1b | 3397 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3398 | |
a6d41a40 | 3399 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3400 | return 0; |
3401 | ||
b24b1b63 JR |
3402 | offset_mask = pte_pgsize - 1; |
3403 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3404 | |
b24b1b63 | 3405 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3406 | } |
3407 | ||
ab636481 | 3408 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3409 | { |
80a506b8 JR |
3410 | switch (cap) { |
3411 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3412 | return true; |
bdddadcb | 3413 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3414 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3415 | case IOMMU_CAP_NOEXEC: |
3416 | return false; | |
80a506b8 JR |
3417 | } |
3418 | ||
ab636481 | 3419 | return false; |
dbb9fd86 SY |
3420 | } |
3421 | ||
35cf248f JR |
3422 | static void amd_iommu_get_dm_regions(struct device *dev, |
3423 | struct list_head *head) | |
3424 | { | |
3425 | struct unity_map_entry *entry; | |
3426 | u16 devid; | |
3427 | ||
3428 | devid = get_device_id(dev); | |
3429 | ||
3430 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3431 | struct iommu_dm_region *region; | |
3432 | ||
3433 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3434 | continue; | |
3435 | ||
3436 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3437 | if (!region) { | |
3438 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3439 | dev_name(dev)); | |
3440 | return; | |
3441 | } | |
3442 | ||
3443 | region->start = entry->address_start; | |
3444 | region->length = entry->address_end - entry->address_start; | |
3445 | if (entry->prot & IOMMU_PROT_IR) | |
3446 | region->prot |= IOMMU_READ; | |
3447 | if (entry->prot & IOMMU_PROT_IW) | |
3448 | region->prot |= IOMMU_WRITE; | |
3449 | ||
3450 | list_add_tail(®ion->list, head); | |
3451 | } | |
3452 | } | |
3453 | ||
3454 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3455 | struct list_head *head) | |
3456 | { | |
3457 | struct iommu_dm_region *entry, *next; | |
3458 | ||
3459 | list_for_each_entry_safe(entry, next, head, list) | |
3460 | kfree(entry); | |
3461 | } | |
3462 | ||
b22f6434 | 3463 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3464 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3465 | .domain_alloc = amd_iommu_domain_alloc, |
3466 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3467 | .attach_dev = amd_iommu_attach_device, |
3468 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3469 | .map = amd_iommu_map, |
3470 | .unmap = amd_iommu_unmap, | |
315786eb | 3471 | .map_sg = default_iommu_map_sg, |
26961efe | 3472 | .iova_to_phys = amd_iommu_iova_to_phys, |
35cf248f JR |
3473 | .get_dm_regions = amd_iommu_get_dm_regions, |
3474 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3475 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3476 | }; |
3477 | ||
0feae533 JR |
3478 | /***************************************************************************** |
3479 | * | |
3480 | * The next functions do a basic initialization of IOMMU for pass through | |
3481 | * mode | |
3482 | * | |
3483 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3484 | * DMA-API translation. | |
3485 | * | |
3486 | *****************************************************************************/ | |
3487 | ||
3488 | int __init amd_iommu_init_passthrough(void) | |
3489 | { | |
5abcdba4 | 3490 | struct iommu_dev_data *dev_data; |
0feae533 | 3491 | struct pci_dev *dev = NULL; |
5abcdba4 | 3492 | int ret; |
0feae533 | 3493 | |
5abcdba4 JR |
3494 | ret = alloc_passthrough_domain(); |
3495 | if (ret) | |
3496 | return ret; | |
0feae533 | 3497 | |
6c54aabd | 3498 | for_each_pci_dev(dev) { |
98fc5a69 | 3499 | if (!check_device(&dev->dev)) |
0feae533 JR |
3500 | continue; |
3501 | ||
5abcdba4 JR |
3502 | dev_data = get_dev_data(&dev->dev); |
3503 | dev_data->passthrough = true; | |
3504 | ||
15898bbc | 3505 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3506 | } |
3507 | ||
2655d7a2 JR |
3508 | amd_iommu_stats_init(); |
3509 | ||
0feae533 JR |
3510 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3511 | ||
3512 | return 0; | |
3513 | } | |
72e1dcc4 JR |
3514 | |
3515 | /* IOMMUv2 specific functions */ | |
3516 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3517 | { | |
3518 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3519 | } | |
3520 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3521 | ||
3522 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3523 | { | |
3524 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3525 | } | |
3526 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3527 | |
3528 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3529 | { | |
3f4b87b9 | 3530 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3531 | unsigned long flags; |
3532 | ||
3533 | spin_lock_irqsave(&domain->lock, flags); | |
3534 | ||
3535 | /* Update data structure */ | |
3536 | domain->mode = PAGE_MODE_NONE; | |
3537 | domain->updated = true; | |
3538 | ||
3539 | /* Make changes visible to IOMMUs */ | |
3540 | update_domain(domain); | |
3541 | ||
3542 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3543 | free_pagetable(domain); | |
3544 | ||
3545 | spin_unlock_irqrestore(&domain->lock, flags); | |
3546 | } | |
3547 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3548 | |
3549 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3550 | { | |
3f4b87b9 | 3551 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3552 | unsigned long flags; |
3553 | int levels, ret; | |
3554 | ||
3555 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3556 | return -EINVAL; | |
3557 | ||
3558 | /* Number of GCR3 table levels required */ | |
3559 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3560 | levels += 1; | |
3561 | ||
3562 | if (levels > amd_iommu_max_glx_val) | |
3563 | return -EINVAL; | |
3564 | ||
3565 | spin_lock_irqsave(&domain->lock, flags); | |
3566 | ||
3567 | /* | |
3568 | * Save us all sanity checks whether devices already in the | |
3569 | * domain support IOMMUv2. Just force that the domain has no | |
3570 | * devices attached when it is switched into IOMMUv2 mode. | |
3571 | */ | |
3572 | ret = -EBUSY; | |
3573 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3574 | goto out; | |
3575 | ||
3576 | ret = -ENOMEM; | |
3577 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3578 | if (domain->gcr3_tbl == NULL) | |
3579 | goto out; | |
3580 | ||
3581 | domain->glx = levels; | |
3582 | domain->flags |= PD_IOMMUV2_MASK; | |
3583 | domain->updated = true; | |
3584 | ||
3585 | update_domain(domain); | |
3586 | ||
3587 | ret = 0; | |
3588 | ||
3589 | out: | |
3590 | spin_unlock_irqrestore(&domain->lock, flags); | |
3591 | ||
3592 | return ret; | |
3593 | } | |
3594 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3595 | |
3596 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3597 | u64 address, bool size) | |
3598 | { | |
3599 | struct iommu_dev_data *dev_data; | |
3600 | struct iommu_cmd cmd; | |
3601 | int i, ret; | |
3602 | ||
3603 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3604 | return -EINVAL; | |
3605 | ||
3606 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3607 | ||
3608 | /* | |
3609 | * IOMMU TLB needs to be flushed before Device TLB to | |
3610 | * prevent device TLB refill from IOMMU TLB | |
3611 | */ | |
3612 | for (i = 0; i < amd_iommus_present; ++i) { | |
3613 | if (domain->dev_iommu[i] == 0) | |
3614 | continue; | |
3615 | ||
3616 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3617 | if (ret != 0) | |
3618 | goto out; | |
3619 | } | |
3620 | ||
3621 | /* Wait until IOMMU TLB flushes are complete */ | |
3622 | domain_flush_complete(domain); | |
3623 | ||
3624 | /* Now flush device TLBs */ | |
3625 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3626 | struct amd_iommu *iommu; | |
3627 | int qdep; | |
3628 | ||
3629 | BUG_ON(!dev_data->ats.enabled); | |
3630 | ||
3631 | qdep = dev_data->ats.qdep; | |
3632 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3633 | ||
3634 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3635 | qdep, address, size); | |
3636 | ||
3637 | ret = iommu_queue_command(iommu, &cmd); | |
3638 | if (ret != 0) | |
3639 | goto out; | |
3640 | } | |
3641 | ||
3642 | /* Wait until all device TLBs are flushed */ | |
3643 | domain_flush_complete(domain); | |
3644 | ||
3645 | ret = 0; | |
3646 | ||
3647 | out: | |
3648 | ||
3649 | return ret; | |
3650 | } | |
3651 | ||
3652 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3653 | u64 address) | |
3654 | { | |
399be2f5 JR |
3655 | INC_STATS_COUNTER(invalidate_iotlb); |
3656 | ||
22e266c7 JR |
3657 | return __flush_pasid(domain, pasid, address, false); |
3658 | } | |
3659 | ||
3660 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3661 | u64 address) | |
3662 | { | |
3f4b87b9 | 3663 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3664 | unsigned long flags; |
3665 | int ret; | |
3666 | ||
3667 | spin_lock_irqsave(&domain->lock, flags); | |
3668 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3669 | spin_unlock_irqrestore(&domain->lock, flags); | |
3670 | ||
3671 | return ret; | |
3672 | } | |
3673 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3674 | ||
3675 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3676 | { | |
399be2f5 JR |
3677 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3678 | ||
22e266c7 JR |
3679 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3680 | true); | |
3681 | } | |
3682 | ||
3683 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3684 | { | |
3f4b87b9 | 3685 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3686 | unsigned long flags; |
3687 | int ret; | |
3688 | ||
3689 | spin_lock_irqsave(&domain->lock, flags); | |
3690 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3691 | spin_unlock_irqrestore(&domain->lock, flags); | |
3692 | ||
3693 | return ret; | |
3694 | } | |
3695 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3696 | ||
b16137b1 JR |
3697 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3698 | { | |
3699 | int index; | |
3700 | u64 *pte; | |
3701 | ||
3702 | while (true) { | |
3703 | ||
3704 | index = (pasid >> (9 * level)) & 0x1ff; | |
3705 | pte = &root[index]; | |
3706 | ||
3707 | if (level == 0) | |
3708 | break; | |
3709 | ||
3710 | if (!(*pte & GCR3_VALID)) { | |
3711 | if (!alloc) | |
3712 | return NULL; | |
3713 | ||
3714 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3715 | if (root == NULL) | |
3716 | return NULL; | |
3717 | ||
3718 | *pte = __pa(root) | GCR3_VALID; | |
3719 | } | |
3720 | ||
3721 | root = __va(*pte & PAGE_MASK); | |
3722 | ||
3723 | level -= 1; | |
3724 | } | |
3725 | ||
3726 | return pte; | |
3727 | } | |
3728 | ||
3729 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3730 | unsigned long cr3) | |
3731 | { | |
3732 | u64 *pte; | |
3733 | ||
3734 | if (domain->mode != PAGE_MODE_NONE) | |
3735 | return -EINVAL; | |
3736 | ||
3737 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3738 | if (pte == NULL) | |
3739 | return -ENOMEM; | |
3740 | ||
3741 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3742 | ||
3743 | return __amd_iommu_flush_tlb(domain, pasid); | |
3744 | } | |
3745 | ||
3746 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3747 | { | |
3748 | u64 *pte; | |
3749 | ||
3750 | if (domain->mode != PAGE_MODE_NONE) | |
3751 | return -EINVAL; | |
3752 | ||
3753 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3754 | if (pte == NULL) | |
3755 | return 0; | |
3756 | ||
3757 | *pte = 0; | |
3758 | ||
3759 | return __amd_iommu_flush_tlb(domain, pasid); | |
3760 | } | |
3761 | ||
3762 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3763 | unsigned long cr3) | |
3764 | { | |
3f4b87b9 | 3765 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3766 | unsigned long flags; |
3767 | int ret; | |
3768 | ||
3769 | spin_lock_irqsave(&domain->lock, flags); | |
3770 | ret = __set_gcr3(domain, pasid, cr3); | |
3771 | spin_unlock_irqrestore(&domain->lock, flags); | |
3772 | ||
3773 | return ret; | |
3774 | } | |
3775 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3776 | ||
3777 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3778 | { | |
3f4b87b9 | 3779 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3780 | unsigned long flags; |
3781 | int ret; | |
3782 | ||
3783 | spin_lock_irqsave(&domain->lock, flags); | |
3784 | ret = __clear_gcr3(domain, pasid); | |
3785 | spin_unlock_irqrestore(&domain->lock, flags); | |
3786 | ||
3787 | return ret; | |
3788 | } | |
3789 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3790 | |
3791 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3792 | int status, int tag) | |
3793 | { | |
3794 | struct iommu_dev_data *dev_data; | |
3795 | struct amd_iommu *iommu; | |
3796 | struct iommu_cmd cmd; | |
3797 | ||
399be2f5 JR |
3798 | INC_STATS_COUNTER(complete_ppr); |
3799 | ||
c99afa25 JR |
3800 | dev_data = get_dev_data(&pdev->dev); |
3801 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3802 | ||
3803 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3804 | tag, dev_data->pri_tlp); | |
3805 | ||
3806 | return iommu_queue_command(iommu, &cmd); | |
3807 | } | |
3808 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3809 | |
3810 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3811 | { | |
3f4b87b9 | 3812 | struct protection_domain *pdomain; |
f3572db8 | 3813 | |
3f4b87b9 JR |
3814 | pdomain = get_domain(&pdev->dev); |
3815 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3816 | return NULL; |
3817 | ||
3818 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3819 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3820 | return NULL; |
3821 | ||
3f4b87b9 | 3822 | return &pdomain->domain; |
f3572db8 JR |
3823 | } |
3824 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3825 | |
3826 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3827 | { | |
3828 | struct iommu_dev_data *dev_data; | |
3829 | ||
3830 | if (!amd_iommu_v2_supported()) | |
3831 | return; | |
3832 | ||
3833 | dev_data = get_dev_data(&pdev->dev); | |
3834 | dev_data->errata |= (1 << erratum); | |
3835 | } | |
3836 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3837 | |
3838 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3839 | struct amd_iommu_device_info *info) | |
3840 | { | |
3841 | int max_pasids; | |
3842 | int pos; | |
3843 | ||
3844 | if (pdev == NULL || info == NULL) | |
3845 | return -EINVAL; | |
3846 | ||
3847 | if (!amd_iommu_v2_supported()) | |
3848 | return -EINVAL; | |
3849 | ||
3850 | memset(info, 0, sizeof(*info)); | |
3851 | ||
3852 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3853 | if (pos) | |
3854 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3855 | ||
3856 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3857 | if (pos) | |
3858 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3859 | ||
3860 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3861 | if (pos) { | |
3862 | int features; | |
3863 | ||
3864 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3865 | max_pasids = min(max_pasids, (1 << 20)); | |
3866 | ||
3867 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3868 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3869 | ||
3870 | features = pci_pasid_features(pdev); | |
3871 | if (features & PCI_PASID_CAP_EXEC) | |
3872 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3873 | if (features & PCI_PASID_CAP_PRIV) | |
3874 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3875 | } | |
3876 | ||
3877 | return 0; | |
3878 | } | |
3879 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3880 | |
3881 | #ifdef CONFIG_IRQ_REMAP | |
3882 | ||
3883 | /***************************************************************************** | |
3884 | * | |
3885 | * Interrupt Remapping Implementation | |
3886 | * | |
3887 | *****************************************************************************/ | |
3888 | ||
3889 | union irte { | |
3890 | u32 val; | |
3891 | struct { | |
3892 | u32 valid : 1, | |
3893 | no_fault : 1, | |
3894 | int_type : 3, | |
3895 | rq_eoi : 1, | |
3896 | dm : 1, | |
3897 | rsvd_1 : 1, | |
3898 | destination : 8, | |
3899 | vector : 8, | |
3900 | rsvd_2 : 8; | |
3901 | } fields; | |
3902 | }; | |
3903 | ||
3904 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3905 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3906 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3907 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3908 | ||
3909 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3910 | { | |
3911 | u64 dte; | |
3912 | ||
3913 | dte = amd_iommu_dev_table[devid].data[2]; | |
3914 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3915 | dte |= virt_to_phys(table->table); | |
3916 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3917 | dte |= DTE_IRQ_TABLE_LEN; | |
3918 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3919 | ||
3920 | amd_iommu_dev_table[devid].data[2] = dte; | |
3921 | } | |
3922 | ||
3923 | #define IRTE_ALLOCATED (~1U) | |
3924 | ||
3925 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3926 | { | |
3927 | struct irq_remap_table *table = NULL; | |
3928 | struct amd_iommu *iommu; | |
3929 | unsigned long flags; | |
3930 | u16 alias; | |
3931 | ||
3932 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3933 | ||
3934 | iommu = amd_iommu_rlookup_table[devid]; | |
3935 | if (!iommu) | |
3936 | goto out_unlock; | |
3937 | ||
3938 | table = irq_lookup_table[devid]; | |
3939 | if (table) | |
3940 | goto out; | |
3941 | ||
3942 | alias = amd_iommu_alias_table[devid]; | |
3943 | table = irq_lookup_table[alias]; | |
3944 | if (table) { | |
3945 | irq_lookup_table[devid] = table; | |
3946 | set_dte_irq_entry(devid, table); | |
3947 | iommu_flush_dte(iommu, devid); | |
3948 | goto out; | |
3949 | } | |
3950 | ||
3951 | /* Nothing there yet, allocate new irq remapping table */ | |
3952 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3953 | if (!table) | |
3954 | goto out; | |
3955 | ||
197887f0 JR |
3956 | /* Initialize table spin-lock */ |
3957 | spin_lock_init(&table->lock); | |
3958 | ||
2b324506 JR |
3959 | if (ioapic) |
3960 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3961 | table->min_index = 32; | |
3962 | ||
3963 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3964 | if (!table->table) { | |
3965 | kfree(table); | |
821f0f68 | 3966 | table = NULL; |
2b324506 JR |
3967 | goto out; |
3968 | } | |
3969 | ||
3970 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3971 | ||
3972 | if (ioapic) { | |
3973 | int i; | |
3974 | ||
3975 | for (i = 0; i < 32; ++i) | |
3976 | table->table[i] = IRTE_ALLOCATED; | |
3977 | } | |
3978 | ||
3979 | irq_lookup_table[devid] = table; | |
3980 | set_dte_irq_entry(devid, table); | |
3981 | iommu_flush_dte(iommu, devid); | |
3982 | if (devid != alias) { | |
3983 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3984 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3985 | iommu_flush_dte(iommu, alias); |
3986 | } | |
3987 | ||
3988 | out: | |
3989 | iommu_completion_wait(iommu); | |
3990 | ||
3991 | out_unlock: | |
3992 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3993 | ||
3994 | return table; | |
3995 | } | |
3996 | ||
3997 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3998 | { | |
3999 | struct irq_remap_table *table; | |
4000 | unsigned long flags; | |
4001 | int index, c; | |
4002 | ||
4003 | table = get_irq_table(devid, false); | |
4004 | if (!table) | |
4005 | return -ENODEV; | |
4006 | ||
4007 | spin_lock_irqsave(&table->lock, flags); | |
4008 | ||
4009 | /* Scan table for free entries */ | |
4010 | for (c = 0, index = table->min_index; | |
4011 | index < MAX_IRQS_PER_TABLE; | |
4012 | ++index) { | |
4013 | if (table->table[index] == 0) | |
4014 | c += 1; | |
4015 | else | |
4016 | c = 0; | |
4017 | ||
4018 | if (c == count) { | |
0dfedd61 | 4019 | struct irq_2_irte *irte_info; |
2b324506 JR |
4020 | |
4021 | for (; c != 0; --c) | |
4022 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
4023 | ||
4024 | index -= count - 1; | |
4025 | ||
9b1b0e42 | 4026 | cfg->remapped = 1; |
0dfedd61 JR |
4027 | irte_info = &cfg->irq_2_irte; |
4028 | irte_info->devid = devid; | |
4029 | irte_info->index = index; | |
2b324506 JR |
4030 | |
4031 | goto out; | |
4032 | } | |
4033 | } | |
4034 | ||
4035 | index = -ENOSPC; | |
4036 | ||
4037 | out: | |
4038 | spin_unlock_irqrestore(&table->lock, flags); | |
4039 | ||
4040 | return index; | |
4041 | } | |
4042 | ||
4043 | static int get_irte(u16 devid, int index, union irte *irte) | |
4044 | { | |
4045 | struct irq_remap_table *table; | |
4046 | unsigned long flags; | |
4047 | ||
4048 | table = get_irq_table(devid, false); | |
4049 | if (!table) | |
4050 | return -ENOMEM; | |
4051 | ||
4052 | spin_lock_irqsave(&table->lock, flags); | |
4053 | irte->val = table->table[index]; | |
4054 | spin_unlock_irqrestore(&table->lock, flags); | |
4055 | ||
4056 | return 0; | |
4057 | } | |
4058 | ||
4059 | static int modify_irte(u16 devid, int index, union irte irte) | |
4060 | { | |
4061 | struct irq_remap_table *table; | |
4062 | struct amd_iommu *iommu; | |
4063 | unsigned long flags; | |
4064 | ||
4065 | iommu = amd_iommu_rlookup_table[devid]; | |
4066 | if (iommu == NULL) | |
4067 | return -EINVAL; | |
4068 | ||
4069 | table = get_irq_table(devid, false); | |
4070 | if (!table) | |
4071 | return -ENOMEM; | |
4072 | ||
4073 | spin_lock_irqsave(&table->lock, flags); | |
4074 | table->table[index] = irte.val; | |
4075 | spin_unlock_irqrestore(&table->lock, flags); | |
4076 | ||
4077 | iommu_flush_irt(iommu, devid); | |
4078 | iommu_completion_wait(iommu); | |
4079 | ||
4080 | return 0; | |
4081 | } | |
4082 | ||
4083 | static void free_irte(u16 devid, int index) | |
4084 | { | |
4085 | struct irq_remap_table *table; | |
4086 | struct amd_iommu *iommu; | |
4087 | unsigned long flags; | |
4088 | ||
4089 | iommu = amd_iommu_rlookup_table[devid]; | |
4090 | if (iommu == NULL) | |
4091 | return; | |
4092 | ||
4093 | table = get_irq_table(devid, false); | |
4094 | if (!table) | |
4095 | return; | |
4096 | ||
4097 | spin_lock_irqsave(&table->lock, flags); | |
4098 | table->table[index] = 0; | |
4099 | spin_unlock_irqrestore(&table->lock, flags); | |
4100 | ||
4101 | iommu_flush_irt(iommu, devid); | |
4102 | iommu_completion_wait(iommu); | |
4103 | } | |
4104 | ||
5527de74 JR |
4105 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4106 | unsigned int destination, int vector, | |
4107 | struct io_apic_irq_attr *attr) | |
4108 | { | |
4109 | struct irq_remap_table *table; | |
0dfedd61 | 4110 | struct irq_2_irte *irte_info; |
5527de74 JR |
4111 | struct irq_cfg *cfg; |
4112 | union irte irte; | |
4113 | int ioapic_id; | |
4114 | int index; | |
4115 | int devid; | |
4116 | int ret; | |
4117 | ||
719b530c | 4118 | cfg = irq_cfg(irq); |
5527de74 JR |
4119 | if (!cfg) |
4120 | return -EINVAL; | |
4121 | ||
0dfedd61 | 4122 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4123 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4124 | devid = get_ioapic_devid(ioapic_id); | |
4125 | ||
4126 | if (devid < 0) | |
4127 | return devid; | |
4128 | ||
4129 | table = get_irq_table(devid, true); | |
4130 | if (table == NULL) | |
4131 | return -ENOMEM; | |
4132 | ||
4133 | index = attr->ioapic_pin; | |
4134 | ||
4135 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4136 | cfg->remapped = 1; |
0dfedd61 JR |
4137 | irte_info->devid = devid; |
4138 | irte_info->index = index; | |
5527de74 JR |
4139 | |
4140 | /* Setup IRTE for IOMMU */ | |
4141 | irte.val = 0; | |
4142 | irte.fields.vector = vector; | |
4143 | irte.fields.int_type = apic->irq_delivery_mode; | |
4144 | irte.fields.destination = destination; | |
4145 | irte.fields.dm = apic->irq_dest_mode; | |
4146 | irte.fields.valid = 1; | |
4147 | ||
4148 | ret = modify_irte(devid, index, irte); | |
4149 | if (ret) | |
4150 | return ret; | |
4151 | ||
4152 | /* Setup IOAPIC entry */ | |
4153 | memset(entry, 0, sizeof(*entry)); | |
4154 | ||
4155 | entry->vector = index; | |
4156 | entry->mask = 0; | |
4157 | entry->trigger = attr->trigger; | |
4158 | entry->polarity = attr->polarity; | |
4159 | ||
4160 | /* | |
4161 | * Mask level triggered irqs. | |
5527de74 JR |
4162 | */ |
4163 | if (attr->trigger) | |
4164 | entry->mask = 1; | |
4165 | ||
4166 | return 0; | |
4167 | } | |
4168 | ||
4169 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4170 | bool force) | |
4171 | { | |
0dfedd61 | 4172 | struct irq_2_irte *irte_info; |
5527de74 JR |
4173 | unsigned int dest, irq; |
4174 | struct irq_cfg *cfg; | |
4175 | union irte irte; | |
4176 | int err; | |
4177 | ||
4178 | if (!config_enabled(CONFIG_SMP)) | |
4179 | return -1; | |
4180 | ||
719b530c | 4181 | cfg = irqd_cfg(data); |
5527de74 | 4182 | irq = data->irq; |
0dfedd61 | 4183 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4184 | |
4185 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4186 | return -EINVAL; | |
4187 | ||
0dfedd61 | 4188 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4189 | return -EBUSY; |
4190 | ||
4191 | if (assign_irq_vector(irq, cfg, mask)) | |
4192 | return -EBUSY; | |
4193 | ||
4194 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4195 | if (err) { | |
4196 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4197 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4198 | return err; | |
4199 | } | |
4200 | ||
4201 | irte.fields.vector = cfg->vector; | |
4202 | irte.fields.destination = dest; | |
4203 | ||
0dfedd61 | 4204 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4205 | |
4206 | if (cfg->move_in_progress) | |
4207 | send_cleanup_vector(cfg); | |
4208 | ||
4209 | cpumask_copy(data->affinity, mask); | |
4210 | ||
4211 | return 0; | |
4212 | } | |
4213 | ||
4214 | static int free_irq(int irq) | |
4215 | { | |
0dfedd61 | 4216 | struct irq_2_irte *irte_info; |
5527de74 JR |
4217 | struct irq_cfg *cfg; |
4218 | ||
719b530c | 4219 | cfg = irq_cfg(irq); |
5527de74 JR |
4220 | if (!cfg) |
4221 | return -EINVAL; | |
4222 | ||
0dfedd61 | 4223 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4224 | |
0dfedd61 | 4225 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4226 | |
4227 | return 0; | |
4228 | } | |
4229 | ||
0b4d48cb JR |
4230 | static void compose_msi_msg(struct pci_dev *pdev, |
4231 | unsigned int irq, unsigned int dest, | |
4232 | struct msi_msg *msg, u8 hpet_id) | |
4233 | { | |
0dfedd61 | 4234 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4235 | struct irq_cfg *cfg; |
4236 | union irte irte; | |
4237 | ||
719b530c | 4238 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4239 | if (!cfg) |
4240 | return; | |
4241 | ||
0dfedd61 | 4242 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4243 | |
4244 | irte.val = 0; | |
4245 | irte.fields.vector = cfg->vector; | |
4246 | irte.fields.int_type = apic->irq_delivery_mode; | |
4247 | irte.fields.destination = dest; | |
4248 | irte.fields.dm = apic->irq_dest_mode; | |
4249 | irte.fields.valid = 1; | |
4250 | ||
0dfedd61 | 4251 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4252 | |
4253 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4254 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4255 | msg->data = irte_info->index; |
0b4d48cb JR |
4256 | } |
4257 | ||
4258 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4259 | { | |
4260 | struct irq_cfg *cfg; | |
4261 | int index; | |
4262 | u16 devid; | |
4263 | ||
4264 | if (!pdev) | |
4265 | return -EINVAL; | |
4266 | ||
719b530c | 4267 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4268 | if (!cfg) |
4269 | return -EINVAL; | |
4270 | ||
4271 | devid = get_device_id(&pdev->dev); | |
4272 | index = alloc_irq_index(cfg, devid, nvec); | |
4273 | ||
4274 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4275 | } | |
4276 | ||
4277 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4278 | int index, int offset) | |
4279 | { | |
0dfedd61 | 4280 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4281 | struct irq_cfg *cfg; |
4282 | u16 devid; | |
4283 | ||
4284 | if (!pdev) | |
4285 | return -EINVAL; | |
4286 | ||
719b530c | 4287 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4288 | if (!cfg) |
4289 | return -EINVAL; | |
4290 | ||
4291 | if (index >= MAX_IRQS_PER_TABLE) | |
4292 | return 0; | |
4293 | ||
4294 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4295 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4296 | |
9b1b0e42 | 4297 | cfg->remapped = 1; |
0dfedd61 JR |
4298 | irte_info->devid = devid; |
4299 | irte_info->index = index + offset; | |
0b4d48cb JR |
4300 | |
4301 | return 0; | |
4302 | } | |
4303 | ||
5fc24d8c | 4304 | static int alloc_hpet_msi(unsigned int irq, unsigned int id) |
d976195c | 4305 | { |
0dfedd61 | 4306 | struct irq_2_irte *irte_info; |
d976195c JR |
4307 | struct irq_cfg *cfg; |
4308 | int index, devid; | |
4309 | ||
719b530c | 4310 | cfg = irq_cfg(irq); |
d976195c JR |
4311 | if (!cfg) |
4312 | return -EINVAL; | |
4313 | ||
0dfedd61 | 4314 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4315 | devid = get_hpet_devid(id); |
4316 | if (devid < 0) | |
4317 | return devid; | |
4318 | ||
4319 | index = alloc_irq_index(cfg, devid, 1); | |
4320 | if (index < 0) | |
4321 | return index; | |
4322 | ||
9b1b0e42 | 4323 | cfg->remapped = 1; |
0dfedd61 JR |
4324 | irte_info->devid = devid; |
4325 | irte_info->index = index; | |
d976195c JR |
4326 | |
4327 | return 0; | |
4328 | } | |
4329 | ||
6b474b82 | 4330 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4331 | .prepare = amd_iommu_prepare, |
4332 | .enable = amd_iommu_enable, | |
4333 | .disable = amd_iommu_disable, | |
4334 | .reenable = amd_iommu_reenable, | |
4335 | .enable_faulting = amd_iommu_enable_faulting, | |
4336 | .setup_ioapic_entry = setup_ioapic_entry, | |
4337 | .set_affinity = set_affinity, | |
4338 | .free_irq = free_irq, | |
4339 | .compose_msi_msg = compose_msi_msg, | |
4340 | .msi_alloc_irq = msi_alloc_irq, | |
4341 | .msi_setup_irq = msi_setup_irq, | |
5fc24d8c | 4342 | .alloc_hpet_msi = alloc_hpet_msi, |
6b474b82 | 4343 | }; |
2b324506 | 4344 | #endif |