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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
b6c02715 JR |
47 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
48 | ||
bd60b735 JR |
49 | /* A list of preallocated protection domains */ |
50 | static LIST_HEAD(iommu_pd_list); | |
51 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
52 | ||
8fa5f802 JR |
53 | /* List of all available dev_data structures */ |
54 | static LIST_HEAD(dev_data_list); | |
55 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
56 | ||
0feae533 JR |
57 | /* |
58 | * Domain for untranslated devices - only allocated | |
59 | * if iommu=pt passed on kernel cmd line. | |
60 | */ | |
61 | static struct protection_domain *pt_domain; | |
62 | ||
26961efe | 63 | static struct iommu_ops amd_iommu_ops; |
26961efe | 64 | |
72e1dcc4 | 65 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 66 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 67 | |
431b2a20 JR |
68 | /* |
69 | * general struct to manage commands send to an IOMMU | |
70 | */ | |
d6449536 | 71 | struct iommu_cmd { |
b6c02715 JR |
72 | u32 data[4]; |
73 | }; | |
74 | ||
04bfdd84 | 75 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 76 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 77 | |
15898bbc JR |
78 | /**************************************************************************** |
79 | * | |
80 | * Helper functions | |
81 | * | |
82 | ****************************************************************************/ | |
83 | ||
f62dda66 | 84 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
85 | { |
86 | struct iommu_dev_data *dev_data; | |
87 | unsigned long flags; | |
88 | ||
89 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
90 | if (!dev_data) | |
91 | return NULL; | |
92 | ||
f62dda66 | 93 | dev_data->devid = devid; |
8fa5f802 JR |
94 | atomic_set(&dev_data->bind, 0); |
95 | ||
96 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
97 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
98 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
99 | ||
100 | return dev_data; | |
101 | } | |
102 | ||
103 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
104 | { | |
105 | unsigned long flags; | |
106 | ||
107 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
108 | list_del(&dev_data->dev_data_list); | |
109 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
110 | ||
111 | kfree(dev_data); | |
112 | } | |
113 | ||
3b03bb74 JR |
114 | static struct iommu_dev_data *search_dev_data(u16 devid) |
115 | { | |
116 | struct iommu_dev_data *dev_data; | |
117 | unsigned long flags; | |
118 | ||
119 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
120 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
121 | if (dev_data->devid == devid) | |
122 | goto out_unlock; | |
123 | } | |
124 | ||
125 | dev_data = NULL; | |
126 | ||
127 | out_unlock: | |
128 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
129 | ||
130 | return dev_data; | |
131 | } | |
132 | ||
133 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
134 | { | |
135 | struct iommu_dev_data *dev_data; | |
136 | ||
137 | dev_data = search_dev_data(devid); | |
138 | ||
139 | if (dev_data == NULL) | |
140 | dev_data = alloc_dev_data(devid); | |
141 | ||
142 | return dev_data; | |
143 | } | |
144 | ||
15898bbc JR |
145 | static inline u16 get_device_id(struct device *dev) |
146 | { | |
147 | struct pci_dev *pdev = to_pci_dev(dev); | |
148 | ||
149 | return calc_devid(pdev->bus->number, pdev->devfn); | |
150 | } | |
151 | ||
657cbb6b JR |
152 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
153 | { | |
154 | return dev->archdata.iommu; | |
155 | } | |
156 | ||
5abcdba4 JR |
157 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
158 | { | |
159 | static const int caps[] = { | |
160 | PCI_EXT_CAP_ID_ATS, | |
161 | PCI_PRI_CAP, | |
162 | PCI_PASID_CAP, | |
163 | }; | |
164 | int i, pos; | |
165 | ||
166 | for (i = 0; i < 3; ++i) { | |
167 | pos = pci_find_ext_capability(pdev, caps[i]); | |
168 | if (pos == 0) | |
169 | return false; | |
170 | } | |
171 | ||
172 | return true; | |
173 | } | |
174 | ||
6a113ddc JR |
175 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
176 | { | |
177 | struct iommu_dev_data *dev_data; | |
178 | ||
179 | dev_data = get_dev_data(&pdev->dev); | |
180 | ||
181 | return dev_data->errata & (1 << erratum) ? true : false; | |
182 | } | |
183 | ||
71c70984 JR |
184 | /* |
185 | * In this function the list of preallocated protection domains is traversed to | |
186 | * find the domain for a specific device | |
187 | */ | |
188 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
189 | { | |
190 | struct dma_ops_domain *entry, *ret = NULL; | |
191 | unsigned long flags; | |
192 | u16 alias = amd_iommu_alias_table[devid]; | |
193 | ||
194 | if (list_empty(&iommu_pd_list)) | |
195 | return NULL; | |
196 | ||
197 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
198 | ||
199 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
200 | if (entry->target_dev == devid || | |
201 | entry->target_dev == alias) { | |
202 | ret = entry; | |
203 | break; | |
204 | } | |
205 | } | |
206 | ||
207 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
208 | ||
209 | return ret; | |
210 | } | |
211 | ||
98fc5a69 JR |
212 | /* |
213 | * This function checks if the driver got a valid device from the caller to | |
214 | * avoid dereferencing invalid pointers. | |
215 | */ | |
216 | static bool check_device(struct device *dev) | |
217 | { | |
218 | u16 devid; | |
219 | ||
220 | if (!dev || !dev->dma_mask) | |
221 | return false; | |
222 | ||
223 | /* No device or no PCI device */ | |
339d3261 | 224 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
225 | return false; |
226 | ||
227 | devid = get_device_id(dev); | |
228 | ||
229 | /* Out of our scope? */ | |
230 | if (devid > amd_iommu_last_bdf) | |
231 | return false; | |
232 | ||
233 | if (amd_iommu_rlookup_table[devid] == NULL) | |
234 | return false; | |
235 | ||
236 | return true; | |
237 | } | |
238 | ||
657cbb6b JR |
239 | static int iommu_init_device(struct device *dev) |
240 | { | |
5abcdba4 | 241 | struct pci_dev *pdev = to_pci_dev(dev); |
657cbb6b | 242 | struct iommu_dev_data *dev_data; |
8fa5f802 | 243 | u16 alias; |
657cbb6b JR |
244 | |
245 | if (dev->archdata.iommu) | |
246 | return 0; | |
247 | ||
3b03bb74 | 248 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
249 | if (!dev_data) |
250 | return -ENOMEM; | |
251 | ||
f62dda66 | 252 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 253 | if (alias != dev_data->devid) { |
71f77580 | 254 | struct iommu_dev_data *alias_data; |
b00d3bcf | 255 | |
71f77580 JR |
256 | alias_data = find_dev_data(alias); |
257 | if (alias_data == NULL) { | |
258 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
259 | dev_name(dev)); | |
2b02b091 JR |
260 | free_dev_data(dev_data); |
261 | return -ENOTSUPP; | |
262 | } | |
71f77580 | 263 | dev_data->alias_data = alias_data; |
26018874 | 264 | } |
657cbb6b | 265 | |
5abcdba4 JR |
266 | if (pci_iommuv2_capable(pdev)) { |
267 | struct amd_iommu *iommu; | |
268 | ||
269 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
270 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
271 | } | |
272 | ||
657cbb6b JR |
273 | dev->archdata.iommu = dev_data; |
274 | ||
657cbb6b JR |
275 | return 0; |
276 | } | |
277 | ||
26018874 JR |
278 | static void iommu_ignore_device(struct device *dev) |
279 | { | |
280 | u16 devid, alias; | |
281 | ||
282 | devid = get_device_id(dev); | |
283 | alias = amd_iommu_alias_table[devid]; | |
284 | ||
285 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
286 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
287 | ||
288 | amd_iommu_rlookup_table[devid] = NULL; | |
289 | amd_iommu_rlookup_table[alias] = NULL; | |
290 | } | |
291 | ||
657cbb6b JR |
292 | static void iommu_uninit_device(struct device *dev) |
293 | { | |
8fa5f802 JR |
294 | /* |
295 | * Nothing to do here - we keep dev_data around for unplugged devices | |
296 | * and reuse it when the device is re-plugged - not doing so would | |
297 | * introduce a ton of races. | |
298 | */ | |
657cbb6b | 299 | } |
b7cc9554 JR |
300 | |
301 | void __init amd_iommu_uninit_devices(void) | |
302 | { | |
8fa5f802 | 303 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
304 | struct pci_dev *pdev = NULL; |
305 | ||
306 | for_each_pci_dev(pdev) { | |
307 | ||
308 | if (!check_device(&pdev->dev)) | |
309 | continue; | |
310 | ||
311 | iommu_uninit_device(&pdev->dev); | |
312 | } | |
8fa5f802 JR |
313 | |
314 | /* Free all of our dev_data structures */ | |
315 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
316 | free_dev_data(dev_data); | |
b7cc9554 JR |
317 | } |
318 | ||
319 | int __init amd_iommu_init_devices(void) | |
320 | { | |
321 | struct pci_dev *pdev = NULL; | |
322 | int ret = 0; | |
323 | ||
324 | for_each_pci_dev(pdev) { | |
325 | ||
326 | if (!check_device(&pdev->dev)) | |
327 | continue; | |
328 | ||
329 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
330 | if (ret == -ENOTSUPP) |
331 | iommu_ignore_device(&pdev->dev); | |
332 | else if (ret) | |
b7cc9554 JR |
333 | goto out_free; |
334 | } | |
335 | ||
336 | return 0; | |
337 | ||
338 | out_free: | |
339 | ||
340 | amd_iommu_uninit_devices(); | |
341 | ||
342 | return ret; | |
343 | } | |
7f26508b JR |
344 | #ifdef CONFIG_AMD_IOMMU_STATS |
345 | ||
346 | /* | |
347 | * Initialization code for statistics collection | |
348 | */ | |
349 | ||
da49f6df | 350 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 351 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 352 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 353 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 354 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 355 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 356 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 357 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 358 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 359 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 360 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 361 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 362 | |
7f26508b | 363 | static struct dentry *stats_dir; |
7f26508b JR |
364 | static struct dentry *de_fflush; |
365 | ||
366 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
367 | { | |
368 | if (stats_dir == NULL) | |
369 | return; | |
370 | ||
371 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
372 | &cnt->value); | |
373 | } | |
374 | ||
375 | static void amd_iommu_stats_init(void) | |
376 | { | |
377 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
378 | if (stats_dir == NULL) | |
379 | return; | |
380 | ||
7f26508b JR |
381 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
382 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
383 | |
384 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 385 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 386 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 387 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 388 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 389 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 390 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 391 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 392 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 393 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 394 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 395 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
396 | } |
397 | ||
398 | #endif | |
399 | ||
a80dc3e0 JR |
400 | /**************************************************************************** |
401 | * | |
402 | * Interrupt handling functions | |
403 | * | |
404 | ****************************************************************************/ | |
405 | ||
e3e59876 JR |
406 | static void dump_dte_entry(u16 devid) |
407 | { | |
408 | int i; | |
409 | ||
ee6c2868 JR |
410 | for (i = 0; i < 4; ++i) |
411 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
412 | amd_iommu_dev_table[devid].data[i]); |
413 | } | |
414 | ||
945b4ac4 JR |
415 | static void dump_command(unsigned long phys_addr) |
416 | { | |
417 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
418 | int i; | |
419 | ||
420 | for (i = 0; i < 4; ++i) | |
421 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
422 | } | |
423 | ||
a345b23b | 424 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
425 | { |
426 | u32 *event = __evt; | |
427 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
428 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
429 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
430 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
431 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
432 | ||
4c6f40d4 | 433 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
434 | |
435 | switch (type) { | |
436 | case EVENT_TYPE_ILL_DEV: | |
437 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
438 | "address=0x%016llx flags=0x%04x]\n", | |
439 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
440 | address, flags); | |
e3e59876 | 441 | dump_dte_entry(devid); |
90008ee4 JR |
442 | break; |
443 | case EVENT_TYPE_IO_FAULT: | |
444 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
445 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
446 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
447 | domid, address, flags); | |
448 | break; | |
449 | case EVENT_TYPE_DEV_TAB_ERR: | |
450 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
451 | "address=0x%016llx flags=0x%04x]\n", | |
452 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
453 | address, flags); | |
454 | break; | |
455 | case EVENT_TYPE_PAGE_TAB_ERR: | |
456 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
457 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
458 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
459 | domid, address, flags); | |
460 | break; | |
461 | case EVENT_TYPE_ILL_CMD: | |
462 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 463 | dump_command(address); |
90008ee4 JR |
464 | break; |
465 | case EVENT_TYPE_CMD_HARD_ERR: | |
466 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
467 | "flags=0x%04x]\n", address, flags); | |
468 | break; | |
469 | case EVENT_TYPE_IOTLB_INV_TO: | |
470 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
471 | "address=0x%016llx]\n", | |
472 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
473 | address); | |
474 | break; | |
475 | case EVENT_TYPE_INV_DEV_REQ: | |
476 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
477 | "address=0x%016llx flags=0x%04x]\n", | |
478 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
479 | address, flags); | |
480 | break; | |
481 | default: | |
482 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
483 | } | |
484 | } | |
485 | ||
486 | static void iommu_poll_events(struct amd_iommu *iommu) | |
487 | { | |
488 | u32 head, tail; | |
489 | unsigned long flags; | |
490 | ||
491 | spin_lock_irqsave(&iommu->lock, flags); | |
492 | ||
493 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
494 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
495 | ||
496 | while (head != tail) { | |
a345b23b | 497 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
498 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
499 | } | |
500 | ||
501 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
502 | ||
503 | spin_unlock_irqrestore(&iommu->lock, flags); | |
504 | } | |
505 | ||
72e1dcc4 JR |
506 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head) |
507 | { | |
508 | struct amd_iommu_fault fault; | |
509 | volatile u64 *raw; | |
510 | int i; | |
511 | ||
512 | raw = (u64 *)(iommu->ppr_log + head); | |
513 | ||
514 | /* | |
515 | * Hardware bug: Interrupt may arrive before the entry is written to | |
516 | * memory. If this happens we need to wait for the entry to arrive. | |
517 | */ | |
518 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
519 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
520 | break; | |
521 | udelay(1); | |
522 | } | |
523 | ||
524 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { | |
525 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
526 | return; | |
527 | } | |
528 | ||
529 | fault.address = raw[1]; | |
530 | fault.pasid = PPR_PASID(raw[0]); | |
531 | fault.device_id = PPR_DEVID(raw[0]); | |
532 | fault.tag = PPR_TAG(raw[0]); | |
533 | fault.flags = PPR_FLAGS(raw[0]); | |
534 | ||
535 | /* | |
536 | * To detect the hardware bug we need to clear the entry | |
537 | * to back to zero. | |
538 | */ | |
539 | raw[0] = raw[1] = 0; | |
540 | ||
541 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); | |
542 | } | |
543 | ||
544 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
545 | { | |
546 | unsigned long flags; | |
547 | u32 head, tail; | |
548 | ||
549 | if (iommu->ppr_log == NULL) | |
550 | return; | |
551 | ||
552 | spin_lock_irqsave(&iommu->lock, flags); | |
553 | ||
554 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
555 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
556 | ||
557 | while (head != tail) { | |
558 | ||
559 | /* Handle PPR entry */ | |
560 | iommu_handle_ppr_entry(iommu, head); | |
561 | ||
562 | /* Update and refresh ring-buffer state*/ | |
563 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; | |
564 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
565 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
566 | } | |
567 | ||
568 | /* enable ppr interrupts again */ | |
569 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
570 | ||
571 | spin_unlock_irqrestore(&iommu->lock, flags); | |
572 | } | |
573 | ||
72fe00f0 | 574 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 575 | { |
90008ee4 JR |
576 | struct amd_iommu *iommu; |
577 | ||
72e1dcc4 | 578 | for_each_iommu(iommu) { |
90008ee4 | 579 | iommu_poll_events(iommu); |
72e1dcc4 JR |
580 | iommu_poll_ppr_log(iommu); |
581 | } | |
90008ee4 JR |
582 | |
583 | return IRQ_HANDLED; | |
a80dc3e0 JR |
584 | } |
585 | ||
72fe00f0 JR |
586 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
587 | { | |
588 | return IRQ_WAKE_THREAD; | |
589 | } | |
590 | ||
431b2a20 JR |
591 | /**************************************************************************** |
592 | * | |
593 | * IOMMU command queuing functions | |
594 | * | |
595 | ****************************************************************************/ | |
596 | ||
ac0ea6e9 JR |
597 | static int wait_on_sem(volatile u64 *sem) |
598 | { | |
599 | int i = 0; | |
600 | ||
601 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
602 | udelay(1); | |
603 | i += 1; | |
604 | } | |
605 | ||
606 | if (i == LOOP_TIMEOUT) { | |
607 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
608 | return -EIO; | |
609 | } | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
615 | struct iommu_cmd *cmd, | |
616 | u32 tail) | |
a19ae1ec | 617 | { |
a19ae1ec JR |
618 | u8 *target; |
619 | ||
8a7c5ef3 | 620 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
621 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
622 | ||
623 | /* Copy command to buffer */ | |
624 | memcpy(target, cmd, sizeof(*cmd)); | |
625 | ||
626 | /* Tell the IOMMU about it */ | |
a19ae1ec | 627 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 628 | } |
a19ae1ec | 629 | |
815b33fd | 630 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 631 | { |
815b33fd JR |
632 | WARN_ON(address & 0x7ULL); |
633 | ||
ded46737 | 634 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
635 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
636 | cmd->data[1] = upper_32_bits(__pa(address)); | |
637 | cmd->data[2] = 1; | |
ded46737 JR |
638 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
639 | } | |
640 | ||
94fe79e2 JR |
641 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
642 | { | |
643 | memset(cmd, 0, sizeof(*cmd)); | |
644 | cmd->data[0] = devid; | |
645 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
646 | } | |
647 | ||
11b6402c JR |
648 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
649 | size_t size, u16 domid, int pde) | |
650 | { | |
651 | u64 pages; | |
652 | int s; | |
653 | ||
654 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
655 | s = 0; | |
656 | ||
657 | if (pages > 1) { | |
658 | /* | |
659 | * If we have to flush more than one page, flush all | |
660 | * TLB entries for this domain | |
661 | */ | |
662 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
663 | s = 1; | |
664 | } | |
665 | ||
666 | address &= PAGE_MASK; | |
667 | ||
668 | memset(cmd, 0, sizeof(*cmd)); | |
669 | cmd->data[1] |= domid; | |
670 | cmd->data[2] = lower_32_bits(address); | |
671 | cmd->data[3] = upper_32_bits(address); | |
672 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
673 | if (s) /* size bit - we flush more than one 4kb page */ | |
674 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
675 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
676 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
677 | } | |
678 | ||
cb41ed85 JR |
679 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
680 | u64 address, size_t size) | |
681 | { | |
682 | u64 pages; | |
683 | int s; | |
684 | ||
685 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
686 | s = 0; | |
687 | ||
688 | if (pages > 1) { | |
689 | /* | |
690 | * If we have to flush more than one page, flush all | |
691 | * TLB entries for this domain | |
692 | */ | |
693 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
694 | s = 1; | |
695 | } | |
696 | ||
697 | address &= PAGE_MASK; | |
698 | ||
699 | memset(cmd, 0, sizeof(*cmd)); | |
700 | cmd->data[0] = devid; | |
701 | cmd->data[0] |= (qdep & 0xff) << 24; | |
702 | cmd->data[1] = devid; | |
703 | cmd->data[2] = lower_32_bits(address); | |
704 | cmd->data[3] = upper_32_bits(address); | |
705 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
706 | if (s) | |
707 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
708 | } | |
709 | ||
22e266c7 JR |
710 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
711 | u64 address, bool size) | |
712 | { | |
713 | memset(cmd, 0, sizeof(*cmd)); | |
714 | ||
715 | address &= ~(0xfffULL); | |
716 | ||
717 | cmd->data[0] = pasid & PASID_MASK; | |
718 | cmd->data[1] = domid; | |
719 | cmd->data[2] = lower_32_bits(address); | |
720 | cmd->data[3] = upper_32_bits(address); | |
721 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
722 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
723 | if (size) | |
724 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
725 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
726 | } | |
727 | ||
728 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
729 | int qdep, u64 address, bool size) | |
730 | { | |
731 | memset(cmd, 0, sizeof(*cmd)); | |
732 | ||
733 | address &= ~(0xfffULL); | |
734 | ||
735 | cmd->data[0] = devid; | |
736 | cmd->data[0] |= (pasid & 0xff) << 16; | |
737 | cmd->data[0] |= (qdep & 0xff) << 24; | |
738 | cmd->data[1] = devid; | |
739 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
740 | cmd->data[2] = lower_32_bits(address); | |
741 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
742 | cmd->data[3] = upper_32_bits(address); | |
743 | if (size) | |
744 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
745 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
746 | } | |
747 | ||
c99afa25 JR |
748 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
749 | int status, int tag, bool gn) | |
750 | { | |
751 | memset(cmd, 0, sizeof(*cmd)); | |
752 | ||
753 | cmd->data[0] = devid; | |
754 | if (gn) { | |
755 | cmd->data[1] = pasid & PASID_MASK; | |
756 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
757 | } | |
758 | cmd->data[3] = tag & 0x1ff; | |
759 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
760 | ||
761 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
762 | } | |
763 | ||
58fc7f14 JR |
764 | static void build_inv_all(struct iommu_cmd *cmd) |
765 | { | |
766 | memset(cmd, 0, sizeof(*cmd)); | |
767 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
768 | } |
769 | ||
431b2a20 | 770 | /* |
431b2a20 | 771 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 772 | * hardware about the new command. |
431b2a20 | 773 | */ |
f1ca1512 JR |
774 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
775 | struct iommu_cmd *cmd, | |
776 | bool sync) | |
a19ae1ec | 777 | { |
ac0ea6e9 | 778 | u32 left, tail, head, next_tail; |
a19ae1ec | 779 | unsigned long flags; |
a19ae1ec | 780 | |
549c90dc | 781 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
782 | |
783 | again: | |
a19ae1ec | 784 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 785 | |
ac0ea6e9 JR |
786 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
787 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
788 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
789 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 790 | |
ac0ea6e9 JR |
791 | if (left <= 2) { |
792 | struct iommu_cmd sync_cmd; | |
793 | volatile u64 sem = 0; | |
794 | int ret; | |
8d201968 | 795 | |
ac0ea6e9 JR |
796 | build_completion_wait(&sync_cmd, (u64)&sem); |
797 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 798 | |
ac0ea6e9 JR |
799 | spin_unlock_irqrestore(&iommu->lock, flags); |
800 | ||
801 | if ((ret = wait_on_sem(&sem)) != 0) | |
802 | return ret; | |
803 | ||
804 | goto again; | |
8d201968 JR |
805 | } |
806 | ||
ac0ea6e9 JR |
807 | copy_cmd_to_buffer(iommu, cmd, tail); |
808 | ||
809 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 810 | iommu->need_sync = sync; |
ac0ea6e9 | 811 | |
a19ae1ec | 812 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 813 | |
815b33fd | 814 | return 0; |
8d201968 JR |
815 | } |
816 | ||
f1ca1512 JR |
817 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
818 | { | |
819 | return iommu_queue_command_sync(iommu, cmd, true); | |
820 | } | |
821 | ||
8d201968 JR |
822 | /* |
823 | * This function queues a completion wait command into the command | |
824 | * buffer of an IOMMU | |
825 | */ | |
a19ae1ec | 826 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
827 | { |
828 | struct iommu_cmd cmd; | |
815b33fd | 829 | volatile u64 sem = 0; |
ac0ea6e9 | 830 | int ret; |
8d201968 | 831 | |
09ee17eb | 832 | if (!iommu->need_sync) |
815b33fd | 833 | return 0; |
09ee17eb | 834 | |
815b33fd | 835 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 836 | |
f1ca1512 | 837 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 838 | if (ret) |
815b33fd | 839 | return ret; |
8d201968 | 840 | |
ac0ea6e9 | 841 | return wait_on_sem(&sem); |
8d201968 JR |
842 | } |
843 | ||
d8c13085 | 844 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 845 | { |
d8c13085 | 846 | struct iommu_cmd cmd; |
a19ae1ec | 847 | |
d8c13085 | 848 | build_inv_dte(&cmd, devid); |
7e4f88da | 849 | |
d8c13085 JR |
850 | return iommu_queue_command(iommu, &cmd); |
851 | } | |
09ee17eb | 852 | |
7d0c5cc5 JR |
853 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
854 | { | |
855 | u32 devid; | |
09ee17eb | 856 | |
7d0c5cc5 JR |
857 | for (devid = 0; devid <= 0xffff; ++devid) |
858 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 859 | |
7d0c5cc5 JR |
860 | iommu_completion_wait(iommu); |
861 | } | |
84df8175 | 862 | |
7d0c5cc5 JR |
863 | /* |
864 | * This function uses heavy locking and may disable irqs for some time. But | |
865 | * this is no issue because it is only called during resume. | |
866 | */ | |
867 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
868 | { | |
869 | u32 dom_id; | |
a19ae1ec | 870 | |
7d0c5cc5 JR |
871 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
872 | struct iommu_cmd cmd; | |
873 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
874 | dom_id, 1); | |
875 | iommu_queue_command(iommu, &cmd); | |
876 | } | |
8eed9833 | 877 | |
7d0c5cc5 | 878 | iommu_completion_wait(iommu); |
a19ae1ec JR |
879 | } |
880 | ||
58fc7f14 | 881 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 882 | { |
58fc7f14 | 883 | struct iommu_cmd cmd; |
0518a3a4 | 884 | |
58fc7f14 | 885 | build_inv_all(&cmd); |
0518a3a4 | 886 | |
58fc7f14 JR |
887 | iommu_queue_command(iommu, &cmd); |
888 | iommu_completion_wait(iommu); | |
889 | } | |
890 | ||
7d0c5cc5 JR |
891 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
892 | { | |
58fc7f14 JR |
893 | if (iommu_feature(iommu, FEATURE_IA)) { |
894 | iommu_flush_all(iommu); | |
895 | } else { | |
896 | iommu_flush_dte_all(iommu); | |
897 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
898 | } |
899 | } | |
900 | ||
431b2a20 | 901 | /* |
cb41ed85 | 902 | * Command send function for flushing on-device TLB |
431b2a20 | 903 | */ |
6c542047 JR |
904 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
905 | u64 address, size_t size) | |
3fa43655 JR |
906 | { |
907 | struct amd_iommu *iommu; | |
b00d3bcf | 908 | struct iommu_cmd cmd; |
cb41ed85 | 909 | int qdep; |
3fa43655 | 910 | |
ea61cddb JR |
911 | qdep = dev_data->ats.qdep; |
912 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 913 | |
ea61cddb | 914 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
915 | |
916 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
917 | } |
918 | ||
431b2a20 | 919 | /* |
431b2a20 | 920 | * Command send function for invalidating a device table entry |
431b2a20 | 921 | */ |
6c542047 | 922 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 923 | { |
3fa43655 | 924 | struct amd_iommu *iommu; |
ee2fa743 | 925 | int ret; |
a19ae1ec | 926 | |
6c542047 | 927 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 928 | |
f62dda66 | 929 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
930 | if (ret) |
931 | return ret; | |
932 | ||
ea61cddb | 933 | if (dev_data->ats.enabled) |
6c542047 | 934 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 935 | |
ee2fa743 | 936 | return ret; |
a19ae1ec JR |
937 | } |
938 | ||
431b2a20 JR |
939 | /* |
940 | * TLB invalidation function which is called from the mapping functions. | |
941 | * It invalidates a single PTE if the range to flush is within a single | |
942 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
943 | */ | |
17b124bf JR |
944 | static void __domain_flush_pages(struct protection_domain *domain, |
945 | u64 address, size_t size, int pde) | |
a19ae1ec | 946 | { |
cb41ed85 | 947 | struct iommu_dev_data *dev_data; |
11b6402c JR |
948 | struct iommu_cmd cmd; |
949 | int ret = 0, i; | |
a19ae1ec | 950 | |
11b6402c | 951 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 952 | |
6de8ad9b JR |
953 | for (i = 0; i < amd_iommus_present; ++i) { |
954 | if (!domain->dev_iommu[i]) | |
955 | continue; | |
956 | ||
957 | /* | |
958 | * Devices of this domain are behind this IOMMU | |
959 | * We need a TLB flush | |
960 | */ | |
11b6402c | 961 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
962 | } |
963 | ||
cb41ed85 | 964 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 965 | |
ea61cddb | 966 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
967 | continue; |
968 | ||
6c542047 | 969 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
970 | } |
971 | ||
11b6402c | 972 | WARN_ON(ret); |
6de8ad9b JR |
973 | } |
974 | ||
17b124bf JR |
975 | static void domain_flush_pages(struct protection_domain *domain, |
976 | u64 address, size_t size) | |
6de8ad9b | 977 | { |
17b124bf | 978 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 979 | } |
b6c02715 | 980 | |
1c655773 | 981 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 982 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 983 | { |
17b124bf | 984 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
985 | } |
986 | ||
42a49f96 | 987 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 988 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 989 | { |
17b124bf | 990 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
991 | } |
992 | ||
17b124bf | 993 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 994 | { |
17b124bf | 995 | int i; |
18811f55 | 996 | |
17b124bf JR |
997 | for (i = 0; i < amd_iommus_present; ++i) { |
998 | if (!domain->dev_iommu[i]) | |
999 | continue; | |
bfd1be18 | 1000 | |
17b124bf JR |
1001 | /* |
1002 | * Devices of this domain are behind this IOMMU | |
1003 | * We need to wait for completion of all commands. | |
1004 | */ | |
1005 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1006 | } |
e394d72a JR |
1007 | } |
1008 | ||
b00d3bcf | 1009 | |
09b42804 | 1010 | /* |
b00d3bcf | 1011 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1012 | */ |
17b124bf | 1013 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1014 | { |
b00d3bcf | 1015 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1016 | |
b00d3bcf | 1017 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1018 | device_flush_dte(dev_data); |
a345b23b JR |
1019 | } |
1020 | ||
431b2a20 JR |
1021 | /**************************************************************************** |
1022 | * | |
1023 | * The functions below are used the create the page table mappings for | |
1024 | * unity mapped regions. | |
1025 | * | |
1026 | ****************************************************************************/ | |
1027 | ||
308973d3 JR |
1028 | /* |
1029 | * This function is used to add another level to an IO page table. Adding | |
1030 | * another level increases the size of the address space by 9 bits to a size up | |
1031 | * to 64 bits. | |
1032 | */ | |
1033 | static bool increase_address_space(struct protection_domain *domain, | |
1034 | gfp_t gfp) | |
1035 | { | |
1036 | u64 *pte; | |
1037 | ||
1038 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1039 | /* address space already 64 bit large */ | |
1040 | return false; | |
1041 | ||
1042 | pte = (void *)get_zeroed_page(gfp); | |
1043 | if (!pte) | |
1044 | return false; | |
1045 | ||
1046 | *pte = PM_LEVEL_PDE(domain->mode, | |
1047 | virt_to_phys(domain->pt_root)); | |
1048 | domain->pt_root = pte; | |
1049 | domain->mode += 1; | |
1050 | domain->updated = true; | |
1051 | ||
1052 | return true; | |
1053 | } | |
1054 | ||
1055 | static u64 *alloc_pte(struct protection_domain *domain, | |
1056 | unsigned long address, | |
cbb9d729 | 1057 | unsigned long page_size, |
308973d3 JR |
1058 | u64 **pte_page, |
1059 | gfp_t gfp) | |
1060 | { | |
cbb9d729 | 1061 | int level, end_lvl; |
308973d3 | 1062 | u64 *pte, *page; |
cbb9d729 JR |
1063 | |
1064 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1065 | |
1066 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1067 | increase_address_space(domain, gfp); | |
1068 | ||
cbb9d729 JR |
1069 | level = domain->mode - 1; |
1070 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1071 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1072 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1073 | |
1074 | while (level > end_lvl) { | |
1075 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1076 | page = (u64 *)get_zeroed_page(gfp); | |
1077 | if (!page) | |
1078 | return NULL; | |
1079 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1080 | } | |
1081 | ||
cbb9d729 JR |
1082 | /* No level skipping support yet */ |
1083 | if (PM_PTE_LEVEL(*pte) != level) | |
1084 | return NULL; | |
1085 | ||
308973d3 JR |
1086 | level -= 1; |
1087 | ||
1088 | pte = IOMMU_PTE_PAGE(*pte); | |
1089 | ||
1090 | if (pte_page && level == end_lvl) | |
1091 | *pte_page = pte; | |
1092 | ||
1093 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1094 | } | |
1095 | ||
1096 | return pte; | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * This function checks if there is a PTE for a given dma address. If | |
1101 | * there is one, it returns the pointer to it. | |
1102 | */ | |
24cd7723 | 1103 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1104 | { |
1105 | int level; | |
1106 | u64 *pte; | |
1107 | ||
24cd7723 JR |
1108 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1109 | return NULL; | |
1110 | ||
1111 | level = domain->mode - 1; | |
1112 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1113 | |
24cd7723 JR |
1114 | while (level > 0) { |
1115 | ||
1116 | /* Not Present */ | |
308973d3 JR |
1117 | if (!IOMMU_PTE_PRESENT(*pte)) |
1118 | return NULL; | |
1119 | ||
24cd7723 JR |
1120 | /* Large PTE */ |
1121 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1122 | unsigned long pte_mask, __pte; | |
1123 | ||
1124 | /* | |
1125 | * If we have a series of large PTEs, make | |
1126 | * sure to return a pointer to the first one. | |
1127 | */ | |
1128 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1129 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1130 | __pte = ((unsigned long)pte) & pte_mask; | |
1131 | ||
1132 | return (u64 *)__pte; | |
1133 | } | |
1134 | ||
1135 | /* No level skipping support yet */ | |
1136 | if (PM_PTE_LEVEL(*pte) != level) | |
1137 | return NULL; | |
1138 | ||
308973d3 JR |
1139 | level -= 1; |
1140 | ||
24cd7723 | 1141 | /* Walk to the next level */ |
308973d3 JR |
1142 | pte = IOMMU_PTE_PAGE(*pte); |
1143 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1144 | } |
1145 | ||
1146 | return pte; | |
1147 | } | |
1148 | ||
431b2a20 JR |
1149 | /* |
1150 | * Generic mapping functions. It maps a physical address into a DMA | |
1151 | * address space. It allocates the page table pages if necessary. | |
1152 | * In the future it can be extended to a generic mapping function | |
1153 | * supporting all features of AMD IOMMU page tables like level skipping | |
1154 | * and full 64 bit address spaces. | |
1155 | */ | |
38e817fe JR |
1156 | static int iommu_map_page(struct protection_domain *dom, |
1157 | unsigned long bus_addr, | |
1158 | unsigned long phys_addr, | |
abdc5eb3 | 1159 | int prot, |
cbb9d729 | 1160 | unsigned long page_size) |
bd0e5211 | 1161 | { |
8bda3092 | 1162 | u64 __pte, *pte; |
cbb9d729 | 1163 | int i, count; |
abdc5eb3 | 1164 | |
bad1cac2 | 1165 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1166 | return -EINVAL; |
1167 | ||
cbb9d729 JR |
1168 | bus_addr = PAGE_ALIGN(bus_addr); |
1169 | phys_addr = PAGE_ALIGN(phys_addr); | |
1170 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1171 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1172 | ||
1173 | for (i = 0; i < count; ++i) | |
1174 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1175 | return -EBUSY; | |
bd0e5211 | 1176 | |
cbb9d729 JR |
1177 | if (page_size > PAGE_SIZE) { |
1178 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1179 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1180 | } else | |
1181 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1182 | |
bd0e5211 JR |
1183 | if (prot & IOMMU_PROT_IR) |
1184 | __pte |= IOMMU_PTE_IR; | |
1185 | if (prot & IOMMU_PROT_IW) | |
1186 | __pte |= IOMMU_PTE_IW; | |
1187 | ||
cbb9d729 JR |
1188 | for (i = 0; i < count; ++i) |
1189 | pte[i] = __pte; | |
bd0e5211 | 1190 | |
04bfdd84 JR |
1191 | update_domain(dom); |
1192 | ||
bd0e5211 JR |
1193 | return 0; |
1194 | } | |
1195 | ||
24cd7723 JR |
1196 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1197 | unsigned long bus_addr, | |
1198 | unsigned long page_size) | |
eb74ff6c | 1199 | { |
24cd7723 JR |
1200 | unsigned long long unmap_size, unmapped; |
1201 | u64 *pte; | |
1202 | ||
1203 | BUG_ON(!is_power_of_2(page_size)); | |
1204 | ||
1205 | unmapped = 0; | |
eb74ff6c | 1206 | |
24cd7723 JR |
1207 | while (unmapped < page_size) { |
1208 | ||
1209 | pte = fetch_pte(dom, bus_addr); | |
1210 | ||
1211 | if (!pte) { | |
1212 | /* | |
1213 | * No PTE for this address | |
1214 | * move forward in 4kb steps | |
1215 | */ | |
1216 | unmap_size = PAGE_SIZE; | |
1217 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1218 | /* 4kb PTE found for this address */ | |
1219 | unmap_size = PAGE_SIZE; | |
1220 | *pte = 0ULL; | |
1221 | } else { | |
1222 | int count, i; | |
1223 | ||
1224 | /* Large PTE found which maps this address */ | |
1225 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1226 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1227 | for (i = 0; i < count; i++) | |
1228 | pte[i] = 0ULL; | |
1229 | } | |
1230 | ||
1231 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1232 | unmapped += unmap_size; | |
1233 | } | |
1234 | ||
1235 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1236 | |
24cd7723 | 1237 | return unmapped; |
eb74ff6c | 1238 | } |
eb74ff6c | 1239 | |
431b2a20 JR |
1240 | /* |
1241 | * This function checks if a specific unity mapping entry is needed for | |
1242 | * this specific IOMMU. | |
1243 | */ | |
bd0e5211 JR |
1244 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1245 | struct unity_map_entry *entry) | |
1246 | { | |
1247 | u16 bdf, i; | |
1248 | ||
1249 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1250 | bdf = amd_iommu_alias_table[i]; | |
1251 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1252 | return 1; | |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
431b2a20 JR |
1258 | /* |
1259 | * This function actually applies the mapping to the page table of the | |
1260 | * dma_ops domain. | |
1261 | */ | |
bd0e5211 JR |
1262 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1263 | struct unity_map_entry *e) | |
1264 | { | |
1265 | u64 addr; | |
1266 | int ret; | |
1267 | ||
1268 | for (addr = e->address_start; addr < e->address_end; | |
1269 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1270 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1271 | PAGE_SIZE); |
bd0e5211 JR |
1272 | if (ret) |
1273 | return ret; | |
1274 | /* | |
1275 | * if unity mapping is in aperture range mark the page | |
1276 | * as allocated in the aperture | |
1277 | */ | |
1278 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1279 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1280 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1281 | } |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
171e7b37 JR |
1286 | /* |
1287 | * Init the unity mappings for a specific IOMMU in the system | |
1288 | * | |
1289 | * Basically iterates over all unity mapping entries and applies them to | |
1290 | * the default domain DMA of that IOMMU if necessary. | |
1291 | */ | |
1292 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1293 | { | |
1294 | struct unity_map_entry *entry; | |
1295 | int ret; | |
1296 | ||
1297 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1298 | if (!iommu_for_unity_map(iommu, entry)) | |
1299 | continue; | |
1300 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1301 | if (ret) | |
1302 | return ret; | |
1303 | } | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
431b2a20 JR |
1308 | /* |
1309 | * Inits the unity mappings required for a specific device | |
1310 | */ | |
bd0e5211 JR |
1311 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1312 | u16 devid) | |
1313 | { | |
1314 | struct unity_map_entry *e; | |
1315 | int ret; | |
1316 | ||
1317 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1318 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1319 | continue; | |
1320 | ret = dma_ops_unity_map(dma_dom, e); | |
1321 | if (ret) | |
1322 | return ret; | |
1323 | } | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
431b2a20 JR |
1328 | /**************************************************************************** |
1329 | * | |
1330 | * The next functions belong to the address allocator for the dma_ops | |
1331 | * interface functions. They work like the allocators in the other IOMMU | |
1332 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1333 | * the aperture. Maybe it could be enhanced in the future to a more | |
1334 | * efficient allocator. | |
1335 | * | |
1336 | ****************************************************************************/ | |
d3086444 | 1337 | |
431b2a20 | 1338 | /* |
384de729 | 1339 | * The address allocator core functions. |
431b2a20 JR |
1340 | * |
1341 | * called with domain->lock held | |
1342 | */ | |
384de729 | 1343 | |
171e7b37 JR |
1344 | /* |
1345 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1346 | * ranges. | |
1347 | */ | |
1348 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1349 | unsigned long start_page, | |
1350 | unsigned int pages) | |
1351 | { | |
1352 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1353 | ||
1354 | if (start_page + pages > last_page) | |
1355 | pages = last_page - start_page; | |
1356 | ||
1357 | for (i = start_page; i < start_page + pages; ++i) { | |
1358 | int index = i / APERTURE_RANGE_PAGES; | |
1359 | int page = i % APERTURE_RANGE_PAGES; | |
1360 | __set_bit(page, dom->aperture[index]->bitmap); | |
1361 | } | |
1362 | } | |
1363 | ||
9cabe89b JR |
1364 | /* |
1365 | * This function is used to add a new aperture range to an existing | |
1366 | * aperture in case of dma_ops domain allocation or address allocation | |
1367 | * failure. | |
1368 | */ | |
576175c2 | 1369 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1370 | bool populate, gfp_t gfp) |
1371 | { | |
1372 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1373 | struct amd_iommu *iommu; |
17f5b569 | 1374 | unsigned long i, old_size; |
9cabe89b | 1375 | |
f5e9705c JR |
1376 | #ifdef CONFIG_IOMMU_STRESS |
1377 | populate = false; | |
1378 | #endif | |
1379 | ||
9cabe89b JR |
1380 | if (index >= APERTURE_MAX_RANGES) |
1381 | return -ENOMEM; | |
1382 | ||
1383 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1384 | if (!dma_dom->aperture[index]) | |
1385 | return -ENOMEM; | |
1386 | ||
1387 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1388 | if (!dma_dom->aperture[index]->bitmap) | |
1389 | goto out_free; | |
1390 | ||
1391 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1392 | ||
1393 | if (populate) { | |
1394 | unsigned long address = dma_dom->aperture_size; | |
1395 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1396 | u64 *pte, *pte_page; | |
1397 | ||
1398 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1399 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1400 | &pte_page, gfp); |
1401 | if (!pte) | |
1402 | goto out_free; | |
1403 | ||
1404 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1405 | ||
1406 | address += APERTURE_RANGE_SIZE / 64; | |
1407 | } | |
1408 | } | |
1409 | ||
17f5b569 | 1410 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1411 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1412 | ||
17f5b569 JR |
1413 | /* Reserve address range used for MSI messages */ |
1414 | if (old_size < MSI_ADDR_BASE_LO && | |
1415 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1416 | unsigned long spage; | |
1417 | int pages; | |
1418 | ||
1419 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1420 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1421 | ||
1422 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1423 | } | |
1424 | ||
b595076a | 1425 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1426 | for_each_iommu(iommu) { |
1427 | if (iommu->exclusion_start && | |
1428 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1429 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1430 | unsigned long startpage; | |
1431 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1432 | iommu->exclusion_length, | |
1433 | PAGE_SIZE); | |
1434 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1435 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1436 | } | |
00cd122a JR |
1437 | } |
1438 | ||
1439 | /* | |
1440 | * Check for areas already mapped as present in the new aperture | |
1441 | * range and mark those pages as reserved in the allocator. Such | |
1442 | * mappings may already exist as a result of requested unity | |
1443 | * mappings for devices. | |
1444 | */ | |
1445 | for (i = dma_dom->aperture[index]->offset; | |
1446 | i < dma_dom->aperture_size; | |
1447 | i += PAGE_SIZE) { | |
24cd7723 | 1448 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1449 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1450 | continue; | |
1451 | ||
fcd0861d | 1452 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1453 | } |
1454 | ||
04bfdd84 JR |
1455 | update_domain(&dma_dom->domain); |
1456 | ||
9cabe89b JR |
1457 | return 0; |
1458 | ||
1459 | out_free: | |
04bfdd84 JR |
1460 | update_domain(&dma_dom->domain); |
1461 | ||
9cabe89b JR |
1462 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1463 | ||
1464 | kfree(dma_dom->aperture[index]); | |
1465 | dma_dom->aperture[index] = NULL; | |
1466 | ||
1467 | return -ENOMEM; | |
1468 | } | |
1469 | ||
384de729 JR |
1470 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1471 | struct dma_ops_domain *dom, | |
1472 | unsigned int pages, | |
1473 | unsigned long align_mask, | |
1474 | u64 dma_mask, | |
1475 | unsigned long start) | |
1476 | { | |
803b8cb4 | 1477 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1478 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1479 | int i = start >> APERTURE_RANGE_SHIFT; | |
1480 | unsigned long boundary_size; | |
1481 | unsigned long address = -1; | |
1482 | unsigned long limit; | |
1483 | ||
803b8cb4 JR |
1484 | next_bit >>= PAGE_SHIFT; |
1485 | ||
384de729 JR |
1486 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1487 | PAGE_SIZE) >> PAGE_SHIFT; | |
1488 | ||
1489 | for (;i < max_index; ++i) { | |
1490 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1491 | ||
1492 | if (dom->aperture[i]->offset >= dma_mask) | |
1493 | break; | |
1494 | ||
1495 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1496 | dma_mask >> PAGE_SHIFT); | |
1497 | ||
1498 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1499 | limit, next_bit, pages, 0, | |
1500 | boundary_size, align_mask); | |
1501 | if (address != -1) { | |
1502 | address = dom->aperture[i]->offset + | |
1503 | (address << PAGE_SHIFT); | |
803b8cb4 | 1504 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1505 | break; |
1506 | } | |
1507 | ||
1508 | next_bit = 0; | |
1509 | } | |
1510 | ||
1511 | return address; | |
1512 | } | |
1513 | ||
d3086444 JR |
1514 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1515 | struct dma_ops_domain *dom, | |
6d4f343f | 1516 | unsigned int pages, |
832a90c3 JR |
1517 | unsigned long align_mask, |
1518 | u64 dma_mask) | |
d3086444 | 1519 | { |
d3086444 | 1520 | unsigned long address; |
d3086444 | 1521 | |
fe16f088 JR |
1522 | #ifdef CONFIG_IOMMU_STRESS |
1523 | dom->next_address = 0; | |
1524 | dom->need_flush = true; | |
1525 | #endif | |
d3086444 | 1526 | |
384de729 | 1527 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1528 | dma_mask, dom->next_address); |
d3086444 | 1529 | |
1c655773 | 1530 | if (address == -1) { |
803b8cb4 | 1531 | dom->next_address = 0; |
384de729 JR |
1532 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1533 | dma_mask, 0); | |
1c655773 JR |
1534 | dom->need_flush = true; |
1535 | } | |
d3086444 | 1536 | |
384de729 | 1537 | if (unlikely(address == -1)) |
8fd524b3 | 1538 | address = DMA_ERROR_CODE; |
d3086444 JR |
1539 | |
1540 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1541 | ||
1542 | return address; | |
1543 | } | |
1544 | ||
431b2a20 JR |
1545 | /* |
1546 | * The address free function. | |
1547 | * | |
1548 | * called with domain->lock held | |
1549 | */ | |
d3086444 JR |
1550 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1551 | unsigned long address, | |
1552 | unsigned int pages) | |
1553 | { | |
384de729 JR |
1554 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1555 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1556 | |
384de729 JR |
1557 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1558 | ||
47bccd6b JR |
1559 | #ifdef CONFIG_IOMMU_STRESS |
1560 | if (i < 4) | |
1561 | return; | |
1562 | #endif | |
80be308d | 1563 | |
803b8cb4 | 1564 | if (address >= dom->next_address) |
80be308d | 1565 | dom->need_flush = true; |
384de729 JR |
1566 | |
1567 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1568 | |
a66022c4 | 1569 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1570 | |
d3086444 JR |
1571 | } |
1572 | ||
431b2a20 JR |
1573 | /**************************************************************************** |
1574 | * | |
1575 | * The next functions belong to the domain allocation. A domain is | |
1576 | * allocated for every IOMMU as the default domain. If device isolation | |
1577 | * is enabled, every device get its own domain. The most important thing | |
1578 | * about domains is the page table mapping the DMA address space they | |
1579 | * contain. | |
1580 | * | |
1581 | ****************************************************************************/ | |
1582 | ||
aeb26f55 JR |
1583 | /* |
1584 | * This function adds a protection domain to the global protection domain list | |
1585 | */ | |
1586 | static void add_domain_to_list(struct protection_domain *domain) | |
1587 | { | |
1588 | unsigned long flags; | |
1589 | ||
1590 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1591 | list_add(&domain->list, &amd_iommu_pd_list); | |
1592 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1593 | } | |
1594 | ||
1595 | /* | |
1596 | * This function removes a protection domain to the global | |
1597 | * protection domain list | |
1598 | */ | |
1599 | static void del_domain_from_list(struct protection_domain *domain) | |
1600 | { | |
1601 | unsigned long flags; | |
1602 | ||
1603 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1604 | list_del(&domain->list); | |
1605 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1606 | } | |
1607 | ||
ec487d1a JR |
1608 | static u16 domain_id_alloc(void) |
1609 | { | |
1610 | unsigned long flags; | |
1611 | int id; | |
1612 | ||
1613 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1614 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1615 | BUG_ON(id == 0); | |
1616 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1617 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1618 | else | |
1619 | id = 0; | |
1620 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1621 | ||
1622 | return id; | |
1623 | } | |
1624 | ||
a2acfb75 JR |
1625 | static void domain_id_free(int id) |
1626 | { | |
1627 | unsigned long flags; | |
1628 | ||
1629 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1630 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1631 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1632 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1633 | } | |
a2acfb75 | 1634 | |
86db2e5d | 1635 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1636 | { |
1637 | int i, j; | |
1638 | u64 *p1, *p2, *p3; | |
1639 | ||
86db2e5d | 1640 | p1 = domain->pt_root; |
ec487d1a JR |
1641 | |
1642 | if (!p1) | |
1643 | return; | |
1644 | ||
1645 | for (i = 0; i < 512; ++i) { | |
1646 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1647 | continue; | |
1648 | ||
1649 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1650 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1651 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1652 | continue; | |
1653 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1654 | free_page((unsigned long)p3); | |
1655 | } | |
1656 | ||
1657 | free_page((unsigned long)p2); | |
1658 | } | |
1659 | ||
1660 | free_page((unsigned long)p1); | |
86db2e5d JR |
1661 | |
1662 | domain->pt_root = NULL; | |
ec487d1a JR |
1663 | } |
1664 | ||
b16137b1 JR |
1665 | static void free_gcr3_tbl_level1(u64 *tbl) |
1666 | { | |
1667 | u64 *ptr; | |
1668 | int i; | |
1669 | ||
1670 | for (i = 0; i < 512; ++i) { | |
1671 | if (!(tbl[i] & GCR3_VALID)) | |
1672 | continue; | |
1673 | ||
1674 | ptr = __va(tbl[i] & PAGE_MASK); | |
1675 | ||
1676 | free_page((unsigned long)ptr); | |
1677 | } | |
1678 | } | |
1679 | ||
1680 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1681 | { | |
1682 | u64 *ptr; | |
1683 | int i; | |
1684 | ||
1685 | for (i = 0; i < 512; ++i) { | |
1686 | if (!(tbl[i] & GCR3_VALID)) | |
1687 | continue; | |
1688 | ||
1689 | ptr = __va(tbl[i] & PAGE_MASK); | |
1690 | ||
1691 | free_gcr3_tbl_level1(ptr); | |
1692 | } | |
1693 | } | |
1694 | ||
52815b75 JR |
1695 | static void free_gcr3_table(struct protection_domain *domain) |
1696 | { | |
b16137b1 JR |
1697 | if (domain->glx == 2) |
1698 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1699 | else if (domain->glx == 1) | |
1700 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1701 | else if (domain->glx != 0) | |
1702 | BUG(); | |
1703 | ||
52815b75 JR |
1704 | free_page((unsigned long)domain->gcr3_tbl); |
1705 | } | |
1706 | ||
431b2a20 JR |
1707 | /* |
1708 | * Free a domain, only used if something went wrong in the | |
1709 | * allocation path and we need to free an already allocated page table | |
1710 | */ | |
ec487d1a JR |
1711 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1712 | { | |
384de729 JR |
1713 | int i; |
1714 | ||
ec487d1a JR |
1715 | if (!dom) |
1716 | return; | |
1717 | ||
aeb26f55 JR |
1718 | del_domain_from_list(&dom->domain); |
1719 | ||
86db2e5d | 1720 | free_pagetable(&dom->domain); |
ec487d1a | 1721 | |
384de729 JR |
1722 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1723 | if (!dom->aperture[i]) | |
1724 | continue; | |
1725 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1726 | kfree(dom->aperture[i]); | |
1727 | } | |
ec487d1a JR |
1728 | |
1729 | kfree(dom); | |
1730 | } | |
1731 | ||
431b2a20 JR |
1732 | /* |
1733 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1734 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1735 | * structures required for the dma_ops interface |
1736 | */ | |
87a64d52 | 1737 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1738 | { |
1739 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1740 | |
1741 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1742 | if (!dma_dom) | |
1743 | return NULL; | |
1744 | ||
1745 | spin_lock_init(&dma_dom->domain.lock); | |
1746 | ||
1747 | dma_dom->domain.id = domain_id_alloc(); | |
1748 | if (dma_dom->domain.id == 0) | |
1749 | goto free_dma_dom; | |
7c392cbe | 1750 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1751 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1752 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1753 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1754 | dma_dom->domain.priv = dma_dom; |
1755 | if (!dma_dom->domain.pt_root) | |
1756 | goto free_dma_dom; | |
ec487d1a | 1757 | |
1c655773 | 1758 | dma_dom->need_flush = false; |
bd60b735 | 1759 | dma_dom->target_dev = 0xffff; |
1c655773 | 1760 | |
aeb26f55 JR |
1761 | add_domain_to_list(&dma_dom->domain); |
1762 | ||
576175c2 | 1763 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1764 | goto free_dma_dom; |
ec487d1a | 1765 | |
431b2a20 | 1766 | /* |
ec487d1a JR |
1767 | * mark the first page as allocated so we never return 0 as |
1768 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1769 | */ |
384de729 | 1770 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1771 | dma_dom->next_address = 0; |
ec487d1a | 1772 | |
ec487d1a JR |
1773 | |
1774 | return dma_dom; | |
1775 | ||
1776 | free_dma_dom: | |
1777 | dma_ops_domain_free(dma_dom); | |
1778 | ||
1779 | return NULL; | |
1780 | } | |
1781 | ||
5b28df6f JR |
1782 | /* |
1783 | * little helper function to check whether a given protection domain is a | |
1784 | * dma_ops domain | |
1785 | */ | |
1786 | static bool dma_ops_domain(struct protection_domain *domain) | |
1787 | { | |
1788 | return domain->flags & PD_DMA_OPS_MASK; | |
1789 | } | |
1790 | ||
fd7b5535 | 1791 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1792 | { |
132bd68f | 1793 | u64 pte_root = 0; |
ee6c2868 | 1794 | u64 flags = 0; |
863c74eb | 1795 | |
132bd68f JR |
1796 | if (domain->mode != PAGE_MODE_NONE) |
1797 | pte_root = virt_to_phys(domain->pt_root); | |
1798 | ||
38ddf41b JR |
1799 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1800 | << DEV_ENTRY_MODE_SHIFT; | |
1801 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1802 | |
ee6c2868 JR |
1803 | flags = amd_iommu_dev_table[devid].data[1]; |
1804 | ||
fd7b5535 JR |
1805 | if (ats) |
1806 | flags |= DTE_FLAG_IOTLB; | |
1807 | ||
52815b75 JR |
1808 | if (domain->flags & PD_IOMMUV2_MASK) { |
1809 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1810 | u64 glx = domain->glx; | |
1811 | u64 tmp; | |
1812 | ||
1813 | pte_root |= DTE_FLAG_GV; | |
1814 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1815 | ||
1816 | /* First mask out possible old values for GCR3 table */ | |
1817 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1818 | flags &= ~tmp; | |
1819 | ||
1820 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1821 | flags &= ~tmp; | |
1822 | ||
1823 | /* Encode GCR3 table into DTE */ | |
1824 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1825 | pte_root |= tmp; | |
1826 | ||
1827 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1828 | flags |= tmp; | |
1829 | ||
1830 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1831 | flags |= tmp; | |
1832 | } | |
1833 | ||
ee6c2868 JR |
1834 | flags &= ~(0xffffUL); |
1835 | flags |= domain->id; | |
1836 | ||
1837 | amd_iommu_dev_table[devid].data[1] = flags; | |
1838 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1839 | } |
1840 | ||
1841 | static void clear_dte_entry(u16 devid) | |
1842 | { | |
15898bbc JR |
1843 | /* remove entry from the device table seen by the hardware */ |
1844 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1845 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1846 | |
1847 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1848 | } |
1849 | ||
ec9e79ef JR |
1850 | static void do_attach(struct iommu_dev_data *dev_data, |
1851 | struct protection_domain *domain) | |
7f760ddd | 1852 | { |
7f760ddd | 1853 | struct amd_iommu *iommu; |
ec9e79ef | 1854 | bool ats; |
fd7b5535 | 1855 | |
ec9e79ef JR |
1856 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1857 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1858 | |
1859 | /* Update data structures */ | |
1860 | dev_data->domain = domain; | |
1861 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1862 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1863 | |
1864 | /* Do reference counting */ | |
1865 | domain->dev_iommu[iommu->index] += 1; | |
1866 | domain->dev_cnt += 1; | |
1867 | ||
1868 | /* Flush the DTE entry */ | |
6c542047 | 1869 | device_flush_dte(dev_data); |
7f760ddd JR |
1870 | } |
1871 | ||
ec9e79ef | 1872 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1873 | { |
7f760ddd | 1874 | struct amd_iommu *iommu; |
7f760ddd | 1875 | |
ec9e79ef | 1876 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1877 | |
1878 | /* decrease reference counters */ | |
7f760ddd JR |
1879 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1880 | dev_data->domain->dev_cnt -= 1; | |
1881 | ||
1882 | /* Update data structures */ | |
1883 | dev_data->domain = NULL; | |
1884 | list_del(&dev_data->list); | |
f62dda66 | 1885 | clear_dte_entry(dev_data->devid); |
15898bbc | 1886 | |
7f760ddd | 1887 | /* Flush the DTE entry */ |
6c542047 | 1888 | device_flush_dte(dev_data); |
2b681faf JR |
1889 | } |
1890 | ||
1891 | /* | |
1892 | * If a device is not yet associated with a domain, this function does | |
1893 | * assigns it visible for the hardware | |
1894 | */ | |
ec9e79ef | 1895 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1896 | struct protection_domain *domain) |
2b681faf | 1897 | { |
84fe6c19 | 1898 | int ret; |
657cbb6b | 1899 | |
2b681faf JR |
1900 | /* lock domain */ |
1901 | spin_lock(&domain->lock); | |
1902 | ||
71f77580 JR |
1903 | if (dev_data->alias_data != NULL) { |
1904 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1905 | |
2b02b091 JR |
1906 | /* Some sanity checks */ |
1907 | ret = -EBUSY; | |
1908 | if (alias_data->domain != NULL && | |
1909 | alias_data->domain != domain) | |
1910 | goto out_unlock; | |
eba6ac60 | 1911 | |
2b02b091 JR |
1912 | if (dev_data->domain != NULL && |
1913 | dev_data->domain != domain) | |
1914 | goto out_unlock; | |
15898bbc | 1915 | |
2b02b091 | 1916 | /* Do real assignment */ |
7f760ddd | 1917 | if (alias_data->domain == NULL) |
ec9e79ef | 1918 | do_attach(alias_data, domain); |
24100055 JR |
1919 | |
1920 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1921 | } |
15898bbc | 1922 | |
7f760ddd | 1923 | if (dev_data->domain == NULL) |
ec9e79ef | 1924 | do_attach(dev_data, domain); |
eba6ac60 | 1925 | |
24100055 JR |
1926 | atomic_inc(&dev_data->bind); |
1927 | ||
84fe6c19 JL |
1928 | ret = 0; |
1929 | ||
1930 | out_unlock: | |
1931 | ||
eba6ac60 JR |
1932 | /* ready */ |
1933 | spin_unlock(&domain->lock); | |
15898bbc | 1934 | |
84fe6c19 | 1935 | return ret; |
0feae533 | 1936 | } |
b20ac0d4 | 1937 | |
52815b75 JR |
1938 | |
1939 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1940 | { | |
1941 | pci_disable_ats(pdev); | |
1942 | pci_disable_pri(pdev); | |
1943 | pci_disable_pasid(pdev); | |
1944 | } | |
1945 | ||
6a113ddc JR |
1946 | /* FIXME: Change generic reset-function to do the same */ |
1947 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1948 | { | |
1949 | u16 control; | |
1950 | int pos; | |
1951 | ||
1952 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
1953 | if (!pos) | |
1954 | return -EINVAL; | |
1955 | ||
1956 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
1957 | control |= PCI_PRI_RESET; | |
1958 | pci_write_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, control); | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
52815b75 JR |
1963 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
1964 | { | |
6a113ddc JR |
1965 | bool reset_enable; |
1966 | int reqs, ret; | |
1967 | ||
1968 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1969 | reqs = 32; | |
1970 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
1971 | reqs = 1; | |
1972 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
1973 | |
1974 | /* Only allow access to user-accessible pages */ | |
1975 | ret = pci_enable_pasid(pdev, 0); | |
1976 | if (ret) | |
1977 | goto out_err; | |
1978 | ||
1979 | /* First reset the PRI state of the device */ | |
1980 | ret = pci_reset_pri(pdev); | |
1981 | if (ret) | |
1982 | goto out_err; | |
1983 | ||
6a113ddc JR |
1984 | /* Enable PRI */ |
1985 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
1986 | if (ret) |
1987 | goto out_err; | |
1988 | ||
6a113ddc JR |
1989 | if (reset_enable) { |
1990 | ret = pri_reset_while_enabled(pdev); | |
1991 | if (ret) | |
1992 | goto out_err; | |
1993 | } | |
1994 | ||
52815b75 JR |
1995 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
1996 | if (ret) | |
1997 | goto out_err; | |
1998 | ||
1999 | return 0; | |
2000 | ||
2001 | out_err: | |
2002 | pci_disable_pri(pdev); | |
2003 | pci_disable_pasid(pdev); | |
2004 | ||
2005 | return ret; | |
2006 | } | |
2007 | ||
c99afa25 JR |
2008 | /* FIXME: Move this to PCI code */ |
2009 | #define PCI_PRI_TLP_OFF (1 << 2) | |
2010 | ||
2011 | bool pci_pri_tlp_required(struct pci_dev *pdev) | |
2012 | { | |
2013 | u16 control; | |
2014 | int pos; | |
2015 | ||
2016 | pos = pci_find_ext_capability(pdev, PCI_PRI_CAP); | |
2017 | if (!pos) | |
2018 | return false; | |
2019 | ||
2020 | pci_read_config_word(pdev, pos + PCI_PRI_CONTROL_OFF, &control); | |
2021 | ||
2022 | return (control & PCI_PRI_TLP_OFF) ? true : false; | |
2023 | } | |
2024 | ||
407d733e JR |
2025 | /* |
2026 | * If a device is not yet associated with a domain, this function does | |
2027 | * assigns it visible for the hardware | |
2028 | */ | |
15898bbc JR |
2029 | static int attach_device(struct device *dev, |
2030 | struct protection_domain *domain) | |
0feae533 | 2031 | { |
fd7b5535 | 2032 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2033 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2034 | unsigned long flags; |
15898bbc | 2035 | int ret; |
eba6ac60 | 2036 | |
ea61cddb JR |
2037 | dev_data = get_dev_data(dev); |
2038 | ||
52815b75 JR |
2039 | if (domain->flags & PD_IOMMUV2_MASK) { |
2040 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2041 | return -EINVAL; | |
2042 | ||
2043 | if (pdev_iommuv2_enable(pdev) != 0) | |
2044 | return -EINVAL; | |
2045 | ||
2046 | dev_data->ats.enabled = true; | |
2047 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2048 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2049 | } else if (amd_iommu_iotlb_sup && |
2050 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2051 | dev_data->ats.enabled = true; |
2052 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2053 | } | |
fd7b5535 | 2054 | |
eba6ac60 | 2055 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2056 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2057 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2058 | ||
0feae533 JR |
2059 | /* |
2060 | * We might boot into a crash-kernel here. The crashed kernel | |
2061 | * left the caches in the IOMMU dirty. So we have to flush | |
2062 | * here to evict all dirty stuff. | |
2063 | */ | |
17b124bf | 2064 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2065 | |
2066 | return ret; | |
b20ac0d4 JR |
2067 | } |
2068 | ||
355bf553 JR |
2069 | /* |
2070 | * Removes a device from a protection domain (unlocked) | |
2071 | */ | |
ec9e79ef | 2072 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2073 | { |
2ca76279 | 2074 | struct protection_domain *domain; |
7c392cbe | 2075 | unsigned long flags; |
c4596114 | 2076 | |
7f760ddd | 2077 | BUG_ON(!dev_data->domain); |
355bf553 | 2078 | |
2ca76279 JR |
2079 | domain = dev_data->domain; |
2080 | ||
2081 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2082 | |
71f77580 JR |
2083 | if (dev_data->alias_data != NULL) { |
2084 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2085 | ||
7f760ddd | 2086 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2087 | do_detach(alias_data); |
24100055 JR |
2088 | } |
2089 | ||
7f760ddd | 2090 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2091 | do_detach(dev_data); |
7f760ddd | 2092 | |
2ca76279 | 2093 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2094 | |
2095 | /* | |
2096 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2097 | * passthrough domain if it is detached from any other domain. |
2098 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2099 | */ |
5abcdba4 | 2100 | if (dev_data->passthrough && |
d3ad9373 | 2101 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2102 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2103 | } |
2104 | ||
2105 | /* | |
2106 | * Removes a device from a protection domain (with devtable_lock held) | |
2107 | */ | |
15898bbc | 2108 | static void detach_device(struct device *dev) |
355bf553 | 2109 | { |
52815b75 | 2110 | struct protection_domain *domain; |
ea61cddb | 2111 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2112 | unsigned long flags; |
2113 | ||
ec9e79ef | 2114 | dev_data = get_dev_data(dev); |
52815b75 | 2115 | domain = dev_data->domain; |
ec9e79ef | 2116 | |
355bf553 JR |
2117 | /* lock device table */ |
2118 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2119 | __detach_device(dev_data); |
355bf553 | 2120 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2121 | |
52815b75 JR |
2122 | if (domain->flags & PD_IOMMUV2_MASK) |
2123 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2124 | else if (dev_data->ats.enabled) | |
ea61cddb | 2125 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2126 | |
2127 | dev_data->ats.enabled = false; | |
355bf553 | 2128 | } |
e275a2a0 | 2129 | |
15898bbc JR |
2130 | /* |
2131 | * Find out the protection domain structure for a given PCI device. This | |
2132 | * will give us the pointer to the page table root for example. | |
2133 | */ | |
2134 | static struct protection_domain *domain_for_device(struct device *dev) | |
2135 | { | |
71f77580 | 2136 | struct iommu_dev_data *dev_data; |
2b02b091 | 2137 | struct protection_domain *dom = NULL; |
15898bbc | 2138 | unsigned long flags; |
15898bbc | 2139 | |
657cbb6b | 2140 | dev_data = get_dev_data(dev); |
15898bbc | 2141 | |
2b02b091 JR |
2142 | if (dev_data->domain) |
2143 | return dev_data->domain; | |
15898bbc | 2144 | |
71f77580 JR |
2145 | if (dev_data->alias_data != NULL) { |
2146 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2147 | |
2148 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2149 | if (alias_data->domain != NULL) { | |
2150 | __attach_device(dev_data, alias_data->domain); | |
2151 | dom = alias_data->domain; | |
2152 | } | |
2153 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2154 | } | |
15898bbc JR |
2155 | |
2156 | return dom; | |
2157 | } | |
2158 | ||
e275a2a0 JR |
2159 | static int device_change_notifier(struct notifier_block *nb, |
2160 | unsigned long action, void *data) | |
2161 | { | |
e275a2a0 | 2162 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2163 | struct protection_domain *domain; |
2164 | struct iommu_dev_data *dev_data; | |
2165 | struct device *dev = data; | |
e275a2a0 | 2166 | struct amd_iommu *iommu; |
1ac4cbbc | 2167 | unsigned long flags; |
5abcdba4 | 2168 | u16 devid; |
e275a2a0 | 2169 | |
98fc5a69 JR |
2170 | if (!check_device(dev)) |
2171 | return 0; | |
e275a2a0 | 2172 | |
5abcdba4 JR |
2173 | devid = get_device_id(dev); |
2174 | iommu = amd_iommu_rlookup_table[devid]; | |
2175 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2176 | |
2177 | switch (action) { | |
c1eee67b | 2178 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2179 | |
2180 | domain = domain_for_device(dev); | |
2181 | ||
e275a2a0 JR |
2182 | if (!domain) |
2183 | goto out; | |
5abcdba4 | 2184 | if (dev_data->passthrough) |
a1ca331c | 2185 | break; |
15898bbc | 2186 | detach_device(dev); |
1ac4cbbc JR |
2187 | break; |
2188 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2189 | |
2190 | iommu_init_device(dev); | |
2191 | ||
2192 | domain = domain_for_device(dev); | |
2193 | ||
1ac4cbbc JR |
2194 | /* allocate a protection domain if a device is added */ |
2195 | dma_domain = find_protection_domain(devid); | |
2196 | if (dma_domain) | |
2197 | goto out; | |
87a64d52 | 2198 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2199 | if (!dma_domain) |
2200 | goto out; | |
2201 | dma_domain->target_dev = devid; | |
2202 | ||
2203 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2204 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2205 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2206 | ||
e275a2a0 | 2207 | break; |
657cbb6b JR |
2208 | case BUS_NOTIFY_DEL_DEVICE: |
2209 | ||
2210 | iommu_uninit_device(dev); | |
2211 | ||
e275a2a0 JR |
2212 | default: |
2213 | goto out; | |
2214 | } | |
2215 | ||
e275a2a0 JR |
2216 | iommu_completion_wait(iommu); |
2217 | ||
2218 | out: | |
2219 | return 0; | |
2220 | } | |
2221 | ||
b25ae679 | 2222 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2223 | .notifier_call = device_change_notifier, |
2224 | }; | |
355bf553 | 2225 | |
8638c491 JR |
2226 | void amd_iommu_init_notifier(void) |
2227 | { | |
2228 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2229 | } | |
2230 | ||
431b2a20 JR |
2231 | /***************************************************************************** |
2232 | * | |
2233 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2234 | * | |
2235 | *****************************************************************************/ | |
2236 | ||
2237 | /* | |
2238 | * In the dma_ops path we only have the struct device. This function | |
2239 | * finds the corresponding IOMMU, the protection domain and the | |
2240 | * requestor id for a given device. | |
2241 | * If the device is not yet associated with a domain this is also done | |
2242 | * in this function. | |
2243 | */ | |
94f6d190 | 2244 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2245 | { |
94f6d190 | 2246 | struct protection_domain *domain; |
b20ac0d4 | 2247 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2248 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2249 | |
f99c0f1c | 2250 | if (!check_device(dev)) |
94f6d190 | 2251 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2252 | |
94f6d190 JR |
2253 | domain = domain_for_device(dev); |
2254 | if (domain != NULL && !dma_ops_domain(domain)) | |
2255 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2256 | |
94f6d190 JR |
2257 | if (domain != NULL) |
2258 | return domain; | |
b20ac0d4 | 2259 | |
15898bbc | 2260 | /* Device not bount yet - bind it */ |
94f6d190 | 2261 | dma_dom = find_protection_domain(devid); |
15898bbc | 2262 | if (!dma_dom) |
94f6d190 JR |
2263 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2264 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2265 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2266 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2267 | |
94f6d190 | 2268 | return &dma_dom->domain; |
b20ac0d4 JR |
2269 | } |
2270 | ||
04bfdd84 JR |
2271 | static void update_device_table(struct protection_domain *domain) |
2272 | { | |
492667da | 2273 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2274 | |
ea61cddb JR |
2275 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2276 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2277 | } |
2278 | ||
2279 | static void update_domain(struct protection_domain *domain) | |
2280 | { | |
2281 | if (!domain->updated) | |
2282 | return; | |
2283 | ||
2284 | update_device_table(domain); | |
17b124bf JR |
2285 | |
2286 | domain_flush_devices(domain); | |
2287 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2288 | |
2289 | domain->updated = false; | |
2290 | } | |
2291 | ||
8bda3092 JR |
2292 | /* |
2293 | * This function fetches the PTE for a given address in the aperture | |
2294 | */ | |
2295 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2296 | unsigned long address) | |
2297 | { | |
384de729 | 2298 | struct aperture_range *aperture; |
8bda3092 JR |
2299 | u64 *pte, *pte_page; |
2300 | ||
384de729 JR |
2301 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2302 | if (!aperture) | |
2303 | return NULL; | |
2304 | ||
2305 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2306 | if (!pte) { |
cbb9d729 | 2307 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2308 | GFP_ATOMIC); |
384de729 JR |
2309 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2310 | } else | |
8c8c143c | 2311 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2312 | |
04bfdd84 | 2313 | update_domain(&dom->domain); |
8bda3092 JR |
2314 | |
2315 | return pte; | |
2316 | } | |
2317 | ||
431b2a20 JR |
2318 | /* |
2319 | * This is the generic map function. It maps one 4kb page at paddr to | |
2320 | * the given address in the DMA address space for the domain. | |
2321 | */ | |
680525e0 | 2322 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2323 | unsigned long address, |
2324 | phys_addr_t paddr, | |
2325 | int direction) | |
2326 | { | |
2327 | u64 *pte, __pte; | |
2328 | ||
2329 | WARN_ON(address > dom->aperture_size); | |
2330 | ||
2331 | paddr &= PAGE_MASK; | |
2332 | ||
8bda3092 | 2333 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2334 | if (!pte) |
8fd524b3 | 2335 | return DMA_ERROR_CODE; |
cb76c322 JR |
2336 | |
2337 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2338 | ||
2339 | if (direction == DMA_TO_DEVICE) | |
2340 | __pte |= IOMMU_PTE_IR; | |
2341 | else if (direction == DMA_FROM_DEVICE) | |
2342 | __pte |= IOMMU_PTE_IW; | |
2343 | else if (direction == DMA_BIDIRECTIONAL) | |
2344 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2345 | ||
2346 | WARN_ON(*pte); | |
2347 | ||
2348 | *pte = __pte; | |
2349 | ||
2350 | return (dma_addr_t)address; | |
2351 | } | |
2352 | ||
431b2a20 JR |
2353 | /* |
2354 | * The generic unmapping function for on page in the DMA address space. | |
2355 | */ | |
680525e0 | 2356 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2357 | unsigned long address) |
2358 | { | |
384de729 | 2359 | struct aperture_range *aperture; |
cb76c322 JR |
2360 | u64 *pte; |
2361 | ||
2362 | if (address >= dom->aperture_size) | |
2363 | return; | |
2364 | ||
384de729 JR |
2365 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2366 | if (!aperture) | |
2367 | return; | |
2368 | ||
2369 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2370 | if (!pte) | |
2371 | return; | |
cb76c322 | 2372 | |
8c8c143c | 2373 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2374 | |
2375 | WARN_ON(!*pte); | |
2376 | ||
2377 | *pte = 0ULL; | |
2378 | } | |
2379 | ||
431b2a20 JR |
2380 | /* |
2381 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2382 | * contiguous memory region into DMA address space. It is used by all |
2383 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2384 | * Must be called with the domain lock held. |
2385 | */ | |
cb76c322 | 2386 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2387 | struct dma_ops_domain *dma_dom, |
2388 | phys_addr_t paddr, | |
2389 | size_t size, | |
6d4f343f | 2390 | int dir, |
832a90c3 JR |
2391 | bool align, |
2392 | u64 dma_mask) | |
cb76c322 JR |
2393 | { |
2394 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2395 | dma_addr_t address, start, ret; |
cb76c322 | 2396 | unsigned int pages; |
6d4f343f | 2397 | unsigned long align_mask = 0; |
cb76c322 JR |
2398 | int i; |
2399 | ||
e3c449f5 | 2400 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2401 | paddr &= PAGE_MASK; |
2402 | ||
8ecaf8f1 JR |
2403 | INC_STATS_COUNTER(total_map_requests); |
2404 | ||
c1858976 JR |
2405 | if (pages > 1) |
2406 | INC_STATS_COUNTER(cross_page); | |
2407 | ||
6d4f343f JR |
2408 | if (align) |
2409 | align_mask = (1UL << get_order(size)) - 1; | |
2410 | ||
11b83888 | 2411 | retry: |
832a90c3 JR |
2412 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2413 | dma_mask); | |
8fd524b3 | 2414 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2415 | /* |
2416 | * setting next_address here will let the address | |
2417 | * allocator only scan the new allocated range in the | |
2418 | * first run. This is a small optimization. | |
2419 | */ | |
2420 | dma_dom->next_address = dma_dom->aperture_size; | |
2421 | ||
576175c2 | 2422 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2423 | goto out; |
2424 | ||
2425 | /* | |
af901ca1 | 2426 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2427 | * allocation again |
2428 | */ | |
2429 | goto retry; | |
2430 | } | |
cb76c322 JR |
2431 | |
2432 | start = address; | |
2433 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2434 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2435 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2436 | goto out_unmap; |
2437 | ||
cb76c322 JR |
2438 | paddr += PAGE_SIZE; |
2439 | start += PAGE_SIZE; | |
2440 | } | |
2441 | address += offset; | |
2442 | ||
5774f7c5 JR |
2443 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2444 | ||
afa9fdc2 | 2445 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2446 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2447 | dma_dom->need_flush = false; |
318afd41 | 2448 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2449 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2450 | |
cb76c322 JR |
2451 | out: |
2452 | return address; | |
53812c11 JR |
2453 | |
2454 | out_unmap: | |
2455 | ||
2456 | for (--i; i >= 0; --i) { | |
2457 | start -= PAGE_SIZE; | |
680525e0 | 2458 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2459 | } |
2460 | ||
2461 | dma_ops_free_addresses(dma_dom, address, pages); | |
2462 | ||
8fd524b3 | 2463 | return DMA_ERROR_CODE; |
cb76c322 JR |
2464 | } |
2465 | ||
431b2a20 JR |
2466 | /* |
2467 | * Does the reverse of the __map_single function. Must be called with | |
2468 | * the domain lock held too | |
2469 | */ | |
cd8c82e8 | 2470 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2471 | dma_addr_t dma_addr, |
2472 | size_t size, | |
2473 | int dir) | |
2474 | { | |
04e0463e | 2475 | dma_addr_t flush_addr; |
cb76c322 JR |
2476 | dma_addr_t i, start; |
2477 | unsigned int pages; | |
2478 | ||
8fd524b3 | 2479 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2480 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2481 | return; |
2482 | ||
04e0463e | 2483 | flush_addr = dma_addr; |
e3c449f5 | 2484 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2485 | dma_addr &= PAGE_MASK; |
2486 | start = dma_addr; | |
2487 | ||
2488 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2489 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2490 | start += PAGE_SIZE; |
2491 | } | |
2492 | ||
5774f7c5 JR |
2493 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2494 | ||
cb76c322 | 2495 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2496 | |
80be308d | 2497 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2498 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2499 | dma_dom->need_flush = false; |
2500 | } | |
cb76c322 JR |
2501 | } |
2502 | ||
431b2a20 JR |
2503 | /* |
2504 | * The exported map_single function for dma_ops. | |
2505 | */ | |
51491367 FT |
2506 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2507 | unsigned long offset, size_t size, | |
2508 | enum dma_data_direction dir, | |
2509 | struct dma_attrs *attrs) | |
4da70b9e JR |
2510 | { |
2511 | unsigned long flags; | |
4da70b9e | 2512 | struct protection_domain *domain; |
4da70b9e | 2513 | dma_addr_t addr; |
832a90c3 | 2514 | u64 dma_mask; |
51491367 | 2515 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2516 | |
0f2a86f2 JR |
2517 | INC_STATS_COUNTER(cnt_map_single); |
2518 | ||
94f6d190 JR |
2519 | domain = get_domain(dev); |
2520 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2521 | return (dma_addr_t)paddr; |
94f6d190 JR |
2522 | else if (IS_ERR(domain)) |
2523 | return DMA_ERROR_CODE; | |
4da70b9e | 2524 | |
f99c0f1c JR |
2525 | dma_mask = *dev->dma_mask; |
2526 | ||
4da70b9e | 2527 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2528 | |
cd8c82e8 | 2529 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2530 | dma_mask); |
8fd524b3 | 2531 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2532 | goto out; |
2533 | ||
17b124bf | 2534 | domain_flush_complete(domain); |
4da70b9e JR |
2535 | |
2536 | out: | |
2537 | spin_unlock_irqrestore(&domain->lock, flags); | |
2538 | ||
2539 | return addr; | |
2540 | } | |
2541 | ||
431b2a20 JR |
2542 | /* |
2543 | * The exported unmap_single function for dma_ops. | |
2544 | */ | |
51491367 FT |
2545 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2546 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2547 | { |
2548 | unsigned long flags; | |
4da70b9e | 2549 | struct protection_domain *domain; |
4da70b9e | 2550 | |
146a6917 JR |
2551 | INC_STATS_COUNTER(cnt_unmap_single); |
2552 | ||
94f6d190 JR |
2553 | domain = get_domain(dev); |
2554 | if (IS_ERR(domain)) | |
5b28df6f JR |
2555 | return; |
2556 | ||
4da70b9e JR |
2557 | spin_lock_irqsave(&domain->lock, flags); |
2558 | ||
cd8c82e8 | 2559 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2560 | |
17b124bf | 2561 | domain_flush_complete(domain); |
4da70b9e JR |
2562 | |
2563 | spin_unlock_irqrestore(&domain->lock, flags); | |
2564 | } | |
2565 | ||
431b2a20 JR |
2566 | /* |
2567 | * This is a special map_sg function which is used if we should map a | |
2568 | * device which is not handled by an AMD IOMMU in the system. | |
2569 | */ | |
65b050ad JR |
2570 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2571 | int nelems, int dir) | |
2572 | { | |
2573 | struct scatterlist *s; | |
2574 | int i; | |
2575 | ||
2576 | for_each_sg(sglist, s, nelems, i) { | |
2577 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2578 | s->dma_length = s->length; | |
2579 | } | |
2580 | ||
2581 | return nelems; | |
2582 | } | |
2583 | ||
431b2a20 JR |
2584 | /* |
2585 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2586 | * lists). | |
2587 | */ | |
65b050ad | 2588 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2589 | int nelems, enum dma_data_direction dir, |
2590 | struct dma_attrs *attrs) | |
65b050ad JR |
2591 | { |
2592 | unsigned long flags; | |
65b050ad | 2593 | struct protection_domain *domain; |
65b050ad JR |
2594 | int i; |
2595 | struct scatterlist *s; | |
2596 | phys_addr_t paddr; | |
2597 | int mapped_elems = 0; | |
832a90c3 | 2598 | u64 dma_mask; |
65b050ad | 2599 | |
d03f067a JR |
2600 | INC_STATS_COUNTER(cnt_map_sg); |
2601 | ||
94f6d190 JR |
2602 | domain = get_domain(dev); |
2603 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2604 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2605 | else if (IS_ERR(domain)) |
2606 | return 0; | |
dbcc112e | 2607 | |
832a90c3 | 2608 | dma_mask = *dev->dma_mask; |
65b050ad | 2609 | |
65b050ad JR |
2610 | spin_lock_irqsave(&domain->lock, flags); |
2611 | ||
2612 | for_each_sg(sglist, s, nelems, i) { | |
2613 | paddr = sg_phys(s); | |
2614 | ||
cd8c82e8 | 2615 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2616 | paddr, s->length, dir, false, |
2617 | dma_mask); | |
65b050ad JR |
2618 | |
2619 | if (s->dma_address) { | |
2620 | s->dma_length = s->length; | |
2621 | mapped_elems++; | |
2622 | } else | |
2623 | goto unmap; | |
65b050ad JR |
2624 | } |
2625 | ||
17b124bf | 2626 | domain_flush_complete(domain); |
65b050ad JR |
2627 | |
2628 | out: | |
2629 | spin_unlock_irqrestore(&domain->lock, flags); | |
2630 | ||
2631 | return mapped_elems; | |
2632 | unmap: | |
2633 | for_each_sg(sglist, s, mapped_elems, i) { | |
2634 | if (s->dma_address) | |
cd8c82e8 | 2635 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2636 | s->dma_length, dir); |
2637 | s->dma_address = s->dma_length = 0; | |
2638 | } | |
2639 | ||
2640 | mapped_elems = 0; | |
2641 | ||
2642 | goto out; | |
2643 | } | |
2644 | ||
431b2a20 JR |
2645 | /* |
2646 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2647 | * lists). | |
2648 | */ | |
65b050ad | 2649 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2650 | int nelems, enum dma_data_direction dir, |
2651 | struct dma_attrs *attrs) | |
65b050ad JR |
2652 | { |
2653 | unsigned long flags; | |
65b050ad JR |
2654 | struct protection_domain *domain; |
2655 | struct scatterlist *s; | |
65b050ad JR |
2656 | int i; |
2657 | ||
55877a6b JR |
2658 | INC_STATS_COUNTER(cnt_unmap_sg); |
2659 | ||
94f6d190 JR |
2660 | domain = get_domain(dev); |
2661 | if (IS_ERR(domain)) | |
5b28df6f JR |
2662 | return; |
2663 | ||
65b050ad JR |
2664 | spin_lock_irqsave(&domain->lock, flags); |
2665 | ||
2666 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2667 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2668 | s->dma_length, dir); |
65b050ad JR |
2669 | s->dma_address = s->dma_length = 0; |
2670 | } | |
2671 | ||
17b124bf | 2672 | domain_flush_complete(domain); |
65b050ad JR |
2673 | |
2674 | spin_unlock_irqrestore(&domain->lock, flags); | |
2675 | } | |
2676 | ||
431b2a20 JR |
2677 | /* |
2678 | * The exported alloc_coherent function for dma_ops. | |
2679 | */ | |
5d8b53cf JR |
2680 | static void *alloc_coherent(struct device *dev, size_t size, |
2681 | dma_addr_t *dma_addr, gfp_t flag) | |
2682 | { | |
2683 | unsigned long flags; | |
2684 | void *virt_addr; | |
5d8b53cf | 2685 | struct protection_domain *domain; |
5d8b53cf | 2686 | phys_addr_t paddr; |
832a90c3 | 2687 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2688 | |
c8f0fb36 JR |
2689 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2690 | ||
94f6d190 JR |
2691 | domain = get_domain(dev); |
2692 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2693 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2694 | *dma_addr = __pa(virt_addr); | |
2695 | return virt_addr; | |
94f6d190 JR |
2696 | } else if (IS_ERR(domain)) |
2697 | return NULL; | |
5d8b53cf | 2698 | |
f99c0f1c JR |
2699 | dma_mask = dev->coherent_dma_mask; |
2700 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2701 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2702 | |
2703 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2704 | if (!virt_addr) | |
b25ae679 | 2705 | return NULL; |
5d8b53cf | 2706 | |
5d8b53cf JR |
2707 | paddr = virt_to_phys(virt_addr); |
2708 | ||
832a90c3 JR |
2709 | if (!dma_mask) |
2710 | dma_mask = *dev->dma_mask; | |
2711 | ||
5d8b53cf JR |
2712 | spin_lock_irqsave(&domain->lock, flags); |
2713 | ||
cd8c82e8 | 2714 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2715 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2716 | |
8fd524b3 | 2717 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2718 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2719 | goto out_free; |
367d04c4 | 2720 | } |
5d8b53cf | 2721 | |
17b124bf | 2722 | domain_flush_complete(domain); |
5d8b53cf | 2723 | |
5d8b53cf JR |
2724 | spin_unlock_irqrestore(&domain->lock, flags); |
2725 | ||
2726 | return virt_addr; | |
5b28df6f JR |
2727 | |
2728 | out_free: | |
2729 | ||
2730 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2731 | ||
2732 | return NULL; | |
5d8b53cf JR |
2733 | } |
2734 | ||
431b2a20 JR |
2735 | /* |
2736 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2737 | */ |
5d8b53cf JR |
2738 | static void free_coherent(struct device *dev, size_t size, |
2739 | void *virt_addr, dma_addr_t dma_addr) | |
2740 | { | |
2741 | unsigned long flags; | |
5d8b53cf | 2742 | struct protection_domain *domain; |
5d8b53cf | 2743 | |
5d31ee7e JR |
2744 | INC_STATS_COUNTER(cnt_free_coherent); |
2745 | ||
94f6d190 JR |
2746 | domain = get_domain(dev); |
2747 | if (IS_ERR(domain)) | |
5b28df6f JR |
2748 | goto free_mem; |
2749 | ||
5d8b53cf JR |
2750 | spin_lock_irqsave(&domain->lock, flags); |
2751 | ||
cd8c82e8 | 2752 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2753 | |
17b124bf | 2754 | domain_flush_complete(domain); |
5d8b53cf JR |
2755 | |
2756 | spin_unlock_irqrestore(&domain->lock, flags); | |
2757 | ||
2758 | free_mem: | |
2759 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2760 | } | |
2761 | ||
b39ba6ad JR |
2762 | /* |
2763 | * This function is called by the DMA layer to find out if we can handle a | |
2764 | * particular device. It is part of the dma_ops. | |
2765 | */ | |
2766 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2767 | { | |
420aef8a | 2768 | return check_device(dev); |
b39ba6ad JR |
2769 | } |
2770 | ||
c432f3df | 2771 | /* |
431b2a20 JR |
2772 | * The function for pre-allocating protection domains. |
2773 | * | |
c432f3df JR |
2774 | * If the driver core informs the DMA layer if a driver grabs a device |
2775 | * we don't need to preallocate the protection domains anymore. | |
2776 | * For now we have to. | |
2777 | */ | |
0e93dd88 | 2778 | static void prealloc_protection_domains(void) |
c432f3df | 2779 | { |
5abcdba4 | 2780 | struct iommu_dev_data *dev_data; |
c432f3df | 2781 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2782 | struct pci_dev *dev = NULL; |
98fc5a69 | 2783 | u16 devid; |
c432f3df | 2784 | |
d18c69d3 | 2785 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2786 | |
2787 | /* Do we handle this device? */ | |
2788 | if (!check_device(&dev->dev)) | |
c432f3df | 2789 | continue; |
98fc5a69 | 2790 | |
5abcdba4 JR |
2791 | dev_data = get_dev_data(&dev->dev); |
2792 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2793 | /* Make sure passthrough domain is allocated */ | |
2794 | alloc_passthrough_domain(); | |
2795 | dev_data->passthrough = true; | |
2796 | attach_device(&dev->dev, pt_domain); | |
2797 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2798 | dev_name(&dev->dev)); | |
2799 | } | |
2800 | ||
98fc5a69 | 2801 | /* Is there already any domain for it? */ |
15898bbc | 2802 | if (domain_for_device(&dev->dev)) |
c432f3df | 2803 | continue; |
98fc5a69 JR |
2804 | |
2805 | devid = get_device_id(&dev->dev); | |
2806 | ||
87a64d52 | 2807 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2808 | if (!dma_dom) |
2809 | continue; | |
2810 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2811 | dma_dom->target_dev = devid; |
2812 | ||
15898bbc | 2813 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2814 | |
bd60b735 | 2815 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2816 | } |
2817 | } | |
2818 | ||
160c1d8e | 2819 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2820 | .alloc_coherent = alloc_coherent, |
2821 | .free_coherent = free_coherent, | |
51491367 FT |
2822 | .map_page = map_page, |
2823 | .unmap_page = unmap_page, | |
6631ee9d JR |
2824 | .map_sg = map_sg, |
2825 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2826 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2827 | }; |
2828 | ||
27c2127a JR |
2829 | static unsigned device_dma_ops_init(void) |
2830 | { | |
5abcdba4 | 2831 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2832 | struct pci_dev *pdev = NULL; |
2833 | unsigned unhandled = 0; | |
2834 | ||
2835 | for_each_pci_dev(pdev) { | |
2836 | if (!check_device(&pdev->dev)) { | |
2837 | unhandled += 1; | |
2838 | continue; | |
2839 | } | |
2840 | ||
5abcdba4 JR |
2841 | dev_data = get_dev_data(&pdev->dev); |
2842 | ||
2843 | if (!dev_data->passthrough) | |
2844 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2845 | else | |
2846 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
2847 | } |
2848 | ||
2849 | return unhandled; | |
2850 | } | |
2851 | ||
431b2a20 JR |
2852 | /* |
2853 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2854 | */ | |
f5325094 JR |
2855 | |
2856 | void __init amd_iommu_init_api(void) | |
2857 | { | |
2cc21c42 | 2858 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2859 | } |
2860 | ||
6631ee9d JR |
2861 | int __init amd_iommu_init_dma_ops(void) |
2862 | { | |
2863 | struct amd_iommu *iommu; | |
27c2127a | 2864 | int ret, unhandled; |
6631ee9d | 2865 | |
431b2a20 JR |
2866 | /* |
2867 | * first allocate a default protection domain for every IOMMU we | |
2868 | * found in the system. Devices not assigned to any other | |
2869 | * protection domain will be assigned to the default one. | |
2870 | */ | |
3bd22172 | 2871 | for_each_iommu(iommu) { |
87a64d52 | 2872 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2873 | if (iommu->default_dom == NULL) |
2874 | return -ENOMEM; | |
e2dc14a2 | 2875 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2876 | ret = iommu_init_unity_mappings(iommu); |
2877 | if (ret) | |
2878 | goto free_domains; | |
2879 | } | |
2880 | ||
431b2a20 | 2881 | /* |
8793abeb | 2882 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2883 | */ |
8793abeb | 2884 | prealloc_protection_domains(); |
6631ee9d JR |
2885 | |
2886 | iommu_detected = 1; | |
75f1cdf1 | 2887 | swiotlb = 0; |
6631ee9d | 2888 | |
431b2a20 | 2889 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2890 | unhandled = device_dma_ops_init(); |
2891 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2892 | /* There are unhandled devices - initialize swiotlb for them */ | |
2893 | swiotlb = 1; | |
2894 | } | |
6631ee9d | 2895 | |
7f26508b JR |
2896 | amd_iommu_stats_init(); |
2897 | ||
6631ee9d JR |
2898 | return 0; |
2899 | ||
2900 | free_domains: | |
2901 | ||
3bd22172 | 2902 | for_each_iommu(iommu) { |
6631ee9d JR |
2903 | if (iommu->default_dom) |
2904 | dma_ops_domain_free(iommu->default_dom); | |
2905 | } | |
2906 | ||
2907 | return ret; | |
2908 | } | |
6d98cd80 JR |
2909 | |
2910 | /***************************************************************************** | |
2911 | * | |
2912 | * The following functions belong to the exported interface of AMD IOMMU | |
2913 | * | |
2914 | * This interface allows access to lower level functions of the IOMMU | |
2915 | * like protection domain handling and assignement of devices to domains | |
2916 | * which is not possible with the dma_ops interface. | |
2917 | * | |
2918 | *****************************************************************************/ | |
2919 | ||
6d98cd80 JR |
2920 | static void cleanup_domain(struct protection_domain *domain) |
2921 | { | |
492667da | 2922 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2923 | unsigned long flags; |
6d98cd80 JR |
2924 | |
2925 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2926 | ||
492667da | 2927 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2928 | __detach_device(dev_data); |
492667da JR |
2929 | atomic_set(&dev_data->bind, 0); |
2930 | } | |
6d98cd80 JR |
2931 | |
2932 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2933 | } | |
2934 | ||
2650815f JR |
2935 | static void protection_domain_free(struct protection_domain *domain) |
2936 | { | |
2937 | if (!domain) | |
2938 | return; | |
2939 | ||
aeb26f55 JR |
2940 | del_domain_from_list(domain); |
2941 | ||
2650815f JR |
2942 | if (domain->id) |
2943 | domain_id_free(domain->id); | |
2944 | ||
2945 | kfree(domain); | |
2946 | } | |
2947 | ||
2948 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2949 | { |
2950 | struct protection_domain *domain; | |
2951 | ||
2952 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2953 | if (!domain) | |
2650815f | 2954 | return NULL; |
c156e347 JR |
2955 | |
2956 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2957 | mutex_init(&domain->api_lock); |
c156e347 JR |
2958 | domain->id = domain_id_alloc(); |
2959 | if (!domain->id) | |
2650815f | 2960 | goto out_err; |
7c392cbe | 2961 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2962 | |
aeb26f55 JR |
2963 | add_domain_to_list(domain); |
2964 | ||
2650815f JR |
2965 | return domain; |
2966 | ||
2967 | out_err: | |
2968 | kfree(domain); | |
2969 | ||
2970 | return NULL; | |
2971 | } | |
2972 | ||
5abcdba4 JR |
2973 | static int __init alloc_passthrough_domain(void) |
2974 | { | |
2975 | if (pt_domain != NULL) | |
2976 | return 0; | |
2977 | ||
2978 | /* allocate passthrough domain */ | |
2979 | pt_domain = protection_domain_alloc(); | |
2980 | if (!pt_domain) | |
2981 | return -ENOMEM; | |
2982 | ||
2983 | pt_domain->mode = PAGE_MODE_NONE; | |
2984 | ||
2985 | return 0; | |
2986 | } | |
2650815f JR |
2987 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2988 | { | |
2989 | struct protection_domain *domain; | |
2990 | ||
2991 | domain = protection_domain_alloc(); | |
2992 | if (!domain) | |
c156e347 | 2993 | goto out_free; |
2650815f JR |
2994 | |
2995 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2996 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2997 | if (!domain->pt_root) | |
2998 | goto out_free; | |
2999 | ||
f3572db8 JR |
3000 | domain->iommu_domain = dom; |
3001 | ||
c156e347 JR |
3002 | dom->priv = domain; |
3003 | ||
3004 | return 0; | |
3005 | ||
3006 | out_free: | |
2650815f | 3007 | protection_domain_free(domain); |
c156e347 JR |
3008 | |
3009 | return -ENOMEM; | |
3010 | } | |
3011 | ||
98383fc3 JR |
3012 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3013 | { | |
3014 | struct protection_domain *domain = dom->priv; | |
3015 | ||
3016 | if (!domain) | |
3017 | return; | |
3018 | ||
3019 | if (domain->dev_cnt > 0) | |
3020 | cleanup_domain(domain); | |
3021 | ||
3022 | BUG_ON(domain->dev_cnt != 0); | |
3023 | ||
132bd68f JR |
3024 | if (domain->mode != PAGE_MODE_NONE) |
3025 | free_pagetable(domain); | |
98383fc3 | 3026 | |
52815b75 JR |
3027 | if (domain->flags & PD_IOMMUV2_MASK) |
3028 | free_gcr3_table(domain); | |
3029 | ||
8b408fe4 | 3030 | protection_domain_free(domain); |
98383fc3 JR |
3031 | |
3032 | dom->priv = NULL; | |
3033 | } | |
3034 | ||
684f2888 JR |
3035 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3036 | struct device *dev) | |
3037 | { | |
657cbb6b | 3038 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3039 | struct amd_iommu *iommu; |
684f2888 JR |
3040 | u16 devid; |
3041 | ||
98fc5a69 | 3042 | if (!check_device(dev)) |
684f2888 JR |
3043 | return; |
3044 | ||
98fc5a69 | 3045 | devid = get_device_id(dev); |
684f2888 | 3046 | |
657cbb6b | 3047 | if (dev_data->domain != NULL) |
15898bbc | 3048 | detach_device(dev); |
684f2888 JR |
3049 | |
3050 | iommu = amd_iommu_rlookup_table[devid]; | |
3051 | if (!iommu) | |
3052 | return; | |
3053 | ||
684f2888 JR |
3054 | iommu_completion_wait(iommu); |
3055 | } | |
3056 | ||
01106066 JR |
3057 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3058 | struct device *dev) | |
3059 | { | |
3060 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3061 | struct iommu_dev_data *dev_data; |
01106066 | 3062 | struct amd_iommu *iommu; |
15898bbc | 3063 | int ret; |
01106066 | 3064 | |
98fc5a69 | 3065 | if (!check_device(dev)) |
01106066 JR |
3066 | return -EINVAL; |
3067 | ||
657cbb6b JR |
3068 | dev_data = dev->archdata.iommu; |
3069 | ||
f62dda66 | 3070 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3071 | if (!iommu) |
3072 | return -EINVAL; | |
3073 | ||
657cbb6b | 3074 | if (dev_data->domain) |
15898bbc | 3075 | detach_device(dev); |
01106066 | 3076 | |
15898bbc | 3077 | ret = attach_device(dev, domain); |
01106066 JR |
3078 | |
3079 | iommu_completion_wait(iommu); | |
3080 | ||
15898bbc | 3081 | return ret; |
01106066 JR |
3082 | } |
3083 | ||
468e2366 JR |
3084 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
3085 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 3086 | { |
468e2366 | 3087 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 3088 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
3089 | int prot = 0; |
3090 | int ret; | |
3091 | ||
132bd68f JR |
3092 | if (domain->mode == PAGE_MODE_NONE) |
3093 | return -EINVAL; | |
3094 | ||
c6229ca6 JR |
3095 | if (iommu_prot & IOMMU_READ) |
3096 | prot |= IOMMU_PROT_IR; | |
3097 | if (iommu_prot & IOMMU_WRITE) | |
3098 | prot |= IOMMU_PROT_IW; | |
3099 | ||
5d214fe6 | 3100 | mutex_lock(&domain->api_lock); |
795e74f7 | 3101 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3102 | mutex_unlock(&domain->api_lock); |
3103 | ||
795e74f7 | 3104 | return ret; |
c6229ca6 JR |
3105 | } |
3106 | ||
468e2366 JR |
3107 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3108 | int gfp_order) | |
eb74ff6c | 3109 | { |
eb74ff6c | 3110 | struct protection_domain *domain = dom->priv; |
468e2366 | 3111 | unsigned long page_size, unmap_size; |
eb74ff6c | 3112 | |
132bd68f JR |
3113 | if (domain->mode == PAGE_MODE_NONE) |
3114 | return -EINVAL; | |
3115 | ||
468e2366 | 3116 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 3117 | |
5d214fe6 | 3118 | mutex_lock(&domain->api_lock); |
468e2366 | 3119 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3120 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3121 | |
17b124bf | 3122 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3123 | |
468e2366 | 3124 | return get_order(unmap_size); |
eb74ff6c JR |
3125 | } |
3126 | ||
645c4c8d JR |
3127 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3128 | unsigned long iova) | |
3129 | { | |
3130 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3131 | unsigned long offset_mask; |
645c4c8d | 3132 | phys_addr_t paddr; |
f03152bb | 3133 | u64 *pte, __pte; |
645c4c8d | 3134 | |
132bd68f JR |
3135 | if (domain->mode == PAGE_MODE_NONE) |
3136 | return iova; | |
3137 | ||
24cd7723 | 3138 | pte = fetch_pte(domain, iova); |
645c4c8d | 3139 | |
a6d41a40 | 3140 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3141 | return 0; |
3142 | ||
f03152bb JR |
3143 | if (PM_PTE_LEVEL(*pte) == 0) |
3144 | offset_mask = PAGE_SIZE - 1; | |
3145 | else | |
3146 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3147 | ||
3148 | __pte = *pte & PM_ADDR_MASK; | |
3149 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3150 | |
3151 | return paddr; | |
3152 | } | |
3153 | ||
dbb9fd86 SY |
3154 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3155 | unsigned long cap) | |
3156 | { | |
80a506b8 JR |
3157 | switch (cap) { |
3158 | case IOMMU_CAP_CACHE_COHERENCY: | |
3159 | return 1; | |
3160 | } | |
3161 | ||
dbb9fd86 SY |
3162 | return 0; |
3163 | } | |
3164 | ||
26961efe JR |
3165 | static struct iommu_ops amd_iommu_ops = { |
3166 | .domain_init = amd_iommu_domain_init, | |
3167 | .domain_destroy = amd_iommu_domain_destroy, | |
3168 | .attach_dev = amd_iommu_attach_device, | |
3169 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3170 | .map = amd_iommu_map, |
3171 | .unmap = amd_iommu_unmap, | |
26961efe | 3172 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3173 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
3174 | }; |
3175 | ||
0feae533 JR |
3176 | /***************************************************************************** |
3177 | * | |
3178 | * The next functions do a basic initialization of IOMMU for pass through | |
3179 | * mode | |
3180 | * | |
3181 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3182 | * DMA-API translation. | |
3183 | * | |
3184 | *****************************************************************************/ | |
3185 | ||
3186 | int __init amd_iommu_init_passthrough(void) | |
3187 | { | |
5abcdba4 | 3188 | struct iommu_dev_data *dev_data; |
0feae533 | 3189 | struct pci_dev *dev = NULL; |
5abcdba4 | 3190 | struct amd_iommu *iommu; |
15898bbc | 3191 | u16 devid; |
5abcdba4 | 3192 | int ret; |
0feae533 | 3193 | |
5abcdba4 JR |
3194 | ret = alloc_passthrough_domain(); |
3195 | if (ret) | |
3196 | return ret; | |
0feae533 | 3197 | |
6c54aabd | 3198 | for_each_pci_dev(dev) { |
98fc5a69 | 3199 | if (!check_device(&dev->dev)) |
0feae533 JR |
3200 | continue; |
3201 | ||
5abcdba4 JR |
3202 | dev_data = get_dev_data(&dev->dev); |
3203 | dev_data->passthrough = true; | |
3204 | ||
98fc5a69 JR |
3205 | devid = get_device_id(&dev->dev); |
3206 | ||
15898bbc | 3207 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3208 | if (!iommu) |
3209 | continue; | |
3210 | ||
15898bbc | 3211 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3212 | } |
3213 | ||
3214 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
3215 | ||
3216 | return 0; | |
3217 | } | |
72e1dcc4 JR |
3218 | |
3219 | /* IOMMUv2 specific functions */ | |
3220 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3221 | { | |
3222 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3223 | } | |
3224 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3225 | ||
3226 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3227 | { | |
3228 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3229 | } | |
3230 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3231 | |
3232 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3233 | { | |
3234 | struct protection_domain *domain = dom->priv; | |
3235 | unsigned long flags; | |
3236 | ||
3237 | spin_lock_irqsave(&domain->lock, flags); | |
3238 | ||
3239 | /* Update data structure */ | |
3240 | domain->mode = PAGE_MODE_NONE; | |
3241 | domain->updated = true; | |
3242 | ||
3243 | /* Make changes visible to IOMMUs */ | |
3244 | update_domain(domain); | |
3245 | ||
3246 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3247 | free_pagetable(domain); | |
3248 | ||
3249 | spin_unlock_irqrestore(&domain->lock, flags); | |
3250 | } | |
3251 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3252 | |
3253 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3254 | { | |
3255 | struct protection_domain *domain = dom->priv; | |
3256 | unsigned long flags; | |
3257 | int levels, ret; | |
3258 | ||
3259 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3260 | return -EINVAL; | |
3261 | ||
3262 | /* Number of GCR3 table levels required */ | |
3263 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3264 | levels += 1; | |
3265 | ||
3266 | if (levels > amd_iommu_max_glx_val) | |
3267 | return -EINVAL; | |
3268 | ||
3269 | spin_lock_irqsave(&domain->lock, flags); | |
3270 | ||
3271 | /* | |
3272 | * Save us all sanity checks whether devices already in the | |
3273 | * domain support IOMMUv2. Just force that the domain has no | |
3274 | * devices attached when it is switched into IOMMUv2 mode. | |
3275 | */ | |
3276 | ret = -EBUSY; | |
3277 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3278 | goto out; | |
3279 | ||
3280 | ret = -ENOMEM; | |
3281 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3282 | if (domain->gcr3_tbl == NULL) | |
3283 | goto out; | |
3284 | ||
3285 | domain->glx = levels; | |
3286 | domain->flags |= PD_IOMMUV2_MASK; | |
3287 | domain->updated = true; | |
3288 | ||
3289 | update_domain(domain); | |
3290 | ||
3291 | ret = 0; | |
3292 | ||
3293 | out: | |
3294 | spin_unlock_irqrestore(&domain->lock, flags); | |
3295 | ||
3296 | return ret; | |
3297 | } | |
3298 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3299 | |
3300 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3301 | u64 address, bool size) | |
3302 | { | |
3303 | struct iommu_dev_data *dev_data; | |
3304 | struct iommu_cmd cmd; | |
3305 | int i, ret; | |
3306 | ||
3307 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3308 | return -EINVAL; | |
3309 | ||
3310 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3311 | ||
3312 | /* | |
3313 | * IOMMU TLB needs to be flushed before Device TLB to | |
3314 | * prevent device TLB refill from IOMMU TLB | |
3315 | */ | |
3316 | for (i = 0; i < amd_iommus_present; ++i) { | |
3317 | if (domain->dev_iommu[i] == 0) | |
3318 | continue; | |
3319 | ||
3320 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3321 | if (ret != 0) | |
3322 | goto out; | |
3323 | } | |
3324 | ||
3325 | /* Wait until IOMMU TLB flushes are complete */ | |
3326 | domain_flush_complete(domain); | |
3327 | ||
3328 | /* Now flush device TLBs */ | |
3329 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3330 | struct amd_iommu *iommu; | |
3331 | int qdep; | |
3332 | ||
3333 | BUG_ON(!dev_data->ats.enabled); | |
3334 | ||
3335 | qdep = dev_data->ats.qdep; | |
3336 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3337 | ||
3338 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3339 | qdep, address, size); | |
3340 | ||
3341 | ret = iommu_queue_command(iommu, &cmd); | |
3342 | if (ret != 0) | |
3343 | goto out; | |
3344 | } | |
3345 | ||
3346 | /* Wait until all device TLBs are flushed */ | |
3347 | domain_flush_complete(domain); | |
3348 | ||
3349 | ret = 0; | |
3350 | ||
3351 | out: | |
3352 | ||
3353 | return ret; | |
3354 | } | |
3355 | ||
3356 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3357 | u64 address) | |
3358 | { | |
3359 | return __flush_pasid(domain, pasid, address, false); | |
3360 | } | |
3361 | ||
3362 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3363 | u64 address) | |
3364 | { | |
3365 | struct protection_domain *domain = dom->priv; | |
3366 | unsigned long flags; | |
3367 | int ret; | |
3368 | ||
3369 | spin_lock_irqsave(&domain->lock, flags); | |
3370 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3371 | spin_unlock_irqrestore(&domain->lock, flags); | |
3372 | ||
3373 | return ret; | |
3374 | } | |
3375 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3376 | ||
3377 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3378 | { | |
3379 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3380 | true); | |
3381 | } | |
3382 | ||
3383 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3384 | { | |
3385 | struct protection_domain *domain = dom->priv; | |
3386 | unsigned long flags; | |
3387 | int ret; | |
3388 | ||
3389 | spin_lock_irqsave(&domain->lock, flags); | |
3390 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3391 | spin_unlock_irqrestore(&domain->lock, flags); | |
3392 | ||
3393 | return ret; | |
3394 | } | |
3395 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3396 | ||
b16137b1 JR |
3397 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3398 | { | |
3399 | int index; | |
3400 | u64 *pte; | |
3401 | ||
3402 | while (true) { | |
3403 | ||
3404 | index = (pasid >> (9 * level)) & 0x1ff; | |
3405 | pte = &root[index]; | |
3406 | ||
3407 | if (level == 0) | |
3408 | break; | |
3409 | ||
3410 | if (!(*pte & GCR3_VALID)) { | |
3411 | if (!alloc) | |
3412 | return NULL; | |
3413 | ||
3414 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3415 | if (root == NULL) | |
3416 | return NULL; | |
3417 | ||
3418 | *pte = __pa(root) | GCR3_VALID; | |
3419 | } | |
3420 | ||
3421 | root = __va(*pte & PAGE_MASK); | |
3422 | ||
3423 | level -= 1; | |
3424 | } | |
3425 | ||
3426 | return pte; | |
3427 | } | |
3428 | ||
3429 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3430 | unsigned long cr3) | |
3431 | { | |
3432 | u64 *pte; | |
3433 | ||
3434 | if (domain->mode != PAGE_MODE_NONE) | |
3435 | return -EINVAL; | |
3436 | ||
3437 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3438 | if (pte == NULL) | |
3439 | return -ENOMEM; | |
3440 | ||
3441 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3442 | ||
3443 | return __amd_iommu_flush_tlb(domain, pasid); | |
3444 | } | |
3445 | ||
3446 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3447 | { | |
3448 | u64 *pte; | |
3449 | ||
3450 | if (domain->mode != PAGE_MODE_NONE) | |
3451 | return -EINVAL; | |
3452 | ||
3453 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3454 | if (pte == NULL) | |
3455 | return 0; | |
3456 | ||
3457 | *pte = 0; | |
3458 | ||
3459 | return __amd_iommu_flush_tlb(domain, pasid); | |
3460 | } | |
3461 | ||
3462 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3463 | unsigned long cr3) | |
3464 | { | |
3465 | struct protection_domain *domain = dom->priv; | |
3466 | unsigned long flags; | |
3467 | int ret; | |
3468 | ||
3469 | spin_lock_irqsave(&domain->lock, flags); | |
3470 | ret = __set_gcr3(domain, pasid, cr3); | |
3471 | spin_unlock_irqrestore(&domain->lock, flags); | |
3472 | ||
3473 | return ret; | |
3474 | } | |
3475 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3476 | ||
3477 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3478 | { | |
3479 | struct protection_domain *domain = dom->priv; | |
3480 | unsigned long flags; | |
3481 | int ret; | |
3482 | ||
3483 | spin_lock_irqsave(&domain->lock, flags); | |
3484 | ret = __clear_gcr3(domain, pasid); | |
3485 | spin_unlock_irqrestore(&domain->lock, flags); | |
3486 | ||
3487 | return ret; | |
3488 | } | |
3489 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3490 | |
3491 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3492 | int status, int tag) | |
3493 | { | |
3494 | struct iommu_dev_data *dev_data; | |
3495 | struct amd_iommu *iommu; | |
3496 | struct iommu_cmd cmd; | |
3497 | ||
3498 | dev_data = get_dev_data(&pdev->dev); | |
3499 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3500 | ||
3501 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3502 | tag, dev_data->pri_tlp); | |
3503 | ||
3504 | return iommu_queue_command(iommu, &cmd); | |
3505 | } | |
3506 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3507 | |
3508 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3509 | { | |
3510 | struct protection_domain *domain; | |
3511 | ||
3512 | domain = get_domain(&pdev->dev); | |
3513 | if (IS_ERR(domain)) | |
3514 | return NULL; | |
3515 | ||
3516 | /* Only return IOMMUv2 domains */ | |
3517 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3518 | return NULL; | |
3519 | ||
3520 | return domain->iommu_domain; | |
3521 | } | |
3522 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3523 | |
3524 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3525 | { | |
3526 | struct iommu_dev_data *dev_data; | |
3527 | ||
3528 | if (!amd_iommu_v2_supported()) | |
3529 | return; | |
3530 | ||
3531 | dev_data = get_dev_data(&pdev->dev); | |
3532 | dev_data->errata |= (1 << erratum); | |
3533 | } | |
3534 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); |