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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
36 | #include <asm/irq_remapping.h> | |
37 | #include <asm/io_apic.h> | |
38 | #include <asm/apic.h> | |
39 | #include <asm/hw_irq.h> | |
17f5b569 | 40 | #include <asm/msidef.h> |
b6c02715 | 41 | #include <asm/proto.h> |
46a7fa27 | 42 | #include <asm/iommu.h> |
1d9b16d1 | 43 | #include <asm/gart.h> |
27c2127a | 44 | #include <asm/dma.h> |
403f81d8 JR |
45 | |
46 | #include "amd_iommu_proto.h" | |
47 | #include "amd_iommu_types.h" | |
6b474b82 | 48 | #include "irq_remapping.h" |
61e015ac | 49 | #include "pci.h" |
b6c02715 JR |
50 | |
51 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
52 | ||
815b33fd | 53 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 54 | |
aa3de9c0 OBC |
55 | /* |
56 | * This bitmap is used to advertise the page sizes our hardware support | |
57 | * to the IOMMU core, which will then use this information to split | |
58 | * physically contiguous memory regions it is mapping into page sizes | |
59 | * that we support. | |
60 | * | |
954e3dd8 | 61 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 62 | */ |
954e3dd8 | 63 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 64 | |
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
6efed63b JR |
75 | LIST_HEAD(ioapic_map); |
76 | LIST_HEAD(hpet_map); | |
77 | ||
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
82 | static struct protection_domain *pt_domain; | |
83 | ||
26961efe | 84 | static struct iommu_ops amd_iommu_ops; |
26961efe | 85 | |
72e1dcc4 | 86 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 87 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 88 | |
ac1534a5 JR |
89 | static struct dma_map_ops amd_iommu_dma_ops; |
90 | ||
431b2a20 JR |
91 | /* |
92 | * general struct to manage commands send to an IOMMU | |
93 | */ | |
d6449536 | 94 | struct iommu_cmd { |
b6c02715 JR |
95 | u32 data[4]; |
96 | }; | |
97 | ||
05152a04 JR |
98 | struct kmem_cache *amd_iommu_irq_cache; |
99 | ||
04bfdd84 | 100 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 101 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 102 | |
15898bbc JR |
103 | /**************************************************************************** |
104 | * | |
105 | * Helper functions | |
106 | * | |
107 | ****************************************************************************/ | |
108 | ||
f62dda66 | 109 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
110 | { |
111 | struct iommu_dev_data *dev_data; | |
112 | unsigned long flags; | |
113 | ||
114 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
115 | if (!dev_data) | |
116 | return NULL; | |
117 | ||
f62dda66 | 118 | dev_data->devid = devid; |
8fa5f802 JR |
119 | atomic_set(&dev_data->bind, 0); |
120 | ||
121 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
122 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
123 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
124 | ||
125 | return dev_data; | |
126 | } | |
127 | ||
128 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
133 | list_del(&dev_data->dev_data_list); | |
134 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
135 | ||
78bfa9f3 AW |
136 | if (dev_data->group) |
137 | iommu_group_put(dev_data->group); | |
138 | ||
8fa5f802 JR |
139 | kfree(dev_data); |
140 | } | |
141 | ||
3b03bb74 JR |
142 | static struct iommu_dev_data *search_dev_data(u16 devid) |
143 | { | |
144 | struct iommu_dev_data *dev_data; | |
145 | unsigned long flags; | |
146 | ||
147 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
148 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
149 | if (dev_data->devid == devid) | |
150 | goto out_unlock; | |
151 | } | |
152 | ||
153 | dev_data = NULL; | |
154 | ||
155 | out_unlock: | |
156 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
157 | ||
158 | return dev_data; | |
159 | } | |
160 | ||
161 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
162 | { | |
163 | struct iommu_dev_data *dev_data; | |
164 | ||
165 | dev_data = search_dev_data(devid); | |
166 | ||
167 | if (dev_data == NULL) | |
168 | dev_data = alloc_dev_data(devid); | |
169 | ||
170 | return dev_data; | |
171 | } | |
172 | ||
15898bbc JR |
173 | static inline u16 get_device_id(struct device *dev) |
174 | { | |
175 | struct pci_dev *pdev = to_pci_dev(dev); | |
176 | ||
6f2729ba | 177 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
178 | } |
179 | ||
657cbb6b JR |
180 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
181 | { | |
182 | return dev->archdata.iommu; | |
183 | } | |
184 | ||
5abcdba4 JR |
185 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
186 | { | |
187 | static const int caps[] = { | |
188 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
189 | PCI_EXT_CAP_ID_PRI, |
190 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
191 | }; |
192 | int i, pos; | |
193 | ||
194 | for (i = 0; i < 3; ++i) { | |
195 | pos = pci_find_ext_capability(pdev, caps[i]); | |
196 | if (pos == 0) | |
197 | return false; | |
198 | } | |
199 | ||
200 | return true; | |
201 | } | |
202 | ||
6a113ddc JR |
203 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
204 | { | |
205 | struct iommu_dev_data *dev_data; | |
206 | ||
207 | dev_data = get_dev_data(&pdev->dev); | |
208 | ||
209 | return dev_data->errata & (1 << erratum) ? true : false; | |
210 | } | |
211 | ||
71c70984 JR |
212 | /* |
213 | * In this function the list of preallocated protection domains is traversed to | |
214 | * find the domain for a specific device | |
215 | */ | |
216 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
217 | { | |
218 | struct dma_ops_domain *entry, *ret = NULL; | |
219 | unsigned long flags; | |
220 | u16 alias = amd_iommu_alias_table[devid]; | |
221 | ||
222 | if (list_empty(&iommu_pd_list)) | |
223 | return NULL; | |
224 | ||
225 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
226 | ||
227 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
228 | if (entry->target_dev == devid || | |
229 | entry->target_dev == alias) { | |
230 | ret = entry; | |
231 | break; | |
232 | } | |
233 | } | |
234 | ||
235 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
98fc5a69 JR |
240 | /* |
241 | * This function checks if the driver got a valid device from the caller to | |
242 | * avoid dereferencing invalid pointers. | |
243 | */ | |
244 | static bool check_device(struct device *dev) | |
245 | { | |
246 | u16 devid; | |
247 | ||
248 | if (!dev || !dev->dma_mask) | |
249 | return false; | |
250 | ||
251 | /* No device or no PCI device */ | |
339d3261 | 252 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
253 | return false; |
254 | ||
255 | devid = get_device_id(dev); | |
256 | ||
257 | /* Out of our scope? */ | |
258 | if (devid > amd_iommu_last_bdf) | |
259 | return false; | |
260 | ||
261 | if (amd_iommu_rlookup_table[devid] == NULL) | |
262 | return false; | |
263 | ||
264 | return true; | |
265 | } | |
266 | ||
2bff6a50 AW |
267 | static struct pci_bus *find_hosted_bus(struct pci_bus *bus) |
268 | { | |
269 | while (!bus->self) { | |
270 | if (!pci_is_root_bus(bus)) | |
271 | bus = bus->parent; | |
272 | else | |
273 | return ERR_PTR(-ENODEV); | |
274 | } | |
275 | ||
276 | return bus; | |
277 | } | |
278 | ||
664b6003 AW |
279 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
280 | ||
2851db21 | 281 | static struct pci_dev *get_isolation_root(struct pci_dev *pdev) |
657cbb6b | 282 | { |
2851db21 | 283 | struct pci_dev *dma_pdev = pdev; |
9dcd6130 | 284 | |
31fe9435 | 285 | /* Account for quirked devices */ |
664b6003 AW |
286 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
287 | ||
31fe9435 AW |
288 | /* |
289 | * If it's a multifunction device that does not support our | |
290 | * required ACS flags, add to the same group as function 0. | |
291 | */ | |
664b6003 AW |
292 | if (dma_pdev->multifunction && |
293 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) | |
294 | swap_pci_ref(&dma_pdev, | |
295 | pci_get_slot(dma_pdev->bus, | |
296 | PCI_DEVFN(PCI_SLOT(dma_pdev->devfn), | |
297 | 0))); | |
298 | ||
31fe9435 AW |
299 | /* |
300 | * Devices on the root bus go through the iommu. If that's not us, | |
301 | * find the next upstream device and test ACS up to the root bus. | |
302 | * Finding the next device may require skipping virtual buses. | |
303 | */ | |
664b6003 | 304 | while (!pci_is_root_bus(dma_pdev->bus)) { |
2bff6a50 AW |
305 | struct pci_bus *bus = find_hosted_bus(dma_pdev->bus); |
306 | if (IS_ERR(bus)) | |
307 | break; | |
31fe9435 AW |
308 | |
309 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
664b6003 AW |
310 | break; |
311 | ||
31fe9435 | 312 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
664b6003 AW |
313 | } |
314 | ||
2851db21 AW |
315 | return dma_pdev; |
316 | } | |
317 | ||
ce7ac4ab AW |
318 | static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev) |
319 | { | |
320 | struct iommu_group *group = iommu_group_get(&pdev->dev); | |
321 | int ret; | |
322 | ||
323 | if (!group) { | |
324 | group = iommu_group_alloc(); | |
325 | if (IS_ERR(group)) | |
326 | return PTR_ERR(group); | |
327 | ||
328 | WARN_ON(&pdev->dev != dev); | |
329 | } | |
330 | ||
331 | ret = iommu_group_add_device(group, dev); | |
332 | iommu_group_put(group); | |
333 | return ret; | |
334 | } | |
335 | ||
78bfa9f3 AW |
336 | static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data, |
337 | struct device *dev) | |
338 | { | |
339 | if (!dev_data->group) { | |
340 | struct iommu_group *group = iommu_group_alloc(); | |
341 | if (IS_ERR(group)) | |
342 | return PTR_ERR(group); | |
343 | ||
344 | dev_data->group = group; | |
345 | } | |
346 | ||
347 | return iommu_group_add_device(dev_data->group, dev); | |
348 | } | |
349 | ||
2851db21 AW |
350 | static int init_iommu_group(struct device *dev) |
351 | { | |
352 | struct iommu_dev_data *dev_data; | |
353 | struct iommu_group *group; | |
78bfa9f3 | 354 | struct pci_dev *dma_pdev; |
2851db21 AW |
355 | int ret; |
356 | ||
357 | group = iommu_group_get(dev); | |
358 | if (group) { | |
359 | iommu_group_put(group); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | dev_data = find_dev_data(get_device_id(dev)); | |
364 | if (!dev_data) | |
365 | return -ENOMEM; | |
366 | ||
367 | if (dev_data->alias_data) { | |
368 | u16 alias; | |
78bfa9f3 AW |
369 | struct pci_bus *bus; |
370 | ||
371 | if (dev_data->alias_data->group) | |
372 | goto use_group; | |
2851db21 | 373 | |
78bfa9f3 AW |
374 | /* |
375 | * If the alias device exists, it's effectively just a first | |
376 | * level quirk for finding the DMA source. | |
377 | */ | |
2851db21 AW |
378 | alias = amd_iommu_alias_table[dev_data->devid]; |
379 | dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); | |
78bfa9f3 AW |
380 | if (dma_pdev) { |
381 | dma_pdev = get_isolation_root(dma_pdev); | |
382 | goto use_pdev; | |
383 | } | |
2851db21 | 384 | |
78bfa9f3 AW |
385 | /* |
386 | * If the alias is virtual, try to find a parent device | |
387 | * and test whether the IOMMU group is actualy rooted above | |
388 | * the alias. Be careful to also test the parent device if | |
389 | * we think the alias is the root of the group. | |
390 | */ | |
391 | bus = pci_find_bus(0, alias >> 8); | |
392 | if (!bus) | |
393 | goto use_group; | |
394 | ||
395 | bus = find_hosted_bus(bus); | |
396 | if (IS_ERR(bus) || !bus->self) | |
397 | goto use_group; | |
398 | ||
399 | dma_pdev = get_isolation_root(pci_dev_get(bus->self)); | |
400 | if (dma_pdev != bus->self || (dma_pdev->multifunction && | |
401 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))) | |
402 | goto use_pdev; | |
403 | ||
404 | pci_dev_put(dma_pdev); | |
405 | goto use_group; | |
406 | } | |
2851db21 | 407 | |
78bfa9f3 AW |
408 | dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev))); |
409 | use_pdev: | |
ce7ac4ab | 410 | ret = use_pdev_iommu_group(dma_pdev, dev); |
9dcd6130 | 411 | pci_dev_put(dma_pdev); |
eb9c9527 | 412 | return ret; |
78bfa9f3 AW |
413 | use_group: |
414 | return use_dev_data_iommu_group(dev_data->alias_data, dev); | |
eb9c9527 AW |
415 | } |
416 | ||
417 | static int iommu_init_device(struct device *dev) | |
418 | { | |
419 | struct pci_dev *pdev = to_pci_dev(dev); | |
420 | struct iommu_dev_data *dev_data; | |
421 | u16 alias; | |
422 | int ret; | |
423 | ||
424 | if (dev->archdata.iommu) | |
425 | return 0; | |
426 | ||
427 | dev_data = find_dev_data(get_device_id(dev)); | |
428 | if (!dev_data) | |
429 | return -ENOMEM; | |
430 | ||
431 | alias = amd_iommu_alias_table[dev_data->devid]; | |
432 | if (alias != dev_data->devid) { | |
433 | struct iommu_dev_data *alias_data; | |
434 | ||
435 | alias_data = find_dev_data(alias); | |
436 | if (alias_data == NULL) { | |
437 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
438 | dev_name(dev)); | |
439 | free_dev_data(dev_data); | |
440 | return -ENOTSUPP; | |
441 | } | |
442 | dev_data->alias_data = alias_data; | |
443 | } | |
444 | ||
445 | ret = init_iommu_group(dev); | |
9dcd6130 AW |
446 | if (ret) |
447 | return ret; | |
448 | ||
5abcdba4 JR |
449 | if (pci_iommuv2_capable(pdev)) { |
450 | struct amd_iommu *iommu; | |
451 | ||
452 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
453 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
454 | } | |
455 | ||
657cbb6b JR |
456 | dev->archdata.iommu = dev_data; |
457 | ||
657cbb6b JR |
458 | return 0; |
459 | } | |
460 | ||
26018874 JR |
461 | static void iommu_ignore_device(struct device *dev) |
462 | { | |
463 | u16 devid, alias; | |
464 | ||
465 | devid = get_device_id(dev); | |
466 | alias = amd_iommu_alias_table[devid]; | |
467 | ||
468 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
469 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
470 | ||
471 | amd_iommu_rlookup_table[devid] = NULL; | |
472 | amd_iommu_rlookup_table[alias] = NULL; | |
473 | } | |
474 | ||
657cbb6b JR |
475 | static void iommu_uninit_device(struct device *dev) |
476 | { | |
9dcd6130 AW |
477 | iommu_group_remove_device(dev); |
478 | ||
8fa5f802 JR |
479 | /* |
480 | * Nothing to do here - we keep dev_data around for unplugged devices | |
481 | * and reuse it when the device is re-plugged - not doing so would | |
482 | * introduce a ton of races. | |
483 | */ | |
657cbb6b | 484 | } |
b7cc9554 JR |
485 | |
486 | void __init amd_iommu_uninit_devices(void) | |
487 | { | |
8fa5f802 | 488 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
489 | struct pci_dev *pdev = NULL; |
490 | ||
491 | for_each_pci_dev(pdev) { | |
492 | ||
493 | if (!check_device(&pdev->dev)) | |
494 | continue; | |
495 | ||
496 | iommu_uninit_device(&pdev->dev); | |
497 | } | |
8fa5f802 JR |
498 | |
499 | /* Free all of our dev_data structures */ | |
500 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
501 | free_dev_data(dev_data); | |
b7cc9554 JR |
502 | } |
503 | ||
504 | int __init amd_iommu_init_devices(void) | |
505 | { | |
506 | struct pci_dev *pdev = NULL; | |
507 | int ret = 0; | |
508 | ||
509 | for_each_pci_dev(pdev) { | |
510 | ||
511 | if (!check_device(&pdev->dev)) | |
512 | continue; | |
513 | ||
514 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
515 | if (ret == -ENOTSUPP) |
516 | iommu_ignore_device(&pdev->dev); | |
517 | else if (ret) | |
b7cc9554 JR |
518 | goto out_free; |
519 | } | |
520 | ||
521 | return 0; | |
522 | ||
523 | out_free: | |
524 | ||
525 | amd_iommu_uninit_devices(); | |
526 | ||
527 | return ret; | |
528 | } | |
7f26508b JR |
529 | #ifdef CONFIG_AMD_IOMMU_STATS |
530 | ||
531 | /* | |
532 | * Initialization code for statistics collection | |
533 | */ | |
534 | ||
da49f6df | 535 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 536 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 537 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 538 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 539 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 540 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 541 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 542 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 543 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 544 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 545 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 546 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
547 | DECLARE_STATS_COUNTER(complete_ppr); |
548 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
549 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
550 | DECLARE_STATS_COUNTER(pri_requests); | |
551 | ||
7f26508b | 552 | static struct dentry *stats_dir; |
7f26508b JR |
553 | static struct dentry *de_fflush; |
554 | ||
555 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
556 | { | |
557 | if (stats_dir == NULL) | |
558 | return; | |
559 | ||
560 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
561 | &cnt->value); | |
562 | } | |
563 | ||
564 | static void amd_iommu_stats_init(void) | |
565 | { | |
566 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
567 | if (stats_dir == NULL) | |
568 | return; | |
569 | ||
7f26508b | 570 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 571 | &amd_iommu_unmap_flush); |
da49f6df JR |
572 | |
573 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 574 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 575 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 576 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 577 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 578 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 579 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 580 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 581 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 582 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 583 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 584 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
585 | amd_iommu_stats_add(&complete_ppr); |
586 | amd_iommu_stats_add(&invalidate_iotlb); | |
587 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
588 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
589 | } |
590 | ||
591 | #endif | |
592 | ||
a80dc3e0 JR |
593 | /**************************************************************************** |
594 | * | |
595 | * Interrupt handling functions | |
596 | * | |
597 | ****************************************************************************/ | |
598 | ||
e3e59876 JR |
599 | static void dump_dte_entry(u16 devid) |
600 | { | |
601 | int i; | |
602 | ||
ee6c2868 JR |
603 | for (i = 0; i < 4; ++i) |
604 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
605 | amd_iommu_dev_table[devid].data[i]); |
606 | } | |
607 | ||
945b4ac4 JR |
608 | static void dump_command(unsigned long phys_addr) |
609 | { | |
610 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
611 | int i; | |
612 | ||
613 | for (i = 0; i < 4; ++i) | |
614 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
615 | } | |
616 | ||
a345b23b | 617 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 618 | { |
3d06fca8 JR |
619 | int type, devid, domid, flags; |
620 | volatile u32 *event = __evt; | |
621 | int count = 0; | |
622 | u64 address; | |
623 | ||
624 | retry: | |
625 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
626 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
627 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
628 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
629 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
630 | ||
631 | if (type == 0) { | |
632 | /* Did we hit the erratum? */ | |
633 | if (++count == LOOP_TIMEOUT) { | |
634 | pr_err("AMD-Vi: No event written to event log\n"); | |
635 | return; | |
636 | } | |
637 | udelay(1); | |
638 | goto retry; | |
639 | } | |
90008ee4 | 640 | |
4c6f40d4 | 641 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
642 | |
643 | switch (type) { | |
644 | case EVENT_TYPE_ILL_DEV: | |
645 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
646 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 647 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 648 | address, flags); |
e3e59876 | 649 | dump_dte_entry(devid); |
90008ee4 JR |
650 | break; |
651 | case EVENT_TYPE_IO_FAULT: | |
652 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
653 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 654 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
655 | domid, address, flags); |
656 | break; | |
657 | case EVENT_TYPE_DEV_TAB_ERR: | |
658 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
659 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 660 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
661 | address, flags); |
662 | break; | |
663 | case EVENT_TYPE_PAGE_TAB_ERR: | |
664 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
665 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 666 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
667 | domid, address, flags); |
668 | break; | |
669 | case EVENT_TYPE_ILL_CMD: | |
670 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 671 | dump_command(address); |
90008ee4 JR |
672 | break; |
673 | case EVENT_TYPE_CMD_HARD_ERR: | |
674 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
675 | "flags=0x%04x]\n", address, flags); | |
676 | break; | |
677 | case EVENT_TYPE_IOTLB_INV_TO: | |
678 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
679 | "address=0x%016llx]\n", | |
c5081cd7 | 680 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
681 | address); |
682 | break; | |
683 | case EVENT_TYPE_INV_DEV_REQ: | |
684 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
685 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 686 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
687 | address, flags); |
688 | break; | |
689 | default: | |
690 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
691 | } | |
3d06fca8 JR |
692 | |
693 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
694 | } |
695 | ||
696 | static void iommu_poll_events(struct amd_iommu *iommu) | |
697 | { | |
698 | u32 head, tail; | |
90008ee4 JR |
699 | |
700 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
701 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
702 | ||
703 | while (head != tail) { | |
a345b23b | 704 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
705 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
706 | } | |
707 | ||
708 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
709 | } |
710 | ||
eee53537 | 711 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
712 | { |
713 | struct amd_iommu_fault fault; | |
72e1dcc4 | 714 | |
399be2f5 JR |
715 | INC_STATS_COUNTER(pri_requests); |
716 | ||
72e1dcc4 JR |
717 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
718 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
719 | return; | |
720 | } | |
721 | ||
722 | fault.address = raw[1]; | |
723 | fault.pasid = PPR_PASID(raw[0]); | |
724 | fault.device_id = PPR_DEVID(raw[0]); | |
725 | fault.tag = PPR_TAG(raw[0]); | |
726 | fault.flags = PPR_FLAGS(raw[0]); | |
727 | ||
72e1dcc4 JR |
728 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
729 | } | |
730 | ||
731 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
732 | { | |
72e1dcc4 JR |
733 | u32 head, tail; |
734 | ||
735 | if (iommu->ppr_log == NULL) | |
736 | return; | |
737 | ||
72e1dcc4 JR |
738 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
739 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
740 | ||
741 | while (head != tail) { | |
eee53537 JR |
742 | volatile u64 *raw; |
743 | u64 entry[2]; | |
744 | int i; | |
745 | ||
746 | raw = (u64 *)(iommu->ppr_log + head); | |
747 | ||
748 | /* | |
749 | * Hardware bug: Interrupt may arrive before the entry is | |
750 | * written to memory. If this happens we need to wait for the | |
751 | * entry to arrive. | |
752 | */ | |
753 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
754 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
755 | break; | |
756 | udelay(1); | |
757 | } | |
72e1dcc4 | 758 | |
eee53537 JR |
759 | /* Avoid memcpy function-call overhead */ |
760 | entry[0] = raw[0]; | |
761 | entry[1] = raw[1]; | |
72e1dcc4 | 762 | |
eee53537 JR |
763 | /* |
764 | * To detect the hardware bug we need to clear the entry | |
765 | * back to zero. | |
766 | */ | |
767 | raw[0] = raw[1] = 0UL; | |
768 | ||
769 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
770 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
771 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 772 | |
eee53537 JR |
773 | /* Handle PPR entry */ |
774 | iommu_handle_ppr_entry(iommu, entry); | |
775 | ||
eee53537 JR |
776 | /* Refresh ring-buffer information */ |
777 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
778 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
779 | } | |
72e1dcc4 JR |
780 | } |
781 | ||
72fe00f0 | 782 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 783 | { |
3f398bc7 SS |
784 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
785 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 786 | |
3f398bc7 SS |
787 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
788 | /* Enable EVT and PPR interrupts again */ | |
789 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
790 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 791 | |
3f398bc7 SS |
792 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
793 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
794 | iommu_poll_events(iommu); | |
795 | } | |
90008ee4 | 796 | |
3f398bc7 SS |
797 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
798 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
799 | iommu_poll_ppr_log(iommu); | |
800 | } | |
90008ee4 | 801 | |
3f398bc7 SS |
802 | /* |
803 | * Hardware bug: ERBT1312 | |
804 | * When re-enabling interrupt (by writing 1 | |
805 | * to clear the bit), the hardware might also try to set | |
806 | * the interrupt bit in the event status register. | |
807 | * In this scenario, the bit will be set, and disable | |
808 | * subsequent interrupts. | |
809 | * | |
810 | * Workaround: The IOMMU driver should read back the | |
811 | * status register and check if the interrupt bits are cleared. | |
812 | * If not, driver will need to go through the interrupt handler | |
813 | * again and re-clear the bits | |
814 | */ | |
815 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
816 | } | |
90008ee4 | 817 | return IRQ_HANDLED; |
a80dc3e0 JR |
818 | } |
819 | ||
72fe00f0 JR |
820 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
821 | { | |
822 | return IRQ_WAKE_THREAD; | |
823 | } | |
824 | ||
431b2a20 JR |
825 | /**************************************************************************** |
826 | * | |
827 | * IOMMU command queuing functions | |
828 | * | |
829 | ****************************************************************************/ | |
830 | ||
ac0ea6e9 JR |
831 | static int wait_on_sem(volatile u64 *sem) |
832 | { | |
833 | int i = 0; | |
834 | ||
835 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
836 | udelay(1); | |
837 | i += 1; | |
838 | } | |
839 | ||
840 | if (i == LOOP_TIMEOUT) { | |
841 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
842 | return -EIO; | |
843 | } | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
849 | struct iommu_cmd *cmd, | |
850 | u32 tail) | |
a19ae1ec | 851 | { |
a19ae1ec JR |
852 | u8 *target; |
853 | ||
8a7c5ef3 | 854 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
855 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
856 | ||
857 | /* Copy command to buffer */ | |
858 | memcpy(target, cmd, sizeof(*cmd)); | |
859 | ||
860 | /* Tell the IOMMU about it */ | |
a19ae1ec | 861 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 862 | } |
a19ae1ec | 863 | |
815b33fd | 864 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 865 | { |
815b33fd JR |
866 | WARN_ON(address & 0x7ULL); |
867 | ||
ded46737 | 868 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
869 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
870 | cmd->data[1] = upper_32_bits(__pa(address)); | |
871 | cmd->data[2] = 1; | |
ded46737 JR |
872 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
873 | } | |
874 | ||
94fe79e2 JR |
875 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
876 | { | |
877 | memset(cmd, 0, sizeof(*cmd)); | |
878 | cmd->data[0] = devid; | |
879 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
880 | } | |
881 | ||
11b6402c JR |
882 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
883 | size_t size, u16 domid, int pde) | |
884 | { | |
885 | u64 pages; | |
886 | int s; | |
887 | ||
888 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
889 | s = 0; | |
890 | ||
891 | if (pages > 1) { | |
892 | /* | |
893 | * If we have to flush more than one page, flush all | |
894 | * TLB entries for this domain | |
895 | */ | |
896 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
897 | s = 1; | |
898 | } | |
899 | ||
900 | address &= PAGE_MASK; | |
901 | ||
902 | memset(cmd, 0, sizeof(*cmd)); | |
903 | cmd->data[1] |= domid; | |
904 | cmd->data[2] = lower_32_bits(address); | |
905 | cmd->data[3] = upper_32_bits(address); | |
906 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
907 | if (s) /* size bit - we flush more than one 4kb page */ | |
908 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 909 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
910 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
911 | } | |
912 | ||
cb41ed85 JR |
913 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
914 | u64 address, size_t size) | |
915 | { | |
916 | u64 pages; | |
917 | int s; | |
918 | ||
919 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
920 | s = 0; | |
921 | ||
922 | if (pages > 1) { | |
923 | /* | |
924 | * If we have to flush more than one page, flush all | |
925 | * TLB entries for this domain | |
926 | */ | |
927 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
928 | s = 1; | |
929 | } | |
930 | ||
931 | address &= PAGE_MASK; | |
932 | ||
933 | memset(cmd, 0, sizeof(*cmd)); | |
934 | cmd->data[0] = devid; | |
935 | cmd->data[0] |= (qdep & 0xff) << 24; | |
936 | cmd->data[1] = devid; | |
937 | cmd->data[2] = lower_32_bits(address); | |
938 | cmd->data[3] = upper_32_bits(address); | |
939 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
940 | if (s) | |
941 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
942 | } | |
943 | ||
22e266c7 JR |
944 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
945 | u64 address, bool size) | |
946 | { | |
947 | memset(cmd, 0, sizeof(*cmd)); | |
948 | ||
949 | address &= ~(0xfffULL); | |
950 | ||
951 | cmd->data[0] = pasid & PASID_MASK; | |
952 | cmd->data[1] = domid; | |
953 | cmd->data[2] = lower_32_bits(address); | |
954 | cmd->data[3] = upper_32_bits(address); | |
955 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
956 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
957 | if (size) | |
958 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
959 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
960 | } | |
961 | ||
962 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
963 | int qdep, u64 address, bool size) | |
964 | { | |
965 | memset(cmd, 0, sizeof(*cmd)); | |
966 | ||
967 | address &= ~(0xfffULL); | |
968 | ||
969 | cmd->data[0] = devid; | |
970 | cmd->data[0] |= (pasid & 0xff) << 16; | |
971 | cmd->data[0] |= (qdep & 0xff) << 24; | |
972 | cmd->data[1] = devid; | |
973 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
974 | cmd->data[2] = lower_32_bits(address); | |
975 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
976 | cmd->data[3] = upper_32_bits(address); | |
977 | if (size) | |
978 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
979 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
980 | } | |
981 | ||
c99afa25 JR |
982 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
983 | int status, int tag, bool gn) | |
984 | { | |
985 | memset(cmd, 0, sizeof(*cmd)); | |
986 | ||
987 | cmd->data[0] = devid; | |
988 | if (gn) { | |
989 | cmd->data[1] = pasid & PASID_MASK; | |
990 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
991 | } | |
992 | cmd->data[3] = tag & 0x1ff; | |
993 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
994 | ||
995 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
996 | } | |
997 | ||
58fc7f14 JR |
998 | static void build_inv_all(struct iommu_cmd *cmd) |
999 | { | |
1000 | memset(cmd, 0, sizeof(*cmd)); | |
1001 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1002 | } |
1003 | ||
7ef2798d JR |
1004 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1005 | { | |
1006 | memset(cmd, 0, sizeof(*cmd)); | |
1007 | cmd->data[0] = devid; | |
1008 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1009 | } | |
1010 | ||
431b2a20 | 1011 | /* |
431b2a20 | 1012 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1013 | * hardware about the new command. |
431b2a20 | 1014 | */ |
f1ca1512 JR |
1015 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
1016 | struct iommu_cmd *cmd, | |
1017 | bool sync) | |
a19ae1ec | 1018 | { |
ac0ea6e9 | 1019 | u32 left, tail, head, next_tail; |
a19ae1ec | 1020 | unsigned long flags; |
a19ae1ec | 1021 | |
549c90dc | 1022 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
1023 | |
1024 | again: | |
a19ae1ec | 1025 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 1026 | |
ac0ea6e9 JR |
1027 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
1028 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
1029 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
1030 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 1031 | |
ac0ea6e9 JR |
1032 | if (left <= 2) { |
1033 | struct iommu_cmd sync_cmd; | |
1034 | volatile u64 sem = 0; | |
1035 | int ret; | |
8d201968 | 1036 | |
ac0ea6e9 JR |
1037 | build_completion_wait(&sync_cmd, (u64)&sem); |
1038 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1039 | |
ac0ea6e9 JR |
1040 | spin_unlock_irqrestore(&iommu->lock, flags); |
1041 | ||
1042 | if ((ret = wait_on_sem(&sem)) != 0) | |
1043 | return ret; | |
1044 | ||
1045 | goto again; | |
8d201968 JR |
1046 | } |
1047 | ||
ac0ea6e9 JR |
1048 | copy_cmd_to_buffer(iommu, cmd, tail); |
1049 | ||
1050 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1051 | iommu->need_sync = sync; |
ac0ea6e9 | 1052 | |
a19ae1ec | 1053 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1054 | |
815b33fd | 1055 | return 0; |
8d201968 JR |
1056 | } |
1057 | ||
f1ca1512 JR |
1058 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1059 | { | |
1060 | return iommu_queue_command_sync(iommu, cmd, true); | |
1061 | } | |
1062 | ||
8d201968 JR |
1063 | /* |
1064 | * This function queues a completion wait command into the command | |
1065 | * buffer of an IOMMU | |
1066 | */ | |
a19ae1ec | 1067 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1068 | { |
1069 | struct iommu_cmd cmd; | |
815b33fd | 1070 | volatile u64 sem = 0; |
ac0ea6e9 | 1071 | int ret; |
8d201968 | 1072 | |
09ee17eb | 1073 | if (!iommu->need_sync) |
815b33fd | 1074 | return 0; |
09ee17eb | 1075 | |
815b33fd | 1076 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1077 | |
f1ca1512 | 1078 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1079 | if (ret) |
815b33fd | 1080 | return ret; |
8d201968 | 1081 | |
ac0ea6e9 | 1082 | return wait_on_sem(&sem); |
8d201968 JR |
1083 | } |
1084 | ||
d8c13085 | 1085 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1086 | { |
d8c13085 | 1087 | struct iommu_cmd cmd; |
a19ae1ec | 1088 | |
d8c13085 | 1089 | build_inv_dte(&cmd, devid); |
7e4f88da | 1090 | |
d8c13085 JR |
1091 | return iommu_queue_command(iommu, &cmd); |
1092 | } | |
09ee17eb | 1093 | |
7d0c5cc5 JR |
1094 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1095 | { | |
1096 | u32 devid; | |
09ee17eb | 1097 | |
7d0c5cc5 JR |
1098 | for (devid = 0; devid <= 0xffff; ++devid) |
1099 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1100 | |
7d0c5cc5 JR |
1101 | iommu_completion_wait(iommu); |
1102 | } | |
84df8175 | 1103 | |
7d0c5cc5 JR |
1104 | /* |
1105 | * This function uses heavy locking and may disable irqs for some time. But | |
1106 | * this is no issue because it is only called during resume. | |
1107 | */ | |
1108 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1109 | { | |
1110 | u32 dom_id; | |
a19ae1ec | 1111 | |
7d0c5cc5 JR |
1112 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1113 | struct iommu_cmd cmd; | |
1114 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1115 | dom_id, 1); | |
1116 | iommu_queue_command(iommu, &cmd); | |
1117 | } | |
8eed9833 | 1118 | |
7d0c5cc5 | 1119 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1120 | } |
1121 | ||
58fc7f14 | 1122 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1123 | { |
58fc7f14 | 1124 | struct iommu_cmd cmd; |
0518a3a4 | 1125 | |
58fc7f14 | 1126 | build_inv_all(&cmd); |
0518a3a4 | 1127 | |
58fc7f14 JR |
1128 | iommu_queue_command(iommu, &cmd); |
1129 | iommu_completion_wait(iommu); | |
1130 | } | |
1131 | ||
7ef2798d JR |
1132 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1133 | { | |
1134 | struct iommu_cmd cmd; | |
1135 | ||
1136 | build_inv_irt(&cmd, devid); | |
1137 | ||
1138 | iommu_queue_command(iommu, &cmd); | |
1139 | } | |
1140 | ||
1141 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1142 | { | |
1143 | u32 devid; | |
1144 | ||
1145 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1146 | iommu_flush_irt(iommu, devid); | |
1147 | ||
1148 | iommu_completion_wait(iommu); | |
1149 | } | |
1150 | ||
7d0c5cc5 JR |
1151 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1152 | { | |
58fc7f14 JR |
1153 | if (iommu_feature(iommu, FEATURE_IA)) { |
1154 | iommu_flush_all(iommu); | |
1155 | } else { | |
1156 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1157 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1158 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1159 | } |
1160 | } | |
1161 | ||
431b2a20 | 1162 | /* |
cb41ed85 | 1163 | * Command send function for flushing on-device TLB |
431b2a20 | 1164 | */ |
6c542047 JR |
1165 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1166 | u64 address, size_t size) | |
3fa43655 JR |
1167 | { |
1168 | struct amd_iommu *iommu; | |
b00d3bcf | 1169 | struct iommu_cmd cmd; |
cb41ed85 | 1170 | int qdep; |
3fa43655 | 1171 | |
ea61cddb JR |
1172 | qdep = dev_data->ats.qdep; |
1173 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1174 | |
ea61cddb | 1175 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1176 | |
1177 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1178 | } |
1179 | ||
431b2a20 | 1180 | /* |
431b2a20 | 1181 | * Command send function for invalidating a device table entry |
431b2a20 | 1182 | */ |
6c542047 | 1183 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1184 | { |
3fa43655 | 1185 | struct amd_iommu *iommu; |
ee2fa743 | 1186 | int ret; |
a19ae1ec | 1187 | |
6c542047 | 1188 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1189 | |
f62dda66 | 1190 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1191 | if (ret) |
1192 | return ret; | |
1193 | ||
ea61cddb | 1194 | if (dev_data->ats.enabled) |
6c542047 | 1195 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1196 | |
ee2fa743 | 1197 | return ret; |
a19ae1ec JR |
1198 | } |
1199 | ||
431b2a20 JR |
1200 | /* |
1201 | * TLB invalidation function which is called from the mapping functions. | |
1202 | * It invalidates a single PTE if the range to flush is within a single | |
1203 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1204 | */ | |
17b124bf JR |
1205 | static void __domain_flush_pages(struct protection_domain *domain, |
1206 | u64 address, size_t size, int pde) | |
a19ae1ec | 1207 | { |
cb41ed85 | 1208 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1209 | struct iommu_cmd cmd; |
1210 | int ret = 0, i; | |
a19ae1ec | 1211 | |
11b6402c | 1212 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1213 | |
6de8ad9b JR |
1214 | for (i = 0; i < amd_iommus_present; ++i) { |
1215 | if (!domain->dev_iommu[i]) | |
1216 | continue; | |
1217 | ||
1218 | /* | |
1219 | * Devices of this domain are behind this IOMMU | |
1220 | * We need a TLB flush | |
1221 | */ | |
11b6402c | 1222 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1223 | } |
1224 | ||
cb41ed85 | 1225 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1226 | |
ea61cddb | 1227 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1228 | continue; |
1229 | ||
6c542047 | 1230 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1231 | } |
1232 | ||
11b6402c | 1233 | WARN_ON(ret); |
6de8ad9b JR |
1234 | } |
1235 | ||
17b124bf JR |
1236 | static void domain_flush_pages(struct protection_domain *domain, |
1237 | u64 address, size_t size) | |
6de8ad9b | 1238 | { |
17b124bf | 1239 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1240 | } |
b6c02715 | 1241 | |
1c655773 | 1242 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1243 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1244 | { |
17b124bf | 1245 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1246 | } |
1247 | ||
42a49f96 | 1248 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1249 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1250 | { |
17b124bf | 1251 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1252 | } |
1253 | ||
17b124bf | 1254 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1255 | { |
17b124bf | 1256 | int i; |
18811f55 | 1257 | |
17b124bf JR |
1258 | for (i = 0; i < amd_iommus_present; ++i) { |
1259 | if (!domain->dev_iommu[i]) | |
1260 | continue; | |
bfd1be18 | 1261 | |
17b124bf JR |
1262 | /* |
1263 | * Devices of this domain are behind this IOMMU | |
1264 | * We need to wait for completion of all commands. | |
1265 | */ | |
1266 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1267 | } |
e394d72a JR |
1268 | } |
1269 | ||
b00d3bcf | 1270 | |
09b42804 | 1271 | /* |
b00d3bcf | 1272 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1273 | */ |
17b124bf | 1274 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1275 | { |
b00d3bcf | 1276 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1277 | |
b00d3bcf | 1278 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1279 | device_flush_dte(dev_data); |
a345b23b JR |
1280 | } |
1281 | ||
431b2a20 JR |
1282 | /**************************************************************************** |
1283 | * | |
1284 | * The functions below are used the create the page table mappings for | |
1285 | * unity mapped regions. | |
1286 | * | |
1287 | ****************************************************************************/ | |
1288 | ||
308973d3 JR |
1289 | /* |
1290 | * This function is used to add another level to an IO page table. Adding | |
1291 | * another level increases the size of the address space by 9 bits to a size up | |
1292 | * to 64 bits. | |
1293 | */ | |
1294 | static bool increase_address_space(struct protection_domain *domain, | |
1295 | gfp_t gfp) | |
1296 | { | |
1297 | u64 *pte; | |
1298 | ||
1299 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1300 | /* address space already 64 bit large */ | |
1301 | return false; | |
1302 | ||
1303 | pte = (void *)get_zeroed_page(gfp); | |
1304 | if (!pte) | |
1305 | return false; | |
1306 | ||
1307 | *pte = PM_LEVEL_PDE(domain->mode, | |
1308 | virt_to_phys(domain->pt_root)); | |
1309 | domain->pt_root = pte; | |
1310 | domain->mode += 1; | |
1311 | domain->updated = true; | |
1312 | ||
1313 | return true; | |
1314 | } | |
1315 | ||
1316 | static u64 *alloc_pte(struct protection_domain *domain, | |
1317 | unsigned long address, | |
cbb9d729 | 1318 | unsigned long page_size, |
308973d3 JR |
1319 | u64 **pte_page, |
1320 | gfp_t gfp) | |
1321 | { | |
cbb9d729 | 1322 | int level, end_lvl; |
308973d3 | 1323 | u64 *pte, *page; |
cbb9d729 JR |
1324 | |
1325 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1326 | |
1327 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1328 | increase_address_space(domain, gfp); | |
1329 | ||
cbb9d729 JR |
1330 | level = domain->mode - 1; |
1331 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1332 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1333 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1334 | |
1335 | while (level > end_lvl) { | |
1336 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1337 | page = (u64 *)get_zeroed_page(gfp); | |
1338 | if (!page) | |
1339 | return NULL; | |
1340 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1341 | } | |
1342 | ||
cbb9d729 JR |
1343 | /* No level skipping support yet */ |
1344 | if (PM_PTE_LEVEL(*pte) != level) | |
1345 | return NULL; | |
1346 | ||
308973d3 JR |
1347 | level -= 1; |
1348 | ||
1349 | pte = IOMMU_PTE_PAGE(*pte); | |
1350 | ||
1351 | if (pte_page && level == end_lvl) | |
1352 | *pte_page = pte; | |
1353 | ||
1354 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1355 | } | |
1356 | ||
1357 | return pte; | |
1358 | } | |
1359 | ||
1360 | /* | |
1361 | * This function checks if there is a PTE for a given dma address. If | |
1362 | * there is one, it returns the pointer to it. | |
1363 | */ | |
24cd7723 | 1364 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1365 | { |
1366 | int level; | |
1367 | u64 *pte; | |
1368 | ||
24cd7723 JR |
1369 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1370 | return NULL; | |
1371 | ||
1372 | level = domain->mode - 1; | |
1373 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1374 | |
24cd7723 JR |
1375 | while (level > 0) { |
1376 | ||
1377 | /* Not Present */ | |
308973d3 JR |
1378 | if (!IOMMU_PTE_PRESENT(*pte)) |
1379 | return NULL; | |
1380 | ||
24cd7723 JR |
1381 | /* Large PTE */ |
1382 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1383 | unsigned long pte_mask, __pte; | |
1384 | ||
1385 | /* | |
1386 | * If we have a series of large PTEs, make | |
1387 | * sure to return a pointer to the first one. | |
1388 | */ | |
1389 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1390 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1391 | __pte = ((unsigned long)pte) & pte_mask; | |
1392 | ||
1393 | return (u64 *)__pte; | |
1394 | } | |
1395 | ||
1396 | /* No level skipping support yet */ | |
1397 | if (PM_PTE_LEVEL(*pte) != level) | |
1398 | return NULL; | |
1399 | ||
308973d3 JR |
1400 | level -= 1; |
1401 | ||
24cd7723 | 1402 | /* Walk to the next level */ |
308973d3 JR |
1403 | pte = IOMMU_PTE_PAGE(*pte); |
1404 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1405 | } |
1406 | ||
1407 | return pte; | |
1408 | } | |
1409 | ||
431b2a20 JR |
1410 | /* |
1411 | * Generic mapping functions. It maps a physical address into a DMA | |
1412 | * address space. It allocates the page table pages if necessary. | |
1413 | * In the future it can be extended to a generic mapping function | |
1414 | * supporting all features of AMD IOMMU page tables like level skipping | |
1415 | * and full 64 bit address spaces. | |
1416 | */ | |
38e817fe JR |
1417 | static int iommu_map_page(struct protection_domain *dom, |
1418 | unsigned long bus_addr, | |
1419 | unsigned long phys_addr, | |
abdc5eb3 | 1420 | int prot, |
cbb9d729 | 1421 | unsigned long page_size) |
bd0e5211 | 1422 | { |
8bda3092 | 1423 | u64 __pte, *pte; |
cbb9d729 | 1424 | int i, count; |
abdc5eb3 | 1425 | |
bad1cac2 | 1426 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1427 | return -EINVAL; |
1428 | ||
cbb9d729 JR |
1429 | bus_addr = PAGE_ALIGN(bus_addr); |
1430 | phys_addr = PAGE_ALIGN(phys_addr); | |
1431 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1432 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1433 | ||
1434 | for (i = 0; i < count; ++i) | |
1435 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1436 | return -EBUSY; | |
bd0e5211 | 1437 | |
cbb9d729 JR |
1438 | if (page_size > PAGE_SIZE) { |
1439 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1440 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1441 | } else | |
1442 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1443 | |
bd0e5211 JR |
1444 | if (prot & IOMMU_PROT_IR) |
1445 | __pte |= IOMMU_PTE_IR; | |
1446 | if (prot & IOMMU_PROT_IW) | |
1447 | __pte |= IOMMU_PTE_IW; | |
1448 | ||
cbb9d729 JR |
1449 | for (i = 0; i < count; ++i) |
1450 | pte[i] = __pte; | |
bd0e5211 | 1451 | |
04bfdd84 JR |
1452 | update_domain(dom); |
1453 | ||
bd0e5211 JR |
1454 | return 0; |
1455 | } | |
1456 | ||
24cd7723 JR |
1457 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1458 | unsigned long bus_addr, | |
1459 | unsigned long page_size) | |
eb74ff6c | 1460 | { |
24cd7723 JR |
1461 | unsigned long long unmap_size, unmapped; |
1462 | u64 *pte; | |
1463 | ||
1464 | BUG_ON(!is_power_of_2(page_size)); | |
1465 | ||
1466 | unmapped = 0; | |
eb74ff6c | 1467 | |
24cd7723 JR |
1468 | while (unmapped < page_size) { |
1469 | ||
1470 | pte = fetch_pte(dom, bus_addr); | |
1471 | ||
1472 | if (!pte) { | |
1473 | /* | |
1474 | * No PTE for this address | |
1475 | * move forward in 4kb steps | |
1476 | */ | |
1477 | unmap_size = PAGE_SIZE; | |
1478 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1479 | /* 4kb PTE found for this address */ | |
1480 | unmap_size = PAGE_SIZE; | |
1481 | *pte = 0ULL; | |
1482 | } else { | |
1483 | int count, i; | |
1484 | ||
1485 | /* Large PTE found which maps this address */ | |
1486 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1487 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1488 | for (i = 0; i < count; i++) | |
1489 | pte[i] = 0ULL; | |
1490 | } | |
1491 | ||
1492 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1493 | unmapped += unmap_size; | |
1494 | } | |
1495 | ||
1496 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1497 | |
24cd7723 | 1498 | return unmapped; |
eb74ff6c | 1499 | } |
eb74ff6c | 1500 | |
431b2a20 JR |
1501 | /* |
1502 | * This function checks if a specific unity mapping entry is needed for | |
1503 | * this specific IOMMU. | |
1504 | */ | |
bd0e5211 JR |
1505 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1506 | struct unity_map_entry *entry) | |
1507 | { | |
1508 | u16 bdf, i; | |
1509 | ||
1510 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1511 | bdf = amd_iommu_alias_table[i]; | |
1512 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1513 | return 1; | |
1514 | } | |
1515 | ||
1516 | return 0; | |
1517 | } | |
1518 | ||
431b2a20 JR |
1519 | /* |
1520 | * This function actually applies the mapping to the page table of the | |
1521 | * dma_ops domain. | |
1522 | */ | |
bd0e5211 JR |
1523 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1524 | struct unity_map_entry *e) | |
1525 | { | |
1526 | u64 addr; | |
1527 | int ret; | |
1528 | ||
1529 | for (addr = e->address_start; addr < e->address_end; | |
1530 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1531 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1532 | PAGE_SIZE); |
bd0e5211 JR |
1533 | if (ret) |
1534 | return ret; | |
1535 | /* | |
1536 | * if unity mapping is in aperture range mark the page | |
1537 | * as allocated in the aperture | |
1538 | */ | |
1539 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1540 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1541 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1542 | } |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
171e7b37 JR |
1547 | /* |
1548 | * Init the unity mappings for a specific IOMMU in the system | |
1549 | * | |
1550 | * Basically iterates over all unity mapping entries and applies them to | |
1551 | * the default domain DMA of that IOMMU if necessary. | |
1552 | */ | |
1553 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1554 | { | |
1555 | struct unity_map_entry *entry; | |
1556 | int ret; | |
1557 | ||
1558 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1559 | if (!iommu_for_unity_map(iommu, entry)) | |
1560 | continue; | |
1561 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1562 | if (ret) | |
1563 | return ret; | |
1564 | } | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
431b2a20 JR |
1569 | /* |
1570 | * Inits the unity mappings required for a specific device | |
1571 | */ | |
bd0e5211 JR |
1572 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1573 | u16 devid) | |
1574 | { | |
1575 | struct unity_map_entry *e; | |
1576 | int ret; | |
1577 | ||
1578 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1579 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1580 | continue; | |
1581 | ret = dma_ops_unity_map(dma_dom, e); | |
1582 | if (ret) | |
1583 | return ret; | |
1584 | } | |
1585 | ||
1586 | return 0; | |
1587 | } | |
1588 | ||
431b2a20 JR |
1589 | /**************************************************************************** |
1590 | * | |
1591 | * The next functions belong to the address allocator for the dma_ops | |
1592 | * interface functions. They work like the allocators in the other IOMMU | |
1593 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1594 | * the aperture. Maybe it could be enhanced in the future to a more | |
1595 | * efficient allocator. | |
1596 | * | |
1597 | ****************************************************************************/ | |
d3086444 | 1598 | |
431b2a20 | 1599 | /* |
384de729 | 1600 | * The address allocator core functions. |
431b2a20 JR |
1601 | * |
1602 | * called with domain->lock held | |
1603 | */ | |
384de729 | 1604 | |
171e7b37 JR |
1605 | /* |
1606 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1607 | * ranges. | |
1608 | */ | |
1609 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1610 | unsigned long start_page, | |
1611 | unsigned int pages) | |
1612 | { | |
1613 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1614 | ||
1615 | if (start_page + pages > last_page) | |
1616 | pages = last_page - start_page; | |
1617 | ||
1618 | for (i = start_page; i < start_page + pages; ++i) { | |
1619 | int index = i / APERTURE_RANGE_PAGES; | |
1620 | int page = i % APERTURE_RANGE_PAGES; | |
1621 | __set_bit(page, dom->aperture[index]->bitmap); | |
1622 | } | |
1623 | } | |
1624 | ||
9cabe89b JR |
1625 | /* |
1626 | * This function is used to add a new aperture range to an existing | |
1627 | * aperture in case of dma_ops domain allocation or address allocation | |
1628 | * failure. | |
1629 | */ | |
576175c2 | 1630 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1631 | bool populate, gfp_t gfp) |
1632 | { | |
1633 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1634 | struct amd_iommu *iommu; |
17f5b569 | 1635 | unsigned long i, old_size; |
9cabe89b | 1636 | |
f5e9705c JR |
1637 | #ifdef CONFIG_IOMMU_STRESS |
1638 | populate = false; | |
1639 | #endif | |
1640 | ||
9cabe89b JR |
1641 | if (index >= APERTURE_MAX_RANGES) |
1642 | return -ENOMEM; | |
1643 | ||
1644 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1645 | if (!dma_dom->aperture[index]) | |
1646 | return -ENOMEM; | |
1647 | ||
1648 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1649 | if (!dma_dom->aperture[index]->bitmap) | |
1650 | goto out_free; | |
1651 | ||
1652 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1653 | ||
1654 | if (populate) { | |
1655 | unsigned long address = dma_dom->aperture_size; | |
1656 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1657 | u64 *pte, *pte_page; | |
1658 | ||
1659 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1660 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1661 | &pte_page, gfp); |
1662 | if (!pte) | |
1663 | goto out_free; | |
1664 | ||
1665 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1666 | ||
1667 | address += APERTURE_RANGE_SIZE / 64; | |
1668 | } | |
1669 | } | |
1670 | ||
17f5b569 | 1671 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1672 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1673 | ||
17f5b569 JR |
1674 | /* Reserve address range used for MSI messages */ |
1675 | if (old_size < MSI_ADDR_BASE_LO && | |
1676 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1677 | unsigned long spage; | |
1678 | int pages; | |
1679 | ||
1680 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1681 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1682 | ||
1683 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1684 | } | |
1685 | ||
b595076a | 1686 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1687 | for_each_iommu(iommu) { |
1688 | if (iommu->exclusion_start && | |
1689 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1690 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1691 | unsigned long startpage; | |
1692 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1693 | iommu->exclusion_length, | |
1694 | PAGE_SIZE); | |
1695 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1696 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1697 | } | |
00cd122a JR |
1698 | } |
1699 | ||
1700 | /* | |
1701 | * Check for areas already mapped as present in the new aperture | |
1702 | * range and mark those pages as reserved in the allocator. Such | |
1703 | * mappings may already exist as a result of requested unity | |
1704 | * mappings for devices. | |
1705 | */ | |
1706 | for (i = dma_dom->aperture[index]->offset; | |
1707 | i < dma_dom->aperture_size; | |
1708 | i += PAGE_SIZE) { | |
24cd7723 | 1709 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1710 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1711 | continue; | |
1712 | ||
fcd0861d | 1713 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1714 | } |
1715 | ||
04bfdd84 JR |
1716 | update_domain(&dma_dom->domain); |
1717 | ||
9cabe89b JR |
1718 | return 0; |
1719 | ||
1720 | out_free: | |
04bfdd84 JR |
1721 | update_domain(&dma_dom->domain); |
1722 | ||
9cabe89b JR |
1723 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1724 | ||
1725 | kfree(dma_dom->aperture[index]); | |
1726 | dma_dom->aperture[index] = NULL; | |
1727 | ||
1728 | return -ENOMEM; | |
1729 | } | |
1730 | ||
384de729 JR |
1731 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1732 | struct dma_ops_domain *dom, | |
1733 | unsigned int pages, | |
1734 | unsigned long align_mask, | |
1735 | u64 dma_mask, | |
1736 | unsigned long start) | |
1737 | { | |
803b8cb4 | 1738 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1739 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1740 | int i = start >> APERTURE_RANGE_SHIFT; | |
1741 | unsigned long boundary_size; | |
1742 | unsigned long address = -1; | |
1743 | unsigned long limit; | |
1744 | ||
803b8cb4 JR |
1745 | next_bit >>= PAGE_SHIFT; |
1746 | ||
384de729 JR |
1747 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1748 | PAGE_SIZE) >> PAGE_SHIFT; | |
1749 | ||
1750 | for (;i < max_index; ++i) { | |
1751 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1752 | ||
1753 | if (dom->aperture[i]->offset >= dma_mask) | |
1754 | break; | |
1755 | ||
1756 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1757 | dma_mask >> PAGE_SHIFT); | |
1758 | ||
1759 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1760 | limit, next_bit, pages, 0, | |
1761 | boundary_size, align_mask); | |
1762 | if (address != -1) { | |
1763 | address = dom->aperture[i]->offset + | |
1764 | (address << PAGE_SHIFT); | |
803b8cb4 | 1765 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1766 | break; |
1767 | } | |
1768 | ||
1769 | next_bit = 0; | |
1770 | } | |
1771 | ||
1772 | return address; | |
1773 | } | |
1774 | ||
d3086444 JR |
1775 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1776 | struct dma_ops_domain *dom, | |
6d4f343f | 1777 | unsigned int pages, |
832a90c3 JR |
1778 | unsigned long align_mask, |
1779 | u64 dma_mask) | |
d3086444 | 1780 | { |
d3086444 | 1781 | unsigned long address; |
d3086444 | 1782 | |
fe16f088 JR |
1783 | #ifdef CONFIG_IOMMU_STRESS |
1784 | dom->next_address = 0; | |
1785 | dom->need_flush = true; | |
1786 | #endif | |
d3086444 | 1787 | |
384de729 | 1788 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1789 | dma_mask, dom->next_address); |
d3086444 | 1790 | |
1c655773 | 1791 | if (address == -1) { |
803b8cb4 | 1792 | dom->next_address = 0; |
384de729 JR |
1793 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1794 | dma_mask, 0); | |
1c655773 JR |
1795 | dom->need_flush = true; |
1796 | } | |
d3086444 | 1797 | |
384de729 | 1798 | if (unlikely(address == -1)) |
8fd524b3 | 1799 | address = DMA_ERROR_CODE; |
d3086444 JR |
1800 | |
1801 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1802 | ||
1803 | return address; | |
1804 | } | |
1805 | ||
431b2a20 JR |
1806 | /* |
1807 | * The address free function. | |
1808 | * | |
1809 | * called with domain->lock held | |
1810 | */ | |
d3086444 JR |
1811 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1812 | unsigned long address, | |
1813 | unsigned int pages) | |
1814 | { | |
384de729 JR |
1815 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1816 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1817 | |
384de729 JR |
1818 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1819 | ||
47bccd6b JR |
1820 | #ifdef CONFIG_IOMMU_STRESS |
1821 | if (i < 4) | |
1822 | return; | |
1823 | #endif | |
80be308d | 1824 | |
803b8cb4 | 1825 | if (address >= dom->next_address) |
80be308d | 1826 | dom->need_flush = true; |
384de729 JR |
1827 | |
1828 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1829 | |
a66022c4 | 1830 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1831 | |
d3086444 JR |
1832 | } |
1833 | ||
431b2a20 JR |
1834 | /**************************************************************************** |
1835 | * | |
1836 | * The next functions belong to the domain allocation. A domain is | |
1837 | * allocated for every IOMMU as the default domain. If device isolation | |
1838 | * is enabled, every device get its own domain. The most important thing | |
1839 | * about domains is the page table mapping the DMA address space they | |
1840 | * contain. | |
1841 | * | |
1842 | ****************************************************************************/ | |
1843 | ||
aeb26f55 JR |
1844 | /* |
1845 | * This function adds a protection domain to the global protection domain list | |
1846 | */ | |
1847 | static void add_domain_to_list(struct protection_domain *domain) | |
1848 | { | |
1849 | unsigned long flags; | |
1850 | ||
1851 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1852 | list_add(&domain->list, &amd_iommu_pd_list); | |
1853 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1854 | } | |
1855 | ||
1856 | /* | |
1857 | * This function removes a protection domain to the global | |
1858 | * protection domain list | |
1859 | */ | |
1860 | static void del_domain_from_list(struct protection_domain *domain) | |
1861 | { | |
1862 | unsigned long flags; | |
1863 | ||
1864 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1865 | list_del(&domain->list); | |
1866 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1867 | } | |
1868 | ||
ec487d1a JR |
1869 | static u16 domain_id_alloc(void) |
1870 | { | |
1871 | unsigned long flags; | |
1872 | int id; | |
1873 | ||
1874 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1875 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1876 | BUG_ON(id == 0); | |
1877 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1878 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1879 | else | |
1880 | id = 0; | |
1881 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1882 | ||
1883 | return id; | |
1884 | } | |
1885 | ||
a2acfb75 JR |
1886 | static void domain_id_free(int id) |
1887 | { | |
1888 | unsigned long flags; | |
1889 | ||
1890 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1891 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1892 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1893 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1894 | } | |
a2acfb75 | 1895 | |
86db2e5d | 1896 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1897 | { |
1898 | int i, j; | |
1899 | u64 *p1, *p2, *p3; | |
1900 | ||
86db2e5d | 1901 | p1 = domain->pt_root; |
ec487d1a JR |
1902 | |
1903 | if (!p1) | |
1904 | return; | |
1905 | ||
1906 | for (i = 0; i < 512; ++i) { | |
1907 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1908 | continue; | |
1909 | ||
1910 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1911 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1912 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1913 | continue; | |
1914 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1915 | free_page((unsigned long)p3); | |
1916 | } | |
1917 | ||
1918 | free_page((unsigned long)p2); | |
1919 | } | |
1920 | ||
1921 | free_page((unsigned long)p1); | |
86db2e5d JR |
1922 | |
1923 | domain->pt_root = NULL; | |
ec487d1a JR |
1924 | } |
1925 | ||
b16137b1 JR |
1926 | static void free_gcr3_tbl_level1(u64 *tbl) |
1927 | { | |
1928 | u64 *ptr; | |
1929 | int i; | |
1930 | ||
1931 | for (i = 0; i < 512; ++i) { | |
1932 | if (!(tbl[i] & GCR3_VALID)) | |
1933 | continue; | |
1934 | ||
1935 | ptr = __va(tbl[i] & PAGE_MASK); | |
1936 | ||
1937 | free_page((unsigned long)ptr); | |
1938 | } | |
1939 | } | |
1940 | ||
1941 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1942 | { | |
1943 | u64 *ptr; | |
1944 | int i; | |
1945 | ||
1946 | for (i = 0; i < 512; ++i) { | |
1947 | if (!(tbl[i] & GCR3_VALID)) | |
1948 | continue; | |
1949 | ||
1950 | ptr = __va(tbl[i] & PAGE_MASK); | |
1951 | ||
1952 | free_gcr3_tbl_level1(ptr); | |
1953 | } | |
1954 | } | |
1955 | ||
52815b75 JR |
1956 | static void free_gcr3_table(struct protection_domain *domain) |
1957 | { | |
b16137b1 JR |
1958 | if (domain->glx == 2) |
1959 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1960 | else if (domain->glx == 1) | |
1961 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1962 | else if (domain->glx != 0) | |
1963 | BUG(); | |
1964 | ||
52815b75 JR |
1965 | free_page((unsigned long)domain->gcr3_tbl); |
1966 | } | |
1967 | ||
431b2a20 JR |
1968 | /* |
1969 | * Free a domain, only used if something went wrong in the | |
1970 | * allocation path and we need to free an already allocated page table | |
1971 | */ | |
ec487d1a JR |
1972 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1973 | { | |
384de729 JR |
1974 | int i; |
1975 | ||
ec487d1a JR |
1976 | if (!dom) |
1977 | return; | |
1978 | ||
aeb26f55 JR |
1979 | del_domain_from_list(&dom->domain); |
1980 | ||
86db2e5d | 1981 | free_pagetable(&dom->domain); |
ec487d1a | 1982 | |
384de729 JR |
1983 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1984 | if (!dom->aperture[i]) | |
1985 | continue; | |
1986 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1987 | kfree(dom->aperture[i]); | |
1988 | } | |
ec487d1a JR |
1989 | |
1990 | kfree(dom); | |
1991 | } | |
1992 | ||
431b2a20 JR |
1993 | /* |
1994 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1995 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1996 | * structures required for the dma_ops interface |
1997 | */ | |
87a64d52 | 1998 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1999 | { |
2000 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
2001 | |
2002 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
2003 | if (!dma_dom) | |
2004 | return NULL; | |
2005 | ||
2006 | spin_lock_init(&dma_dom->domain.lock); | |
2007 | ||
2008 | dma_dom->domain.id = domain_id_alloc(); | |
2009 | if (dma_dom->domain.id == 0) | |
2010 | goto free_dma_dom; | |
7c392cbe | 2011 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 2012 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2013 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2014 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2015 | dma_dom->domain.priv = dma_dom; |
2016 | if (!dma_dom->domain.pt_root) | |
2017 | goto free_dma_dom; | |
ec487d1a | 2018 | |
1c655773 | 2019 | dma_dom->need_flush = false; |
bd60b735 | 2020 | dma_dom->target_dev = 0xffff; |
1c655773 | 2021 | |
aeb26f55 JR |
2022 | add_domain_to_list(&dma_dom->domain); |
2023 | ||
576175c2 | 2024 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2025 | goto free_dma_dom; |
ec487d1a | 2026 | |
431b2a20 | 2027 | /* |
ec487d1a JR |
2028 | * mark the first page as allocated so we never return 0 as |
2029 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2030 | */ |
384de729 | 2031 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 2032 | dma_dom->next_address = 0; |
ec487d1a | 2033 | |
ec487d1a JR |
2034 | |
2035 | return dma_dom; | |
2036 | ||
2037 | free_dma_dom: | |
2038 | dma_ops_domain_free(dma_dom); | |
2039 | ||
2040 | return NULL; | |
2041 | } | |
2042 | ||
5b28df6f JR |
2043 | /* |
2044 | * little helper function to check whether a given protection domain is a | |
2045 | * dma_ops domain | |
2046 | */ | |
2047 | static bool dma_ops_domain(struct protection_domain *domain) | |
2048 | { | |
2049 | return domain->flags & PD_DMA_OPS_MASK; | |
2050 | } | |
2051 | ||
fd7b5535 | 2052 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2053 | { |
132bd68f | 2054 | u64 pte_root = 0; |
ee6c2868 | 2055 | u64 flags = 0; |
863c74eb | 2056 | |
132bd68f JR |
2057 | if (domain->mode != PAGE_MODE_NONE) |
2058 | pte_root = virt_to_phys(domain->pt_root); | |
2059 | ||
38ddf41b JR |
2060 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2061 | << DEV_ENTRY_MODE_SHIFT; | |
2062 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2063 | |
ee6c2868 JR |
2064 | flags = amd_iommu_dev_table[devid].data[1]; |
2065 | ||
fd7b5535 JR |
2066 | if (ats) |
2067 | flags |= DTE_FLAG_IOTLB; | |
2068 | ||
52815b75 JR |
2069 | if (domain->flags & PD_IOMMUV2_MASK) { |
2070 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2071 | u64 glx = domain->glx; | |
2072 | u64 tmp; | |
2073 | ||
2074 | pte_root |= DTE_FLAG_GV; | |
2075 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2076 | ||
2077 | /* First mask out possible old values for GCR3 table */ | |
2078 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2079 | flags &= ~tmp; | |
2080 | ||
2081 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2082 | flags &= ~tmp; | |
2083 | ||
2084 | /* Encode GCR3 table into DTE */ | |
2085 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2086 | pte_root |= tmp; | |
2087 | ||
2088 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2089 | flags |= tmp; | |
2090 | ||
2091 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2092 | flags |= tmp; | |
2093 | } | |
2094 | ||
ee6c2868 JR |
2095 | flags &= ~(0xffffUL); |
2096 | flags |= domain->id; | |
2097 | ||
2098 | amd_iommu_dev_table[devid].data[1] = flags; | |
2099 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2100 | } |
2101 | ||
2102 | static void clear_dte_entry(u16 devid) | |
2103 | { | |
15898bbc JR |
2104 | /* remove entry from the device table seen by the hardware */ |
2105 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2106 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2107 | |
2108 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2109 | } |
2110 | ||
ec9e79ef JR |
2111 | static void do_attach(struct iommu_dev_data *dev_data, |
2112 | struct protection_domain *domain) | |
7f760ddd | 2113 | { |
7f760ddd | 2114 | struct amd_iommu *iommu; |
ec9e79ef | 2115 | bool ats; |
fd7b5535 | 2116 | |
ec9e79ef JR |
2117 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2118 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2119 | |
2120 | /* Update data structures */ | |
2121 | dev_data->domain = domain; | |
2122 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2123 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2124 | |
2125 | /* Do reference counting */ | |
2126 | domain->dev_iommu[iommu->index] += 1; | |
2127 | domain->dev_cnt += 1; | |
2128 | ||
2129 | /* Flush the DTE entry */ | |
6c542047 | 2130 | device_flush_dte(dev_data); |
7f760ddd JR |
2131 | } |
2132 | ||
ec9e79ef | 2133 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2134 | { |
7f760ddd | 2135 | struct amd_iommu *iommu; |
7f760ddd | 2136 | |
ec9e79ef | 2137 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2138 | |
2139 | /* decrease reference counters */ | |
7f760ddd JR |
2140 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2141 | dev_data->domain->dev_cnt -= 1; | |
2142 | ||
2143 | /* Update data structures */ | |
2144 | dev_data->domain = NULL; | |
2145 | list_del(&dev_data->list); | |
f62dda66 | 2146 | clear_dte_entry(dev_data->devid); |
15898bbc | 2147 | |
7f760ddd | 2148 | /* Flush the DTE entry */ |
6c542047 | 2149 | device_flush_dte(dev_data); |
2b681faf JR |
2150 | } |
2151 | ||
2152 | /* | |
2153 | * If a device is not yet associated with a domain, this function does | |
2154 | * assigns it visible for the hardware | |
2155 | */ | |
ec9e79ef | 2156 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2157 | struct protection_domain *domain) |
2b681faf | 2158 | { |
84fe6c19 | 2159 | int ret; |
657cbb6b | 2160 | |
2b681faf JR |
2161 | /* lock domain */ |
2162 | spin_lock(&domain->lock); | |
2163 | ||
71f77580 JR |
2164 | if (dev_data->alias_data != NULL) { |
2165 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2166 | |
2b02b091 JR |
2167 | /* Some sanity checks */ |
2168 | ret = -EBUSY; | |
2169 | if (alias_data->domain != NULL && | |
2170 | alias_data->domain != domain) | |
2171 | goto out_unlock; | |
eba6ac60 | 2172 | |
2b02b091 JR |
2173 | if (dev_data->domain != NULL && |
2174 | dev_data->domain != domain) | |
2175 | goto out_unlock; | |
15898bbc | 2176 | |
2b02b091 | 2177 | /* Do real assignment */ |
7f760ddd | 2178 | if (alias_data->domain == NULL) |
ec9e79ef | 2179 | do_attach(alias_data, domain); |
24100055 JR |
2180 | |
2181 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2182 | } |
15898bbc | 2183 | |
7f760ddd | 2184 | if (dev_data->domain == NULL) |
ec9e79ef | 2185 | do_attach(dev_data, domain); |
eba6ac60 | 2186 | |
24100055 JR |
2187 | atomic_inc(&dev_data->bind); |
2188 | ||
84fe6c19 JL |
2189 | ret = 0; |
2190 | ||
2191 | out_unlock: | |
2192 | ||
eba6ac60 JR |
2193 | /* ready */ |
2194 | spin_unlock(&domain->lock); | |
15898bbc | 2195 | |
84fe6c19 | 2196 | return ret; |
0feae533 | 2197 | } |
b20ac0d4 | 2198 | |
52815b75 JR |
2199 | |
2200 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2201 | { | |
2202 | pci_disable_ats(pdev); | |
2203 | pci_disable_pri(pdev); | |
2204 | pci_disable_pasid(pdev); | |
2205 | } | |
2206 | ||
6a113ddc JR |
2207 | /* FIXME: Change generic reset-function to do the same */ |
2208 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2209 | { | |
2210 | u16 control; | |
2211 | int pos; | |
2212 | ||
46277b75 | 2213 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2214 | if (!pos) |
2215 | return -EINVAL; | |
2216 | ||
46277b75 JR |
2217 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2218 | control |= PCI_PRI_CTRL_RESET; | |
2219 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2220 | |
2221 | return 0; | |
2222 | } | |
2223 | ||
52815b75 JR |
2224 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2225 | { | |
6a113ddc JR |
2226 | bool reset_enable; |
2227 | int reqs, ret; | |
2228 | ||
2229 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2230 | reqs = 32; | |
2231 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2232 | reqs = 1; | |
2233 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2234 | |
2235 | /* Only allow access to user-accessible pages */ | |
2236 | ret = pci_enable_pasid(pdev, 0); | |
2237 | if (ret) | |
2238 | goto out_err; | |
2239 | ||
2240 | /* First reset the PRI state of the device */ | |
2241 | ret = pci_reset_pri(pdev); | |
2242 | if (ret) | |
2243 | goto out_err; | |
2244 | ||
6a113ddc JR |
2245 | /* Enable PRI */ |
2246 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2247 | if (ret) |
2248 | goto out_err; | |
2249 | ||
6a113ddc JR |
2250 | if (reset_enable) { |
2251 | ret = pri_reset_while_enabled(pdev); | |
2252 | if (ret) | |
2253 | goto out_err; | |
2254 | } | |
2255 | ||
52815b75 JR |
2256 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2257 | if (ret) | |
2258 | goto out_err; | |
2259 | ||
2260 | return 0; | |
2261 | ||
2262 | out_err: | |
2263 | pci_disable_pri(pdev); | |
2264 | pci_disable_pasid(pdev); | |
2265 | ||
2266 | return ret; | |
2267 | } | |
2268 | ||
c99afa25 | 2269 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2270 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2271 | |
98f1ad25 | 2272 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2273 | { |
a3b93121 | 2274 | u16 status; |
c99afa25 JR |
2275 | int pos; |
2276 | ||
46277b75 | 2277 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2278 | if (!pos) |
2279 | return false; | |
2280 | ||
a3b93121 | 2281 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2282 | |
a3b93121 | 2283 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2284 | } |
2285 | ||
407d733e | 2286 | /* |
df805abb | 2287 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2288 | * assigns it visible for the hardware |
2289 | */ | |
15898bbc JR |
2290 | static int attach_device(struct device *dev, |
2291 | struct protection_domain *domain) | |
0feae533 | 2292 | { |
fd7b5535 | 2293 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2294 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2295 | unsigned long flags; |
15898bbc | 2296 | int ret; |
eba6ac60 | 2297 | |
ea61cddb JR |
2298 | dev_data = get_dev_data(dev); |
2299 | ||
52815b75 JR |
2300 | if (domain->flags & PD_IOMMUV2_MASK) { |
2301 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2302 | return -EINVAL; | |
2303 | ||
2304 | if (pdev_iommuv2_enable(pdev) != 0) | |
2305 | return -EINVAL; | |
2306 | ||
2307 | dev_data->ats.enabled = true; | |
2308 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2309 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2310 | } else if (amd_iommu_iotlb_sup && |
2311 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2312 | dev_data->ats.enabled = true; |
2313 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2314 | } | |
fd7b5535 | 2315 | |
eba6ac60 | 2316 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2317 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2318 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2319 | ||
0feae533 JR |
2320 | /* |
2321 | * We might boot into a crash-kernel here. The crashed kernel | |
2322 | * left the caches in the IOMMU dirty. So we have to flush | |
2323 | * here to evict all dirty stuff. | |
2324 | */ | |
17b124bf | 2325 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2326 | |
2327 | return ret; | |
b20ac0d4 JR |
2328 | } |
2329 | ||
355bf553 JR |
2330 | /* |
2331 | * Removes a device from a protection domain (unlocked) | |
2332 | */ | |
ec9e79ef | 2333 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2334 | { |
2ca76279 | 2335 | struct protection_domain *domain; |
7c392cbe | 2336 | unsigned long flags; |
c4596114 | 2337 | |
7f760ddd | 2338 | BUG_ON(!dev_data->domain); |
355bf553 | 2339 | |
2ca76279 JR |
2340 | domain = dev_data->domain; |
2341 | ||
2342 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2343 | |
71f77580 JR |
2344 | if (dev_data->alias_data != NULL) { |
2345 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2346 | ||
7f760ddd | 2347 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2348 | do_detach(alias_data); |
24100055 JR |
2349 | } |
2350 | ||
7f760ddd | 2351 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2352 | do_detach(dev_data); |
7f760ddd | 2353 | |
2ca76279 | 2354 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2355 | |
2356 | /* | |
2357 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2358 | * passthrough domain if it is detached from any other domain. |
2359 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2360 | */ |
5abcdba4 | 2361 | if (dev_data->passthrough && |
d3ad9373 | 2362 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2363 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2364 | } |
2365 | ||
2366 | /* | |
2367 | * Removes a device from a protection domain (with devtable_lock held) | |
2368 | */ | |
15898bbc | 2369 | static void detach_device(struct device *dev) |
355bf553 | 2370 | { |
52815b75 | 2371 | struct protection_domain *domain; |
ea61cddb | 2372 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2373 | unsigned long flags; |
2374 | ||
ec9e79ef | 2375 | dev_data = get_dev_data(dev); |
52815b75 | 2376 | domain = dev_data->domain; |
ec9e79ef | 2377 | |
355bf553 JR |
2378 | /* lock device table */ |
2379 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2380 | __detach_device(dev_data); |
355bf553 | 2381 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2382 | |
52815b75 JR |
2383 | if (domain->flags & PD_IOMMUV2_MASK) |
2384 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2385 | else if (dev_data->ats.enabled) | |
ea61cddb | 2386 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2387 | |
2388 | dev_data->ats.enabled = false; | |
355bf553 | 2389 | } |
e275a2a0 | 2390 | |
15898bbc JR |
2391 | /* |
2392 | * Find out the protection domain structure for a given PCI device. This | |
2393 | * will give us the pointer to the page table root for example. | |
2394 | */ | |
2395 | static struct protection_domain *domain_for_device(struct device *dev) | |
2396 | { | |
71f77580 | 2397 | struct iommu_dev_data *dev_data; |
2b02b091 | 2398 | struct protection_domain *dom = NULL; |
15898bbc | 2399 | unsigned long flags; |
15898bbc | 2400 | |
657cbb6b | 2401 | dev_data = get_dev_data(dev); |
15898bbc | 2402 | |
2b02b091 JR |
2403 | if (dev_data->domain) |
2404 | return dev_data->domain; | |
15898bbc | 2405 | |
71f77580 JR |
2406 | if (dev_data->alias_data != NULL) { |
2407 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2408 | |
2409 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2410 | if (alias_data->domain != NULL) { | |
2411 | __attach_device(dev_data, alias_data->domain); | |
2412 | dom = alias_data->domain; | |
2413 | } | |
2414 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2415 | } | |
15898bbc JR |
2416 | |
2417 | return dom; | |
2418 | } | |
2419 | ||
e275a2a0 JR |
2420 | static int device_change_notifier(struct notifier_block *nb, |
2421 | unsigned long action, void *data) | |
2422 | { | |
e275a2a0 | 2423 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2424 | struct protection_domain *domain; |
2425 | struct iommu_dev_data *dev_data; | |
2426 | struct device *dev = data; | |
e275a2a0 | 2427 | struct amd_iommu *iommu; |
1ac4cbbc | 2428 | unsigned long flags; |
5abcdba4 | 2429 | u16 devid; |
e275a2a0 | 2430 | |
98fc5a69 JR |
2431 | if (!check_device(dev)) |
2432 | return 0; | |
e275a2a0 | 2433 | |
5abcdba4 JR |
2434 | devid = get_device_id(dev); |
2435 | iommu = amd_iommu_rlookup_table[devid]; | |
2436 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2437 | |
2438 | switch (action) { | |
c1eee67b | 2439 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2440 | |
2441 | domain = domain_for_device(dev); | |
2442 | ||
e275a2a0 JR |
2443 | if (!domain) |
2444 | goto out; | |
5abcdba4 | 2445 | if (dev_data->passthrough) |
a1ca331c | 2446 | break; |
15898bbc | 2447 | detach_device(dev); |
1ac4cbbc JR |
2448 | break; |
2449 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2450 | |
2451 | iommu_init_device(dev); | |
2452 | ||
2c9195e9 JR |
2453 | /* |
2454 | * dev_data is still NULL and | |
2455 | * got initialized in iommu_init_device | |
2456 | */ | |
2457 | dev_data = get_dev_data(dev); | |
2458 | ||
2459 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2460 | dev_data->passthrough = true; | |
2461 | attach_device(dev, pt_domain); | |
2462 | break; | |
2463 | } | |
2464 | ||
657cbb6b JR |
2465 | domain = domain_for_device(dev); |
2466 | ||
1ac4cbbc JR |
2467 | /* allocate a protection domain if a device is added */ |
2468 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2469 | if (!dma_domain) { |
2470 | dma_domain = dma_ops_domain_alloc(); | |
2471 | if (!dma_domain) | |
2472 | goto out; | |
2473 | dma_domain->target_dev = devid; | |
2474 | ||
2475 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2476 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2477 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2478 | } | |
ac1534a5 | 2479 | |
2c9195e9 | 2480 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2481 | |
e275a2a0 | 2482 | break; |
657cbb6b JR |
2483 | case BUS_NOTIFY_DEL_DEVICE: |
2484 | ||
2485 | iommu_uninit_device(dev); | |
2486 | ||
e275a2a0 JR |
2487 | default: |
2488 | goto out; | |
2489 | } | |
2490 | ||
e275a2a0 JR |
2491 | iommu_completion_wait(iommu); |
2492 | ||
2493 | out: | |
2494 | return 0; | |
2495 | } | |
2496 | ||
b25ae679 | 2497 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2498 | .notifier_call = device_change_notifier, |
2499 | }; | |
355bf553 | 2500 | |
8638c491 JR |
2501 | void amd_iommu_init_notifier(void) |
2502 | { | |
2503 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2504 | } | |
2505 | ||
431b2a20 JR |
2506 | /***************************************************************************** |
2507 | * | |
2508 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2509 | * | |
2510 | *****************************************************************************/ | |
2511 | ||
2512 | /* | |
2513 | * In the dma_ops path we only have the struct device. This function | |
2514 | * finds the corresponding IOMMU, the protection domain and the | |
2515 | * requestor id for a given device. | |
2516 | * If the device is not yet associated with a domain this is also done | |
2517 | * in this function. | |
2518 | */ | |
94f6d190 | 2519 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2520 | { |
94f6d190 | 2521 | struct protection_domain *domain; |
b20ac0d4 | 2522 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2523 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2524 | |
f99c0f1c | 2525 | if (!check_device(dev)) |
94f6d190 | 2526 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2527 | |
94f6d190 JR |
2528 | domain = domain_for_device(dev); |
2529 | if (domain != NULL && !dma_ops_domain(domain)) | |
2530 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2531 | |
94f6d190 JR |
2532 | if (domain != NULL) |
2533 | return domain; | |
b20ac0d4 | 2534 | |
df805abb | 2535 | /* Device not bound yet - bind it */ |
94f6d190 | 2536 | dma_dom = find_protection_domain(devid); |
15898bbc | 2537 | if (!dma_dom) |
94f6d190 JR |
2538 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2539 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2540 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2541 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2542 | |
94f6d190 | 2543 | return &dma_dom->domain; |
b20ac0d4 JR |
2544 | } |
2545 | ||
04bfdd84 JR |
2546 | static void update_device_table(struct protection_domain *domain) |
2547 | { | |
492667da | 2548 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2549 | |
ea61cddb JR |
2550 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2551 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2552 | } |
2553 | ||
2554 | static void update_domain(struct protection_domain *domain) | |
2555 | { | |
2556 | if (!domain->updated) | |
2557 | return; | |
2558 | ||
2559 | update_device_table(domain); | |
17b124bf JR |
2560 | |
2561 | domain_flush_devices(domain); | |
2562 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2563 | |
2564 | domain->updated = false; | |
2565 | } | |
2566 | ||
8bda3092 JR |
2567 | /* |
2568 | * This function fetches the PTE for a given address in the aperture | |
2569 | */ | |
2570 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2571 | unsigned long address) | |
2572 | { | |
384de729 | 2573 | struct aperture_range *aperture; |
8bda3092 JR |
2574 | u64 *pte, *pte_page; |
2575 | ||
384de729 JR |
2576 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2577 | if (!aperture) | |
2578 | return NULL; | |
2579 | ||
2580 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2581 | if (!pte) { |
cbb9d729 | 2582 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2583 | GFP_ATOMIC); |
384de729 JR |
2584 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2585 | } else | |
8c8c143c | 2586 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2587 | |
04bfdd84 | 2588 | update_domain(&dom->domain); |
8bda3092 JR |
2589 | |
2590 | return pte; | |
2591 | } | |
2592 | ||
431b2a20 JR |
2593 | /* |
2594 | * This is the generic map function. It maps one 4kb page at paddr to | |
2595 | * the given address in the DMA address space for the domain. | |
2596 | */ | |
680525e0 | 2597 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2598 | unsigned long address, |
2599 | phys_addr_t paddr, | |
2600 | int direction) | |
2601 | { | |
2602 | u64 *pte, __pte; | |
2603 | ||
2604 | WARN_ON(address > dom->aperture_size); | |
2605 | ||
2606 | paddr &= PAGE_MASK; | |
2607 | ||
8bda3092 | 2608 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2609 | if (!pte) |
8fd524b3 | 2610 | return DMA_ERROR_CODE; |
cb76c322 JR |
2611 | |
2612 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2613 | ||
2614 | if (direction == DMA_TO_DEVICE) | |
2615 | __pte |= IOMMU_PTE_IR; | |
2616 | else if (direction == DMA_FROM_DEVICE) | |
2617 | __pte |= IOMMU_PTE_IW; | |
2618 | else if (direction == DMA_BIDIRECTIONAL) | |
2619 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2620 | ||
2621 | WARN_ON(*pte); | |
2622 | ||
2623 | *pte = __pte; | |
2624 | ||
2625 | return (dma_addr_t)address; | |
2626 | } | |
2627 | ||
431b2a20 JR |
2628 | /* |
2629 | * The generic unmapping function for on page in the DMA address space. | |
2630 | */ | |
680525e0 | 2631 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2632 | unsigned long address) |
2633 | { | |
384de729 | 2634 | struct aperture_range *aperture; |
cb76c322 JR |
2635 | u64 *pte; |
2636 | ||
2637 | if (address >= dom->aperture_size) | |
2638 | return; | |
2639 | ||
384de729 JR |
2640 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2641 | if (!aperture) | |
2642 | return; | |
2643 | ||
2644 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2645 | if (!pte) | |
2646 | return; | |
cb76c322 | 2647 | |
8c8c143c | 2648 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2649 | |
2650 | WARN_ON(!*pte); | |
2651 | ||
2652 | *pte = 0ULL; | |
2653 | } | |
2654 | ||
431b2a20 JR |
2655 | /* |
2656 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2657 | * contiguous memory region into DMA address space. It is used by all |
2658 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2659 | * Must be called with the domain lock held. |
2660 | */ | |
cb76c322 | 2661 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2662 | struct dma_ops_domain *dma_dom, |
2663 | phys_addr_t paddr, | |
2664 | size_t size, | |
6d4f343f | 2665 | int dir, |
832a90c3 JR |
2666 | bool align, |
2667 | u64 dma_mask) | |
cb76c322 JR |
2668 | { |
2669 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2670 | dma_addr_t address, start, ret; |
cb76c322 | 2671 | unsigned int pages; |
6d4f343f | 2672 | unsigned long align_mask = 0; |
cb76c322 JR |
2673 | int i; |
2674 | ||
e3c449f5 | 2675 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2676 | paddr &= PAGE_MASK; |
2677 | ||
8ecaf8f1 JR |
2678 | INC_STATS_COUNTER(total_map_requests); |
2679 | ||
c1858976 JR |
2680 | if (pages > 1) |
2681 | INC_STATS_COUNTER(cross_page); | |
2682 | ||
6d4f343f JR |
2683 | if (align) |
2684 | align_mask = (1UL << get_order(size)) - 1; | |
2685 | ||
11b83888 | 2686 | retry: |
832a90c3 JR |
2687 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2688 | dma_mask); | |
8fd524b3 | 2689 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2690 | /* |
2691 | * setting next_address here will let the address | |
2692 | * allocator only scan the new allocated range in the | |
2693 | * first run. This is a small optimization. | |
2694 | */ | |
2695 | dma_dom->next_address = dma_dom->aperture_size; | |
2696 | ||
576175c2 | 2697 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2698 | goto out; |
2699 | ||
2700 | /* | |
af901ca1 | 2701 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2702 | * allocation again |
2703 | */ | |
2704 | goto retry; | |
2705 | } | |
cb76c322 JR |
2706 | |
2707 | start = address; | |
2708 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2709 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2710 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2711 | goto out_unmap; |
2712 | ||
cb76c322 JR |
2713 | paddr += PAGE_SIZE; |
2714 | start += PAGE_SIZE; | |
2715 | } | |
2716 | address += offset; | |
2717 | ||
5774f7c5 JR |
2718 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2719 | ||
afa9fdc2 | 2720 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2721 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2722 | dma_dom->need_flush = false; |
318afd41 | 2723 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2724 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2725 | |
cb76c322 JR |
2726 | out: |
2727 | return address; | |
53812c11 JR |
2728 | |
2729 | out_unmap: | |
2730 | ||
2731 | for (--i; i >= 0; --i) { | |
2732 | start -= PAGE_SIZE; | |
680525e0 | 2733 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2734 | } |
2735 | ||
2736 | dma_ops_free_addresses(dma_dom, address, pages); | |
2737 | ||
8fd524b3 | 2738 | return DMA_ERROR_CODE; |
cb76c322 JR |
2739 | } |
2740 | ||
431b2a20 JR |
2741 | /* |
2742 | * Does the reverse of the __map_single function. Must be called with | |
2743 | * the domain lock held too | |
2744 | */ | |
cd8c82e8 | 2745 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2746 | dma_addr_t dma_addr, |
2747 | size_t size, | |
2748 | int dir) | |
2749 | { | |
04e0463e | 2750 | dma_addr_t flush_addr; |
cb76c322 JR |
2751 | dma_addr_t i, start; |
2752 | unsigned int pages; | |
2753 | ||
8fd524b3 | 2754 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2755 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2756 | return; |
2757 | ||
04e0463e | 2758 | flush_addr = dma_addr; |
e3c449f5 | 2759 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2760 | dma_addr &= PAGE_MASK; |
2761 | start = dma_addr; | |
2762 | ||
2763 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2764 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2765 | start += PAGE_SIZE; |
2766 | } | |
2767 | ||
5774f7c5 JR |
2768 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2769 | ||
cb76c322 | 2770 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2771 | |
80be308d | 2772 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2773 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2774 | dma_dom->need_flush = false; |
2775 | } | |
cb76c322 JR |
2776 | } |
2777 | ||
431b2a20 JR |
2778 | /* |
2779 | * The exported map_single function for dma_ops. | |
2780 | */ | |
51491367 FT |
2781 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2782 | unsigned long offset, size_t size, | |
2783 | enum dma_data_direction dir, | |
2784 | struct dma_attrs *attrs) | |
4da70b9e JR |
2785 | { |
2786 | unsigned long flags; | |
4da70b9e | 2787 | struct protection_domain *domain; |
4da70b9e | 2788 | dma_addr_t addr; |
832a90c3 | 2789 | u64 dma_mask; |
51491367 | 2790 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2791 | |
0f2a86f2 JR |
2792 | INC_STATS_COUNTER(cnt_map_single); |
2793 | ||
94f6d190 JR |
2794 | domain = get_domain(dev); |
2795 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2796 | return (dma_addr_t)paddr; |
94f6d190 JR |
2797 | else if (IS_ERR(domain)) |
2798 | return DMA_ERROR_CODE; | |
4da70b9e | 2799 | |
f99c0f1c JR |
2800 | dma_mask = *dev->dma_mask; |
2801 | ||
4da70b9e | 2802 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2803 | |
cd8c82e8 | 2804 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2805 | dma_mask); |
8fd524b3 | 2806 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2807 | goto out; |
2808 | ||
17b124bf | 2809 | domain_flush_complete(domain); |
4da70b9e JR |
2810 | |
2811 | out: | |
2812 | spin_unlock_irqrestore(&domain->lock, flags); | |
2813 | ||
2814 | return addr; | |
2815 | } | |
2816 | ||
431b2a20 JR |
2817 | /* |
2818 | * The exported unmap_single function for dma_ops. | |
2819 | */ | |
51491367 FT |
2820 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2821 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2822 | { |
2823 | unsigned long flags; | |
4da70b9e | 2824 | struct protection_domain *domain; |
4da70b9e | 2825 | |
146a6917 JR |
2826 | INC_STATS_COUNTER(cnt_unmap_single); |
2827 | ||
94f6d190 JR |
2828 | domain = get_domain(dev); |
2829 | if (IS_ERR(domain)) | |
5b28df6f JR |
2830 | return; |
2831 | ||
4da70b9e JR |
2832 | spin_lock_irqsave(&domain->lock, flags); |
2833 | ||
cd8c82e8 | 2834 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2835 | |
17b124bf | 2836 | domain_flush_complete(domain); |
4da70b9e JR |
2837 | |
2838 | spin_unlock_irqrestore(&domain->lock, flags); | |
2839 | } | |
2840 | ||
431b2a20 JR |
2841 | /* |
2842 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2843 | * lists). | |
2844 | */ | |
65b050ad | 2845 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2846 | int nelems, enum dma_data_direction dir, |
2847 | struct dma_attrs *attrs) | |
65b050ad JR |
2848 | { |
2849 | unsigned long flags; | |
65b050ad | 2850 | struct protection_domain *domain; |
65b050ad JR |
2851 | int i; |
2852 | struct scatterlist *s; | |
2853 | phys_addr_t paddr; | |
2854 | int mapped_elems = 0; | |
832a90c3 | 2855 | u64 dma_mask; |
65b050ad | 2856 | |
d03f067a JR |
2857 | INC_STATS_COUNTER(cnt_map_sg); |
2858 | ||
94f6d190 | 2859 | domain = get_domain(dev); |
a0e191b2 | 2860 | if (IS_ERR(domain)) |
94f6d190 | 2861 | return 0; |
dbcc112e | 2862 | |
832a90c3 | 2863 | dma_mask = *dev->dma_mask; |
65b050ad | 2864 | |
65b050ad JR |
2865 | spin_lock_irqsave(&domain->lock, flags); |
2866 | ||
2867 | for_each_sg(sglist, s, nelems, i) { | |
2868 | paddr = sg_phys(s); | |
2869 | ||
cd8c82e8 | 2870 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2871 | paddr, s->length, dir, false, |
2872 | dma_mask); | |
65b050ad JR |
2873 | |
2874 | if (s->dma_address) { | |
2875 | s->dma_length = s->length; | |
2876 | mapped_elems++; | |
2877 | } else | |
2878 | goto unmap; | |
65b050ad JR |
2879 | } |
2880 | ||
17b124bf | 2881 | domain_flush_complete(domain); |
65b050ad JR |
2882 | |
2883 | out: | |
2884 | spin_unlock_irqrestore(&domain->lock, flags); | |
2885 | ||
2886 | return mapped_elems; | |
2887 | unmap: | |
2888 | for_each_sg(sglist, s, mapped_elems, i) { | |
2889 | if (s->dma_address) | |
cd8c82e8 | 2890 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2891 | s->dma_length, dir); |
2892 | s->dma_address = s->dma_length = 0; | |
2893 | } | |
2894 | ||
2895 | mapped_elems = 0; | |
2896 | ||
2897 | goto out; | |
2898 | } | |
2899 | ||
431b2a20 JR |
2900 | /* |
2901 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2902 | * lists). | |
2903 | */ | |
65b050ad | 2904 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2905 | int nelems, enum dma_data_direction dir, |
2906 | struct dma_attrs *attrs) | |
65b050ad JR |
2907 | { |
2908 | unsigned long flags; | |
65b050ad JR |
2909 | struct protection_domain *domain; |
2910 | struct scatterlist *s; | |
65b050ad JR |
2911 | int i; |
2912 | ||
55877a6b JR |
2913 | INC_STATS_COUNTER(cnt_unmap_sg); |
2914 | ||
94f6d190 JR |
2915 | domain = get_domain(dev); |
2916 | if (IS_ERR(domain)) | |
5b28df6f JR |
2917 | return; |
2918 | ||
65b050ad JR |
2919 | spin_lock_irqsave(&domain->lock, flags); |
2920 | ||
2921 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2922 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2923 | s->dma_length, dir); |
65b050ad JR |
2924 | s->dma_address = s->dma_length = 0; |
2925 | } | |
2926 | ||
17b124bf | 2927 | domain_flush_complete(domain); |
65b050ad JR |
2928 | |
2929 | spin_unlock_irqrestore(&domain->lock, flags); | |
2930 | } | |
2931 | ||
431b2a20 JR |
2932 | /* |
2933 | * The exported alloc_coherent function for dma_ops. | |
2934 | */ | |
5d8b53cf | 2935 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2936 | dma_addr_t *dma_addr, gfp_t flag, |
2937 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2938 | { |
2939 | unsigned long flags; | |
2940 | void *virt_addr; | |
5d8b53cf | 2941 | struct protection_domain *domain; |
5d8b53cf | 2942 | phys_addr_t paddr; |
832a90c3 | 2943 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2944 | |
c8f0fb36 JR |
2945 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2946 | ||
94f6d190 JR |
2947 | domain = get_domain(dev); |
2948 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2949 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2950 | *dma_addr = __pa(virt_addr); | |
2951 | return virt_addr; | |
94f6d190 JR |
2952 | } else if (IS_ERR(domain)) |
2953 | return NULL; | |
5d8b53cf | 2954 | |
f99c0f1c JR |
2955 | dma_mask = dev->coherent_dma_mask; |
2956 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2957 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2958 | |
2959 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2960 | if (!virt_addr) | |
b25ae679 | 2961 | return NULL; |
5d8b53cf | 2962 | |
5d8b53cf JR |
2963 | paddr = virt_to_phys(virt_addr); |
2964 | ||
832a90c3 JR |
2965 | if (!dma_mask) |
2966 | dma_mask = *dev->dma_mask; | |
2967 | ||
5d8b53cf JR |
2968 | spin_lock_irqsave(&domain->lock, flags); |
2969 | ||
cd8c82e8 | 2970 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2971 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2972 | |
8fd524b3 | 2973 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2974 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2975 | goto out_free; |
367d04c4 | 2976 | } |
5d8b53cf | 2977 | |
17b124bf | 2978 | domain_flush_complete(domain); |
5d8b53cf | 2979 | |
5d8b53cf JR |
2980 | spin_unlock_irqrestore(&domain->lock, flags); |
2981 | ||
2982 | return virt_addr; | |
5b28df6f JR |
2983 | |
2984 | out_free: | |
2985 | ||
2986 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2987 | ||
2988 | return NULL; | |
5d8b53cf JR |
2989 | } |
2990 | ||
431b2a20 JR |
2991 | /* |
2992 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2993 | */ |
5d8b53cf | 2994 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2995 | void *virt_addr, dma_addr_t dma_addr, |
2996 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2997 | { |
2998 | unsigned long flags; | |
5d8b53cf | 2999 | struct protection_domain *domain; |
5d8b53cf | 3000 | |
5d31ee7e JR |
3001 | INC_STATS_COUNTER(cnt_free_coherent); |
3002 | ||
94f6d190 JR |
3003 | domain = get_domain(dev); |
3004 | if (IS_ERR(domain)) | |
5b28df6f JR |
3005 | goto free_mem; |
3006 | ||
5d8b53cf JR |
3007 | spin_lock_irqsave(&domain->lock, flags); |
3008 | ||
cd8c82e8 | 3009 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 3010 | |
17b124bf | 3011 | domain_flush_complete(domain); |
5d8b53cf JR |
3012 | |
3013 | spin_unlock_irqrestore(&domain->lock, flags); | |
3014 | ||
3015 | free_mem: | |
3016 | free_pages((unsigned long)virt_addr, get_order(size)); | |
3017 | } | |
3018 | ||
b39ba6ad JR |
3019 | /* |
3020 | * This function is called by the DMA layer to find out if we can handle a | |
3021 | * particular device. It is part of the dma_ops. | |
3022 | */ | |
3023 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
3024 | { | |
420aef8a | 3025 | return check_device(dev); |
b39ba6ad JR |
3026 | } |
3027 | ||
c432f3df | 3028 | /* |
431b2a20 JR |
3029 | * The function for pre-allocating protection domains. |
3030 | * | |
c432f3df JR |
3031 | * If the driver core informs the DMA layer if a driver grabs a device |
3032 | * we don't need to preallocate the protection domains anymore. | |
3033 | * For now we have to. | |
3034 | */ | |
943bc7e1 | 3035 | static void __init prealloc_protection_domains(void) |
c432f3df | 3036 | { |
5abcdba4 | 3037 | struct iommu_dev_data *dev_data; |
c432f3df | 3038 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3039 | struct pci_dev *dev = NULL; |
98fc5a69 | 3040 | u16 devid; |
c432f3df | 3041 | |
d18c69d3 | 3042 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3043 | |
3044 | /* Do we handle this device? */ | |
3045 | if (!check_device(&dev->dev)) | |
c432f3df | 3046 | continue; |
98fc5a69 | 3047 | |
5abcdba4 JR |
3048 | dev_data = get_dev_data(&dev->dev); |
3049 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3050 | /* Make sure passthrough domain is allocated */ | |
3051 | alloc_passthrough_domain(); | |
3052 | dev_data->passthrough = true; | |
3053 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3054 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3055 | dev_name(&dev->dev)); |
3056 | } | |
3057 | ||
98fc5a69 | 3058 | /* Is there already any domain for it? */ |
15898bbc | 3059 | if (domain_for_device(&dev->dev)) |
c432f3df | 3060 | continue; |
98fc5a69 JR |
3061 | |
3062 | devid = get_device_id(&dev->dev); | |
3063 | ||
87a64d52 | 3064 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3065 | if (!dma_dom) |
3066 | continue; | |
3067 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3068 | dma_dom->target_dev = devid; |
3069 | ||
15898bbc | 3070 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3071 | |
bd60b735 | 3072 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3073 | } |
3074 | } | |
3075 | ||
160c1d8e | 3076 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3077 | .alloc = alloc_coherent, |
3078 | .free = free_coherent, | |
51491367 FT |
3079 | .map_page = map_page, |
3080 | .unmap_page = unmap_page, | |
6631ee9d JR |
3081 | .map_sg = map_sg, |
3082 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3083 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3084 | }; |
3085 | ||
27c2127a JR |
3086 | static unsigned device_dma_ops_init(void) |
3087 | { | |
5abcdba4 | 3088 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3089 | struct pci_dev *pdev = NULL; |
3090 | unsigned unhandled = 0; | |
3091 | ||
3092 | for_each_pci_dev(pdev) { | |
3093 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3094 | |
3095 | iommu_ignore_device(&pdev->dev); | |
3096 | ||
27c2127a JR |
3097 | unhandled += 1; |
3098 | continue; | |
3099 | } | |
3100 | ||
5abcdba4 JR |
3101 | dev_data = get_dev_data(&pdev->dev); |
3102 | ||
3103 | if (!dev_data->passthrough) | |
3104 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3105 | else | |
3106 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3107 | } |
3108 | ||
3109 | return unhandled; | |
3110 | } | |
3111 | ||
431b2a20 JR |
3112 | /* |
3113 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3114 | */ | |
f5325094 JR |
3115 | |
3116 | void __init amd_iommu_init_api(void) | |
3117 | { | |
2cc21c42 | 3118 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3119 | } |
3120 | ||
6631ee9d JR |
3121 | int __init amd_iommu_init_dma_ops(void) |
3122 | { | |
3123 | struct amd_iommu *iommu; | |
27c2127a | 3124 | int ret, unhandled; |
6631ee9d | 3125 | |
431b2a20 JR |
3126 | /* |
3127 | * first allocate a default protection domain for every IOMMU we | |
3128 | * found in the system. Devices not assigned to any other | |
3129 | * protection domain will be assigned to the default one. | |
3130 | */ | |
3bd22172 | 3131 | for_each_iommu(iommu) { |
87a64d52 | 3132 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3133 | if (iommu->default_dom == NULL) |
3134 | return -ENOMEM; | |
e2dc14a2 | 3135 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3136 | ret = iommu_init_unity_mappings(iommu); |
3137 | if (ret) | |
3138 | goto free_domains; | |
3139 | } | |
3140 | ||
431b2a20 | 3141 | /* |
8793abeb | 3142 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3143 | */ |
8793abeb | 3144 | prealloc_protection_domains(); |
6631ee9d JR |
3145 | |
3146 | iommu_detected = 1; | |
75f1cdf1 | 3147 | swiotlb = 0; |
6631ee9d | 3148 | |
431b2a20 | 3149 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3150 | unhandled = device_dma_ops_init(); |
3151 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3152 | /* There are unhandled devices - initialize swiotlb for them */ | |
3153 | swiotlb = 1; | |
3154 | } | |
6631ee9d | 3155 | |
7f26508b JR |
3156 | amd_iommu_stats_init(); |
3157 | ||
62410eeb JR |
3158 | if (amd_iommu_unmap_flush) |
3159 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3160 | else | |
3161 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3162 | ||
6631ee9d JR |
3163 | return 0; |
3164 | ||
3165 | free_domains: | |
3166 | ||
3bd22172 | 3167 | for_each_iommu(iommu) { |
91457df7 | 3168 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3169 | } |
3170 | ||
3171 | return ret; | |
3172 | } | |
6d98cd80 JR |
3173 | |
3174 | /***************************************************************************** | |
3175 | * | |
3176 | * The following functions belong to the exported interface of AMD IOMMU | |
3177 | * | |
3178 | * This interface allows access to lower level functions of the IOMMU | |
3179 | * like protection domain handling and assignement of devices to domains | |
3180 | * which is not possible with the dma_ops interface. | |
3181 | * | |
3182 | *****************************************************************************/ | |
3183 | ||
6d98cd80 JR |
3184 | static void cleanup_domain(struct protection_domain *domain) |
3185 | { | |
492667da | 3186 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 3187 | unsigned long flags; |
6d98cd80 JR |
3188 | |
3189 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3190 | ||
492667da | 3191 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3192 | __detach_device(dev_data); |
492667da JR |
3193 | atomic_set(&dev_data->bind, 0); |
3194 | } | |
6d98cd80 JR |
3195 | |
3196 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3197 | } | |
3198 | ||
2650815f JR |
3199 | static void protection_domain_free(struct protection_domain *domain) |
3200 | { | |
3201 | if (!domain) | |
3202 | return; | |
3203 | ||
aeb26f55 JR |
3204 | del_domain_from_list(domain); |
3205 | ||
2650815f JR |
3206 | if (domain->id) |
3207 | domain_id_free(domain->id); | |
3208 | ||
3209 | kfree(domain); | |
3210 | } | |
3211 | ||
3212 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3213 | { |
3214 | struct protection_domain *domain; | |
3215 | ||
3216 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3217 | if (!domain) | |
2650815f | 3218 | return NULL; |
c156e347 JR |
3219 | |
3220 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3221 | mutex_init(&domain->api_lock); |
c156e347 JR |
3222 | domain->id = domain_id_alloc(); |
3223 | if (!domain->id) | |
2650815f | 3224 | goto out_err; |
7c392cbe | 3225 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3226 | |
aeb26f55 JR |
3227 | add_domain_to_list(domain); |
3228 | ||
2650815f JR |
3229 | return domain; |
3230 | ||
3231 | out_err: | |
3232 | kfree(domain); | |
3233 | ||
3234 | return NULL; | |
3235 | } | |
3236 | ||
5abcdba4 JR |
3237 | static int __init alloc_passthrough_domain(void) |
3238 | { | |
3239 | if (pt_domain != NULL) | |
3240 | return 0; | |
3241 | ||
3242 | /* allocate passthrough domain */ | |
3243 | pt_domain = protection_domain_alloc(); | |
3244 | if (!pt_domain) | |
3245 | return -ENOMEM; | |
3246 | ||
3247 | pt_domain->mode = PAGE_MODE_NONE; | |
3248 | ||
3249 | return 0; | |
3250 | } | |
2650815f JR |
3251 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3252 | { | |
3253 | struct protection_domain *domain; | |
3254 | ||
3255 | domain = protection_domain_alloc(); | |
3256 | if (!domain) | |
c156e347 | 3257 | goto out_free; |
2650815f JR |
3258 | |
3259 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3260 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3261 | if (!domain->pt_root) | |
3262 | goto out_free; | |
3263 | ||
f3572db8 JR |
3264 | domain->iommu_domain = dom; |
3265 | ||
c156e347 JR |
3266 | dom->priv = domain; |
3267 | ||
0ff64f80 JR |
3268 | dom->geometry.aperture_start = 0; |
3269 | dom->geometry.aperture_end = ~0ULL; | |
3270 | dom->geometry.force_aperture = true; | |
3271 | ||
c156e347 JR |
3272 | return 0; |
3273 | ||
3274 | out_free: | |
2650815f | 3275 | protection_domain_free(domain); |
c156e347 JR |
3276 | |
3277 | return -ENOMEM; | |
3278 | } | |
3279 | ||
98383fc3 JR |
3280 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3281 | { | |
3282 | struct protection_domain *domain = dom->priv; | |
3283 | ||
3284 | if (!domain) | |
3285 | return; | |
3286 | ||
3287 | if (domain->dev_cnt > 0) | |
3288 | cleanup_domain(domain); | |
3289 | ||
3290 | BUG_ON(domain->dev_cnt != 0); | |
3291 | ||
132bd68f JR |
3292 | if (domain->mode != PAGE_MODE_NONE) |
3293 | free_pagetable(domain); | |
98383fc3 | 3294 | |
52815b75 JR |
3295 | if (domain->flags & PD_IOMMUV2_MASK) |
3296 | free_gcr3_table(domain); | |
3297 | ||
8b408fe4 | 3298 | protection_domain_free(domain); |
98383fc3 JR |
3299 | |
3300 | dom->priv = NULL; | |
3301 | } | |
3302 | ||
684f2888 JR |
3303 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3304 | struct device *dev) | |
3305 | { | |
657cbb6b | 3306 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3307 | struct amd_iommu *iommu; |
684f2888 JR |
3308 | u16 devid; |
3309 | ||
98fc5a69 | 3310 | if (!check_device(dev)) |
684f2888 JR |
3311 | return; |
3312 | ||
98fc5a69 | 3313 | devid = get_device_id(dev); |
684f2888 | 3314 | |
657cbb6b | 3315 | if (dev_data->domain != NULL) |
15898bbc | 3316 | detach_device(dev); |
684f2888 JR |
3317 | |
3318 | iommu = amd_iommu_rlookup_table[devid]; | |
3319 | if (!iommu) | |
3320 | return; | |
3321 | ||
684f2888 JR |
3322 | iommu_completion_wait(iommu); |
3323 | } | |
3324 | ||
01106066 JR |
3325 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3326 | struct device *dev) | |
3327 | { | |
3328 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3329 | struct iommu_dev_data *dev_data; |
01106066 | 3330 | struct amd_iommu *iommu; |
15898bbc | 3331 | int ret; |
01106066 | 3332 | |
98fc5a69 | 3333 | if (!check_device(dev)) |
01106066 JR |
3334 | return -EINVAL; |
3335 | ||
657cbb6b JR |
3336 | dev_data = dev->archdata.iommu; |
3337 | ||
f62dda66 | 3338 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3339 | if (!iommu) |
3340 | return -EINVAL; | |
3341 | ||
657cbb6b | 3342 | if (dev_data->domain) |
15898bbc | 3343 | detach_device(dev); |
01106066 | 3344 | |
15898bbc | 3345 | ret = attach_device(dev, domain); |
01106066 JR |
3346 | |
3347 | iommu_completion_wait(iommu); | |
3348 | ||
15898bbc | 3349 | return ret; |
01106066 JR |
3350 | } |
3351 | ||
468e2366 | 3352 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3353 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3354 | { |
3355 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3356 | int prot = 0; |
3357 | int ret; | |
3358 | ||
132bd68f JR |
3359 | if (domain->mode == PAGE_MODE_NONE) |
3360 | return -EINVAL; | |
3361 | ||
c6229ca6 JR |
3362 | if (iommu_prot & IOMMU_READ) |
3363 | prot |= IOMMU_PROT_IR; | |
3364 | if (iommu_prot & IOMMU_WRITE) | |
3365 | prot |= IOMMU_PROT_IW; | |
3366 | ||
5d214fe6 | 3367 | mutex_lock(&domain->api_lock); |
795e74f7 | 3368 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3369 | mutex_unlock(&domain->api_lock); |
3370 | ||
795e74f7 | 3371 | return ret; |
c6229ca6 JR |
3372 | } |
3373 | ||
5009065d OBC |
3374 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3375 | size_t page_size) | |
eb74ff6c | 3376 | { |
eb74ff6c | 3377 | struct protection_domain *domain = dom->priv; |
5009065d | 3378 | size_t unmap_size; |
eb74ff6c | 3379 | |
132bd68f JR |
3380 | if (domain->mode == PAGE_MODE_NONE) |
3381 | return -EINVAL; | |
3382 | ||
5d214fe6 | 3383 | mutex_lock(&domain->api_lock); |
468e2366 | 3384 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3385 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3386 | |
17b124bf | 3387 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3388 | |
5009065d | 3389 | return unmap_size; |
eb74ff6c JR |
3390 | } |
3391 | ||
645c4c8d | 3392 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3393 | dma_addr_t iova) |
645c4c8d JR |
3394 | { |
3395 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3396 | unsigned long offset_mask; |
645c4c8d | 3397 | phys_addr_t paddr; |
f03152bb | 3398 | u64 *pte, __pte; |
645c4c8d | 3399 | |
132bd68f JR |
3400 | if (domain->mode == PAGE_MODE_NONE) |
3401 | return iova; | |
3402 | ||
24cd7723 | 3403 | pte = fetch_pte(domain, iova); |
645c4c8d | 3404 | |
a6d41a40 | 3405 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3406 | return 0; |
3407 | ||
f03152bb JR |
3408 | if (PM_PTE_LEVEL(*pte) == 0) |
3409 | offset_mask = PAGE_SIZE - 1; | |
3410 | else | |
3411 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3412 | ||
3413 | __pte = *pte & PM_ADDR_MASK; | |
3414 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3415 | |
3416 | return paddr; | |
3417 | } | |
3418 | ||
dbb9fd86 SY |
3419 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3420 | unsigned long cap) | |
3421 | { | |
80a506b8 JR |
3422 | switch (cap) { |
3423 | case IOMMU_CAP_CACHE_COHERENCY: | |
3424 | return 1; | |
bdddadcb JR |
3425 | case IOMMU_CAP_INTR_REMAP: |
3426 | return irq_remapping_enabled; | |
80a506b8 JR |
3427 | } |
3428 | ||
dbb9fd86 SY |
3429 | return 0; |
3430 | } | |
3431 | ||
26961efe JR |
3432 | static struct iommu_ops amd_iommu_ops = { |
3433 | .domain_init = amd_iommu_domain_init, | |
3434 | .domain_destroy = amd_iommu_domain_destroy, | |
3435 | .attach_dev = amd_iommu_attach_device, | |
3436 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3437 | .map = amd_iommu_map, |
3438 | .unmap = amd_iommu_unmap, | |
26961efe | 3439 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3440 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3441 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3442 | }; |
3443 | ||
0feae533 JR |
3444 | /***************************************************************************** |
3445 | * | |
3446 | * The next functions do a basic initialization of IOMMU for pass through | |
3447 | * mode | |
3448 | * | |
3449 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3450 | * DMA-API translation. | |
3451 | * | |
3452 | *****************************************************************************/ | |
3453 | ||
3454 | int __init amd_iommu_init_passthrough(void) | |
3455 | { | |
5abcdba4 | 3456 | struct iommu_dev_data *dev_data; |
0feae533 | 3457 | struct pci_dev *dev = NULL; |
5abcdba4 | 3458 | struct amd_iommu *iommu; |
15898bbc | 3459 | u16 devid; |
5abcdba4 | 3460 | int ret; |
0feae533 | 3461 | |
5abcdba4 JR |
3462 | ret = alloc_passthrough_domain(); |
3463 | if (ret) | |
3464 | return ret; | |
0feae533 | 3465 | |
6c54aabd | 3466 | for_each_pci_dev(dev) { |
98fc5a69 | 3467 | if (!check_device(&dev->dev)) |
0feae533 JR |
3468 | continue; |
3469 | ||
5abcdba4 JR |
3470 | dev_data = get_dev_data(&dev->dev); |
3471 | dev_data->passthrough = true; | |
3472 | ||
98fc5a69 JR |
3473 | devid = get_device_id(&dev->dev); |
3474 | ||
15898bbc | 3475 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3476 | if (!iommu) |
3477 | continue; | |
3478 | ||
15898bbc | 3479 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3480 | } |
3481 | ||
2655d7a2 JR |
3482 | amd_iommu_stats_init(); |
3483 | ||
0feae533 JR |
3484 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3485 | ||
3486 | return 0; | |
3487 | } | |
72e1dcc4 JR |
3488 | |
3489 | /* IOMMUv2 specific functions */ | |
3490 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3491 | { | |
3492 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3493 | } | |
3494 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3495 | ||
3496 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3497 | { | |
3498 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3499 | } | |
3500 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3501 | |
3502 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3503 | { | |
3504 | struct protection_domain *domain = dom->priv; | |
3505 | unsigned long flags; | |
3506 | ||
3507 | spin_lock_irqsave(&domain->lock, flags); | |
3508 | ||
3509 | /* Update data structure */ | |
3510 | domain->mode = PAGE_MODE_NONE; | |
3511 | domain->updated = true; | |
3512 | ||
3513 | /* Make changes visible to IOMMUs */ | |
3514 | update_domain(domain); | |
3515 | ||
3516 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3517 | free_pagetable(domain); | |
3518 | ||
3519 | spin_unlock_irqrestore(&domain->lock, flags); | |
3520 | } | |
3521 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3522 | |
3523 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3524 | { | |
3525 | struct protection_domain *domain = dom->priv; | |
3526 | unsigned long flags; | |
3527 | int levels, ret; | |
3528 | ||
3529 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3530 | return -EINVAL; | |
3531 | ||
3532 | /* Number of GCR3 table levels required */ | |
3533 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3534 | levels += 1; | |
3535 | ||
3536 | if (levels > amd_iommu_max_glx_val) | |
3537 | return -EINVAL; | |
3538 | ||
3539 | spin_lock_irqsave(&domain->lock, flags); | |
3540 | ||
3541 | /* | |
3542 | * Save us all sanity checks whether devices already in the | |
3543 | * domain support IOMMUv2. Just force that the domain has no | |
3544 | * devices attached when it is switched into IOMMUv2 mode. | |
3545 | */ | |
3546 | ret = -EBUSY; | |
3547 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3548 | goto out; | |
3549 | ||
3550 | ret = -ENOMEM; | |
3551 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3552 | if (domain->gcr3_tbl == NULL) | |
3553 | goto out; | |
3554 | ||
3555 | domain->glx = levels; | |
3556 | domain->flags |= PD_IOMMUV2_MASK; | |
3557 | domain->updated = true; | |
3558 | ||
3559 | update_domain(domain); | |
3560 | ||
3561 | ret = 0; | |
3562 | ||
3563 | out: | |
3564 | spin_unlock_irqrestore(&domain->lock, flags); | |
3565 | ||
3566 | return ret; | |
3567 | } | |
3568 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3569 | |
3570 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3571 | u64 address, bool size) | |
3572 | { | |
3573 | struct iommu_dev_data *dev_data; | |
3574 | struct iommu_cmd cmd; | |
3575 | int i, ret; | |
3576 | ||
3577 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3578 | return -EINVAL; | |
3579 | ||
3580 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3581 | ||
3582 | /* | |
3583 | * IOMMU TLB needs to be flushed before Device TLB to | |
3584 | * prevent device TLB refill from IOMMU TLB | |
3585 | */ | |
3586 | for (i = 0; i < amd_iommus_present; ++i) { | |
3587 | if (domain->dev_iommu[i] == 0) | |
3588 | continue; | |
3589 | ||
3590 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3591 | if (ret != 0) | |
3592 | goto out; | |
3593 | } | |
3594 | ||
3595 | /* Wait until IOMMU TLB flushes are complete */ | |
3596 | domain_flush_complete(domain); | |
3597 | ||
3598 | /* Now flush device TLBs */ | |
3599 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3600 | struct amd_iommu *iommu; | |
3601 | int qdep; | |
3602 | ||
3603 | BUG_ON(!dev_data->ats.enabled); | |
3604 | ||
3605 | qdep = dev_data->ats.qdep; | |
3606 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3607 | ||
3608 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3609 | qdep, address, size); | |
3610 | ||
3611 | ret = iommu_queue_command(iommu, &cmd); | |
3612 | if (ret != 0) | |
3613 | goto out; | |
3614 | } | |
3615 | ||
3616 | /* Wait until all device TLBs are flushed */ | |
3617 | domain_flush_complete(domain); | |
3618 | ||
3619 | ret = 0; | |
3620 | ||
3621 | out: | |
3622 | ||
3623 | return ret; | |
3624 | } | |
3625 | ||
3626 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3627 | u64 address) | |
3628 | { | |
399be2f5 JR |
3629 | INC_STATS_COUNTER(invalidate_iotlb); |
3630 | ||
22e266c7 JR |
3631 | return __flush_pasid(domain, pasid, address, false); |
3632 | } | |
3633 | ||
3634 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3635 | u64 address) | |
3636 | { | |
3637 | struct protection_domain *domain = dom->priv; | |
3638 | unsigned long flags; | |
3639 | int ret; | |
3640 | ||
3641 | spin_lock_irqsave(&domain->lock, flags); | |
3642 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3643 | spin_unlock_irqrestore(&domain->lock, flags); | |
3644 | ||
3645 | return ret; | |
3646 | } | |
3647 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3648 | ||
3649 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3650 | { | |
399be2f5 JR |
3651 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3652 | ||
22e266c7 JR |
3653 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3654 | true); | |
3655 | } | |
3656 | ||
3657 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3658 | { | |
3659 | struct protection_domain *domain = dom->priv; | |
3660 | unsigned long flags; | |
3661 | int ret; | |
3662 | ||
3663 | spin_lock_irqsave(&domain->lock, flags); | |
3664 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3665 | spin_unlock_irqrestore(&domain->lock, flags); | |
3666 | ||
3667 | return ret; | |
3668 | } | |
3669 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3670 | ||
b16137b1 JR |
3671 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3672 | { | |
3673 | int index; | |
3674 | u64 *pte; | |
3675 | ||
3676 | while (true) { | |
3677 | ||
3678 | index = (pasid >> (9 * level)) & 0x1ff; | |
3679 | pte = &root[index]; | |
3680 | ||
3681 | if (level == 0) | |
3682 | break; | |
3683 | ||
3684 | if (!(*pte & GCR3_VALID)) { | |
3685 | if (!alloc) | |
3686 | return NULL; | |
3687 | ||
3688 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3689 | if (root == NULL) | |
3690 | return NULL; | |
3691 | ||
3692 | *pte = __pa(root) | GCR3_VALID; | |
3693 | } | |
3694 | ||
3695 | root = __va(*pte & PAGE_MASK); | |
3696 | ||
3697 | level -= 1; | |
3698 | } | |
3699 | ||
3700 | return pte; | |
3701 | } | |
3702 | ||
3703 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3704 | unsigned long cr3) | |
3705 | { | |
3706 | u64 *pte; | |
3707 | ||
3708 | if (domain->mode != PAGE_MODE_NONE) | |
3709 | return -EINVAL; | |
3710 | ||
3711 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3712 | if (pte == NULL) | |
3713 | return -ENOMEM; | |
3714 | ||
3715 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3716 | ||
3717 | return __amd_iommu_flush_tlb(domain, pasid); | |
3718 | } | |
3719 | ||
3720 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3721 | { | |
3722 | u64 *pte; | |
3723 | ||
3724 | if (domain->mode != PAGE_MODE_NONE) | |
3725 | return -EINVAL; | |
3726 | ||
3727 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3728 | if (pte == NULL) | |
3729 | return 0; | |
3730 | ||
3731 | *pte = 0; | |
3732 | ||
3733 | return __amd_iommu_flush_tlb(domain, pasid); | |
3734 | } | |
3735 | ||
3736 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3737 | unsigned long cr3) | |
3738 | { | |
3739 | struct protection_domain *domain = dom->priv; | |
3740 | unsigned long flags; | |
3741 | int ret; | |
3742 | ||
3743 | spin_lock_irqsave(&domain->lock, flags); | |
3744 | ret = __set_gcr3(domain, pasid, cr3); | |
3745 | spin_unlock_irqrestore(&domain->lock, flags); | |
3746 | ||
3747 | return ret; | |
3748 | } | |
3749 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3750 | ||
3751 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3752 | { | |
3753 | struct protection_domain *domain = dom->priv; | |
3754 | unsigned long flags; | |
3755 | int ret; | |
3756 | ||
3757 | spin_lock_irqsave(&domain->lock, flags); | |
3758 | ret = __clear_gcr3(domain, pasid); | |
3759 | spin_unlock_irqrestore(&domain->lock, flags); | |
3760 | ||
3761 | return ret; | |
3762 | } | |
3763 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3764 | |
3765 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3766 | int status, int tag) | |
3767 | { | |
3768 | struct iommu_dev_data *dev_data; | |
3769 | struct amd_iommu *iommu; | |
3770 | struct iommu_cmd cmd; | |
3771 | ||
399be2f5 JR |
3772 | INC_STATS_COUNTER(complete_ppr); |
3773 | ||
c99afa25 JR |
3774 | dev_data = get_dev_data(&pdev->dev); |
3775 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3776 | ||
3777 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3778 | tag, dev_data->pri_tlp); | |
3779 | ||
3780 | return iommu_queue_command(iommu, &cmd); | |
3781 | } | |
3782 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3783 | |
3784 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3785 | { | |
3786 | struct protection_domain *domain; | |
3787 | ||
3788 | domain = get_domain(&pdev->dev); | |
3789 | if (IS_ERR(domain)) | |
3790 | return NULL; | |
3791 | ||
3792 | /* Only return IOMMUv2 domains */ | |
3793 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3794 | return NULL; | |
3795 | ||
3796 | return domain->iommu_domain; | |
3797 | } | |
3798 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3799 | |
3800 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3801 | { | |
3802 | struct iommu_dev_data *dev_data; | |
3803 | ||
3804 | if (!amd_iommu_v2_supported()) | |
3805 | return; | |
3806 | ||
3807 | dev_data = get_dev_data(&pdev->dev); | |
3808 | dev_data->errata |= (1 << erratum); | |
3809 | } | |
3810 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3811 | |
3812 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3813 | struct amd_iommu_device_info *info) | |
3814 | { | |
3815 | int max_pasids; | |
3816 | int pos; | |
3817 | ||
3818 | if (pdev == NULL || info == NULL) | |
3819 | return -EINVAL; | |
3820 | ||
3821 | if (!amd_iommu_v2_supported()) | |
3822 | return -EINVAL; | |
3823 | ||
3824 | memset(info, 0, sizeof(*info)); | |
3825 | ||
3826 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3827 | if (pos) | |
3828 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3829 | ||
3830 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3831 | if (pos) | |
3832 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3833 | ||
3834 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3835 | if (pos) { | |
3836 | int features; | |
3837 | ||
3838 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3839 | max_pasids = min(max_pasids, (1 << 20)); | |
3840 | ||
3841 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3842 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3843 | ||
3844 | features = pci_pasid_features(pdev); | |
3845 | if (features & PCI_PASID_CAP_EXEC) | |
3846 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3847 | if (features & PCI_PASID_CAP_PRIV) | |
3848 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3849 | } | |
3850 | ||
3851 | return 0; | |
3852 | } | |
3853 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3854 | |
3855 | #ifdef CONFIG_IRQ_REMAP | |
3856 | ||
3857 | /***************************************************************************** | |
3858 | * | |
3859 | * Interrupt Remapping Implementation | |
3860 | * | |
3861 | *****************************************************************************/ | |
3862 | ||
3863 | union irte { | |
3864 | u32 val; | |
3865 | struct { | |
3866 | u32 valid : 1, | |
3867 | no_fault : 1, | |
3868 | int_type : 3, | |
3869 | rq_eoi : 1, | |
3870 | dm : 1, | |
3871 | rsvd_1 : 1, | |
3872 | destination : 8, | |
3873 | vector : 8, | |
3874 | rsvd_2 : 8; | |
3875 | } fields; | |
3876 | }; | |
3877 | ||
3878 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3879 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3880 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3881 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3882 | ||
3883 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3884 | { | |
3885 | u64 dte; | |
3886 | ||
3887 | dte = amd_iommu_dev_table[devid].data[2]; | |
3888 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3889 | dte |= virt_to_phys(table->table); | |
3890 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3891 | dte |= DTE_IRQ_TABLE_LEN; | |
3892 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3893 | ||
3894 | amd_iommu_dev_table[devid].data[2] = dte; | |
3895 | } | |
3896 | ||
3897 | #define IRTE_ALLOCATED (~1U) | |
3898 | ||
3899 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3900 | { | |
3901 | struct irq_remap_table *table = NULL; | |
3902 | struct amd_iommu *iommu; | |
3903 | unsigned long flags; | |
3904 | u16 alias; | |
3905 | ||
3906 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3907 | ||
3908 | iommu = amd_iommu_rlookup_table[devid]; | |
3909 | if (!iommu) | |
3910 | goto out_unlock; | |
3911 | ||
3912 | table = irq_lookup_table[devid]; | |
3913 | if (table) | |
3914 | goto out; | |
3915 | ||
3916 | alias = amd_iommu_alias_table[devid]; | |
3917 | table = irq_lookup_table[alias]; | |
3918 | if (table) { | |
3919 | irq_lookup_table[devid] = table; | |
3920 | set_dte_irq_entry(devid, table); | |
3921 | iommu_flush_dte(iommu, devid); | |
3922 | goto out; | |
3923 | } | |
3924 | ||
3925 | /* Nothing there yet, allocate new irq remapping table */ | |
3926 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3927 | if (!table) | |
3928 | goto out; | |
3929 | ||
197887f0 JR |
3930 | /* Initialize table spin-lock */ |
3931 | spin_lock_init(&table->lock); | |
3932 | ||
2b324506 JR |
3933 | if (ioapic) |
3934 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3935 | table->min_index = 32; | |
3936 | ||
3937 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3938 | if (!table->table) { | |
3939 | kfree(table); | |
821f0f68 | 3940 | table = NULL; |
2b324506 JR |
3941 | goto out; |
3942 | } | |
3943 | ||
3944 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3945 | ||
3946 | if (ioapic) { | |
3947 | int i; | |
3948 | ||
3949 | for (i = 0; i < 32; ++i) | |
3950 | table->table[i] = IRTE_ALLOCATED; | |
3951 | } | |
3952 | ||
3953 | irq_lookup_table[devid] = table; | |
3954 | set_dte_irq_entry(devid, table); | |
3955 | iommu_flush_dte(iommu, devid); | |
3956 | if (devid != alias) { | |
3957 | irq_lookup_table[alias] = table; | |
3958 | set_dte_irq_entry(devid, table); | |
3959 | iommu_flush_dte(iommu, alias); | |
3960 | } | |
3961 | ||
3962 | out: | |
3963 | iommu_completion_wait(iommu); | |
3964 | ||
3965 | out_unlock: | |
3966 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3967 | ||
3968 | return table; | |
3969 | } | |
3970 | ||
3971 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3972 | { | |
3973 | struct irq_remap_table *table; | |
3974 | unsigned long flags; | |
3975 | int index, c; | |
3976 | ||
3977 | table = get_irq_table(devid, false); | |
3978 | if (!table) | |
3979 | return -ENODEV; | |
3980 | ||
3981 | spin_lock_irqsave(&table->lock, flags); | |
3982 | ||
3983 | /* Scan table for free entries */ | |
3984 | for (c = 0, index = table->min_index; | |
3985 | index < MAX_IRQS_PER_TABLE; | |
3986 | ++index) { | |
3987 | if (table->table[index] == 0) | |
3988 | c += 1; | |
3989 | else | |
3990 | c = 0; | |
3991 | ||
3992 | if (c == count) { | |
0dfedd61 | 3993 | struct irq_2_irte *irte_info; |
2b324506 JR |
3994 | |
3995 | for (; c != 0; --c) | |
3996 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3997 | ||
3998 | index -= count - 1; | |
3999 | ||
9b1b0e42 | 4000 | cfg->remapped = 1; |
0dfedd61 JR |
4001 | irte_info = &cfg->irq_2_irte; |
4002 | irte_info->devid = devid; | |
4003 | irte_info->index = index; | |
2b324506 JR |
4004 | |
4005 | goto out; | |
4006 | } | |
4007 | } | |
4008 | ||
4009 | index = -ENOSPC; | |
4010 | ||
4011 | out: | |
4012 | spin_unlock_irqrestore(&table->lock, flags); | |
4013 | ||
4014 | return index; | |
4015 | } | |
4016 | ||
4017 | static int get_irte(u16 devid, int index, union irte *irte) | |
4018 | { | |
4019 | struct irq_remap_table *table; | |
4020 | unsigned long flags; | |
4021 | ||
4022 | table = get_irq_table(devid, false); | |
4023 | if (!table) | |
4024 | return -ENOMEM; | |
4025 | ||
4026 | spin_lock_irqsave(&table->lock, flags); | |
4027 | irte->val = table->table[index]; | |
4028 | spin_unlock_irqrestore(&table->lock, flags); | |
4029 | ||
4030 | return 0; | |
4031 | } | |
4032 | ||
4033 | static int modify_irte(u16 devid, int index, union irte irte) | |
4034 | { | |
4035 | struct irq_remap_table *table; | |
4036 | struct amd_iommu *iommu; | |
4037 | unsigned long flags; | |
4038 | ||
4039 | iommu = amd_iommu_rlookup_table[devid]; | |
4040 | if (iommu == NULL) | |
4041 | return -EINVAL; | |
4042 | ||
4043 | table = get_irq_table(devid, false); | |
4044 | if (!table) | |
4045 | return -ENOMEM; | |
4046 | ||
4047 | spin_lock_irqsave(&table->lock, flags); | |
4048 | table->table[index] = irte.val; | |
4049 | spin_unlock_irqrestore(&table->lock, flags); | |
4050 | ||
4051 | iommu_flush_irt(iommu, devid); | |
4052 | iommu_completion_wait(iommu); | |
4053 | ||
4054 | return 0; | |
4055 | } | |
4056 | ||
4057 | static void free_irte(u16 devid, int index) | |
4058 | { | |
4059 | struct irq_remap_table *table; | |
4060 | struct amd_iommu *iommu; | |
4061 | unsigned long flags; | |
4062 | ||
4063 | iommu = amd_iommu_rlookup_table[devid]; | |
4064 | if (iommu == NULL) | |
4065 | return; | |
4066 | ||
4067 | table = get_irq_table(devid, false); | |
4068 | if (!table) | |
4069 | return; | |
4070 | ||
4071 | spin_lock_irqsave(&table->lock, flags); | |
4072 | table->table[index] = 0; | |
4073 | spin_unlock_irqrestore(&table->lock, flags); | |
4074 | ||
4075 | iommu_flush_irt(iommu, devid); | |
4076 | iommu_completion_wait(iommu); | |
4077 | } | |
4078 | ||
5527de74 JR |
4079 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4080 | unsigned int destination, int vector, | |
4081 | struct io_apic_irq_attr *attr) | |
4082 | { | |
4083 | struct irq_remap_table *table; | |
0dfedd61 | 4084 | struct irq_2_irte *irte_info; |
5527de74 JR |
4085 | struct irq_cfg *cfg; |
4086 | union irte irte; | |
4087 | int ioapic_id; | |
4088 | int index; | |
4089 | int devid; | |
4090 | int ret; | |
4091 | ||
4092 | cfg = irq_get_chip_data(irq); | |
4093 | if (!cfg) | |
4094 | return -EINVAL; | |
4095 | ||
0dfedd61 | 4096 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4097 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4098 | devid = get_ioapic_devid(ioapic_id); | |
4099 | ||
4100 | if (devid < 0) | |
4101 | return devid; | |
4102 | ||
4103 | table = get_irq_table(devid, true); | |
4104 | if (table == NULL) | |
4105 | return -ENOMEM; | |
4106 | ||
4107 | index = attr->ioapic_pin; | |
4108 | ||
4109 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4110 | cfg->remapped = 1; |
0dfedd61 JR |
4111 | irte_info->devid = devid; |
4112 | irte_info->index = index; | |
5527de74 JR |
4113 | |
4114 | /* Setup IRTE for IOMMU */ | |
4115 | irte.val = 0; | |
4116 | irte.fields.vector = vector; | |
4117 | irte.fields.int_type = apic->irq_delivery_mode; | |
4118 | irte.fields.destination = destination; | |
4119 | irte.fields.dm = apic->irq_dest_mode; | |
4120 | irte.fields.valid = 1; | |
4121 | ||
4122 | ret = modify_irte(devid, index, irte); | |
4123 | if (ret) | |
4124 | return ret; | |
4125 | ||
4126 | /* Setup IOAPIC entry */ | |
4127 | memset(entry, 0, sizeof(*entry)); | |
4128 | ||
4129 | entry->vector = index; | |
4130 | entry->mask = 0; | |
4131 | entry->trigger = attr->trigger; | |
4132 | entry->polarity = attr->polarity; | |
4133 | ||
4134 | /* | |
4135 | * Mask level triggered irqs. | |
5527de74 JR |
4136 | */ |
4137 | if (attr->trigger) | |
4138 | entry->mask = 1; | |
4139 | ||
4140 | return 0; | |
4141 | } | |
4142 | ||
4143 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4144 | bool force) | |
4145 | { | |
0dfedd61 | 4146 | struct irq_2_irte *irte_info; |
5527de74 JR |
4147 | unsigned int dest, irq; |
4148 | struct irq_cfg *cfg; | |
4149 | union irte irte; | |
4150 | int err; | |
4151 | ||
4152 | if (!config_enabled(CONFIG_SMP)) | |
4153 | return -1; | |
4154 | ||
4155 | cfg = data->chip_data; | |
4156 | irq = data->irq; | |
0dfedd61 | 4157 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4158 | |
4159 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4160 | return -EINVAL; | |
4161 | ||
0dfedd61 | 4162 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4163 | return -EBUSY; |
4164 | ||
4165 | if (assign_irq_vector(irq, cfg, mask)) | |
4166 | return -EBUSY; | |
4167 | ||
4168 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4169 | if (err) { | |
4170 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4171 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4172 | return err; | |
4173 | } | |
4174 | ||
4175 | irte.fields.vector = cfg->vector; | |
4176 | irte.fields.destination = dest; | |
4177 | ||
0dfedd61 | 4178 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4179 | |
4180 | if (cfg->move_in_progress) | |
4181 | send_cleanup_vector(cfg); | |
4182 | ||
4183 | cpumask_copy(data->affinity, mask); | |
4184 | ||
4185 | return 0; | |
4186 | } | |
4187 | ||
4188 | static int free_irq(int irq) | |
4189 | { | |
0dfedd61 | 4190 | struct irq_2_irte *irte_info; |
5527de74 JR |
4191 | struct irq_cfg *cfg; |
4192 | ||
4193 | cfg = irq_get_chip_data(irq); | |
4194 | if (!cfg) | |
4195 | return -EINVAL; | |
4196 | ||
0dfedd61 | 4197 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4198 | |
0dfedd61 | 4199 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4200 | |
4201 | return 0; | |
4202 | } | |
4203 | ||
0b4d48cb JR |
4204 | static void compose_msi_msg(struct pci_dev *pdev, |
4205 | unsigned int irq, unsigned int dest, | |
4206 | struct msi_msg *msg, u8 hpet_id) | |
4207 | { | |
0dfedd61 | 4208 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4209 | struct irq_cfg *cfg; |
4210 | union irte irte; | |
4211 | ||
4212 | cfg = irq_get_chip_data(irq); | |
4213 | if (!cfg) | |
4214 | return; | |
4215 | ||
0dfedd61 | 4216 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4217 | |
4218 | irte.val = 0; | |
4219 | irte.fields.vector = cfg->vector; | |
4220 | irte.fields.int_type = apic->irq_delivery_mode; | |
4221 | irte.fields.destination = dest; | |
4222 | irte.fields.dm = apic->irq_dest_mode; | |
4223 | irte.fields.valid = 1; | |
4224 | ||
0dfedd61 | 4225 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4226 | |
4227 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4228 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4229 | msg->data = irte_info->index; |
0b4d48cb JR |
4230 | } |
4231 | ||
4232 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4233 | { | |
4234 | struct irq_cfg *cfg; | |
4235 | int index; | |
4236 | u16 devid; | |
4237 | ||
4238 | if (!pdev) | |
4239 | return -EINVAL; | |
4240 | ||
4241 | cfg = irq_get_chip_data(irq); | |
4242 | if (!cfg) | |
4243 | return -EINVAL; | |
4244 | ||
4245 | devid = get_device_id(&pdev->dev); | |
4246 | index = alloc_irq_index(cfg, devid, nvec); | |
4247 | ||
4248 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4249 | } | |
4250 | ||
4251 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4252 | int index, int offset) | |
4253 | { | |
0dfedd61 | 4254 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4255 | struct irq_cfg *cfg; |
4256 | u16 devid; | |
4257 | ||
4258 | if (!pdev) | |
4259 | return -EINVAL; | |
4260 | ||
4261 | cfg = irq_get_chip_data(irq); | |
4262 | if (!cfg) | |
4263 | return -EINVAL; | |
4264 | ||
4265 | if (index >= MAX_IRQS_PER_TABLE) | |
4266 | return 0; | |
4267 | ||
4268 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4269 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4270 | |
9b1b0e42 | 4271 | cfg->remapped = 1; |
0dfedd61 JR |
4272 | irte_info->devid = devid; |
4273 | irte_info->index = index + offset; | |
0b4d48cb JR |
4274 | |
4275 | return 0; | |
4276 | } | |
4277 | ||
d976195c JR |
4278 | static int setup_hpet_msi(unsigned int irq, unsigned int id) |
4279 | { | |
0dfedd61 | 4280 | struct irq_2_irte *irte_info; |
d976195c JR |
4281 | struct irq_cfg *cfg; |
4282 | int index, devid; | |
4283 | ||
4284 | cfg = irq_get_chip_data(irq); | |
4285 | if (!cfg) | |
4286 | return -EINVAL; | |
4287 | ||
0dfedd61 | 4288 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4289 | devid = get_hpet_devid(id); |
4290 | if (devid < 0) | |
4291 | return devid; | |
4292 | ||
4293 | index = alloc_irq_index(cfg, devid, 1); | |
4294 | if (index < 0) | |
4295 | return index; | |
4296 | ||
9b1b0e42 | 4297 | cfg->remapped = 1; |
0dfedd61 JR |
4298 | irte_info->devid = devid; |
4299 | irte_info->index = index; | |
d976195c JR |
4300 | |
4301 | return 0; | |
4302 | } | |
4303 | ||
6b474b82 JR |
4304 | struct irq_remap_ops amd_iommu_irq_ops = { |
4305 | .supported = amd_iommu_supported, | |
4306 | .prepare = amd_iommu_prepare, | |
4307 | .enable = amd_iommu_enable, | |
4308 | .disable = amd_iommu_disable, | |
4309 | .reenable = amd_iommu_reenable, | |
4310 | .enable_faulting = amd_iommu_enable_faulting, | |
4311 | .setup_ioapic_entry = setup_ioapic_entry, | |
4312 | .set_affinity = set_affinity, | |
4313 | .free_irq = free_irq, | |
4314 | .compose_msi_msg = compose_msi_msg, | |
4315 | .msi_alloc_irq = msi_alloc_irq, | |
4316 | .msi_setup_irq = msi_setup_irq, | |
4317 | .setup_hpet_msi = setup_hpet_msi, | |
4318 | }; | |
2b324506 | 4319 | #endif |