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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
aa3de9c0 OBC |
47 | /* |
48 | * This bitmap is used to advertise the page sizes our hardware support | |
49 | * to the IOMMU core, which will then use this information to split | |
50 | * physically contiguous memory regions it is mapping into page sizes | |
51 | * that we support. | |
52 | * | |
53 | * Traditionally the IOMMU core just handed us the mappings directly, | |
54 | * after making sure the size is an order of a 4KiB page and that the | |
55 | * mapping has natural alignment. | |
56 | * | |
57 | * To retain this behavior, we currently advertise that we support | |
58 | * all page sizes that are an order of 4KiB. | |
59 | * | |
60 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
61 | * we could change this to advertise the real page sizes we support. | |
62 | */ | |
63 | #define AMD_IOMMU_PGSIZES (~0xFFFUL) | |
64 | ||
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
6efed63b JR |
75 | LIST_HEAD(ioapic_map); |
76 | LIST_HEAD(hpet_map); | |
77 | ||
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
82 | static struct protection_domain *pt_domain; | |
83 | ||
26961efe | 84 | static struct iommu_ops amd_iommu_ops; |
26961efe | 85 | |
72e1dcc4 | 86 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 87 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 88 | |
ac1534a5 JR |
89 | static struct dma_map_ops amd_iommu_dma_ops; |
90 | ||
431b2a20 JR |
91 | /* |
92 | * general struct to manage commands send to an IOMMU | |
93 | */ | |
d6449536 | 94 | struct iommu_cmd { |
b6c02715 JR |
95 | u32 data[4]; |
96 | }; | |
97 | ||
05152a04 JR |
98 | struct kmem_cache *amd_iommu_irq_cache; |
99 | ||
04bfdd84 | 100 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 101 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 102 | |
15898bbc JR |
103 | /**************************************************************************** |
104 | * | |
105 | * Helper functions | |
106 | * | |
107 | ****************************************************************************/ | |
108 | ||
f62dda66 | 109 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
110 | { |
111 | struct iommu_dev_data *dev_data; | |
112 | unsigned long flags; | |
113 | ||
114 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
115 | if (!dev_data) | |
116 | return NULL; | |
117 | ||
f62dda66 | 118 | dev_data->devid = devid; |
8fa5f802 JR |
119 | atomic_set(&dev_data->bind, 0); |
120 | ||
121 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
122 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
123 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
124 | ||
125 | return dev_data; | |
126 | } | |
127 | ||
128 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
133 | list_del(&dev_data->dev_data_list); | |
134 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
135 | ||
136 | kfree(dev_data); | |
137 | } | |
138 | ||
3b03bb74 JR |
139 | static struct iommu_dev_data *search_dev_data(u16 devid) |
140 | { | |
141 | struct iommu_dev_data *dev_data; | |
142 | unsigned long flags; | |
143 | ||
144 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
145 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
146 | if (dev_data->devid == devid) | |
147 | goto out_unlock; | |
148 | } | |
149 | ||
150 | dev_data = NULL; | |
151 | ||
152 | out_unlock: | |
153 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
154 | ||
155 | return dev_data; | |
156 | } | |
157 | ||
158 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
159 | { | |
160 | struct iommu_dev_data *dev_data; | |
161 | ||
162 | dev_data = search_dev_data(devid); | |
163 | ||
164 | if (dev_data == NULL) | |
165 | dev_data = alloc_dev_data(devid); | |
166 | ||
167 | return dev_data; | |
168 | } | |
169 | ||
15898bbc JR |
170 | static inline u16 get_device_id(struct device *dev) |
171 | { | |
172 | struct pci_dev *pdev = to_pci_dev(dev); | |
173 | ||
174 | return calc_devid(pdev->bus->number, pdev->devfn); | |
175 | } | |
176 | ||
657cbb6b JR |
177 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
178 | { | |
179 | return dev->archdata.iommu; | |
180 | } | |
181 | ||
5abcdba4 JR |
182 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
183 | { | |
184 | static const int caps[] = { | |
185 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
186 | PCI_EXT_CAP_ID_PRI, |
187 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
188 | }; |
189 | int i, pos; | |
190 | ||
191 | for (i = 0; i < 3; ++i) { | |
192 | pos = pci_find_ext_capability(pdev, caps[i]); | |
193 | if (pos == 0) | |
194 | return false; | |
195 | } | |
196 | ||
197 | return true; | |
198 | } | |
199 | ||
6a113ddc JR |
200 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
201 | { | |
202 | struct iommu_dev_data *dev_data; | |
203 | ||
204 | dev_data = get_dev_data(&pdev->dev); | |
205 | ||
206 | return dev_data->errata & (1 << erratum) ? true : false; | |
207 | } | |
208 | ||
71c70984 JR |
209 | /* |
210 | * In this function the list of preallocated protection domains is traversed to | |
211 | * find the domain for a specific device | |
212 | */ | |
213 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
214 | { | |
215 | struct dma_ops_domain *entry, *ret = NULL; | |
216 | unsigned long flags; | |
217 | u16 alias = amd_iommu_alias_table[devid]; | |
218 | ||
219 | if (list_empty(&iommu_pd_list)) | |
220 | return NULL; | |
221 | ||
222 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
223 | ||
224 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
225 | if (entry->target_dev == devid || | |
226 | entry->target_dev == alias) { | |
227 | ret = entry; | |
228 | break; | |
229 | } | |
230 | } | |
231 | ||
232 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
233 | ||
234 | return ret; | |
235 | } | |
236 | ||
98fc5a69 JR |
237 | /* |
238 | * This function checks if the driver got a valid device from the caller to | |
239 | * avoid dereferencing invalid pointers. | |
240 | */ | |
241 | static bool check_device(struct device *dev) | |
242 | { | |
243 | u16 devid; | |
244 | ||
245 | if (!dev || !dev->dma_mask) | |
246 | return false; | |
247 | ||
248 | /* No device or no PCI device */ | |
339d3261 | 249 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
250 | return false; |
251 | ||
252 | devid = get_device_id(dev); | |
253 | ||
254 | /* Out of our scope? */ | |
255 | if (devid > amd_iommu_last_bdf) | |
256 | return false; | |
257 | ||
258 | if (amd_iommu_rlookup_table[devid] == NULL) | |
259 | return false; | |
260 | ||
261 | return true; | |
262 | } | |
263 | ||
664b6003 AW |
264 | static void swap_pci_ref(struct pci_dev **from, struct pci_dev *to) |
265 | { | |
266 | pci_dev_put(*from); | |
267 | *from = to; | |
268 | } | |
269 | ||
270 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) | |
271 | ||
657cbb6b JR |
272 | static int iommu_init_device(struct device *dev) |
273 | { | |
9dcd6130 | 274 | struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); |
657cbb6b | 275 | struct iommu_dev_data *dev_data; |
9dcd6130 | 276 | struct iommu_group *group; |
8fa5f802 | 277 | u16 alias; |
9dcd6130 | 278 | int ret; |
657cbb6b JR |
279 | |
280 | if (dev->archdata.iommu) | |
281 | return 0; | |
282 | ||
3b03bb74 | 283 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
284 | if (!dev_data) |
285 | return -ENOMEM; | |
286 | ||
f62dda66 | 287 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 288 | if (alias != dev_data->devid) { |
71f77580 | 289 | struct iommu_dev_data *alias_data; |
b00d3bcf | 290 | |
71f77580 JR |
291 | alias_data = find_dev_data(alias); |
292 | if (alias_data == NULL) { | |
293 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
294 | dev_name(dev)); | |
2b02b091 JR |
295 | free_dev_data(dev_data); |
296 | return -ENOTSUPP; | |
297 | } | |
71f77580 | 298 | dev_data->alias_data = alias_data; |
9dcd6130 AW |
299 | |
300 | dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); | |
301 | } else | |
302 | dma_pdev = pci_dev_get(pdev); | |
303 | ||
31fe9435 | 304 | /* Account for quirked devices */ |
664b6003 AW |
305 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
306 | ||
31fe9435 AW |
307 | /* |
308 | * If it's a multifunction device that does not support our | |
309 | * required ACS flags, add to the same group as function 0. | |
310 | */ | |
664b6003 AW |
311 | if (dma_pdev->multifunction && |
312 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) | |
313 | swap_pci_ref(&dma_pdev, | |
314 | pci_get_slot(dma_pdev->bus, | |
315 | PCI_DEVFN(PCI_SLOT(dma_pdev->devfn), | |
316 | 0))); | |
317 | ||
31fe9435 AW |
318 | /* |
319 | * Devices on the root bus go through the iommu. If that's not us, | |
320 | * find the next upstream device and test ACS up to the root bus. | |
321 | * Finding the next device may require skipping virtual buses. | |
322 | */ | |
664b6003 | 323 | while (!pci_is_root_bus(dma_pdev->bus)) { |
31fe9435 AW |
324 | struct pci_bus *bus = dma_pdev->bus; |
325 | ||
326 | while (!bus->self) { | |
327 | if (!pci_is_root_bus(bus)) | |
328 | bus = bus->parent; | |
329 | else | |
330 | goto root_bus; | |
331 | } | |
332 | ||
333 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
664b6003 AW |
334 | break; |
335 | ||
31fe9435 | 336 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
664b6003 AW |
337 | } |
338 | ||
31fe9435 | 339 | root_bus: |
9dcd6130 AW |
340 | group = iommu_group_get(&dma_pdev->dev); |
341 | pci_dev_put(dma_pdev); | |
342 | if (!group) { | |
343 | group = iommu_group_alloc(); | |
344 | if (IS_ERR(group)) | |
345 | return PTR_ERR(group); | |
26018874 | 346 | } |
657cbb6b | 347 | |
9dcd6130 AW |
348 | ret = iommu_group_add_device(group, dev); |
349 | ||
350 | iommu_group_put(group); | |
351 | ||
352 | if (ret) | |
353 | return ret; | |
354 | ||
5abcdba4 JR |
355 | if (pci_iommuv2_capable(pdev)) { |
356 | struct amd_iommu *iommu; | |
357 | ||
358 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
359 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
360 | } | |
361 | ||
657cbb6b JR |
362 | dev->archdata.iommu = dev_data; |
363 | ||
657cbb6b JR |
364 | return 0; |
365 | } | |
366 | ||
26018874 JR |
367 | static void iommu_ignore_device(struct device *dev) |
368 | { | |
369 | u16 devid, alias; | |
370 | ||
371 | devid = get_device_id(dev); | |
372 | alias = amd_iommu_alias_table[devid]; | |
373 | ||
374 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
375 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
376 | ||
377 | amd_iommu_rlookup_table[devid] = NULL; | |
378 | amd_iommu_rlookup_table[alias] = NULL; | |
379 | } | |
380 | ||
657cbb6b JR |
381 | static void iommu_uninit_device(struct device *dev) |
382 | { | |
9dcd6130 AW |
383 | iommu_group_remove_device(dev); |
384 | ||
8fa5f802 JR |
385 | /* |
386 | * Nothing to do here - we keep dev_data around for unplugged devices | |
387 | * and reuse it when the device is re-plugged - not doing so would | |
388 | * introduce a ton of races. | |
389 | */ | |
657cbb6b | 390 | } |
b7cc9554 JR |
391 | |
392 | void __init amd_iommu_uninit_devices(void) | |
393 | { | |
8fa5f802 | 394 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
395 | struct pci_dev *pdev = NULL; |
396 | ||
397 | for_each_pci_dev(pdev) { | |
398 | ||
399 | if (!check_device(&pdev->dev)) | |
400 | continue; | |
401 | ||
402 | iommu_uninit_device(&pdev->dev); | |
403 | } | |
8fa5f802 JR |
404 | |
405 | /* Free all of our dev_data structures */ | |
406 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
407 | free_dev_data(dev_data); | |
b7cc9554 JR |
408 | } |
409 | ||
410 | int __init amd_iommu_init_devices(void) | |
411 | { | |
412 | struct pci_dev *pdev = NULL; | |
413 | int ret = 0; | |
414 | ||
415 | for_each_pci_dev(pdev) { | |
416 | ||
417 | if (!check_device(&pdev->dev)) | |
418 | continue; | |
419 | ||
420 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
421 | if (ret == -ENOTSUPP) |
422 | iommu_ignore_device(&pdev->dev); | |
423 | else if (ret) | |
b7cc9554 JR |
424 | goto out_free; |
425 | } | |
426 | ||
427 | return 0; | |
428 | ||
429 | out_free: | |
430 | ||
431 | amd_iommu_uninit_devices(); | |
432 | ||
433 | return ret; | |
434 | } | |
7f26508b JR |
435 | #ifdef CONFIG_AMD_IOMMU_STATS |
436 | ||
437 | /* | |
438 | * Initialization code for statistics collection | |
439 | */ | |
440 | ||
da49f6df | 441 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 442 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 443 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 444 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 445 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 446 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 447 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 448 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 449 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 450 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 451 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 452 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
453 | DECLARE_STATS_COUNTER(complete_ppr); |
454 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
455 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
456 | DECLARE_STATS_COUNTER(pri_requests); | |
457 | ||
7f26508b | 458 | static struct dentry *stats_dir; |
7f26508b JR |
459 | static struct dentry *de_fflush; |
460 | ||
461 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
462 | { | |
463 | if (stats_dir == NULL) | |
464 | return; | |
465 | ||
466 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
467 | &cnt->value); | |
468 | } | |
469 | ||
470 | static void amd_iommu_stats_init(void) | |
471 | { | |
472 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
473 | if (stats_dir == NULL) | |
474 | return; | |
475 | ||
7f26508b | 476 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 477 | &amd_iommu_unmap_flush); |
da49f6df JR |
478 | |
479 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 480 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 481 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 482 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 483 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 484 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 485 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 486 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 487 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 488 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 489 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 490 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
491 | amd_iommu_stats_add(&complete_ppr); |
492 | amd_iommu_stats_add(&invalidate_iotlb); | |
493 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
494 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
495 | } |
496 | ||
497 | #endif | |
498 | ||
a80dc3e0 JR |
499 | /**************************************************************************** |
500 | * | |
501 | * Interrupt handling functions | |
502 | * | |
503 | ****************************************************************************/ | |
504 | ||
e3e59876 JR |
505 | static void dump_dte_entry(u16 devid) |
506 | { | |
507 | int i; | |
508 | ||
ee6c2868 JR |
509 | for (i = 0; i < 4; ++i) |
510 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
511 | amd_iommu_dev_table[devid].data[i]); |
512 | } | |
513 | ||
945b4ac4 JR |
514 | static void dump_command(unsigned long phys_addr) |
515 | { | |
516 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
517 | int i; | |
518 | ||
519 | for (i = 0; i < 4; ++i) | |
520 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
521 | } | |
522 | ||
a345b23b | 523 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 524 | { |
3d06fca8 JR |
525 | int type, devid, domid, flags; |
526 | volatile u32 *event = __evt; | |
527 | int count = 0; | |
528 | u64 address; | |
529 | ||
530 | retry: | |
531 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
532 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
533 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
534 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
535 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
536 | ||
537 | if (type == 0) { | |
538 | /* Did we hit the erratum? */ | |
539 | if (++count == LOOP_TIMEOUT) { | |
540 | pr_err("AMD-Vi: No event written to event log\n"); | |
541 | return; | |
542 | } | |
543 | udelay(1); | |
544 | goto retry; | |
545 | } | |
90008ee4 | 546 | |
4c6f40d4 | 547 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
548 | |
549 | switch (type) { | |
550 | case EVENT_TYPE_ILL_DEV: | |
551 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
552 | "address=0x%016llx flags=0x%04x]\n", | |
553 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
554 | address, flags); | |
e3e59876 | 555 | dump_dte_entry(devid); |
90008ee4 JR |
556 | break; |
557 | case EVENT_TYPE_IO_FAULT: | |
558 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
559 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
560 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
561 | domid, address, flags); | |
562 | break; | |
563 | case EVENT_TYPE_DEV_TAB_ERR: | |
564 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
565 | "address=0x%016llx flags=0x%04x]\n", | |
566 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
567 | address, flags); | |
568 | break; | |
569 | case EVENT_TYPE_PAGE_TAB_ERR: | |
570 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
571 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
572 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
573 | domid, address, flags); | |
574 | break; | |
575 | case EVENT_TYPE_ILL_CMD: | |
576 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 577 | dump_command(address); |
90008ee4 JR |
578 | break; |
579 | case EVENT_TYPE_CMD_HARD_ERR: | |
580 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
581 | "flags=0x%04x]\n", address, flags); | |
582 | break; | |
583 | case EVENT_TYPE_IOTLB_INV_TO: | |
584 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
585 | "address=0x%016llx]\n", | |
586 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
587 | address); | |
588 | break; | |
589 | case EVENT_TYPE_INV_DEV_REQ: | |
590 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
591 | "address=0x%016llx flags=0x%04x]\n", | |
592 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
593 | address, flags); | |
594 | break; | |
595 | default: | |
596 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
597 | } | |
3d06fca8 JR |
598 | |
599 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
600 | } |
601 | ||
602 | static void iommu_poll_events(struct amd_iommu *iommu) | |
603 | { | |
604 | u32 head, tail; | |
605 | unsigned long flags; | |
606 | ||
607 | spin_lock_irqsave(&iommu->lock, flags); | |
608 | ||
609 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
610 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
611 | ||
612 | while (head != tail) { | |
a345b23b | 613 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
614 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
615 | } | |
616 | ||
617 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
618 | ||
619 | spin_unlock_irqrestore(&iommu->lock, flags); | |
620 | } | |
621 | ||
eee53537 | 622 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
623 | { |
624 | struct amd_iommu_fault fault; | |
72e1dcc4 | 625 | |
399be2f5 JR |
626 | INC_STATS_COUNTER(pri_requests); |
627 | ||
72e1dcc4 JR |
628 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
629 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
630 | return; | |
631 | } | |
632 | ||
633 | fault.address = raw[1]; | |
634 | fault.pasid = PPR_PASID(raw[0]); | |
635 | fault.device_id = PPR_DEVID(raw[0]); | |
636 | fault.tag = PPR_TAG(raw[0]); | |
637 | fault.flags = PPR_FLAGS(raw[0]); | |
638 | ||
72e1dcc4 JR |
639 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
640 | } | |
641 | ||
642 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
643 | { | |
644 | unsigned long flags; | |
645 | u32 head, tail; | |
646 | ||
647 | if (iommu->ppr_log == NULL) | |
648 | return; | |
649 | ||
eee53537 JR |
650 | /* enable ppr interrupts again */ |
651 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
652 | ||
72e1dcc4 JR |
653 | spin_lock_irqsave(&iommu->lock, flags); |
654 | ||
655 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
656 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
657 | ||
658 | while (head != tail) { | |
eee53537 JR |
659 | volatile u64 *raw; |
660 | u64 entry[2]; | |
661 | int i; | |
662 | ||
663 | raw = (u64 *)(iommu->ppr_log + head); | |
664 | ||
665 | /* | |
666 | * Hardware bug: Interrupt may arrive before the entry is | |
667 | * written to memory. If this happens we need to wait for the | |
668 | * entry to arrive. | |
669 | */ | |
670 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
671 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
672 | break; | |
673 | udelay(1); | |
674 | } | |
72e1dcc4 | 675 | |
eee53537 JR |
676 | /* Avoid memcpy function-call overhead */ |
677 | entry[0] = raw[0]; | |
678 | entry[1] = raw[1]; | |
72e1dcc4 | 679 | |
eee53537 JR |
680 | /* |
681 | * To detect the hardware bug we need to clear the entry | |
682 | * back to zero. | |
683 | */ | |
684 | raw[0] = raw[1] = 0UL; | |
685 | ||
686 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
687 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
688 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 JR |
689 | |
690 | /* | |
691 | * Release iommu->lock because ppr-handling might need to | |
692 | * re-aquire it | |
693 | */ | |
694 | spin_unlock_irqrestore(&iommu->lock, flags); | |
695 | ||
696 | /* Handle PPR entry */ | |
697 | iommu_handle_ppr_entry(iommu, entry); | |
698 | ||
699 | spin_lock_irqsave(&iommu->lock, flags); | |
700 | ||
701 | /* Refresh ring-buffer information */ | |
702 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
703 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
704 | } | |
705 | ||
72e1dcc4 JR |
706 | spin_unlock_irqrestore(&iommu->lock, flags); |
707 | } | |
708 | ||
72fe00f0 | 709 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 710 | { |
90008ee4 JR |
711 | struct amd_iommu *iommu; |
712 | ||
72e1dcc4 | 713 | for_each_iommu(iommu) { |
90008ee4 | 714 | iommu_poll_events(iommu); |
72e1dcc4 JR |
715 | iommu_poll_ppr_log(iommu); |
716 | } | |
90008ee4 JR |
717 | |
718 | return IRQ_HANDLED; | |
a80dc3e0 JR |
719 | } |
720 | ||
72fe00f0 JR |
721 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
722 | { | |
723 | return IRQ_WAKE_THREAD; | |
724 | } | |
725 | ||
431b2a20 JR |
726 | /**************************************************************************** |
727 | * | |
728 | * IOMMU command queuing functions | |
729 | * | |
730 | ****************************************************************************/ | |
731 | ||
ac0ea6e9 JR |
732 | static int wait_on_sem(volatile u64 *sem) |
733 | { | |
734 | int i = 0; | |
735 | ||
736 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
737 | udelay(1); | |
738 | i += 1; | |
739 | } | |
740 | ||
741 | if (i == LOOP_TIMEOUT) { | |
742 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
743 | return -EIO; | |
744 | } | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
749 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
750 | struct iommu_cmd *cmd, | |
751 | u32 tail) | |
a19ae1ec | 752 | { |
a19ae1ec JR |
753 | u8 *target; |
754 | ||
8a7c5ef3 | 755 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
756 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
757 | ||
758 | /* Copy command to buffer */ | |
759 | memcpy(target, cmd, sizeof(*cmd)); | |
760 | ||
761 | /* Tell the IOMMU about it */ | |
a19ae1ec | 762 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 763 | } |
a19ae1ec | 764 | |
815b33fd | 765 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 766 | { |
815b33fd JR |
767 | WARN_ON(address & 0x7ULL); |
768 | ||
ded46737 | 769 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
770 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
771 | cmd->data[1] = upper_32_bits(__pa(address)); | |
772 | cmd->data[2] = 1; | |
ded46737 JR |
773 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
774 | } | |
775 | ||
94fe79e2 JR |
776 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
777 | { | |
778 | memset(cmd, 0, sizeof(*cmd)); | |
779 | cmd->data[0] = devid; | |
780 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
781 | } | |
782 | ||
11b6402c JR |
783 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
784 | size_t size, u16 domid, int pde) | |
785 | { | |
786 | u64 pages; | |
787 | int s; | |
788 | ||
789 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
790 | s = 0; | |
791 | ||
792 | if (pages > 1) { | |
793 | /* | |
794 | * If we have to flush more than one page, flush all | |
795 | * TLB entries for this domain | |
796 | */ | |
797 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
798 | s = 1; | |
799 | } | |
800 | ||
801 | address &= PAGE_MASK; | |
802 | ||
803 | memset(cmd, 0, sizeof(*cmd)); | |
804 | cmd->data[1] |= domid; | |
805 | cmd->data[2] = lower_32_bits(address); | |
806 | cmd->data[3] = upper_32_bits(address); | |
807 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
808 | if (s) /* size bit - we flush more than one 4kb page */ | |
809 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
810 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
811 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
812 | } | |
813 | ||
cb41ed85 JR |
814 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
815 | u64 address, size_t size) | |
816 | { | |
817 | u64 pages; | |
818 | int s; | |
819 | ||
820 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
821 | s = 0; | |
822 | ||
823 | if (pages > 1) { | |
824 | /* | |
825 | * If we have to flush more than one page, flush all | |
826 | * TLB entries for this domain | |
827 | */ | |
828 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
829 | s = 1; | |
830 | } | |
831 | ||
832 | address &= PAGE_MASK; | |
833 | ||
834 | memset(cmd, 0, sizeof(*cmd)); | |
835 | cmd->data[0] = devid; | |
836 | cmd->data[0] |= (qdep & 0xff) << 24; | |
837 | cmd->data[1] = devid; | |
838 | cmd->data[2] = lower_32_bits(address); | |
839 | cmd->data[3] = upper_32_bits(address); | |
840 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
841 | if (s) | |
842 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
843 | } | |
844 | ||
22e266c7 JR |
845 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
846 | u64 address, bool size) | |
847 | { | |
848 | memset(cmd, 0, sizeof(*cmd)); | |
849 | ||
850 | address &= ~(0xfffULL); | |
851 | ||
852 | cmd->data[0] = pasid & PASID_MASK; | |
853 | cmd->data[1] = domid; | |
854 | cmd->data[2] = lower_32_bits(address); | |
855 | cmd->data[3] = upper_32_bits(address); | |
856 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
857 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
858 | if (size) | |
859 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
860 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
861 | } | |
862 | ||
863 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
864 | int qdep, u64 address, bool size) | |
865 | { | |
866 | memset(cmd, 0, sizeof(*cmd)); | |
867 | ||
868 | address &= ~(0xfffULL); | |
869 | ||
870 | cmd->data[0] = devid; | |
871 | cmd->data[0] |= (pasid & 0xff) << 16; | |
872 | cmd->data[0] |= (qdep & 0xff) << 24; | |
873 | cmd->data[1] = devid; | |
874 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
875 | cmd->data[2] = lower_32_bits(address); | |
876 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
877 | cmd->data[3] = upper_32_bits(address); | |
878 | if (size) | |
879 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
880 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
881 | } | |
882 | ||
c99afa25 JR |
883 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
884 | int status, int tag, bool gn) | |
885 | { | |
886 | memset(cmd, 0, sizeof(*cmd)); | |
887 | ||
888 | cmd->data[0] = devid; | |
889 | if (gn) { | |
890 | cmd->data[1] = pasid & PASID_MASK; | |
891 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
892 | } | |
893 | cmd->data[3] = tag & 0x1ff; | |
894 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
895 | ||
896 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
897 | } | |
898 | ||
58fc7f14 JR |
899 | static void build_inv_all(struct iommu_cmd *cmd) |
900 | { | |
901 | memset(cmd, 0, sizeof(*cmd)); | |
902 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
903 | } |
904 | ||
7ef2798d JR |
905 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
906 | { | |
907 | memset(cmd, 0, sizeof(*cmd)); | |
908 | cmd->data[0] = devid; | |
909 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
910 | } | |
911 | ||
431b2a20 | 912 | /* |
431b2a20 | 913 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 914 | * hardware about the new command. |
431b2a20 | 915 | */ |
f1ca1512 JR |
916 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
917 | struct iommu_cmd *cmd, | |
918 | bool sync) | |
a19ae1ec | 919 | { |
ac0ea6e9 | 920 | u32 left, tail, head, next_tail; |
a19ae1ec | 921 | unsigned long flags; |
a19ae1ec | 922 | |
549c90dc | 923 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
924 | |
925 | again: | |
a19ae1ec | 926 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 927 | |
ac0ea6e9 JR |
928 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
929 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
930 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
931 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 932 | |
ac0ea6e9 JR |
933 | if (left <= 2) { |
934 | struct iommu_cmd sync_cmd; | |
935 | volatile u64 sem = 0; | |
936 | int ret; | |
8d201968 | 937 | |
ac0ea6e9 JR |
938 | build_completion_wait(&sync_cmd, (u64)&sem); |
939 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 940 | |
ac0ea6e9 JR |
941 | spin_unlock_irqrestore(&iommu->lock, flags); |
942 | ||
943 | if ((ret = wait_on_sem(&sem)) != 0) | |
944 | return ret; | |
945 | ||
946 | goto again; | |
8d201968 JR |
947 | } |
948 | ||
ac0ea6e9 JR |
949 | copy_cmd_to_buffer(iommu, cmd, tail); |
950 | ||
951 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 952 | iommu->need_sync = sync; |
ac0ea6e9 | 953 | |
a19ae1ec | 954 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 955 | |
815b33fd | 956 | return 0; |
8d201968 JR |
957 | } |
958 | ||
f1ca1512 JR |
959 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
960 | { | |
961 | return iommu_queue_command_sync(iommu, cmd, true); | |
962 | } | |
963 | ||
8d201968 JR |
964 | /* |
965 | * This function queues a completion wait command into the command | |
966 | * buffer of an IOMMU | |
967 | */ | |
a19ae1ec | 968 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
969 | { |
970 | struct iommu_cmd cmd; | |
815b33fd | 971 | volatile u64 sem = 0; |
ac0ea6e9 | 972 | int ret; |
8d201968 | 973 | |
09ee17eb | 974 | if (!iommu->need_sync) |
815b33fd | 975 | return 0; |
09ee17eb | 976 | |
815b33fd | 977 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 978 | |
f1ca1512 | 979 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 980 | if (ret) |
815b33fd | 981 | return ret; |
8d201968 | 982 | |
ac0ea6e9 | 983 | return wait_on_sem(&sem); |
8d201968 JR |
984 | } |
985 | ||
d8c13085 | 986 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 987 | { |
d8c13085 | 988 | struct iommu_cmd cmd; |
a19ae1ec | 989 | |
d8c13085 | 990 | build_inv_dte(&cmd, devid); |
7e4f88da | 991 | |
d8c13085 JR |
992 | return iommu_queue_command(iommu, &cmd); |
993 | } | |
09ee17eb | 994 | |
7d0c5cc5 JR |
995 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
996 | { | |
997 | u32 devid; | |
09ee17eb | 998 | |
7d0c5cc5 JR |
999 | for (devid = 0; devid <= 0xffff; ++devid) |
1000 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1001 | |
7d0c5cc5 JR |
1002 | iommu_completion_wait(iommu); |
1003 | } | |
84df8175 | 1004 | |
7d0c5cc5 JR |
1005 | /* |
1006 | * This function uses heavy locking and may disable irqs for some time. But | |
1007 | * this is no issue because it is only called during resume. | |
1008 | */ | |
1009 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1010 | { | |
1011 | u32 dom_id; | |
a19ae1ec | 1012 | |
7d0c5cc5 JR |
1013 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1014 | struct iommu_cmd cmd; | |
1015 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1016 | dom_id, 1); | |
1017 | iommu_queue_command(iommu, &cmd); | |
1018 | } | |
8eed9833 | 1019 | |
7d0c5cc5 | 1020 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1021 | } |
1022 | ||
58fc7f14 | 1023 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1024 | { |
58fc7f14 | 1025 | struct iommu_cmd cmd; |
0518a3a4 | 1026 | |
58fc7f14 | 1027 | build_inv_all(&cmd); |
0518a3a4 | 1028 | |
58fc7f14 JR |
1029 | iommu_queue_command(iommu, &cmd); |
1030 | iommu_completion_wait(iommu); | |
1031 | } | |
1032 | ||
7ef2798d JR |
1033 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1034 | { | |
1035 | struct iommu_cmd cmd; | |
1036 | ||
1037 | build_inv_irt(&cmd, devid); | |
1038 | ||
1039 | iommu_queue_command(iommu, &cmd); | |
1040 | } | |
1041 | ||
1042 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1043 | { | |
1044 | u32 devid; | |
1045 | ||
1046 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1047 | iommu_flush_irt(iommu, devid); | |
1048 | ||
1049 | iommu_completion_wait(iommu); | |
1050 | } | |
1051 | ||
7d0c5cc5 JR |
1052 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1053 | { | |
58fc7f14 JR |
1054 | if (iommu_feature(iommu, FEATURE_IA)) { |
1055 | iommu_flush_all(iommu); | |
1056 | } else { | |
1057 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1058 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1059 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1060 | } |
1061 | } | |
1062 | ||
431b2a20 | 1063 | /* |
cb41ed85 | 1064 | * Command send function for flushing on-device TLB |
431b2a20 | 1065 | */ |
6c542047 JR |
1066 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1067 | u64 address, size_t size) | |
3fa43655 JR |
1068 | { |
1069 | struct amd_iommu *iommu; | |
b00d3bcf | 1070 | struct iommu_cmd cmd; |
cb41ed85 | 1071 | int qdep; |
3fa43655 | 1072 | |
ea61cddb JR |
1073 | qdep = dev_data->ats.qdep; |
1074 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1075 | |
ea61cddb | 1076 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1077 | |
1078 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1079 | } |
1080 | ||
431b2a20 | 1081 | /* |
431b2a20 | 1082 | * Command send function for invalidating a device table entry |
431b2a20 | 1083 | */ |
6c542047 | 1084 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1085 | { |
3fa43655 | 1086 | struct amd_iommu *iommu; |
ee2fa743 | 1087 | int ret; |
a19ae1ec | 1088 | |
6c542047 | 1089 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1090 | |
f62dda66 | 1091 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1092 | if (ret) |
1093 | return ret; | |
1094 | ||
ea61cddb | 1095 | if (dev_data->ats.enabled) |
6c542047 | 1096 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1097 | |
ee2fa743 | 1098 | return ret; |
a19ae1ec JR |
1099 | } |
1100 | ||
431b2a20 JR |
1101 | /* |
1102 | * TLB invalidation function which is called from the mapping functions. | |
1103 | * It invalidates a single PTE if the range to flush is within a single | |
1104 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1105 | */ | |
17b124bf JR |
1106 | static void __domain_flush_pages(struct protection_domain *domain, |
1107 | u64 address, size_t size, int pde) | |
a19ae1ec | 1108 | { |
cb41ed85 | 1109 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1110 | struct iommu_cmd cmd; |
1111 | int ret = 0, i; | |
a19ae1ec | 1112 | |
11b6402c | 1113 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1114 | |
6de8ad9b JR |
1115 | for (i = 0; i < amd_iommus_present; ++i) { |
1116 | if (!domain->dev_iommu[i]) | |
1117 | continue; | |
1118 | ||
1119 | /* | |
1120 | * Devices of this domain are behind this IOMMU | |
1121 | * We need a TLB flush | |
1122 | */ | |
11b6402c | 1123 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1124 | } |
1125 | ||
cb41ed85 | 1126 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1127 | |
ea61cddb | 1128 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1129 | continue; |
1130 | ||
6c542047 | 1131 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1132 | } |
1133 | ||
11b6402c | 1134 | WARN_ON(ret); |
6de8ad9b JR |
1135 | } |
1136 | ||
17b124bf JR |
1137 | static void domain_flush_pages(struct protection_domain *domain, |
1138 | u64 address, size_t size) | |
6de8ad9b | 1139 | { |
17b124bf | 1140 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1141 | } |
b6c02715 | 1142 | |
1c655773 | 1143 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1144 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1145 | { |
17b124bf | 1146 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1147 | } |
1148 | ||
42a49f96 | 1149 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1150 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1151 | { |
17b124bf | 1152 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1153 | } |
1154 | ||
17b124bf | 1155 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1156 | { |
17b124bf | 1157 | int i; |
18811f55 | 1158 | |
17b124bf JR |
1159 | for (i = 0; i < amd_iommus_present; ++i) { |
1160 | if (!domain->dev_iommu[i]) | |
1161 | continue; | |
bfd1be18 | 1162 | |
17b124bf JR |
1163 | /* |
1164 | * Devices of this domain are behind this IOMMU | |
1165 | * We need to wait for completion of all commands. | |
1166 | */ | |
1167 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1168 | } |
e394d72a JR |
1169 | } |
1170 | ||
b00d3bcf | 1171 | |
09b42804 | 1172 | /* |
b00d3bcf | 1173 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1174 | */ |
17b124bf | 1175 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1176 | { |
b00d3bcf | 1177 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1178 | |
b00d3bcf | 1179 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1180 | device_flush_dte(dev_data); |
a345b23b JR |
1181 | } |
1182 | ||
431b2a20 JR |
1183 | /**************************************************************************** |
1184 | * | |
1185 | * The functions below are used the create the page table mappings for | |
1186 | * unity mapped regions. | |
1187 | * | |
1188 | ****************************************************************************/ | |
1189 | ||
308973d3 JR |
1190 | /* |
1191 | * This function is used to add another level to an IO page table. Adding | |
1192 | * another level increases the size of the address space by 9 bits to a size up | |
1193 | * to 64 bits. | |
1194 | */ | |
1195 | static bool increase_address_space(struct protection_domain *domain, | |
1196 | gfp_t gfp) | |
1197 | { | |
1198 | u64 *pte; | |
1199 | ||
1200 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1201 | /* address space already 64 bit large */ | |
1202 | return false; | |
1203 | ||
1204 | pte = (void *)get_zeroed_page(gfp); | |
1205 | if (!pte) | |
1206 | return false; | |
1207 | ||
1208 | *pte = PM_LEVEL_PDE(domain->mode, | |
1209 | virt_to_phys(domain->pt_root)); | |
1210 | domain->pt_root = pte; | |
1211 | domain->mode += 1; | |
1212 | domain->updated = true; | |
1213 | ||
1214 | return true; | |
1215 | } | |
1216 | ||
1217 | static u64 *alloc_pte(struct protection_domain *domain, | |
1218 | unsigned long address, | |
cbb9d729 | 1219 | unsigned long page_size, |
308973d3 JR |
1220 | u64 **pte_page, |
1221 | gfp_t gfp) | |
1222 | { | |
cbb9d729 | 1223 | int level, end_lvl; |
308973d3 | 1224 | u64 *pte, *page; |
cbb9d729 JR |
1225 | |
1226 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1227 | |
1228 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1229 | increase_address_space(domain, gfp); | |
1230 | ||
cbb9d729 JR |
1231 | level = domain->mode - 1; |
1232 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1233 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1234 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1235 | |
1236 | while (level > end_lvl) { | |
1237 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1238 | page = (u64 *)get_zeroed_page(gfp); | |
1239 | if (!page) | |
1240 | return NULL; | |
1241 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1242 | } | |
1243 | ||
cbb9d729 JR |
1244 | /* No level skipping support yet */ |
1245 | if (PM_PTE_LEVEL(*pte) != level) | |
1246 | return NULL; | |
1247 | ||
308973d3 JR |
1248 | level -= 1; |
1249 | ||
1250 | pte = IOMMU_PTE_PAGE(*pte); | |
1251 | ||
1252 | if (pte_page && level == end_lvl) | |
1253 | *pte_page = pte; | |
1254 | ||
1255 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1256 | } | |
1257 | ||
1258 | return pte; | |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * This function checks if there is a PTE for a given dma address. If | |
1263 | * there is one, it returns the pointer to it. | |
1264 | */ | |
24cd7723 | 1265 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1266 | { |
1267 | int level; | |
1268 | u64 *pte; | |
1269 | ||
24cd7723 JR |
1270 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1271 | return NULL; | |
1272 | ||
1273 | level = domain->mode - 1; | |
1274 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1275 | |
24cd7723 JR |
1276 | while (level > 0) { |
1277 | ||
1278 | /* Not Present */ | |
308973d3 JR |
1279 | if (!IOMMU_PTE_PRESENT(*pte)) |
1280 | return NULL; | |
1281 | ||
24cd7723 JR |
1282 | /* Large PTE */ |
1283 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1284 | unsigned long pte_mask, __pte; | |
1285 | ||
1286 | /* | |
1287 | * If we have a series of large PTEs, make | |
1288 | * sure to return a pointer to the first one. | |
1289 | */ | |
1290 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1291 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1292 | __pte = ((unsigned long)pte) & pte_mask; | |
1293 | ||
1294 | return (u64 *)__pte; | |
1295 | } | |
1296 | ||
1297 | /* No level skipping support yet */ | |
1298 | if (PM_PTE_LEVEL(*pte) != level) | |
1299 | return NULL; | |
1300 | ||
308973d3 JR |
1301 | level -= 1; |
1302 | ||
24cd7723 | 1303 | /* Walk to the next level */ |
308973d3 JR |
1304 | pte = IOMMU_PTE_PAGE(*pte); |
1305 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1306 | } |
1307 | ||
1308 | return pte; | |
1309 | } | |
1310 | ||
431b2a20 JR |
1311 | /* |
1312 | * Generic mapping functions. It maps a physical address into a DMA | |
1313 | * address space. It allocates the page table pages if necessary. | |
1314 | * In the future it can be extended to a generic mapping function | |
1315 | * supporting all features of AMD IOMMU page tables like level skipping | |
1316 | * and full 64 bit address spaces. | |
1317 | */ | |
38e817fe JR |
1318 | static int iommu_map_page(struct protection_domain *dom, |
1319 | unsigned long bus_addr, | |
1320 | unsigned long phys_addr, | |
abdc5eb3 | 1321 | int prot, |
cbb9d729 | 1322 | unsigned long page_size) |
bd0e5211 | 1323 | { |
8bda3092 | 1324 | u64 __pte, *pte; |
cbb9d729 | 1325 | int i, count; |
abdc5eb3 | 1326 | |
bad1cac2 | 1327 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1328 | return -EINVAL; |
1329 | ||
cbb9d729 JR |
1330 | bus_addr = PAGE_ALIGN(bus_addr); |
1331 | phys_addr = PAGE_ALIGN(phys_addr); | |
1332 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1333 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1334 | ||
1335 | for (i = 0; i < count; ++i) | |
1336 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1337 | return -EBUSY; | |
bd0e5211 | 1338 | |
cbb9d729 JR |
1339 | if (page_size > PAGE_SIZE) { |
1340 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1341 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1342 | } else | |
1343 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1344 | |
bd0e5211 JR |
1345 | if (prot & IOMMU_PROT_IR) |
1346 | __pte |= IOMMU_PTE_IR; | |
1347 | if (prot & IOMMU_PROT_IW) | |
1348 | __pte |= IOMMU_PTE_IW; | |
1349 | ||
cbb9d729 JR |
1350 | for (i = 0; i < count; ++i) |
1351 | pte[i] = __pte; | |
bd0e5211 | 1352 | |
04bfdd84 JR |
1353 | update_domain(dom); |
1354 | ||
bd0e5211 JR |
1355 | return 0; |
1356 | } | |
1357 | ||
24cd7723 JR |
1358 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1359 | unsigned long bus_addr, | |
1360 | unsigned long page_size) | |
eb74ff6c | 1361 | { |
24cd7723 JR |
1362 | unsigned long long unmap_size, unmapped; |
1363 | u64 *pte; | |
1364 | ||
1365 | BUG_ON(!is_power_of_2(page_size)); | |
1366 | ||
1367 | unmapped = 0; | |
eb74ff6c | 1368 | |
24cd7723 JR |
1369 | while (unmapped < page_size) { |
1370 | ||
1371 | pte = fetch_pte(dom, bus_addr); | |
1372 | ||
1373 | if (!pte) { | |
1374 | /* | |
1375 | * No PTE for this address | |
1376 | * move forward in 4kb steps | |
1377 | */ | |
1378 | unmap_size = PAGE_SIZE; | |
1379 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1380 | /* 4kb PTE found for this address */ | |
1381 | unmap_size = PAGE_SIZE; | |
1382 | *pte = 0ULL; | |
1383 | } else { | |
1384 | int count, i; | |
1385 | ||
1386 | /* Large PTE found which maps this address */ | |
1387 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1388 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1389 | for (i = 0; i < count; i++) | |
1390 | pte[i] = 0ULL; | |
1391 | } | |
1392 | ||
1393 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1394 | unmapped += unmap_size; | |
1395 | } | |
1396 | ||
1397 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1398 | |
24cd7723 | 1399 | return unmapped; |
eb74ff6c | 1400 | } |
eb74ff6c | 1401 | |
431b2a20 JR |
1402 | /* |
1403 | * This function checks if a specific unity mapping entry is needed for | |
1404 | * this specific IOMMU. | |
1405 | */ | |
bd0e5211 JR |
1406 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1407 | struct unity_map_entry *entry) | |
1408 | { | |
1409 | u16 bdf, i; | |
1410 | ||
1411 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1412 | bdf = amd_iommu_alias_table[i]; | |
1413 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1414 | return 1; | |
1415 | } | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
431b2a20 JR |
1420 | /* |
1421 | * This function actually applies the mapping to the page table of the | |
1422 | * dma_ops domain. | |
1423 | */ | |
bd0e5211 JR |
1424 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1425 | struct unity_map_entry *e) | |
1426 | { | |
1427 | u64 addr; | |
1428 | int ret; | |
1429 | ||
1430 | for (addr = e->address_start; addr < e->address_end; | |
1431 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1432 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1433 | PAGE_SIZE); |
bd0e5211 JR |
1434 | if (ret) |
1435 | return ret; | |
1436 | /* | |
1437 | * if unity mapping is in aperture range mark the page | |
1438 | * as allocated in the aperture | |
1439 | */ | |
1440 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1441 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1442 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1443 | } |
1444 | ||
1445 | return 0; | |
1446 | } | |
1447 | ||
171e7b37 JR |
1448 | /* |
1449 | * Init the unity mappings for a specific IOMMU in the system | |
1450 | * | |
1451 | * Basically iterates over all unity mapping entries and applies them to | |
1452 | * the default domain DMA of that IOMMU if necessary. | |
1453 | */ | |
1454 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1455 | { | |
1456 | struct unity_map_entry *entry; | |
1457 | int ret; | |
1458 | ||
1459 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1460 | if (!iommu_for_unity_map(iommu, entry)) | |
1461 | continue; | |
1462 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1463 | if (ret) | |
1464 | return ret; | |
1465 | } | |
1466 | ||
1467 | return 0; | |
1468 | } | |
1469 | ||
431b2a20 JR |
1470 | /* |
1471 | * Inits the unity mappings required for a specific device | |
1472 | */ | |
bd0e5211 JR |
1473 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1474 | u16 devid) | |
1475 | { | |
1476 | struct unity_map_entry *e; | |
1477 | int ret; | |
1478 | ||
1479 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1480 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1481 | continue; | |
1482 | ret = dma_ops_unity_map(dma_dom, e); | |
1483 | if (ret) | |
1484 | return ret; | |
1485 | } | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
431b2a20 JR |
1490 | /**************************************************************************** |
1491 | * | |
1492 | * The next functions belong to the address allocator for the dma_ops | |
1493 | * interface functions. They work like the allocators in the other IOMMU | |
1494 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1495 | * the aperture. Maybe it could be enhanced in the future to a more | |
1496 | * efficient allocator. | |
1497 | * | |
1498 | ****************************************************************************/ | |
d3086444 | 1499 | |
431b2a20 | 1500 | /* |
384de729 | 1501 | * The address allocator core functions. |
431b2a20 JR |
1502 | * |
1503 | * called with domain->lock held | |
1504 | */ | |
384de729 | 1505 | |
171e7b37 JR |
1506 | /* |
1507 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1508 | * ranges. | |
1509 | */ | |
1510 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1511 | unsigned long start_page, | |
1512 | unsigned int pages) | |
1513 | { | |
1514 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1515 | ||
1516 | if (start_page + pages > last_page) | |
1517 | pages = last_page - start_page; | |
1518 | ||
1519 | for (i = start_page; i < start_page + pages; ++i) { | |
1520 | int index = i / APERTURE_RANGE_PAGES; | |
1521 | int page = i % APERTURE_RANGE_PAGES; | |
1522 | __set_bit(page, dom->aperture[index]->bitmap); | |
1523 | } | |
1524 | } | |
1525 | ||
9cabe89b JR |
1526 | /* |
1527 | * This function is used to add a new aperture range to an existing | |
1528 | * aperture in case of dma_ops domain allocation or address allocation | |
1529 | * failure. | |
1530 | */ | |
576175c2 | 1531 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1532 | bool populate, gfp_t gfp) |
1533 | { | |
1534 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1535 | struct amd_iommu *iommu; |
17f5b569 | 1536 | unsigned long i, old_size; |
9cabe89b | 1537 | |
f5e9705c JR |
1538 | #ifdef CONFIG_IOMMU_STRESS |
1539 | populate = false; | |
1540 | #endif | |
1541 | ||
9cabe89b JR |
1542 | if (index >= APERTURE_MAX_RANGES) |
1543 | return -ENOMEM; | |
1544 | ||
1545 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1546 | if (!dma_dom->aperture[index]) | |
1547 | return -ENOMEM; | |
1548 | ||
1549 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1550 | if (!dma_dom->aperture[index]->bitmap) | |
1551 | goto out_free; | |
1552 | ||
1553 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1554 | ||
1555 | if (populate) { | |
1556 | unsigned long address = dma_dom->aperture_size; | |
1557 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1558 | u64 *pte, *pte_page; | |
1559 | ||
1560 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1561 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1562 | &pte_page, gfp); |
1563 | if (!pte) | |
1564 | goto out_free; | |
1565 | ||
1566 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1567 | ||
1568 | address += APERTURE_RANGE_SIZE / 64; | |
1569 | } | |
1570 | } | |
1571 | ||
17f5b569 | 1572 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1573 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1574 | ||
17f5b569 JR |
1575 | /* Reserve address range used for MSI messages */ |
1576 | if (old_size < MSI_ADDR_BASE_LO && | |
1577 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1578 | unsigned long spage; | |
1579 | int pages; | |
1580 | ||
1581 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1582 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1583 | ||
1584 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1585 | } | |
1586 | ||
b595076a | 1587 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1588 | for_each_iommu(iommu) { |
1589 | if (iommu->exclusion_start && | |
1590 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1591 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1592 | unsigned long startpage; | |
1593 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1594 | iommu->exclusion_length, | |
1595 | PAGE_SIZE); | |
1596 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1597 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1598 | } | |
00cd122a JR |
1599 | } |
1600 | ||
1601 | /* | |
1602 | * Check for areas already mapped as present in the new aperture | |
1603 | * range and mark those pages as reserved in the allocator. Such | |
1604 | * mappings may already exist as a result of requested unity | |
1605 | * mappings for devices. | |
1606 | */ | |
1607 | for (i = dma_dom->aperture[index]->offset; | |
1608 | i < dma_dom->aperture_size; | |
1609 | i += PAGE_SIZE) { | |
24cd7723 | 1610 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1611 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1612 | continue; | |
1613 | ||
fcd0861d | 1614 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1615 | } |
1616 | ||
04bfdd84 JR |
1617 | update_domain(&dma_dom->domain); |
1618 | ||
9cabe89b JR |
1619 | return 0; |
1620 | ||
1621 | out_free: | |
04bfdd84 JR |
1622 | update_domain(&dma_dom->domain); |
1623 | ||
9cabe89b JR |
1624 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1625 | ||
1626 | kfree(dma_dom->aperture[index]); | |
1627 | dma_dom->aperture[index] = NULL; | |
1628 | ||
1629 | return -ENOMEM; | |
1630 | } | |
1631 | ||
384de729 JR |
1632 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1633 | struct dma_ops_domain *dom, | |
1634 | unsigned int pages, | |
1635 | unsigned long align_mask, | |
1636 | u64 dma_mask, | |
1637 | unsigned long start) | |
1638 | { | |
803b8cb4 | 1639 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1640 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1641 | int i = start >> APERTURE_RANGE_SHIFT; | |
1642 | unsigned long boundary_size; | |
1643 | unsigned long address = -1; | |
1644 | unsigned long limit; | |
1645 | ||
803b8cb4 JR |
1646 | next_bit >>= PAGE_SHIFT; |
1647 | ||
384de729 JR |
1648 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1649 | PAGE_SIZE) >> PAGE_SHIFT; | |
1650 | ||
1651 | for (;i < max_index; ++i) { | |
1652 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1653 | ||
1654 | if (dom->aperture[i]->offset >= dma_mask) | |
1655 | break; | |
1656 | ||
1657 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1658 | dma_mask >> PAGE_SHIFT); | |
1659 | ||
1660 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1661 | limit, next_bit, pages, 0, | |
1662 | boundary_size, align_mask); | |
1663 | if (address != -1) { | |
1664 | address = dom->aperture[i]->offset + | |
1665 | (address << PAGE_SHIFT); | |
803b8cb4 | 1666 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1667 | break; |
1668 | } | |
1669 | ||
1670 | next_bit = 0; | |
1671 | } | |
1672 | ||
1673 | return address; | |
1674 | } | |
1675 | ||
d3086444 JR |
1676 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1677 | struct dma_ops_domain *dom, | |
6d4f343f | 1678 | unsigned int pages, |
832a90c3 JR |
1679 | unsigned long align_mask, |
1680 | u64 dma_mask) | |
d3086444 | 1681 | { |
d3086444 | 1682 | unsigned long address; |
d3086444 | 1683 | |
fe16f088 JR |
1684 | #ifdef CONFIG_IOMMU_STRESS |
1685 | dom->next_address = 0; | |
1686 | dom->need_flush = true; | |
1687 | #endif | |
d3086444 | 1688 | |
384de729 | 1689 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1690 | dma_mask, dom->next_address); |
d3086444 | 1691 | |
1c655773 | 1692 | if (address == -1) { |
803b8cb4 | 1693 | dom->next_address = 0; |
384de729 JR |
1694 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1695 | dma_mask, 0); | |
1c655773 JR |
1696 | dom->need_flush = true; |
1697 | } | |
d3086444 | 1698 | |
384de729 | 1699 | if (unlikely(address == -1)) |
8fd524b3 | 1700 | address = DMA_ERROR_CODE; |
d3086444 JR |
1701 | |
1702 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1703 | ||
1704 | return address; | |
1705 | } | |
1706 | ||
431b2a20 JR |
1707 | /* |
1708 | * The address free function. | |
1709 | * | |
1710 | * called with domain->lock held | |
1711 | */ | |
d3086444 JR |
1712 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1713 | unsigned long address, | |
1714 | unsigned int pages) | |
1715 | { | |
384de729 JR |
1716 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1717 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1718 | |
384de729 JR |
1719 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1720 | ||
47bccd6b JR |
1721 | #ifdef CONFIG_IOMMU_STRESS |
1722 | if (i < 4) | |
1723 | return; | |
1724 | #endif | |
80be308d | 1725 | |
803b8cb4 | 1726 | if (address >= dom->next_address) |
80be308d | 1727 | dom->need_flush = true; |
384de729 JR |
1728 | |
1729 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1730 | |
a66022c4 | 1731 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1732 | |
d3086444 JR |
1733 | } |
1734 | ||
431b2a20 JR |
1735 | /**************************************************************************** |
1736 | * | |
1737 | * The next functions belong to the domain allocation. A domain is | |
1738 | * allocated for every IOMMU as the default domain. If device isolation | |
1739 | * is enabled, every device get its own domain. The most important thing | |
1740 | * about domains is the page table mapping the DMA address space they | |
1741 | * contain. | |
1742 | * | |
1743 | ****************************************************************************/ | |
1744 | ||
aeb26f55 JR |
1745 | /* |
1746 | * This function adds a protection domain to the global protection domain list | |
1747 | */ | |
1748 | static void add_domain_to_list(struct protection_domain *domain) | |
1749 | { | |
1750 | unsigned long flags; | |
1751 | ||
1752 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1753 | list_add(&domain->list, &amd_iommu_pd_list); | |
1754 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1755 | } | |
1756 | ||
1757 | /* | |
1758 | * This function removes a protection domain to the global | |
1759 | * protection domain list | |
1760 | */ | |
1761 | static void del_domain_from_list(struct protection_domain *domain) | |
1762 | { | |
1763 | unsigned long flags; | |
1764 | ||
1765 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1766 | list_del(&domain->list); | |
1767 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1768 | } | |
1769 | ||
ec487d1a JR |
1770 | static u16 domain_id_alloc(void) |
1771 | { | |
1772 | unsigned long flags; | |
1773 | int id; | |
1774 | ||
1775 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1776 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1777 | BUG_ON(id == 0); | |
1778 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1779 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1780 | else | |
1781 | id = 0; | |
1782 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1783 | ||
1784 | return id; | |
1785 | } | |
1786 | ||
a2acfb75 JR |
1787 | static void domain_id_free(int id) |
1788 | { | |
1789 | unsigned long flags; | |
1790 | ||
1791 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1792 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1793 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1794 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1795 | } | |
a2acfb75 | 1796 | |
86db2e5d | 1797 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1798 | { |
1799 | int i, j; | |
1800 | u64 *p1, *p2, *p3; | |
1801 | ||
86db2e5d | 1802 | p1 = domain->pt_root; |
ec487d1a JR |
1803 | |
1804 | if (!p1) | |
1805 | return; | |
1806 | ||
1807 | for (i = 0; i < 512; ++i) { | |
1808 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1809 | continue; | |
1810 | ||
1811 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1812 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1813 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1814 | continue; | |
1815 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1816 | free_page((unsigned long)p3); | |
1817 | } | |
1818 | ||
1819 | free_page((unsigned long)p2); | |
1820 | } | |
1821 | ||
1822 | free_page((unsigned long)p1); | |
86db2e5d JR |
1823 | |
1824 | domain->pt_root = NULL; | |
ec487d1a JR |
1825 | } |
1826 | ||
b16137b1 JR |
1827 | static void free_gcr3_tbl_level1(u64 *tbl) |
1828 | { | |
1829 | u64 *ptr; | |
1830 | int i; | |
1831 | ||
1832 | for (i = 0; i < 512; ++i) { | |
1833 | if (!(tbl[i] & GCR3_VALID)) | |
1834 | continue; | |
1835 | ||
1836 | ptr = __va(tbl[i] & PAGE_MASK); | |
1837 | ||
1838 | free_page((unsigned long)ptr); | |
1839 | } | |
1840 | } | |
1841 | ||
1842 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1843 | { | |
1844 | u64 *ptr; | |
1845 | int i; | |
1846 | ||
1847 | for (i = 0; i < 512; ++i) { | |
1848 | if (!(tbl[i] & GCR3_VALID)) | |
1849 | continue; | |
1850 | ||
1851 | ptr = __va(tbl[i] & PAGE_MASK); | |
1852 | ||
1853 | free_gcr3_tbl_level1(ptr); | |
1854 | } | |
1855 | } | |
1856 | ||
52815b75 JR |
1857 | static void free_gcr3_table(struct protection_domain *domain) |
1858 | { | |
b16137b1 JR |
1859 | if (domain->glx == 2) |
1860 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1861 | else if (domain->glx == 1) | |
1862 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1863 | else if (domain->glx != 0) | |
1864 | BUG(); | |
1865 | ||
52815b75 JR |
1866 | free_page((unsigned long)domain->gcr3_tbl); |
1867 | } | |
1868 | ||
431b2a20 JR |
1869 | /* |
1870 | * Free a domain, only used if something went wrong in the | |
1871 | * allocation path and we need to free an already allocated page table | |
1872 | */ | |
ec487d1a JR |
1873 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1874 | { | |
384de729 JR |
1875 | int i; |
1876 | ||
ec487d1a JR |
1877 | if (!dom) |
1878 | return; | |
1879 | ||
aeb26f55 JR |
1880 | del_domain_from_list(&dom->domain); |
1881 | ||
86db2e5d | 1882 | free_pagetable(&dom->domain); |
ec487d1a | 1883 | |
384de729 JR |
1884 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1885 | if (!dom->aperture[i]) | |
1886 | continue; | |
1887 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1888 | kfree(dom->aperture[i]); | |
1889 | } | |
ec487d1a JR |
1890 | |
1891 | kfree(dom); | |
1892 | } | |
1893 | ||
431b2a20 JR |
1894 | /* |
1895 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1896 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1897 | * structures required for the dma_ops interface |
1898 | */ | |
87a64d52 | 1899 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1900 | { |
1901 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1902 | |
1903 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1904 | if (!dma_dom) | |
1905 | return NULL; | |
1906 | ||
1907 | spin_lock_init(&dma_dom->domain.lock); | |
1908 | ||
1909 | dma_dom->domain.id = domain_id_alloc(); | |
1910 | if (dma_dom->domain.id == 0) | |
1911 | goto free_dma_dom; | |
7c392cbe | 1912 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1913 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1914 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1915 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1916 | dma_dom->domain.priv = dma_dom; |
1917 | if (!dma_dom->domain.pt_root) | |
1918 | goto free_dma_dom; | |
ec487d1a | 1919 | |
1c655773 | 1920 | dma_dom->need_flush = false; |
bd60b735 | 1921 | dma_dom->target_dev = 0xffff; |
1c655773 | 1922 | |
aeb26f55 JR |
1923 | add_domain_to_list(&dma_dom->domain); |
1924 | ||
576175c2 | 1925 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1926 | goto free_dma_dom; |
ec487d1a | 1927 | |
431b2a20 | 1928 | /* |
ec487d1a JR |
1929 | * mark the first page as allocated so we never return 0 as |
1930 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1931 | */ |
384de729 | 1932 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1933 | dma_dom->next_address = 0; |
ec487d1a | 1934 | |
ec487d1a JR |
1935 | |
1936 | return dma_dom; | |
1937 | ||
1938 | free_dma_dom: | |
1939 | dma_ops_domain_free(dma_dom); | |
1940 | ||
1941 | return NULL; | |
1942 | } | |
1943 | ||
5b28df6f JR |
1944 | /* |
1945 | * little helper function to check whether a given protection domain is a | |
1946 | * dma_ops domain | |
1947 | */ | |
1948 | static bool dma_ops_domain(struct protection_domain *domain) | |
1949 | { | |
1950 | return domain->flags & PD_DMA_OPS_MASK; | |
1951 | } | |
1952 | ||
fd7b5535 | 1953 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1954 | { |
132bd68f | 1955 | u64 pte_root = 0; |
ee6c2868 | 1956 | u64 flags = 0; |
863c74eb | 1957 | |
132bd68f JR |
1958 | if (domain->mode != PAGE_MODE_NONE) |
1959 | pte_root = virt_to_phys(domain->pt_root); | |
1960 | ||
38ddf41b JR |
1961 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1962 | << DEV_ENTRY_MODE_SHIFT; | |
1963 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1964 | |
ee6c2868 JR |
1965 | flags = amd_iommu_dev_table[devid].data[1]; |
1966 | ||
fd7b5535 JR |
1967 | if (ats) |
1968 | flags |= DTE_FLAG_IOTLB; | |
1969 | ||
52815b75 JR |
1970 | if (domain->flags & PD_IOMMUV2_MASK) { |
1971 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1972 | u64 glx = domain->glx; | |
1973 | u64 tmp; | |
1974 | ||
1975 | pte_root |= DTE_FLAG_GV; | |
1976 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1977 | ||
1978 | /* First mask out possible old values for GCR3 table */ | |
1979 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1980 | flags &= ~tmp; | |
1981 | ||
1982 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1983 | flags &= ~tmp; | |
1984 | ||
1985 | /* Encode GCR3 table into DTE */ | |
1986 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1987 | pte_root |= tmp; | |
1988 | ||
1989 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1990 | flags |= tmp; | |
1991 | ||
1992 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1993 | flags |= tmp; | |
1994 | } | |
1995 | ||
ee6c2868 JR |
1996 | flags &= ~(0xffffUL); |
1997 | flags |= domain->id; | |
1998 | ||
1999 | amd_iommu_dev_table[devid].data[1] = flags; | |
2000 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2001 | } |
2002 | ||
2003 | static void clear_dte_entry(u16 devid) | |
2004 | { | |
15898bbc JR |
2005 | /* remove entry from the device table seen by the hardware */ |
2006 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2007 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2008 | |
2009 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2010 | } |
2011 | ||
ec9e79ef JR |
2012 | static void do_attach(struct iommu_dev_data *dev_data, |
2013 | struct protection_domain *domain) | |
7f760ddd | 2014 | { |
7f760ddd | 2015 | struct amd_iommu *iommu; |
ec9e79ef | 2016 | bool ats; |
fd7b5535 | 2017 | |
ec9e79ef JR |
2018 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2019 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2020 | |
2021 | /* Update data structures */ | |
2022 | dev_data->domain = domain; | |
2023 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2024 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2025 | |
2026 | /* Do reference counting */ | |
2027 | domain->dev_iommu[iommu->index] += 1; | |
2028 | domain->dev_cnt += 1; | |
2029 | ||
2030 | /* Flush the DTE entry */ | |
6c542047 | 2031 | device_flush_dte(dev_data); |
7f760ddd JR |
2032 | } |
2033 | ||
ec9e79ef | 2034 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2035 | { |
7f760ddd | 2036 | struct amd_iommu *iommu; |
7f760ddd | 2037 | |
ec9e79ef | 2038 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2039 | |
2040 | /* decrease reference counters */ | |
7f760ddd JR |
2041 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2042 | dev_data->domain->dev_cnt -= 1; | |
2043 | ||
2044 | /* Update data structures */ | |
2045 | dev_data->domain = NULL; | |
2046 | list_del(&dev_data->list); | |
f62dda66 | 2047 | clear_dte_entry(dev_data->devid); |
15898bbc | 2048 | |
7f760ddd | 2049 | /* Flush the DTE entry */ |
6c542047 | 2050 | device_flush_dte(dev_data); |
2b681faf JR |
2051 | } |
2052 | ||
2053 | /* | |
2054 | * If a device is not yet associated with a domain, this function does | |
2055 | * assigns it visible for the hardware | |
2056 | */ | |
ec9e79ef | 2057 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2058 | struct protection_domain *domain) |
2b681faf | 2059 | { |
84fe6c19 | 2060 | int ret; |
657cbb6b | 2061 | |
2b681faf JR |
2062 | /* lock domain */ |
2063 | spin_lock(&domain->lock); | |
2064 | ||
71f77580 JR |
2065 | if (dev_data->alias_data != NULL) { |
2066 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2067 | |
2b02b091 JR |
2068 | /* Some sanity checks */ |
2069 | ret = -EBUSY; | |
2070 | if (alias_data->domain != NULL && | |
2071 | alias_data->domain != domain) | |
2072 | goto out_unlock; | |
eba6ac60 | 2073 | |
2b02b091 JR |
2074 | if (dev_data->domain != NULL && |
2075 | dev_data->domain != domain) | |
2076 | goto out_unlock; | |
15898bbc | 2077 | |
2b02b091 | 2078 | /* Do real assignment */ |
7f760ddd | 2079 | if (alias_data->domain == NULL) |
ec9e79ef | 2080 | do_attach(alias_data, domain); |
24100055 JR |
2081 | |
2082 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2083 | } |
15898bbc | 2084 | |
7f760ddd | 2085 | if (dev_data->domain == NULL) |
ec9e79ef | 2086 | do_attach(dev_data, domain); |
eba6ac60 | 2087 | |
24100055 JR |
2088 | atomic_inc(&dev_data->bind); |
2089 | ||
84fe6c19 JL |
2090 | ret = 0; |
2091 | ||
2092 | out_unlock: | |
2093 | ||
eba6ac60 JR |
2094 | /* ready */ |
2095 | spin_unlock(&domain->lock); | |
15898bbc | 2096 | |
84fe6c19 | 2097 | return ret; |
0feae533 | 2098 | } |
b20ac0d4 | 2099 | |
52815b75 JR |
2100 | |
2101 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2102 | { | |
2103 | pci_disable_ats(pdev); | |
2104 | pci_disable_pri(pdev); | |
2105 | pci_disable_pasid(pdev); | |
2106 | } | |
2107 | ||
6a113ddc JR |
2108 | /* FIXME: Change generic reset-function to do the same */ |
2109 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2110 | { | |
2111 | u16 control; | |
2112 | int pos; | |
2113 | ||
46277b75 | 2114 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2115 | if (!pos) |
2116 | return -EINVAL; | |
2117 | ||
46277b75 JR |
2118 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2119 | control |= PCI_PRI_CTRL_RESET; | |
2120 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2121 | |
2122 | return 0; | |
2123 | } | |
2124 | ||
52815b75 JR |
2125 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2126 | { | |
6a113ddc JR |
2127 | bool reset_enable; |
2128 | int reqs, ret; | |
2129 | ||
2130 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2131 | reqs = 32; | |
2132 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2133 | reqs = 1; | |
2134 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2135 | |
2136 | /* Only allow access to user-accessible pages */ | |
2137 | ret = pci_enable_pasid(pdev, 0); | |
2138 | if (ret) | |
2139 | goto out_err; | |
2140 | ||
2141 | /* First reset the PRI state of the device */ | |
2142 | ret = pci_reset_pri(pdev); | |
2143 | if (ret) | |
2144 | goto out_err; | |
2145 | ||
6a113ddc JR |
2146 | /* Enable PRI */ |
2147 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2148 | if (ret) |
2149 | goto out_err; | |
2150 | ||
6a113ddc JR |
2151 | if (reset_enable) { |
2152 | ret = pri_reset_while_enabled(pdev); | |
2153 | if (ret) | |
2154 | goto out_err; | |
2155 | } | |
2156 | ||
52815b75 JR |
2157 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2158 | if (ret) | |
2159 | goto out_err; | |
2160 | ||
2161 | return 0; | |
2162 | ||
2163 | out_err: | |
2164 | pci_disable_pri(pdev); | |
2165 | pci_disable_pasid(pdev); | |
2166 | ||
2167 | return ret; | |
2168 | } | |
2169 | ||
c99afa25 | 2170 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2171 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2172 | |
98f1ad25 | 2173 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2174 | { |
a3b93121 | 2175 | u16 status; |
c99afa25 JR |
2176 | int pos; |
2177 | ||
46277b75 | 2178 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2179 | if (!pos) |
2180 | return false; | |
2181 | ||
a3b93121 | 2182 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2183 | |
a3b93121 | 2184 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2185 | } |
2186 | ||
407d733e JR |
2187 | /* |
2188 | * If a device is not yet associated with a domain, this function does | |
2189 | * assigns it visible for the hardware | |
2190 | */ | |
15898bbc JR |
2191 | static int attach_device(struct device *dev, |
2192 | struct protection_domain *domain) | |
0feae533 | 2193 | { |
fd7b5535 | 2194 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2195 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2196 | unsigned long flags; |
15898bbc | 2197 | int ret; |
eba6ac60 | 2198 | |
ea61cddb JR |
2199 | dev_data = get_dev_data(dev); |
2200 | ||
52815b75 JR |
2201 | if (domain->flags & PD_IOMMUV2_MASK) { |
2202 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2203 | return -EINVAL; | |
2204 | ||
2205 | if (pdev_iommuv2_enable(pdev) != 0) | |
2206 | return -EINVAL; | |
2207 | ||
2208 | dev_data->ats.enabled = true; | |
2209 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2210 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2211 | } else if (amd_iommu_iotlb_sup && |
2212 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2213 | dev_data->ats.enabled = true; |
2214 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2215 | } | |
fd7b5535 | 2216 | |
eba6ac60 | 2217 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2218 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2219 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2220 | ||
0feae533 JR |
2221 | /* |
2222 | * We might boot into a crash-kernel here. The crashed kernel | |
2223 | * left the caches in the IOMMU dirty. So we have to flush | |
2224 | * here to evict all dirty stuff. | |
2225 | */ | |
17b124bf | 2226 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2227 | |
2228 | return ret; | |
b20ac0d4 JR |
2229 | } |
2230 | ||
355bf553 JR |
2231 | /* |
2232 | * Removes a device from a protection domain (unlocked) | |
2233 | */ | |
ec9e79ef | 2234 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2235 | { |
2ca76279 | 2236 | struct protection_domain *domain; |
7c392cbe | 2237 | unsigned long flags; |
c4596114 | 2238 | |
7f760ddd | 2239 | BUG_ON(!dev_data->domain); |
355bf553 | 2240 | |
2ca76279 JR |
2241 | domain = dev_data->domain; |
2242 | ||
2243 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2244 | |
71f77580 JR |
2245 | if (dev_data->alias_data != NULL) { |
2246 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2247 | ||
7f760ddd | 2248 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2249 | do_detach(alias_data); |
24100055 JR |
2250 | } |
2251 | ||
7f760ddd | 2252 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2253 | do_detach(dev_data); |
7f760ddd | 2254 | |
2ca76279 | 2255 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2256 | |
2257 | /* | |
2258 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2259 | * passthrough domain if it is detached from any other domain. |
2260 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2261 | */ |
5abcdba4 | 2262 | if (dev_data->passthrough && |
d3ad9373 | 2263 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2264 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2265 | } |
2266 | ||
2267 | /* | |
2268 | * Removes a device from a protection domain (with devtable_lock held) | |
2269 | */ | |
15898bbc | 2270 | static void detach_device(struct device *dev) |
355bf553 | 2271 | { |
52815b75 | 2272 | struct protection_domain *domain; |
ea61cddb | 2273 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2274 | unsigned long flags; |
2275 | ||
ec9e79ef | 2276 | dev_data = get_dev_data(dev); |
52815b75 | 2277 | domain = dev_data->domain; |
ec9e79ef | 2278 | |
355bf553 JR |
2279 | /* lock device table */ |
2280 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2281 | __detach_device(dev_data); |
355bf553 | 2282 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2283 | |
52815b75 JR |
2284 | if (domain->flags & PD_IOMMUV2_MASK) |
2285 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2286 | else if (dev_data->ats.enabled) | |
ea61cddb | 2287 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2288 | |
2289 | dev_data->ats.enabled = false; | |
355bf553 | 2290 | } |
e275a2a0 | 2291 | |
15898bbc JR |
2292 | /* |
2293 | * Find out the protection domain structure for a given PCI device. This | |
2294 | * will give us the pointer to the page table root for example. | |
2295 | */ | |
2296 | static struct protection_domain *domain_for_device(struct device *dev) | |
2297 | { | |
71f77580 | 2298 | struct iommu_dev_data *dev_data; |
2b02b091 | 2299 | struct protection_domain *dom = NULL; |
15898bbc | 2300 | unsigned long flags; |
15898bbc | 2301 | |
657cbb6b | 2302 | dev_data = get_dev_data(dev); |
15898bbc | 2303 | |
2b02b091 JR |
2304 | if (dev_data->domain) |
2305 | return dev_data->domain; | |
15898bbc | 2306 | |
71f77580 JR |
2307 | if (dev_data->alias_data != NULL) { |
2308 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2309 | |
2310 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2311 | if (alias_data->domain != NULL) { | |
2312 | __attach_device(dev_data, alias_data->domain); | |
2313 | dom = alias_data->domain; | |
2314 | } | |
2315 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2316 | } | |
15898bbc JR |
2317 | |
2318 | return dom; | |
2319 | } | |
2320 | ||
e275a2a0 JR |
2321 | static int device_change_notifier(struct notifier_block *nb, |
2322 | unsigned long action, void *data) | |
2323 | { | |
e275a2a0 | 2324 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2325 | struct protection_domain *domain; |
2326 | struct iommu_dev_data *dev_data; | |
2327 | struct device *dev = data; | |
e275a2a0 | 2328 | struct amd_iommu *iommu; |
1ac4cbbc | 2329 | unsigned long flags; |
5abcdba4 | 2330 | u16 devid; |
e275a2a0 | 2331 | |
98fc5a69 JR |
2332 | if (!check_device(dev)) |
2333 | return 0; | |
e275a2a0 | 2334 | |
5abcdba4 JR |
2335 | devid = get_device_id(dev); |
2336 | iommu = amd_iommu_rlookup_table[devid]; | |
2337 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2338 | |
2339 | switch (action) { | |
c1eee67b | 2340 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2341 | |
2342 | domain = domain_for_device(dev); | |
2343 | ||
e275a2a0 JR |
2344 | if (!domain) |
2345 | goto out; | |
5abcdba4 | 2346 | if (dev_data->passthrough) |
a1ca331c | 2347 | break; |
15898bbc | 2348 | detach_device(dev); |
1ac4cbbc JR |
2349 | break; |
2350 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2351 | |
2352 | iommu_init_device(dev); | |
2353 | ||
2c9195e9 JR |
2354 | /* |
2355 | * dev_data is still NULL and | |
2356 | * got initialized in iommu_init_device | |
2357 | */ | |
2358 | dev_data = get_dev_data(dev); | |
2359 | ||
2360 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2361 | dev_data->passthrough = true; | |
2362 | attach_device(dev, pt_domain); | |
2363 | break; | |
2364 | } | |
2365 | ||
657cbb6b JR |
2366 | domain = domain_for_device(dev); |
2367 | ||
1ac4cbbc JR |
2368 | /* allocate a protection domain if a device is added */ |
2369 | dma_domain = find_protection_domain(devid); | |
2370 | if (dma_domain) | |
2371 | goto out; | |
87a64d52 | 2372 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2373 | if (!dma_domain) |
2374 | goto out; | |
2375 | dma_domain->target_dev = devid; | |
2376 | ||
2377 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2378 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2379 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2380 | ||
ac1534a5 JR |
2381 | dev_data = get_dev_data(dev); |
2382 | ||
2c9195e9 | 2383 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2384 | |
e275a2a0 | 2385 | break; |
657cbb6b JR |
2386 | case BUS_NOTIFY_DEL_DEVICE: |
2387 | ||
2388 | iommu_uninit_device(dev); | |
2389 | ||
e275a2a0 JR |
2390 | default: |
2391 | goto out; | |
2392 | } | |
2393 | ||
e275a2a0 JR |
2394 | iommu_completion_wait(iommu); |
2395 | ||
2396 | out: | |
2397 | return 0; | |
2398 | } | |
2399 | ||
b25ae679 | 2400 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2401 | .notifier_call = device_change_notifier, |
2402 | }; | |
355bf553 | 2403 | |
8638c491 JR |
2404 | void amd_iommu_init_notifier(void) |
2405 | { | |
2406 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2407 | } | |
2408 | ||
431b2a20 JR |
2409 | /***************************************************************************** |
2410 | * | |
2411 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2412 | * | |
2413 | *****************************************************************************/ | |
2414 | ||
2415 | /* | |
2416 | * In the dma_ops path we only have the struct device. This function | |
2417 | * finds the corresponding IOMMU, the protection domain and the | |
2418 | * requestor id for a given device. | |
2419 | * If the device is not yet associated with a domain this is also done | |
2420 | * in this function. | |
2421 | */ | |
94f6d190 | 2422 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2423 | { |
94f6d190 | 2424 | struct protection_domain *domain; |
b20ac0d4 | 2425 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2426 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2427 | |
f99c0f1c | 2428 | if (!check_device(dev)) |
94f6d190 | 2429 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2430 | |
94f6d190 JR |
2431 | domain = domain_for_device(dev); |
2432 | if (domain != NULL && !dma_ops_domain(domain)) | |
2433 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2434 | |
94f6d190 JR |
2435 | if (domain != NULL) |
2436 | return domain; | |
b20ac0d4 | 2437 | |
15898bbc | 2438 | /* Device not bount yet - bind it */ |
94f6d190 | 2439 | dma_dom = find_protection_domain(devid); |
15898bbc | 2440 | if (!dma_dom) |
94f6d190 JR |
2441 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2442 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2443 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2444 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2445 | |
94f6d190 | 2446 | return &dma_dom->domain; |
b20ac0d4 JR |
2447 | } |
2448 | ||
04bfdd84 JR |
2449 | static void update_device_table(struct protection_domain *domain) |
2450 | { | |
492667da | 2451 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2452 | |
ea61cddb JR |
2453 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2454 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2455 | } |
2456 | ||
2457 | static void update_domain(struct protection_domain *domain) | |
2458 | { | |
2459 | if (!domain->updated) | |
2460 | return; | |
2461 | ||
2462 | update_device_table(domain); | |
17b124bf JR |
2463 | |
2464 | domain_flush_devices(domain); | |
2465 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2466 | |
2467 | domain->updated = false; | |
2468 | } | |
2469 | ||
8bda3092 JR |
2470 | /* |
2471 | * This function fetches the PTE for a given address in the aperture | |
2472 | */ | |
2473 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2474 | unsigned long address) | |
2475 | { | |
384de729 | 2476 | struct aperture_range *aperture; |
8bda3092 JR |
2477 | u64 *pte, *pte_page; |
2478 | ||
384de729 JR |
2479 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2480 | if (!aperture) | |
2481 | return NULL; | |
2482 | ||
2483 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2484 | if (!pte) { |
cbb9d729 | 2485 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2486 | GFP_ATOMIC); |
384de729 JR |
2487 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2488 | } else | |
8c8c143c | 2489 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2490 | |
04bfdd84 | 2491 | update_domain(&dom->domain); |
8bda3092 JR |
2492 | |
2493 | return pte; | |
2494 | } | |
2495 | ||
431b2a20 JR |
2496 | /* |
2497 | * This is the generic map function. It maps one 4kb page at paddr to | |
2498 | * the given address in the DMA address space for the domain. | |
2499 | */ | |
680525e0 | 2500 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2501 | unsigned long address, |
2502 | phys_addr_t paddr, | |
2503 | int direction) | |
2504 | { | |
2505 | u64 *pte, __pte; | |
2506 | ||
2507 | WARN_ON(address > dom->aperture_size); | |
2508 | ||
2509 | paddr &= PAGE_MASK; | |
2510 | ||
8bda3092 | 2511 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2512 | if (!pte) |
8fd524b3 | 2513 | return DMA_ERROR_CODE; |
cb76c322 JR |
2514 | |
2515 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2516 | ||
2517 | if (direction == DMA_TO_DEVICE) | |
2518 | __pte |= IOMMU_PTE_IR; | |
2519 | else if (direction == DMA_FROM_DEVICE) | |
2520 | __pte |= IOMMU_PTE_IW; | |
2521 | else if (direction == DMA_BIDIRECTIONAL) | |
2522 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2523 | ||
2524 | WARN_ON(*pte); | |
2525 | ||
2526 | *pte = __pte; | |
2527 | ||
2528 | return (dma_addr_t)address; | |
2529 | } | |
2530 | ||
431b2a20 JR |
2531 | /* |
2532 | * The generic unmapping function for on page in the DMA address space. | |
2533 | */ | |
680525e0 | 2534 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2535 | unsigned long address) |
2536 | { | |
384de729 | 2537 | struct aperture_range *aperture; |
cb76c322 JR |
2538 | u64 *pte; |
2539 | ||
2540 | if (address >= dom->aperture_size) | |
2541 | return; | |
2542 | ||
384de729 JR |
2543 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2544 | if (!aperture) | |
2545 | return; | |
2546 | ||
2547 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2548 | if (!pte) | |
2549 | return; | |
cb76c322 | 2550 | |
8c8c143c | 2551 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2552 | |
2553 | WARN_ON(!*pte); | |
2554 | ||
2555 | *pte = 0ULL; | |
2556 | } | |
2557 | ||
431b2a20 JR |
2558 | /* |
2559 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2560 | * contiguous memory region into DMA address space. It is used by all |
2561 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2562 | * Must be called with the domain lock held. |
2563 | */ | |
cb76c322 | 2564 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2565 | struct dma_ops_domain *dma_dom, |
2566 | phys_addr_t paddr, | |
2567 | size_t size, | |
6d4f343f | 2568 | int dir, |
832a90c3 JR |
2569 | bool align, |
2570 | u64 dma_mask) | |
cb76c322 JR |
2571 | { |
2572 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2573 | dma_addr_t address, start, ret; |
cb76c322 | 2574 | unsigned int pages; |
6d4f343f | 2575 | unsigned long align_mask = 0; |
cb76c322 JR |
2576 | int i; |
2577 | ||
e3c449f5 | 2578 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2579 | paddr &= PAGE_MASK; |
2580 | ||
8ecaf8f1 JR |
2581 | INC_STATS_COUNTER(total_map_requests); |
2582 | ||
c1858976 JR |
2583 | if (pages > 1) |
2584 | INC_STATS_COUNTER(cross_page); | |
2585 | ||
6d4f343f JR |
2586 | if (align) |
2587 | align_mask = (1UL << get_order(size)) - 1; | |
2588 | ||
11b83888 | 2589 | retry: |
832a90c3 JR |
2590 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2591 | dma_mask); | |
8fd524b3 | 2592 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2593 | /* |
2594 | * setting next_address here will let the address | |
2595 | * allocator only scan the new allocated range in the | |
2596 | * first run. This is a small optimization. | |
2597 | */ | |
2598 | dma_dom->next_address = dma_dom->aperture_size; | |
2599 | ||
576175c2 | 2600 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2601 | goto out; |
2602 | ||
2603 | /* | |
af901ca1 | 2604 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2605 | * allocation again |
2606 | */ | |
2607 | goto retry; | |
2608 | } | |
cb76c322 JR |
2609 | |
2610 | start = address; | |
2611 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2612 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2613 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2614 | goto out_unmap; |
2615 | ||
cb76c322 JR |
2616 | paddr += PAGE_SIZE; |
2617 | start += PAGE_SIZE; | |
2618 | } | |
2619 | address += offset; | |
2620 | ||
5774f7c5 JR |
2621 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2622 | ||
afa9fdc2 | 2623 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2624 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2625 | dma_dom->need_flush = false; |
318afd41 | 2626 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2627 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2628 | |
cb76c322 JR |
2629 | out: |
2630 | return address; | |
53812c11 JR |
2631 | |
2632 | out_unmap: | |
2633 | ||
2634 | for (--i; i >= 0; --i) { | |
2635 | start -= PAGE_SIZE; | |
680525e0 | 2636 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2637 | } |
2638 | ||
2639 | dma_ops_free_addresses(dma_dom, address, pages); | |
2640 | ||
8fd524b3 | 2641 | return DMA_ERROR_CODE; |
cb76c322 JR |
2642 | } |
2643 | ||
431b2a20 JR |
2644 | /* |
2645 | * Does the reverse of the __map_single function. Must be called with | |
2646 | * the domain lock held too | |
2647 | */ | |
cd8c82e8 | 2648 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2649 | dma_addr_t dma_addr, |
2650 | size_t size, | |
2651 | int dir) | |
2652 | { | |
04e0463e | 2653 | dma_addr_t flush_addr; |
cb76c322 JR |
2654 | dma_addr_t i, start; |
2655 | unsigned int pages; | |
2656 | ||
8fd524b3 | 2657 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2658 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2659 | return; |
2660 | ||
04e0463e | 2661 | flush_addr = dma_addr; |
e3c449f5 | 2662 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2663 | dma_addr &= PAGE_MASK; |
2664 | start = dma_addr; | |
2665 | ||
2666 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2667 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2668 | start += PAGE_SIZE; |
2669 | } | |
2670 | ||
5774f7c5 JR |
2671 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2672 | ||
cb76c322 | 2673 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2674 | |
80be308d | 2675 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2676 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2677 | dma_dom->need_flush = false; |
2678 | } | |
cb76c322 JR |
2679 | } |
2680 | ||
431b2a20 JR |
2681 | /* |
2682 | * The exported map_single function for dma_ops. | |
2683 | */ | |
51491367 FT |
2684 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2685 | unsigned long offset, size_t size, | |
2686 | enum dma_data_direction dir, | |
2687 | struct dma_attrs *attrs) | |
4da70b9e JR |
2688 | { |
2689 | unsigned long flags; | |
4da70b9e | 2690 | struct protection_domain *domain; |
4da70b9e | 2691 | dma_addr_t addr; |
832a90c3 | 2692 | u64 dma_mask; |
51491367 | 2693 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2694 | |
0f2a86f2 JR |
2695 | INC_STATS_COUNTER(cnt_map_single); |
2696 | ||
94f6d190 JR |
2697 | domain = get_domain(dev); |
2698 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2699 | return (dma_addr_t)paddr; |
94f6d190 JR |
2700 | else if (IS_ERR(domain)) |
2701 | return DMA_ERROR_CODE; | |
4da70b9e | 2702 | |
f99c0f1c JR |
2703 | dma_mask = *dev->dma_mask; |
2704 | ||
4da70b9e | 2705 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2706 | |
cd8c82e8 | 2707 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2708 | dma_mask); |
8fd524b3 | 2709 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2710 | goto out; |
2711 | ||
17b124bf | 2712 | domain_flush_complete(domain); |
4da70b9e JR |
2713 | |
2714 | out: | |
2715 | spin_unlock_irqrestore(&domain->lock, flags); | |
2716 | ||
2717 | return addr; | |
2718 | } | |
2719 | ||
431b2a20 JR |
2720 | /* |
2721 | * The exported unmap_single function for dma_ops. | |
2722 | */ | |
51491367 FT |
2723 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2724 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2725 | { |
2726 | unsigned long flags; | |
4da70b9e | 2727 | struct protection_domain *domain; |
4da70b9e | 2728 | |
146a6917 JR |
2729 | INC_STATS_COUNTER(cnt_unmap_single); |
2730 | ||
94f6d190 JR |
2731 | domain = get_domain(dev); |
2732 | if (IS_ERR(domain)) | |
5b28df6f JR |
2733 | return; |
2734 | ||
4da70b9e JR |
2735 | spin_lock_irqsave(&domain->lock, flags); |
2736 | ||
cd8c82e8 | 2737 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2738 | |
17b124bf | 2739 | domain_flush_complete(domain); |
4da70b9e JR |
2740 | |
2741 | spin_unlock_irqrestore(&domain->lock, flags); | |
2742 | } | |
2743 | ||
431b2a20 JR |
2744 | /* |
2745 | * This is a special map_sg function which is used if we should map a | |
2746 | * device which is not handled by an AMD IOMMU in the system. | |
2747 | */ | |
65b050ad JR |
2748 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2749 | int nelems, int dir) | |
2750 | { | |
2751 | struct scatterlist *s; | |
2752 | int i; | |
2753 | ||
2754 | for_each_sg(sglist, s, nelems, i) { | |
2755 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2756 | s->dma_length = s->length; | |
2757 | } | |
2758 | ||
2759 | return nelems; | |
2760 | } | |
2761 | ||
431b2a20 JR |
2762 | /* |
2763 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2764 | * lists). | |
2765 | */ | |
65b050ad | 2766 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2767 | int nelems, enum dma_data_direction dir, |
2768 | struct dma_attrs *attrs) | |
65b050ad JR |
2769 | { |
2770 | unsigned long flags; | |
65b050ad | 2771 | struct protection_domain *domain; |
65b050ad JR |
2772 | int i; |
2773 | struct scatterlist *s; | |
2774 | phys_addr_t paddr; | |
2775 | int mapped_elems = 0; | |
832a90c3 | 2776 | u64 dma_mask; |
65b050ad | 2777 | |
d03f067a JR |
2778 | INC_STATS_COUNTER(cnt_map_sg); |
2779 | ||
94f6d190 JR |
2780 | domain = get_domain(dev); |
2781 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2782 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2783 | else if (IS_ERR(domain)) |
2784 | return 0; | |
dbcc112e | 2785 | |
832a90c3 | 2786 | dma_mask = *dev->dma_mask; |
65b050ad | 2787 | |
65b050ad JR |
2788 | spin_lock_irqsave(&domain->lock, flags); |
2789 | ||
2790 | for_each_sg(sglist, s, nelems, i) { | |
2791 | paddr = sg_phys(s); | |
2792 | ||
cd8c82e8 | 2793 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2794 | paddr, s->length, dir, false, |
2795 | dma_mask); | |
65b050ad JR |
2796 | |
2797 | if (s->dma_address) { | |
2798 | s->dma_length = s->length; | |
2799 | mapped_elems++; | |
2800 | } else | |
2801 | goto unmap; | |
65b050ad JR |
2802 | } |
2803 | ||
17b124bf | 2804 | domain_flush_complete(domain); |
65b050ad JR |
2805 | |
2806 | out: | |
2807 | spin_unlock_irqrestore(&domain->lock, flags); | |
2808 | ||
2809 | return mapped_elems; | |
2810 | unmap: | |
2811 | for_each_sg(sglist, s, mapped_elems, i) { | |
2812 | if (s->dma_address) | |
cd8c82e8 | 2813 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2814 | s->dma_length, dir); |
2815 | s->dma_address = s->dma_length = 0; | |
2816 | } | |
2817 | ||
2818 | mapped_elems = 0; | |
2819 | ||
2820 | goto out; | |
2821 | } | |
2822 | ||
431b2a20 JR |
2823 | /* |
2824 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2825 | * lists). | |
2826 | */ | |
65b050ad | 2827 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2828 | int nelems, enum dma_data_direction dir, |
2829 | struct dma_attrs *attrs) | |
65b050ad JR |
2830 | { |
2831 | unsigned long flags; | |
65b050ad JR |
2832 | struct protection_domain *domain; |
2833 | struct scatterlist *s; | |
65b050ad JR |
2834 | int i; |
2835 | ||
55877a6b JR |
2836 | INC_STATS_COUNTER(cnt_unmap_sg); |
2837 | ||
94f6d190 JR |
2838 | domain = get_domain(dev); |
2839 | if (IS_ERR(domain)) | |
5b28df6f JR |
2840 | return; |
2841 | ||
65b050ad JR |
2842 | spin_lock_irqsave(&domain->lock, flags); |
2843 | ||
2844 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2845 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2846 | s->dma_length, dir); |
65b050ad JR |
2847 | s->dma_address = s->dma_length = 0; |
2848 | } | |
2849 | ||
17b124bf | 2850 | domain_flush_complete(domain); |
65b050ad JR |
2851 | |
2852 | spin_unlock_irqrestore(&domain->lock, flags); | |
2853 | } | |
2854 | ||
431b2a20 JR |
2855 | /* |
2856 | * The exported alloc_coherent function for dma_ops. | |
2857 | */ | |
5d8b53cf | 2858 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2859 | dma_addr_t *dma_addr, gfp_t flag, |
2860 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2861 | { |
2862 | unsigned long flags; | |
2863 | void *virt_addr; | |
5d8b53cf | 2864 | struct protection_domain *domain; |
5d8b53cf | 2865 | phys_addr_t paddr; |
832a90c3 | 2866 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2867 | |
c8f0fb36 JR |
2868 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2869 | ||
94f6d190 JR |
2870 | domain = get_domain(dev); |
2871 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2872 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2873 | *dma_addr = __pa(virt_addr); | |
2874 | return virt_addr; | |
94f6d190 JR |
2875 | } else if (IS_ERR(domain)) |
2876 | return NULL; | |
5d8b53cf | 2877 | |
f99c0f1c JR |
2878 | dma_mask = dev->coherent_dma_mask; |
2879 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2880 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2881 | |
2882 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2883 | if (!virt_addr) | |
b25ae679 | 2884 | return NULL; |
5d8b53cf | 2885 | |
5d8b53cf JR |
2886 | paddr = virt_to_phys(virt_addr); |
2887 | ||
832a90c3 JR |
2888 | if (!dma_mask) |
2889 | dma_mask = *dev->dma_mask; | |
2890 | ||
5d8b53cf JR |
2891 | spin_lock_irqsave(&domain->lock, flags); |
2892 | ||
cd8c82e8 | 2893 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2894 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2895 | |
8fd524b3 | 2896 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2897 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2898 | goto out_free; |
367d04c4 | 2899 | } |
5d8b53cf | 2900 | |
17b124bf | 2901 | domain_flush_complete(domain); |
5d8b53cf | 2902 | |
5d8b53cf JR |
2903 | spin_unlock_irqrestore(&domain->lock, flags); |
2904 | ||
2905 | return virt_addr; | |
5b28df6f JR |
2906 | |
2907 | out_free: | |
2908 | ||
2909 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2910 | ||
2911 | return NULL; | |
5d8b53cf JR |
2912 | } |
2913 | ||
431b2a20 JR |
2914 | /* |
2915 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2916 | */ |
5d8b53cf | 2917 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2918 | void *virt_addr, dma_addr_t dma_addr, |
2919 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2920 | { |
2921 | unsigned long flags; | |
5d8b53cf | 2922 | struct protection_domain *domain; |
5d8b53cf | 2923 | |
5d31ee7e JR |
2924 | INC_STATS_COUNTER(cnt_free_coherent); |
2925 | ||
94f6d190 JR |
2926 | domain = get_domain(dev); |
2927 | if (IS_ERR(domain)) | |
5b28df6f JR |
2928 | goto free_mem; |
2929 | ||
5d8b53cf JR |
2930 | spin_lock_irqsave(&domain->lock, flags); |
2931 | ||
cd8c82e8 | 2932 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2933 | |
17b124bf | 2934 | domain_flush_complete(domain); |
5d8b53cf JR |
2935 | |
2936 | spin_unlock_irqrestore(&domain->lock, flags); | |
2937 | ||
2938 | free_mem: | |
2939 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2940 | } | |
2941 | ||
b39ba6ad JR |
2942 | /* |
2943 | * This function is called by the DMA layer to find out if we can handle a | |
2944 | * particular device. It is part of the dma_ops. | |
2945 | */ | |
2946 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2947 | { | |
420aef8a | 2948 | return check_device(dev); |
b39ba6ad JR |
2949 | } |
2950 | ||
c432f3df | 2951 | /* |
431b2a20 JR |
2952 | * The function for pre-allocating protection domains. |
2953 | * | |
c432f3df JR |
2954 | * If the driver core informs the DMA layer if a driver grabs a device |
2955 | * we don't need to preallocate the protection domains anymore. | |
2956 | * For now we have to. | |
2957 | */ | |
943bc7e1 | 2958 | static void __init prealloc_protection_domains(void) |
c432f3df | 2959 | { |
5abcdba4 | 2960 | struct iommu_dev_data *dev_data; |
c432f3df | 2961 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2962 | struct pci_dev *dev = NULL; |
98fc5a69 | 2963 | u16 devid; |
c432f3df | 2964 | |
d18c69d3 | 2965 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2966 | |
2967 | /* Do we handle this device? */ | |
2968 | if (!check_device(&dev->dev)) | |
c432f3df | 2969 | continue; |
98fc5a69 | 2970 | |
5abcdba4 JR |
2971 | dev_data = get_dev_data(&dev->dev); |
2972 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2973 | /* Make sure passthrough domain is allocated */ | |
2974 | alloc_passthrough_domain(); | |
2975 | dev_data->passthrough = true; | |
2976 | attach_device(&dev->dev, pt_domain); | |
2977 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2978 | dev_name(&dev->dev)); | |
2979 | } | |
2980 | ||
98fc5a69 | 2981 | /* Is there already any domain for it? */ |
15898bbc | 2982 | if (domain_for_device(&dev->dev)) |
c432f3df | 2983 | continue; |
98fc5a69 JR |
2984 | |
2985 | devid = get_device_id(&dev->dev); | |
2986 | ||
87a64d52 | 2987 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2988 | if (!dma_dom) |
2989 | continue; | |
2990 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2991 | dma_dom->target_dev = devid; |
2992 | ||
15898bbc | 2993 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2994 | |
bd60b735 | 2995 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2996 | } |
2997 | } | |
2998 | ||
160c1d8e | 2999 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3000 | .alloc = alloc_coherent, |
3001 | .free = free_coherent, | |
51491367 FT |
3002 | .map_page = map_page, |
3003 | .unmap_page = unmap_page, | |
6631ee9d JR |
3004 | .map_sg = map_sg, |
3005 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3006 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3007 | }; |
3008 | ||
27c2127a JR |
3009 | static unsigned device_dma_ops_init(void) |
3010 | { | |
5abcdba4 | 3011 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3012 | struct pci_dev *pdev = NULL; |
3013 | unsigned unhandled = 0; | |
3014 | ||
3015 | for_each_pci_dev(pdev) { | |
3016 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3017 | |
3018 | iommu_ignore_device(&pdev->dev); | |
3019 | ||
27c2127a JR |
3020 | unhandled += 1; |
3021 | continue; | |
3022 | } | |
3023 | ||
5abcdba4 JR |
3024 | dev_data = get_dev_data(&pdev->dev); |
3025 | ||
3026 | if (!dev_data->passthrough) | |
3027 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3028 | else | |
3029 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3030 | } |
3031 | ||
3032 | return unhandled; | |
3033 | } | |
3034 | ||
431b2a20 JR |
3035 | /* |
3036 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3037 | */ | |
f5325094 JR |
3038 | |
3039 | void __init amd_iommu_init_api(void) | |
3040 | { | |
2cc21c42 | 3041 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3042 | } |
3043 | ||
6631ee9d JR |
3044 | int __init amd_iommu_init_dma_ops(void) |
3045 | { | |
3046 | struct amd_iommu *iommu; | |
27c2127a | 3047 | int ret, unhandled; |
6631ee9d | 3048 | |
431b2a20 JR |
3049 | /* |
3050 | * first allocate a default protection domain for every IOMMU we | |
3051 | * found in the system. Devices not assigned to any other | |
3052 | * protection domain will be assigned to the default one. | |
3053 | */ | |
3bd22172 | 3054 | for_each_iommu(iommu) { |
87a64d52 | 3055 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3056 | if (iommu->default_dom == NULL) |
3057 | return -ENOMEM; | |
e2dc14a2 | 3058 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3059 | ret = iommu_init_unity_mappings(iommu); |
3060 | if (ret) | |
3061 | goto free_domains; | |
3062 | } | |
3063 | ||
431b2a20 | 3064 | /* |
8793abeb | 3065 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3066 | */ |
8793abeb | 3067 | prealloc_protection_domains(); |
6631ee9d JR |
3068 | |
3069 | iommu_detected = 1; | |
75f1cdf1 | 3070 | swiotlb = 0; |
6631ee9d | 3071 | |
431b2a20 | 3072 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3073 | unhandled = device_dma_ops_init(); |
3074 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3075 | /* There are unhandled devices - initialize swiotlb for them */ | |
3076 | swiotlb = 1; | |
3077 | } | |
6631ee9d | 3078 | |
7f26508b JR |
3079 | amd_iommu_stats_init(); |
3080 | ||
62410eeb JR |
3081 | if (amd_iommu_unmap_flush) |
3082 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3083 | else | |
3084 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3085 | ||
6631ee9d JR |
3086 | return 0; |
3087 | ||
3088 | free_domains: | |
3089 | ||
3bd22172 | 3090 | for_each_iommu(iommu) { |
6631ee9d JR |
3091 | if (iommu->default_dom) |
3092 | dma_ops_domain_free(iommu->default_dom); | |
3093 | } | |
3094 | ||
3095 | return ret; | |
3096 | } | |
6d98cd80 JR |
3097 | |
3098 | /***************************************************************************** | |
3099 | * | |
3100 | * The following functions belong to the exported interface of AMD IOMMU | |
3101 | * | |
3102 | * This interface allows access to lower level functions of the IOMMU | |
3103 | * like protection domain handling and assignement of devices to domains | |
3104 | * which is not possible with the dma_ops interface. | |
3105 | * | |
3106 | *****************************************************************************/ | |
3107 | ||
6d98cd80 JR |
3108 | static void cleanup_domain(struct protection_domain *domain) |
3109 | { | |
492667da | 3110 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 3111 | unsigned long flags; |
6d98cd80 JR |
3112 | |
3113 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3114 | ||
492667da | 3115 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3116 | __detach_device(dev_data); |
492667da JR |
3117 | atomic_set(&dev_data->bind, 0); |
3118 | } | |
6d98cd80 JR |
3119 | |
3120 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3121 | } | |
3122 | ||
2650815f JR |
3123 | static void protection_domain_free(struct protection_domain *domain) |
3124 | { | |
3125 | if (!domain) | |
3126 | return; | |
3127 | ||
aeb26f55 JR |
3128 | del_domain_from_list(domain); |
3129 | ||
2650815f JR |
3130 | if (domain->id) |
3131 | domain_id_free(domain->id); | |
3132 | ||
3133 | kfree(domain); | |
3134 | } | |
3135 | ||
3136 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3137 | { |
3138 | struct protection_domain *domain; | |
3139 | ||
3140 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3141 | if (!domain) | |
2650815f | 3142 | return NULL; |
c156e347 JR |
3143 | |
3144 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3145 | mutex_init(&domain->api_lock); |
c156e347 JR |
3146 | domain->id = domain_id_alloc(); |
3147 | if (!domain->id) | |
2650815f | 3148 | goto out_err; |
7c392cbe | 3149 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3150 | |
aeb26f55 JR |
3151 | add_domain_to_list(domain); |
3152 | ||
2650815f JR |
3153 | return domain; |
3154 | ||
3155 | out_err: | |
3156 | kfree(domain); | |
3157 | ||
3158 | return NULL; | |
3159 | } | |
3160 | ||
5abcdba4 JR |
3161 | static int __init alloc_passthrough_domain(void) |
3162 | { | |
3163 | if (pt_domain != NULL) | |
3164 | return 0; | |
3165 | ||
3166 | /* allocate passthrough domain */ | |
3167 | pt_domain = protection_domain_alloc(); | |
3168 | if (!pt_domain) | |
3169 | return -ENOMEM; | |
3170 | ||
3171 | pt_domain->mode = PAGE_MODE_NONE; | |
3172 | ||
3173 | return 0; | |
3174 | } | |
2650815f JR |
3175 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3176 | { | |
3177 | struct protection_domain *domain; | |
3178 | ||
3179 | domain = protection_domain_alloc(); | |
3180 | if (!domain) | |
c156e347 | 3181 | goto out_free; |
2650815f JR |
3182 | |
3183 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3184 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3185 | if (!domain->pt_root) | |
3186 | goto out_free; | |
3187 | ||
f3572db8 JR |
3188 | domain->iommu_domain = dom; |
3189 | ||
c156e347 JR |
3190 | dom->priv = domain; |
3191 | ||
0ff64f80 JR |
3192 | dom->geometry.aperture_start = 0; |
3193 | dom->geometry.aperture_end = ~0ULL; | |
3194 | dom->geometry.force_aperture = true; | |
3195 | ||
c156e347 JR |
3196 | return 0; |
3197 | ||
3198 | out_free: | |
2650815f | 3199 | protection_domain_free(domain); |
c156e347 JR |
3200 | |
3201 | return -ENOMEM; | |
3202 | } | |
3203 | ||
98383fc3 JR |
3204 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3205 | { | |
3206 | struct protection_domain *domain = dom->priv; | |
3207 | ||
3208 | if (!domain) | |
3209 | return; | |
3210 | ||
3211 | if (domain->dev_cnt > 0) | |
3212 | cleanup_domain(domain); | |
3213 | ||
3214 | BUG_ON(domain->dev_cnt != 0); | |
3215 | ||
132bd68f JR |
3216 | if (domain->mode != PAGE_MODE_NONE) |
3217 | free_pagetable(domain); | |
98383fc3 | 3218 | |
52815b75 JR |
3219 | if (domain->flags & PD_IOMMUV2_MASK) |
3220 | free_gcr3_table(domain); | |
3221 | ||
8b408fe4 | 3222 | protection_domain_free(domain); |
98383fc3 JR |
3223 | |
3224 | dom->priv = NULL; | |
3225 | } | |
3226 | ||
684f2888 JR |
3227 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3228 | struct device *dev) | |
3229 | { | |
657cbb6b | 3230 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3231 | struct amd_iommu *iommu; |
684f2888 JR |
3232 | u16 devid; |
3233 | ||
98fc5a69 | 3234 | if (!check_device(dev)) |
684f2888 JR |
3235 | return; |
3236 | ||
98fc5a69 | 3237 | devid = get_device_id(dev); |
684f2888 | 3238 | |
657cbb6b | 3239 | if (dev_data->domain != NULL) |
15898bbc | 3240 | detach_device(dev); |
684f2888 JR |
3241 | |
3242 | iommu = amd_iommu_rlookup_table[devid]; | |
3243 | if (!iommu) | |
3244 | return; | |
3245 | ||
684f2888 JR |
3246 | iommu_completion_wait(iommu); |
3247 | } | |
3248 | ||
01106066 JR |
3249 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3250 | struct device *dev) | |
3251 | { | |
3252 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3253 | struct iommu_dev_data *dev_data; |
01106066 | 3254 | struct amd_iommu *iommu; |
15898bbc | 3255 | int ret; |
01106066 | 3256 | |
98fc5a69 | 3257 | if (!check_device(dev)) |
01106066 JR |
3258 | return -EINVAL; |
3259 | ||
657cbb6b JR |
3260 | dev_data = dev->archdata.iommu; |
3261 | ||
f62dda66 | 3262 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3263 | if (!iommu) |
3264 | return -EINVAL; | |
3265 | ||
657cbb6b | 3266 | if (dev_data->domain) |
15898bbc | 3267 | detach_device(dev); |
01106066 | 3268 | |
15898bbc | 3269 | ret = attach_device(dev, domain); |
01106066 JR |
3270 | |
3271 | iommu_completion_wait(iommu); | |
3272 | ||
15898bbc | 3273 | return ret; |
01106066 JR |
3274 | } |
3275 | ||
468e2366 | 3276 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3277 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3278 | { |
3279 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3280 | int prot = 0; |
3281 | int ret; | |
3282 | ||
132bd68f JR |
3283 | if (domain->mode == PAGE_MODE_NONE) |
3284 | return -EINVAL; | |
3285 | ||
c6229ca6 JR |
3286 | if (iommu_prot & IOMMU_READ) |
3287 | prot |= IOMMU_PROT_IR; | |
3288 | if (iommu_prot & IOMMU_WRITE) | |
3289 | prot |= IOMMU_PROT_IW; | |
3290 | ||
5d214fe6 | 3291 | mutex_lock(&domain->api_lock); |
795e74f7 | 3292 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3293 | mutex_unlock(&domain->api_lock); |
3294 | ||
795e74f7 | 3295 | return ret; |
c6229ca6 JR |
3296 | } |
3297 | ||
5009065d OBC |
3298 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3299 | size_t page_size) | |
eb74ff6c | 3300 | { |
eb74ff6c | 3301 | struct protection_domain *domain = dom->priv; |
5009065d | 3302 | size_t unmap_size; |
eb74ff6c | 3303 | |
132bd68f JR |
3304 | if (domain->mode == PAGE_MODE_NONE) |
3305 | return -EINVAL; | |
3306 | ||
5d214fe6 | 3307 | mutex_lock(&domain->api_lock); |
468e2366 | 3308 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3309 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3310 | |
17b124bf | 3311 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3312 | |
5009065d | 3313 | return unmap_size; |
eb74ff6c JR |
3314 | } |
3315 | ||
645c4c8d JR |
3316 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3317 | unsigned long iova) | |
3318 | { | |
3319 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3320 | unsigned long offset_mask; |
645c4c8d | 3321 | phys_addr_t paddr; |
f03152bb | 3322 | u64 *pte, __pte; |
645c4c8d | 3323 | |
132bd68f JR |
3324 | if (domain->mode == PAGE_MODE_NONE) |
3325 | return iova; | |
3326 | ||
24cd7723 | 3327 | pte = fetch_pte(domain, iova); |
645c4c8d | 3328 | |
a6d41a40 | 3329 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3330 | return 0; |
3331 | ||
f03152bb JR |
3332 | if (PM_PTE_LEVEL(*pte) == 0) |
3333 | offset_mask = PAGE_SIZE - 1; | |
3334 | else | |
3335 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3336 | ||
3337 | __pte = *pte & PM_ADDR_MASK; | |
3338 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3339 | |
3340 | return paddr; | |
3341 | } | |
3342 | ||
dbb9fd86 SY |
3343 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3344 | unsigned long cap) | |
3345 | { | |
80a506b8 JR |
3346 | switch (cap) { |
3347 | case IOMMU_CAP_CACHE_COHERENCY: | |
3348 | return 1; | |
3349 | } | |
3350 | ||
dbb9fd86 SY |
3351 | return 0; |
3352 | } | |
3353 | ||
26961efe JR |
3354 | static struct iommu_ops amd_iommu_ops = { |
3355 | .domain_init = amd_iommu_domain_init, | |
3356 | .domain_destroy = amd_iommu_domain_destroy, | |
3357 | .attach_dev = amd_iommu_attach_device, | |
3358 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3359 | .map = amd_iommu_map, |
3360 | .unmap = amd_iommu_unmap, | |
26961efe | 3361 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3362 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3363 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3364 | }; |
3365 | ||
0feae533 JR |
3366 | /***************************************************************************** |
3367 | * | |
3368 | * The next functions do a basic initialization of IOMMU for pass through | |
3369 | * mode | |
3370 | * | |
3371 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3372 | * DMA-API translation. | |
3373 | * | |
3374 | *****************************************************************************/ | |
3375 | ||
3376 | int __init amd_iommu_init_passthrough(void) | |
3377 | { | |
5abcdba4 | 3378 | struct iommu_dev_data *dev_data; |
0feae533 | 3379 | struct pci_dev *dev = NULL; |
5abcdba4 | 3380 | struct amd_iommu *iommu; |
15898bbc | 3381 | u16 devid; |
5abcdba4 | 3382 | int ret; |
0feae533 | 3383 | |
5abcdba4 JR |
3384 | ret = alloc_passthrough_domain(); |
3385 | if (ret) | |
3386 | return ret; | |
0feae533 | 3387 | |
6c54aabd | 3388 | for_each_pci_dev(dev) { |
98fc5a69 | 3389 | if (!check_device(&dev->dev)) |
0feae533 JR |
3390 | continue; |
3391 | ||
5abcdba4 JR |
3392 | dev_data = get_dev_data(&dev->dev); |
3393 | dev_data->passthrough = true; | |
3394 | ||
98fc5a69 JR |
3395 | devid = get_device_id(&dev->dev); |
3396 | ||
15898bbc | 3397 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3398 | if (!iommu) |
3399 | continue; | |
3400 | ||
15898bbc | 3401 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3402 | } |
3403 | ||
2655d7a2 JR |
3404 | amd_iommu_stats_init(); |
3405 | ||
0feae533 JR |
3406 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3407 | ||
3408 | return 0; | |
3409 | } | |
72e1dcc4 JR |
3410 | |
3411 | /* IOMMUv2 specific functions */ | |
3412 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3413 | { | |
3414 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3415 | } | |
3416 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3417 | ||
3418 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3419 | { | |
3420 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3421 | } | |
3422 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3423 | |
3424 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3425 | { | |
3426 | struct protection_domain *domain = dom->priv; | |
3427 | unsigned long flags; | |
3428 | ||
3429 | spin_lock_irqsave(&domain->lock, flags); | |
3430 | ||
3431 | /* Update data structure */ | |
3432 | domain->mode = PAGE_MODE_NONE; | |
3433 | domain->updated = true; | |
3434 | ||
3435 | /* Make changes visible to IOMMUs */ | |
3436 | update_domain(domain); | |
3437 | ||
3438 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3439 | free_pagetable(domain); | |
3440 | ||
3441 | spin_unlock_irqrestore(&domain->lock, flags); | |
3442 | } | |
3443 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3444 | |
3445 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3446 | { | |
3447 | struct protection_domain *domain = dom->priv; | |
3448 | unsigned long flags; | |
3449 | int levels, ret; | |
3450 | ||
3451 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3452 | return -EINVAL; | |
3453 | ||
3454 | /* Number of GCR3 table levels required */ | |
3455 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3456 | levels += 1; | |
3457 | ||
3458 | if (levels > amd_iommu_max_glx_val) | |
3459 | return -EINVAL; | |
3460 | ||
3461 | spin_lock_irqsave(&domain->lock, flags); | |
3462 | ||
3463 | /* | |
3464 | * Save us all sanity checks whether devices already in the | |
3465 | * domain support IOMMUv2. Just force that the domain has no | |
3466 | * devices attached when it is switched into IOMMUv2 mode. | |
3467 | */ | |
3468 | ret = -EBUSY; | |
3469 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3470 | goto out; | |
3471 | ||
3472 | ret = -ENOMEM; | |
3473 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3474 | if (domain->gcr3_tbl == NULL) | |
3475 | goto out; | |
3476 | ||
3477 | domain->glx = levels; | |
3478 | domain->flags |= PD_IOMMUV2_MASK; | |
3479 | domain->updated = true; | |
3480 | ||
3481 | update_domain(domain); | |
3482 | ||
3483 | ret = 0; | |
3484 | ||
3485 | out: | |
3486 | spin_unlock_irqrestore(&domain->lock, flags); | |
3487 | ||
3488 | return ret; | |
3489 | } | |
3490 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3491 | |
3492 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3493 | u64 address, bool size) | |
3494 | { | |
3495 | struct iommu_dev_data *dev_data; | |
3496 | struct iommu_cmd cmd; | |
3497 | int i, ret; | |
3498 | ||
3499 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3500 | return -EINVAL; | |
3501 | ||
3502 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3503 | ||
3504 | /* | |
3505 | * IOMMU TLB needs to be flushed before Device TLB to | |
3506 | * prevent device TLB refill from IOMMU TLB | |
3507 | */ | |
3508 | for (i = 0; i < amd_iommus_present; ++i) { | |
3509 | if (domain->dev_iommu[i] == 0) | |
3510 | continue; | |
3511 | ||
3512 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3513 | if (ret != 0) | |
3514 | goto out; | |
3515 | } | |
3516 | ||
3517 | /* Wait until IOMMU TLB flushes are complete */ | |
3518 | domain_flush_complete(domain); | |
3519 | ||
3520 | /* Now flush device TLBs */ | |
3521 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3522 | struct amd_iommu *iommu; | |
3523 | int qdep; | |
3524 | ||
3525 | BUG_ON(!dev_data->ats.enabled); | |
3526 | ||
3527 | qdep = dev_data->ats.qdep; | |
3528 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3529 | ||
3530 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3531 | qdep, address, size); | |
3532 | ||
3533 | ret = iommu_queue_command(iommu, &cmd); | |
3534 | if (ret != 0) | |
3535 | goto out; | |
3536 | } | |
3537 | ||
3538 | /* Wait until all device TLBs are flushed */ | |
3539 | domain_flush_complete(domain); | |
3540 | ||
3541 | ret = 0; | |
3542 | ||
3543 | out: | |
3544 | ||
3545 | return ret; | |
3546 | } | |
3547 | ||
3548 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3549 | u64 address) | |
3550 | { | |
399be2f5 JR |
3551 | INC_STATS_COUNTER(invalidate_iotlb); |
3552 | ||
22e266c7 JR |
3553 | return __flush_pasid(domain, pasid, address, false); |
3554 | } | |
3555 | ||
3556 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3557 | u64 address) | |
3558 | { | |
3559 | struct protection_domain *domain = dom->priv; | |
3560 | unsigned long flags; | |
3561 | int ret; | |
3562 | ||
3563 | spin_lock_irqsave(&domain->lock, flags); | |
3564 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3565 | spin_unlock_irqrestore(&domain->lock, flags); | |
3566 | ||
3567 | return ret; | |
3568 | } | |
3569 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3570 | ||
3571 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3572 | { | |
399be2f5 JR |
3573 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3574 | ||
22e266c7 JR |
3575 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3576 | true); | |
3577 | } | |
3578 | ||
3579 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3580 | { | |
3581 | struct protection_domain *domain = dom->priv; | |
3582 | unsigned long flags; | |
3583 | int ret; | |
3584 | ||
3585 | spin_lock_irqsave(&domain->lock, flags); | |
3586 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3587 | spin_unlock_irqrestore(&domain->lock, flags); | |
3588 | ||
3589 | return ret; | |
3590 | } | |
3591 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3592 | ||
b16137b1 JR |
3593 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3594 | { | |
3595 | int index; | |
3596 | u64 *pte; | |
3597 | ||
3598 | while (true) { | |
3599 | ||
3600 | index = (pasid >> (9 * level)) & 0x1ff; | |
3601 | pte = &root[index]; | |
3602 | ||
3603 | if (level == 0) | |
3604 | break; | |
3605 | ||
3606 | if (!(*pte & GCR3_VALID)) { | |
3607 | if (!alloc) | |
3608 | return NULL; | |
3609 | ||
3610 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3611 | if (root == NULL) | |
3612 | return NULL; | |
3613 | ||
3614 | *pte = __pa(root) | GCR3_VALID; | |
3615 | } | |
3616 | ||
3617 | root = __va(*pte & PAGE_MASK); | |
3618 | ||
3619 | level -= 1; | |
3620 | } | |
3621 | ||
3622 | return pte; | |
3623 | } | |
3624 | ||
3625 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3626 | unsigned long cr3) | |
3627 | { | |
3628 | u64 *pte; | |
3629 | ||
3630 | if (domain->mode != PAGE_MODE_NONE) | |
3631 | return -EINVAL; | |
3632 | ||
3633 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3634 | if (pte == NULL) | |
3635 | return -ENOMEM; | |
3636 | ||
3637 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3638 | ||
3639 | return __amd_iommu_flush_tlb(domain, pasid); | |
3640 | } | |
3641 | ||
3642 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3643 | { | |
3644 | u64 *pte; | |
3645 | ||
3646 | if (domain->mode != PAGE_MODE_NONE) | |
3647 | return -EINVAL; | |
3648 | ||
3649 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3650 | if (pte == NULL) | |
3651 | return 0; | |
3652 | ||
3653 | *pte = 0; | |
3654 | ||
3655 | return __amd_iommu_flush_tlb(domain, pasid); | |
3656 | } | |
3657 | ||
3658 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3659 | unsigned long cr3) | |
3660 | { | |
3661 | struct protection_domain *domain = dom->priv; | |
3662 | unsigned long flags; | |
3663 | int ret; | |
3664 | ||
3665 | spin_lock_irqsave(&domain->lock, flags); | |
3666 | ret = __set_gcr3(domain, pasid, cr3); | |
3667 | spin_unlock_irqrestore(&domain->lock, flags); | |
3668 | ||
3669 | return ret; | |
3670 | } | |
3671 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3672 | ||
3673 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3674 | { | |
3675 | struct protection_domain *domain = dom->priv; | |
3676 | unsigned long flags; | |
3677 | int ret; | |
3678 | ||
3679 | spin_lock_irqsave(&domain->lock, flags); | |
3680 | ret = __clear_gcr3(domain, pasid); | |
3681 | spin_unlock_irqrestore(&domain->lock, flags); | |
3682 | ||
3683 | return ret; | |
3684 | } | |
3685 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3686 | |
3687 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3688 | int status, int tag) | |
3689 | { | |
3690 | struct iommu_dev_data *dev_data; | |
3691 | struct amd_iommu *iommu; | |
3692 | struct iommu_cmd cmd; | |
3693 | ||
399be2f5 JR |
3694 | INC_STATS_COUNTER(complete_ppr); |
3695 | ||
c99afa25 JR |
3696 | dev_data = get_dev_data(&pdev->dev); |
3697 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3698 | ||
3699 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3700 | tag, dev_data->pri_tlp); | |
3701 | ||
3702 | return iommu_queue_command(iommu, &cmd); | |
3703 | } | |
3704 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3705 | |
3706 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3707 | { | |
3708 | struct protection_domain *domain; | |
3709 | ||
3710 | domain = get_domain(&pdev->dev); | |
3711 | if (IS_ERR(domain)) | |
3712 | return NULL; | |
3713 | ||
3714 | /* Only return IOMMUv2 domains */ | |
3715 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3716 | return NULL; | |
3717 | ||
3718 | return domain->iommu_domain; | |
3719 | } | |
3720 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3721 | |
3722 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3723 | { | |
3724 | struct iommu_dev_data *dev_data; | |
3725 | ||
3726 | if (!amd_iommu_v2_supported()) | |
3727 | return; | |
3728 | ||
3729 | dev_data = get_dev_data(&pdev->dev); | |
3730 | dev_data->errata |= (1 << erratum); | |
3731 | } | |
3732 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3733 | |
3734 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3735 | struct amd_iommu_device_info *info) | |
3736 | { | |
3737 | int max_pasids; | |
3738 | int pos; | |
3739 | ||
3740 | if (pdev == NULL || info == NULL) | |
3741 | return -EINVAL; | |
3742 | ||
3743 | if (!amd_iommu_v2_supported()) | |
3744 | return -EINVAL; | |
3745 | ||
3746 | memset(info, 0, sizeof(*info)); | |
3747 | ||
3748 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3749 | if (pos) | |
3750 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3751 | ||
3752 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3753 | if (pos) | |
3754 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3755 | ||
3756 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3757 | if (pos) { | |
3758 | int features; | |
3759 | ||
3760 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3761 | max_pasids = min(max_pasids, (1 << 20)); | |
3762 | ||
3763 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3764 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3765 | ||
3766 | features = pci_pasid_features(pdev); | |
3767 | if (features & PCI_PASID_CAP_EXEC) | |
3768 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3769 | if (features & PCI_PASID_CAP_PRIV) | |
3770 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3771 | } | |
3772 | ||
3773 | return 0; | |
3774 | } | |
3775 | EXPORT_SYMBOL(amd_iommu_device_info); |