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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
cb41ed85 | 21 | #include <linux/pci-ats.h> |
a66022c4 | 22 | #include <linux/bitmap.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
7f26508b | 24 | #include <linux/debugfs.h> |
b6c02715 | 25 | #include <linux/scatterlist.h> |
51491367 | 26 | #include <linux/dma-mapping.h> |
b6c02715 | 27 | #include <linux/iommu-helper.h> |
c156e347 | 28 | #include <linux/iommu.h> |
815b33fd | 29 | #include <linux/delay.h> |
403f81d8 | 30 | #include <linux/amd-iommu.h> |
b6c02715 | 31 | #include <asm/proto.h> |
46a7fa27 | 32 | #include <asm/iommu.h> |
1d9b16d1 | 33 | #include <asm/gart.h> |
27c2127a | 34 | #include <asm/dma.h> |
403f81d8 JR |
35 | |
36 | #include "amd_iommu_proto.h" | |
37 | #include "amd_iommu_types.h" | |
b6c02715 JR |
38 | |
39 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
40 | ||
815b33fd | 41 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 42 | |
b6c02715 JR |
43 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
44 | ||
bd60b735 JR |
45 | /* A list of preallocated protection domains */ |
46 | static LIST_HEAD(iommu_pd_list); | |
47 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
48 | ||
8fa5f802 JR |
49 | /* List of all available dev_data structures */ |
50 | static LIST_HEAD(dev_data_list); | |
51 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
52 | ||
0feae533 JR |
53 | /* |
54 | * Domain for untranslated devices - only allocated | |
55 | * if iommu=pt passed on kernel cmd line. | |
56 | */ | |
57 | static struct protection_domain *pt_domain; | |
58 | ||
26961efe | 59 | static struct iommu_ops amd_iommu_ops; |
26961efe | 60 | |
431b2a20 JR |
61 | /* |
62 | * general struct to manage commands send to an IOMMU | |
63 | */ | |
d6449536 | 64 | struct iommu_cmd { |
b6c02715 JR |
65 | u32 data[4]; |
66 | }; | |
67 | ||
04bfdd84 | 68 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 69 | |
15898bbc JR |
70 | /**************************************************************************** |
71 | * | |
72 | * Helper functions | |
73 | * | |
74 | ****************************************************************************/ | |
75 | ||
f62dda66 | 76 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
77 | { |
78 | struct iommu_dev_data *dev_data; | |
79 | unsigned long flags; | |
80 | ||
81 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
82 | if (!dev_data) | |
83 | return NULL; | |
84 | ||
f62dda66 | 85 | dev_data->devid = devid; |
8fa5f802 JR |
86 | atomic_set(&dev_data->bind, 0); |
87 | ||
88 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
89 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
90 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
91 | ||
92 | return dev_data; | |
93 | } | |
94 | ||
95 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
96 | { | |
97 | unsigned long flags; | |
98 | ||
99 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
100 | list_del(&dev_data->dev_data_list); | |
101 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
102 | ||
103 | kfree(dev_data); | |
104 | } | |
105 | ||
3b03bb74 JR |
106 | static struct iommu_dev_data *search_dev_data(u16 devid) |
107 | { | |
108 | struct iommu_dev_data *dev_data; | |
109 | unsigned long flags; | |
110 | ||
111 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
112 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
113 | if (dev_data->devid == devid) | |
114 | goto out_unlock; | |
115 | } | |
116 | ||
117 | dev_data = NULL; | |
118 | ||
119 | out_unlock: | |
120 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
121 | ||
122 | return dev_data; | |
123 | } | |
124 | ||
125 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
126 | { | |
127 | struct iommu_dev_data *dev_data; | |
128 | ||
129 | dev_data = search_dev_data(devid); | |
130 | ||
131 | if (dev_data == NULL) | |
132 | dev_data = alloc_dev_data(devid); | |
133 | ||
134 | return dev_data; | |
135 | } | |
136 | ||
15898bbc JR |
137 | static inline u16 get_device_id(struct device *dev) |
138 | { | |
139 | struct pci_dev *pdev = to_pci_dev(dev); | |
140 | ||
141 | return calc_devid(pdev->bus->number, pdev->devfn); | |
142 | } | |
143 | ||
657cbb6b JR |
144 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
145 | { | |
146 | return dev->archdata.iommu; | |
147 | } | |
148 | ||
71c70984 JR |
149 | /* |
150 | * In this function the list of preallocated protection domains is traversed to | |
151 | * find the domain for a specific device | |
152 | */ | |
153 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
154 | { | |
155 | struct dma_ops_domain *entry, *ret = NULL; | |
156 | unsigned long flags; | |
157 | u16 alias = amd_iommu_alias_table[devid]; | |
158 | ||
159 | if (list_empty(&iommu_pd_list)) | |
160 | return NULL; | |
161 | ||
162 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
163 | ||
164 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
165 | if (entry->target_dev == devid || | |
166 | entry->target_dev == alias) { | |
167 | ret = entry; | |
168 | break; | |
169 | } | |
170 | } | |
171 | ||
172 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
173 | ||
174 | return ret; | |
175 | } | |
176 | ||
98fc5a69 JR |
177 | /* |
178 | * This function checks if the driver got a valid device from the caller to | |
179 | * avoid dereferencing invalid pointers. | |
180 | */ | |
181 | static bool check_device(struct device *dev) | |
182 | { | |
183 | u16 devid; | |
184 | ||
185 | if (!dev || !dev->dma_mask) | |
186 | return false; | |
187 | ||
188 | /* No device or no PCI device */ | |
339d3261 | 189 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
190 | return false; |
191 | ||
192 | devid = get_device_id(dev); | |
193 | ||
194 | /* Out of our scope? */ | |
195 | if (devid > amd_iommu_last_bdf) | |
196 | return false; | |
197 | ||
198 | if (amd_iommu_rlookup_table[devid] == NULL) | |
199 | return false; | |
200 | ||
201 | return true; | |
202 | } | |
203 | ||
657cbb6b JR |
204 | static int iommu_init_device(struct device *dev) |
205 | { | |
206 | struct iommu_dev_data *dev_data; | |
8fa5f802 | 207 | u16 alias; |
657cbb6b JR |
208 | |
209 | if (dev->archdata.iommu) | |
210 | return 0; | |
211 | ||
3b03bb74 | 212 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
213 | if (!dev_data) |
214 | return -ENOMEM; | |
215 | ||
f62dda66 | 216 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 217 | if (alias != dev_data->devid) { |
71f77580 | 218 | struct iommu_dev_data *alias_data; |
b00d3bcf | 219 | |
71f77580 JR |
220 | alias_data = find_dev_data(alias); |
221 | if (alias_data == NULL) { | |
222 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
223 | dev_name(dev)); | |
2b02b091 JR |
224 | free_dev_data(dev_data); |
225 | return -ENOTSUPP; | |
226 | } | |
71f77580 | 227 | dev_data->alias_data = alias_data; |
26018874 | 228 | } |
657cbb6b JR |
229 | |
230 | dev->archdata.iommu = dev_data; | |
231 | ||
657cbb6b JR |
232 | return 0; |
233 | } | |
234 | ||
26018874 JR |
235 | static void iommu_ignore_device(struct device *dev) |
236 | { | |
237 | u16 devid, alias; | |
238 | ||
239 | devid = get_device_id(dev); | |
240 | alias = amd_iommu_alias_table[devid]; | |
241 | ||
242 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
243 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
244 | ||
245 | amd_iommu_rlookup_table[devid] = NULL; | |
246 | amd_iommu_rlookup_table[alias] = NULL; | |
247 | } | |
248 | ||
657cbb6b JR |
249 | static void iommu_uninit_device(struct device *dev) |
250 | { | |
8fa5f802 JR |
251 | /* |
252 | * Nothing to do here - we keep dev_data around for unplugged devices | |
253 | * and reuse it when the device is re-plugged - not doing so would | |
254 | * introduce a ton of races. | |
255 | */ | |
657cbb6b | 256 | } |
b7cc9554 JR |
257 | |
258 | void __init amd_iommu_uninit_devices(void) | |
259 | { | |
8fa5f802 | 260 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
261 | struct pci_dev *pdev = NULL; |
262 | ||
263 | for_each_pci_dev(pdev) { | |
264 | ||
265 | if (!check_device(&pdev->dev)) | |
266 | continue; | |
267 | ||
268 | iommu_uninit_device(&pdev->dev); | |
269 | } | |
8fa5f802 JR |
270 | |
271 | /* Free all of our dev_data structures */ | |
272 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
273 | free_dev_data(dev_data); | |
b7cc9554 JR |
274 | } |
275 | ||
276 | int __init amd_iommu_init_devices(void) | |
277 | { | |
278 | struct pci_dev *pdev = NULL; | |
279 | int ret = 0; | |
280 | ||
281 | for_each_pci_dev(pdev) { | |
282 | ||
283 | if (!check_device(&pdev->dev)) | |
284 | continue; | |
285 | ||
286 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
287 | if (ret == -ENOTSUPP) |
288 | iommu_ignore_device(&pdev->dev); | |
289 | else if (ret) | |
b7cc9554 JR |
290 | goto out_free; |
291 | } | |
292 | ||
293 | return 0; | |
294 | ||
295 | out_free: | |
296 | ||
297 | amd_iommu_uninit_devices(); | |
298 | ||
299 | return ret; | |
300 | } | |
7f26508b JR |
301 | #ifdef CONFIG_AMD_IOMMU_STATS |
302 | ||
303 | /* | |
304 | * Initialization code for statistics collection | |
305 | */ | |
306 | ||
da49f6df | 307 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 308 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 309 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 310 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 311 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 312 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 313 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 314 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 315 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 316 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 317 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 318 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 319 | |
7f26508b | 320 | static struct dentry *stats_dir; |
7f26508b JR |
321 | static struct dentry *de_fflush; |
322 | ||
323 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
324 | { | |
325 | if (stats_dir == NULL) | |
326 | return; | |
327 | ||
328 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
329 | &cnt->value); | |
330 | } | |
331 | ||
332 | static void amd_iommu_stats_init(void) | |
333 | { | |
334 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
335 | if (stats_dir == NULL) | |
336 | return; | |
337 | ||
7f26508b JR |
338 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
339 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
340 | |
341 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 342 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 343 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 344 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 345 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 346 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 347 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 348 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 349 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 350 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 351 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 352 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
353 | } |
354 | ||
355 | #endif | |
356 | ||
a80dc3e0 JR |
357 | /**************************************************************************** |
358 | * | |
359 | * Interrupt handling functions | |
360 | * | |
361 | ****************************************************************************/ | |
362 | ||
e3e59876 JR |
363 | static void dump_dte_entry(u16 devid) |
364 | { | |
365 | int i; | |
366 | ||
367 | for (i = 0; i < 8; ++i) | |
368 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
369 | amd_iommu_dev_table[devid].data[i]); | |
370 | } | |
371 | ||
945b4ac4 JR |
372 | static void dump_command(unsigned long phys_addr) |
373 | { | |
374 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
375 | int i; | |
376 | ||
377 | for (i = 0; i < 4; ++i) | |
378 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
379 | } | |
380 | ||
a345b23b | 381 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
382 | { |
383 | u32 *event = __evt; | |
384 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
385 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
386 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
387 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
388 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
389 | ||
4c6f40d4 | 390 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
391 | |
392 | switch (type) { | |
393 | case EVENT_TYPE_ILL_DEV: | |
394 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
395 | "address=0x%016llx flags=0x%04x]\n", | |
396 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
397 | address, flags); | |
e3e59876 | 398 | dump_dte_entry(devid); |
90008ee4 JR |
399 | break; |
400 | case EVENT_TYPE_IO_FAULT: | |
401 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
402 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
403 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
404 | domid, address, flags); | |
405 | break; | |
406 | case EVENT_TYPE_DEV_TAB_ERR: | |
407 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
408 | "address=0x%016llx flags=0x%04x]\n", | |
409 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
410 | address, flags); | |
411 | break; | |
412 | case EVENT_TYPE_PAGE_TAB_ERR: | |
413 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
414 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
415 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
416 | domid, address, flags); | |
417 | break; | |
418 | case EVENT_TYPE_ILL_CMD: | |
419 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 420 | dump_command(address); |
90008ee4 JR |
421 | break; |
422 | case EVENT_TYPE_CMD_HARD_ERR: | |
423 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
424 | "flags=0x%04x]\n", address, flags); | |
425 | break; | |
426 | case EVENT_TYPE_IOTLB_INV_TO: | |
427 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
428 | "address=0x%016llx]\n", | |
429 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
430 | address); | |
431 | break; | |
432 | case EVENT_TYPE_INV_DEV_REQ: | |
433 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
434 | "address=0x%016llx flags=0x%04x]\n", | |
435 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
436 | address, flags); | |
437 | break; | |
438 | default: | |
439 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
440 | } | |
441 | } | |
442 | ||
443 | static void iommu_poll_events(struct amd_iommu *iommu) | |
444 | { | |
445 | u32 head, tail; | |
446 | unsigned long flags; | |
447 | ||
448 | spin_lock_irqsave(&iommu->lock, flags); | |
449 | ||
450 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
451 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
452 | ||
453 | while (head != tail) { | |
a345b23b | 454 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
455 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
456 | } | |
457 | ||
458 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
459 | ||
460 | spin_unlock_irqrestore(&iommu->lock, flags); | |
461 | } | |
462 | ||
72fe00f0 | 463 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 464 | { |
90008ee4 JR |
465 | struct amd_iommu *iommu; |
466 | ||
3bd22172 | 467 | for_each_iommu(iommu) |
90008ee4 JR |
468 | iommu_poll_events(iommu); |
469 | ||
470 | return IRQ_HANDLED; | |
a80dc3e0 JR |
471 | } |
472 | ||
72fe00f0 JR |
473 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
474 | { | |
475 | return IRQ_WAKE_THREAD; | |
476 | } | |
477 | ||
431b2a20 JR |
478 | /**************************************************************************** |
479 | * | |
480 | * IOMMU command queuing functions | |
481 | * | |
482 | ****************************************************************************/ | |
483 | ||
ac0ea6e9 JR |
484 | static int wait_on_sem(volatile u64 *sem) |
485 | { | |
486 | int i = 0; | |
487 | ||
488 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
489 | udelay(1); | |
490 | i += 1; | |
491 | } | |
492 | ||
493 | if (i == LOOP_TIMEOUT) { | |
494 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
495 | return -EIO; | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
502 | struct iommu_cmd *cmd, | |
503 | u32 tail) | |
a19ae1ec | 504 | { |
a19ae1ec JR |
505 | u8 *target; |
506 | ||
8a7c5ef3 | 507 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
508 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
509 | ||
510 | /* Copy command to buffer */ | |
511 | memcpy(target, cmd, sizeof(*cmd)); | |
512 | ||
513 | /* Tell the IOMMU about it */ | |
a19ae1ec | 514 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 515 | } |
a19ae1ec | 516 | |
815b33fd | 517 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 518 | { |
815b33fd JR |
519 | WARN_ON(address & 0x7ULL); |
520 | ||
ded46737 | 521 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
522 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
523 | cmd->data[1] = upper_32_bits(__pa(address)); | |
524 | cmd->data[2] = 1; | |
ded46737 JR |
525 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
526 | } | |
527 | ||
94fe79e2 JR |
528 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
529 | { | |
530 | memset(cmd, 0, sizeof(*cmd)); | |
531 | cmd->data[0] = devid; | |
532 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
533 | } | |
534 | ||
11b6402c JR |
535 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
536 | size_t size, u16 domid, int pde) | |
537 | { | |
538 | u64 pages; | |
539 | int s; | |
540 | ||
541 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
542 | s = 0; | |
543 | ||
544 | if (pages > 1) { | |
545 | /* | |
546 | * If we have to flush more than one page, flush all | |
547 | * TLB entries for this domain | |
548 | */ | |
549 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
550 | s = 1; | |
551 | } | |
552 | ||
553 | address &= PAGE_MASK; | |
554 | ||
555 | memset(cmd, 0, sizeof(*cmd)); | |
556 | cmd->data[1] |= domid; | |
557 | cmd->data[2] = lower_32_bits(address); | |
558 | cmd->data[3] = upper_32_bits(address); | |
559 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
560 | if (s) /* size bit - we flush more than one 4kb page */ | |
561 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
562 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
563 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
564 | } | |
565 | ||
cb41ed85 JR |
566 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
567 | u64 address, size_t size) | |
568 | { | |
569 | u64 pages; | |
570 | int s; | |
571 | ||
572 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
573 | s = 0; | |
574 | ||
575 | if (pages > 1) { | |
576 | /* | |
577 | * If we have to flush more than one page, flush all | |
578 | * TLB entries for this domain | |
579 | */ | |
580 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
581 | s = 1; | |
582 | } | |
583 | ||
584 | address &= PAGE_MASK; | |
585 | ||
586 | memset(cmd, 0, sizeof(*cmd)); | |
587 | cmd->data[0] = devid; | |
588 | cmd->data[0] |= (qdep & 0xff) << 24; | |
589 | cmd->data[1] = devid; | |
590 | cmd->data[2] = lower_32_bits(address); | |
591 | cmd->data[3] = upper_32_bits(address); | |
592 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
593 | if (s) | |
594 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
595 | } | |
596 | ||
58fc7f14 JR |
597 | static void build_inv_all(struct iommu_cmd *cmd) |
598 | { | |
599 | memset(cmd, 0, sizeof(*cmd)); | |
600 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
601 | } |
602 | ||
431b2a20 | 603 | /* |
431b2a20 | 604 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 605 | * hardware about the new command. |
431b2a20 | 606 | */ |
d6449536 | 607 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec | 608 | { |
ac0ea6e9 | 609 | u32 left, tail, head, next_tail; |
a19ae1ec | 610 | unsigned long flags; |
a19ae1ec | 611 | |
549c90dc | 612 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
613 | |
614 | again: | |
a19ae1ec | 615 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 616 | |
ac0ea6e9 JR |
617 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
618 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
619 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
620 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 621 | |
ac0ea6e9 JR |
622 | if (left <= 2) { |
623 | struct iommu_cmd sync_cmd; | |
624 | volatile u64 sem = 0; | |
625 | int ret; | |
8d201968 | 626 | |
ac0ea6e9 JR |
627 | build_completion_wait(&sync_cmd, (u64)&sem); |
628 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 629 | |
ac0ea6e9 JR |
630 | spin_unlock_irqrestore(&iommu->lock, flags); |
631 | ||
632 | if ((ret = wait_on_sem(&sem)) != 0) | |
633 | return ret; | |
634 | ||
635 | goto again; | |
8d201968 JR |
636 | } |
637 | ||
ac0ea6e9 JR |
638 | copy_cmd_to_buffer(iommu, cmd, tail); |
639 | ||
640 | /* We need to sync now to make sure all commands are processed */ | |
815b33fd | 641 | iommu->need_sync = true; |
ac0ea6e9 | 642 | |
a19ae1ec | 643 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 644 | |
815b33fd | 645 | return 0; |
8d201968 JR |
646 | } |
647 | ||
648 | /* | |
649 | * This function queues a completion wait command into the command | |
650 | * buffer of an IOMMU | |
651 | */ | |
a19ae1ec | 652 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
653 | { |
654 | struct iommu_cmd cmd; | |
815b33fd | 655 | volatile u64 sem = 0; |
ac0ea6e9 | 656 | int ret; |
8d201968 | 657 | |
09ee17eb | 658 | if (!iommu->need_sync) |
815b33fd | 659 | return 0; |
09ee17eb | 660 | |
815b33fd | 661 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 662 | |
815b33fd | 663 | ret = iommu_queue_command(iommu, &cmd); |
a19ae1ec | 664 | if (ret) |
815b33fd | 665 | return ret; |
8d201968 | 666 | |
ac0ea6e9 | 667 | return wait_on_sem(&sem); |
8d201968 JR |
668 | } |
669 | ||
d8c13085 | 670 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 671 | { |
d8c13085 | 672 | struct iommu_cmd cmd; |
a19ae1ec | 673 | |
d8c13085 | 674 | build_inv_dte(&cmd, devid); |
7e4f88da | 675 | |
d8c13085 JR |
676 | return iommu_queue_command(iommu, &cmd); |
677 | } | |
09ee17eb | 678 | |
7d0c5cc5 JR |
679 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
680 | { | |
681 | u32 devid; | |
09ee17eb | 682 | |
7d0c5cc5 JR |
683 | for (devid = 0; devid <= 0xffff; ++devid) |
684 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 685 | |
7d0c5cc5 JR |
686 | iommu_completion_wait(iommu); |
687 | } | |
84df8175 | 688 | |
7d0c5cc5 JR |
689 | /* |
690 | * This function uses heavy locking and may disable irqs for some time. But | |
691 | * this is no issue because it is only called during resume. | |
692 | */ | |
693 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
694 | { | |
695 | u32 dom_id; | |
a19ae1ec | 696 | |
7d0c5cc5 JR |
697 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
698 | struct iommu_cmd cmd; | |
699 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
700 | dom_id, 1); | |
701 | iommu_queue_command(iommu, &cmd); | |
702 | } | |
8eed9833 | 703 | |
7d0c5cc5 | 704 | iommu_completion_wait(iommu); |
a19ae1ec JR |
705 | } |
706 | ||
58fc7f14 | 707 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 708 | { |
58fc7f14 | 709 | struct iommu_cmd cmd; |
0518a3a4 | 710 | |
58fc7f14 | 711 | build_inv_all(&cmd); |
0518a3a4 | 712 | |
58fc7f14 JR |
713 | iommu_queue_command(iommu, &cmd); |
714 | iommu_completion_wait(iommu); | |
715 | } | |
716 | ||
7d0c5cc5 JR |
717 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
718 | { | |
58fc7f14 JR |
719 | if (iommu_feature(iommu, FEATURE_IA)) { |
720 | iommu_flush_all(iommu); | |
721 | } else { | |
722 | iommu_flush_dte_all(iommu); | |
723 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
724 | } |
725 | } | |
726 | ||
431b2a20 | 727 | /* |
cb41ed85 | 728 | * Command send function for flushing on-device TLB |
431b2a20 | 729 | */ |
6c542047 JR |
730 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
731 | u64 address, size_t size) | |
3fa43655 JR |
732 | { |
733 | struct amd_iommu *iommu; | |
b00d3bcf | 734 | struct iommu_cmd cmd; |
cb41ed85 | 735 | int qdep; |
3fa43655 | 736 | |
ea61cddb JR |
737 | qdep = dev_data->ats.qdep; |
738 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 739 | |
ea61cddb | 740 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
741 | |
742 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
743 | } |
744 | ||
431b2a20 | 745 | /* |
431b2a20 | 746 | * Command send function for invalidating a device table entry |
431b2a20 | 747 | */ |
6c542047 | 748 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 749 | { |
3fa43655 | 750 | struct amd_iommu *iommu; |
ee2fa743 | 751 | int ret; |
a19ae1ec | 752 | |
6c542047 | 753 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 754 | |
f62dda66 | 755 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
756 | if (ret) |
757 | return ret; | |
758 | ||
ea61cddb | 759 | if (dev_data->ats.enabled) |
6c542047 | 760 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 761 | |
ee2fa743 | 762 | return ret; |
a19ae1ec JR |
763 | } |
764 | ||
431b2a20 JR |
765 | /* |
766 | * TLB invalidation function which is called from the mapping functions. | |
767 | * It invalidates a single PTE if the range to flush is within a single | |
768 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
769 | */ | |
17b124bf JR |
770 | static void __domain_flush_pages(struct protection_domain *domain, |
771 | u64 address, size_t size, int pde) | |
a19ae1ec | 772 | { |
cb41ed85 | 773 | struct iommu_dev_data *dev_data; |
11b6402c JR |
774 | struct iommu_cmd cmd; |
775 | int ret = 0, i; | |
a19ae1ec | 776 | |
11b6402c | 777 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 778 | |
6de8ad9b JR |
779 | for (i = 0; i < amd_iommus_present; ++i) { |
780 | if (!domain->dev_iommu[i]) | |
781 | continue; | |
782 | ||
783 | /* | |
784 | * Devices of this domain are behind this IOMMU | |
785 | * We need a TLB flush | |
786 | */ | |
11b6402c | 787 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
788 | } |
789 | ||
cb41ed85 | 790 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 791 | |
ea61cddb | 792 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
793 | continue; |
794 | ||
6c542047 | 795 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
796 | } |
797 | ||
11b6402c | 798 | WARN_ON(ret); |
6de8ad9b JR |
799 | } |
800 | ||
17b124bf JR |
801 | static void domain_flush_pages(struct protection_domain *domain, |
802 | u64 address, size_t size) | |
6de8ad9b | 803 | { |
17b124bf | 804 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 805 | } |
b6c02715 | 806 | |
1c655773 | 807 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 808 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 809 | { |
17b124bf | 810 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
811 | } |
812 | ||
42a49f96 | 813 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 814 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 815 | { |
17b124bf | 816 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
817 | } |
818 | ||
17b124bf | 819 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 820 | { |
17b124bf | 821 | int i; |
18811f55 | 822 | |
17b124bf JR |
823 | for (i = 0; i < amd_iommus_present; ++i) { |
824 | if (!domain->dev_iommu[i]) | |
825 | continue; | |
bfd1be18 | 826 | |
17b124bf JR |
827 | /* |
828 | * Devices of this domain are behind this IOMMU | |
829 | * We need to wait for completion of all commands. | |
830 | */ | |
831 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 832 | } |
e394d72a JR |
833 | } |
834 | ||
b00d3bcf | 835 | |
09b42804 | 836 | /* |
b00d3bcf | 837 | * This function flushes the DTEs for all devices in domain |
09b42804 | 838 | */ |
17b124bf | 839 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 840 | { |
b00d3bcf | 841 | struct iommu_dev_data *dev_data; |
09b42804 JR |
842 | unsigned long flags; |
843 | ||
b00d3bcf | 844 | spin_lock_irqsave(&domain->lock, flags); |
b26e81b8 | 845 | |
b00d3bcf | 846 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 847 | device_flush_dte(dev_data); |
b26e81b8 | 848 | |
b00d3bcf | 849 | spin_unlock_irqrestore(&domain->lock, flags); |
a345b23b JR |
850 | } |
851 | ||
431b2a20 JR |
852 | /**************************************************************************** |
853 | * | |
854 | * The functions below are used the create the page table mappings for | |
855 | * unity mapped regions. | |
856 | * | |
857 | ****************************************************************************/ | |
858 | ||
308973d3 JR |
859 | /* |
860 | * This function is used to add another level to an IO page table. Adding | |
861 | * another level increases the size of the address space by 9 bits to a size up | |
862 | * to 64 bits. | |
863 | */ | |
864 | static bool increase_address_space(struct protection_domain *domain, | |
865 | gfp_t gfp) | |
866 | { | |
867 | u64 *pte; | |
868 | ||
869 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
870 | /* address space already 64 bit large */ | |
871 | return false; | |
872 | ||
873 | pte = (void *)get_zeroed_page(gfp); | |
874 | if (!pte) | |
875 | return false; | |
876 | ||
877 | *pte = PM_LEVEL_PDE(domain->mode, | |
878 | virt_to_phys(domain->pt_root)); | |
879 | domain->pt_root = pte; | |
880 | domain->mode += 1; | |
881 | domain->updated = true; | |
882 | ||
883 | return true; | |
884 | } | |
885 | ||
886 | static u64 *alloc_pte(struct protection_domain *domain, | |
887 | unsigned long address, | |
cbb9d729 | 888 | unsigned long page_size, |
308973d3 JR |
889 | u64 **pte_page, |
890 | gfp_t gfp) | |
891 | { | |
cbb9d729 | 892 | int level, end_lvl; |
308973d3 | 893 | u64 *pte, *page; |
cbb9d729 JR |
894 | |
895 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
896 | |
897 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
898 | increase_address_space(domain, gfp); | |
899 | ||
cbb9d729 JR |
900 | level = domain->mode - 1; |
901 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
902 | address = PAGE_SIZE_ALIGN(address, page_size); | |
903 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
904 | |
905 | while (level > end_lvl) { | |
906 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
907 | page = (u64 *)get_zeroed_page(gfp); | |
908 | if (!page) | |
909 | return NULL; | |
910 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
911 | } | |
912 | ||
cbb9d729 JR |
913 | /* No level skipping support yet */ |
914 | if (PM_PTE_LEVEL(*pte) != level) | |
915 | return NULL; | |
916 | ||
308973d3 JR |
917 | level -= 1; |
918 | ||
919 | pte = IOMMU_PTE_PAGE(*pte); | |
920 | ||
921 | if (pte_page && level == end_lvl) | |
922 | *pte_page = pte; | |
923 | ||
924 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
925 | } | |
926 | ||
927 | return pte; | |
928 | } | |
929 | ||
930 | /* | |
931 | * This function checks if there is a PTE for a given dma address. If | |
932 | * there is one, it returns the pointer to it. | |
933 | */ | |
24cd7723 | 934 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
935 | { |
936 | int level; | |
937 | u64 *pte; | |
938 | ||
24cd7723 JR |
939 | if (address > PM_LEVEL_SIZE(domain->mode)) |
940 | return NULL; | |
941 | ||
942 | level = domain->mode - 1; | |
943 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 944 | |
24cd7723 JR |
945 | while (level > 0) { |
946 | ||
947 | /* Not Present */ | |
308973d3 JR |
948 | if (!IOMMU_PTE_PRESENT(*pte)) |
949 | return NULL; | |
950 | ||
24cd7723 JR |
951 | /* Large PTE */ |
952 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
953 | unsigned long pte_mask, __pte; | |
954 | ||
955 | /* | |
956 | * If we have a series of large PTEs, make | |
957 | * sure to return a pointer to the first one. | |
958 | */ | |
959 | pte_mask = PTE_PAGE_SIZE(*pte); | |
960 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
961 | __pte = ((unsigned long)pte) & pte_mask; | |
962 | ||
963 | return (u64 *)__pte; | |
964 | } | |
965 | ||
966 | /* No level skipping support yet */ | |
967 | if (PM_PTE_LEVEL(*pte) != level) | |
968 | return NULL; | |
969 | ||
308973d3 JR |
970 | level -= 1; |
971 | ||
24cd7723 | 972 | /* Walk to the next level */ |
308973d3 JR |
973 | pte = IOMMU_PTE_PAGE(*pte); |
974 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
975 | } |
976 | ||
977 | return pte; | |
978 | } | |
979 | ||
431b2a20 JR |
980 | /* |
981 | * Generic mapping functions. It maps a physical address into a DMA | |
982 | * address space. It allocates the page table pages if necessary. | |
983 | * In the future it can be extended to a generic mapping function | |
984 | * supporting all features of AMD IOMMU page tables like level skipping | |
985 | * and full 64 bit address spaces. | |
986 | */ | |
38e817fe JR |
987 | static int iommu_map_page(struct protection_domain *dom, |
988 | unsigned long bus_addr, | |
989 | unsigned long phys_addr, | |
abdc5eb3 | 990 | int prot, |
cbb9d729 | 991 | unsigned long page_size) |
bd0e5211 | 992 | { |
8bda3092 | 993 | u64 __pte, *pte; |
cbb9d729 | 994 | int i, count; |
abdc5eb3 | 995 | |
bad1cac2 | 996 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
997 | return -EINVAL; |
998 | ||
cbb9d729 JR |
999 | bus_addr = PAGE_ALIGN(bus_addr); |
1000 | phys_addr = PAGE_ALIGN(phys_addr); | |
1001 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1002 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1003 | ||
1004 | for (i = 0; i < count; ++i) | |
1005 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1006 | return -EBUSY; | |
bd0e5211 | 1007 | |
cbb9d729 JR |
1008 | if (page_size > PAGE_SIZE) { |
1009 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1010 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1011 | } else | |
1012 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1013 | |
bd0e5211 JR |
1014 | if (prot & IOMMU_PROT_IR) |
1015 | __pte |= IOMMU_PTE_IR; | |
1016 | if (prot & IOMMU_PROT_IW) | |
1017 | __pte |= IOMMU_PTE_IW; | |
1018 | ||
cbb9d729 JR |
1019 | for (i = 0; i < count; ++i) |
1020 | pte[i] = __pte; | |
bd0e5211 | 1021 | |
04bfdd84 JR |
1022 | update_domain(dom); |
1023 | ||
bd0e5211 JR |
1024 | return 0; |
1025 | } | |
1026 | ||
24cd7723 JR |
1027 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1028 | unsigned long bus_addr, | |
1029 | unsigned long page_size) | |
eb74ff6c | 1030 | { |
24cd7723 JR |
1031 | unsigned long long unmap_size, unmapped; |
1032 | u64 *pte; | |
1033 | ||
1034 | BUG_ON(!is_power_of_2(page_size)); | |
1035 | ||
1036 | unmapped = 0; | |
eb74ff6c | 1037 | |
24cd7723 JR |
1038 | while (unmapped < page_size) { |
1039 | ||
1040 | pte = fetch_pte(dom, bus_addr); | |
1041 | ||
1042 | if (!pte) { | |
1043 | /* | |
1044 | * No PTE for this address | |
1045 | * move forward in 4kb steps | |
1046 | */ | |
1047 | unmap_size = PAGE_SIZE; | |
1048 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1049 | /* 4kb PTE found for this address */ | |
1050 | unmap_size = PAGE_SIZE; | |
1051 | *pte = 0ULL; | |
1052 | } else { | |
1053 | int count, i; | |
1054 | ||
1055 | /* Large PTE found which maps this address */ | |
1056 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1057 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1058 | for (i = 0; i < count; i++) | |
1059 | pte[i] = 0ULL; | |
1060 | } | |
1061 | ||
1062 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1063 | unmapped += unmap_size; | |
1064 | } | |
1065 | ||
1066 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1067 | |
24cd7723 | 1068 | return unmapped; |
eb74ff6c | 1069 | } |
eb74ff6c | 1070 | |
431b2a20 JR |
1071 | /* |
1072 | * This function checks if a specific unity mapping entry is needed for | |
1073 | * this specific IOMMU. | |
1074 | */ | |
bd0e5211 JR |
1075 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1076 | struct unity_map_entry *entry) | |
1077 | { | |
1078 | u16 bdf, i; | |
1079 | ||
1080 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1081 | bdf = amd_iommu_alias_table[i]; | |
1082 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1083 | return 1; | |
1084 | } | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
431b2a20 JR |
1089 | /* |
1090 | * This function actually applies the mapping to the page table of the | |
1091 | * dma_ops domain. | |
1092 | */ | |
bd0e5211 JR |
1093 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1094 | struct unity_map_entry *e) | |
1095 | { | |
1096 | u64 addr; | |
1097 | int ret; | |
1098 | ||
1099 | for (addr = e->address_start; addr < e->address_end; | |
1100 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1101 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1102 | PAGE_SIZE); |
bd0e5211 JR |
1103 | if (ret) |
1104 | return ret; | |
1105 | /* | |
1106 | * if unity mapping is in aperture range mark the page | |
1107 | * as allocated in the aperture | |
1108 | */ | |
1109 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1110 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1111 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1112 | } |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
171e7b37 JR |
1117 | /* |
1118 | * Init the unity mappings for a specific IOMMU in the system | |
1119 | * | |
1120 | * Basically iterates over all unity mapping entries and applies them to | |
1121 | * the default domain DMA of that IOMMU if necessary. | |
1122 | */ | |
1123 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1124 | { | |
1125 | struct unity_map_entry *entry; | |
1126 | int ret; | |
1127 | ||
1128 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1129 | if (!iommu_for_unity_map(iommu, entry)) | |
1130 | continue; | |
1131 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | } | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
431b2a20 JR |
1139 | /* |
1140 | * Inits the unity mappings required for a specific device | |
1141 | */ | |
bd0e5211 JR |
1142 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1143 | u16 devid) | |
1144 | { | |
1145 | struct unity_map_entry *e; | |
1146 | int ret; | |
1147 | ||
1148 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1149 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1150 | continue; | |
1151 | ret = dma_ops_unity_map(dma_dom, e); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
431b2a20 JR |
1159 | /**************************************************************************** |
1160 | * | |
1161 | * The next functions belong to the address allocator for the dma_ops | |
1162 | * interface functions. They work like the allocators in the other IOMMU | |
1163 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1164 | * the aperture. Maybe it could be enhanced in the future to a more | |
1165 | * efficient allocator. | |
1166 | * | |
1167 | ****************************************************************************/ | |
d3086444 | 1168 | |
431b2a20 | 1169 | /* |
384de729 | 1170 | * The address allocator core functions. |
431b2a20 JR |
1171 | * |
1172 | * called with domain->lock held | |
1173 | */ | |
384de729 | 1174 | |
171e7b37 JR |
1175 | /* |
1176 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1177 | * ranges. | |
1178 | */ | |
1179 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1180 | unsigned long start_page, | |
1181 | unsigned int pages) | |
1182 | { | |
1183 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1184 | ||
1185 | if (start_page + pages > last_page) | |
1186 | pages = last_page - start_page; | |
1187 | ||
1188 | for (i = start_page; i < start_page + pages; ++i) { | |
1189 | int index = i / APERTURE_RANGE_PAGES; | |
1190 | int page = i % APERTURE_RANGE_PAGES; | |
1191 | __set_bit(page, dom->aperture[index]->bitmap); | |
1192 | } | |
1193 | } | |
1194 | ||
9cabe89b JR |
1195 | /* |
1196 | * This function is used to add a new aperture range to an existing | |
1197 | * aperture in case of dma_ops domain allocation or address allocation | |
1198 | * failure. | |
1199 | */ | |
576175c2 | 1200 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1201 | bool populate, gfp_t gfp) |
1202 | { | |
1203 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1204 | struct amd_iommu *iommu; |
d91afd15 | 1205 | unsigned long i; |
9cabe89b | 1206 | |
f5e9705c JR |
1207 | #ifdef CONFIG_IOMMU_STRESS |
1208 | populate = false; | |
1209 | #endif | |
1210 | ||
9cabe89b JR |
1211 | if (index >= APERTURE_MAX_RANGES) |
1212 | return -ENOMEM; | |
1213 | ||
1214 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1215 | if (!dma_dom->aperture[index]) | |
1216 | return -ENOMEM; | |
1217 | ||
1218 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1219 | if (!dma_dom->aperture[index]->bitmap) | |
1220 | goto out_free; | |
1221 | ||
1222 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1223 | ||
1224 | if (populate) { | |
1225 | unsigned long address = dma_dom->aperture_size; | |
1226 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1227 | u64 *pte, *pte_page; | |
1228 | ||
1229 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1230 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1231 | &pte_page, gfp); |
1232 | if (!pte) | |
1233 | goto out_free; | |
1234 | ||
1235 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1236 | ||
1237 | address += APERTURE_RANGE_SIZE / 64; | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
1242 | ||
b595076a | 1243 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1244 | for_each_iommu(iommu) { |
1245 | if (iommu->exclusion_start && | |
1246 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1247 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1248 | unsigned long startpage; | |
1249 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1250 | iommu->exclusion_length, | |
1251 | PAGE_SIZE); | |
1252 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1253 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1254 | } | |
00cd122a JR |
1255 | } |
1256 | ||
1257 | /* | |
1258 | * Check for areas already mapped as present in the new aperture | |
1259 | * range and mark those pages as reserved in the allocator. Such | |
1260 | * mappings may already exist as a result of requested unity | |
1261 | * mappings for devices. | |
1262 | */ | |
1263 | for (i = dma_dom->aperture[index]->offset; | |
1264 | i < dma_dom->aperture_size; | |
1265 | i += PAGE_SIZE) { | |
24cd7723 | 1266 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1267 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1268 | continue; | |
1269 | ||
1270 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
1271 | } | |
1272 | ||
04bfdd84 JR |
1273 | update_domain(&dma_dom->domain); |
1274 | ||
9cabe89b JR |
1275 | return 0; |
1276 | ||
1277 | out_free: | |
04bfdd84 JR |
1278 | update_domain(&dma_dom->domain); |
1279 | ||
9cabe89b JR |
1280 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1281 | ||
1282 | kfree(dma_dom->aperture[index]); | |
1283 | dma_dom->aperture[index] = NULL; | |
1284 | ||
1285 | return -ENOMEM; | |
1286 | } | |
1287 | ||
384de729 JR |
1288 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1289 | struct dma_ops_domain *dom, | |
1290 | unsigned int pages, | |
1291 | unsigned long align_mask, | |
1292 | u64 dma_mask, | |
1293 | unsigned long start) | |
1294 | { | |
803b8cb4 | 1295 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1296 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1297 | int i = start >> APERTURE_RANGE_SHIFT; | |
1298 | unsigned long boundary_size; | |
1299 | unsigned long address = -1; | |
1300 | unsigned long limit; | |
1301 | ||
803b8cb4 JR |
1302 | next_bit >>= PAGE_SHIFT; |
1303 | ||
384de729 JR |
1304 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1305 | PAGE_SIZE) >> PAGE_SHIFT; | |
1306 | ||
1307 | for (;i < max_index; ++i) { | |
1308 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1309 | ||
1310 | if (dom->aperture[i]->offset >= dma_mask) | |
1311 | break; | |
1312 | ||
1313 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1314 | dma_mask >> PAGE_SHIFT); | |
1315 | ||
1316 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1317 | limit, next_bit, pages, 0, | |
1318 | boundary_size, align_mask); | |
1319 | if (address != -1) { | |
1320 | address = dom->aperture[i]->offset + | |
1321 | (address << PAGE_SHIFT); | |
803b8cb4 | 1322 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1323 | break; |
1324 | } | |
1325 | ||
1326 | next_bit = 0; | |
1327 | } | |
1328 | ||
1329 | return address; | |
1330 | } | |
1331 | ||
d3086444 JR |
1332 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1333 | struct dma_ops_domain *dom, | |
6d4f343f | 1334 | unsigned int pages, |
832a90c3 JR |
1335 | unsigned long align_mask, |
1336 | u64 dma_mask) | |
d3086444 | 1337 | { |
d3086444 | 1338 | unsigned long address; |
d3086444 | 1339 | |
fe16f088 JR |
1340 | #ifdef CONFIG_IOMMU_STRESS |
1341 | dom->next_address = 0; | |
1342 | dom->need_flush = true; | |
1343 | #endif | |
d3086444 | 1344 | |
384de729 | 1345 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1346 | dma_mask, dom->next_address); |
d3086444 | 1347 | |
1c655773 | 1348 | if (address == -1) { |
803b8cb4 | 1349 | dom->next_address = 0; |
384de729 JR |
1350 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1351 | dma_mask, 0); | |
1c655773 JR |
1352 | dom->need_flush = true; |
1353 | } | |
d3086444 | 1354 | |
384de729 | 1355 | if (unlikely(address == -1)) |
8fd524b3 | 1356 | address = DMA_ERROR_CODE; |
d3086444 JR |
1357 | |
1358 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1359 | ||
1360 | return address; | |
1361 | } | |
1362 | ||
431b2a20 JR |
1363 | /* |
1364 | * The address free function. | |
1365 | * | |
1366 | * called with domain->lock held | |
1367 | */ | |
d3086444 JR |
1368 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1369 | unsigned long address, | |
1370 | unsigned int pages) | |
1371 | { | |
384de729 JR |
1372 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1373 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1374 | |
384de729 JR |
1375 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1376 | ||
47bccd6b JR |
1377 | #ifdef CONFIG_IOMMU_STRESS |
1378 | if (i < 4) | |
1379 | return; | |
1380 | #endif | |
80be308d | 1381 | |
803b8cb4 | 1382 | if (address >= dom->next_address) |
80be308d | 1383 | dom->need_flush = true; |
384de729 JR |
1384 | |
1385 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1386 | |
a66022c4 | 1387 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1388 | |
d3086444 JR |
1389 | } |
1390 | ||
431b2a20 JR |
1391 | /**************************************************************************** |
1392 | * | |
1393 | * The next functions belong to the domain allocation. A domain is | |
1394 | * allocated for every IOMMU as the default domain. If device isolation | |
1395 | * is enabled, every device get its own domain. The most important thing | |
1396 | * about domains is the page table mapping the DMA address space they | |
1397 | * contain. | |
1398 | * | |
1399 | ****************************************************************************/ | |
1400 | ||
aeb26f55 JR |
1401 | /* |
1402 | * This function adds a protection domain to the global protection domain list | |
1403 | */ | |
1404 | static void add_domain_to_list(struct protection_domain *domain) | |
1405 | { | |
1406 | unsigned long flags; | |
1407 | ||
1408 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1409 | list_add(&domain->list, &amd_iommu_pd_list); | |
1410 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1411 | } | |
1412 | ||
1413 | /* | |
1414 | * This function removes a protection domain to the global | |
1415 | * protection domain list | |
1416 | */ | |
1417 | static void del_domain_from_list(struct protection_domain *domain) | |
1418 | { | |
1419 | unsigned long flags; | |
1420 | ||
1421 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1422 | list_del(&domain->list); | |
1423 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1424 | } | |
1425 | ||
ec487d1a JR |
1426 | static u16 domain_id_alloc(void) |
1427 | { | |
1428 | unsigned long flags; | |
1429 | int id; | |
1430 | ||
1431 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1432 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1433 | BUG_ON(id == 0); | |
1434 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1435 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1436 | else | |
1437 | id = 0; | |
1438 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1439 | ||
1440 | return id; | |
1441 | } | |
1442 | ||
a2acfb75 JR |
1443 | static void domain_id_free(int id) |
1444 | { | |
1445 | unsigned long flags; | |
1446 | ||
1447 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1448 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1449 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1450 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1451 | } | |
a2acfb75 | 1452 | |
86db2e5d | 1453 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1454 | { |
1455 | int i, j; | |
1456 | u64 *p1, *p2, *p3; | |
1457 | ||
86db2e5d | 1458 | p1 = domain->pt_root; |
ec487d1a JR |
1459 | |
1460 | if (!p1) | |
1461 | return; | |
1462 | ||
1463 | for (i = 0; i < 512; ++i) { | |
1464 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1465 | continue; | |
1466 | ||
1467 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1468 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1469 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1470 | continue; | |
1471 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1472 | free_page((unsigned long)p3); | |
1473 | } | |
1474 | ||
1475 | free_page((unsigned long)p2); | |
1476 | } | |
1477 | ||
1478 | free_page((unsigned long)p1); | |
86db2e5d JR |
1479 | |
1480 | domain->pt_root = NULL; | |
ec487d1a JR |
1481 | } |
1482 | ||
431b2a20 JR |
1483 | /* |
1484 | * Free a domain, only used if something went wrong in the | |
1485 | * allocation path and we need to free an already allocated page table | |
1486 | */ | |
ec487d1a JR |
1487 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1488 | { | |
384de729 JR |
1489 | int i; |
1490 | ||
ec487d1a JR |
1491 | if (!dom) |
1492 | return; | |
1493 | ||
aeb26f55 JR |
1494 | del_domain_from_list(&dom->domain); |
1495 | ||
86db2e5d | 1496 | free_pagetable(&dom->domain); |
ec487d1a | 1497 | |
384de729 JR |
1498 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1499 | if (!dom->aperture[i]) | |
1500 | continue; | |
1501 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1502 | kfree(dom->aperture[i]); | |
1503 | } | |
ec487d1a JR |
1504 | |
1505 | kfree(dom); | |
1506 | } | |
1507 | ||
431b2a20 JR |
1508 | /* |
1509 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1510 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1511 | * structures required for the dma_ops interface |
1512 | */ | |
87a64d52 | 1513 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1514 | { |
1515 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1516 | |
1517 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1518 | if (!dma_dom) | |
1519 | return NULL; | |
1520 | ||
1521 | spin_lock_init(&dma_dom->domain.lock); | |
1522 | ||
1523 | dma_dom->domain.id = domain_id_alloc(); | |
1524 | if (dma_dom->domain.id == 0) | |
1525 | goto free_dma_dom; | |
7c392cbe | 1526 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1527 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1528 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1529 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1530 | dma_dom->domain.priv = dma_dom; |
1531 | if (!dma_dom->domain.pt_root) | |
1532 | goto free_dma_dom; | |
ec487d1a | 1533 | |
1c655773 | 1534 | dma_dom->need_flush = false; |
bd60b735 | 1535 | dma_dom->target_dev = 0xffff; |
1c655773 | 1536 | |
aeb26f55 JR |
1537 | add_domain_to_list(&dma_dom->domain); |
1538 | ||
576175c2 | 1539 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1540 | goto free_dma_dom; |
ec487d1a | 1541 | |
431b2a20 | 1542 | /* |
ec487d1a JR |
1543 | * mark the first page as allocated so we never return 0 as |
1544 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1545 | */ |
384de729 | 1546 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1547 | dma_dom->next_address = 0; |
ec487d1a | 1548 | |
ec487d1a JR |
1549 | |
1550 | return dma_dom; | |
1551 | ||
1552 | free_dma_dom: | |
1553 | dma_ops_domain_free(dma_dom); | |
1554 | ||
1555 | return NULL; | |
1556 | } | |
1557 | ||
5b28df6f JR |
1558 | /* |
1559 | * little helper function to check whether a given protection domain is a | |
1560 | * dma_ops domain | |
1561 | */ | |
1562 | static bool dma_ops_domain(struct protection_domain *domain) | |
1563 | { | |
1564 | return domain->flags & PD_DMA_OPS_MASK; | |
1565 | } | |
1566 | ||
fd7b5535 | 1567 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1568 | { |
b20ac0d4 | 1569 | u64 pte_root = virt_to_phys(domain->pt_root); |
fd7b5535 | 1570 | u32 flags = 0; |
863c74eb | 1571 | |
38ddf41b JR |
1572 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1573 | << DEV_ENTRY_MODE_SHIFT; | |
1574 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1575 | |
fd7b5535 JR |
1576 | if (ats) |
1577 | flags |= DTE_FLAG_IOTLB; | |
1578 | ||
1579 | amd_iommu_dev_table[devid].data[3] |= flags; | |
1580 | amd_iommu_dev_table[devid].data[2] = domain->id; | |
1581 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
1582 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
15898bbc JR |
1583 | } |
1584 | ||
1585 | static void clear_dte_entry(u16 devid) | |
1586 | { | |
15898bbc JR |
1587 | /* remove entry from the device table seen by the hardware */ |
1588 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1589 | amd_iommu_dev_table[devid].data[1] = 0; | |
1590 | amd_iommu_dev_table[devid].data[2] = 0; | |
1591 | ||
1592 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1593 | } |
1594 | ||
ec9e79ef JR |
1595 | static void do_attach(struct iommu_dev_data *dev_data, |
1596 | struct protection_domain *domain) | |
7f760ddd | 1597 | { |
7f760ddd | 1598 | struct amd_iommu *iommu; |
ec9e79ef | 1599 | bool ats; |
fd7b5535 | 1600 | |
ec9e79ef JR |
1601 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1602 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1603 | |
1604 | /* Update data structures */ | |
1605 | dev_data->domain = domain; | |
1606 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1607 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1608 | |
1609 | /* Do reference counting */ | |
1610 | domain->dev_iommu[iommu->index] += 1; | |
1611 | domain->dev_cnt += 1; | |
1612 | ||
1613 | /* Flush the DTE entry */ | |
6c542047 | 1614 | device_flush_dte(dev_data); |
7f760ddd JR |
1615 | } |
1616 | ||
ec9e79ef | 1617 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1618 | { |
7f760ddd | 1619 | struct amd_iommu *iommu; |
7f760ddd | 1620 | |
ec9e79ef | 1621 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1622 | |
1623 | /* decrease reference counters */ | |
7f760ddd JR |
1624 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1625 | dev_data->domain->dev_cnt -= 1; | |
1626 | ||
1627 | /* Update data structures */ | |
1628 | dev_data->domain = NULL; | |
1629 | list_del(&dev_data->list); | |
f62dda66 | 1630 | clear_dte_entry(dev_data->devid); |
15898bbc | 1631 | |
7f760ddd | 1632 | /* Flush the DTE entry */ |
6c542047 | 1633 | device_flush_dte(dev_data); |
2b681faf JR |
1634 | } |
1635 | ||
1636 | /* | |
1637 | * If a device is not yet associated with a domain, this function does | |
1638 | * assigns it visible for the hardware | |
1639 | */ | |
ec9e79ef | 1640 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1641 | struct protection_domain *domain) |
2b681faf | 1642 | { |
84fe6c19 | 1643 | int ret; |
657cbb6b | 1644 | |
2b681faf JR |
1645 | /* lock domain */ |
1646 | spin_lock(&domain->lock); | |
1647 | ||
71f77580 JR |
1648 | if (dev_data->alias_data != NULL) { |
1649 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1650 | |
2b02b091 JR |
1651 | /* Some sanity checks */ |
1652 | ret = -EBUSY; | |
1653 | if (alias_data->domain != NULL && | |
1654 | alias_data->domain != domain) | |
1655 | goto out_unlock; | |
eba6ac60 | 1656 | |
2b02b091 JR |
1657 | if (dev_data->domain != NULL && |
1658 | dev_data->domain != domain) | |
1659 | goto out_unlock; | |
15898bbc | 1660 | |
2b02b091 | 1661 | /* Do real assignment */ |
7f760ddd | 1662 | if (alias_data->domain == NULL) |
ec9e79ef | 1663 | do_attach(alias_data, domain); |
24100055 JR |
1664 | |
1665 | atomic_inc(&alias_data->bind); | |
657cbb6b | 1666 | } |
15898bbc | 1667 | |
7f760ddd | 1668 | if (dev_data->domain == NULL) |
ec9e79ef | 1669 | do_attach(dev_data, domain); |
eba6ac60 | 1670 | |
24100055 JR |
1671 | atomic_inc(&dev_data->bind); |
1672 | ||
84fe6c19 JL |
1673 | ret = 0; |
1674 | ||
1675 | out_unlock: | |
1676 | ||
eba6ac60 JR |
1677 | /* ready */ |
1678 | spin_unlock(&domain->lock); | |
15898bbc | 1679 | |
84fe6c19 | 1680 | return ret; |
0feae533 | 1681 | } |
b20ac0d4 | 1682 | |
407d733e JR |
1683 | /* |
1684 | * If a device is not yet associated with a domain, this function does | |
1685 | * assigns it visible for the hardware | |
1686 | */ | |
15898bbc JR |
1687 | static int attach_device(struct device *dev, |
1688 | struct protection_domain *domain) | |
0feae533 | 1689 | { |
fd7b5535 | 1690 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 1691 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1692 | unsigned long flags; |
15898bbc | 1693 | int ret; |
eba6ac60 | 1694 | |
ea61cddb JR |
1695 | dev_data = get_dev_data(dev); |
1696 | ||
1697 | if (amd_iommu_iotlb_sup && pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
1698 | dev_data->ats.enabled = true; | |
1699 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1700 | } | |
fd7b5535 | 1701 | |
eba6ac60 | 1702 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1703 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1704 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1705 | ||
0feae533 JR |
1706 | /* |
1707 | * We might boot into a crash-kernel here. The crashed kernel | |
1708 | * left the caches in the IOMMU dirty. So we have to flush | |
1709 | * here to evict all dirty stuff. | |
1710 | */ | |
17b124bf | 1711 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1712 | |
1713 | return ret; | |
b20ac0d4 JR |
1714 | } |
1715 | ||
355bf553 JR |
1716 | /* |
1717 | * Removes a device from a protection domain (unlocked) | |
1718 | */ | |
ec9e79ef | 1719 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 1720 | { |
2ca76279 | 1721 | struct protection_domain *domain; |
7c392cbe | 1722 | unsigned long flags; |
c4596114 | 1723 | |
7f760ddd | 1724 | BUG_ON(!dev_data->domain); |
355bf553 | 1725 | |
2ca76279 JR |
1726 | domain = dev_data->domain; |
1727 | ||
1728 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 1729 | |
71f77580 JR |
1730 | if (dev_data->alias_data != NULL) { |
1731 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
1732 | ||
7f760ddd | 1733 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 1734 | do_detach(alias_data); |
24100055 JR |
1735 | } |
1736 | ||
7f760ddd | 1737 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 1738 | do_detach(dev_data); |
7f760ddd | 1739 | |
2ca76279 | 1740 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
1741 | |
1742 | /* | |
1743 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
1744 | * passthrough domain if it is detached from any other domain. |
1745 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 1746 | */ |
d3ad9373 JR |
1747 | if (iommu_pass_through && |
1748 | (dev_data->domain == NULL && domain != pt_domain)) | |
ec9e79ef | 1749 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
1750 | } |
1751 | ||
1752 | /* | |
1753 | * Removes a device from a protection domain (with devtable_lock held) | |
1754 | */ | |
15898bbc | 1755 | static void detach_device(struct device *dev) |
355bf553 | 1756 | { |
ea61cddb | 1757 | struct iommu_dev_data *dev_data; |
355bf553 JR |
1758 | unsigned long flags; |
1759 | ||
ec9e79ef JR |
1760 | dev_data = get_dev_data(dev); |
1761 | ||
355bf553 JR |
1762 | /* lock device table */ |
1763 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 1764 | __detach_device(dev_data); |
355bf553 | 1765 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 1766 | |
ea61cddb JR |
1767 | if (dev_data->ats.enabled) { |
1768 | pci_disable_ats(to_pci_dev(dev)); | |
1769 | dev_data->ats.enabled = false; | |
1770 | } | |
355bf553 | 1771 | } |
e275a2a0 | 1772 | |
15898bbc JR |
1773 | /* |
1774 | * Find out the protection domain structure for a given PCI device. This | |
1775 | * will give us the pointer to the page table root for example. | |
1776 | */ | |
1777 | static struct protection_domain *domain_for_device(struct device *dev) | |
1778 | { | |
71f77580 | 1779 | struct iommu_dev_data *dev_data; |
2b02b091 | 1780 | struct protection_domain *dom = NULL; |
15898bbc | 1781 | unsigned long flags; |
15898bbc | 1782 | |
657cbb6b | 1783 | dev_data = get_dev_data(dev); |
15898bbc | 1784 | |
2b02b091 JR |
1785 | if (dev_data->domain) |
1786 | return dev_data->domain; | |
15898bbc | 1787 | |
71f77580 JR |
1788 | if (dev_data->alias_data != NULL) { |
1789 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
1790 | |
1791 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1792 | if (alias_data->domain != NULL) { | |
1793 | __attach_device(dev_data, alias_data->domain); | |
1794 | dom = alias_data->domain; | |
1795 | } | |
1796 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1797 | } | |
15898bbc JR |
1798 | |
1799 | return dom; | |
1800 | } | |
1801 | ||
e275a2a0 JR |
1802 | static int device_change_notifier(struct notifier_block *nb, |
1803 | unsigned long action, void *data) | |
1804 | { | |
1805 | struct device *dev = data; | |
98fc5a69 | 1806 | u16 devid; |
e275a2a0 JR |
1807 | struct protection_domain *domain; |
1808 | struct dma_ops_domain *dma_domain; | |
1809 | struct amd_iommu *iommu; | |
1ac4cbbc | 1810 | unsigned long flags; |
e275a2a0 | 1811 | |
98fc5a69 JR |
1812 | if (!check_device(dev)) |
1813 | return 0; | |
e275a2a0 | 1814 | |
98fc5a69 JR |
1815 | devid = get_device_id(dev); |
1816 | iommu = amd_iommu_rlookup_table[devid]; | |
e275a2a0 JR |
1817 | |
1818 | switch (action) { | |
c1eee67b | 1819 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
1820 | |
1821 | domain = domain_for_device(dev); | |
1822 | ||
e275a2a0 JR |
1823 | if (!domain) |
1824 | goto out; | |
a1ca331c JR |
1825 | if (iommu_pass_through) |
1826 | break; | |
15898bbc | 1827 | detach_device(dev); |
1ac4cbbc JR |
1828 | break; |
1829 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
1830 | |
1831 | iommu_init_device(dev); | |
1832 | ||
1833 | domain = domain_for_device(dev); | |
1834 | ||
1ac4cbbc JR |
1835 | /* allocate a protection domain if a device is added */ |
1836 | dma_domain = find_protection_domain(devid); | |
1837 | if (dma_domain) | |
1838 | goto out; | |
87a64d52 | 1839 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
1840 | if (!dma_domain) |
1841 | goto out; | |
1842 | dma_domain->target_dev = devid; | |
1843 | ||
1844 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1845 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1846 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1847 | ||
e275a2a0 | 1848 | break; |
657cbb6b JR |
1849 | case BUS_NOTIFY_DEL_DEVICE: |
1850 | ||
1851 | iommu_uninit_device(dev); | |
1852 | ||
e275a2a0 JR |
1853 | default: |
1854 | goto out; | |
1855 | } | |
1856 | ||
e275a2a0 JR |
1857 | iommu_completion_wait(iommu); |
1858 | ||
1859 | out: | |
1860 | return 0; | |
1861 | } | |
1862 | ||
b25ae679 | 1863 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1864 | .notifier_call = device_change_notifier, |
1865 | }; | |
355bf553 | 1866 | |
8638c491 JR |
1867 | void amd_iommu_init_notifier(void) |
1868 | { | |
1869 | bus_register_notifier(&pci_bus_type, &device_nb); | |
1870 | } | |
1871 | ||
431b2a20 JR |
1872 | /***************************************************************************** |
1873 | * | |
1874 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1875 | * | |
1876 | *****************************************************************************/ | |
1877 | ||
1878 | /* | |
1879 | * In the dma_ops path we only have the struct device. This function | |
1880 | * finds the corresponding IOMMU, the protection domain and the | |
1881 | * requestor id for a given device. | |
1882 | * If the device is not yet associated with a domain this is also done | |
1883 | * in this function. | |
1884 | */ | |
94f6d190 | 1885 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1886 | { |
94f6d190 | 1887 | struct protection_domain *domain; |
b20ac0d4 | 1888 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1889 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1890 | |
f99c0f1c | 1891 | if (!check_device(dev)) |
94f6d190 | 1892 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1893 | |
94f6d190 JR |
1894 | domain = domain_for_device(dev); |
1895 | if (domain != NULL && !dma_ops_domain(domain)) | |
1896 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1897 | |
94f6d190 JR |
1898 | if (domain != NULL) |
1899 | return domain; | |
b20ac0d4 | 1900 | |
15898bbc | 1901 | /* Device not bount yet - bind it */ |
94f6d190 | 1902 | dma_dom = find_protection_domain(devid); |
15898bbc | 1903 | if (!dma_dom) |
94f6d190 JR |
1904 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1905 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1906 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1907 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1908 | |
94f6d190 | 1909 | return &dma_dom->domain; |
b20ac0d4 JR |
1910 | } |
1911 | ||
04bfdd84 JR |
1912 | static void update_device_table(struct protection_domain *domain) |
1913 | { | |
492667da | 1914 | struct iommu_dev_data *dev_data; |
04bfdd84 | 1915 | |
ea61cddb JR |
1916 | list_for_each_entry(dev_data, &domain->dev_list, list) |
1917 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
1918 | } |
1919 | ||
1920 | static void update_domain(struct protection_domain *domain) | |
1921 | { | |
1922 | if (!domain->updated) | |
1923 | return; | |
1924 | ||
1925 | update_device_table(domain); | |
17b124bf JR |
1926 | |
1927 | domain_flush_devices(domain); | |
1928 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
1929 | |
1930 | domain->updated = false; | |
1931 | } | |
1932 | ||
8bda3092 JR |
1933 | /* |
1934 | * This function fetches the PTE for a given address in the aperture | |
1935 | */ | |
1936 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1937 | unsigned long address) | |
1938 | { | |
384de729 | 1939 | struct aperture_range *aperture; |
8bda3092 JR |
1940 | u64 *pte, *pte_page; |
1941 | ||
384de729 JR |
1942 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1943 | if (!aperture) | |
1944 | return NULL; | |
1945 | ||
1946 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1947 | if (!pte) { |
cbb9d729 | 1948 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 1949 | GFP_ATOMIC); |
384de729 JR |
1950 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1951 | } else | |
8c8c143c | 1952 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1953 | |
04bfdd84 | 1954 | update_domain(&dom->domain); |
8bda3092 JR |
1955 | |
1956 | return pte; | |
1957 | } | |
1958 | ||
431b2a20 JR |
1959 | /* |
1960 | * This is the generic map function. It maps one 4kb page at paddr to | |
1961 | * the given address in the DMA address space for the domain. | |
1962 | */ | |
680525e0 | 1963 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1964 | unsigned long address, |
1965 | phys_addr_t paddr, | |
1966 | int direction) | |
1967 | { | |
1968 | u64 *pte, __pte; | |
1969 | ||
1970 | WARN_ON(address > dom->aperture_size); | |
1971 | ||
1972 | paddr &= PAGE_MASK; | |
1973 | ||
8bda3092 | 1974 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1975 | if (!pte) |
8fd524b3 | 1976 | return DMA_ERROR_CODE; |
cb76c322 JR |
1977 | |
1978 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1979 | ||
1980 | if (direction == DMA_TO_DEVICE) | |
1981 | __pte |= IOMMU_PTE_IR; | |
1982 | else if (direction == DMA_FROM_DEVICE) | |
1983 | __pte |= IOMMU_PTE_IW; | |
1984 | else if (direction == DMA_BIDIRECTIONAL) | |
1985 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1986 | ||
1987 | WARN_ON(*pte); | |
1988 | ||
1989 | *pte = __pte; | |
1990 | ||
1991 | return (dma_addr_t)address; | |
1992 | } | |
1993 | ||
431b2a20 JR |
1994 | /* |
1995 | * The generic unmapping function for on page in the DMA address space. | |
1996 | */ | |
680525e0 | 1997 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1998 | unsigned long address) |
1999 | { | |
384de729 | 2000 | struct aperture_range *aperture; |
cb76c322 JR |
2001 | u64 *pte; |
2002 | ||
2003 | if (address >= dom->aperture_size) | |
2004 | return; | |
2005 | ||
384de729 JR |
2006 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2007 | if (!aperture) | |
2008 | return; | |
2009 | ||
2010 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2011 | if (!pte) | |
2012 | return; | |
cb76c322 | 2013 | |
8c8c143c | 2014 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2015 | |
2016 | WARN_ON(!*pte); | |
2017 | ||
2018 | *pte = 0ULL; | |
2019 | } | |
2020 | ||
431b2a20 JR |
2021 | /* |
2022 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2023 | * contiguous memory region into DMA address space. It is used by all |
2024 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2025 | * Must be called with the domain lock held. |
2026 | */ | |
cb76c322 | 2027 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2028 | struct dma_ops_domain *dma_dom, |
2029 | phys_addr_t paddr, | |
2030 | size_t size, | |
6d4f343f | 2031 | int dir, |
832a90c3 JR |
2032 | bool align, |
2033 | u64 dma_mask) | |
cb76c322 JR |
2034 | { |
2035 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2036 | dma_addr_t address, start, ret; |
cb76c322 | 2037 | unsigned int pages; |
6d4f343f | 2038 | unsigned long align_mask = 0; |
cb76c322 JR |
2039 | int i; |
2040 | ||
e3c449f5 | 2041 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2042 | paddr &= PAGE_MASK; |
2043 | ||
8ecaf8f1 JR |
2044 | INC_STATS_COUNTER(total_map_requests); |
2045 | ||
c1858976 JR |
2046 | if (pages > 1) |
2047 | INC_STATS_COUNTER(cross_page); | |
2048 | ||
6d4f343f JR |
2049 | if (align) |
2050 | align_mask = (1UL << get_order(size)) - 1; | |
2051 | ||
11b83888 | 2052 | retry: |
832a90c3 JR |
2053 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2054 | dma_mask); | |
8fd524b3 | 2055 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2056 | /* |
2057 | * setting next_address here will let the address | |
2058 | * allocator only scan the new allocated range in the | |
2059 | * first run. This is a small optimization. | |
2060 | */ | |
2061 | dma_dom->next_address = dma_dom->aperture_size; | |
2062 | ||
576175c2 | 2063 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2064 | goto out; |
2065 | ||
2066 | /* | |
af901ca1 | 2067 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2068 | * allocation again |
2069 | */ | |
2070 | goto retry; | |
2071 | } | |
cb76c322 JR |
2072 | |
2073 | start = address; | |
2074 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2075 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2076 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2077 | goto out_unmap; |
2078 | ||
cb76c322 JR |
2079 | paddr += PAGE_SIZE; |
2080 | start += PAGE_SIZE; | |
2081 | } | |
2082 | address += offset; | |
2083 | ||
5774f7c5 JR |
2084 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2085 | ||
afa9fdc2 | 2086 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2087 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2088 | dma_dom->need_flush = false; |
318afd41 | 2089 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2090 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2091 | |
cb76c322 JR |
2092 | out: |
2093 | return address; | |
53812c11 JR |
2094 | |
2095 | out_unmap: | |
2096 | ||
2097 | for (--i; i >= 0; --i) { | |
2098 | start -= PAGE_SIZE; | |
680525e0 | 2099 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2100 | } |
2101 | ||
2102 | dma_ops_free_addresses(dma_dom, address, pages); | |
2103 | ||
8fd524b3 | 2104 | return DMA_ERROR_CODE; |
cb76c322 JR |
2105 | } |
2106 | ||
431b2a20 JR |
2107 | /* |
2108 | * Does the reverse of the __map_single function. Must be called with | |
2109 | * the domain lock held too | |
2110 | */ | |
cd8c82e8 | 2111 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2112 | dma_addr_t dma_addr, |
2113 | size_t size, | |
2114 | int dir) | |
2115 | { | |
04e0463e | 2116 | dma_addr_t flush_addr; |
cb76c322 JR |
2117 | dma_addr_t i, start; |
2118 | unsigned int pages; | |
2119 | ||
8fd524b3 | 2120 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2121 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2122 | return; |
2123 | ||
04e0463e | 2124 | flush_addr = dma_addr; |
e3c449f5 | 2125 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2126 | dma_addr &= PAGE_MASK; |
2127 | start = dma_addr; | |
2128 | ||
2129 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2130 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2131 | start += PAGE_SIZE; |
2132 | } | |
2133 | ||
5774f7c5 JR |
2134 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2135 | ||
cb76c322 | 2136 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2137 | |
80be308d | 2138 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2139 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2140 | dma_dom->need_flush = false; |
2141 | } | |
cb76c322 JR |
2142 | } |
2143 | ||
431b2a20 JR |
2144 | /* |
2145 | * The exported map_single function for dma_ops. | |
2146 | */ | |
51491367 FT |
2147 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2148 | unsigned long offset, size_t size, | |
2149 | enum dma_data_direction dir, | |
2150 | struct dma_attrs *attrs) | |
4da70b9e JR |
2151 | { |
2152 | unsigned long flags; | |
4da70b9e | 2153 | struct protection_domain *domain; |
4da70b9e | 2154 | dma_addr_t addr; |
832a90c3 | 2155 | u64 dma_mask; |
51491367 | 2156 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2157 | |
0f2a86f2 JR |
2158 | INC_STATS_COUNTER(cnt_map_single); |
2159 | ||
94f6d190 JR |
2160 | domain = get_domain(dev); |
2161 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2162 | return (dma_addr_t)paddr; |
94f6d190 JR |
2163 | else if (IS_ERR(domain)) |
2164 | return DMA_ERROR_CODE; | |
4da70b9e | 2165 | |
f99c0f1c JR |
2166 | dma_mask = *dev->dma_mask; |
2167 | ||
4da70b9e | 2168 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2169 | |
cd8c82e8 | 2170 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2171 | dma_mask); |
8fd524b3 | 2172 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2173 | goto out; |
2174 | ||
17b124bf | 2175 | domain_flush_complete(domain); |
4da70b9e JR |
2176 | |
2177 | out: | |
2178 | spin_unlock_irqrestore(&domain->lock, flags); | |
2179 | ||
2180 | return addr; | |
2181 | } | |
2182 | ||
431b2a20 JR |
2183 | /* |
2184 | * The exported unmap_single function for dma_ops. | |
2185 | */ | |
51491367 FT |
2186 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2187 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2188 | { |
2189 | unsigned long flags; | |
4da70b9e | 2190 | struct protection_domain *domain; |
4da70b9e | 2191 | |
146a6917 JR |
2192 | INC_STATS_COUNTER(cnt_unmap_single); |
2193 | ||
94f6d190 JR |
2194 | domain = get_domain(dev); |
2195 | if (IS_ERR(domain)) | |
5b28df6f JR |
2196 | return; |
2197 | ||
4da70b9e JR |
2198 | spin_lock_irqsave(&domain->lock, flags); |
2199 | ||
cd8c82e8 | 2200 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2201 | |
17b124bf | 2202 | domain_flush_complete(domain); |
4da70b9e JR |
2203 | |
2204 | spin_unlock_irqrestore(&domain->lock, flags); | |
2205 | } | |
2206 | ||
431b2a20 JR |
2207 | /* |
2208 | * This is a special map_sg function which is used if we should map a | |
2209 | * device which is not handled by an AMD IOMMU in the system. | |
2210 | */ | |
65b050ad JR |
2211 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2212 | int nelems, int dir) | |
2213 | { | |
2214 | struct scatterlist *s; | |
2215 | int i; | |
2216 | ||
2217 | for_each_sg(sglist, s, nelems, i) { | |
2218 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2219 | s->dma_length = s->length; | |
2220 | } | |
2221 | ||
2222 | return nelems; | |
2223 | } | |
2224 | ||
431b2a20 JR |
2225 | /* |
2226 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2227 | * lists). | |
2228 | */ | |
65b050ad | 2229 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2230 | int nelems, enum dma_data_direction dir, |
2231 | struct dma_attrs *attrs) | |
65b050ad JR |
2232 | { |
2233 | unsigned long flags; | |
65b050ad | 2234 | struct protection_domain *domain; |
65b050ad JR |
2235 | int i; |
2236 | struct scatterlist *s; | |
2237 | phys_addr_t paddr; | |
2238 | int mapped_elems = 0; | |
832a90c3 | 2239 | u64 dma_mask; |
65b050ad | 2240 | |
d03f067a JR |
2241 | INC_STATS_COUNTER(cnt_map_sg); |
2242 | ||
94f6d190 JR |
2243 | domain = get_domain(dev); |
2244 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2245 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2246 | else if (IS_ERR(domain)) |
2247 | return 0; | |
dbcc112e | 2248 | |
832a90c3 | 2249 | dma_mask = *dev->dma_mask; |
65b050ad | 2250 | |
65b050ad JR |
2251 | spin_lock_irqsave(&domain->lock, flags); |
2252 | ||
2253 | for_each_sg(sglist, s, nelems, i) { | |
2254 | paddr = sg_phys(s); | |
2255 | ||
cd8c82e8 | 2256 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2257 | paddr, s->length, dir, false, |
2258 | dma_mask); | |
65b050ad JR |
2259 | |
2260 | if (s->dma_address) { | |
2261 | s->dma_length = s->length; | |
2262 | mapped_elems++; | |
2263 | } else | |
2264 | goto unmap; | |
65b050ad JR |
2265 | } |
2266 | ||
17b124bf | 2267 | domain_flush_complete(domain); |
65b050ad JR |
2268 | |
2269 | out: | |
2270 | spin_unlock_irqrestore(&domain->lock, flags); | |
2271 | ||
2272 | return mapped_elems; | |
2273 | unmap: | |
2274 | for_each_sg(sglist, s, mapped_elems, i) { | |
2275 | if (s->dma_address) | |
cd8c82e8 | 2276 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2277 | s->dma_length, dir); |
2278 | s->dma_address = s->dma_length = 0; | |
2279 | } | |
2280 | ||
2281 | mapped_elems = 0; | |
2282 | ||
2283 | goto out; | |
2284 | } | |
2285 | ||
431b2a20 JR |
2286 | /* |
2287 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2288 | * lists). | |
2289 | */ | |
65b050ad | 2290 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2291 | int nelems, enum dma_data_direction dir, |
2292 | struct dma_attrs *attrs) | |
65b050ad JR |
2293 | { |
2294 | unsigned long flags; | |
65b050ad JR |
2295 | struct protection_domain *domain; |
2296 | struct scatterlist *s; | |
65b050ad JR |
2297 | int i; |
2298 | ||
55877a6b JR |
2299 | INC_STATS_COUNTER(cnt_unmap_sg); |
2300 | ||
94f6d190 JR |
2301 | domain = get_domain(dev); |
2302 | if (IS_ERR(domain)) | |
5b28df6f JR |
2303 | return; |
2304 | ||
65b050ad JR |
2305 | spin_lock_irqsave(&domain->lock, flags); |
2306 | ||
2307 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2308 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2309 | s->dma_length, dir); |
65b050ad JR |
2310 | s->dma_address = s->dma_length = 0; |
2311 | } | |
2312 | ||
17b124bf | 2313 | domain_flush_complete(domain); |
65b050ad JR |
2314 | |
2315 | spin_unlock_irqrestore(&domain->lock, flags); | |
2316 | } | |
2317 | ||
431b2a20 JR |
2318 | /* |
2319 | * The exported alloc_coherent function for dma_ops. | |
2320 | */ | |
5d8b53cf JR |
2321 | static void *alloc_coherent(struct device *dev, size_t size, |
2322 | dma_addr_t *dma_addr, gfp_t flag) | |
2323 | { | |
2324 | unsigned long flags; | |
2325 | void *virt_addr; | |
5d8b53cf | 2326 | struct protection_domain *domain; |
5d8b53cf | 2327 | phys_addr_t paddr; |
832a90c3 | 2328 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2329 | |
c8f0fb36 JR |
2330 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2331 | ||
94f6d190 JR |
2332 | domain = get_domain(dev); |
2333 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2334 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2335 | *dma_addr = __pa(virt_addr); | |
2336 | return virt_addr; | |
94f6d190 JR |
2337 | } else if (IS_ERR(domain)) |
2338 | return NULL; | |
5d8b53cf | 2339 | |
f99c0f1c JR |
2340 | dma_mask = dev->coherent_dma_mask; |
2341 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2342 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2343 | |
2344 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2345 | if (!virt_addr) | |
b25ae679 | 2346 | return NULL; |
5d8b53cf | 2347 | |
5d8b53cf JR |
2348 | paddr = virt_to_phys(virt_addr); |
2349 | ||
832a90c3 JR |
2350 | if (!dma_mask) |
2351 | dma_mask = *dev->dma_mask; | |
2352 | ||
5d8b53cf JR |
2353 | spin_lock_irqsave(&domain->lock, flags); |
2354 | ||
cd8c82e8 | 2355 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2356 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2357 | |
8fd524b3 | 2358 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2359 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2360 | goto out_free; |
367d04c4 | 2361 | } |
5d8b53cf | 2362 | |
17b124bf | 2363 | domain_flush_complete(domain); |
5d8b53cf | 2364 | |
5d8b53cf JR |
2365 | spin_unlock_irqrestore(&domain->lock, flags); |
2366 | ||
2367 | return virt_addr; | |
5b28df6f JR |
2368 | |
2369 | out_free: | |
2370 | ||
2371 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2372 | ||
2373 | return NULL; | |
5d8b53cf JR |
2374 | } |
2375 | ||
431b2a20 JR |
2376 | /* |
2377 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2378 | */ |
5d8b53cf JR |
2379 | static void free_coherent(struct device *dev, size_t size, |
2380 | void *virt_addr, dma_addr_t dma_addr) | |
2381 | { | |
2382 | unsigned long flags; | |
5d8b53cf | 2383 | struct protection_domain *domain; |
5d8b53cf | 2384 | |
5d31ee7e JR |
2385 | INC_STATS_COUNTER(cnt_free_coherent); |
2386 | ||
94f6d190 JR |
2387 | domain = get_domain(dev); |
2388 | if (IS_ERR(domain)) | |
5b28df6f JR |
2389 | goto free_mem; |
2390 | ||
5d8b53cf JR |
2391 | spin_lock_irqsave(&domain->lock, flags); |
2392 | ||
cd8c82e8 | 2393 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2394 | |
17b124bf | 2395 | domain_flush_complete(domain); |
5d8b53cf JR |
2396 | |
2397 | spin_unlock_irqrestore(&domain->lock, flags); | |
2398 | ||
2399 | free_mem: | |
2400 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2401 | } | |
2402 | ||
b39ba6ad JR |
2403 | /* |
2404 | * This function is called by the DMA layer to find out if we can handle a | |
2405 | * particular device. It is part of the dma_ops. | |
2406 | */ | |
2407 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2408 | { | |
420aef8a | 2409 | return check_device(dev); |
b39ba6ad JR |
2410 | } |
2411 | ||
c432f3df | 2412 | /* |
431b2a20 JR |
2413 | * The function for pre-allocating protection domains. |
2414 | * | |
c432f3df JR |
2415 | * If the driver core informs the DMA layer if a driver grabs a device |
2416 | * we don't need to preallocate the protection domains anymore. | |
2417 | * For now we have to. | |
2418 | */ | |
0e93dd88 | 2419 | static void prealloc_protection_domains(void) |
c432f3df JR |
2420 | { |
2421 | struct pci_dev *dev = NULL; | |
2422 | struct dma_ops_domain *dma_dom; | |
98fc5a69 | 2423 | u16 devid; |
c432f3df | 2424 | |
d18c69d3 | 2425 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2426 | |
2427 | /* Do we handle this device? */ | |
2428 | if (!check_device(&dev->dev)) | |
c432f3df | 2429 | continue; |
98fc5a69 JR |
2430 | |
2431 | /* Is there already any domain for it? */ | |
15898bbc | 2432 | if (domain_for_device(&dev->dev)) |
c432f3df | 2433 | continue; |
98fc5a69 JR |
2434 | |
2435 | devid = get_device_id(&dev->dev); | |
2436 | ||
87a64d52 | 2437 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2438 | if (!dma_dom) |
2439 | continue; | |
2440 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2441 | dma_dom->target_dev = devid; |
2442 | ||
15898bbc | 2443 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2444 | |
bd60b735 | 2445 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2446 | } |
2447 | } | |
2448 | ||
160c1d8e | 2449 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2450 | .alloc_coherent = alloc_coherent, |
2451 | .free_coherent = free_coherent, | |
51491367 FT |
2452 | .map_page = map_page, |
2453 | .unmap_page = unmap_page, | |
6631ee9d JR |
2454 | .map_sg = map_sg, |
2455 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2456 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2457 | }; |
2458 | ||
27c2127a JR |
2459 | static unsigned device_dma_ops_init(void) |
2460 | { | |
2461 | struct pci_dev *pdev = NULL; | |
2462 | unsigned unhandled = 0; | |
2463 | ||
2464 | for_each_pci_dev(pdev) { | |
2465 | if (!check_device(&pdev->dev)) { | |
2466 | unhandled += 1; | |
2467 | continue; | |
2468 | } | |
2469 | ||
2470 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2471 | } | |
2472 | ||
2473 | return unhandled; | |
2474 | } | |
2475 | ||
431b2a20 JR |
2476 | /* |
2477 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2478 | */ | |
f5325094 JR |
2479 | |
2480 | void __init amd_iommu_init_api(void) | |
2481 | { | |
2482 | register_iommu(&amd_iommu_ops); | |
2483 | } | |
2484 | ||
6631ee9d JR |
2485 | int __init amd_iommu_init_dma_ops(void) |
2486 | { | |
2487 | struct amd_iommu *iommu; | |
27c2127a | 2488 | int ret, unhandled; |
6631ee9d | 2489 | |
431b2a20 JR |
2490 | /* |
2491 | * first allocate a default protection domain for every IOMMU we | |
2492 | * found in the system. Devices not assigned to any other | |
2493 | * protection domain will be assigned to the default one. | |
2494 | */ | |
3bd22172 | 2495 | for_each_iommu(iommu) { |
87a64d52 | 2496 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2497 | if (iommu->default_dom == NULL) |
2498 | return -ENOMEM; | |
e2dc14a2 | 2499 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2500 | ret = iommu_init_unity_mappings(iommu); |
2501 | if (ret) | |
2502 | goto free_domains; | |
2503 | } | |
2504 | ||
431b2a20 | 2505 | /* |
8793abeb | 2506 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2507 | */ |
8793abeb | 2508 | prealloc_protection_domains(); |
6631ee9d JR |
2509 | |
2510 | iommu_detected = 1; | |
75f1cdf1 | 2511 | swiotlb = 0; |
6631ee9d | 2512 | |
431b2a20 | 2513 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2514 | unhandled = device_dma_ops_init(); |
2515 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2516 | /* There are unhandled devices - initialize swiotlb for them */ | |
2517 | swiotlb = 1; | |
2518 | } | |
6631ee9d | 2519 | |
7f26508b JR |
2520 | amd_iommu_stats_init(); |
2521 | ||
6631ee9d JR |
2522 | return 0; |
2523 | ||
2524 | free_domains: | |
2525 | ||
3bd22172 | 2526 | for_each_iommu(iommu) { |
6631ee9d JR |
2527 | if (iommu->default_dom) |
2528 | dma_ops_domain_free(iommu->default_dom); | |
2529 | } | |
2530 | ||
2531 | return ret; | |
2532 | } | |
6d98cd80 JR |
2533 | |
2534 | /***************************************************************************** | |
2535 | * | |
2536 | * The following functions belong to the exported interface of AMD IOMMU | |
2537 | * | |
2538 | * This interface allows access to lower level functions of the IOMMU | |
2539 | * like protection domain handling and assignement of devices to domains | |
2540 | * which is not possible with the dma_ops interface. | |
2541 | * | |
2542 | *****************************************************************************/ | |
2543 | ||
6d98cd80 JR |
2544 | static void cleanup_domain(struct protection_domain *domain) |
2545 | { | |
492667da | 2546 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 2547 | unsigned long flags; |
6d98cd80 JR |
2548 | |
2549 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2550 | ||
492667da | 2551 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 2552 | __detach_device(dev_data); |
492667da JR |
2553 | atomic_set(&dev_data->bind, 0); |
2554 | } | |
6d98cd80 JR |
2555 | |
2556 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2557 | } | |
2558 | ||
2650815f JR |
2559 | static void protection_domain_free(struct protection_domain *domain) |
2560 | { | |
2561 | if (!domain) | |
2562 | return; | |
2563 | ||
aeb26f55 JR |
2564 | del_domain_from_list(domain); |
2565 | ||
2650815f JR |
2566 | if (domain->id) |
2567 | domain_id_free(domain->id); | |
2568 | ||
2569 | kfree(domain); | |
2570 | } | |
2571 | ||
2572 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2573 | { |
2574 | struct protection_domain *domain; | |
2575 | ||
2576 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2577 | if (!domain) | |
2650815f | 2578 | return NULL; |
c156e347 JR |
2579 | |
2580 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2581 | mutex_init(&domain->api_lock); |
c156e347 JR |
2582 | domain->id = domain_id_alloc(); |
2583 | if (!domain->id) | |
2650815f | 2584 | goto out_err; |
7c392cbe | 2585 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2586 | |
aeb26f55 JR |
2587 | add_domain_to_list(domain); |
2588 | ||
2650815f JR |
2589 | return domain; |
2590 | ||
2591 | out_err: | |
2592 | kfree(domain); | |
2593 | ||
2594 | return NULL; | |
2595 | } | |
2596 | ||
2597 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2598 | { | |
2599 | struct protection_domain *domain; | |
2600 | ||
2601 | domain = protection_domain_alloc(); | |
2602 | if (!domain) | |
c156e347 | 2603 | goto out_free; |
2650815f JR |
2604 | |
2605 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2606 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2607 | if (!domain->pt_root) | |
2608 | goto out_free; | |
2609 | ||
2610 | dom->priv = domain; | |
2611 | ||
2612 | return 0; | |
2613 | ||
2614 | out_free: | |
2650815f | 2615 | protection_domain_free(domain); |
c156e347 JR |
2616 | |
2617 | return -ENOMEM; | |
2618 | } | |
2619 | ||
98383fc3 JR |
2620 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2621 | { | |
2622 | struct protection_domain *domain = dom->priv; | |
2623 | ||
2624 | if (!domain) | |
2625 | return; | |
2626 | ||
2627 | if (domain->dev_cnt > 0) | |
2628 | cleanup_domain(domain); | |
2629 | ||
2630 | BUG_ON(domain->dev_cnt != 0); | |
2631 | ||
2632 | free_pagetable(domain); | |
2633 | ||
8b408fe4 | 2634 | protection_domain_free(domain); |
98383fc3 JR |
2635 | |
2636 | dom->priv = NULL; | |
2637 | } | |
2638 | ||
684f2888 JR |
2639 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2640 | struct device *dev) | |
2641 | { | |
657cbb6b | 2642 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2643 | struct amd_iommu *iommu; |
684f2888 JR |
2644 | u16 devid; |
2645 | ||
98fc5a69 | 2646 | if (!check_device(dev)) |
684f2888 JR |
2647 | return; |
2648 | ||
98fc5a69 | 2649 | devid = get_device_id(dev); |
684f2888 | 2650 | |
657cbb6b | 2651 | if (dev_data->domain != NULL) |
15898bbc | 2652 | detach_device(dev); |
684f2888 JR |
2653 | |
2654 | iommu = amd_iommu_rlookup_table[devid]; | |
2655 | if (!iommu) | |
2656 | return; | |
2657 | ||
684f2888 JR |
2658 | iommu_completion_wait(iommu); |
2659 | } | |
2660 | ||
01106066 JR |
2661 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2662 | struct device *dev) | |
2663 | { | |
2664 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 2665 | struct iommu_dev_data *dev_data; |
01106066 | 2666 | struct amd_iommu *iommu; |
15898bbc | 2667 | int ret; |
01106066 | 2668 | |
98fc5a69 | 2669 | if (!check_device(dev)) |
01106066 JR |
2670 | return -EINVAL; |
2671 | ||
657cbb6b JR |
2672 | dev_data = dev->archdata.iommu; |
2673 | ||
f62dda66 | 2674 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2675 | if (!iommu) |
2676 | return -EINVAL; | |
2677 | ||
657cbb6b | 2678 | if (dev_data->domain) |
15898bbc | 2679 | detach_device(dev); |
01106066 | 2680 | |
15898bbc | 2681 | ret = attach_device(dev, domain); |
01106066 JR |
2682 | |
2683 | iommu_completion_wait(iommu); | |
2684 | ||
15898bbc | 2685 | return ret; |
01106066 JR |
2686 | } |
2687 | ||
468e2366 JR |
2688 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
2689 | phys_addr_t paddr, int gfp_order, int iommu_prot) | |
c6229ca6 | 2690 | { |
468e2366 | 2691 | unsigned long page_size = 0x1000UL << gfp_order; |
c6229ca6 | 2692 | struct protection_domain *domain = dom->priv; |
c6229ca6 JR |
2693 | int prot = 0; |
2694 | int ret; | |
2695 | ||
2696 | if (iommu_prot & IOMMU_READ) | |
2697 | prot |= IOMMU_PROT_IR; | |
2698 | if (iommu_prot & IOMMU_WRITE) | |
2699 | prot |= IOMMU_PROT_IW; | |
2700 | ||
5d214fe6 | 2701 | mutex_lock(&domain->api_lock); |
795e74f7 | 2702 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
2703 | mutex_unlock(&domain->api_lock); |
2704 | ||
795e74f7 | 2705 | return ret; |
c6229ca6 JR |
2706 | } |
2707 | ||
468e2366 JR |
2708 | static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2709 | int gfp_order) | |
eb74ff6c | 2710 | { |
eb74ff6c | 2711 | struct protection_domain *domain = dom->priv; |
468e2366 | 2712 | unsigned long page_size, unmap_size; |
eb74ff6c | 2713 | |
468e2366 | 2714 | page_size = 0x1000UL << gfp_order; |
eb74ff6c | 2715 | |
5d214fe6 | 2716 | mutex_lock(&domain->api_lock); |
468e2366 | 2717 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2718 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2719 | |
17b124bf | 2720 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2721 | |
468e2366 | 2722 | return get_order(unmap_size); |
eb74ff6c JR |
2723 | } |
2724 | ||
645c4c8d JR |
2725 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2726 | unsigned long iova) | |
2727 | { | |
2728 | struct protection_domain *domain = dom->priv; | |
f03152bb | 2729 | unsigned long offset_mask; |
645c4c8d | 2730 | phys_addr_t paddr; |
f03152bb | 2731 | u64 *pte, __pte; |
645c4c8d | 2732 | |
24cd7723 | 2733 | pte = fetch_pte(domain, iova); |
645c4c8d | 2734 | |
a6d41a40 | 2735 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2736 | return 0; |
2737 | ||
f03152bb JR |
2738 | if (PM_PTE_LEVEL(*pte) == 0) |
2739 | offset_mask = PAGE_SIZE - 1; | |
2740 | else | |
2741 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
2742 | ||
2743 | __pte = *pte & PM_ADDR_MASK; | |
2744 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
2745 | |
2746 | return paddr; | |
2747 | } | |
2748 | ||
dbb9fd86 SY |
2749 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2750 | unsigned long cap) | |
2751 | { | |
80a506b8 JR |
2752 | switch (cap) { |
2753 | case IOMMU_CAP_CACHE_COHERENCY: | |
2754 | return 1; | |
2755 | } | |
2756 | ||
dbb9fd86 SY |
2757 | return 0; |
2758 | } | |
2759 | ||
26961efe JR |
2760 | static struct iommu_ops amd_iommu_ops = { |
2761 | .domain_init = amd_iommu_domain_init, | |
2762 | .domain_destroy = amd_iommu_domain_destroy, | |
2763 | .attach_dev = amd_iommu_attach_device, | |
2764 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2765 | .map = amd_iommu_map, |
2766 | .unmap = amd_iommu_unmap, | |
26961efe | 2767 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 2768 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2769 | }; |
2770 | ||
0feae533 JR |
2771 | /***************************************************************************** |
2772 | * | |
2773 | * The next functions do a basic initialization of IOMMU for pass through | |
2774 | * mode | |
2775 | * | |
2776 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2777 | * DMA-API translation. | |
2778 | * | |
2779 | *****************************************************************************/ | |
2780 | ||
2781 | int __init amd_iommu_init_passthrough(void) | |
2782 | { | |
15898bbc | 2783 | struct amd_iommu *iommu; |
0feae533 | 2784 | struct pci_dev *dev = NULL; |
15898bbc | 2785 | u16 devid; |
0feae533 | 2786 | |
af901ca1 | 2787 | /* allocate passthrough domain */ |
0feae533 JR |
2788 | pt_domain = protection_domain_alloc(); |
2789 | if (!pt_domain) | |
2790 | return -ENOMEM; | |
2791 | ||
2792 | pt_domain->mode |= PAGE_MODE_NONE; | |
2793 | ||
6c54aabd | 2794 | for_each_pci_dev(dev) { |
98fc5a69 | 2795 | if (!check_device(&dev->dev)) |
0feae533 JR |
2796 | continue; |
2797 | ||
98fc5a69 JR |
2798 | devid = get_device_id(&dev->dev); |
2799 | ||
15898bbc | 2800 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2801 | if (!iommu) |
2802 | continue; | |
2803 | ||
15898bbc | 2804 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2805 | } |
2806 | ||
2807 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2808 | ||
2809 | return 0; | |
2810 | } |