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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 JR |
56 | |
57 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
58 | ||
815b33fd | 59 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 60 | |
307d5851 JR |
61 | /* IO virtual address start page frame number */ |
62 | #define IOVA_START_PFN (1) | |
63 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
64 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) | |
65 | ||
81cd07b9 JR |
66 | /* Reserved IOVA ranges */ |
67 | #define MSI_RANGE_START (0xfee00000) | |
68 | #define MSI_RANGE_END (0xfeefffff) | |
69 | #define HT_RANGE_START (0xfd00000000ULL) | |
70 | #define HT_RANGE_END (0xffffffffffULL) | |
71 | ||
aa3de9c0 OBC |
72 | /* |
73 | * This bitmap is used to advertise the page sizes our hardware support | |
74 | * to the IOMMU core, which will then use this information to split | |
75 | * physically contiguous memory regions it is mapping into page sizes | |
76 | * that we support. | |
77 | * | |
954e3dd8 | 78 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 79 | */ |
954e3dd8 | 80 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 81 | |
b6c02715 JR |
82 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
83 | ||
8fa5f802 JR |
84 | /* List of all available dev_data structures */ |
85 | static LIST_HEAD(dev_data_list); | |
86 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
87 | ||
6efed63b JR |
88 | LIST_HEAD(ioapic_map); |
89 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 90 | LIST_HEAD(acpihid_map); |
6efed63b | 91 | |
c5b5da9c JR |
92 | #define FLUSH_QUEUE_SIZE 256 |
93 | ||
94 | struct flush_queue_entry { | |
95 | unsigned long iova_pfn; | |
96 | unsigned long pages; | |
97 | struct dma_ops_domain *dma_dom; | |
98 | }; | |
99 | ||
100 | struct flush_queue { | |
101 | spinlock_t lock; | |
102 | unsigned next; | |
103 | struct flush_queue_entry *entries; | |
104 | }; | |
105 | ||
a5604f26 | 106 | static DEFINE_PER_CPU(struct flush_queue, flush_queue); |
c5b5da9c | 107 | |
bb279475 JR |
108 | static atomic_t queue_timer_on; |
109 | static struct timer_list queue_timer; | |
110 | ||
0feae533 JR |
111 | /* |
112 | * Domain for untranslated devices - only allocated | |
113 | * if iommu=pt passed on kernel cmd line. | |
114 | */ | |
b0119e87 | 115 | const struct iommu_ops amd_iommu_ops; |
26961efe | 116 | |
72e1dcc4 | 117 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 118 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 119 | |
ac1534a5 JR |
120 | static struct dma_map_ops amd_iommu_dma_ops; |
121 | ||
50917e26 JR |
122 | /* |
123 | * This struct contains device specific data for the IOMMU | |
124 | */ | |
125 | struct iommu_dev_data { | |
126 | struct list_head list; /* For domain->dev_list */ | |
127 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 128 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 | 129 | u16 devid; /* PCI Device ID */ |
e3156048 | 130 | u16 alias; /* Alias Device ID */ |
50917e26 | 131 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
1e6a7b04 | 132 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
133 | struct { |
134 | bool enabled; | |
135 | int qdep; | |
136 | } ats; /* ATS state */ | |
137 | bool pri_tlp; /* PASID TLB required for | |
138 | PPR completions */ | |
139 | u32 errata; /* Bitmap for errata to apply */ | |
d98de49a | 140 | bool use_vapic; /* Enable device to use vapic mode */ |
50917e26 JR |
141 | }; |
142 | ||
431b2a20 JR |
143 | /* |
144 | * general struct to manage commands send to an IOMMU | |
145 | */ | |
d6449536 | 146 | struct iommu_cmd { |
b6c02715 JR |
147 | u32 data[4]; |
148 | }; | |
149 | ||
05152a04 JR |
150 | struct kmem_cache *amd_iommu_irq_cache; |
151 | ||
04bfdd84 | 152 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 153 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 154 | static void detach_device(struct device *dev); |
c1eee67b | 155 | |
007b74ba JR |
156 | /* |
157 | * Data container for a dma_ops specific protection domain | |
158 | */ | |
159 | struct dma_ops_domain { | |
160 | /* generic protection domain information */ | |
161 | struct protection_domain domain; | |
162 | ||
307d5851 JR |
163 | /* IOVA RB-Tree */ |
164 | struct iova_domain iovad; | |
007b74ba JR |
165 | }; |
166 | ||
81cd07b9 JR |
167 | static struct iova_domain reserved_iova_ranges; |
168 | static struct lock_class_key reserved_rbtree_key; | |
169 | ||
15898bbc JR |
170 | /**************************************************************************** |
171 | * | |
172 | * Helper functions | |
173 | * | |
174 | ****************************************************************************/ | |
175 | ||
2bf9a0a1 WZ |
176 | static inline int match_hid_uid(struct device *dev, |
177 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 178 | { |
2bf9a0a1 WZ |
179 | const char *hid, *uid; |
180 | ||
181 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
182 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
183 | ||
184 | if (!hid || !(*hid)) | |
185 | return -ENODEV; | |
186 | ||
187 | if (!uid || !(*uid)) | |
188 | return strcmp(hid, entry->hid); | |
189 | ||
190 | if (!(*entry->uid)) | |
191 | return strcmp(hid, entry->hid); | |
192 | ||
193 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
194 | } |
195 | ||
2bf9a0a1 | 196 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
197 | { |
198 | struct pci_dev *pdev = to_pci_dev(dev); | |
199 | ||
200 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
201 | } | |
202 | ||
2bf9a0a1 WZ |
203 | static inline int get_acpihid_device_id(struct device *dev, |
204 | struct acpihid_map_entry **entry) | |
205 | { | |
206 | struct acpihid_map_entry *p; | |
207 | ||
208 | list_for_each_entry(p, &acpihid_map, list) { | |
209 | if (!match_hid_uid(dev, p)) { | |
210 | if (entry) | |
211 | *entry = p; | |
212 | return p->devid; | |
213 | } | |
214 | } | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | static inline int get_device_id(struct device *dev) | |
219 | { | |
220 | int devid; | |
221 | ||
222 | if (dev_is_pci(dev)) | |
223 | devid = get_pci_device_id(dev); | |
224 | else | |
225 | devid = get_acpihid_device_id(dev, NULL); | |
226 | ||
227 | return devid; | |
228 | } | |
229 | ||
3f4b87b9 JR |
230 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
231 | { | |
232 | return container_of(dom, struct protection_domain, domain); | |
233 | } | |
234 | ||
b3311b06 JR |
235 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
236 | { | |
237 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
238 | return container_of(domain, struct dma_ops_domain, domain); | |
239 | } | |
240 | ||
f62dda66 | 241 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
242 | { |
243 | struct iommu_dev_data *dev_data; | |
244 | unsigned long flags; | |
245 | ||
246 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
247 | if (!dev_data) | |
248 | return NULL; | |
249 | ||
f62dda66 | 250 | dev_data->devid = devid; |
8fa5f802 JR |
251 | |
252 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
253 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
254 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
255 | ||
256 | return dev_data; | |
257 | } | |
258 | ||
3b03bb74 JR |
259 | static struct iommu_dev_data *search_dev_data(u16 devid) |
260 | { | |
261 | struct iommu_dev_data *dev_data; | |
262 | unsigned long flags; | |
263 | ||
264 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
265 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
266 | if (dev_data->devid == devid) | |
267 | goto out_unlock; | |
268 | } | |
269 | ||
270 | dev_data = NULL; | |
271 | ||
272 | out_unlock: | |
273 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
274 | ||
275 | return dev_data; | |
276 | } | |
277 | ||
e3156048 JR |
278 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
279 | { | |
280 | *(u16 *)data = alias; | |
281 | return 0; | |
282 | } | |
283 | ||
284 | static u16 get_alias(struct device *dev) | |
285 | { | |
286 | struct pci_dev *pdev = to_pci_dev(dev); | |
287 | u16 devid, ivrs_alias, pci_alias; | |
288 | ||
6c0b43df | 289 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 JR |
290 | devid = get_device_id(dev); |
291 | ivrs_alias = amd_iommu_alias_table[devid]; | |
292 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
293 | ||
294 | if (ivrs_alias == pci_alias) | |
295 | return ivrs_alias; | |
296 | ||
297 | /* | |
298 | * DMA alias showdown | |
299 | * | |
300 | * The IVRS is fairly reliable in telling us about aliases, but it | |
301 | * can't know about every screwy device. If we don't have an IVRS | |
302 | * reported alias, use the PCI reported alias. In that case we may | |
303 | * still need to initialize the rlookup and dev_table entries if the | |
304 | * alias is to a non-existent device. | |
305 | */ | |
306 | if (ivrs_alias == devid) { | |
307 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
308 | amd_iommu_rlookup_table[pci_alias] = | |
309 | amd_iommu_rlookup_table[devid]; | |
310 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
311 | amd_iommu_dev_table[devid].data, | |
312 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
313 | } | |
314 | ||
315 | return pci_alias; | |
316 | } | |
317 | ||
318 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
319 | "for device %s[%04x:%04x], kernel reported alias " | |
320 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
321 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
322 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
323 | PCI_FUNC(pci_alias)); | |
324 | ||
325 | /* | |
326 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
327 | * bus, then the IVRS table may know about a quirk that we don't. | |
328 | */ | |
329 | if (pci_alias == devid && | |
330 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 331 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
332 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
333 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
334 | dev_name(dev)); | |
335 | } | |
336 | ||
337 | return ivrs_alias; | |
338 | } | |
339 | ||
3b03bb74 JR |
340 | static struct iommu_dev_data *find_dev_data(u16 devid) |
341 | { | |
342 | struct iommu_dev_data *dev_data; | |
343 | ||
344 | dev_data = search_dev_data(devid); | |
345 | ||
346 | if (dev_data == NULL) | |
347 | dev_data = alloc_dev_data(devid); | |
348 | ||
349 | return dev_data; | |
350 | } | |
351 | ||
657cbb6b JR |
352 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
353 | { | |
354 | return dev->archdata.iommu; | |
355 | } | |
356 | ||
b097d11a WZ |
357 | /* |
358 | * Find or create an IOMMU group for a acpihid device. | |
359 | */ | |
360 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 361 | { |
b097d11a | 362 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 363 | int devid; |
b097d11a WZ |
364 | |
365 | devid = get_acpihid_device_id(dev, &entry); | |
366 | if (devid < 0) | |
367 | return ERR_PTR(devid); | |
368 | ||
369 | list_for_each_entry(p, &acpihid_map, list) { | |
370 | if ((devid == p->devid) && p->group) | |
371 | entry->group = p->group; | |
372 | } | |
373 | ||
374 | if (!entry->group) | |
375 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
376 | else |
377 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
378 | |
379 | return entry->group; | |
657cbb6b JR |
380 | } |
381 | ||
5abcdba4 JR |
382 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
383 | { | |
384 | static const int caps[] = { | |
385 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
386 | PCI_EXT_CAP_ID_PRI, |
387 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
388 | }; |
389 | int i, pos; | |
390 | ||
391 | for (i = 0; i < 3; ++i) { | |
392 | pos = pci_find_ext_capability(pdev, caps[i]); | |
393 | if (pos == 0) | |
394 | return false; | |
395 | } | |
396 | ||
397 | return true; | |
398 | } | |
399 | ||
6a113ddc JR |
400 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
401 | { | |
402 | struct iommu_dev_data *dev_data; | |
403 | ||
404 | dev_data = get_dev_data(&pdev->dev); | |
405 | ||
406 | return dev_data->errata & (1 << erratum) ? true : false; | |
407 | } | |
408 | ||
98fc5a69 JR |
409 | /* |
410 | * This function checks if the driver got a valid device from the caller to | |
411 | * avoid dereferencing invalid pointers. | |
412 | */ | |
413 | static bool check_device(struct device *dev) | |
414 | { | |
7aba6cb9 | 415 | int devid; |
98fc5a69 JR |
416 | |
417 | if (!dev || !dev->dma_mask) | |
418 | return false; | |
419 | ||
98fc5a69 | 420 | devid = get_device_id(dev); |
9ee35e4c | 421 | if (devid < 0) |
7aba6cb9 | 422 | return false; |
98fc5a69 JR |
423 | |
424 | /* Out of our scope? */ | |
425 | if (devid > amd_iommu_last_bdf) | |
426 | return false; | |
427 | ||
428 | if (amd_iommu_rlookup_table[devid] == NULL) | |
429 | return false; | |
430 | ||
431 | return true; | |
432 | } | |
433 | ||
25b11ce2 | 434 | static void init_iommu_group(struct device *dev) |
2851db21 | 435 | { |
2851db21 | 436 | struct iommu_group *group; |
2851db21 | 437 | |
65d5352f | 438 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
439 | if (IS_ERR(group)) |
440 | return; | |
441 | ||
0bb6e243 | 442 | iommu_group_put(group); |
eb9c9527 AW |
443 | } |
444 | ||
445 | static int iommu_init_device(struct device *dev) | |
446 | { | |
eb9c9527 | 447 | struct iommu_dev_data *dev_data; |
39ab9555 | 448 | struct amd_iommu *iommu; |
7aba6cb9 | 449 | int devid; |
eb9c9527 AW |
450 | |
451 | if (dev->archdata.iommu) | |
452 | return 0; | |
453 | ||
7aba6cb9 | 454 | devid = get_device_id(dev); |
9ee35e4c | 455 | if (devid < 0) |
7aba6cb9 WZ |
456 | return devid; |
457 | ||
39ab9555 JR |
458 | iommu = amd_iommu_rlookup_table[devid]; |
459 | ||
7aba6cb9 | 460 | dev_data = find_dev_data(devid); |
eb9c9527 AW |
461 | if (!dev_data) |
462 | return -ENOMEM; | |
463 | ||
e3156048 JR |
464 | dev_data->alias = get_alias(dev); |
465 | ||
2bf9a0a1 | 466 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
467 | struct amd_iommu *iommu; |
468 | ||
2bf9a0a1 | 469 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
470 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
471 | } | |
472 | ||
657cbb6b JR |
473 | dev->archdata.iommu = dev_data; |
474 | ||
e3d10af1 | 475 | iommu_device_link(&iommu->iommu, dev); |
066f2e98 | 476 | |
657cbb6b JR |
477 | return 0; |
478 | } | |
479 | ||
26018874 JR |
480 | static void iommu_ignore_device(struct device *dev) |
481 | { | |
7aba6cb9 WZ |
482 | u16 alias; |
483 | int devid; | |
26018874 JR |
484 | |
485 | devid = get_device_id(dev); | |
9ee35e4c | 486 | if (devid < 0) |
7aba6cb9 WZ |
487 | return; |
488 | ||
e3156048 | 489 | alias = get_alias(dev); |
26018874 JR |
490 | |
491 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
492 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
493 | ||
494 | amd_iommu_rlookup_table[devid] = NULL; | |
495 | amd_iommu_rlookup_table[alias] = NULL; | |
496 | } | |
497 | ||
657cbb6b JR |
498 | static void iommu_uninit_device(struct device *dev) |
499 | { | |
7aba6cb9 | 500 | struct iommu_dev_data *dev_data; |
39ab9555 JR |
501 | struct amd_iommu *iommu; |
502 | int devid; | |
c1931090 | 503 | |
7aba6cb9 | 504 | devid = get_device_id(dev); |
9ee35e4c | 505 | if (devid < 0) |
7aba6cb9 | 506 | return; |
c1931090 | 507 | |
39ab9555 JR |
508 | iommu = amd_iommu_rlookup_table[devid]; |
509 | ||
7aba6cb9 | 510 | dev_data = search_dev_data(devid); |
c1931090 AW |
511 | if (!dev_data) |
512 | return; | |
513 | ||
b6809ee5 JR |
514 | if (dev_data->domain) |
515 | detach_device(dev); | |
516 | ||
e3d10af1 | 517 | iommu_device_unlink(&iommu->iommu, dev); |
066f2e98 | 518 | |
9dcd6130 AW |
519 | iommu_group_remove_device(dev); |
520 | ||
aafd8ba0 JR |
521 | /* Remove dma-ops */ |
522 | dev->archdata.dma_ops = NULL; | |
523 | ||
8fa5f802 | 524 | /* |
c1931090 AW |
525 | * We keep dev_data around for unplugged devices and reuse it when the |
526 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 527 | */ |
657cbb6b | 528 | } |
b7cc9554 | 529 | |
a80dc3e0 JR |
530 | /**************************************************************************** |
531 | * | |
532 | * Interrupt handling functions | |
533 | * | |
534 | ****************************************************************************/ | |
535 | ||
e3e59876 JR |
536 | static void dump_dte_entry(u16 devid) |
537 | { | |
538 | int i; | |
539 | ||
ee6c2868 JR |
540 | for (i = 0; i < 4; ++i) |
541 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
542 | amd_iommu_dev_table[devid].data[i]); |
543 | } | |
544 | ||
945b4ac4 JR |
545 | static void dump_command(unsigned long phys_addr) |
546 | { | |
547 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
548 | int i; | |
549 | ||
550 | for (i = 0; i < 4; ++i) | |
551 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
552 | } | |
553 | ||
a345b23b | 554 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 555 | { |
3d06fca8 JR |
556 | int type, devid, domid, flags; |
557 | volatile u32 *event = __evt; | |
558 | int count = 0; | |
559 | u64 address; | |
560 | ||
561 | retry: | |
562 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
563 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
564 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
565 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
566 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
567 | ||
568 | if (type == 0) { | |
569 | /* Did we hit the erratum? */ | |
570 | if (++count == LOOP_TIMEOUT) { | |
571 | pr_err("AMD-Vi: No event written to event log\n"); | |
572 | return; | |
573 | } | |
574 | udelay(1); | |
575 | goto retry; | |
576 | } | |
90008ee4 | 577 | |
4c6f40d4 | 578 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
579 | |
580 | switch (type) { | |
581 | case EVENT_TYPE_ILL_DEV: | |
582 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
583 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 584 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 585 | address, flags); |
e3e59876 | 586 | dump_dte_entry(devid); |
90008ee4 JR |
587 | break; |
588 | case EVENT_TYPE_IO_FAULT: | |
589 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
590 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 591 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
592 | domid, address, flags); |
593 | break; | |
594 | case EVENT_TYPE_DEV_TAB_ERR: | |
595 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
596 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 597 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
598 | address, flags); |
599 | break; | |
600 | case EVENT_TYPE_PAGE_TAB_ERR: | |
601 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
602 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 603 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
604 | domid, address, flags); |
605 | break; | |
606 | case EVENT_TYPE_ILL_CMD: | |
607 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 608 | dump_command(address); |
90008ee4 JR |
609 | break; |
610 | case EVENT_TYPE_CMD_HARD_ERR: | |
611 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
612 | "flags=0x%04x]\n", address, flags); | |
613 | break; | |
614 | case EVENT_TYPE_IOTLB_INV_TO: | |
615 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
616 | "address=0x%016llx]\n", | |
c5081cd7 | 617 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
618 | address); |
619 | break; | |
620 | case EVENT_TYPE_INV_DEV_REQ: | |
621 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
622 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 623 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
624 | address, flags); |
625 | break; | |
626 | default: | |
627 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
628 | } | |
3d06fca8 JR |
629 | |
630 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
631 | } |
632 | ||
633 | static void iommu_poll_events(struct amd_iommu *iommu) | |
634 | { | |
635 | u32 head, tail; | |
90008ee4 JR |
636 | |
637 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
638 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
639 | ||
640 | while (head != tail) { | |
a345b23b | 641 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 642 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
643 | } |
644 | ||
645 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
646 | } |
647 | ||
eee53537 | 648 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
649 | { |
650 | struct amd_iommu_fault fault; | |
72e1dcc4 | 651 | |
72e1dcc4 JR |
652 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
653 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
654 | return; | |
655 | } | |
656 | ||
657 | fault.address = raw[1]; | |
658 | fault.pasid = PPR_PASID(raw[0]); | |
659 | fault.device_id = PPR_DEVID(raw[0]); | |
660 | fault.tag = PPR_TAG(raw[0]); | |
661 | fault.flags = PPR_FLAGS(raw[0]); | |
662 | ||
72e1dcc4 JR |
663 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
664 | } | |
665 | ||
666 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
667 | { | |
72e1dcc4 JR |
668 | u32 head, tail; |
669 | ||
670 | if (iommu->ppr_log == NULL) | |
671 | return; | |
672 | ||
72e1dcc4 JR |
673 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
674 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
675 | ||
676 | while (head != tail) { | |
eee53537 JR |
677 | volatile u64 *raw; |
678 | u64 entry[2]; | |
679 | int i; | |
680 | ||
681 | raw = (u64 *)(iommu->ppr_log + head); | |
682 | ||
683 | /* | |
684 | * Hardware bug: Interrupt may arrive before the entry is | |
685 | * written to memory. If this happens we need to wait for the | |
686 | * entry to arrive. | |
687 | */ | |
688 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
689 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
690 | break; | |
691 | udelay(1); | |
692 | } | |
72e1dcc4 | 693 | |
eee53537 JR |
694 | /* Avoid memcpy function-call overhead */ |
695 | entry[0] = raw[0]; | |
696 | entry[1] = raw[1]; | |
72e1dcc4 | 697 | |
eee53537 JR |
698 | /* |
699 | * To detect the hardware bug we need to clear the entry | |
700 | * back to zero. | |
701 | */ | |
702 | raw[0] = raw[1] = 0UL; | |
703 | ||
704 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
705 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
706 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 707 | |
eee53537 JR |
708 | /* Handle PPR entry */ |
709 | iommu_handle_ppr_entry(iommu, entry); | |
710 | ||
eee53537 JR |
711 | /* Refresh ring-buffer information */ |
712 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
713 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
714 | } | |
72e1dcc4 JR |
715 | } |
716 | ||
bd6fcefc SS |
717 | #ifdef CONFIG_IRQ_REMAP |
718 | static int (*iommu_ga_log_notifier)(u32); | |
719 | ||
720 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
721 | { | |
722 | iommu_ga_log_notifier = notifier; | |
723 | ||
724 | return 0; | |
725 | } | |
726 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
727 | ||
728 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
729 | { | |
730 | u32 head, tail, cnt = 0; | |
731 | ||
732 | if (iommu->ga_log == NULL) | |
733 | return; | |
734 | ||
735 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
736 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
737 | ||
738 | while (head != tail) { | |
739 | volatile u64 *raw; | |
740 | u64 log_entry; | |
741 | ||
742 | raw = (u64 *)(iommu->ga_log + head); | |
743 | cnt++; | |
744 | ||
745 | /* Avoid memcpy function-call overhead */ | |
746 | log_entry = *raw; | |
747 | ||
748 | /* Update head pointer of hardware ring-buffer */ | |
749 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
750 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
751 | ||
752 | /* Handle GA entry */ | |
753 | switch (GA_REQ_TYPE(log_entry)) { | |
754 | case GA_GUEST_NR: | |
755 | if (!iommu_ga_log_notifier) | |
756 | break; | |
757 | ||
758 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", | |
759 | __func__, GA_DEVID(log_entry), | |
760 | GA_TAG(log_entry)); | |
761 | ||
762 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
763 | pr_err("AMD-Vi: GA log notifier failed.\n"); | |
764 | break; | |
765 | default: | |
766 | break; | |
767 | } | |
768 | } | |
769 | } | |
770 | #endif /* CONFIG_IRQ_REMAP */ | |
771 | ||
772 | #define AMD_IOMMU_INT_MASK \ | |
773 | (MMIO_STATUS_EVT_INT_MASK | \ | |
774 | MMIO_STATUS_PPR_INT_MASK | \ | |
775 | MMIO_STATUS_GALOG_INT_MASK) | |
776 | ||
72fe00f0 | 777 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 778 | { |
3f398bc7 SS |
779 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
780 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 781 | |
bd6fcefc SS |
782 | while (status & AMD_IOMMU_INT_MASK) { |
783 | /* Enable EVT and PPR and GA interrupts again */ | |
784 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 785 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 786 | |
3f398bc7 SS |
787 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
788 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
789 | iommu_poll_events(iommu); | |
790 | } | |
90008ee4 | 791 | |
3f398bc7 SS |
792 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
793 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
794 | iommu_poll_ppr_log(iommu); | |
795 | } | |
90008ee4 | 796 | |
bd6fcefc SS |
797 | #ifdef CONFIG_IRQ_REMAP |
798 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
799 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); | |
800 | iommu_poll_ga_log(iommu); | |
801 | } | |
802 | #endif | |
803 | ||
3f398bc7 SS |
804 | /* |
805 | * Hardware bug: ERBT1312 | |
806 | * When re-enabling interrupt (by writing 1 | |
807 | * to clear the bit), the hardware might also try to set | |
808 | * the interrupt bit in the event status register. | |
809 | * In this scenario, the bit will be set, and disable | |
810 | * subsequent interrupts. | |
811 | * | |
812 | * Workaround: The IOMMU driver should read back the | |
813 | * status register and check if the interrupt bits are cleared. | |
814 | * If not, driver will need to go through the interrupt handler | |
815 | * again and re-clear the bits | |
816 | */ | |
817 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
818 | } | |
90008ee4 | 819 | return IRQ_HANDLED; |
a80dc3e0 JR |
820 | } |
821 | ||
72fe00f0 JR |
822 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
823 | { | |
824 | return IRQ_WAKE_THREAD; | |
825 | } | |
826 | ||
431b2a20 JR |
827 | /**************************************************************************** |
828 | * | |
829 | * IOMMU command queuing functions | |
830 | * | |
831 | ****************************************************************************/ | |
832 | ||
ac0ea6e9 JR |
833 | static int wait_on_sem(volatile u64 *sem) |
834 | { | |
835 | int i = 0; | |
836 | ||
837 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
838 | udelay(1); | |
839 | i += 1; | |
840 | } | |
841 | ||
842 | if (i == LOOP_TIMEOUT) { | |
843 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
844 | return -EIO; | |
845 | } | |
846 | ||
847 | return 0; | |
848 | } | |
849 | ||
850 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
851 | struct iommu_cmd *cmd, | |
852 | u32 tail) | |
a19ae1ec | 853 | { |
a19ae1ec JR |
854 | u8 *target; |
855 | ||
8a7c5ef3 | 856 | target = iommu->cmd_buf + tail; |
deba4bce | 857 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
858 | |
859 | /* Copy command to buffer */ | |
860 | memcpy(target, cmd, sizeof(*cmd)); | |
861 | ||
862 | /* Tell the IOMMU about it */ | |
a19ae1ec | 863 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 864 | } |
a19ae1ec | 865 | |
815b33fd | 866 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 867 | { |
815b33fd JR |
868 | WARN_ON(address & 0x7ULL); |
869 | ||
ded46737 | 870 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
871 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
872 | cmd->data[1] = upper_32_bits(__pa(address)); | |
873 | cmd->data[2] = 1; | |
ded46737 JR |
874 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
875 | } | |
876 | ||
94fe79e2 JR |
877 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
878 | { | |
879 | memset(cmd, 0, sizeof(*cmd)); | |
880 | cmd->data[0] = devid; | |
881 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
882 | } | |
883 | ||
11b6402c JR |
884 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
885 | size_t size, u16 domid, int pde) | |
886 | { | |
887 | u64 pages; | |
ae0cbbb1 | 888 | bool s; |
11b6402c JR |
889 | |
890 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 891 | s = false; |
11b6402c JR |
892 | |
893 | if (pages > 1) { | |
894 | /* | |
895 | * If we have to flush more than one page, flush all | |
896 | * TLB entries for this domain | |
897 | */ | |
898 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 899 | s = true; |
11b6402c JR |
900 | } |
901 | ||
902 | address &= PAGE_MASK; | |
903 | ||
904 | memset(cmd, 0, sizeof(*cmd)); | |
905 | cmd->data[1] |= domid; | |
906 | cmd->data[2] = lower_32_bits(address); | |
907 | cmd->data[3] = upper_32_bits(address); | |
908 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
909 | if (s) /* size bit - we flush more than one 4kb page */ | |
910 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 911 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
912 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
913 | } | |
914 | ||
cb41ed85 JR |
915 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
916 | u64 address, size_t size) | |
917 | { | |
918 | u64 pages; | |
ae0cbbb1 | 919 | bool s; |
cb41ed85 JR |
920 | |
921 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 922 | s = false; |
cb41ed85 JR |
923 | |
924 | if (pages > 1) { | |
925 | /* | |
926 | * If we have to flush more than one page, flush all | |
927 | * TLB entries for this domain | |
928 | */ | |
929 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 930 | s = true; |
cb41ed85 JR |
931 | } |
932 | ||
933 | address &= PAGE_MASK; | |
934 | ||
935 | memset(cmd, 0, sizeof(*cmd)); | |
936 | cmd->data[0] = devid; | |
937 | cmd->data[0] |= (qdep & 0xff) << 24; | |
938 | cmd->data[1] = devid; | |
939 | cmd->data[2] = lower_32_bits(address); | |
940 | cmd->data[3] = upper_32_bits(address); | |
941 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
942 | if (s) | |
943 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
944 | } | |
945 | ||
22e266c7 JR |
946 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
947 | u64 address, bool size) | |
948 | { | |
949 | memset(cmd, 0, sizeof(*cmd)); | |
950 | ||
951 | address &= ~(0xfffULL); | |
952 | ||
a919a018 | 953 | cmd->data[0] = pasid; |
22e266c7 JR |
954 | cmd->data[1] = domid; |
955 | cmd->data[2] = lower_32_bits(address); | |
956 | cmd->data[3] = upper_32_bits(address); | |
957 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
958 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
959 | if (size) | |
960 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
961 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
962 | } | |
963 | ||
964 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
965 | int qdep, u64 address, bool size) | |
966 | { | |
967 | memset(cmd, 0, sizeof(*cmd)); | |
968 | ||
969 | address &= ~(0xfffULL); | |
970 | ||
971 | cmd->data[0] = devid; | |
e8d2d82d | 972 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
973 | cmd->data[0] |= (qdep & 0xff) << 24; |
974 | cmd->data[1] = devid; | |
e8d2d82d | 975 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
976 | cmd->data[2] = lower_32_bits(address); |
977 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
978 | cmd->data[3] = upper_32_bits(address); | |
979 | if (size) | |
980 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
981 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
982 | } | |
983 | ||
c99afa25 JR |
984 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
985 | int status, int tag, bool gn) | |
986 | { | |
987 | memset(cmd, 0, sizeof(*cmd)); | |
988 | ||
989 | cmd->data[0] = devid; | |
990 | if (gn) { | |
a919a018 | 991 | cmd->data[1] = pasid; |
c99afa25 JR |
992 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
993 | } | |
994 | cmd->data[3] = tag & 0x1ff; | |
995 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
996 | ||
997 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
998 | } | |
999 | ||
58fc7f14 JR |
1000 | static void build_inv_all(struct iommu_cmd *cmd) |
1001 | { | |
1002 | memset(cmd, 0, sizeof(*cmd)); | |
1003 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1004 | } |
1005 | ||
7ef2798d JR |
1006 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1007 | { | |
1008 | memset(cmd, 0, sizeof(*cmd)); | |
1009 | cmd->data[0] = devid; | |
1010 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1011 | } | |
1012 | ||
431b2a20 | 1013 | /* |
431b2a20 | 1014 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1015 | * hardware about the new command. |
431b2a20 | 1016 | */ |
4bf5beef JR |
1017 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1018 | struct iommu_cmd *cmd, | |
1019 | bool sync) | |
a19ae1ec | 1020 | { |
ac0ea6e9 | 1021 | u32 left, tail, head, next_tail; |
a19ae1ec | 1022 | |
ac0ea6e9 | 1023 | again: |
a19ae1ec | 1024 | |
ac0ea6e9 JR |
1025 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
1026 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
1027 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
1028 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 1029 | |
432abf68 | 1030 | if (left <= 0x20) { |
ac0ea6e9 | 1031 | struct iommu_cmd sync_cmd; |
ac0ea6e9 | 1032 | int ret; |
8d201968 | 1033 | |
4bf5beef | 1034 | iommu->cmd_sem = 0; |
da49f6df | 1035 | |
4bf5beef JR |
1036 | build_completion_wait(&sync_cmd, (u64)&iommu->cmd_sem); |
1037 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
ac0ea6e9 | 1038 | |
4bf5beef | 1039 | if ((ret = wait_on_sem(&iommu->cmd_sem)) != 0) |
ac0ea6e9 JR |
1040 | return ret; |
1041 | ||
1042 | goto again; | |
8d201968 JR |
1043 | } |
1044 | ||
ac0ea6e9 JR |
1045 | copy_cmd_to_buffer(iommu, cmd, tail); |
1046 | ||
1047 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1048 | iommu->need_sync = sync; |
ac0ea6e9 | 1049 | |
4bf5beef JR |
1050 | return 0; |
1051 | } | |
1052 | ||
1053 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1054 | struct iommu_cmd *cmd, | |
1055 | bool sync) | |
1056 | { | |
1057 | unsigned long flags; | |
1058 | int ret; | |
1059 | ||
1060 | spin_lock_irqsave(&iommu->lock, flags); | |
1061 | ret = __iommu_queue_command_sync(iommu, cmd, sync); | |
a19ae1ec | 1062 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1063 | |
4bf5beef | 1064 | return ret; |
8d201968 JR |
1065 | } |
1066 | ||
f1ca1512 JR |
1067 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1068 | { | |
1069 | return iommu_queue_command_sync(iommu, cmd, true); | |
1070 | } | |
1071 | ||
8d201968 JR |
1072 | /* |
1073 | * This function queues a completion wait command into the command | |
1074 | * buffer of an IOMMU | |
1075 | */ | |
a19ae1ec | 1076 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1077 | { |
1078 | struct iommu_cmd cmd; | |
4bf5beef | 1079 | unsigned long flags; |
ac0ea6e9 | 1080 | int ret; |
8d201968 | 1081 | |
09ee17eb | 1082 | if (!iommu->need_sync) |
815b33fd | 1083 | return 0; |
09ee17eb | 1084 | |
a19ae1ec | 1085 | |
4bf5beef JR |
1086 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1087 | ||
1088 | spin_lock_irqsave(&iommu->lock, flags); | |
1089 | ||
1090 | iommu->cmd_sem = 0; | |
1091 | ||
1092 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1093 | if (ret) |
4bf5beef JR |
1094 | goto out_unlock; |
1095 | ||
1096 | ret = wait_on_sem(&iommu->cmd_sem); | |
1097 | ||
1098 | out_unlock: | |
1099 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8d201968 | 1100 | |
4bf5beef | 1101 | return ret; |
8d201968 JR |
1102 | } |
1103 | ||
d8c13085 | 1104 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1105 | { |
d8c13085 | 1106 | struct iommu_cmd cmd; |
a19ae1ec | 1107 | |
d8c13085 | 1108 | build_inv_dte(&cmd, devid); |
7e4f88da | 1109 | |
d8c13085 JR |
1110 | return iommu_queue_command(iommu, &cmd); |
1111 | } | |
09ee17eb | 1112 | |
7d0c5cc5 JR |
1113 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1114 | { | |
1115 | u32 devid; | |
09ee17eb | 1116 | |
7d0c5cc5 JR |
1117 | for (devid = 0; devid <= 0xffff; ++devid) |
1118 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1119 | |
7d0c5cc5 JR |
1120 | iommu_completion_wait(iommu); |
1121 | } | |
84df8175 | 1122 | |
7d0c5cc5 JR |
1123 | /* |
1124 | * This function uses heavy locking and may disable irqs for some time. But | |
1125 | * this is no issue because it is only called during resume. | |
1126 | */ | |
1127 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1128 | { | |
1129 | u32 dom_id; | |
a19ae1ec | 1130 | |
7d0c5cc5 JR |
1131 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1132 | struct iommu_cmd cmd; | |
1133 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1134 | dom_id, 1); | |
1135 | iommu_queue_command(iommu, &cmd); | |
1136 | } | |
8eed9833 | 1137 | |
7d0c5cc5 | 1138 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1139 | } |
1140 | ||
58fc7f14 | 1141 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1142 | { |
58fc7f14 | 1143 | struct iommu_cmd cmd; |
0518a3a4 | 1144 | |
58fc7f14 | 1145 | build_inv_all(&cmd); |
0518a3a4 | 1146 | |
58fc7f14 JR |
1147 | iommu_queue_command(iommu, &cmd); |
1148 | iommu_completion_wait(iommu); | |
1149 | } | |
1150 | ||
7ef2798d JR |
1151 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1152 | { | |
1153 | struct iommu_cmd cmd; | |
1154 | ||
1155 | build_inv_irt(&cmd, devid); | |
1156 | ||
1157 | iommu_queue_command(iommu, &cmd); | |
1158 | } | |
1159 | ||
1160 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1161 | { | |
1162 | u32 devid; | |
1163 | ||
1164 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1165 | iommu_flush_irt(iommu, devid); | |
1166 | ||
1167 | iommu_completion_wait(iommu); | |
1168 | } | |
1169 | ||
7d0c5cc5 JR |
1170 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1171 | { | |
58fc7f14 JR |
1172 | if (iommu_feature(iommu, FEATURE_IA)) { |
1173 | iommu_flush_all(iommu); | |
1174 | } else { | |
1175 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1176 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1177 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1178 | } |
1179 | } | |
1180 | ||
431b2a20 | 1181 | /* |
cb41ed85 | 1182 | * Command send function for flushing on-device TLB |
431b2a20 | 1183 | */ |
6c542047 JR |
1184 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1185 | u64 address, size_t size) | |
3fa43655 JR |
1186 | { |
1187 | struct amd_iommu *iommu; | |
b00d3bcf | 1188 | struct iommu_cmd cmd; |
cb41ed85 | 1189 | int qdep; |
3fa43655 | 1190 | |
ea61cddb JR |
1191 | qdep = dev_data->ats.qdep; |
1192 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1193 | |
ea61cddb | 1194 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1195 | |
1196 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1197 | } |
1198 | ||
431b2a20 | 1199 | /* |
431b2a20 | 1200 | * Command send function for invalidating a device table entry |
431b2a20 | 1201 | */ |
6c542047 | 1202 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1203 | { |
3fa43655 | 1204 | struct amd_iommu *iommu; |
e25bfb56 | 1205 | u16 alias; |
ee2fa743 | 1206 | int ret; |
a19ae1ec | 1207 | |
6c542047 | 1208 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1209 | alias = dev_data->alias; |
a19ae1ec | 1210 | |
f62dda66 | 1211 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1212 | if (!ret && alias != dev_data->devid) |
1213 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1214 | if (ret) |
1215 | return ret; | |
1216 | ||
ea61cddb | 1217 | if (dev_data->ats.enabled) |
6c542047 | 1218 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1219 | |
ee2fa743 | 1220 | return ret; |
a19ae1ec JR |
1221 | } |
1222 | ||
431b2a20 JR |
1223 | /* |
1224 | * TLB invalidation function which is called from the mapping functions. | |
1225 | * It invalidates a single PTE if the range to flush is within a single | |
1226 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1227 | */ | |
17b124bf JR |
1228 | static void __domain_flush_pages(struct protection_domain *domain, |
1229 | u64 address, size_t size, int pde) | |
a19ae1ec | 1230 | { |
cb41ed85 | 1231 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1232 | struct iommu_cmd cmd; |
1233 | int ret = 0, i; | |
a19ae1ec | 1234 | |
11b6402c | 1235 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1236 | |
6de8ad9b JR |
1237 | for (i = 0; i < amd_iommus_present; ++i) { |
1238 | if (!domain->dev_iommu[i]) | |
1239 | continue; | |
1240 | ||
1241 | /* | |
1242 | * Devices of this domain are behind this IOMMU | |
1243 | * We need a TLB flush | |
1244 | */ | |
11b6402c | 1245 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1246 | } |
1247 | ||
cb41ed85 | 1248 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1249 | |
ea61cddb | 1250 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1251 | continue; |
1252 | ||
6c542047 | 1253 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1254 | } |
1255 | ||
11b6402c | 1256 | WARN_ON(ret); |
6de8ad9b JR |
1257 | } |
1258 | ||
17b124bf JR |
1259 | static void domain_flush_pages(struct protection_domain *domain, |
1260 | u64 address, size_t size) | |
6de8ad9b | 1261 | { |
17b124bf | 1262 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1263 | } |
b6c02715 | 1264 | |
1c655773 | 1265 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1266 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1267 | { |
17b124bf | 1268 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1269 | } |
1270 | ||
42a49f96 | 1271 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1272 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1273 | { |
17b124bf | 1274 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1275 | } |
1276 | ||
17b124bf | 1277 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1278 | { |
17b124bf | 1279 | int i; |
18811f55 | 1280 | |
17b124bf | 1281 | for (i = 0; i < amd_iommus_present; ++i) { |
f1eae7c5 | 1282 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1283 | continue; |
bfd1be18 | 1284 | |
17b124bf JR |
1285 | /* |
1286 | * Devices of this domain are behind this IOMMU | |
1287 | * We need to wait for completion of all commands. | |
1288 | */ | |
1289 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1290 | } |
e394d72a JR |
1291 | } |
1292 | ||
b00d3bcf | 1293 | |
09b42804 | 1294 | /* |
b00d3bcf | 1295 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1296 | */ |
17b124bf | 1297 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1298 | { |
b00d3bcf | 1299 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1300 | |
b00d3bcf | 1301 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1302 | device_flush_dte(dev_data); |
a345b23b JR |
1303 | } |
1304 | ||
431b2a20 JR |
1305 | /**************************************************************************** |
1306 | * | |
1307 | * The functions below are used the create the page table mappings for | |
1308 | * unity mapped regions. | |
1309 | * | |
1310 | ****************************************************************************/ | |
1311 | ||
308973d3 JR |
1312 | /* |
1313 | * This function is used to add another level to an IO page table. Adding | |
1314 | * another level increases the size of the address space by 9 bits to a size up | |
1315 | * to 64 bits. | |
1316 | */ | |
1317 | static bool increase_address_space(struct protection_domain *domain, | |
1318 | gfp_t gfp) | |
1319 | { | |
1320 | u64 *pte; | |
1321 | ||
1322 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1323 | /* address space already 64 bit large */ | |
1324 | return false; | |
1325 | ||
1326 | pte = (void *)get_zeroed_page(gfp); | |
1327 | if (!pte) | |
1328 | return false; | |
1329 | ||
1330 | *pte = PM_LEVEL_PDE(domain->mode, | |
1331 | virt_to_phys(domain->pt_root)); | |
1332 | domain->pt_root = pte; | |
1333 | domain->mode += 1; | |
1334 | domain->updated = true; | |
1335 | ||
1336 | return true; | |
1337 | } | |
1338 | ||
1339 | static u64 *alloc_pte(struct protection_domain *domain, | |
1340 | unsigned long address, | |
cbb9d729 | 1341 | unsigned long page_size, |
308973d3 JR |
1342 | u64 **pte_page, |
1343 | gfp_t gfp) | |
1344 | { | |
cbb9d729 | 1345 | int level, end_lvl; |
308973d3 | 1346 | u64 *pte, *page; |
cbb9d729 JR |
1347 | |
1348 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1349 | |
1350 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1351 | increase_address_space(domain, gfp); | |
1352 | ||
cbb9d729 JR |
1353 | level = domain->mode - 1; |
1354 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1355 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1356 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1357 | |
1358 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1359 | u64 __pte, __npte; |
1360 | ||
1361 | __pte = *pte; | |
1362 | ||
1363 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1364 | page = (u64 *)get_zeroed_page(gfp); |
1365 | if (!page) | |
1366 | return NULL; | |
7bfa5bd2 JR |
1367 | |
1368 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1369 | ||
134414ff BH |
1370 | /* pte could have been changed somewhere. */ |
1371 | if (cmpxchg64(pte, __pte, __npte) != __pte) { | |
7bfa5bd2 JR |
1372 | free_page((unsigned long)page); |
1373 | continue; | |
1374 | } | |
308973d3 JR |
1375 | } |
1376 | ||
cbb9d729 JR |
1377 | /* No level skipping support yet */ |
1378 | if (PM_PTE_LEVEL(*pte) != level) | |
1379 | return NULL; | |
1380 | ||
308973d3 JR |
1381 | level -= 1; |
1382 | ||
1383 | pte = IOMMU_PTE_PAGE(*pte); | |
1384 | ||
1385 | if (pte_page && level == end_lvl) | |
1386 | *pte_page = pte; | |
1387 | ||
1388 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1389 | } | |
1390 | ||
1391 | return pte; | |
1392 | } | |
1393 | ||
1394 | /* | |
1395 | * This function checks if there is a PTE for a given dma address. If | |
1396 | * there is one, it returns the pointer to it. | |
1397 | */ | |
3039ca1b JR |
1398 | static u64 *fetch_pte(struct protection_domain *domain, |
1399 | unsigned long address, | |
1400 | unsigned long *page_size) | |
308973d3 JR |
1401 | { |
1402 | int level; | |
1403 | u64 *pte; | |
1404 | ||
24cd7723 JR |
1405 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1406 | return NULL; | |
1407 | ||
3039ca1b JR |
1408 | level = domain->mode - 1; |
1409 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1410 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1411 | |
24cd7723 JR |
1412 | while (level > 0) { |
1413 | ||
1414 | /* Not Present */ | |
308973d3 JR |
1415 | if (!IOMMU_PTE_PRESENT(*pte)) |
1416 | return NULL; | |
1417 | ||
24cd7723 | 1418 | /* Large PTE */ |
3039ca1b JR |
1419 | if (PM_PTE_LEVEL(*pte) == 7 || |
1420 | PM_PTE_LEVEL(*pte) == 0) | |
1421 | break; | |
24cd7723 JR |
1422 | |
1423 | /* No level skipping support yet */ | |
1424 | if (PM_PTE_LEVEL(*pte) != level) | |
1425 | return NULL; | |
1426 | ||
308973d3 JR |
1427 | level -= 1; |
1428 | ||
24cd7723 | 1429 | /* Walk to the next level */ |
3039ca1b JR |
1430 | pte = IOMMU_PTE_PAGE(*pte); |
1431 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1432 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1433 | } | |
1434 | ||
1435 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1436 | unsigned long pte_mask; | |
1437 | ||
1438 | /* | |
1439 | * If we have a series of large PTEs, make | |
1440 | * sure to return a pointer to the first one. | |
1441 | */ | |
1442 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1443 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1444 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1445 | } |
1446 | ||
1447 | return pte; | |
1448 | } | |
1449 | ||
431b2a20 JR |
1450 | /* |
1451 | * Generic mapping functions. It maps a physical address into a DMA | |
1452 | * address space. It allocates the page table pages if necessary. | |
1453 | * In the future it can be extended to a generic mapping function | |
1454 | * supporting all features of AMD IOMMU page tables like level skipping | |
1455 | * and full 64 bit address spaces. | |
1456 | */ | |
38e817fe JR |
1457 | static int iommu_map_page(struct protection_domain *dom, |
1458 | unsigned long bus_addr, | |
1459 | unsigned long phys_addr, | |
b911b89b | 1460 | unsigned long page_size, |
abdc5eb3 | 1461 | int prot, |
b911b89b | 1462 | gfp_t gfp) |
bd0e5211 | 1463 | { |
8bda3092 | 1464 | u64 __pte, *pte; |
cbb9d729 | 1465 | int i, count; |
abdc5eb3 | 1466 | |
d4b03664 JR |
1467 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1468 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1469 | ||
bad1cac2 | 1470 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1471 | return -EINVAL; |
1472 | ||
d4b03664 | 1473 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1474 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1475 | |
63eaa75e ML |
1476 | if (!pte) |
1477 | return -ENOMEM; | |
1478 | ||
cbb9d729 JR |
1479 | for (i = 0; i < count; ++i) |
1480 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1481 | return -EBUSY; | |
bd0e5211 | 1482 | |
d4b03664 | 1483 | if (count > 1) { |
cbb9d729 JR |
1484 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1485 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1486 | } else | |
1487 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1488 | |
bd0e5211 JR |
1489 | if (prot & IOMMU_PROT_IR) |
1490 | __pte |= IOMMU_PTE_IR; | |
1491 | if (prot & IOMMU_PROT_IW) | |
1492 | __pte |= IOMMU_PTE_IW; | |
1493 | ||
cbb9d729 JR |
1494 | for (i = 0; i < count; ++i) |
1495 | pte[i] = __pte; | |
bd0e5211 | 1496 | |
04bfdd84 JR |
1497 | update_domain(dom); |
1498 | ||
bd0e5211 JR |
1499 | return 0; |
1500 | } | |
1501 | ||
24cd7723 JR |
1502 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1503 | unsigned long bus_addr, | |
1504 | unsigned long page_size) | |
eb74ff6c | 1505 | { |
71b390e9 JR |
1506 | unsigned long long unmapped; |
1507 | unsigned long unmap_size; | |
24cd7723 JR |
1508 | u64 *pte; |
1509 | ||
1510 | BUG_ON(!is_power_of_2(page_size)); | |
1511 | ||
1512 | unmapped = 0; | |
eb74ff6c | 1513 | |
24cd7723 JR |
1514 | while (unmapped < page_size) { |
1515 | ||
71b390e9 JR |
1516 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1517 | ||
1518 | if (pte) { | |
1519 | int i, count; | |
1520 | ||
1521 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1522 | for (i = 0; i < count; i++) |
1523 | pte[i] = 0ULL; | |
1524 | } | |
1525 | ||
1526 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1527 | unmapped += unmap_size; | |
1528 | } | |
1529 | ||
60d0ca3c | 1530 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1531 | |
24cd7723 | 1532 | return unmapped; |
eb74ff6c | 1533 | } |
eb74ff6c | 1534 | |
431b2a20 JR |
1535 | /**************************************************************************** |
1536 | * | |
1537 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1538 | * interface functions. |
431b2a20 JR |
1539 | * |
1540 | ****************************************************************************/ | |
d3086444 | 1541 | |
9cabe89b | 1542 | |
256e4621 JR |
1543 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1544 | struct dma_ops_domain *dma_dom, | |
1545 | unsigned int pages, u64 dma_mask) | |
384de729 | 1546 | { |
256e4621 | 1547 | unsigned long pfn = 0; |
384de729 | 1548 | |
256e4621 | 1549 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1550 | |
256e4621 JR |
1551 | if (dma_mask > DMA_BIT_MASK(32)) |
1552 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
1553 | IOVA_PFN(DMA_BIT_MASK(32))); | |
7b5e25b8 | 1554 | |
256e4621 JR |
1555 | if (!pfn) |
1556 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask)); | |
5f6bed50 | 1557 | |
256e4621 | 1558 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1559 | } |
1560 | ||
256e4621 JR |
1561 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1562 | unsigned long address, | |
1563 | unsigned int pages) | |
d3086444 | 1564 | { |
256e4621 JR |
1565 | pages = __roundup_pow_of_two(pages); |
1566 | address >>= PAGE_SHIFT; | |
384de729 | 1567 | |
256e4621 | 1568 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1569 | } |
1570 | ||
431b2a20 JR |
1571 | /**************************************************************************** |
1572 | * | |
1573 | * The next functions belong to the domain allocation. A domain is | |
1574 | * allocated for every IOMMU as the default domain. If device isolation | |
1575 | * is enabled, every device get its own domain. The most important thing | |
1576 | * about domains is the page table mapping the DMA address space they | |
1577 | * contain. | |
1578 | * | |
1579 | ****************************************************************************/ | |
1580 | ||
aeb26f55 JR |
1581 | /* |
1582 | * This function adds a protection domain to the global protection domain list | |
1583 | */ | |
1584 | static void add_domain_to_list(struct protection_domain *domain) | |
1585 | { | |
1586 | unsigned long flags; | |
1587 | ||
1588 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1589 | list_add(&domain->list, &amd_iommu_pd_list); | |
1590 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1591 | } | |
1592 | ||
1593 | /* | |
1594 | * This function removes a protection domain to the global | |
1595 | * protection domain list | |
1596 | */ | |
1597 | static void del_domain_from_list(struct protection_domain *domain) | |
1598 | { | |
1599 | unsigned long flags; | |
1600 | ||
1601 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1602 | list_del(&domain->list); | |
1603 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1604 | } | |
1605 | ||
ec487d1a JR |
1606 | static u16 domain_id_alloc(void) |
1607 | { | |
1608 | unsigned long flags; | |
1609 | int id; | |
1610 | ||
1611 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1612 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1613 | BUG_ON(id == 0); | |
1614 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1615 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1616 | else | |
1617 | id = 0; | |
1618 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1619 | ||
1620 | return id; | |
1621 | } | |
1622 | ||
a2acfb75 JR |
1623 | static void domain_id_free(int id) |
1624 | { | |
1625 | unsigned long flags; | |
1626 | ||
1627 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1628 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1629 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1630 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1631 | } | |
a2acfb75 | 1632 | |
5c34c403 JR |
1633 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1634 | static void free_pt_##LVL (unsigned long __pt) \ | |
1635 | { \ | |
1636 | unsigned long p; \ | |
1637 | u64 *pt; \ | |
1638 | int i; \ | |
1639 | \ | |
1640 | pt = (u64 *)__pt; \ | |
1641 | \ | |
1642 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1643 | /* PTE present? */ \ |
5c34c403 JR |
1644 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1645 | continue; \ | |
1646 | \ | |
0b3fff54 JR |
1647 | /* Large PTE? */ \ |
1648 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1649 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1650 | continue; \ | |
1651 | \ | |
5c34c403 JR |
1652 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1653 | FN(p); \ | |
1654 | } \ | |
1655 | free_page((unsigned long)pt); \ | |
1656 | } | |
1657 | ||
1658 | DEFINE_FREE_PT_FN(l2, free_page) | |
1659 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1660 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1661 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1662 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1663 | ||
86db2e5d | 1664 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1665 | { |
5c34c403 | 1666 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1667 | |
5c34c403 JR |
1668 | switch (domain->mode) { |
1669 | case PAGE_MODE_NONE: | |
1670 | break; | |
1671 | case PAGE_MODE_1_LEVEL: | |
1672 | free_page(root); | |
1673 | break; | |
1674 | case PAGE_MODE_2_LEVEL: | |
1675 | free_pt_l2(root); | |
1676 | break; | |
1677 | case PAGE_MODE_3_LEVEL: | |
1678 | free_pt_l3(root); | |
1679 | break; | |
1680 | case PAGE_MODE_4_LEVEL: | |
1681 | free_pt_l4(root); | |
1682 | break; | |
1683 | case PAGE_MODE_5_LEVEL: | |
1684 | free_pt_l5(root); | |
1685 | break; | |
1686 | case PAGE_MODE_6_LEVEL: | |
1687 | free_pt_l6(root); | |
1688 | break; | |
1689 | default: | |
1690 | BUG(); | |
ec487d1a | 1691 | } |
ec487d1a JR |
1692 | } |
1693 | ||
b16137b1 JR |
1694 | static void free_gcr3_tbl_level1(u64 *tbl) |
1695 | { | |
1696 | u64 *ptr; | |
1697 | int i; | |
1698 | ||
1699 | for (i = 0; i < 512; ++i) { | |
1700 | if (!(tbl[i] & GCR3_VALID)) | |
1701 | continue; | |
1702 | ||
1703 | ptr = __va(tbl[i] & PAGE_MASK); | |
1704 | ||
1705 | free_page((unsigned long)ptr); | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1710 | { | |
1711 | u64 *ptr; | |
1712 | int i; | |
1713 | ||
1714 | for (i = 0; i < 512; ++i) { | |
1715 | if (!(tbl[i] & GCR3_VALID)) | |
1716 | continue; | |
1717 | ||
1718 | ptr = __va(tbl[i] & PAGE_MASK); | |
1719 | ||
1720 | free_gcr3_tbl_level1(ptr); | |
1721 | } | |
1722 | } | |
1723 | ||
52815b75 JR |
1724 | static void free_gcr3_table(struct protection_domain *domain) |
1725 | { | |
b16137b1 JR |
1726 | if (domain->glx == 2) |
1727 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1728 | else if (domain->glx == 1) | |
1729 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1730 | else |
1731 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1732 | |
52815b75 JR |
1733 | free_page((unsigned long)domain->gcr3_tbl); |
1734 | } | |
1735 | ||
431b2a20 JR |
1736 | /* |
1737 | * Free a domain, only used if something went wrong in the | |
1738 | * allocation path and we need to free an already allocated page table | |
1739 | */ | |
ec487d1a JR |
1740 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1741 | { | |
1742 | if (!dom) | |
1743 | return; | |
1744 | ||
aeb26f55 JR |
1745 | del_domain_from_list(&dom->domain); |
1746 | ||
2d4c515b | 1747 | put_iova_domain(&dom->iovad); |
ec487d1a | 1748 | |
2d4c515b | 1749 | free_pagetable(&dom->domain); |
ec487d1a | 1750 | |
c3db901c BH |
1751 | if (dom->domain.id) |
1752 | domain_id_free(dom->domain.id); | |
1753 | ||
ec487d1a JR |
1754 | kfree(dom); |
1755 | } | |
1756 | ||
431b2a20 JR |
1757 | /* |
1758 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1759 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1760 | * structures required for the dma_ops interface |
1761 | */ | |
87a64d52 | 1762 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1763 | { |
1764 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1765 | |
1766 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1767 | if (!dma_dom) | |
1768 | return NULL; | |
1769 | ||
7a5a566e | 1770 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1771 | goto free_dma_dom; |
7a5a566e | 1772 | |
ffec2197 | 1773 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1774 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1775 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1776 | if (!dma_dom->domain.pt_root) |
1777 | goto free_dma_dom; | |
ec487d1a | 1778 | |
307d5851 JR |
1779 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, |
1780 | IOVA_START_PFN, DMA_32BIT_PFN); | |
1781 | ||
81cd07b9 JR |
1782 | /* Initialize reserved ranges */ |
1783 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
1784 | ||
2d4c515b JR |
1785 | add_domain_to_list(&dma_dom->domain); |
1786 | ||
ec487d1a JR |
1787 | return dma_dom; |
1788 | ||
1789 | free_dma_dom: | |
1790 | dma_ops_domain_free(dma_dom); | |
1791 | ||
1792 | return NULL; | |
1793 | } | |
1794 | ||
5b28df6f JR |
1795 | /* |
1796 | * little helper function to check whether a given protection domain is a | |
1797 | * dma_ops domain | |
1798 | */ | |
1799 | static bool dma_ops_domain(struct protection_domain *domain) | |
1800 | { | |
1801 | return domain->flags & PD_DMA_OPS_MASK; | |
1802 | } | |
1803 | ||
fd7b5535 | 1804 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1805 | { |
132bd68f | 1806 | u64 pte_root = 0; |
ee6c2868 | 1807 | u64 flags = 0; |
863c74eb | 1808 | |
132bd68f JR |
1809 | if (domain->mode != PAGE_MODE_NONE) |
1810 | pte_root = virt_to_phys(domain->pt_root); | |
1811 | ||
38ddf41b JR |
1812 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1813 | << DEV_ENTRY_MODE_SHIFT; | |
1814 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1815 | |
ee6c2868 JR |
1816 | flags = amd_iommu_dev_table[devid].data[1]; |
1817 | ||
fd7b5535 JR |
1818 | if (ats) |
1819 | flags |= DTE_FLAG_IOTLB; | |
1820 | ||
52815b75 JR |
1821 | if (domain->flags & PD_IOMMUV2_MASK) { |
1822 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1823 | u64 glx = domain->glx; | |
1824 | u64 tmp; | |
1825 | ||
1826 | pte_root |= DTE_FLAG_GV; | |
1827 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1828 | ||
1829 | /* First mask out possible old values for GCR3 table */ | |
1830 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1831 | flags &= ~tmp; | |
1832 | ||
1833 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1834 | flags &= ~tmp; | |
1835 | ||
1836 | /* Encode GCR3 table into DTE */ | |
1837 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1838 | pte_root |= tmp; | |
1839 | ||
1840 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1841 | flags |= tmp; | |
1842 | ||
1843 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1844 | flags |= tmp; | |
1845 | } | |
1846 | ||
ee6c2868 JR |
1847 | flags &= ~(0xffffUL); |
1848 | flags |= domain->id; | |
1849 | ||
1850 | amd_iommu_dev_table[devid].data[1] = flags; | |
1851 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1852 | } |
1853 | ||
1854 | static void clear_dte_entry(u16 devid) | |
1855 | { | |
15898bbc | 1856 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
1857 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
1858 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
1859 | |
1860 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1861 | } |
1862 | ||
ec9e79ef JR |
1863 | static void do_attach(struct iommu_dev_data *dev_data, |
1864 | struct protection_domain *domain) | |
7f760ddd | 1865 | { |
7f760ddd | 1866 | struct amd_iommu *iommu; |
e25bfb56 | 1867 | u16 alias; |
ec9e79ef | 1868 | bool ats; |
fd7b5535 | 1869 | |
ec9e79ef | 1870 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1871 | alias = dev_data->alias; |
ec9e79ef | 1872 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1873 | |
1874 | /* Update data structures */ | |
1875 | dev_data->domain = domain; | |
1876 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1877 | |
1878 | /* Do reference counting */ | |
1879 | domain->dev_iommu[iommu->index] += 1; | |
1880 | domain->dev_cnt += 1; | |
1881 | ||
e25bfb56 JR |
1882 | /* Update device table */ |
1883 | set_dte_entry(dev_data->devid, domain, ats); | |
1884 | if (alias != dev_data->devid) | |
9b1a12d2 | 1885 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 1886 | |
6c542047 | 1887 | device_flush_dte(dev_data); |
7f760ddd JR |
1888 | } |
1889 | ||
ec9e79ef | 1890 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1891 | { |
7f760ddd | 1892 | struct amd_iommu *iommu; |
e25bfb56 | 1893 | u16 alias; |
7f760ddd | 1894 | |
5adad991 JR |
1895 | /* |
1896 | * First check if the device is still attached. It might already | |
1897 | * be detached from its domain because the generic | |
1898 | * iommu_detach_group code detached it and we try again here in | |
1899 | * our alias handling. | |
1900 | */ | |
1901 | if (!dev_data->domain) | |
1902 | return; | |
1903 | ||
ec9e79ef | 1904 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1905 | alias = dev_data->alias; |
15898bbc JR |
1906 | |
1907 | /* decrease reference counters */ | |
7f760ddd JR |
1908 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1909 | dev_data->domain->dev_cnt -= 1; | |
1910 | ||
1911 | /* Update data structures */ | |
1912 | dev_data->domain = NULL; | |
1913 | list_del(&dev_data->list); | |
f62dda66 | 1914 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1915 | if (alias != dev_data->devid) |
1916 | clear_dte_entry(alias); | |
15898bbc | 1917 | |
7f760ddd | 1918 | /* Flush the DTE entry */ |
6c542047 | 1919 | device_flush_dte(dev_data); |
2b681faf JR |
1920 | } |
1921 | ||
1922 | /* | |
1923 | * If a device is not yet associated with a domain, this function does | |
1924 | * assigns it visible for the hardware | |
1925 | */ | |
ec9e79ef | 1926 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1927 | struct protection_domain *domain) |
2b681faf | 1928 | { |
84fe6c19 | 1929 | int ret; |
657cbb6b | 1930 | |
272e4f99 JR |
1931 | /* |
1932 | * Must be called with IRQs disabled. Warn here to detect early | |
1933 | * when its not. | |
1934 | */ | |
1935 | WARN_ON(!irqs_disabled()); | |
1936 | ||
2b681faf JR |
1937 | /* lock domain */ |
1938 | spin_lock(&domain->lock); | |
1939 | ||
397111ab | 1940 | ret = -EBUSY; |
150952f9 | 1941 | if (dev_data->domain != NULL) |
397111ab | 1942 | goto out_unlock; |
15898bbc | 1943 | |
397111ab | 1944 | /* Attach alias group root */ |
150952f9 | 1945 | do_attach(dev_data, domain); |
24100055 | 1946 | |
84fe6c19 JL |
1947 | ret = 0; |
1948 | ||
1949 | out_unlock: | |
1950 | ||
eba6ac60 JR |
1951 | /* ready */ |
1952 | spin_unlock(&domain->lock); | |
15898bbc | 1953 | |
84fe6c19 | 1954 | return ret; |
0feae533 | 1955 | } |
b20ac0d4 | 1956 | |
52815b75 JR |
1957 | |
1958 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1959 | { | |
1960 | pci_disable_ats(pdev); | |
1961 | pci_disable_pri(pdev); | |
1962 | pci_disable_pasid(pdev); | |
1963 | } | |
1964 | ||
6a113ddc JR |
1965 | /* FIXME: Change generic reset-function to do the same */ |
1966 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1967 | { | |
1968 | u16 control; | |
1969 | int pos; | |
1970 | ||
46277b75 | 1971 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
1972 | if (!pos) |
1973 | return -EINVAL; | |
1974 | ||
46277b75 JR |
1975 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
1976 | control |= PCI_PRI_CTRL_RESET; | |
1977 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
1978 | |
1979 | return 0; | |
1980 | } | |
1981 | ||
52815b75 JR |
1982 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
1983 | { | |
6a113ddc JR |
1984 | bool reset_enable; |
1985 | int reqs, ret; | |
1986 | ||
1987 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1988 | reqs = 32; | |
1989 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
1990 | reqs = 1; | |
1991 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
1992 | |
1993 | /* Only allow access to user-accessible pages */ | |
1994 | ret = pci_enable_pasid(pdev, 0); | |
1995 | if (ret) | |
1996 | goto out_err; | |
1997 | ||
1998 | /* First reset the PRI state of the device */ | |
1999 | ret = pci_reset_pri(pdev); | |
2000 | if (ret) | |
2001 | goto out_err; | |
2002 | ||
6a113ddc JR |
2003 | /* Enable PRI */ |
2004 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2005 | if (ret) |
2006 | goto out_err; | |
2007 | ||
6a113ddc JR |
2008 | if (reset_enable) { |
2009 | ret = pri_reset_while_enabled(pdev); | |
2010 | if (ret) | |
2011 | goto out_err; | |
2012 | } | |
2013 | ||
52815b75 JR |
2014 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2015 | if (ret) | |
2016 | goto out_err; | |
2017 | ||
2018 | return 0; | |
2019 | ||
2020 | out_err: | |
2021 | pci_disable_pri(pdev); | |
2022 | pci_disable_pasid(pdev); | |
2023 | ||
2024 | return ret; | |
2025 | } | |
2026 | ||
c99afa25 | 2027 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2028 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2029 | |
98f1ad25 | 2030 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2031 | { |
a3b93121 | 2032 | u16 status; |
c99afa25 JR |
2033 | int pos; |
2034 | ||
46277b75 | 2035 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2036 | if (!pos) |
2037 | return false; | |
2038 | ||
a3b93121 | 2039 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2040 | |
a3b93121 | 2041 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2042 | } |
2043 | ||
407d733e | 2044 | /* |
df805abb | 2045 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2046 | * assigns it visible for the hardware |
2047 | */ | |
15898bbc JR |
2048 | static int attach_device(struct device *dev, |
2049 | struct protection_domain *domain) | |
0feae533 | 2050 | { |
2bf9a0a1 | 2051 | struct pci_dev *pdev; |
ea61cddb | 2052 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2053 | unsigned long flags; |
15898bbc | 2054 | int ret; |
eba6ac60 | 2055 | |
ea61cddb JR |
2056 | dev_data = get_dev_data(dev); |
2057 | ||
2bf9a0a1 WZ |
2058 | if (!dev_is_pci(dev)) |
2059 | goto skip_ats_check; | |
2060 | ||
2061 | pdev = to_pci_dev(dev); | |
52815b75 | 2062 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2063 | if (!dev_data->passthrough) |
52815b75 JR |
2064 | return -EINVAL; |
2065 | ||
02ca2021 JR |
2066 | if (dev_data->iommu_v2) { |
2067 | if (pdev_iommuv2_enable(pdev) != 0) | |
2068 | return -EINVAL; | |
52815b75 | 2069 | |
02ca2021 JR |
2070 | dev_data->ats.enabled = true; |
2071 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2072 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2073 | } | |
52815b75 JR |
2074 | } else if (amd_iommu_iotlb_sup && |
2075 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2076 | dev_data->ats.enabled = true; |
2077 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2078 | } | |
fd7b5535 | 2079 | |
2bf9a0a1 | 2080 | skip_ats_check: |
eba6ac60 | 2081 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2082 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2083 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2084 | ||
0feae533 JR |
2085 | /* |
2086 | * We might boot into a crash-kernel here. The crashed kernel | |
2087 | * left the caches in the IOMMU dirty. So we have to flush | |
2088 | * here to evict all dirty stuff. | |
2089 | */ | |
17b124bf | 2090 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2091 | |
2092 | return ret; | |
b20ac0d4 JR |
2093 | } |
2094 | ||
355bf553 JR |
2095 | /* |
2096 | * Removes a device from a protection domain (unlocked) | |
2097 | */ | |
ec9e79ef | 2098 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2099 | { |
2ca76279 | 2100 | struct protection_domain *domain; |
c4596114 | 2101 | |
272e4f99 JR |
2102 | /* |
2103 | * Must be called with IRQs disabled. Warn here to detect early | |
2104 | * when its not. | |
2105 | */ | |
2106 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2107 | |
f34c73f5 JR |
2108 | if (WARN_ON(!dev_data->domain)) |
2109 | return; | |
24100055 | 2110 | |
2ca76279 | 2111 | domain = dev_data->domain; |
71f77580 | 2112 | |
f1dd0a8b | 2113 | spin_lock(&domain->lock); |
24100055 | 2114 | |
150952f9 | 2115 | do_detach(dev_data); |
7f760ddd | 2116 | |
f1dd0a8b | 2117 | spin_unlock(&domain->lock); |
355bf553 JR |
2118 | } |
2119 | ||
2120 | /* | |
2121 | * Removes a device from a protection domain (with devtable_lock held) | |
2122 | */ | |
15898bbc | 2123 | static void detach_device(struct device *dev) |
355bf553 | 2124 | { |
52815b75 | 2125 | struct protection_domain *domain; |
ea61cddb | 2126 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2127 | unsigned long flags; |
2128 | ||
ec9e79ef | 2129 | dev_data = get_dev_data(dev); |
52815b75 | 2130 | domain = dev_data->domain; |
ec9e79ef | 2131 | |
355bf553 JR |
2132 | /* lock device table */ |
2133 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2134 | __detach_device(dev_data); |
355bf553 | 2135 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2136 | |
2bf9a0a1 WZ |
2137 | if (!dev_is_pci(dev)) |
2138 | return; | |
2139 | ||
02ca2021 | 2140 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2141 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2142 | else if (dev_data->ats.enabled) | |
ea61cddb | 2143 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2144 | |
2145 | dev_data->ats.enabled = false; | |
355bf553 | 2146 | } |
e275a2a0 | 2147 | |
aafd8ba0 | 2148 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2149 | { |
5abcdba4 | 2150 | struct iommu_dev_data *dev_data; |
07ee8694 | 2151 | struct iommu_domain *domain; |
e275a2a0 | 2152 | struct amd_iommu *iommu; |
7aba6cb9 | 2153 | int ret, devid; |
e275a2a0 | 2154 | |
aafd8ba0 | 2155 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2156 | return 0; |
e275a2a0 | 2157 | |
aafd8ba0 | 2158 | devid = get_device_id(dev); |
9ee35e4c | 2159 | if (devid < 0) |
7aba6cb9 WZ |
2160 | return devid; |
2161 | ||
aafd8ba0 | 2162 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2163 | |
aafd8ba0 | 2164 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2165 | if (ret) { |
2166 | if (ret != -ENOTSUPP) | |
2167 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2168 | dev_name(dev)); | |
657cbb6b | 2169 | |
aafd8ba0 | 2170 | iommu_ignore_device(dev); |
343e9cac | 2171 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2172 | goto out; |
2173 | } | |
2174 | init_iommu_group(dev); | |
2c9195e9 | 2175 | |
07ee8694 | 2176 | dev_data = get_dev_data(dev); |
2c9195e9 | 2177 | |
4d58b8a6 | 2178 | BUG_ON(!dev_data); |
657cbb6b | 2179 | |
1e6a7b04 | 2180 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2181 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2182 | |
07ee8694 JR |
2183 | /* Domains are initialized for this device - have a look what we ended up with */ |
2184 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2185 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2186 | dev_data->passthrough = true; |
32302324 | 2187 | else |
2c9195e9 | 2188 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2189 | |
aafd8ba0 | 2190 | out: |
e275a2a0 JR |
2191 | iommu_completion_wait(iommu); |
2192 | ||
e275a2a0 JR |
2193 | return 0; |
2194 | } | |
2195 | ||
aafd8ba0 | 2196 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2197 | { |
aafd8ba0 | 2198 | struct amd_iommu *iommu; |
7aba6cb9 | 2199 | int devid; |
aafd8ba0 JR |
2200 | |
2201 | if (!check_device(dev)) | |
2202 | return; | |
2203 | ||
2204 | devid = get_device_id(dev); | |
9ee35e4c | 2205 | if (devid < 0) |
7aba6cb9 WZ |
2206 | return; |
2207 | ||
aafd8ba0 JR |
2208 | iommu = amd_iommu_rlookup_table[devid]; |
2209 | ||
2210 | iommu_uninit_device(dev); | |
2211 | iommu_completion_wait(iommu); | |
8638c491 JR |
2212 | } |
2213 | ||
b097d11a WZ |
2214 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2215 | { | |
2216 | if (dev_is_pci(dev)) | |
2217 | return pci_device_group(dev); | |
2218 | ||
2219 | return acpihid_device_group(dev); | |
2220 | } | |
2221 | ||
431b2a20 JR |
2222 | /***************************************************************************** |
2223 | * | |
2224 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2225 | * | |
2226 | *****************************************************************************/ | |
2227 | ||
b1516a14 JR |
2228 | static void __queue_flush(struct flush_queue *queue) |
2229 | { | |
2230 | struct protection_domain *domain; | |
2231 | unsigned long flags; | |
2232 | int idx; | |
2233 | ||
2234 | /* First flush TLB of all known domains */ | |
2235 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
2236 | list_for_each_entry(domain, &amd_iommu_pd_list, list) | |
2237 | domain_flush_tlb(domain); | |
2238 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
2239 | ||
2240 | /* Wait until flushes have completed */ | |
2241 | domain_flush_complete(NULL); | |
2242 | ||
2243 | for (idx = 0; idx < queue->next; ++idx) { | |
2244 | struct flush_queue_entry *entry; | |
2245 | ||
2246 | entry = queue->entries + idx; | |
2247 | ||
2248 | free_iova_fast(&entry->dma_dom->iovad, | |
2249 | entry->iova_pfn, | |
2250 | entry->pages); | |
2251 | ||
2252 | /* Not really necessary, just to make sure we catch any bugs */ | |
2253 | entry->dma_dom = NULL; | |
2254 | } | |
2255 | ||
2256 | queue->next = 0; | |
2257 | } | |
2258 | ||
281e8ccb | 2259 | static void queue_flush_all(void) |
bb279475 JR |
2260 | { |
2261 | int cpu; | |
2262 | ||
bb279475 JR |
2263 | for_each_possible_cpu(cpu) { |
2264 | struct flush_queue *queue; | |
2265 | unsigned long flags; | |
2266 | ||
2267 | queue = per_cpu_ptr(&flush_queue, cpu); | |
2268 | spin_lock_irqsave(&queue->lock, flags); | |
2269 | if (queue->next > 0) | |
2270 | __queue_flush(queue); | |
2271 | spin_unlock_irqrestore(&queue->lock, flags); | |
2272 | } | |
2273 | } | |
2274 | ||
281e8ccb JR |
2275 | static void queue_flush_timeout(unsigned long unsused) |
2276 | { | |
2277 | atomic_set(&queue_timer_on, 0); | |
2278 | queue_flush_all(); | |
2279 | } | |
2280 | ||
b1516a14 JR |
2281 | static void queue_add(struct dma_ops_domain *dma_dom, |
2282 | unsigned long address, unsigned long pages) | |
2283 | { | |
2284 | struct flush_queue_entry *entry; | |
2285 | struct flush_queue *queue; | |
2286 | unsigned long flags; | |
2287 | int idx; | |
2288 | ||
2289 | pages = __roundup_pow_of_two(pages); | |
2290 | address >>= PAGE_SHIFT; | |
2291 | ||
2292 | queue = get_cpu_ptr(&flush_queue); | |
2293 | spin_lock_irqsave(&queue->lock, flags); | |
2294 | ||
2295 | if (queue->next == FLUSH_QUEUE_SIZE) | |
2296 | __queue_flush(queue); | |
2297 | ||
2298 | idx = queue->next++; | |
2299 | entry = queue->entries + idx; | |
2300 | ||
2301 | entry->iova_pfn = address; | |
2302 | entry->pages = pages; | |
2303 | entry->dma_dom = dma_dom; | |
2304 | ||
2305 | spin_unlock_irqrestore(&queue->lock, flags); | |
bb279475 JR |
2306 | |
2307 | if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0) | |
2308 | mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10)); | |
2309 | ||
b1516a14 JR |
2310 | put_cpu_ptr(&flush_queue); |
2311 | } | |
2312 | ||
2313 | ||
431b2a20 JR |
2314 | /* |
2315 | * In the dma_ops path we only have the struct device. This function | |
2316 | * finds the corresponding IOMMU, the protection domain and the | |
2317 | * requestor id for a given device. | |
2318 | * If the device is not yet associated with a domain this is also done | |
2319 | * in this function. | |
2320 | */ | |
94f6d190 | 2321 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2322 | { |
94f6d190 | 2323 | struct protection_domain *domain; |
b20ac0d4 | 2324 | |
f99c0f1c | 2325 | if (!check_device(dev)) |
94f6d190 | 2326 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2327 | |
d26592a9 | 2328 | domain = get_dev_data(dev)->domain; |
0bb6e243 | 2329 | if (!dma_ops_domain(domain)) |
94f6d190 | 2330 | return ERR_PTR(-EBUSY); |
f91ba190 | 2331 | |
0bb6e243 | 2332 | return domain; |
b20ac0d4 JR |
2333 | } |
2334 | ||
04bfdd84 JR |
2335 | static void update_device_table(struct protection_domain *domain) |
2336 | { | |
492667da | 2337 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2338 | |
3254de6b | 2339 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ea61cddb | 2340 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); |
3254de6b JR |
2341 | |
2342 | if (dev_data->devid == dev_data->alias) | |
2343 | continue; | |
2344 | ||
2345 | /* There is an alias, update device table entry for it */ | |
2346 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled); | |
2347 | } | |
04bfdd84 JR |
2348 | } |
2349 | ||
2350 | static void update_domain(struct protection_domain *domain) | |
2351 | { | |
2352 | if (!domain->updated) | |
2353 | return; | |
2354 | ||
2355 | update_device_table(domain); | |
17b124bf JR |
2356 | |
2357 | domain_flush_devices(domain); | |
2358 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2359 | |
2360 | domain->updated = false; | |
2361 | } | |
2362 | ||
f37f7f33 JR |
2363 | static int dir2prot(enum dma_data_direction direction) |
2364 | { | |
2365 | if (direction == DMA_TO_DEVICE) | |
2366 | return IOMMU_PROT_IR; | |
2367 | else if (direction == DMA_FROM_DEVICE) | |
2368 | return IOMMU_PROT_IW; | |
2369 | else if (direction == DMA_BIDIRECTIONAL) | |
2370 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2371 | else | |
2372 | return 0; | |
2373 | } | |
431b2a20 JR |
2374 | /* |
2375 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2376 | * contiguous memory region into DMA address space. It is used by all |
2377 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2378 | * Must be called with the domain lock held. |
2379 | */ | |
cb76c322 | 2380 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2381 | struct dma_ops_domain *dma_dom, |
2382 | phys_addr_t paddr, | |
2383 | size_t size, | |
f37f7f33 | 2384 | enum dma_data_direction direction, |
832a90c3 | 2385 | u64 dma_mask) |
cb76c322 JR |
2386 | { |
2387 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2388 | dma_addr_t address, start, ret; |
cb76c322 | 2389 | unsigned int pages; |
518d9b45 | 2390 | int prot = 0; |
cb76c322 JR |
2391 | int i; |
2392 | ||
e3c449f5 | 2393 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2394 | paddr &= PAGE_MASK; |
2395 | ||
256e4621 | 2396 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
266a3bd2 JR |
2397 | if (address == DMA_ERROR_CODE) |
2398 | goto out; | |
cb76c322 | 2399 | |
f37f7f33 | 2400 | prot = dir2prot(direction); |
518d9b45 | 2401 | |
cb76c322 JR |
2402 | start = address; |
2403 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2404 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2405 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2406 | if (ret) | |
53812c11 JR |
2407 | goto out_unmap; |
2408 | ||
cb76c322 JR |
2409 | paddr += PAGE_SIZE; |
2410 | start += PAGE_SIZE; | |
2411 | } | |
2412 | address += offset; | |
2413 | ||
ab7032bb | 2414 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2415 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2416 | domain_flush_complete(&dma_dom->domain); |
2417 | } | |
270cab24 | 2418 | |
cb76c322 JR |
2419 | out: |
2420 | return address; | |
53812c11 JR |
2421 | |
2422 | out_unmap: | |
2423 | ||
2424 | for (--i; i >= 0; --i) { | |
2425 | start -= PAGE_SIZE; | |
518d9b45 | 2426 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2427 | } |
2428 | ||
256e4621 JR |
2429 | domain_flush_tlb(&dma_dom->domain); |
2430 | domain_flush_complete(&dma_dom->domain); | |
2431 | ||
2432 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2433 | |
8fd524b3 | 2434 | return DMA_ERROR_CODE; |
cb76c322 JR |
2435 | } |
2436 | ||
431b2a20 JR |
2437 | /* |
2438 | * Does the reverse of the __map_single function. Must be called with | |
2439 | * the domain lock held too | |
2440 | */ | |
cd8c82e8 | 2441 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2442 | dma_addr_t dma_addr, |
2443 | size_t size, | |
2444 | int dir) | |
2445 | { | |
04e0463e | 2446 | dma_addr_t flush_addr; |
cb76c322 JR |
2447 | dma_addr_t i, start; |
2448 | unsigned int pages; | |
2449 | ||
04e0463e | 2450 | flush_addr = dma_addr; |
e3c449f5 | 2451 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2452 | dma_addr &= PAGE_MASK; |
2453 | start = dma_addr; | |
2454 | ||
2455 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2456 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2457 | start += PAGE_SIZE; |
2458 | } | |
2459 | ||
b1516a14 JR |
2460 | if (amd_iommu_unmap_flush) { |
2461 | dma_ops_free_iova(dma_dom, dma_addr, pages); | |
2462 | domain_flush_tlb(&dma_dom->domain); | |
2463 | domain_flush_complete(&dma_dom->domain); | |
2464 | } else { | |
2465 | queue_add(dma_dom, dma_addr, pages); | |
2466 | } | |
cb76c322 JR |
2467 | } |
2468 | ||
431b2a20 JR |
2469 | /* |
2470 | * The exported map_single function for dma_ops. | |
2471 | */ | |
51491367 FT |
2472 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2473 | unsigned long offset, size_t size, | |
2474 | enum dma_data_direction dir, | |
00085f1e | 2475 | unsigned long attrs) |
4da70b9e | 2476 | { |
92d420ec | 2477 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2478 | struct protection_domain *domain; |
b3311b06 | 2479 | struct dma_ops_domain *dma_dom; |
832a90c3 | 2480 | u64 dma_mask; |
4da70b9e | 2481 | |
94f6d190 JR |
2482 | domain = get_domain(dev); |
2483 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2484 | return (dma_addr_t)paddr; |
94f6d190 JR |
2485 | else if (IS_ERR(domain)) |
2486 | return DMA_ERROR_CODE; | |
4da70b9e | 2487 | |
f99c0f1c | 2488 | dma_mask = *dev->dma_mask; |
b3311b06 | 2489 | dma_dom = to_dma_ops_domain(domain); |
f99c0f1c | 2490 | |
b3311b06 | 2491 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2492 | } |
2493 | ||
431b2a20 JR |
2494 | /* |
2495 | * The exported unmap_single function for dma_ops. | |
2496 | */ | |
51491367 | 2497 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2498 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2499 | { |
4da70b9e | 2500 | struct protection_domain *domain; |
b3311b06 | 2501 | struct dma_ops_domain *dma_dom; |
4da70b9e | 2502 | |
94f6d190 JR |
2503 | domain = get_domain(dev); |
2504 | if (IS_ERR(domain)) | |
5b28df6f JR |
2505 | return; |
2506 | ||
b3311b06 JR |
2507 | dma_dom = to_dma_ops_domain(domain); |
2508 | ||
2509 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2510 | } |
2511 | ||
80187fd3 JR |
2512 | static int sg_num_pages(struct device *dev, |
2513 | struct scatterlist *sglist, | |
2514 | int nelems) | |
2515 | { | |
2516 | unsigned long mask, boundary_size; | |
2517 | struct scatterlist *s; | |
2518 | int i, npages = 0; | |
2519 | ||
2520 | mask = dma_get_seg_boundary(dev); | |
2521 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2522 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2523 | ||
2524 | for_each_sg(sglist, s, nelems, i) { | |
2525 | int p, n; | |
2526 | ||
2527 | s->dma_address = npages << PAGE_SHIFT; | |
2528 | p = npages % boundary_size; | |
2529 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2530 | if (p + n > boundary_size) | |
2531 | npages += boundary_size - p; | |
2532 | npages += n; | |
2533 | } | |
2534 | ||
2535 | return npages; | |
2536 | } | |
2537 | ||
431b2a20 JR |
2538 | /* |
2539 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2540 | * lists). | |
2541 | */ | |
65b050ad | 2542 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2543 | int nelems, enum dma_data_direction direction, |
00085f1e | 2544 | unsigned long attrs) |
65b050ad | 2545 | { |
80187fd3 | 2546 | int mapped_pages = 0, npages = 0, prot = 0, i; |
65b050ad | 2547 | struct protection_domain *domain; |
80187fd3 | 2548 | struct dma_ops_domain *dma_dom; |
65b050ad | 2549 | struct scatterlist *s; |
80187fd3 | 2550 | unsigned long address; |
832a90c3 | 2551 | u64 dma_mask; |
65b050ad | 2552 | |
94f6d190 | 2553 | domain = get_domain(dev); |
a0e191b2 | 2554 | if (IS_ERR(domain)) |
94f6d190 | 2555 | return 0; |
dbcc112e | 2556 | |
b3311b06 | 2557 | dma_dom = to_dma_ops_domain(domain); |
832a90c3 | 2558 | dma_mask = *dev->dma_mask; |
65b050ad | 2559 | |
80187fd3 JR |
2560 | npages = sg_num_pages(dev, sglist, nelems); |
2561 | ||
2562 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
2563 | if (address == DMA_ERROR_CODE) | |
2564 | goto out_err; | |
2565 | ||
2566 | prot = dir2prot(direction); | |
2567 | ||
2568 | /* Map all sg entries */ | |
65b050ad | 2569 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2570 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2571 | ||
2572 | for (j = 0; j < pages; ++j) { | |
2573 | unsigned long bus_addr, phys_addr; | |
2574 | int ret; | |
65b050ad | 2575 | |
80187fd3 JR |
2576 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2577 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2578 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2579 | if (ret) | |
2580 | goto out_unmap; | |
65b050ad | 2581 | |
80187fd3 JR |
2582 | mapped_pages += 1; |
2583 | } | |
65b050ad JR |
2584 | } |
2585 | ||
80187fd3 JR |
2586 | /* Everything is mapped - write the right values into s->dma_address */ |
2587 | for_each_sg(sglist, s, nelems, i) { | |
2588 | s->dma_address += address + s->offset; | |
2589 | s->dma_length = s->length; | |
2590 | } | |
2591 | ||
2592 | return nelems; | |
2593 | ||
2594 | out_unmap: | |
2595 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2596 | dev_name(dev), npages); | |
2597 | ||
2598 | for_each_sg(sglist, s, nelems, i) { | |
2599 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2600 | ||
2601 | for (j = 0; j < pages; ++j) { | |
2602 | unsigned long bus_addr; | |
92d420ec | 2603 | |
80187fd3 JR |
2604 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2605 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2606 | ||
2607 | if (--mapped_pages) | |
2608 | goto out_free_iova; | |
2609 | } | |
65b050ad JR |
2610 | } |
2611 | ||
80187fd3 JR |
2612 | out_free_iova: |
2613 | free_iova_fast(&dma_dom->iovad, address, npages); | |
2614 | ||
2615 | out_err: | |
92d420ec | 2616 | return 0; |
65b050ad JR |
2617 | } |
2618 | ||
431b2a20 JR |
2619 | /* |
2620 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2621 | * lists). | |
2622 | */ | |
65b050ad | 2623 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2624 | int nelems, enum dma_data_direction dir, |
00085f1e | 2625 | unsigned long attrs) |
65b050ad | 2626 | { |
65b050ad | 2627 | struct protection_domain *domain; |
b3311b06 | 2628 | struct dma_ops_domain *dma_dom; |
80187fd3 JR |
2629 | unsigned long startaddr; |
2630 | int npages = 2; | |
65b050ad | 2631 | |
94f6d190 JR |
2632 | domain = get_domain(dev); |
2633 | if (IS_ERR(domain)) | |
5b28df6f JR |
2634 | return; |
2635 | ||
80187fd3 | 2636 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
b3311b06 | 2637 | dma_dom = to_dma_ops_domain(domain); |
80187fd3 JR |
2638 | npages = sg_num_pages(dev, sglist, nelems); |
2639 | ||
b3311b06 | 2640 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2641 | } |
2642 | ||
431b2a20 JR |
2643 | /* |
2644 | * The exported alloc_coherent function for dma_ops. | |
2645 | */ | |
5d8b53cf | 2646 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2647 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2648 | unsigned long attrs) |
5d8b53cf | 2649 | { |
832a90c3 | 2650 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2651 | struct protection_domain *domain; |
b3311b06 | 2652 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2653 | struct page *page; |
5d8b53cf | 2654 | |
94f6d190 JR |
2655 | domain = get_domain(dev); |
2656 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2657 | page = alloc_pages(flag, get_order(size)); |
2658 | *dma_addr = page_to_phys(page); | |
2659 | return page_address(page); | |
94f6d190 JR |
2660 | } else if (IS_ERR(domain)) |
2661 | return NULL; | |
5d8b53cf | 2662 | |
b3311b06 | 2663 | dma_dom = to_dma_ops_domain(domain); |
3b839a57 | 2664 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2665 | dma_mask = dev->coherent_dma_mask; |
2666 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2667 | flag |= __GFP_ZERO; |
5d8b53cf | 2668 | |
3b839a57 JR |
2669 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2670 | if (!page) { | |
d0164adc | 2671 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2672 | return NULL; |
5d8b53cf | 2673 | |
3b839a57 JR |
2674 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2675 | get_order(size)); | |
2676 | if (!page) | |
2677 | return NULL; | |
2678 | } | |
5d8b53cf | 2679 | |
832a90c3 JR |
2680 | if (!dma_mask) |
2681 | dma_mask = *dev->dma_mask; | |
2682 | ||
b3311b06 | 2683 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
bda350db | 2684 | size, DMA_BIDIRECTIONAL, dma_mask); |
5d8b53cf | 2685 | |
92d420ec | 2686 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2687 | goto out_free; |
5d8b53cf | 2688 | |
3b839a57 | 2689 | return page_address(page); |
5b28df6f JR |
2690 | |
2691 | out_free: | |
2692 | ||
3b839a57 JR |
2693 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2694 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2695 | |
2696 | return NULL; | |
5d8b53cf JR |
2697 | } |
2698 | ||
431b2a20 JR |
2699 | /* |
2700 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2701 | */ |
5d8b53cf | 2702 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2703 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2704 | unsigned long attrs) |
5d8b53cf | 2705 | { |
5d8b53cf | 2706 | struct protection_domain *domain; |
b3311b06 | 2707 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2708 | struct page *page; |
5d8b53cf | 2709 | |
3b839a57 JR |
2710 | page = virt_to_page(virt_addr); |
2711 | size = PAGE_ALIGN(size); | |
2712 | ||
94f6d190 JR |
2713 | domain = get_domain(dev); |
2714 | if (IS_ERR(domain)) | |
5b28df6f JR |
2715 | goto free_mem; |
2716 | ||
b3311b06 JR |
2717 | dma_dom = to_dma_ops_domain(domain); |
2718 | ||
2719 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2720 | |
5d8b53cf | 2721 | free_mem: |
3b839a57 JR |
2722 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2723 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2724 | } |
2725 | ||
b39ba6ad JR |
2726 | /* |
2727 | * This function is called by the DMA layer to find out if we can handle a | |
2728 | * particular device. It is part of the dma_ops. | |
2729 | */ | |
2730 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2731 | { | |
420aef8a | 2732 | return check_device(dev); |
b39ba6ad JR |
2733 | } |
2734 | ||
160c1d8e | 2735 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2736 | .alloc = alloc_coherent, |
2737 | .free = free_coherent, | |
2738 | .map_page = map_page, | |
2739 | .unmap_page = unmap_page, | |
2740 | .map_sg = map_sg, | |
2741 | .unmap_sg = unmap_sg, | |
2742 | .dma_supported = amd_iommu_dma_supported, | |
6631ee9d JR |
2743 | }; |
2744 | ||
81cd07b9 JR |
2745 | static int init_reserved_iova_ranges(void) |
2746 | { | |
2747 | struct pci_dev *pdev = NULL; | |
2748 | struct iova *val; | |
2749 | ||
2750 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, | |
2751 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2752 | ||
2753 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2754 | &reserved_rbtree_key); | |
2755 | ||
2756 | /* MSI memory range */ | |
2757 | val = reserve_iova(&reserved_iova_ranges, | |
2758 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2759 | if (!val) { | |
2760 | pr_err("Reserving MSI range failed\n"); | |
2761 | return -ENOMEM; | |
2762 | } | |
2763 | ||
2764 | /* HT memory range */ | |
2765 | val = reserve_iova(&reserved_iova_ranges, | |
2766 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2767 | if (!val) { | |
2768 | pr_err("Reserving HT range failed\n"); | |
2769 | return -ENOMEM; | |
2770 | } | |
2771 | ||
2772 | /* | |
2773 | * Memory used for PCI resources | |
2774 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2775 | */ | |
2776 | for_each_pci_dev(pdev) { | |
2777 | int i; | |
2778 | ||
2779 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2780 | struct resource *r = &pdev->resource[i]; | |
2781 | ||
2782 | if (!(r->flags & IORESOURCE_MEM)) | |
2783 | continue; | |
2784 | ||
2785 | val = reserve_iova(&reserved_iova_ranges, | |
2786 | IOVA_PFN(r->start), | |
2787 | IOVA_PFN(r->end)); | |
2788 | if (!val) { | |
2789 | pr_err("Reserve pci-resource range failed\n"); | |
2790 | return -ENOMEM; | |
2791 | } | |
2792 | } | |
2793 | } | |
2794 | ||
2795 | return 0; | |
2796 | } | |
2797 | ||
3a18404c | 2798 | int __init amd_iommu_init_api(void) |
27c2127a | 2799 | { |
c5b5da9c | 2800 | int ret, cpu, err = 0; |
307d5851 JR |
2801 | |
2802 | ret = iova_cache_get(); | |
2803 | if (ret) | |
2804 | return ret; | |
9a4d3bf5 | 2805 | |
81cd07b9 JR |
2806 | ret = init_reserved_iova_ranges(); |
2807 | if (ret) | |
2808 | return ret; | |
2809 | ||
c5b5da9c JR |
2810 | for_each_possible_cpu(cpu) { |
2811 | struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu); | |
2812 | ||
2813 | queue->entries = kzalloc(FLUSH_QUEUE_SIZE * | |
2814 | sizeof(*queue->entries), | |
2815 | GFP_KERNEL); | |
2816 | if (!queue->entries) | |
2817 | goto out_put_iova; | |
2818 | ||
2819 | spin_lock_init(&queue->lock); | |
2820 | } | |
2821 | ||
9a4d3bf5 WZ |
2822 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2823 | if (err) | |
2824 | return err; | |
2825 | #ifdef CONFIG_ARM_AMBA | |
2826 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2827 | if (err) | |
2828 | return err; | |
2829 | #endif | |
0076cd3d WZ |
2830 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2831 | if (err) | |
2832 | return err; | |
9a4d3bf5 | 2833 | return 0; |
c5b5da9c JR |
2834 | |
2835 | out_put_iova: | |
2836 | for_each_possible_cpu(cpu) { | |
2837 | struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu); | |
2838 | ||
2839 | kfree(queue->entries); | |
2840 | } | |
2841 | ||
2842 | return -ENOMEM; | |
f5325094 JR |
2843 | } |
2844 | ||
6631ee9d JR |
2845 | int __init amd_iommu_init_dma_ops(void) |
2846 | { | |
bb279475 JR |
2847 | setup_timer(&queue_timer, queue_flush_timeout, 0); |
2848 | atomic_set(&queue_timer_on, 0); | |
2849 | ||
32302324 | 2850 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2851 | iommu_detected = 1; |
6631ee9d | 2852 | |
52717828 JR |
2853 | /* |
2854 | * In case we don't initialize SWIOTLB (actually the common case | |
2855 | * when AMD IOMMU is enabled), make sure there are global | |
2856 | * dma_ops set as a fall-back for devices not handled by this | |
2857 | * driver (for example non-PCI devices). | |
2858 | */ | |
2859 | if (!swiotlb) | |
2860 | dma_ops = &nommu_dma_ops; | |
2861 | ||
62410eeb JR |
2862 | if (amd_iommu_unmap_flush) |
2863 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2864 | else | |
2865 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2866 | ||
6631ee9d | 2867 | return 0; |
c5b5da9c | 2868 | |
6631ee9d | 2869 | } |
6d98cd80 JR |
2870 | |
2871 | /***************************************************************************** | |
2872 | * | |
2873 | * The following functions belong to the exported interface of AMD IOMMU | |
2874 | * | |
2875 | * This interface allows access to lower level functions of the IOMMU | |
2876 | * like protection domain handling and assignement of devices to domains | |
2877 | * which is not possible with the dma_ops interface. | |
2878 | * | |
2879 | *****************************************************************************/ | |
2880 | ||
6d98cd80 JR |
2881 | static void cleanup_domain(struct protection_domain *domain) |
2882 | { | |
9b29d3c6 | 2883 | struct iommu_dev_data *entry; |
6d98cd80 | 2884 | unsigned long flags; |
6d98cd80 JR |
2885 | |
2886 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2887 | ||
9b29d3c6 JR |
2888 | while (!list_empty(&domain->dev_list)) { |
2889 | entry = list_first_entry(&domain->dev_list, | |
2890 | struct iommu_dev_data, list); | |
2891 | __detach_device(entry); | |
492667da | 2892 | } |
6d98cd80 JR |
2893 | |
2894 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2895 | } | |
2896 | ||
2650815f JR |
2897 | static void protection_domain_free(struct protection_domain *domain) |
2898 | { | |
2899 | if (!domain) | |
2900 | return; | |
2901 | ||
aeb26f55 JR |
2902 | del_domain_from_list(domain); |
2903 | ||
2650815f JR |
2904 | if (domain->id) |
2905 | domain_id_free(domain->id); | |
2906 | ||
2907 | kfree(domain); | |
2908 | } | |
2909 | ||
7a5a566e JR |
2910 | static int protection_domain_init(struct protection_domain *domain) |
2911 | { | |
2912 | spin_lock_init(&domain->lock); | |
2913 | mutex_init(&domain->api_lock); | |
2914 | domain->id = domain_id_alloc(); | |
2915 | if (!domain->id) | |
2916 | return -ENOMEM; | |
2917 | INIT_LIST_HEAD(&domain->dev_list); | |
2918 | ||
2919 | return 0; | |
2920 | } | |
2921 | ||
2650815f | 2922 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2923 | { |
2924 | struct protection_domain *domain; | |
2925 | ||
2926 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2927 | if (!domain) | |
2650815f | 2928 | return NULL; |
c156e347 | 2929 | |
7a5a566e | 2930 | if (protection_domain_init(domain)) |
2650815f JR |
2931 | goto out_err; |
2932 | ||
aeb26f55 JR |
2933 | add_domain_to_list(domain); |
2934 | ||
2650815f JR |
2935 | return domain; |
2936 | ||
2937 | out_err: | |
2938 | kfree(domain); | |
2939 | ||
2940 | return NULL; | |
2941 | } | |
2942 | ||
3f4b87b9 | 2943 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2944 | { |
3f4b87b9 | 2945 | struct protection_domain *pdomain; |
0bb6e243 | 2946 | struct dma_ops_domain *dma_domain; |
2650815f | 2947 | |
0bb6e243 JR |
2948 | switch (type) { |
2949 | case IOMMU_DOMAIN_UNMANAGED: | |
2950 | pdomain = protection_domain_alloc(); | |
2951 | if (!pdomain) | |
2952 | return NULL; | |
c156e347 | 2953 | |
0bb6e243 JR |
2954 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2955 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2956 | if (!pdomain->pt_root) { | |
2957 | protection_domain_free(pdomain); | |
2958 | return NULL; | |
2959 | } | |
c156e347 | 2960 | |
0bb6e243 JR |
2961 | pdomain->domain.geometry.aperture_start = 0; |
2962 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2963 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2964 | |
0bb6e243 JR |
2965 | break; |
2966 | case IOMMU_DOMAIN_DMA: | |
2967 | dma_domain = dma_ops_domain_alloc(); | |
2968 | if (!dma_domain) { | |
2969 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2970 | return NULL; | |
2971 | } | |
2972 | pdomain = &dma_domain->domain; | |
2973 | break; | |
07f643a3 JR |
2974 | case IOMMU_DOMAIN_IDENTITY: |
2975 | pdomain = protection_domain_alloc(); | |
2976 | if (!pdomain) | |
2977 | return NULL; | |
c156e347 | 2978 | |
07f643a3 JR |
2979 | pdomain->mode = PAGE_MODE_NONE; |
2980 | break; | |
0bb6e243 JR |
2981 | default: |
2982 | return NULL; | |
2983 | } | |
c156e347 | 2984 | |
3f4b87b9 | 2985 | return &pdomain->domain; |
c156e347 JR |
2986 | } |
2987 | ||
3f4b87b9 | 2988 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2989 | { |
3f4b87b9 | 2990 | struct protection_domain *domain; |
cda7005b | 2991 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2992 | |
3f4b87b9 JR |
2993 | domain = to_pdomain(dom); |
2994 | ||
98383fc3 JR |
2995 | if (domain->dev_cnt > 0) |
2996 | cleanup_domain(domain); | |
2997 | ||
2998 | BUG_ON(domain->dev_cnt != 0); | |
2999 | ||
cda7005b JR |
3000 | if (!dom) |
3001 | return; | |
98383fc3 | 3002 | |
cda7005b JR |
3003 | switch (dom->type) { |
3004 | case IOMMU_DOMAIN_DMA: | |
281e8ccb JR |
3005 | /* |
3006 | * First make sure the domain is no longer referenced from the | |
3007 | * flush queue | |
3008 | */ | |
3009 | queue_flush_all(); | |
3010 | ||
3011 | /* Now release the domain */ | |
b3311b06 | 3012 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
3013 | dma_ops_domain_free(dma_dom); |
3014 | break; | |
3015 | default: | |
3016 | if (domain->mode != PAGE_MODE_NONE) | |
3017 | free_pagetable(domain); | |
52815b75 | 3018 | |
cda7005b JR |
3019 | if (domain->flags & PD_IOMMUV2_MASK) |
3020 | free_gcr3_table(domain); | |
3021 | ||
3022 | protection_domain_free(domain); | |
3023 | break; | |
3024 | } | |
98383fc3 JR |
3025 | } |
3026 | ||
684f2888 JR |
3027 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3028 | struct device *dev) | |
3029 | { | |
657cbb6b | 3030 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3031 | struct amd_iommu *iommu; |
7aba6cb9 | 3032 | int devid; |
684f2888 | 3033 | |
98fc5a69 | 3034 | if (!check_device(dev)) |
684f2888 JR |
3035 | return; |
3036 | ||
98fc5a69 | 3037 | devid = get_device_id(dev); |
9ee35e4c | 3038 | if (devid < 0) |
7aba6cb9 | 3039 | return; |
684f2888 | 3040 | |
657cbb6b | 3041 | if (dev_data->domain != NULL) |
15898bbc | 3042 | detach_device(dev); |
684f2888 JR |
3043 | |
3044 | iommu = amd_iommu_rlookup_table[devid]; | |
3045 | if (!iommu) | |
3046 | return; | |
3047 | ||
d98de49a SS |
3048 | #ifdef CONFIG_IRQ_REMAP |
3049 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
3050 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
3051 | dev_data->use_vapic = 0; | |
3052 | #endif | |
3053 | ||
684f2888 JR |
3054 | iommu_completion_wait(iommu); |
3055 | } | |
3056 | ||
01106066 JR |
3057 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3058 | struct device *dev) | |
3059 | { | |
3f4b87b9 | 3060 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3061 | struct iommu_dev_data *dev_data; |
01106066 | 3062 | struct amd_iommu *iommu; |
15898bbc | 3063 | int ret; |
01106066 | 3064 | |
98fc5a69 | 3065 | if (!check_device(dev)) |
01106066 JR |
3066 | return -EINVAL; |
3067 | ||
657cbb6b JR |
3068 | dev_data = dev->archdata.iommu; |
3069 | ||
f62dda66 | 3070 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3071 | if (!iommu) |
3072 | return -EINVAL; | |
3073 | ||
657cbb6b | 3074 | if (dev_data->domain) |
15898bbc | 3075 | detach_device(dev); |
01106066 | 3076 | |
15898bbc | 3077 | ret = attach_device(dev, domain); |
01106066 | 3078 | |
d98de49a SS |
3079 | #ifdef CONFIG_IRQ_REMAP |
3080 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3081 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3082 | dev_data->use_vapic = 1; | |
3083 | else | |
3084 | dev_data->use_vapic = 0; | |
3085 | } | |
3086 | #endif | |
3087 | ||
01106066 JR |
3088 | iommu_completion_wait(iommu); |
3089 | ||
15898bbc | 3090 | return ret; |
01106066 JR |
3091 | } |
3092 | ||
468e2366 | 3093 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3094 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3095 | { |
3f4b87b9 | 3096 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3097 | int prot = 0; |
3098 | int ret; | |
3099 | ||
132bd68f JR |
3100 | if (domain->mode == PAGE_MODE_NONE) |
3101 | return -EINVAL; | |
3102 | ||
c6229ca6 JR |
3103 | if (iommu_prot & IOMMU_READ) |
3104 | prot |= IOMMU_PROT_IR; | |
3105 | if (iommu_prot & IOMMU_WRITE) | |
3106 | prot |= IOMMU_PROT_IW; | |
3107 | ||
5d214fe6 | 3108 | mutex_lock(&domain->api_lock); |
b911b89b | 3109 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3110 | mutex_unlock(&domain->api_lock); |
3111 | ||
795e74f7 | 3112 | return ret; |
c6229ca6 JR |
3113 | } |
3114 | ||
5009065d OBC |
3115 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3116 | size_t page_size) | |
eb74ff6c | 3117 | { |
3f4b87b9 | 3118 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3119 | size_t unmap_size; |
eb74ff6c | 3120 | |
132bd68f JR |
3121 | if (domain->mode == PAGE_MODE_NONE) |
3122 | return -EINVAL; | |
3123 | ||
5d214fe6 | 3124 | mutex_lock(&domain->api_lock); |
468e2366 | 3125 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3126 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3127 | |
17b124bf | 3128 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3129 | |
5009065d | 3130 | return unmap_size; |
eb74ff6c JR |
3131 | } |
3132 | ||
645c4c8d | 3133 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3134 | dma_addr_t iova) |
645c4c8d | 3135 | { |
3f4b87b9 | 3136 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3137 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3138 | u64 *pte, __pte; |
645c4c8d | 3139 | |
132bd68f JR |
3140 | if (domain->mode == PAGE_MODE_NONE) |
3141 | return iova; | |
3142 | ||
3039ca1b | 3143 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3144 | |
a6d41a40 | 3145 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3146 | return 0; |
3147 | ||
b24b1b63 JR |
3148 | offset_mask = pte_pgsize - 1; |
3149 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3150 | |
b24b1b63 | 3151 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3152 | } |
3153 | ||
ab636481 | 3154 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3155 | { |
80a506b8 JR |
3156 | switch (cap) { |
3157 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3158 | return true; |
bdddadcb | 3159 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3160 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3161 | case IOMMU_CAP_NOEXEC: |
3162 | return false; | |
80a506b8 JR |
3163 | } |
3164 | ||
ab636481 | 3165 | return false; |
dbb9fd86 SY |
3166 | } |
3167 | ||
e5b5234a EA |
3168 | static void amd_iommu_get_resv_regions(struct device *dev, |
3169 | struct list_head *head) | |
35cf248f | 3170 | { |
4397f32c | 3171 | struct iommu_resv_region *region; |
35cf248f | 3172 | struct unity_map_entry *entry; |
7aba6cb9 | 3173 | int devid; |
35cf248f JR |
3174 | |
3175 | devid = get_device_id(dev); | |
9ee35e4c | 3176 | if (devid < 0) |
7aba6cb9 | 3177 | return; |
35cf248f JR |
3178 | |
3179 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
4397f32c EA |
3180 | size_t length; |
3181 | int prot = 0; | |
35cf248f JR |
3182 | |
3183 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3184 | continue; | |
3185 | ||
4397f32c EA |
3186 | length = entry->address_end - entry->address_start; |
3187 | if (entry->prot & IOMMU_PROT_IR) | |
3188 | prot |= IOMMU_READ; | |
3189 | if (entry->prot & IOMMU_PROT_IW) | |
3190 | prot |= IOMMU_WRITE; | |
3191 | ||
3192 | region = iommu_alloc_resv_region(entry->address_start, | |
3193 | length, prot, | |
3194 | IOMMU_RESV_DIRECT); | |
35cf248f JR |
3195 | if (!region) { |
3196 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3197 | dev_name(dev)); | |
3198 | return; | |
3199 | } | |
35cf248f JR |
3200 | list_add_tail(®ion->list, head); |
3201 | } | |
4397f32c EA |
3202 | |
3203 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3204 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
3205 | 0, IOMMU_RESV_RESERVED); | |
3206 | if (!region) | |
3207 | return; | |
3208 | list_add_tail(®ion->list, head); | |
3209 | ||
3210 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3211 | HT_RANGE_END - HT_RANGE_START + 1, | |
3212 | 0, IOMMU_RESV_RESERVED); | |
3213 | if (!region) | |
3214 | return; | |
3215 | list_add_tail(®ion->list, head); | |
35cf248f JR |
3216 | } |
3217 | ||
e5b5234a | 3218 | static void amd_iommu_put_resv_regions(struct device *dev, |
35cf248f JR |
3219 | struct list_head *head) |
3220 | { | |
e5b5234a | 3221 | struct iommu_resv_region *entry, *next; |
35cf248f JR |
3222 | |
3223 | list_for_each_entry_safe(entry, next, head, list) | |
3224 | kfree(entry); | |
3225 | } | |
3226 | ||
e5b5234a | 3227 | static void amd_iommu_apply_resv_region(struct device *dev, |
8d54d6c8 | 3228 | struct iommu_domain *domain, |
e5b5234a | 3229 | struct iommu_resv_region *region) |
8d54d6c8 | 3230 | { |
b3311b06 | 3231 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3232 | unsigned long start, end; |
3233 | ||
3234 | start = IOVA_PFN(region->start); | |
3235 | end = IOVA_PFN(region->start + region->length); | |
3236 | ||
3237 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3238 | } | |
3239 | ||
b0119e87 | 3240 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3241 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3242 | .domain_alloc = amd_iommu_domain_alloc, |
3243 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3244 | .attach_dev = amd_iommu_attach_device, |
3245 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3246 | .map = amd_iommu_map, |
3247 | .unmap = amd_iommu_unmap, | |
315786eb | 3248 | .map_sg = default_iommu_map_sg, |
26961efe | 3249 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3250 | .add_device = amd_iommu_add_device, |
3251 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3252 | .device_group = amd_iommu_device_group, |
e5b5234a EA |
3253 | .get_resv_regions = amd_iommu_get_resv_regions, |
3254 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3255 | .apply_resv_region = amd_iommu_apply_resv_region, | |
aa3de9c0 | 3256 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3257 | }; |
3258 | ||
0feae533 JR |
3259 | /***************************************************************************** |
3260 | * | |
3261 | * The next functions do a basic initialization of IOMMU for pass through | |
3262 | * mode | |
3263 | * | |
3264 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3265 | * DMA-API translation. | |
3266 | * | |
3267 | *****************************************************************************/ | |
3268 | ||
72e1dcc4 JR |
3269 | /* IOMMUv2 specific functions */ |
3270 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3271 | { | |
3272 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3273 | } | |
3274 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3275 | ||
3276 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3277 | { | |
3278 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3279 | } | |
3280 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3281 | |
3282 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3283 | { | |
3f4b87b9 | 3284 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3285 | unsigned long flags; |
3286 | ||
3287 | spin_lock_irqsave(&domain->lock, flags); | |
3288 | ||
3289 | /* Update data structure */ | |
3290 | domain->mode = PAGE_MODE_NONE; | |
3291 | domain->updated = true; | |
3292 | ||
3293 | /* Make changes visible to IOMMUs */ | |
3294 | update_domain(domain); | |
3295 | ||
3296 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3297 | free_pagetable(domain); | |
3298 | ||
3299 | spin_unlock_irqrestore(&domain->lock, flags); | |
3300 | } | |
3301 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3302 | |
3303 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3304 | { | |
3f4b87b9 | 3305 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3306 | unsigned long flags; |
3307 | int levels, ret; | |
3308 | ||
3309 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3310 | return -EINVAL; | |
3311 | ||
3312 | /* Number of GCR3 table levels required */ | |
3313 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3314 | levels += 1; | |
3315 | ||
3316 | if (levels > amd_iommu_max_glx_val) | |
3317 | return -EINVAL; | |
3318 | ||
3319 | spin_lock_irqsave(&domain->lock, flags); | |
3320 | ||
3321 | /* | |
3322 | * Save us all sanity checks whether devices already in the | |
3323 | * domain support IOMMUv2. Just force that the domain has no | |
3324 | * devices attached when it is switched into IOMMUv2 mode. | |
3325 | */ | |
3326 | ret = -EBUSY; | |
3327 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3328 | goto out; | |
3329 | ||
3330 | ret = -ENOMEM; | |
3331 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3332 | if (domain->gcr3_tbl == NULL) | |
3333 | goto out; | |
3334 | ||
3335 | domain->glx = levels; | |
3336 | domain->flags |= PD_IOMMUV2_MASK; | |
3337 | domain->updated = true; | |
3338 | ||
3339 | update_domain(domain); | |
3340 | ||
3341 | ret = 0; | |
3342 | ||
3343 | out: | |
3344 | spin_unlock_irqrestore(&domain->lock, flags); | |
3345 | ||
3346 | return ret; | |
3347 | } | |
3348 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3349 | |
3350 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3351 | u64 address, bool size) | |
3352 | { | |
3353 | struct iommu_dev_data *dev_data; | |
3354 | struct iommu_cmd cmd; | |
3355 | int i, ret; | |
3356 | ||
3357 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3358 | return -EINVAL; | |
3359 | ||
3360 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3361 | ||
3362 | /* | |
3363 | * IOMMU TLB needs to be flushed before Device TLB to | |
3364 | * prevent device TLB refill from IOMMU TLB | |
3365 | */ | |
3366 | for (i = 0; i < amd_iommus_present; ++i) { | |
3367 | if (domain->dev_iommu[i] == 0) | |
3368 | continue; | |
3369 | ||
3370 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3371 | if (ret != 0) | |
3372 | goto out; | |
3373 | } | |
3374 | ||
3375 | /* Wait until IOMMU TLB flushes are complete */ | |
3376 | domain_flush_complete(domain); | |
3377 | ||
3378 | /* Now flush device TLBs */ | |
3379 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3380 | struct amd_iommu *iommu; | |
3381 | int qdep; | |
3382 | ||
1c1cc454 JR |
3383 | /* |
3384 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3385 | * domain. | |
3386 | */ | |
3387 | if (!dev_data->ats.enabled) | |
3388 | continue; | |
22e266c7 JR |
3389 | |
3390 | qdep = dev_data->ats.qdep; | |
3391 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3392 | ||
3393 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3394 | qdep, address, size); | |
3395 | ||
3396 | ret = iommu_queue_command(iommu, &cmd); | |
3397 | if (ret != 0) | |
3398 | goto out; | |
3399 | } | |
3400 | ||
3401 | /* Wait until all device TLBs are flushed */ | |
3402 | domain_flush_complete(domain); | |
3403 | ||
3404 | ret = 0; | |
3405 | ||
3406 | out: | |
3407 | ||
3408 | return ret; | |
3409 | } | |
3410 | ||
3411 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3412 | u64 address) | |
3413 | { | |
3414 | return __flush_pasid(domain, pasid, address, false); | |
3415 | } | |
3416 | ||
3417 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3418 | u64 address) | |
3419 | { | |
3f4b87b9 | 3420 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3421 | unsigned long flags; |
3422 | int ret; | |
3423 | ||
3424 | spin_lock_irqsave(&domain->lock, flags); | |
3425 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3426 | spin_unlock_irqrestore(&domain->lock, flags); | |
3427 | ||
3428 | return ret; | |
3429 | } | |
3430 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3431 | ||
3432 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3433 | { | |
3434 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3435 | true); | |
3436 | } | |
3437 | ||
3438 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3439 | { | |
3f4b87b9 | 3440 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3441 | unsigned long flags; |
3442 | int ret; | |
3443 | ||
3444 | spin_lock_irqsave(&domain->lock, flags); | |
3445 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3446 | spin_unlock_irqrestore(&domain->lock, flags); | |
3447 | ||
3448 | return ret; | |
3449 | } | |
3450 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3451 | ||
b16137b1 JR |
3452 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3453 | { | |
3454 | int index; | |
3455 | u64 *pte; | |
3456 | ||
3457 | while (true) { | |
3458 | ||
3459 | index = (pasid >> (9 * level)) & 0x1ff; | |
3460 | pte = &root[index]; | |
3461 | ||
3462 | if (level == 0) | |
3463 | break; | |
3464 | ||
3465 | if (!(*pte & GCR3_VALID)) { | |
3466 | if (!alloc) | |
3467 | return NULL; | |
3468 | ||
3469 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3470 | if (root == NULL) | |
3471 | return NULL; | |
3472 | ||
3473 | *pte = __pa(root) | GCR3_VALID; | |
3474 | } | |
3475 | ||
3476 | root = __va(*pte & PAGE_MASK); | |
3477 | ||
3478 | level -= 1; | |
3479 | } | |
3480 | ||
3481 | return pte; | |
3482 | } | |
3483 | ||
3484 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3485 | unsigned long cr3) | |
3486 | { | |
3487 | u64 *pte; | |
3488 | ||
3489 | if (domain->mode != PAGE_MODE_NONE) | |
3490 | return -EINVAL; | |
3491 | ||
3492 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3493 | if (pte == NULL) | |
3494 | return -ENOMEM; | |
3495 | ||
3496 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3497 | ||
3498 | return __amd_iommu_flush_tlb(domain, pasid); | |
3499 | } | |
3500 | ||
3501 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3502 | { | |
3503 | u64 *pte; | |
3504 | ||
3505 | if (domain->mode != PAGE_MODE_NONE) | |
3506 | return -EINVAL; | |
3507 | ||
3508 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3509 | if (pte == NULL) | |
3510 | return 0; | |
3511 | ||
3512 | *pte = 0; | |
3513 | ||
3514 | return __amd_iommu_flush_tlb(domain, pasid); | |
3515 | } | |
3516 | ||
3517 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3518 | unsigned long cr3) | |
3519 | { | |
3f4b87b9 | 3520 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3521 | unsigned long flags; |
3522 | int ret; | |
3523 | ||
3524 | spin_lock_irqsave(&domain->lock, flags); | |
3525 | ret = __set_gcr3(domain, pasid, cr3); | |
3526 | spin_unlock_irqrestore(&domain->lock, flags); | |
3527 | ||
3528 | return ret; | |
3529 | } | |
3530 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3531 | ||
3532 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3533 | { | |
3f4b87b9 | 3534 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3535 | unsigned long flags; |
3536 | int ret; | |
3537 | ||
3538 | spin_lock_irqsave(&domain->lock, flags); | |
3539 | ret = __clear_gcr3(domain, pasid); | |
3540 | spin_unlock_irqrestore(&domain->lock, flags); | |
3541 | ||
3542 | return ret; | |
3543 | } | |
3544 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3545 | |
3546 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3547 | int status, int tag) | |
3548 | { | |
3549 | struct iommu_dev_data *dev_data; | |
3550 | struct amd_iommu *iommu; | |
3551 | struct iommu_cmd cmd; | |
3552 | ||
3553 | dev_data = get_dev_data(&pdev->dev); | |
3554 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3555 | ||
3556 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3557 | tag, dev_data->pri_tlp); | |
3558 | ||
3559 | return iommu_queue_command(iommu, &cmd); | |
3560 | } | |
3561 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3562 | |
3563 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3564 | { | |
3f4b87b9 | 3565 | struct protection_domain *pdomain; |
f3572db8 | 3566 | |
3f4b87b9 JR |
3567 | pdomain = get_domain(&pdev->dev); |
3568 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3569 | return NULL; |
3570 | ||
3571 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3572 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3573 | return NULL; |
3574 | ||
3f4b87b9 | 3575 | return &pdomain->domain; |
f3572db8 JR |
3576 | } |
3577 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3578 | |
3579 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3580 | { | |
3581 | struct iommu_dev_data *dev_data; | |
3582 | ||
3583 | if (!amd_iommu_v2_supported()) | |
3584 | return; | |
3585 | ||
3586 | dev_data = get_dev_data(&pdev->dev); | |
3587 | dev_data->errata |= (1 << erratum); | |
3588 | } | |
3589 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3590 | |
3591 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3592 | struct amd_iommu_device_info *info) | |
3593 | { | |
3594 | int max_pasids; | |
3595 | int pos; | |
3596 | ||
3597 | if (pdev == NULL || info == NULL) | |
3598 | return -EINVAL; | |
3599 | ||
3600 | if (!amd_iommu_v2_supported()) | |
3601 | return -EINVAL; | |
3602 | ||
3603 | memset(info, 0, sizeof(*info)); | |
3604 | ||
3605 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3606 | if (pos) | |
3607 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3608 | ||
3609 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3610 | if (pos) | |
3611 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3612 | ||
3613 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3614 | if (pos) { | |
3615 | int features; | |
3616 | ||
3617 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3618 | max_pasids = min(max_pasids, (1 << 20)); | |
3619 | ||
3620 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3621 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3622 | ||
3623 | features = pci_pasid_features(pdev); | |
3624 | if (features & PCI_PASID_CAP_EXEC) | |
3625 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3626 | if (features & PCI_PASID_CAP_PRIV) | |
3627 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3628 | } | |
3629 | ||
3630 | return 0; | |
3631 | } | |
3632 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3633 | |
3634 | #ifdef CONFIG_IRQ_REMAP | |
3635 | ||
3636 | /***************************************************************************** | |
3637 | * | |
3638 | * Interrupt Remapping Implementation | |
3639 | * | |
3640 | *****************************************************************************/ | |
3641 | ||
7c71d306 JL |
3642 | static struct irq_chip amd_ir_chip; |
3643 | ||
2b324506 JR |
3644 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3645 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3646 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3647 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3648 | ||
3649 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3650 | { | |
3651 | u64 dte; | |
3652 | ||
3653 | dte = amd_iommu_dev_table[devid].data[2]; | |
3654 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3655 | dte |= virt_to_phys(table->table); | |
3656 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3657 | dte |= DTE_IRQ_TABLE_LEN; | |
3658 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3659 | ||
3660 | amd_iommu_dev_table[devid].data[2] = dte; | |
3661 | } | |
3662 | ||
2b324506 JR |
3663 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) |
3664 | { | |
3665 | struct irq_remap_table *table = NULL; | |
3666 | struct amd_iommu *iommu; | |
3667 | unsigned long flags; | |
3668 | u16 alias; | |
3669 | ||
3670 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3671 | ||
3672 | iommu = amd_iommu_rlookup_table[devid]; | |
3673 | if (!iommu) | |
3674 | goto out_unlock; | |
3675 | ||
3676 | table = irq_lookup_table[devid]; | |
3677 | if (table) | |
09284b9c | 3678 | goto out_unlock; |
2b324506 JR |
3679 | |
3680 | alias = amd_iommu_alias_table[devid]; | |
3681 | table = irq_lookup_table[alias]; | |
3682 | if (table) { | |
3683 | irq_lookup_table[devid] = table; | |
3684 | set_dte_irq_entry(devid, table); | |
3685 | iommu_flush_dte(iommu, devid); | |
3686 | goto out; | |
3687 | } | |
3688 | ||
3689 | /* Nothing there yet, allocate new irq remapping table */ | |
3690 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3691 | if (!table) | |
09284b9c | 3692 | goto out_unlock; |
2b324506 | 3693 | |
197887f0 JR |
3694 | /* Initialize table spin-lock */ |
3695 | spin_lock_init(&table->lock); | |
3696 | ||
2b324506 JR |
3697 | if (ioapic) |
3698 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3699 | table->min_index = 32; | |
3700 | ||
3701 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3702 | if (!table->table) { | |
3703 | kfree(table); | |
821f0f68 | 3704 | table = NULL; |
09284b9c | 3705 | goto out_unlock; |
2b324506 JR |
3706 | } |
3707 | ||
77bdab46 SS |
3708 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3709 | memset(table->table, 0, | |
3710 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3711 | else | |
3712 | memset(table->table, 0, | |
3713 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
2b324506 JR |
3714 | |
3715 | if (ioapic) { | |
3716 | int i; | |
3717 | ||
3718 | for (i = 0; i < 32; ++i) | |
77bdab46 | 3719 | iommu->irte_ops->set_allocated(table, i); |
2b324506 JR |
3720 | } |
3721 | ||
3722 | irq_lookup_table[devid] = table; | |
3723 | set_dte_irq_entry(devid, table); | |
3724 | iommu_flush_dte(iommu, devid); | |
3725 | if (devid != alias) { | |
3726 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3727 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3728 | iommu_flush_dte(iommu, alias); |
3729 | } | |
3730 | ||
3731 | out: | |
3732 | iommu_completion_wait(iommu); | |
3733 | ||
3734 | out_unlock: | |
3735 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3736 | ||
3737 | return table; | |
3738 | } | |
3739 | ||
3c3d4f90 | 3740 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3741 | { |
3742 | struct irq_remap_table *table; | |
3743 | unsigned long flags; | |
3744 | int index, c; | |
77bdab46 SS |
3745 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3746 | ||
3747 | if (!iommu) | |
3748 | return -ENODEV; | |
2b324506 JR |
3749 | |
3750 | table = get_irq_table(devid, false); | |
3751 | if (!table) | |
3752 | return -ENODEV; | |
3753 | ||
3754 | spin_lock_irqsave(&table->lock, flags); | |
3755 | ||
3756 | /* Scan table for free entries */ | |
3757 | for (c = 0, index = table->min_index; | |
3758 | index < MAX_IRQS_PER_TABLE; | |
3759 | ++index) { | |
77bdab46 | 3760 | if (!iommu->irte_ops->is_allocated(table, index)) |
2b324506 JR |
3761 | c += 1; |
3762 | else | |
3763 | c = 0; | |
3764 | ||
3765 | if (c == count) { | |
2b324506 | 3766 | for (; c != 0; --c) |
77bdab46 | 3767 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3768 | |
3769 | index -= count - 1; | |
2b324506 JR |
3770 | goto out; |
3771 | } | |
3772 | } | |
3773 | ||
3774 | index = -ENOSPC; | |
3775 | ||
3776 | out: | |
3777 | spin_unlock_irqrestore(&table->lock, flags); | |
3778 | ||
3779 | return index; | |
3780 | } | |
3781 | ||
b9fc6b56 SS |
3782 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3783 | struct amd_ir_data *data) | |
2b324506 JR |
3784 | { |
3785 | struct irq_remap_table *table; | |
3786 | struct amd_iommu *iommu; | |
3787 | unsigned long flags; | |
880ac60e | 3788 | struct irte_ga *entry; |
2b324506 JR |
3789 | |
3790 | iommu = amd_iommu_rlookup_table[devid]; | |
3791 | if (iommu == NULL) | |
3792 | return -EINVAL; | |
3793 | ||
3794 | table = get_irq_table(devid, false); | |
3795 | if (!table) | |
3796 | return -ENOMEM; | |
3797 | ||
3798 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e SS |
3799 | |
3800 | entry = (struct irte_ga *)table->table; | |
3801 | entry = &entry[index]; | |
3802 | entry->lo.fields_remap.valid = 0; | |
3803 | entry->hi.val = irte->hi.val; | |
3804 | entry->lo.val = irte->lo.val; | |
3805 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3806 | if (data) |
3807 | data->ref = entry; | |
880ac60e SS |
3808 | |
3809 | spin_unlock_irqrestore(&table->lock, flags); | |
3810 | ||
3811 | iommu_flush_irt(iommu, devid); | |
3812 | iommu_completion_wait(iommu); | |
3813 | ||
3814 | return 0; | |
3815 | } | |
3816 | ||
3817 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3818 | { |
3819 | struct irq_remap_table *table; | |
3820 | struct amd_iommu *iommu; | |
3821 | unsigned long flags; | |
3822 | ||
3823 | iommu = amd_iommu_rlookup_table[devid]; | |
3824 | if (iommu == NULL) | |
3825 | return -EINVAL; | |
3826 | ||
3827 | table = get_irq_table(devid, false); | |
3828 | if (!table) | |
3829 | return -ENOMEM; | |
3830 | ||
3831 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e | 3832 | table->table[index] = irte->val; |
2b324506 JR |
3833 | spin_unlock_irqrestore(&table->lock, flags); |
3834 | ||
3835 | iommu_flush_irt(iommu, devid); | |
3836 | iommu_completion_wait(iommu); | |
3837 | ||
3838 | return 0; | |
3839 | } | |
3840 | ||
3841 | static void free_irte(u16 devid, int index) | |
3842 | { | |
3843 | struct irq_remap_table *table; | |
3844 | struct amd_iommu *iommu; | |
3845 | unsigned long flags; | |
3846 | ||
3847 | iommu = amd_iommu_rlookup_table[devid]; | |
3848 | if (iommu == NULL) | |
3849 | return; | |
3850 | ||
3851 | table = get_irq_table(devid, false); | |
3852 | if (!table) | |
3853 | return; | |
3854 | ||
3855 | spin_lock_irqsave(&table->lock, flags); | |
77bdab46 | 3856 | iommu->irte_ops->clear_allocated(table, index); |
2b324506 JR |
3857 | spin_unlock_irqrestore(&table->lock, flags); |
3858 | ||
3859 | iommu_flush_irt(iommu, devid); | |
3860 | iommu_completion_wait(iommu); | |
3861 | } | |
3862 | ||
880ac60e SS |
3863 | static void irte_prepare(void *entry, |
3864 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3865 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3866 | { |
3867 | union irte *irte = (union irte *) entry; | |
3868 | ||
3869 | irte->val = 0; | |
3870 | irte->fields.vector = vector; | |
3871 | irte->fields.int_type = delivery_mode; | |
3872 | irte->fields.destination = dest_apicid; | |
3873 | irte->fields.dm = dest_mode; | |
3874 | irte->fields.valid = 1; | |
3875 | } | |
3876 | ||
3877 | static void irte_ga_prepare(void *entry, | |
3878 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3879 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3880 | { |
3881 | struct irte_ga *irte = (struct irte_ga *) entry; | |
d98de49a | 3882 | struct iommu_dev_data *dev_data = search_dev_data(devid); |
880ac60e SS |
3883 | |
3884 | irte->lo.val = 0; | |
3885 | irte->hi.val = 0; | |
d98de49a | 3886 | irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0; |
880ac60e SS |
3887 | irte->lo.fields_remap.int_type = delivery_mode; |
3888 | irte->lo.fields_remap.dm = dest_mode; | |
3889 | irte->hi.fields.vector = vector; | |
3890 | irte->lo.fields_remap.destination = dest_apicid; | |
3891 | irte->lo.fields_remap.valid = 1; | |
3892 | } | |
3893 | ||
3894 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3895 | { | |
3896 | union irte *irte = (union irte *) entry; | |
3897 | ||
3898 | irte->fields.valid = 1; | |
3899 | modify_irte(devid, index, irte); | |
3900 | } | |
3901 | ||
3902 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3903 | { | |
3904 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3905 | ||
3906 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3907 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3908 | } |
3909 | ||
3910 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3911 | { | |
3912 | union irte *irte = (union irte *) entry; | |
3913 | ||
3914 | irte->fields.valid = 0; | |
3915 | modify_irte(devid, index, irte); | |
3916 | } | |
3917 | ||
3918 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3919 | { | |
3920 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3921 | ||
3922 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3923 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3924 | } |
3925 | ||
3926 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3927 | u8 vector, u32 dest_apicid) | |
3928 | { | |
3929 | union irte *irte = (union irte *) entry; | |
3930 | ||
3931 | irte->fields.vector = vector; | |
3932 | irte->fields.destination = dest_apicid; | |
3933 | modify_irte(devid, index, irte); | |
3934 | } | |
3935 | ||
3936 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3937 | u8 vector, u32 dest_apicid) | |
3938 | { | |
3939 | struct irte_ga *irte = (struct irte_ga *) entry; | |
d98de49a | 3940 | struct iommu_dev_data *dev_data = search_dev_data(devid); |
880ac60e | 3941 | |
d98de49a SS |
3942 | if (!dev_data || !dev_data->use_vapic) { |
3943 | irte->hi.fields.vector = vector; | |
3944 | irte->lo.fields_remap.destination = dest_apicid; | |
3945 | irte->lo.fields_remap.guest_mode = 0; | |
3946 | modify_irte_ga(devid, index, irte, NULL); | |
3947 | } | |
880ac60e SS |
3948 | } |
3949 | ||
77bdab46 | 3950 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3951 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3952 | { | |
3953 | table->table[index] = IRTE_ALLOCATED; | |
3954 | } | |
3955 | ||
3956 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3957 | { | |
3958 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3959 | struct irte_ga *irte = &ptr[index]; | |
3960 | ||
3961 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3962 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3963 | irte->hi.fields.vector = 0xff; | |
3964 | } | |
3965 | ||
3966 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3967 | { | |
3968 | union irte *ptr = (union irte *)table->table; | |
3969 | union irte *irte = &ptr[index]; | |
3970 | ||
3971 | return irte->val != 0; | |
3972 | } | |
3973 | ||
3974 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3975 | { | |
3976 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3977 | struct irte_ga *irte = &ptr[index]; | |
3978 | ||
3979 | return irte->hi.fields.vector != 0; | |
3980 | } | |
3981 | ||
3982 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3983 | { | |
3984 | table->table[index] = 0; | |
3985 | } | |
3986 | ||
3987 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3988 | { | |
3989 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3990 | struct irte_ga *irte = &ptr[index]; | |
3991 | ||
3992 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3993 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3994 | } | |
3995 | ||
7c71d306 | 3996 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3997 | { |
7c71d306 | 3998 | int devid = -1; |
5527de74 | 3999 | |
7c71d306 JL |
4000 | switch (info->type) { |
4001 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4002 | devid = get_ioapic_devid(info->ioapic_id); | |
4003 | break; | |
4004 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4005 | devid = get_hpet_devid(info->hpet_id); | |
4006 | break; | |
4007 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4008 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4009 | devid = get_device_id(&info->msi_dev->dev); | |
4010 | break; | |
4011 | default: | |
4012 | BUG_ON(1); | |
4013 | break; | |
4014 | } | |
5527de74 | 4015 | |
7c71d306 JL |
4016 | return devid; |
4017 | } | |
5527de74 | 4018 | |
7c71d306 JL |
4019 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4020 | { | |
4021 | struct amd_iommu *iommu; | |
4022 | int devid; | |
5527de74 | 4023 | |
7c71d306 JL |
4024 | if (!info) |
4025 | return NULL; | |
5527de74 | 4026 | |
7c71d306 JL |
4027 | devid = get_devid(info); |
4028 | if (devid >= 0) { | |
4029 | iommu = amd_iommu_rlookup_table[devid]; | |
4030 | if (iommu) | |
4031 | return iommu->ir_domain; | |
4032 | } | |
5527de74 | 4033 | |
7c71d306 | 4034 | return NULL; |
5527de74 JR |
4035 | } |
4036 | ||
7c71d306 | 4037 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4038 | { |
7c71d306 JL |
4039 | struct amd_iommu *iommu; |
4040 | int devid; | |
5527de74 | 4041 | |
7c71d306 JL |
4042 | if (!info) |
4043 | return NULL; | |
5527de74 | 4044 | |
7c71d306 JL |
4045 | switch (info->type) { |
4046 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4047 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4048 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 4049 | if (devid < 0) |
7aba6cb9 WZ |
4050 | return NULL; |
4051 | ||
1fb260bc DC |
4052 | iommu = amd_iommu_rlookup_table[devid]; |
4053 | if (iommu) | |
4054 | return iommu->msi_domain; | |
7c71d306 JL |
4055 | break; |
4056 | default: | |
4057 | break; | |
4058 | } | |
5527de74 | 4059 | |
7c71d306 JL |
4060 | return NULL; |
4061 | } | |
5527de74 | 4062 | |
6b474b82 | 4063 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4064 | .prepare = amd_iommu_prepare, |
4065 | .enable = amd_iommu_enable, | |
4066 | .disable = amd_iommu_disable, | |
4067 | .reenable = amd_iommu_reenable, | |
4068 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4069 | .get_ir_irq_domain = get_ir_irq_domain, |
4070 | .get_irq_domain = get_irq_domain, | |
4071 | }; | |
5527de74 | 4072 | |
7c71d306 JL |
4073 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4074 | struct irq_cfg *irq_cfg, | |
4075 | struct irq_alloc_info *info, | |
4076 | int devid, int index, int sub_handle) | |
4077 | { | |
4078 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4079 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4080 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4081 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4082 | ||
4083 | if (!iommu) | |
4084 | return; | |
5527de74 | 4085 | |
7c71d306 JL |
4086 | data->irq_2_irte.devid = devid; |
4087 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4088 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4089 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 4090 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
4091 | |
4092 | switch (info->type) { | |
4093 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4094 | /* Setup IOAPIC entry */ | |
4095 | entry = info->ioapic_entry; | |
4096 | info->ioapic_entry = NULL; | |
4097 | memset(entry, 0, sizeof(*entry)); | |
4098 | entry->vector = index; | |
4099 | entry->mask = 0; | |
4100 | entry->trigger = info->ioapic_trigger; | |
4101 | entry->polarity = info->ioapic_polarity; | |
4102 | /* Mask level triggered irqs. */ | |
4103 | if (info->ioapic_trigger) | |
4104 | entry->mask = 1; | |
4105 | break; | |
5527de74 | 4106 | |
7c71d306 JL |
4107 | case X86_IRQ_ALLOC_TYPE_HPET: |
4108 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4109 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4110 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4111 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4112 | msg->data = irte_info->index; | |
4113 | break; | |
5527de74 | 4114 | |
7c71d306 JL |
4115 | default: |
4116 | BUG_ON(1); | |
4117 | break; | |
4118 | } | |
5527de74 JR |
4119 | } |
4120 | ||
880ac60e SS |
4121 | struct amd_irte_ops irte_32_ops = { |
4122 | .prepare = irte_prepare, | |
4123 | .activate = irte_activate, | |
4124 | .deactivate = irte_deactivate, | |
4125 | .set_affinity = irte_set_affinity, | |
4126 | .set_allocated = irte_set_allocated, | |
4127 | .is_allocated = irte_is_allocated, | |
4128 | .clear_allocated = irte_clear_allocated, | |
4129 | }; | |
4130 | ||
4131 | struct amd_irte_ops irte_128_ops = { | |
4132 | .prepare = irte_ga_prepare, | |
4133 | .activate = irte_ga_activate, | |
4134 | .deactivate = irte_ga_deactivate, | |
4135 | .set_affinity = irte_ga_set_affinity, | |
4136 | .set_allocated = irte_ga_set_allocated, | |
4137 | .is_allocated = irte_ga_is_allocated, | |
4138 | .clear_allocated = irte_ga_clear_allocated, | |
4139 | }; | |
4140 | ||
7c71d306 JL |
4141 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4142 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4143 | { |
7c71d306 JL |
4144 | struct irq_alloc_info *info = arg; |
4145 | struct irq_data *irq_data; | |
77bdab46 | 4146 | struct amd_ir_data *data = NULL; |
5527de74 | 4147 | struct irq_cfg *cfg; |
7c71d306 JL |
4148 | int i, ret, devid; |
4149 | int index = -1; | |
5527de74 | 4150 | |
7c71d306 JL |
4151 | if (!info) |
4152 | return -EINVAL; | |
4153 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4154 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4155 | return -EINVAL; |
4156 | ||
7c71d306 JL |
4157 | /* |
4158 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4159 | * to support multiple MSI interrupts. | |
4160 | */ | |
4161 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4162 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4163 | |
7c71d306 JL |
4164 | devid = get_devid(info); |
4165 | if (devid < 0) | |
4166 | return -EINVAL; | |
5527de74 | 4167 | |
7c71d306 JL |
4168 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4169 | if (ret < 0) | |
4170 | return ret; | |
0b4d48cb | 4171 | |
7c71d306 JL |
4172 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4173 | if (get_irq_table(devid, true)) | |
4174 | index = info->ioapic_pin; | |
4175 | else | |
4176 | ret = -ENOMEM; | |
4177 | } else { | |
3c3d4f90 | 4178 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4179 | } |
4180 | if (index < 0) { | |
4181 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 4182 | ret = index; |
7c71d306 JL |
4183 | goto out_free_parent; |
4184 | } | |
0b4d48cb | 4185 | |
7c71d306 JL |
4186 | for (i = 0; i < nr_irqs; i++) { |
4187 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4188 | cfg = irqd_cfg(irq_data); | |
4189 | if (!irq_data || !cfg) { | |
4190 | ret = -EINVAL; | |
4191 | goto out_free_data; | |
4192 | } | |
0b4d48cb | 4193 | |
a130e69f JR |
4194 | ret = -ENOMEM; |
4195 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4196 | if (!data) | |
4197 | goto out_free_data; | |
4198 | ||
77bdab46 SS |
4199 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4200 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4201 | else | |
4202 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4203 | GFP_KERNEL); | |
4204 | if (!data->entry) { | |
4205 | kfree(data); | |
4206 | goto out_free_data; | |
4207 | } | |
4208 | ||
7c71d306 JL |
4209 | irq_data->hwirq = (devid << 16) + i; |
4210 | irq_data->chip_data = data; | |
4211 | irq_data->chip = &amd_ir_chip; | |
4212 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4213 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4214 | } | |
a130e69f | 4215 | |
7c71d306 | 4216 | return 0; |
0b4d48cb | 4217 | |
7c71d306 JL |
4218 | out_free_data: |
4219 | for (i--; i >= 0; i--) { | |
4220 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4221 | if (irq_data) | |
4222 | kfree(irq_data->chip_data); | |
4223 | } | |
4224 | for (i = 0; i < nr_irqs; i++) | |
4225 | free_irte(devid, index + i); | |
4226 | out_free_parent: | |
4227 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4228 | return ret; | |
0b4d48cb JR |
4229 | } |
4230 | ||
7c71d306 JL |
4231 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4232 | unsigned int nr_irqs) | |
0b4d48cb | 4233 | { |
7c71d306 JL |
4234 | struct irq_2_irte *irte_info; |
4235 | struct irq_data *irq_data; | |
4236 | struct amd_ir_data *data; | |
4237 | int i; | |
0b4d48cb | 4238 | |
7c71d306 JL |
4239 | for (i = 0; i < nr_irqs; i++) { |
4240 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4241 | if (irq_data && irq_data->chip_data) { | |
4242 | data = irq_data->chip_data; | |
4243 | irte_info = &data->irq_2_irte; | |
4244 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4245 | kfree(data->entry); |
7c71d306 JL |
4246 | kfree(data); |
4247 | } | |
4248 | } | |
4249 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4250 | } | |
0b4d48cb | 4251 | |
7c71d306 JL |
4252 | static void irq_remapping_activate(struct irq_domain *domain, |
4253 | struct irq_data *irq_data) | |
4254 | { | |
4255 | struct amd_ir_data *data = irq_data->chip_data; | |
4256 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4257 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4258 | |
77bdab46 SS |
4259 | if (iommu) |
4260 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4261 | irte_info->index); | |
0b4d48cb JR |
4262 | } |
4263 | ||
7c71d306 JL |
4264 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4265 | struct irq_data *irq_data) | |
0b4d48cb | 4266 | { |
7c71d306 JL |
4267 | struct amd_ir_data *data = irq_data->chip_data; |
4268 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4269 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4270 | |
77bdab46 SS |
4271 | if (iommu) |
4272 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4273 | irte_info->index); | |
7c71d306 | 4274 | } |
0b4d48cb | 4275 | |
7c71d306 JL |
4276 | static struct irq_domain_ops amd_ir_domain_ops = { |
4277 | .alloc = irq_remapping_alloc, | |
4278 | .free = irq_remapping_free, | |
4279 | .activate = irq_remapping_activate, | |
4280 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4281 | }; |
0b4d48cb | 4282 | |
b9fc6b56 SS |
4283 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4284 | { | |
4285 | struct amd_iommu *iommu; | |
4286 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4287 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4288 | struct amd_ir_data *ir_data = data->chip_data; | |
4289 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4290 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
d98de49a SS |
4291 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
4292 | ||
4293 | /* Note: | |
4294 | * This device has never been set up for guest mode. | |
4295 | * we should not modify the IRTE | |
4296 | */ | |
4297 | if (!dev_data || !dev_data->use_vapic) | |
4298 | return 0; | |
b9fc6b56 SS |
4299 | |
4300 | pi_data->ir_data = ir_data; | |
4301 | ||
4302 | /* Note: | |
4303 | * SVM tries to set up for VAPIC mode, but we are in | |
4304 | * legacy mode. So, we force legacy mode instead. | |
4305 | */ | |
4306 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
4307 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", | |
4308 | __func__); | |
4309 | pi_data->is_guest_mode = false; | |
4310 | } | |
4311 | ||
4312 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4313 | if (iommu == NULL) | |
4314 | return -EINVAL; | |
4315 | ||
4316 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4317 | if (pi_data->is_guest_mode) { | |
4318 | /* Setting */ | |
4319 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4320 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
4321 | irte->lo.fields_vapic.guest_mode = 1; | |
4322 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4323 | ||
4324 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4325 | } else { | |
4326 | /* Un-Setting */ | |
4327 | struct irq_cfg *cfg = irqd_cfg(data); | |
4328 | ||
4329 | irte->hi.val = 0; | |
4330 | irte->lo.val = 0; | |
4331 | irte->hi.fields.vector = cfg->vector; | |
4332 | irte->lo.fields_remap.guest_mode = 0; | |
4333 | irte->lo.fields_remap.destination = cfg->dest_apicid; | |
4334 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; | |
4335 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4336 | ||
4337 | /* | |
4338 | * This communicates the ga_tag back to the caller | |
4339 | * so that it can do all the necessary clean up. | |
4340 | */ | |
4341 | ir_data->cached_ga_tag = 0; | |
4342 | } | |
4343 | ||
4344 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4345 | } | |
4346 | ||
7c71d306 JL |
4347 | static int amd_ir_set_affinity(struct irq_data *data, |
4348 | const struct cpumask *mask, bool force) | |
4349 | { | |
4350 | struct amd_ir_data *ir_data = data->chip_data; | |
4351 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4352 | struct irq_cfg *cfg = irqd_cfg(data); | |
4353 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4354 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4355 | int ret; |
0b4d48cb | 4356 | |
77bdab46 SS |
4357 | if (!iommu) |
4358 | return -ENODEV; | |
4359 | ||
7c71d306 JL |
4360 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4361 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4362 | return ret; | |
0b4d48cb | 4363 | |
7c71d306 JL |
4364 | /* |
4365 | * Atomically updates the IRTE with the new destination, vector | |
4366 | * and flushes the interrupt entry cache. | |
4367 | */ | |
77bdab46 SS |
4368 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, |
4369 | irte_info->index, cfg->vector, cfg->dest_apicid); | |
0b4d48cb | 4370 | |
7c71d306 JL |
4371 | /* |
4372 | * After this point, all the interrupts will start arriving | |
4373 | * at the new destination. So, time to cleanup the previous | |
4374 | * vector allocation. | |
4375 | */ | |
c6c2002b | 4376 | send_cleanup_vector(cfg); |
7c71d306 JL |
4377 | |
4378 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4379 | } |
4380 | ||
7c71d306 | 4381 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4382 | { |
7c71d306 | 4383 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4384 | |
7c71d306 JL |
4385 | *msg = ir_data->msi_entry; |
4386 | } | |
d976195c | 4387 | |
7c71d306 JL |
4388 | static struct irq_chip amd_ir_chip = { |
4389 | .irq_ack = ir_ack_apic_edge, | |
4390 | .irq_set_affinity = amd_ir_set_affinity, | |
b9fc6b56 | 4391 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, |
7c71d306 JL |
4392 | .irq_compose_msi_msg = ir_compose_msi_msg, |
4393 | }; | |
d976195c | 4394 | |
7c71d306 JL |
4395 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4396 | { | |
4397 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4398 | if (!iommu->ir_domain) | |
4399 | return -ENOMEM; | |
d976195c | 4400 | |
7c71d306 JL |
4401 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4402 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4403 | |
4404 | return 0; | |
4405 | } | |
8dbea3fd SS |
4406 | |
4407 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4408 | { | |
4409 | unsigned long flags; | |
4410 | struct amd_iommu *iommu; | |
4411 | struct irq_remap_table *irt; | |
4412 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
4413 | int devid = ir_data->irq_2_irte.devid; | |
4414 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4415 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4416 | ||
4417 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4418 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4419 | return 0; | |
4420 | ||
4421 | iommu = amd_iommu_rlookup_table[devid]; | |
4422 | if (!iommu) | |
4423 | return -ENODEV; | |
4424 | ||
4425 | irt = get_irq_table(devid, false); | |
4426 | if (!irt) | |
4427 | return -ENODEV; | |
4428 | ||
4429 | spin_lock_irqsave(&irt->lock, flags); | |
4430 | ||
4431 | if (ref->lo.fields_vapic.guest_mode) { | |
4432 | if (cpu >= 0) | |
4433 | ref->lo.fields_vapic.destination = cpu; | |
4434 | ref->lo.fields_vapic.is_run = is_run; | |
4435 | barrier(); | |
4436 | } | |
4437 | ||
4438 | spin_unlock_irqrestore(&irt->lock, flags); | |
4439 | ||
4440 | iommu_flush_irt(iommu, devid); | |
4441 | iommu_completion_wait(iommu); | |
4442 | return 0; | |
4443 | } | |
4444 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4445 | #endif |