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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
2b324506 JR |
37 | #include <asm/irq_remapping.h> |
38 | #include <asm/io_apic.h> | |
39 | #include <asm/apic.h> | |
40 | #include <asm/hw_irq.h> | |
17f5b569 | 41 | #include <asm/msidef.h> |
b6c02715 | 42 | #include <asm/proto.h> |
46a7fa27 | 43 | #include <asm/iommu.h> |
1d9b16d1 | 44 | #include <asm/gart.h> |
27c2127a | 45 | #include <asm/dma.h> |
403f81d8 JR |
46 | |
47 | #include "amd_iommu_proto.h" | |
48 | #include "amd_iommu_types.h" | |
6b474b82 | 49 | #include "irq_remapping.h" |
b6c02715 JR |
50 | |
51 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
52 | ||
815b33fd | 53 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 54 | |
aa3de9c0 OBC |
55 | /* |
56 | * This bitmap is used to advertise the page sizes our hardware support | |
57 | * to the IOMMU core, which will then use this information to split | |
58 | * physically contiguous memory regions it is mapping into page sizes | |
59 | * that we support. | |
60 | * | |
954e3dd8 | 61 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 62 | */ |
954e3dd8 | 63 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 64 | |
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
8fa5f802 JR |
67 | /* List of all available dev_data structures */ |
68 | static LIST_HEAD(dev_data_list); | |
69 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
70 | ||
6efed63b JR |
71 | LIST_HEAD(ioapic_map); |
72 | LIST_HEAD(hpet_map); | |
73 | ||
0feae533 JR |
74 | /* |
75 | * Domain for untranslated devices - only allocated | |
76 | * if iommu=pt passed on kernel cmd line. | |
77 | */ | |
78 | static struct protection_domain *pt_domain; | |
79 | ||
b22f6434 | 80 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 81 | |
72e1dcc4 | 82 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 83 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 84 | |
ac1534a5 JR |
85 | static struct dma_map_ops amd_iommu_dma_ops; |
86 | ||
50917e26 JR |
87 | /* |
88 | * This struct contains device specific data for the IOMMU | |
89 | */ | |
90 | struct iommu_dev_data { | |
91 | struct list_head list; /* For domain->dev_list */ | |
92 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 93 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
94 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
95 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
96 | u16 devid; /* PCI Device ID */ |
97 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
98 | bool passthrough; /* Default for device is pt_domain */ | |
99 | struct { | |
100 | bool enabled; | |
101 | int qdep; | |
102 | } ats; /* ATS state */ | |
103 | bool pri_tlp; /* PASID TLB required for | |
104 | PPR completions */ | |
105 | u32 errata; /* Bitmap for errata to apply */ | |
106 | }; | |
107 | ||
431b2a20 JR |
108 | /* |
109 | * general struct to manage commands send to an IOMMU | |
110 | */ | |
d6449536 | 111 | struct iommu_cmd { |
b6c02715 JR |
112 | u32 data[4]; |
113 | }; | |
114 | ||
05152a04 JR |
115 | struct kmem_cache *amd_iommu_irq_cache; |
116 | ||
04bfdd84 | 117 | static void update_domain(struct protection_domain *domain); |
aafd8ba0 | 118 | static int alloc_passthrough_domain(void); |
c1eee67b | 119 | |
15898bbc JR |
120 | /**************************************************************************** |
121 | * | |
122 | * Helper functions | |
123 | * | |
124 | ****************************************************************************/ | |
125 | ||
3f4b87b9 JR |
126 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
127 | { | |
128 | return container_of(dom, struct protection_domain, domain); | |
129 | } | |
130 | ||
f62dda66 | 131 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
132 | { |
133 | struct iommu_dev_data *dev_data; | |
134 | unsigned long flags; | |
135 | ||
136 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
137 | if (!dev_data) | |
138 | return NULL; | |
139 | ||
f251e187 JR |
140 | INIT_LIST_HEAD(&dev_data->alias_list); |
141 | ||
f62dda66 | 142 | dev_data->devid = devid; |
8fa5f802 JR |
143 | |
144 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
145 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
146 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
147 | ||
148 | return dev_data; | |
149 | } | |
150 | ||
151 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
152 | { | |
153 | unsigned long flags; | |
154 | ||
155 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
156 | list_del(&dev_data->dev_data_list); | |
157 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
158 | ||
159 | kfree(dev_data); | |
160 | } | |
161 | ||
3b03bb74 JR |
162 | static struct iommu_dev_data *search_dev_data(u16 devid) |
163 | { | |
164 | struct iommu_dev_data *dev_data; | |
165 | unsigned long flags; | |
166 | ||
167 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
168 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
169 | if (dev_data->devid == devid) | |
170 | goto out_unlock; | |
171 | } | |
172 | ||
173 | dev_data = NULL; | |
174 | ||
175 | out_unlock: | |
176 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
177 | ||
178 | return dev_data; | |
179 | } | |
180 | ||
181 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
182 | { | |
183 | struct iommu_dev_data *dev_data; | |
184 | ||
185 | dev_data = search_dev_data(devid); | |
186 | ||
187 | if (dev_data == NULL) | |
188 | dev_data = alloc_dev_data(devid); | |
189 | ||
190 | return dev_data; | |
191 | } | |
192 | ||
15898bbc JR |
193 | static inline u16 get_device_id(struct device *dev) |
194 | { | |
195 | struct pci_dev *pdev = to_pci_dev(dev); | |
196 | ||
6f2729ba | 197 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
198 | } |
199 | ||
657cbb6b JR |
200 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
201 | { | |
202 | return dev->archdata.iommu; | |
203 | } | |
204 | ||
5abcdba4 JR |
205 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
206 | { | |
207 | static const int caps[] = { | |
208 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
209 | PCI_EXT_CAP_ID_PRI, |
210 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
211 | }; |
212 | int i, pos; | |
213 | ||
214 | for (i = 0; i < 3; ++i) { | |
215 | pos = pci_find_ext_capability(pdev, caps[i]); | |
216 | if (pos == 0) | |
217 | return false; | |
218 | } | |
219 | ||
220 | return true; | |
221 | } | |
222 | ||
6a113ddc JR |
223 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
224 | { | |
225 | struct iommu_dev_data *dev_data; | |
226 | ||
227 | dev_data = get_dev_data(&pdev->dev); | |
228 | ||
229 | return dev_data->errata & (1 << erratum) ? true : false; | |
230 | } | |
231 | ||
71c70984 | 232 | /* |
0bb6e243 JR |
233 | * This function actually applies the mapping to the page table of the |
234 | * dma_ops domain. | |
71c70984 | 235 | */ |
0bb6e243 JR |
236 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
237 | struct unity_map_entry *e) | |
71c70984 | 238 | { |
0bb6e243 | 239 | u64 addr; |
71c70984 | 240 | |
0bb6e243 JR |
241 | for (addr = e->address_start; addr < e->address_end; |
242 | addr += PAGE_SIZE) { | |
243 | if (addr < dma_dom->aperture_size) | |
244 | __set_bit(addr >> PAGE_SHIFT, | |
245 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 246 | } |
0bb6e243 | 247 | } |
71c70984 | 248 | |
0bb6e243 JR |
249 | /* |
250 | * Inits the unity mappings required for a specific device | |
251 | */ | |
252 | static void init_unity_mappings_for_device(struct device *dev, | |
253 | struct dma_ops_domain *dma_dom) | |
254 | { | |
255 | struct unity_map_entry *e; | |
256 | u16 devid; | |
71c70984 | 257 | |
0bb6e243 JR |
258 | devid = get_device_id(dev); |
259 | ||
260 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
261 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
262 | continue; | |
263 | alloc_unity_mapping(dma_dom, e); | |
264 | } | |
71c70984 JR |
265 | } |
266 | ||
98fc5a69 JR |
267 | /* |
268 | * This function checks if the driver got a valid device from the caller to | |
269 | * avoid dereferencing invalid pointers. | |
270 | */ | |
271 | static bool check_device(struct device *dev) | |
272 | { | |
273 | u16 devid; | |
274 | ||
275 | if (!dev || !dev->dma_mask) | |
276 | return false; | |
277 | ||
b82a2272 YW |
278 | /* No PCI device */ |
279 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
280 | return false; |
281 | ||
282 | devid = get_device_id(dev); | |
283 | ||
284 | /* Out of our scope? */ | |
285 | if (devid > amd_iommu_last_bdf) | |
286 | return false; | |
287 | ||
288 | if (amd_iommu_rlookup_table[devid] == NULL) | |
289 | return false; | |
290 | ||
291 | return true; | |
292 | } | |
293 | ||
25b11ce2 | 294 | static void init_iommu_group(struct device *dev) |
2851db21 | 295 | { |
0bb6e243 JR |
296 | struct dma_ops_domain *dma_domain; |
297 | struct iommu_domain *domain; | |
2851db21 | 298 | struct iommu_group *group; |
2851db21 | 299 | |
65d5352f | 300 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
301 | if (IS_ERR(group)) |
302 | return; | |
303 | ||
304 | domain = iommu_group_default_domain(group); | |
305 | if (!domain) | |
306 | goto out; | |
307 | ||
308 | dma_domain = to_pdomain(domain)->priv; | |
309 | ||
310 | init_unity_mappings_for_device(dev, dma_domain); | |
311 | out: | |
312 | iommu_group_put(group); | |
eb9c9527 AW |
313 | } |
314 | ||
c1931090 AW |
315 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
316 | { | |
317 | *(u16 *)data = alias; | |
318 | return 0; | |
319 | } | |
320 | ||
321 | static u16 get_alias(struct device *dev) | |
322 | { | |
323 | struct pci_dev *pdev = to_pci_dev(dev); | |
324 | u16 devid, ivrs_alias, pci_alias; | |
325 | ||
326 | devid = get_device_id(dev); | |
327 | ivrs_alias = amd_iommu_alias_table[devid]; | |
328 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
329 | ||
330 | if (ivrs_alias == pci_alias) | |
331 | return ivrs_alias; | |
332 | ||
333 | /* | |
334 | * DMA alias showdown | |
335 | * | |
336 | * The IVRS is fairly reliable in telling us about aliases, but it | |
337 | * can't know about every screwy device. If we don't have an IVRS | |
338 | * reported alias, use the PCI reported alias. In that case we may | |
339 | * still need to initialize the rlookup and dev_table entries if the | |
340 | * alias is to a non-existent device. | |
341 | */ | |
342 | if (ivrs_alias == devid) { | |
343 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
344 | amd_iommu_rlookup_table[pci_alias] = | |
345 | amd_iommu_rlookup_table[devid]; | |
346 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
347 | amd_iommu_dev_table[devid].data, | |
348 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
349 | } | |
350 | ||
351 | return pci_alias; | |
352 | } | |
353 | ||
354 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
355 | "for device %s[%04x:%04x], kernel reported alias " | |
356 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
357 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
358 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
359 | PCI_FUNC(pci_alias)); | |
360 | ||
361 | /* | |
362 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
363 | * bus, then the IVRS table may know about a quirk that we don't. | |
364 | */ | |
365 | if (pci_alias == devid && | |
366 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
367 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
368 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
369 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
370 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
371 | dev_name(dev)); | |
372 | } | |
373 | ||
374 | return ivrs_alias; | |
375 | } | |
376 | ||
eb9c9527 AW |
377 | static int iommu_init_device(struct device *dev) |
378 | { | |
379 | struct pci_dev *pdev = to_pci_dev(dev); | |
380 | struct iommu_dev_data *dev_data; | |
381 | u16 alias; | |
eb9c9527 AW |
382 | |
383 | if (dev->archdata.iommu) | |
384 | return 0; | |
385 | ||
386 | dev_data = find_dev_data(get_device_id(dev)); | |
387 | if (!dev_data) | |
388 | return -ENOMEM; | |
389 | ||
c1931090 AW |
390 | alias = get_alias(dev); |
391 | ||
eb9c9527 AW |
392 | if (alias != dev_data->devid) { |
393 | struct iommu_dev_data *alias_data; | |
394 | ||
395 | alias_data = find_dev_data(alias); | |
396 | if (alias_data == NULL) { | |
397 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
398 | dev_name(dev)); | |
399 | free_dev_data(dev_data); | |
400 | return -ENOTSUPP; | |
401 | } | |
402 | dev_data->alias_data = alias_data; | |
eb9c9527 | 403 | |
f251e187 JR |
404 | /* Add device to the alias_list */ |
405 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 406 | } |
9dcd6130 | 407 | |
5abcdba4 JR |
408 | if (pci_iommuv2_capable(pdev)) { |
409 | struct amd_iommu *iommu; | |
410 | ||
411 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
412 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
413 | } | |
414 | ||
657cbb6b JR |
415 | dev->archdata.iommu = dev_data; |
416 | ||
066f2e98 AW |
417 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
418 | dev); | |
419 | ||
657cbb6b JR |
420 | return 0; |
421 | } | |
422 | ||
26018874 JR |
423 | static void iommu_ignore_device(struct device *dev) |
424 | { | |
425 | u16 devid, alias; | |
426 | ||
427 | devid = get_device_id(dev); | |
428 | alias = amd_iommu_alias_table[devid]; | |
429 | ||
430 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
431 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
432 | ||
433 | amd_iommu_rlookup_table[devid] = NULL; | |
434 | amd_iommu_rlookup_table[alias] = NULL; | |
435 | } | |
436 | ||
657cbb6b JR |
437 | static void iommu_uninit_device(struct device *dev) |
438 | { | |
c1931090 AW |
439 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
440 | ||
441 | if (!dev_data) | |
442 | return; | |
443 | ||
066f2e98 AW |
444 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
445 | dev); | |
446 | ||
9dcd6130 AW |
447 | iommu_group_remove_device(dev); |
448 | ||
c1931090 AW |
449 | /* Unlink from alias, it may change if another device is re-plugged */ |
450 | dev_data->alias_data = NULL; | |
451 | ||
aafd8ba0 JR |
452 | /* Remove dma-ops */ |
453 | dev->archdata.dma_ops = NULL; | |
454 | ||
8fa5f802 | 455 | /* |
c1931090 AW |
456 | * We keep dev_data around for unplugged devices and reuse it when the |
457 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 458 | */ |
657cbb6b | 459 | } |
b7cc9554 | 460 | |
7f26508b JR |
461 | #ifdef CONFIG_AMD_IOMMU_STATS |
462 | ||
463 | /* | |
464 | * Initialization code for statistics collection | |
465 | */ | |
466 | ||
da49f6df | 467 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 468 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 469 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 470 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 471 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 472 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 473 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 474 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 475 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 476 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 477 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 478 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
479 | DECLARE_STATS_COUNTER(complete_ppr); |
480 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
481 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
482 | DECLARE_STATS_COUNTER(pri_requests); | |
483 | ||
7f26508b | 484 | static struct dentry *stats_dir; |
7f26508b JR |
485 | static struct dentry *de_fflush; |
486 | ||
487 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
488 | { | |
489 | if (stats_dir == NULL) | |
490 | return; | |
491 | ||
492 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
493 | &cnt->value); | |
494 | } | |
495 | ||
496 | static void amd_iommu_stats_init(void) | |
497 | { | |
498 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
499 | if (stats_dir == NULL) | |
500 | return; | |
501 | ||
7f26508b | 502 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 503 | &amd_iommu_unmap_flush); |
da49f6df JR |
504 | |
505 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 506 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 507 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 508 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 509 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 510 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 511 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 512 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 513 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 514 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 515 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 516 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
517 | amd_iommu_stats_add(&complete_ppr); |
518 | amd_iommu_stats_add(&invalidate_iotlb); | |
519 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
520 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
521 | } |
522 | ||
523 | #endif | |
524 | ||
a80dc3e0 JR |
525 | /**************************************************************************** |
526 | * | |
527 | * Interrupt handling functions | |
528 | * | |
529 | ****************************************************************************/ | |
530 | ||
e3e59876 JR |
531 | static void dump_dte_entry(u16 devid) |
532 | { | |
533 | int i; | |
534 | ||
ee6c2868 JR |
535 | for (i = 0; i < 4; ++i) |
536 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
537 | amd_iommu_dev_table[devid].data[i]); |
538 | } | |
539 | ||
945b4ac4 JR |
540 | static void dump_command(unsigned long phys_addr) |
541 | { | |
542 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
543 | int i; | |
544 | ||
545 | for (i = 0; i < 4; ++i) | |
546 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
547 | } | |
548 | ||
a345b23b | 549 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 550 | { |
3d06fca8 JR |
551 | int type, devid, domid, flags; |
552 | volatile u32 *event = __evt; | |
553 | int count = 0; | |
554 | u64 address; | |
555 | ||
556 | retry: | |
557 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
558 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
559 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
560 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
561 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
562 | ||
563 | if (type == 0) { | |
564 | /* Did we hit the erratum? */ | |
565 | if (++count == LOOP_TIMEOUT) { | |
566 | pr_err("AMD-Vi: No event written to event log\n"); | |
567 | return; | |
568 | } | |
569 | udelay(1); | |
570 | goto retry; | |
571 | } | |
90008ee4 | 572 | |
4c6f40d4 | 573 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
574 | |
575 | switch (type) { | |
576 | case EVENT_TYPE_ILL_DEV: | |
577 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
578 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 579 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 580 | address, flags); |
e3e59876 | 581 | dump_dte_entry(devid); |
90008ee4 JR |
582 | break; |
583 | case EVENT_TYPE_IO_FAULT: | |
584 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
585 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 586 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
587 | domid, address, flags); |
588 | break; | |
589 | case EVENT_TYPE_DEV_TAB_ERR: | |
590 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
591 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 592 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
593 | address, flags); |
594 | break; | |
595 | case EVENT_TYPE_PAGE_TAB_ERR: | |
596 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
597 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 598 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
599 | domid, address, flags); |
600 | break; | |
601 | case EVENT_TYPE_ILL_CMD: | |
602 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 603 | dump_command(address); |
90008ee4 JR |
604 | break; |
605 | case EVENT_TYPE_CMD_HARD_ERR: | |
606 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
607 | "flags=0x%04x]\n", address, flags); | |
608 | break; | |
609 | case EVENT_TYPE_IOTLB_INV_TO: | |
610 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
611 | "address=0x%016llx]\n", | |
c5081cd7 | 612 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
613 | address); |
614 | break; | |
615 | case EVENT_TYPE_INV_DEV_REQ: | |
616 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
617 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 618 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
619 | address, flags); |
620 | break; | |
621 | default: | |
622 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
623 | } | |
3d06fca8 JR |
624 | |
625 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
626 | } |
627 | ||
628 | static void iommu_poll_events(struct amd_iommu *iommu) | |
629 | { | |
630 | u32 head, tail; | |
90008ee4 JR |
631 | |
632 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
633 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
634 | ||
635 | while (head != tail) { | |
a345b23b | 636 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
637 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
638 | } | |
639 | ||
640 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
641 | } |
642 | ||
eee53537 | 643 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
644 | { |
645 | struct amd_iommu_fault fault; | |
72e1dcc4 | 646 | |
399be2f5 JR |
647 | INC_STATS_COUNTER(pri_requests); |
648 | ||
72e1dcc4 JR |
649 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
650 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
651 | return; | |
652 | } | |
653 | ||
654 | fault.address = raw[1]; | |
655 | fault.pasid = PPR_PASID(raw[0]); | |
656 | fault.device_id = PPR_DEVID(raw[0]); | |
657 | fault.tag = PPR_TAG(raw[0]); | |
658 | fault.flags = PPR_FLAGS(raw[0]); | |
659 | ||
72e1dcc4 JR |
660 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
661 | } | |
662 | ||
663 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
664 | { | |
72e1dcc4 JR |
665 | u32 head, tail; |
666 | ||
667 | if (iommu->ppr_log == NULL) | |
668 | return; | |
669 | ||
72e1dcc4 JR |
670 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
671 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
672 | ||
673 | while (head != tail) { | |
eee53537 JR |
674 | volatile u64 *raw; |
675 | u64 entry[2]; | |
676 | int i; | |
677 | ||
678 | raw = (u64 *)(iommu->ppr_log + head); | |
679 | ||
680 | /* | |
681 | * Hardware bug: Interrupt may arrive before the entry is | |
682 | * written to memory. If this happens we need to wait for the | |
683 | * entry to arrive. | |
684 | */ | |
685 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
686 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
687 | break; | |
688 | udelay(1); | |
689 | } | |
72e1dcc4 | 690 | |
eee53537 JR |
691 | /* Avoid memcpy function-call overhead */ |
692 | entry[0] = raw[0]; | |
693 | entry[1] = raw[1]; | |
72e1dcc4 | 694 | |
eee53537 JR |
695 | /* |
696 | * To detect the hardware bug we need to clear the entry | |
697 | * back to zero. | |
698 | */ | |
699 | raw[0] = raw[1] = 0UL; | |
700 | ||
701 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
702 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
703 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 704 | |
eee53537 JR |
705 | /* Handle PPR entry */ |
706 | iommu_handle_ppr_entry(iommu, entry); | |
707 | ||
eee53537 JR |
708 | /* Refresh ring-buffer information */ |
709 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
710 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
711 | } | |
72e1dcc4 JR |
712 | } |
713 | ||
72fe00f0 | 714 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 715 | { |
3f398bc7 SS |
716 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
717 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 718 | |
3f398bc7 SS |
719 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
720 | /* Enable EVT and PPR interrupts again */ | |
721 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
722 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 723 | |
3f398bc7 SS |
724 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
725 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
726 | iommu_poll_events(iommu); | |
727 | } | |
90008ee4 | 728 | |
3f398bc7 SS |
729 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
730 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
731 | iommu_poll_ppr_log(iommu); | |
732 | } | |
90008ee4 | 733 | |
3f398bc7 SS |
734 | /* |
735 | * Hardware bug: ERBT1312 | |
736 | * When re-enabling interrupt (by writing 1 | |
737 | * to clear the bit), the hardware might also try to set | |
738 | * the interrupt bit in the event status register. | |
739 | * In this scenario, the bit will be set, and disable | |
740 | * subsequent interrupts. | |
741 | * | |
742 | * Workaround: The IOMMU driver should read back the | |
743 | * status register and check if the interrupt bits are cleared. | |
744 | * If not, driver will need to go through the interrupt handler | |
745 | * again and re-clear the bits | |
746 | */ | |
747 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
748 | } | |
90008ee4 | 749 | return IRQ_HANDLED; |
a80dc3e0 JR |
750 | } |
751 | ||
72fe00f0 JR |
752 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
753 | { | |
754 | return IRQ_WAKE_THREAD; | |
755 | } | |
756 | ||
431b2a20 JR |
757 | /**************************************************************************** |
758 | * | |
759 | * IOMMU command queuing functions | |
760 | * | |
761 | ****************************************************************************/ | |
762 | ||
ac0ea6e9 JR |
763 | static int wait_on_sem(volatile u64 *sem) |
764 | { | |
765 | int i = 0; | |
766 | ||
767 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
768 | udelay(1); | |
769 | i += 1; | |
770 | } | |
771 | ||
772 | if (i == LOOP_TIMEOUT) { | |
773 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
774 | return -EIO; | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
780 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
781 | struct iommu_cmd *cmd, | |
782 | u32 tail) | |
a19ae1ec | 783 | { |
a19ae1ec JR |
784 | u8 *target; |
785 | ||
8a7c5ef3 | 786 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
787 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
788 | ||
789 | /* Copy command to buffer */ | |
790 | memcpy(target, cmd, sizeof(*cmd)); | |
791 | ||
792 | /* Tell the IOMMU about it */ | |
a19ae1ec | 793 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 794 | } |
a19ae1ec | 795 | |
815b33fd | 796 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 797 | { |
815b33fd JR |
798 | WARN_ON(address & 0x7ULL); |
799 | ||
ded46737 | 800 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
801 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
802 | cmd->data[1] = upper_32_bits(__pa(address)); | |
803 | cmd->data[2] = 1; | |
ded46737 JR |
804 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
805 | } | |
806 | ||
94fe79e2 JR |
807 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
808 | { | |
809 | memset(cmd, 0, sizeof(*cmd)); | |
810 | cmd->data[0] = devid; | |
811 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
812 | } | |
813 | ||
11b6402c JR |
814 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
815 | size_t size, u16 domid, int pde) | |
816 | { | |
817 | u64 pages; | |
ae0cbbb1 | 818 | bool s; |
11b6402c JR |
819 | |
820 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 821 | s = false; |
11b6402c JR |
822 | |
823 | if (pages > 1) { | |
824 | /* | |
825 | * If we have to flush more than one page, flush all | |
826 | * TLB entries for this domain | |
827 | */ | |
828 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 829 | s = true; |
11b6402c JR |
830 | } |
831 | ||
832 | address &= PAGE_MASK; | |
833 | ||
834 | memset(cmd, 0, sizeof(*cmd)); | |
835 | cmd->data[1] |= domid; | |
836 | cmd->data[2] = lower_32_bits(address); | |
837 | cmd->data[3] = upper_32_bits(address); | |
838 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
839 | if (s) /* size bit - we flush more than one 4kb page */ | |
840 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 841 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
842 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
843 | } | |
844 | ||
cb41ed85 JR |
845 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
846 | u64 address, size_t size) | |
847 | { | |
848 | u64 pages; | |
ae0cbbb1 | 849 | bool s; |
cb41ed85 JR |
850 | |
851 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 852 | s = false; |
cb41ed85 JR |
853 | |
854 | if (pages > 1) { | |
855 | /* | |
856 | * If we have to flush more than one page, flush all | |
857 | * TLB entries for this domain | |
858 | */ | |
859 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 860 | s = true; |
cb41ed85 JR |
861 | } |
862 | ||
863 | address &= PAGE_MASK; | |
864 | ||
865 | memset(cmd, 0, sizeof(*cmd)); | |
866 | cmd->data[0] = devid; | |
867 | cmd->data[0] |= (qdep & 0xff) << 24; | |
868 | cmd->data[1] = devid; | |
869 | cmd->data[2] = lower_32_bits(address); | |
870 | cmd->data[3] = upper_32_bits(address); | |
871 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
872 | if (s) | |
873 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
874 | } | |
875 | ||
22e266c7 JR |
876 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
877 | u64 address, bool size) | |
878 | { | |
879 | memset(cmd, 0, sizeof(*cmd)); | |
880 | ||
881 | address &= ~(0xfffULL); | |
882 | ||
a919a018 | 883 | cmd->data[0] = pasid; |
22e266c7 JR |
884 | cmd->data[1] = domid; |
885 | cmd->data[2] = lower_32_bits(address); | |
886 | cmd->data[3] = upper_32_bits(address); | |
887 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
888 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
889 | if (size) | |
890 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
891 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
892 | } | |
893 | ||
894 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
895 | int qdep, u64 address, bool size) | |
896 | { | |
897 | memset(cmd, 0, sizeof(*cmd)); | |
898 | ||
899 | address &= ~(0xfffULL); | |
900 | ||
901 | cmd->data[0] = devid; | |
e8d2d82d | 902 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
903 | cmd->data[0] |= (qdep & 0xff) << 24; |
904 | cmd->data[1] = devid; | |
e8d2d82d | 905 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
906 | cmd->data[2] = lower_32_bits(address); |
907 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
908 | cmd->data[3] = upper_32_bits(address); | |
909 | if (size) | |
910 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
911 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
912 | } | |
913 | ||
c99afa25 JR |
914 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
915 | int status, int tag, bool gn) | |
916 | { | |
917 | memset(cmd, 0, sizeof(*cmd)); | |
918 | ||
919 | cmd->data[0] = devid; | |
920 | if (gn) { | |
a919a018 | 921 | cmd->data[1] = pasid; |
c99afa25 JR |
922 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
923 | } | |
924 | cmd->data[3] = tag & 0x1ff; | |
925 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
926 | ||
927 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
928 | } | |
929 | ||
58fc7f14 JR |
930 | static void build_inv_all(struct iommu_cmd *cmd) |
931 | { | |
932 | memset(cmd, 0, sizeof(*cmd)); | |
933 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
934 | } |
935 | ||
7ef2798d JR |
936 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
937 | { | |
938 | memset(cmd, 0, sizeof(*cmd)); | |
939 | cmd->data[0] = devid; | |
940 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
941 | } | |
942 | ||
431b2a20 | 943 | /* |
431b2a20 | 944 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 945 | * hardware about the new command. |
431b2a20 | 946 | */ |
f1ca1512 JR |
947 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
948 | struct iommu_cmd *cmd, | |
949 | bool sync) | |
a19ae1ec | 950 | { |
ac0ea6e9 | 951 | u32 left, tail, head, next_tail; |
a19ae1ec | 952 | unsigned long flags; |
a19ae1ec | 953 | |
549c90dc | 954 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
955 | |
956 | again: | |
a19ae1ec | 957 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 958 | |
ac0ea6e9 JR |
959 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
960 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
961 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
962 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 963 | |
ac0ea6e9 JR |
964 | if (left <= 2) { |
965 | struct iommu_cmd sync_cmd; | |
966 | volatile u64 sem = 0; | |
967 | int ret; | |
8d201968 | 968 | |
ac0ea6e9 JR |
969 | build_completion_wait(&sync_cmd, (u64)&sem); |
970 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 971 | |
ac0ea6e9 JR |
972 | spin_unlock_irqrestore(&iommu->lock, flags); |
973 | ||
974 | if ((ret = wait_on_sem(&sem)) != 0) | |
975 | return ret; | |
976 | ||
977 | goto again; | |
8d201968 JR |
978 | } |
979 | ||
ac0ea6e9 JR |
980 | copy_cmd_to_buffer(iommu, cmd, tail); |
981 | ||
982 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 983 | iommu->need_sync = sync; |
ac0ea6e9 | 984 | |
a19ae1ec | 985 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 986 | |
815b33fd | 987 | return 0; |
8d201968 JR |
988 | } |
989 | ||
f1ca1512 JR |
990 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
991 | { | |
992 | return iommu_queue_command_sync(iommu, cmd, true); | |
993 | } | |
994 | ||
8d201968 JR |
995 | /* |
996 | * This function queues a completion wait command into the command | |
997 | * buffer of an IOMMU | |
998 | */ | |
a19ae1ec | 999 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1000 | { |
1001 | struct iommu_cmd cmd; | |
815b33fd | 1002 | volatile u64 sem = 0; |
ac0ea6e9 | 1003 | int ret; |
8d201968 | 1004 | |
09ee17eb | 1005 | if (!iommu->need_sync) |
815b33fd | 1006 | return 0; |
09ee17eb | 1007 | |
815b33fd | 1008 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1009 | |
f1ca1512 | 1010 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1011 | if (ret) |
815b33fd | 1012 | return ret; |
8d201968 | 1013 | |
ac0ea6e9 | 1014 | return wait_on_sem(&sem); |
8d201968 JR |
1015 | } |
1016 | ||
d8c13085 | 1017 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1018 | { |
d8c13085 | 1019 | struct iommu_cmd cmd; |
a19ae1ec | 1020 | |
d8c13085 | 1021 | build_inv_dte(&cmd, devid); |
7e4f88da | 1022 | |
d8c13085 JR |
1023 | return iommu_queue_command(iommu, &cmd); |
1024 | } | |
09ee17eb | 1025 | |
7d0c5cc5 JR |
1026 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1027 | { | |
1028 | u32 devid; | |
09ee17eb | 1029 | |
7d0c5cc5 JR |
1030 | for (devid = 0; devid <= 0xffff; ++devid) |
1031 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1032 | |
7d0c5cc5 JR |
1033 | iommu_completion_wait(iommu); |
1034 | } | |
84df8175 | 1035 | |
7d0c5cc5 JR |
1036 | /* |
1037 | * This function uses heavy locking and may disable irqs for some time. But | |
1038 | * this is no issue because it is only called during resume. | |
1039 | */ | |
1040 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1041 | { | |
1042 | u32 dom_id; | |
a19ae1ec | 1043 | |
7d0c5cc5 JR |
1044 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1045 | struct iommu_cmd cmd; | |
1046 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1047 | dom_id, 1); | |
1048 | iommu_queue_command(iommu, &cmd); | |
1049 | } | |
8eed9833 | 1050 | |
7d0c5cc5 | 1051 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1052 | } |
1053 | ||
58fc7f14 | 1054 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1055 | { |
58fc7f14 | 1056 | struct iommu_cmd cmd; |
0518a3a4 | 1057 | |
58fc7f14 | 1058 | build_inv_all(&cmd); |
0518a3a4 | 1059 | |
58fc7f14 JR |
1060 | iommu_queue_command(iommu, &cmd); |
1061 | iommu_completion_wait(iommu); | |
1062 | } | |
1063 | ||
7ef2798d JR |
1064 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1065 | { | |
1066 | struct iommu_cmd cmd; | |
1067 | ||
1068 | build_inv_irt(&cmd, devid); | |
1069 | ||
1070 | iommu_queue_command(iommu, &cmd); | |
1071 | } | |
1072 | ||
1073 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1074 | { | |
1075 | u32 devid; | |
1076 | ||
1077 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1078 | iommu_flush_irt(iommu, devid); | |
1079 | ||
1080 | iommu_completion_wait(iommu); | |
1081 | } | |
1082 | ||
7d0c5cc5 JR |
1083 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1084 | { | |
58fc7f14 JR |
1085 | if (iommu_feature(iommu, FEATURE_IA)) { |
1086 | iommu_flush_all(iommu); | |
1087 | } else { | |
1088 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1089 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1090 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1091 | } |
1092 | } | |
1093 | ||
431b2a20 | 1094 | /* |
cb41ed85 | 1095 | * Command send function for flushing on-device TLB |
431b2a20 | 1096 | */ |
6c542047 JR |
1097 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1098 | u64 address, size_t size) | |
3fa43655 JR |
1099 | { |
1100 | struct amd_iommu *iommu; | |
b00d3bcf | 1101 | struct iommu_cmd cmd; |
cb41ed85 | 1102 | int qdep; |
3fa43655 | 1103 | |
ea61cddb JR |
1104 | qdep = dev_data->ats.qdep; |
1105 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1106 | |
ea61cddb | 1107 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1108 | |
1109 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1110 | } |
1111 | ||
431b2a20 | 1112 | /* |
431b2a20 | 1113 | * Command send function for invalidating a device table entry |
431b2a20 | 1114 | */ |
6c542047 | 1115 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1116 | { |
3fa43655 | 1117 | struct amd_iommu *iommu; |
ee2fa743 | 1118 | int ret; |
a19ae1ec | 1119 | |
6c542047 | 1120 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1121 | |
f62dda66 | 1122 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1123 | if (ret) |
1124 | return ret; | |
1125 | ||
ea61cddb | 1126 | if (dev_data->ats.enabled) |
6c542047 | 1127 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1128 | |
ee2fa743 | 1129 | return ret; |
a19ae1ec JR |
1130 | } |
1131 | ||
431b2a20 JR |
1132 | /* |
1133 | * TLB invalidation function which is called from the mapping functions. | |
1134 | * It invalidates a single PTE if the range to flush is within a single | |
1135 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1136 | */ | |
17b124bf JR |
1137 | static void __domain_flush_pages(struct protection_domain *domain, |
1138 | u64 address, size_t size, int pde) | |
a19ae1ec | 1139 | { |
cb41ed85 | 1140 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1141 | struct iommu_cmd cmd; |
1142 | int ret = 0, i; | |
a19ae1ec | 1143 | |
11b6402c | 1144 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1145 | |
6de8ad9b JR |
1146 | for (i = 0; i < amd_iommus_present; ++i) { |
1147 | if (!domain->dev_iommu[i]) | |
1148 | continue; | |
1149 | ||
1150 | /* | |
1151 | * Devices of this domain are behind this IOMMU | |
1152 | * We need a TLB flush | |
1153 | */ | |
11b6402c | 1154 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1155 | } |
1156 | ||
cb41ed85 | 1157 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1158 | |
ea61cddb | 1159 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1160 | continue; |
1161 | ||
6c542047 | 1162 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1163 | } |
1164 | ||
11b6402c | 1165 | WARN_ON(ret); |
6de8ad9b JR |
1166 | } |
1167 | ||
17b124bf JR |
1168 | static void domain_flush_pages(struct protection_domain *domain, |
1169 | u64 address, size_t size) | |
6de8ad9b | 1170 | { |
17b124bf | 1171 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1172 | } |
b6c02715 | 1173 | |
1c655773 | 1174 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1175 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1176 | { |
17b124bf | 1177 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1178 | } |
1179 | ||
42a49f96 | 1180 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1181 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1182 | { |
17b124bf | 1183 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1184 | } |
1185 | ||
17b124bf | 1186 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1187 | { |
17b124bf | 1188 | int i; |
18811f55 | 1189 | |
17b124bf JR |
1190 | for (i = 0; i < amd_iommus_present; ++i) { |
1191 | if (!domain->dev_iommu[i]) | |
1192 | continue; | |
bfd1be18 | 1193 | |
17b124bf JR |
1194 | /* |
1195 | * Devices of this domain are behind this IOMMU | |
1196 | * We need to wait for completion of all commands. | |
1197 | */ | |
1198 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1199 | } |
e394d72a JR |
1200 | } |
1201 | ||
b00d3bcf | 1202 | |
09b42804 | 1203 | /* |
b00d3bcf | 1204 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1205 | */ |
17b124bf | 1206 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1207 | { |
b00d3bcf | 1208 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1209 | |
b00d3bcf | 1210 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1211 | device_flush_dte(dev_data); |
a345b23b JR |
1212 | } |
1213 | ||
431b2a20 JR |
1214 | /**************************************************************************** |
1215 | * | |
1216 | * The functions below are used the create the page table mappings for | |
1217 | * unity mapped regions. | |
1218 | * | |
1219 | ****************************************************************************/ | |
1220 | ||
308973d3 JR |
1221 | /* |
1222 | * This function is used to add another level to an IO page table. Adding | |
1223 | * another level increases the size of the address space by 9 bits to a size up | |
1224 | * to 64 bits. | |
1225 | */ | |
1226 | static bool increase_address_space(struct protection_domain *domain, | |
1227 | gfp_t gfp) | |
1228 | { | |
1229 | u64 *pte; | |
1230 | ||
1231 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1232 | /* address space already 64 bit large */ | |
1233 | return false; | |
1234 | ||
1235 | pte = (void *)get_zeroed_page(gfp); | |
1236 | if (!pte) | |
1237 | return false; | |
1238 | ||
1239 | *pte = PM_LEVEL_PDE(domain->mode, | |
1240 | virt_to_phys(domain->pt_root)); | |
1241 | domain->pt_root = pte; | |
1242 | domain->mode += 1; | |
1243 | domain->updated = true; | |
1244 | ||
1245 | return true; | |
1246 | } | |
1247 | ||
1248 | static u64 *alloc_pte(struct protection_domain *domain, | |
1249 | unsigned long address, | |
cbb9d729 | 1250 | unsigned long page_size, |
308973d3 JR |
1251 | u64 **pte_page, |
1252 | gfp_t gfp) | |
1253 | { | |
cbb9d729 | 1254 | int level, end_lvl; |
308973d3 | 1255 | u64 *pte, *page; |
cbb9d729 JR |
1256 | |
1257 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1258 | |
1259 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1260 | increase_address_space(domain, gfp); | |
1261 | ||
cbb9d729 JR |
1262 | level = domain->mode - 1; |
1263 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1264 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1265 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1266 | |
1267 | while (level > end_lvl) { | |
1268 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1269 | page = (u64 *)get_zeroed_page(gfp); | |
1270 | if (!page) | |
1271 | return NULL; | |
1272 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1273 | } | |
1274 | ||
cbb9d729 JR |
1275 | /* No level skipping support yet */ |
1276 | if (PM_PTE_LEVEL(*pte) != level) | |
1277 | return NULL; | |
1278 | ||
308973d3 JR |
1279 | level -= 1; |
1280 | ||
1281 | pte = IOMMU_PTE_PAGE(*pte); | |
1282 | ||
1283 | if (pte_page && level == end_lvl) | |
1284 | *pte_page = pte; | |
1285 | ||
1286 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1287 | } | |
1288 | ||
1289 | return pte; | |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | * This function checks if there is a PTE for a given dma address. If | |
1294 | * there is one, it returns the pointer to it. | |
1295 | */ | |
3039ca1b JR |
1296 | static u64 *fetch_pte(struct protection_domain *domain, |
1297 | unsigned long address, | |
1298 | unsigned long *page_size) | |
308973d3 JR |
1299 | { |
1300 | int level; | |
1301 | u64 *pte; | |
1302 | ||
24cd7723 JR |
1303 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1304 | return NULL; | |
1305 | ||
3039ca1b JR |
1306 | level = domain->mode - 1; |
1307 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1308 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1309 | |
24cd7723 JR |
1310 | while (level > 0) { |
1311 | ||
1312 | /* Not Present */ | |
308973d3 JR |
1313 | if (!IOMMU_PTE_PRESENT(*pte)) |
1314 | return NULL; | |
1315 | ||
24cd7723 | 1316 | /* Large PTE */ |
3039ca1b JR |
1317 | if (PM_PTE_LEVEL(*pte) == 7 || |
1318 | PM_PTE_LEVEL(*pte) == 0) | |
1319 | break; | |
24cd7723 JR |
1320 | |
1321 | /* No level skipping support yet */ | |
1322 | if (PM_PTE_LEVEL(*pte) != level) | |
1323 | return NULL; | |
1324 | ||
308973d3 JR |
1325 | level -= 1; |
1326 | ||
24cd7723 | 1327 | /* Walk to the next level */ |
3039ca1b JR |
1328 | pte = IOMMU_PTE_PAGE(*pte); |
1329 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1330 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1331 | } | |
1332 | ||
1333 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1334 | unsigned long pte_mask; | |
1335 | ||
1336 | /* | |
1337 | * If we have a series of large PTEs, make | |
1338 | * sure to return a pointer to the first one. | |
1339 | */ | |
1340 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1341 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1342 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1343 | } |
1344 | ||
1345 | return pte; | |
1346 | } | |
1347 | ||
431b2a20 JR |
1348 | /* |
1349 | * Generic mapping functions. It maps a physical address into a DMA | |
1350 | * address space. It allocates the page table pages if necessary. | |
1351 | * In the future it can be extended to a generic mapping function | |
1352 | * supporting all features of AMD IOMMU page tables like level skipping | |
1353 | * and full 64 bit address spaces. | |
1354 | */ | |
38e817fe JR |
1355 | static int iommu_map_page(struct protection_domain *dom, |
1356 | unsigned long bus_addr, | |
1357 | unsigned long phys_addr, | |
abdc5eb3 | 1358 | int prot, |
cbb9d729 | 1359 | unsigned long page_size) |
bd0e5211 | 1360 | { |
8bda3092 | 1361 | u64 __pte, *pte; |
cbb9d729 | 1362 | int i, count; |
abdc5eb3 | 1363 | |
d4b03664 JR |
1364 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1365 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1366 | ||
bad1cac2 | 1367 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1368 | return -EINVAL; |
1369 | ||
d4b03664 JR |
1370 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1371 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1372 | |
63eaa75e ML |
1373 | if (!pte) |
1374 | return -ENOMEM; | |
1375 | ||
cbb9d729 JR |
1376 | for (i = 0; i < count; ++i) |
1377 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1378 | return -EBUSY; | |
bd0e5211 | 1379 | |
d4b03664 | 1380 | if (count > 1) { |
cbb9d729 JR |
1381 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1382 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1383 | } else | |
1384 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1385 | |
bd0e5211 JR |
1386 | if (prot & IOMMU_PROT_IR) |
1387 | __pte |= IOMMU_PTE_IR; | |
1388 | if (prot & IOMMU_PROT_IW) | |
1389 | __pte |= IOMMU_PTE_IW; | |
1390 | ||
cbb9d729 JR |
1391 | for (i = 0; i < count; ++i) |
1392 | pte[i] = __pte; | |
bd0e5211 | 1393 | |
04bfdd84 JR |
1394 | update_domain(dom); |
1395 | ||
bd0e5211 JR |
1396 | return 0; |
1397 | } | |
1398 | ||
24cd7723 JR |
1399 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1400 | unsigned long bus_addr, | |
1401 | unsigned long page_size) | |
eb74ff6c | 1402 | { |
71b390e9 JR |
1403 | unsigned long long unmapped; |
1404 | unsigned long unmap_size; | |
24cd7723 JR |
1405 | u64 *pte; |
1406 | ||
1407 | BUG_ON(!is_power_of_2(page_size)); | |
1408 | ||
1409 | unmapped = 0; | |
eb74ff6c | 1410 | |
24cd7723 JR |
1411 | while (unmapped < page_size) { |
1412 | ||
71b390e9 JR |
1413 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1414 | ||
1415 | if (pte) { | |
1416 | int i, count; | |
1417 | ||
1418 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1419 | for (i = 0; i < count; i++) |
1420 | pte[i] = 0ULL; | |
1421 | } | |
1422 | ||
1423 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1424 | unmapped += unmap_size; | |
1425 | } | |
1426 | ||
60d0ca3c | 1427 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1428 | |
24cd7723 | 1429 | return unmapped; |
eb74ff6c | 1430 | } |
eb74ff6c | 1431 | |
431b2a20 JR |
1432 | /**************************************************************************** |
1433 | * | |
1434 | * The next functions belong to the address allocator for the dma_ops | |
1435 | * interface functions. They work like the allocators in the other IOMMU | |
1436 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1437 | * the aperture. Maybe it could be enhanced in the future to a more | |
1438 | * efficient allocator. | |
1439 | * | |
1440 | ****************************************************************************/ | |
d3086444 | 1441 | |
431b2a20 | 1442 | /* |
384de729 | 1443 | * The address allocator core functions. |
431b2a20 JR |
1444 | * |
1445 | * called with domain->lock held | |
1446 | */ | |
384de729 | 1447 | |
171e7b37 JR |
1448 | /* |
1449 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1450 | * ranges. | |
1451 | */ | |
1452 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1453 | unsigned long start_page, | |
1454 | unsigned int pages) | |
1455 | { | |
1456 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1457 | ||
1458 | if (start_page + pages > last_page) | |
1459 | pages = last_page - start_page; | |
1460 | ||
1461 | for (i = start_page; i < start_page + pages; ++i) { | |
1462 | int index = i / APERTURE_RANGE_PAGES; | |
1463 | int page = i % APERTURE_RANGE_PAGES; | |
1464 | __set_bit(page, dom->aperture[index]->bitmap); | |
1465 | } | |
1466 | } | |
1467 | ||
9cabe89b JR |
1468 | /* |
1469 | * This function is used to add a new aperture range to an existing | |
1470 | * aperture in case of dma_ops domain allocation or address allocation | |
1471 | * failure. | |
1472 | */ | |
576175c2 | 1473 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1474 | bool populate, gfp_t gfp) |
1475 | { | |
1476 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1477 | struct amd_iommu *iommu; |
5d7c94c3 | 1478 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1479 | |
f5e9705c JR |
1480 | #ifdef CONFIG_IOMMU_STRESS |
1481 | populate = false; | |
1482 | #endif | |
1483 | ||
9cabe89b JR |
1484 | if (index >= APERTURE_MAX_RANGES) |
1485 | return -ENOMEM; | |
1486 | ||
1487 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1488 | if (!dma_dom->aperture[index]) | |
1489 | return -ENOMEM; | |
1490 | ||
1491 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1492 | if (!dma_dom->aperture[index]->bitmap) | |
1493 | goto out_free; | |
1494 | ||
1495 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1496 | ||
1497 | if (populate) { | |
1498 | unsigned long address = dma_dom->aperture_size; | |
1499 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1500 | u64 *pte, *pte_page; | |
1501 | ||
1502 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1503 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1504 | &pte_page, gfp); |
1505 | if (!pte) | |
1506 | goto out_free; | |
1507 | ||
1508 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1509 | ||
1510 | address += APERTURE_RANGE_SIZE / 64; | |
1511 | } | |
1512 | } | |
1513 | ||
17f5b569 | 1514 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1515 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1516 | ||
17f5b569 JR |
1517 | /* Reserve address range used for MSI messages */ |
1518 | if (old_size < MSI_ADDR_BASE_LO && | |
1519 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1520 | unsigned long spage; | |
1521 | int pages; | |
1522 | ||
1523 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1524 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1525 | ||
1526 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1527 | } | |
1528 | ||
b595076a | 1529 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1530 | for_each_iommu(iommu) { |
1531 | if (iommu->exclusion_start && | |
1532 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1533 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1534 | unsigned long startpage; | |
1535 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1536 | iommu->exclusion_length, | |
1537 | PAGE_SIZE); | |
1538 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1539 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1540 | } | |
00cd122a JR |
1541 | } |
1542 | ||
1543 | /* | |
1544 | * Check for areas already mapped as present in the new aperture | |
1545 | * range and mark those pages as reserved in the allocator. Such | |
1546 | * mappings may already exist as a result of requested unity | |
1547 | * mappings for devices. | |
1548 | */ | |
1549 | for (i = dma_dom->aperture[index]->offset; | |
1550 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1551 | i += pte_pgsize) { |
3039ca1b | 1552 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1553 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1554 | continue; | |
1555 | ||
5d7c94c3 JR |
1556 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1557 | pte_pgsize >> 12); | |
00cd122a JR |
1558 | } |
1559 | ||
04bfdd84 JR |
1560 | update_domain(&dma_dom->domain); |
1561 | ||
9cabe89b JR |
1562 | return 0; |
1563 | ||
1564 | out_free: | |
04bfdd84 JR |
1565 | update_domain(&dma_dom->domain); |
1566 | ||
9cabe89b JR |
1567 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1568 | ||
1569 | kfree(dma_dom->aperture[index]); | |
1570 | dma_dom->aperture[index] = NULL; | |
1571 | ||
1572 | return -ENOMEM; | |
1573 | } | |
1574 | ||
384de729 JR |
1575 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1576 | struct dma_ops_domain *dom, | |
1577 | unsigned int pages, | |
1578 | unsigned long align_mask, | |
1579 | u64 dma_mask, | |
1580 | unsigned long start) | |
1581 | { | |
803b8cb4 | 1582 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1583 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1584 | int i = start >> APERTURE_RANGE_SHIFT; | |
e6aabee0 | 1585 | unsigned long boundary_size, mask; |
384de729 JR |
1586 | unsigned long address = -1; |
1587 | unsigned long limit; | |
1588 | ||
803b8cb4 JR |
1589 | next_bit >>= PAGE_SHIFT; |
1590 | ||
e6aabee0 JR |
1591 | mask = dma_get_seg_boundary(dev); |
1592 | ||
1593 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
1594 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 JR |
1595 | |
1596 | for (;i < max_index; ++i) { | |
1597 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1598 | ||
1599 | if (dom->aperture[i]->offset >= dma_mask) | |
1600 | break; | |
1601 | ||
1602 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1603 | dma_mask >> PAGE_SHIFT); | |
1604 | ||
1605 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1606 | limit, next_bit, pages, 0, | |
1607 | boundary_size, align_mask); | |
1608 | if (address != -1) { | |
1609 | address = dom->aperture[i]->offset + | |
1610 | (address << PAGE_SHIFT); | |
803b8cb4 | 1611 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1612 | break; |
1613 | } | |
1614 | ||
1615 | next_bit = 0; | |
1616 | } | |
1617 | ||
1618 | return address; | |
1619 | } | |
1620 | ||
d3086444 JR |
1621 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1622 | struct dma_ops_domain *dom, | |
6d4f343f | 1623 | unsigned int pages, |
832a90c3 JR |
1624 | unsigned long align_mask, |
1625 | u64 dma_mask) | |
d3086444 | 1626 | { |
d3086444 | 1627 | unsigned long address; |
d3086444 | 1628 | |
fe16f088 JR |
1629 | #ifdef CONFIG_IOMMU_STRESS |
1630 | dom->next_address = 0; | |
1631 | dom->need_flush = true; | |
1632 | #endif | |
d3086444 | 1633 | |
384de729 | 1634 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1635 | dma_mask, dom->next_address); |
d3086444 | 1636 | |
1c655773 | 1637 | if (address == -1) { |
803b8cb4 | 1638 | dom->next_address = 0; |
384de729 JR |
1639 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1640 | dma_mask, 0); | |
1c655773 JR |
1641 | dom->need_flush = true; |
1642 | } | |
d3086444 | 1643 | |
384de729 | 1644 | if (unlikely(address == -1)) |
8fd524b3 | 1645 | address = DMA_ERROR_CODE; |
d3086444 JR |
1646 | |
1647 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1648 | ||
1649 | return address; | |
1650 | } | |
1651 | ||
431b2a20 JR |
1652 | /* |
1653 | * The address free function. | |
1654 | * | |
1655 | * called with domain->lock held | |
1656 | */ | |
d3086444 JR |
1657 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1658 | unsigned long address, | |
1659 | unsigned int pages) | |
1660 | { | |
384de729 JR |
1661 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1662 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1663 | |
384de729 JR |
1664 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1665 | ||
47bccd6b JR |
1666 | #ifdef CONFIG_IOMMU_STRESS |
1667 | if (i < 4) | |
1668 | return; | |
1669 | #endif | |
80be308d | 1670 | |
803b8cb4 | 1671 | if (address >= dom->next_address) |
80be308d | 1672 | dom->need_flush = true; |
384de729 JR |
1673 | |
1674 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1675 | |
a66022c4 | 1676 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1677 | |
d3086444 JR |
1678 | } |
1679 | ||
431b2a20 JR |
1680 | /**************************************************************************** |
1681 | * | |
1682 | * The next functions belong to the domain allocation. A domain is | |
1683 | * allocated for every IOMMU as the default domain. If device isolation | |
1684 | * is enabled, every device get its own domain. The most important thing | |
1685 | * about domains is the page table mapping the DMA address space they | |
1686 | * contain. | |
1687 | * | |
1688 | ****************************************************************************/ | |
1689 | ||
aeb26f55 JR |
1690 | /* |
1691 | * This function adds a protection domain to the global protection domain list | |
1692 | */ | |
1693 | static void add_domain_to_list(struct protection_domain *domain) | |
1694 | { | |
1695 | unsigned long flags; | |
1696 | ||
1697 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1698 | list_add(&domain->list, &amd_iommu_pd_list); | |
1699 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1700 | } | |
1701 | ||
1702 | /* | |
1703 | * This function removes a protection domain to the global | |
1704 | * protection domain list | |
1705 | */ | |
1706 | static void del_domain_from_list(struct protection_domain *domain) | |
1707 | { | |
1708 | unsigned long flags; | |
1709 | ||
1710 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1711 | list_del(&domain->list); | |
1712 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1713 | } | |
1714 | ||
ec487d1a JR |
1715 | static u16 domain_id_alloc(void) |
1716 | { | |
1717 | unsigned long flags; | |
1718 | int id; | |
1719 | ||
1720 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1721 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1722 | BUG_ON(id == 0); | |
1723 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1724 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1725 | else | |
1726 | id = 0; | |
1727 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1728 | ||
1729 | return id; | |
1730 | } | |
1731 | ||
a2acfb75 JR |
1732 | static void domain_id_free(int id) |
1733 | { | |
1734 | unsigned long flags; | |
1735 | ||
1736 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1737 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1738 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1739 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1740 | } | |
a2acfb75 | 1741 | |
5c34c403 JR |
1742 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1743 | static void free_pt_##LVL (unsigned long __pt) \ | |
1744 | { \ | |
1745 | unsigned long p; \ | |
1746 | u64 *pt; \ | |
1747 | int i; \ | |
1748 | \ | |
1749 | pt = (u64 *)__pt; \ | |
1750 | \ | |
1751 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1752 | /* PTE present? */ \ |
5c34c403 JR |
1753 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1754 | continue; \ | |
1755 | \ | |
0b3fff54 JR |
1756 | /* Large PTE? */ \ |
1757 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1758 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1759 | continue; \ | |
1760 | \ | |
5c34c403 JR |
1761 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1762 | FN(p); \ | |
1763 | } \ | |
1764 | free_page((unsigned long)pt); \ | |
1765 | } | |
1766 | ||
1767 | DEFINE_FREE_PT_FN(l2, free_page) | |
1768 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1769 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1770 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1771 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1772 | ||
86db2e5d | 1773 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1774 | { |
5c34c403 | 1775 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1776 | |
5c34c403 JR |
1777 | switch (domain->mode) { |
1778 | case PAGE_MODE_NONE: | |
1779 | break; | |
1780 | case PAGE_MODE_1_LEVEL: | |
1781 | free_page(root); | |
1782 | break; | |
1783 | case PAGE_MODE_2_LEVEL: | |
1784 | free_pt_l2(root); | |
1785 | break; | |
1786 | case PAGE_MODE_3_LEVEL: | |
1787 | free_pt_l3(root); | |
1788 | break; | |
1789 | case PAGE_MODE_4_LEVEL: | |
1790 | free_pt_l4(root); | |
1791 | break; | |
1792 | case PAGE_MODE_5_LEVEL: | |
1793 | free_pt_l5(root); | |
1794 | break; | |
1795 | case PAGE_MODE_6_LEVEL: | |
1796 | free_pt_l6(root); | |
1797 | break; | |
1798 | default: | |
1799 | BUG(); | |
ec487d1a | 1800 | } |
ec487d1a JR |
1801 | } |
1802 | ||
b16137b1 JR |
1803 | static void free_gcr3_tbl_level1(u64 *tbl) |
1804 | { | |
1805 | u64 *ptr; | |
1806 | int i; | |
1807 | ||
1808 | for (i = 0; i < 512; ++i) { | |
1809 | if (!(tbl[i] & GCR3_VALID)) | |
1810 | continue; | |
1811 | ||
1812 | ptr = __va(tbl[i] & PAGE_MASK); | |
1813 | ||
1814 | free_page((unsigned long)ptr); | |
1815 | } | |
1816 | } | |
1817 | ||
1818 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1819 | { | |
1820 | u64 *ptr; | |
1821 | int i; | |
1822 | ||
1823 | for (i = 0; i < 512; ++i) { | |
1824 | if (!(tbl[i] & GCR3_VALID)) | |
1825 | continue; | |
1826 | ||
1827 | ptr = __va(tbl[i] & PAGE_MASK); | |
1828 | ||
1829 | free_gcr3_tbl_level1(ptr); | |
1830 | } | |
1831 | } | |
1832 | ||
52815b75 JR |
1833 | static void free_gcr3_table(struct protection_domain *domain) |
1834 | { | |
b16137b1 JR |
1835 | if (domain->glx == 2) |
1836 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1837 | else if (domain->glx == 1) | |
1838 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1839 | else if (domain->glx != 0) | |
1840 | BUG(); | |
1841 | ||
52815b75 JR |
1842 | free_page((unsigned long)domain->gcr3_tbl); |
1843 | } | |
1844 | ||
431b2a20 JR |
1845 | /* |
1846 | * Free a domain, only used if something went wrong in the | |
1847 | * allocation path and we need to free an already allocated page table | |
1848 | */ | |
ec487d1a JR |
1849 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1850 | { | |
384de729 JR |
1851 | int i; |
1852 | ||
ec487d1a JR |
1853 | if (!dom) |
1854 | return; | |
1855 | ||
aeb26f55 JR |
1856 | del_domain_from_list(&dom->domain); |
1857 | ||
86db2e5d | 1858 | free_pagetable(&dom->domain); |
ec487d1a | 1859 | |
384de729 JR |
1860 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1861 | if (!dom->aperture[i]) | |
1862 | continue; | |
1863 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1864 | kfree(dom->aperture[i]); | |
1865 | } | |
ec487d1a JR |
1866 | |
1867 | kfree(dom); | |
1868 | } | |
1869 | ||
431b2a20 JR |
1870 | /* |
1871 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1872 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1873 | * structures required for the dma_ops interface |
1874 | */ | |
87a64d52 | 1875 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1876 | { |
1877 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1878 | |
1879 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1880 | if (!dma_dom) | |
1881 | return NULL; | |
1882 | ||
1883 | spin_lock_init(&dma_dom->domain.lock); | |
1884 | ||
1885 | dma_dom->domain.id = domain_id_alloc(); | |
1886 | if (dma_dom->domain.id == 0) | |
1887 | goto free_dma_dom; | |
7c392cbe | 1888 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1889 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1890 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1891 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1892 | dma_dom->domain.priv = dma_dom; |
1893 | if (!dma_dom->domain.pt_root) | |
1894 | goto free_dma_dom; | |
ec487d1a | 1895 | |
1c655773 JR |
1896 | dma_dom->need_flush = false; |
1897 | ||
aeb26f55 JR |
1898 | add_domain_to_list(&dma_dom->domain); |
1899 | ||
576175c2 | 1900 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1901 | goto free_dma_dom; |
ec487d1a | 1902 | |
431b2a20 | 1903 | /* |
ec487d1a JR |
1904 | * mark the first page as allocated so we never return 0 as |
1905 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1906 | */ |
384de729 | 1907 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1908 | dma_dom->next_address = 0; |
ec487d1a | 1909 | |
ec487d1a JR |
1910 | |
1911 | return dma_dom; | |
1912 | ||
1913 | free_dma_dom: | |
1914 | dma_ops_domain_free(dma_dom); | |
1915 | ||
1916 | return NULL; | |
1917 | } | |
1918 | ||
5b28df6f JR |
1919 | /* |
1920 | * little helper function to check whether a given protection domain is a | |
1921 | * dma_ops domain | |
1922 | */ | |
1923 | static bool dma_ops_domain(struct protection_domain *domain) | |
1924 | { | |
1925 | return domain->flags & PD_DMA_OPS_MASK; | |
1926 | } | |
1927 | ||
fd7b5535 | 1928 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1929 | { |
132bd68f | 1930 | u64 pte_root = 0; |
ee6c2868 | 1931 | u64 flags = 0; |
863c74eb | 1932 | |
132bd68f JR |
1933 | if (domain->mode != PAGE_MODE_NONE) |
1934 | pte_root = virt_to_phys(domain->pt_root); | |
1935 | ||
38ddf41b JR |
1936 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1937 | << DEV_ENTRY_MODE_SHIFT; | |
1938 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1939 | |
ee6c2868 JR |
1940 | flags = amd_iommu_dev_table[devid].data[1]; |
1941 | ||
fd7b5535 JR |
1942 | if (ats) |
1943 | flags |= DTE_FLAG_IOTLB; | |
1944 | ||
52815b75 JR |
1945 | if (domain->flags & PD_IOMMUV2_MASK) { |
1946 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1947 | u64 glx = domain->glx; | |
1948 | u64 tmp; | |
1949 | ||
1950 | pte_root |= DTE_FLAG_GV; | |
1951 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1952 | ||
1953 | /* First mask out possible old values for GCR3 table */ | |
1954 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1955 | flags &= ~tmp; | |
1956 | ||
1957 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1958 | flags &= ~tmp; | |
1959 | ||
1960 | /* Encode GCR3 table into DTE */ | |
1961 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1962 | pte_root |= tmp; | |
1963 | ||
1964 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1965 | flags |= tmp; | |
1966 | ||
1967 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1968 | flags |= tmp; | |
1969 | } | |
1970 | ||
ee6c2868 JR |
1971 | flags &= ~(0xffffUL); |
1972 | flags |= domain->id; | |
1973 | ||
1974 | amd_iommu_dev_table[devid].data[1] = flags; | |
1975 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1976 | } |
1977 | ||
1978 | static void clear_dte_entry(u16 devid) | |
1979 | { | |
15898bbc JR |
1980 | /* remove entry from the device table seen by the hardware */ |
1981 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1982 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1983 | |
1984 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1985 | } |
1986 | ||
ec9e79ef JR |
1987 | static void do_attach(struct iommu_dev_data *dev_data, |
1988 | struct protection_domain *domain) | |
7f760ddd | 1989 | { |
7f760ddd | 1990 | struct amd_iommu *iommu; |
ec9e79ef | 1991 | bool ats; |
fd7b5535 | 1992 | |
ec9e79ef JR |
1993 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1994 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1995 | |
1996 | /* Update data structures */ | |
1997 | dev_data->domain = domain; | |
1998 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1999 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2000 | |
2001 | /* Do reference counting */ | |
2002 | domain->dev_iommu[iommu->index] += 1; | |
2003 | domain->dev_cnt += 1; | |
2004 | ||
2005 | /* Flush the DTE entry */ | |
6c542047 | 2006 | device_flush_dte(dev_data); |
7f760ddd JR |
2007 | } |
2008 | ||
ec9e79ef | 2009 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2010 | { |
7f760ddd | 2011 | struct amd_iommu *iommu; |
7f760ddd | 2012 | |
ec9e79ef | 2013 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2014 | |
2015 | /* decrease reference counters */ | |
7f760ddd JR |
2016 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2017 | dev_data->domain->dev_cnt -= 1; | |
2018 | ||
2019 | /* Update data structures */ | |
2020 | dev_data->domain = NULL; | |
2021 | list_del(&dev_data->list); | |
f62dda66 | 2022 | clear_dte_entry(dev_data->devid); |
15898bbc | 2023 | |
7f760ddd | 2024 | /* Flush the DTE entry */ |
6c542047 | 2025 | device_flush_dte(dev_data); |
2b681faf JR |
2026 | } |
2027 | ||
2028 | /* | |
2029 | * If a device is not yet associated with a domain, this function does | |
2030 | * assigns it visible for the hardware | |
2031 | */ | |
ec9e79ef | 2032 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2033 | struct protection_domain *domain) |
2b681faf | 2034 | { |
397111ab | 2035 | struct iommu_dev_data *head, *entry; |
84fe6c19 | 2036 | int ret; |
657cbb6b | 2037 | |
2b681faf JR |
2038 | /* lock domain */ |
2039 | spin_lock(&domain->lock); | |
2040 | ||
397111ab | 2041 | head = dev_data; |
15898bbc | 2042 | |
397111ab JR |
2043 | if (head->alias_data != NULL) |
2044 | head = head->alias_data; | |
eba6ac60 | 2045 | |
397111ab | 2046 | /* Now we have the root of the alias group, if any */ |
15898bbc | 2047 | |
397111ab JR |
2048 | ret = -EBUSY; |
2049 | if (head->domain != NULL) | |
2050 | goto out_unlock; | |
15898bbc | 2051 | |
397111ab JR |
2052 | /* Attach alias group root */ |
2053 | do_attach(head, domain); | |
eba6ac60 | 2054 | |
397111ab JR |
2055 | /* Attach other devices in the alias group */ |
2056 | list_for_each_entry(entry, &head->alias_list, alias_list) | |
2057 | do_attach(entry, domain); | |
24100055 | 2058 | |
84fe6c19 JL |
2059 | ret = 0; |
2060 | ||
2061 | out_unlock: | |
2062 | ||
eba6ac60 JR |
2063 | /* ready */ |
2064 | spin_unlock(&domain->lock); | |
15898bbc | 2065 | |
84fe6c19 | 2066 | return ret; |
0feae533 | 2067 | } |
b20ac0d4 | 2068 | |
52815b75 JR |
2069 | |
2070 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2071 | { | |
2072 | pci_disable_ats(pdev); | |
2073 | pci_disable_pri(pdev); | |
2074 | pci_disable_pasid(pdev); | |
2075 | } | |
2076 | ||
6a113ddc JR |
2077 | /* FIXME: Change generic reset-function to do the same */ |
2078 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2079 | { | |
2080 | u16 control; | |
2081 | int pos; | |
2082 | ||
46277b75 | 2083 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2084 | if (!pos) |
2085 | return -EINVAL; | |
2086 | ||
46277b75 JR |
2087 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2088 | control |= PCI_PRI_CTRL_RESET; | |
2089 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2090 | |
2091 | return 0; | |
2092 | } | |
2093 | ||
52815b75 JR |
2094 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2095 | { | |
6a113ddc JR |
2096 | bool reset_enable; |
2097 | int reqs, ret; | |
2098 | ||
2099 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2100 | reqs = 32; | |
2101 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2102 | reqs = 1; | |
2103 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2104 | |
2105 | /* Only allow access to user-accessible pages */ | |
2106 | ret = pci_enable_pasid(pdev, 0); | |
2107 | if (ret) | |
2108 | goto out_err; | |
2109 | ||
2110 | /* First reset the PRI state of the device */ | |
2111 | ret = pci_reset_pri(pdev); | |
2112 | if (ret) | |
2113 | goto out_err; | |
2114 | ||
6a113ddc JR |
2115 | /* Enable PRI */ |
2116 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2117 | if (ret) |
2118 | goto out_err; | |
2119 | ||
6a113ddc JR |
2120 | if (reset_enable) { |
2121 | ret = pri_reset_while_enabled(pdev); | |
2122 | if (ret) | |
2123 | goto out_err; | |
2124 | } | |
2125 | ||
52815b75 JR |
2126 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2127 | if (ret) | |
2128 | goto out_err; | |
2129 | ||
2130 | return 0; | |
2131 | ||
2132 | out_err: | |
2133 | pci_disable_pri(pdev); | |
2134 | pci_disable_pasid(pdev); | |
2135 | ||
2136 | return ret; | |
2137 | } | |
2138 | ||
c99afa25 | 2139 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2140 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2141 | |
98f1ad25 | 2142 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2143 | { |
a3b93121 | 2144 | u16 status; |
c99afa25 JR |
2145 | int pos; |
2146 | ||
46277b75 | 2147 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2148 | if (!pos) |
2149 | return false; | |
2150 | ||
a3b93121 | 2151 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2152 | |
a3b93121 | 2153 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2154 | } |
2155 | ||
407d733e | 2156 | /* |
df805abb | 2157 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2158 | * assigns it visible for the hardware |
2159 | */ | |
15898bbc JR |
2160 | static int attach_device(struct device *dev, |
2161 | struct protection_domain *domain) | |
0feae533 | 2162 | { |
fd7b5535 | 2163 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2164 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2165 | unsigned long flags; |
15898bbc | 2166 | int ret; |
eba6ac60 | 2167 | |
ea61cddb JR |
2168 | dev_data = get_dev_data(dev); |
2169 | ||
52815b75 JR |
2170 | if (domain->flags & PD_IOMMUV2_MASK) { |
2171 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2172 | return -EINVAL; | |
2173 | ||
2174 | if (pdev_iommuv2_enable(pdev) != 0) | |
2175 | return -EINVAL; | |
2176 | ||
2177 | dev_data->ats.enabled = true; | |
2178 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2179 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2180 | } else if (amd_iommu_iotlb_sup && |
2181 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2182 | dev_data->ats.enabled = true; |
2183 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2184 | } | |
fd7b5535 | 2185 | |
eba6ac60 | 2186 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2187 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2188 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2189 | ||
0feae533 JR |
2190 | /* |
2191 | * We might boot into a crash-kernel here. The crashed kernel | |
2192 | * left the caches in the IOMMU dirty. So we have to flush | |
2193 | * here to evict all dirty stuff. | |
2194 | */ | |
17b124bf | 2195 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2196 | |
2197 | return ret; | |
b20ac0d4 JR |
2198 | } |
2199 | ||
355bf553 JR |
2200 | /* |
2201 | * Removes a device from a protection domain (unlocked) | |
2202 | */ | |
ec9e79ef | 2203 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2204 | { |
397111ab | 2205 | struct iommu_dev_data *head, *entry; |
2ca76279 | 2206 | struct protection_domain *domain; |
7c392cbe | 2207 | unsigned long flags; |
c4596114 | 2208 | |
7f760ddd | 2209 | BUG_ON(!dev_data->domain); |
355bf553 | 2210 | |
2ca76279 JR |
2211 | domain = dev_data->domain; |
2212 | ||
2213 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2214 | |
397111ab JR |
2215 | head = dev_data; |
2216 | if (head->alias_data != NULL) | |
2217 | head = head->alias_data; | |
71f77580 | 2218 | |
397111ab JR |
2219 | list_for_each_entry(entry, &head->alias_list, alias_list) |
2220 | do_detach(entry); | |
24100055 | 2221 | |
397111ab | 2222 | do_detach(head); |
7f760ddd | 2223 | |
2ca76279 | 2224 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2225 | |
2226 | /* | |
2227 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2228 | * passthrough domain if it is detached from any other domain. |
2229 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2230 | */ |
5abcdba4 | 2231 | if (dev_data->passthrough && |
d3ad9373 | 2232 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2233 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2234 | } |
2235 | ||
2236 | /* | |
2237 | * Removes a device from a protection domain (with devtable_lock held) | |
2238 | */ | |
15898bbc | 2239 | static void detach_device(struct device *dev) |
355bf553 | 2240 | { |
52815b75 | 2241 | struct protection_domain *domain; |
ea61cddb | 2242 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2243 | unsigned long flags; |
2244 | ||
ec9e79ef | 2245 | dev_data = get_dev_data(dev); |
52815b75 | 2246 | domain = dev_data->domain; |
ec9e79ef | 2247 | |
355bf553 JR |
2248 | /* lock device table */ |
2249 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2250 | __detach_device(dev_data); |
355bf553 | 2251 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2252 | |
52815b75 JR |
2253 | if (domain->flags & PD_IOMMUV2_MASK) |
2254 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2255 | else if (dev_data->ats.enabled) | |
ea61cddb | 2256 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2257 | |
2258 | dev_data->ats.enabled = false; | |
355bf553 | 2259 | } |
e275a2a0 | 2260 | |
aafd8ba0 | 2261 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2262 | { |
5abcdba4 | 2263 | struct iommu_dev_data *dev_data; |
07ee8694 | 2264 | struct iommu_domain *domain; |
e275a2a0 | 2265 | struct amd_iommu *iommu; |
5abcdba4 | 2266 | u16 devid; |
aafd8ba0 | 2267 | int ret; |
e275a2a0 | 2268 | |
aafd8ba0 | 2269 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2270 | return 0; |
e275a2a0 | 2271 | |
aafd8ba0 JR |
2272 | devid = get_device_id(dev); |
2273 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2274 | |
aafd8ba0 | 2275 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2276 | if (ret) { |
2277 | if (ret != -ENOTSUPP) | |
2278 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2279 | dev_name(dev)); | |
657cbb6b | 2280 | |
aafd8ba0 | 2281 | iommu_ignore_device(dev); |
343e9cac | 2282 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2283 | goto out; |
2284 | } | |
2285 | init_iommu_group(dev); | |
2c9195e9 | 2286 | |
07ee8694 | 2287 | dev_data = get_dev_data(dev); |
2c9195e9 | 2288 | |
4d58b8a6 | 2289 | BUG_ON(!dev_data); |
657cbb6b | 2290 | |
4d58b8a6 | 2291 | if (dev_data->iommu_v2) |
07ee8694 | 2292 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2293 | |
07ee8694 JR |
2294 | /* Domains are initialized for this device - have a look what we ended up with */ |
2295 | domain = iommu_get_domain_for_dev(dev); | |
2296 | if (domain->type == IOMMU_DOMAIN_IDENTITY) { | |
2297 | dev_data->passthrough = true; | |
2298 | dev->archdata.dma_ops = &nommu_dma_ops; | |
2299 | } else { | |
2c9195e9 | 2300 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 JR |
2301 | } |
2302 | ||
aafd8ba0 | 2303 | out: |
e275a2a0 JR |
2304 | iommu_completion_wait(iommu); |
2305 | ||
e275a2a0 JR |
2306 | return 0; |
2307 | } | |
2308 | ||
aafd8ba0 | 2309 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2310 | { |
aafd8ba0 JR |
2311 | struct amd_iommu *iommu; |
2312 | u16 devid; | |
2313 | ||
2314 | if (!check_device(dev)) | |
2315 | return; | |
2316 | ||
2317 | devid = get_device_id(dev); | |
2318 | iommu = amd_iommu_rlookup_table[devid]; | |
2319 | ||
2320 | iommu_uninit_device(dev); | |
2321 | iommu_completion_wait(iommu); | |
8638c491 JR |
2322 | } |
2323 | ||
431b2a20 JR |
2324 | /***************************************************************************** |
2325 | * | |
2326 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2327 | * | |
2328 | *****************************************************************************/ | |
2329 | ||
2330 | /* | |
2331 | * In the dma_ops path we only have the struct device. This function | |
2332 | * finds the corresponding IOMMU, the protection domain and the | |
2333 | * requestor id for a given device. | |
2334 | * If the device is not yet associated with a domain this is also done | |
2335 | * in this function. | |
2336 | */ | |
94f6d190 | 2337 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2338 | { |
94f6d190 | 2339 | struct protection_domain *domain; |
063071df | 2340 | struct iommu_domain *io_domain; |
b20ac0d4 | 2341 | |
f99c0f1c | 2342 | if (!check_device(dev)) |
94f6d190 | 2343 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2344 | |
063071df | 2345 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2346 | if (!io_domain) |
2347 | return NULL; | |
b20ac0d4 | 2348 | |
0bb6e243 JR |
2349 | domain = to_pdomain(io_domain); |
2350 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2351 | return ERR_PTR(-EBUSY); |
f91ba190 | 2352 | |
0bb6e243 | 2353 | return domain; |
b20ac0d4 JR |
2354 | } |
2355 | ||
04bfdd84 JR |
2356 | static void update_device_table(struct protection_domain *domain) |
2357 | { | |
492667da | 2358 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2359 | |
ea61cddb JR |
2360 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2361 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2362 | } |
2363 | ||
2364 | static void update_domain(struct protection_domain *domain) | |
2365 | { | |
2366 | if (!domain->updated) | |
2367 | return; | |
2368 | ||
2369 | update_device_table(domain); | |
17b124bf JR |
2370 | |
2371 | domain_flush_devices(domain); | |
2372 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2373 | |
2374 | domain->updated = false; | |
2375 | } | |
2376 | ||
8bda3092 JR |
2377 | /* |
2378 | * This function fetches the PTE for a given address in the aperture | |
2379 | */ | |
2380 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2381 | unsigned long address) | |
2382 | { | |
384de729 | 2383 | struct aperture_range *aperture; |
8bda3092 JR |
2384 | u64 *pte, *pte_page; |
2385 | ||
384de729 JR |
2386 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2387 | if (!aperture) | |
2388 | return NULL; | |
2389 | ||
2390 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2391 | if (!pte) { |
cbb9d729 | 2392 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2393 | GFP_ATOMIC); |
384de729 JR |
2394 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2395 | } else | |
8c8c143c | 2396 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2397 | |
04bfdd84 | 2398 | update_domain(&dom->domain); |
8bda3092 JR |
2399 | |
2400 | return pte; | |
2401 | } | |
2402 | ||
431b2a20 JR |
2403 | /* |
2404 | * This is the generic map function. It maps one 4kb page at paddr to | |
2405 | * the given address in the DMA address space for the domain. | |
2406 | */ | |
680525e0 | 2407 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2408 | unsigned long address, |
2409 | phys_addr_t paddr, | |
2410 | int direction) | |
2411 | { | |
2412 | u64 *pte, __pte; | |
2413 | ||
2414 | WARN_ON(address > dom->aperture_size); | |
2415 | ||
2416 | paddr &= PAGE_MASK; | |
2417 | ||
8bda3092 | 2418 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2419 | if (!pte) |
8fd524b3 | 2420 | return DMA_ERROR_CODE; |
cb76c322 JR |
2421 | |
2422 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2423 | ||
2424 | if (direction == DMA_TO_DEVICE) | |
2425 | __pte |= IOMMU_PTE_IR; | |
2426 | else if (direction == DMA_FROM_DEVICE) | |
2427 | __pte |= IOMMU_PTE_IW; | |
2428 | else if (direction == DMA_BIDIRECTIONAL) | |
2429 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2430 | ||
2431 | WARN_ON(*pte); | |
2432 | ||
2433 | *pte = __pte; | |
2434 | ||
2435 | return (dma_addr_t)address; | |
2436 | } | |
2437 | ||
431b2a20 JR |
2438 | /* |
2439 | * The generic unmapping function for on page in the DMA address space. | |
2440 | */ | |
680525e0 | 2441 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2442 | unsigned long address) |
2443 | { | |
384de729 | 2444 | struct aperture_range *aperture; |
cb76c322 JR |
2445 | u64 *pte; |
2446 | ||
2447 | if (address >= dom->aperture_size) | |
2448 | return; | |
2449 | ||
384de729 JR |
2450 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2451 | if (!aperture) | |
2452 | return; | |
2453 | ||
2454 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2455 | if (!pte) | |
2456 | return; | |
cb76c322 | 2457 | |
8c8c143c | 2458 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2459 | |
2460 | WARN_ON(!*pte); | |
2461 | ||
2462 | *pte = 0ULL; | |
2463 | } | |
2464 | ||
431b2a20 JR |
2465 | /* |
2466 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2467 | * contiguous memory region into DMA address space. It is used by all |
2468 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2469 | * Must be called with the domain lock held. |
2470 | */ | |
cb76c322 | 2471 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2472 | struct dma_ops_domain *dma_dom, |
2473 | phys_addr_t paddr, | |
2474 | size_t size, | |
6d4f343f | 2475 | int dir, |
832a90c3 JR |
2476 | bool align, |
2477 | u64 dma_mask) | |
cb76c322 JR |
2478 | { |
2479 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2480 | dma_addr_t address, start, ret; |
cb76c322 | 2481 | unsigned int pages; |
6d4f343f | 2482 | unsigned long align_mask = 0; |
cb76c322 JR |
2483 | int i; |
2484 | ||
e3c449f5 | 2485 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2486 | paddr &= PAGE_MASK; |
2487 | ||
8ecaf8f1 JR |
2488 | INC_STATS_COUNTER(total_map_requests); |
2489 | ||
c1858976 JR |
2490 | if (pages > 1) |
2491 | INC_STATS_COUNTER(cross_page); | |
2492 | ||
6d4f343f JR |
2493 | if (align) |
2494 | align_mask = (1UL << get_order(size)) - 1; | |
2495 | ||
11b83888 | 2496 | retry: |
832a90c3 JR |
2497 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2498 | dma_mask); | |
8fd524b3 | 2499 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2500 | /* |
2501 | * setting next_address here will let the address | |
2502 | * allocator only scan the new allocated range in the | |
2503 | * first run. This is a small optimization. | |
2504 | */ | |
2505 | dma_dom->next_address = dma_dom->aperture_size; | |
2506 | ||
576175c2 | 2507 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2508 | goto out; |
2509 | ||
2510 | /* | |
af901ca1 | 2511 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2512 | * allocation again |
2513 | */ | |
2514 | goto retry; | |
2515 | } | |
cb76c322 JR |
2516 | |
2517 | start = address; | |
2518 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2519 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2520 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2521 | goto out_unmap; |
2522 | ||
cb76c322 JR |
2523 | paddr += PAGE_SIZE; |
2524 | start += PAGE_SIZE; | |
2525 | } | |
2526 | address += offset; | |
2527 | ||
5774f7c5 JR |
2528 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2529 | ||
afa9fdc2 | 2530 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2531 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2532 | dma_dom->need_flush = false; |
318afd41 | 2533 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2534 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2535 | |
cb76c322 JR |
2536 | out: |
2537 | return address; | |
53812c11 JR |
2538 | |
2539 | out_unmap: | |
2540 | ||
2541 | for (--i; i >= 0; --i) { | |
2542 | start -= PAGE_SIZE; | |
680525e0 | 2543 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2544 | } |
2545 | ||
2546 | dma_ops_free_addresses(dma_dom, address, pages); | |
2547 | ||
8fd524b3 | 2548 | return DMA_ERROR_CODE; |
cb76c322 JR |
2549 | } |
2550 | ||
431b2a20 JR |
2551 | /* |
2552 | * Does the reverse of the __map_single function. Must be called with | |
2553 | * the domain lock held too | |
2554 | */ | |
cd8c82e8 | 2555 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2556 | dma_addr_t dma_addr, |
2557 | size_t size, | |
2558 | int dir) | |
2559 | { | |
04e0463e | 2560 | dma_addr_t flush_addr; |
cb76c322 JR |
2561 | dma_addr_t i, start; |
2562 | unsigned int pages; | |
2563 | ||
8fd524b3 | 2564 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2565 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2566 | return; |
2567 | ||
04e0463e | 2568 | flush_addr = dma_addr; |
e3c449f5 | 2569 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2570 | dma_addr &= PAGE_MASK; |
2571 | start = dma_addr; | |
2572 | ||
2573 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2574 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2575 | start += PAGE_SIZE; |
2576 | } | |
2577 | ||
5774f7c5 JR |
2578 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2579 | ||
cb76c322 | 2580 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2581 | |
80be308d | 2582 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2583 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2584 | dma_dom->need_flush = false; |
2585 | } | |
cb76c322 JR |
2586 | } |
2587 | ||
431b2a20 JR |
2588 | /* |
2589 | * The exported map_single function for dma_ops. | |
2590 | */ | |
51491367 FT |
2591 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2592 | unsigned long offset, size_t size, | |
2593 | enum dma_data_direction dir, | |
2594 | struct dma_attrs *attrs) | |
4da70b9e JR |
2595 | { |
2596 | unsigned long flags; | |
4da70b9e | 2597 | struct protection_domain *domain; |
4da70b9e | 2598 | dma_addr_t addr; |
832a90c3 | 2599 | u64 dma_mask; |
51491367 | 2600 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2601 | |
0f2a86f2 JR |
2602 | INC_STATS_COUNTER(cnt_map_single); |
2603 | ||
94f6d190 JR |
2604 | domain = get_domain(dev); |
2605 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2606 | return (dma_addr_t)paddr; |
94f6d190 JR |
2607 | else if (IS_ERR(domain)) |
2608 | return DMA_ERROR_CODE; | |
4da70b9e | 2609 | |
f99c0f1c JR |
2610 | dma_mask = *dev->dma_mask; |
2611 | ||
4da70b9e | 2612 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2613 | |
cd8c82e8 | 2614 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2615 | dma_mask); |
8fd524b3 | 2616 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2617 | goto out; |
2618 | ||
17b124bf | 2619 | domain_flush_complete(domain); |
4da70b9e JR |
2620 | |
2621 | out: | |
2622 | spin_unlock_irqrestore(&domain->lock, flags); | |
2623 | ||
2624 | return addr; | |
2625 | } | |
2626 | ||
431b2a20 JR |
2627 | /* |
2628 | * The exported unmap_single function for dma_ops. | |
2629 | */ | |
51491367 FT |
2630 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2631 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2632 | { |
2633 | unsigned long flags; | |
4da70b9e | 2634 | struct protection_domain *domain; |
4da70b9e | 2635 | |
146a6917 JR |
2636 | INC_STATS_COUNTER(cnt_unmap_single); |
2637 | ||
94f6d190 JR |
2638 | domain = get_domain(dev); |
2639 | if (IS_ERR(domain)) | |
5b28df6f JR |
2640 | return; |
2641 | ||
4da70b9e JR |
2642 | spin_lock_irqsave(&domain->lock, flags); |
2643 | ||
cd8c82e8 | 2644 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2645 | |
17b124bf | 2646 | domain_flush_complete(domain); |
4da70b9e JR |
2647 | |
2648 | spin_unlock_irqrestore(&domain->lock, flags); | |
2649 | } | |
2650 | ||
431b2a20 JR |
2651 | /* |
2652 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2653 | * lists). | |
2654 | */ | |
65b050ad | 2655 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2656 | int nelems, enum dma_data_direction dir, |
2657 | struct dma_attrs *attrs) | |
65b050ad JR |
2658 | { |
2659 | unsigned long flags; | |
65b050ad | 2660 | struct protection_domain *domain; |
65b050ad JR |
2661 | int i; |
2662 | struct scatterlist *s; | |
2663 | phys_addr_t paddr; | |
2664 | int mapped_elems = 0; | |
832a90c3 | 2665 | u64 dma_mask; |
65b050ad | 2666 | |
d03f067a JR |
2667 | INC_STATS_COUNTER(cnt_map_sg); |
2668 | ||
94f6d190 | 2669 | domain = get_domain(dev); |
a0e191b2 | 2670 | if (IS_ERR(domain)) |
94f6d190 | 2671 | return 0; |
dbcc112e | 2672 | |
832a90c3 | 2673 | dma_mask = *dev->dma_mask; |
65b050ad | 2674 | |
65b050ad JR |
2675 | spin_lock_irqsave(&domain->lock, flags); |
2676 | ||
2677 | for_each_sg(sglist, s, nelems, i) { | |
2678 | paddr = sg_phys(s); | |
2679 | ||
cd8c82e8 | 2680 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2681 | paddr, s->length, dir, false, |
2682 | dma_mask); | |
65b050ad JR |
2683 | |
2684 | if (s->dma_address) { | |
2685 | s->dma_length = s->length; | |
2686 | mapped_elems++; | |
2687 | } else | |
2688 | goto unmap; | |
65b050ad JR |
2689 | } |
2690 | ||
17b124bf | 2691 | domain_flush_complete(domain); |
65b050ad JR |
2692 | |
2693 | out: | |
2694 | spin_unlock_irqrestore(&domain->lock, flags); | |
2695 | ||
2696 | return mapped_elems; | |
2697 | unmap: | |
2698 | for_each_sg(sglist, s, mapped_elems, i) { | |
2699 | if (s->dma_address) | |
cd8c82e8 | 2700 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2701 | s->dma_length, dir); |
2702 | s->dma_address = s->dma_length = 0; | |
2703 | } | |
2704 | ||
2705 | mapped_elems = 0; | |
2706 | ||
2707 | goto out; | |
2708 | } | |
2709 | ||
431b2a20 JR |
2710 | /* |
2711 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2712 | * lists). | |
2713 | */ | |
65b050ad | 2714 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2715 | int nelems, enum dma_data_direction dir, |
2716 | struct dma_attrs *attrs) | |
65b050ad JR |
2717 | { |
2718 | unsigned long flags; | |
65b050ad JR |
2719 | struct protection_domain *domain; |
2720 | struct scatterlist *s; | |
65b050ad JR |
2721 | int i; |
2722 | ||
55877a6b JR |
2723 | INC_STATS_COUNTER(cnt_unmap_sg); |
2724 | ||
94f6d190 JR |
2725 | domain = get_domain(dev); |
2726 | if (IS_ERR(domain)) | |
5b28df6f JR |
2727 | return; |
2728 | ||
65b050ad JR |
2729 | spin_lock_irqsave(&domain->lock, flags); |
2730 | ||
2731 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2732 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2733 | s->dma_length, dir); |
65b050ad JR |
2734 | s->dma_address = s->dma_length = 0; |
2735 | } | |
2736 | ||
17b124bf | 2737 | domain_flush_complete(domain); |
65b050ad JR |
2738 | |
2739 | spin_unlock_irqrestore(&domain->lock, flags); | |
2740 | } | |
2741 | ||
431b2a20 JR |
2742 | /* |
2743 | * The exported alloc_coherent function for dma_ops. | |
2744 | */ | |
5d8b53cf | 2745 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2746 | dma_addr_t *dma_addr, gfp_t flag, |
2747 | struct dma_attrs *attrs) | |
5d8b53cf | 2748 | { |
832a90c3 | 2749 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2750 | struct protection_domain *domain; |
2751 | unsigned long flags; | |
2752 | struct page *page; | |
5d8b53cf | 2753 | |
c8f0fb36 JR |
2754 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2755 | ||
94f6d190 JR |
2756 | domain = get_domain(dev); |
2757 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2758 | page = alloc_pages(flag, get_order(size)); |
2759 | *dma_addr = page_to_phys(page); | |
2760 | return page_address(page); | |
94f6d190 JR |
2761 | } else if (IS_ERR(domain)) |
2762 | return NULL; | |
5d8b53cf | 2763 | |
3b839a57 | 2764 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2765 | dma_mask = dev->coherent_dma_mask; |
2766 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2767 | flag |= __GFP_ZERO; |
5d8b53cf | 2768 | |
3b839a57 JR |
2769 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2770 | if (!page) { | |
2771 | if (!(flag & __GFP_WAIT)) | |
2772 | return NULL; | |
5d8b53cf | 2773 | |
3b839a57 JR |
2774 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2775 | get_order(size)); | |
2776 | if (!page) | |
2777 | return NULL; | |
2778 | } | |
5d8b53cf | 2779 | |
832a90c3 JR |
2780 | if (!dma_mask) |
2781 | dma_mask = *dev->dma_mask; | |
2782 | ||
5d8b53cf JR |
2783 | spin_lock_irqsave(&domain->lock, flags); |
2784 | ||
3b839a57 | 2785 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2786 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2787 | |
8fd524b3 | 2788 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2789 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2790 | goto out_free; |
367d04c4 | 2791 | } |
5d8b53cf | 2792 | |
17b124bf | 2793 | domain_flush_complete(domain); |
5d8b53cf | 2794 | |
5d8b53cf JR |
2795 | spin_unlock_irqrestore(&domain->lock, flags); |
2796 | ||
3b839a57 | 2797 | return page_address(page); |
5b28df6f JR |
2798 | |
2799 | out_free: | |
2800 | ||
3b839a57 JR |
2801 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2802 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2803 | |
2804 | return NULL; | |
5d8b53cf JR |
2805 | } |
2806 | ||
431b2a20 JR |
2807 | /* |
2808 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2809 | */ |
5d8b53cf | 2810 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2811 | void *virt_addr, dma_addr_t dma_addr, |
2812 | struct dma_attrs *attrs) | |
5d8b53cf | 2813 | { |
5d8b53cf | 2814 | struct protection_domain *domain; |
3b839a57 JR |
2815 | unsigned long flags; |
2816 | struct page *page; | |
5d8b53cf | 2817 | |
5d31ee7e JR |
2818 | INC_STATS_COUNTER(cnt_free_coherent); |
2819 | ||
3b839a57 JR |
2820 | page = virt_to_page(virt_addr); |
2821 | size = PAGE_ALIGN(size); | |
2822 | ||
94f6d190 JR |
2823 | domain = get_domain(dev); |
2824 | if (IS_ERR(domain)) | |
5b28df6f JR |
2825 | goto free_mem; |
2826 | ||
5d8b53cf JR |
2827 | spin_lock_irqsave(&domain->lock, flags); |
2828 | ||
cd8c82e8 | 2829 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2830 | |
17b124bf | 2831 | domain_flush_complete(domain); |
5d8b53cf JR |
2832 | |
2833 | spin_unlock_irqrestore(&domain->lock, flags); | |
2834 | ||
2835 | free_mem: | |
3b839a57 JR |
2836 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2837 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2838 | } |
2839 | ||
b39ba6ad JR |
2840 | /* |
2841 | * This function is called by the DMA layer to find out if we can handle a | |
2842 | * particular device. It is part of the dma_ops. | |
2843 | */ | |
2844 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2845 | { | |
420aef8a | 2846 | return check_device(dev); |
b39ba6ad JR |
2847 | } |
2848 | ||
160c1d8e | 2849 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2850 | .alloc = alloc_coherent, |
2851 | .free = free_coherent, | |
51491367 FT |
2852 | .map_page = map_page, |
2853 | .unmap_page = unmap_page, | |
6631ee9d JR |
2854 | .map_sg = map_sg, |
2855 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2856 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2857 | }; |
2858 | ||
3a18404c | 2859 | int __init amd_iommu_init_api(void) |
27c2127a | 2860 | { |
3a18404c | 2861 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2862 | } |
2863 | ||
6631ee9d JR |
2864 | int __init amd_iommu_init_dma_ops(void) |
2865 | { | |
6631ee9d | 2866 | iommu_detected = 1; |
75f1cdf1 | 2867 | swiotlb = 0; |
6631ee9d | 2868 | |
7f26508b JR |
2869 | amd_iommu_stats_init(); |
2870 | ||
62410eeb JR |
2871 | if (amd_iommu_unmap_flush) |
2872 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2873 | else | |
2874 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2875 | ||
6631ee9d | 2876 | return 0; |
6631ee9d | 2877 | } |
6d98cd80 JR |
2878 | |
2879 | /***************************************************************************** | |
2880 | * | |
2881 | * The following functions belong to the exported interface of AMD IOMMU | |
2882 | * | |
2883 | * This interface allows access to lower level functions of the IOMMU | |
2884 | * like protection domain handling and assignement of devices to domains | |
2885 | * which is not possible with the dma_ops interface. | |
2886 | * | |
2887 | *****************************************************************************/ | |
2888 | ||
6d98cd80 JR |
2889 | static void cleanup_domain(struct protection_domain *domain) |
2890 | { | |
9b29d3c6 | 2891 | struct iommu_dev_data *entry; |
6d98cd80 | 2892 | unsigned long flags; |
6d98cd80 JR |
2893 | |
2894 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2895 | ||
9b29d3c6 JR |
2896 | while (!list_empty(&domain->dev_list)) { |
2897 | entry = list_first_entry(&domain->dev_list, | |
2898 | struct iommu_dev_data, list); | |
2899 | __detach_device(entry); | |
492667da | 2900 | } |
6d98cd80 JR |
2901 | |
2902 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2903 | } | |
2904 | ||
2650815f JR |
2905 | static void protection_domain_free(struct protection_domain *domain) |
2906 | { | |
2907 | if (!domain) | |
2908 | return; | |
2909 | ||
aeb26f55 JR |
2910 | del_domain_from_list(domain); |
2911 | ||
2650815f JR |
2912 | if (domain->id) |
2913 | domain_id_free(domain->id); | |
2914 | ||
2915 | kfree(domain); | |
2916 | } | |
2917 | ||
2918 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2919 | { |
2920 | struct protection_domain *domain; | |
2921 | ||
2922 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2923 | if (!domain) | |
2650815f | 2924 | return NULL; |
c156e347 JR |
2925 | |
2926 | spin_lock_init(&domain->lock); | |
5d214fe6 | 2927 | mutex_init(&domain->api_lock); |
c156e347 JR |
2928 | domain->id = domain_id_alloc(); |
2929 | if (!domain->id) | |
2650815f | 2930 | goto out_err; |
7c392cbe | 2931 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 2932 | |
aeb26f55 JR |
2933 | add_domain_to_list(domain); |
2934 | ||
2650815f JR |
2935 | return domain; |
2936 | ||
2937 | out_err: | |
2938 | kfree(domain); | |
2939 | ||
2940 | return NULL; | |
2941 | } | |
2942 | ||
aafd8ba0 | 2943 | static int alloc_passthrough_domain(void) |
5abcdba4 JR |
2944 | { |
2945 | if (pt_domain != NULL) | |
2946 | return 0; | |
2947 | ||
2948 | /* allocate passthrough domain */ | |
2949 | pt_domain = protection_domain_alloc(); | |
2950 | if (!pt_domain) | |
2951 | return -ENOMEM; | |
2952 | ||
2953 | pt_domain->mode = PAGE_MODE_NONE; | |
2954 | ||
2955 | return 0; | |
2956 | } | |
3f4b87b9 JR |
2957 | |
2958 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) | |
2650815f | 2959 | { |
3f4b87b9 | 2960 | struct protection_domain *pdomain; |
0bb6e243 | 2961 | struct dma_ops_domain *dma_domain; |
2650815f | 2962 | |
0bb6e243 JR |
2963 | switch (type) { |
2964 | case IOMMU_DOMAIN_UNMANAGED: | |
2965 | pdomain = protection_domain_alloc(); | |
2966 | if (!pdomain) | |
2967 | return NULL; | |
c156e347 | 2968 | |
0bb6e243 JR |
2969 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2970 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2971 | if (!pdomain->pt_root) { | |
2972 | protection_domain_free(pdomain); | |
2973 | return NULL; | |
2974 | } | |
c156e347 | 2975 | |
0bb6e243 JR |
2976 | pdomain->domain.geometry.aperture_start = 0; |
2977 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2978 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2979 | |
0bb6e243 JR |
2980 | break; |
2981 | case IOMMU_DOMAIN_DMA: | |
2982 | dma_domain = dma_ops_domain_alloc(); | |
2983 | if (!dma_domain) { | |
2984 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2985 | return NULL; | |
2986 | } | |
2987 | pdomain = &dma_domain->domain; | |
2988 | break; | |
07f643a3 JR |
2989 | case IOMMU_DOMAIN_IDENTITY: |
2990 | pdomain = protection_domain_alloc(); | |
2991 | if (!pdomain) | |
2992 | return NULL; | |
c156e347 | 2993 | |
07f643a3 JR |
2994 | pdomain->mode = PAGE_MODE_NONE; |
2995 | break; | |
0bb6e243 JR |
2996 | default: |
2997 | return NULL; | |
2998 | } | |
c156e347 | 2999 | |
3f4b87b9 | 3000 | return &pdomain->domain; |
c156e347 JR |
3001 | } |
3002 | ||
3f4b87b9 | 3003 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3004 | { |
3f4b87b9 | 3005 | struct protection_domain *domain; |
98383fc3 | 3006 | |
3f4b87b9 | 3007 | if (!dom) |
98383fc3 JR |
3008 | return; |
3009 | ||
3f4b87b9 JR |
3010 | domain = to_pdomain(dom); |
3011 | ||
98383fc3 JR |
3012 | if (domain->dev_cnt > 0) |
3013 | cleanup_domain(domain); | |
3014 | ||
3015 | BUG_ON(domain->dev_cnt != 0); | |
3016 | ||
132bd68f JR |
3017 | if (domain->mode != PAGE_MODE_NONE) |
3018 | free_pagetable(domain); | |
98383fc3 | 3019 | |
52815b75 JR |
3020 | if (domain->flags & PD_IOMMUV2_MASK) |
3021 | free_gcr3_table(domain); | |
3022 | ||
8b408fe4 | 3023 | protection_domain_free(domain); |
98383fc3 JR |
3024 | } |
3025 | ||
684f2888 JR |
3026 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3027 | struct device *dev) | |
3028 | { | |
657cbb6b | 3029 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3030 | struct amd_iommu *iommu; |
684f2888 JR |
3031 | u16 devid; |
3032 | ||
98fc5a69 | 3033 | if (!check_device(dev)) |
684f2888 JR |
3034 | return; |
3035 | ||
98fc5a69 | 3036 | devid = get_device_id(dev); |
684f2888 | 3037 | |
657cbb6b | 3038 | if (dev_data->domain != NULL) |
15898bbc | 3039 | detach_device(dev); |
684f2888 JR |
3040 | |
3041 | iommu = amd_iommu_rlookup_table[devid]; | |
3042 | if (!iommu) | |
3043 | return; | |
3044 | ||
684f2888 JR |
3045 | iommu_completion_wait(iommu); |
3046 | } | |
3047 | ||
01106066 JR |
3048 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3049 | struct device *dev) | |
3050 | { | |
3f4b87b9 | 3051 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3052 | struct iommu_dev_data *dev_data; |
01106066 | 3053 | struct amd_iommu *iommu; |
15898bbc | 3054 | int ret; |
01106066 | 3055 | |
98fc5a69 | 3056 | if (!check_device(dev)) |
01106066 JR |
3057 | return -EINVAL; |
3058 | ||
657cbb6b JR |
3059 | dev_data = dev->archdata.iommu; |
3060 | ||
f62dda66 | 3061 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3062 | if (!iommu) |
3063 | return -EINVAL; | |
3064 | ||
657cbb6b | 3065 | if (dev_data->domain) |
15898bbc | 3066 | detach_device(dev); |
01106066 | 3067 | |
15898bbc | 3068 | ret = attach_device(dev, domain); |
01106066 JR |
3069 | |
3070 | iommu_completion_wait(iommu); | |
3071 | ||
15898bbc | 3072 | return ret; |
01106066 JR |
3073 | } |
3074 | ||
468e2366 | 3075 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3076 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3077 | { |
3f4b87b9 | 3078 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3079 | int prot = 0; |
3080 | int ret; | |
3081 | ||
132bd68f JR |
3082 | if (domain->mode == PAGE_MODE_NONE) |
3083 | return -EINVAL; | |
3084 | ||
c6229ca6 JR |
3085 | if (iommu_prot & IOMMU_READ) |
3086 | prot |= IOMMU_PROT_IR; | |
3087 | if (iommu_prot & IOMMU_WRITE) | |
3088 | prot |= IOMMU_PROT_IW; | |
3089 | ||
5d214fe6 | 3090 | mutex_lock(&domain->api_lock); |
795e74f7 | 3091 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3092 | mutex_unlock(&domain->api_lock); |
3093 | ||
795e74f7 | 3094 | return ret; |
c6229ca6 JR |
3095 | } |
3096 | ||
5009065d OBC |
3097 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3098 | size_t page_size) | |
eb74ff6c | 3099 | { |
3f4b87b9 | 3100 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3101 | size_t unmap_size; |
eb74ff6c | 3102 | |
132bd68f JR |
3103 | if (domain->mode == PAGE_MODE_NONE) |
3104 | return -EINVAL; | |
3105 | ||
5d214fe6 | 3106 | mutex_lock(&domain->api_lock); |
468e2366 | 3107 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3108 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3109 | |
17b124bf | 3110 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3111 | |
5009065d | 3112 | return unmap_size; |
eb74ff6c JR |
3113 | } |
3114 | ||
645c4c8d | 3115 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3116 | dma_addr_t iova) |
645c4c8d | 3117 | { |
3f4b87b9 | 3118 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3119 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3120 | u64 *pte, __pte; |
645c4c8d | 3121 | |
132bd68f JR |
3122 | if (domain->mode == PAGE_MODE_NONE) |
3123 | return iova; | |
3124 | ||
3039ca1b | 3125 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3126 | |
a6d41a40 | 3127 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3128 | return 0; |
3129 | ||
b24b1b63 JR |
3130 | offset_mask = pte_pgsize - 1; |
3131 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3132 | |
b24b1b63 | 3133 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3134 | } |
3135 | ||
ab636481 | 3136 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3137 | { |
80a506b8 JR |
3138 | switch (cap) { |
3139 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3140 | return true; |
bdddadcb | 3141 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3142 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3143 | case IOMMU_CAP_NOEXEC: |
3144 | return false; | |
80a506b8 JR |
3145 | } |
3146 | ||
ab636481 | 3147 | return false; |
dbb9fd86 SY |
3148 | } |
3149 | ||
35cf248f JR |
3150 | static void amd_iommu_get_dm_regions(struct device *dev, |
3151 | struct list_head *head) | |
3152 | { | |
3153 | struct unity_map_entry *entry; | |
3154 | u16 devid; | |
3155 | ||
3156 | devid = get_device_id(dev); | |
3157 | ||
3158 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3159 | struct iommu_dm_region *region; | |
3160 | ||
3161 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3162 | continue; | |
3163 | ||
3164 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3165 | if (!region) { | |
3166 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3167 | dev_name(dev)); | |
3168 | return; | |
3169 | } | |
3170 | ||
3171 | region->start = entry->address_start; | |
3172 | region->length = entry->address_end - entry->address_start; | |
3173 | if (entry->prot & IOMMU_PROT_IR) | |
3174 | region->prot |= IOMMU_READ; | |
3175 | if (entry->prot & IOMMU_PROT_IW) | |
3176 | region->prot |= IOMMU_WRITE; | |
3177 | ||
3178 | list_add_tail(®ion->list, head); | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3183 | struct list_head *head) | |
3184 | { | |
3185 | struct iommu_dm_region *entry, *next; | |
3186 | ||
3187 | list_for_each_entry_safe(entry, next, head, list) | |
3188 | kfree(entry); | |
3189 | } | |
3190 | ||
b22f6434 | 3191 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3192 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3193 | .domain_alloc = amd_iommu_domain_alloc, |
3194 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3195 | .attach_dev = amd_iommu_attach_device, |
3196 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3197 | .map = amd_iommu_map, |
3198 | .unmap = amd_iommu_unmap, | |
315786eb | 3199 | .map_sg = default_iommu_map_sg, |
26961efe | 3200 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3201 | .add_device = amd_iommu_add_device, |
3202 | .remove_device = amd_iommu_remove_device, | |
35cf248f JR |
3203 | .get_dm_regions = amd_iommu_get_dm_regions, |
3204 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3205 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3206 | }; |
3207 | ||
0feae533 JR |
3208 | /***************************************************************************** |
3209 | * | |
3210 | * The next functions do a basic initialization of IOMMU for pass through | |
3211 | * mode | |
3212 | * | |
3213 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3214 | * DMA-API translation. | |
3215 | * | |
3216 | *****************************************************************************/ | |
3217 | ||
3218 | int __init amd_iommu_init_passthrough(void) | |
3219 | { | |
5abcdba4 | 3220 | struct iommu_dev_data *dev_data; |
0feae533 | 3221 | struct pci_dev *dev = NULL; |
5abcdba4 | 3222 | int ret; |
0feae533 | 3223 | |
5abcdba4 JR |
3224 | ret = alloc_passthrough_domain(); |
3225 | if (ret) | |
3226 | return ret; | |
0feae533 | 3227 | |
6c54aabd | 3228 | for_each_pci_dev(dev) { |
98fc5a69 | 3229 | if (!check_device(&dev->dev)) |
0feae533 JR |
3230 | continue; |
3231 | ||
5abcdba4 JR |
3232 | dev_data = get_dev_data(&dev->dev); |
3233 | dev_data->passthrough = true; | |
3234 | ||
15898bbc | 3235 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3236 | } |
3237 | ||
2655d7a2 JR |
3238 | amd_iommu_stats_init(); |
3239 | ||
0feae533 JR |
3240 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3241 | ||
3242 | return 0; | |
3243 | } | |
72e1dcc4 JR |
3244 | |
3245 | /* IOMMUv2 specific functions */ | |
3246 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3247 | { | |
3248 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3249 | } | |
3250 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3251 | ||
3252 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3253 | { | |
3254 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3255 | } | |
3256 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3257 | |
3258 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3259 | { | |
3f4b87b9 | 3260 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3261 | unsigned long flags; |
3262 | ||
3263 | spin_lock_irqsave(&domain->lock, flags); | |
3264 | ||
3265 | /* Update data structure */ | |
3266 | domain->mode = PAGE_MODE_NONE; | |
3267 | domain->updated = true; | |
3268 | ||
3269 | /* Make changes visible to IOMMUs */ | |
3270 | update_domain(domain); | |
3271 | ||
3272 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3273 | free_pagetable(domain); | |
3274 | ||
3275 | spin_unlock_irqrestore(&domain->lock, flags); | |
3276 | } | |
3277 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3278 | |
3279 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3280 | { | |
3f4b87b9 | 3281 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3282 | unsigned long flags; |
3283 | int levels, ret; | |
3284 | ||
3285 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3286 | return -EINVAL; | |
3287 | ||
3288 | /* Number of GCR3 table levels required */ | |
3289 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3290 | levels += 1; | |
3291 | ||
3292 | if (levels > amd_iommu_max_glx_val) | |
3293 | return -EINVAL; | |
3294 | ||
3295 | spin_lock_irqsave(&domain->lock, flags); | |
3296 | ||
3297 | /* | |
3298 | * Save us all sanity checks whether devices already in the | |
3299 | * domain support IOMMUv2. Just force that the domain has no | |
3300 | * devices attached when it is switched into IOMMUv2 mode. | |
3301 | */ | |
3302 | ret = -EBUSY; | |
3303 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3304 | goto out; | |
3305 | ||
3306 | ret = -ENOMEM; | |
3307 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3308 | if (domain->gcr3_tbl == NULL) | |
3309 | goto out; | |
3310 | ||
3311 | domain->glx = levels; | |
3312 | domain->flags |= PD_IOMMUV2_MASK; | |
3313 | domain->updated = true; | |
3314 | ||
3315 | update_domain(domain); | |
3316 | ||
3317 | ret = 0; | |
3318 | ||
3319 | out: | |
3320 | spin_unlock_irqrestore(&domain->lock, flags); | |
3321 | ||
3322 | return ret; | |
3323 | } | |
3324 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3325 | |
3326 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3327 | u64 address, bool size) | |
3328 | { | |
3329 | struct iommu_dev_data *dev_data; | |
3330 | struct iommu_cmd cmd; | |
3331 | int i, ret; | |
3332 | ||
3333 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3334 | return -EINVAL; | |
3335 | ||
3336 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3337 | ||
3338 | /* | |
3339 | * IOMMU TLB needs to be flushed before Device TLB to | |
3340 | * prevent device TLB refill from IOMMU TLB | |
3341 | */ | |
3342 | for (i = 0; i < amd_iommus_present; ++i) { | |
3343 | if (domain->dev_iommu[i] == 0) | |
3344 | continue; | |
3345 | ||
3346 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3347 | if (ret != 0) | |
3348 | goto out; | |
3349 | } | |
3350 | ||
3351 | /* Wait until IOMMU TLB flushes are complete */ | |
3352 | domain_flush_complete(domain); | |
3353 | ||
3354 | /* Now flush device TLBs */ | |
3355 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3356 | struct amd_iommu *iommu; | |
3357 | int qdep; | |
3358 | ||
3359 | BUG_ON(!dev_data->ats.enabled); | |
3360 | ||
3361 | qdep = dev_data->ats.qdep; | |
3362 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3363 | ||
3364 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3365 | qdep, address, size); | |
3366 | ||
3367 | ret = iommu_queue_command(iommu, &cmd); | |
3368 | if (ret != 0) | |
3369 | goto out; | |
3370 | } | |
3371 | ||
3372 | /* Wait until all device TLBs are flushed */ | |
3373 | domain_flush_complete(domain); | |
3374 | ||
3375 | ret = 0; | |
3376 | ||
3377 | out: | |
3378 | ||
3379 | return ret; | |
3380 | } | |
3381 | ||
3382 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3383 | u64 address) | |
3384 | { | |
399be2f5 JR |
3385 | INC_STATS_COUNTER(invalidate_iotlb); |
3386 | ||
22e266c7 JR |
3387 | return __flush_pasid(domain, pasid, address, false); |
3388 | } | |
3389 | ||
3390 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3391 | u64 address) | |
3392 | { | |
3f4b87b9 | 3393 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3394 | unsigned long flags; |
3395 | int ret; | |
3396 | ||
3397 | spin_lock_irqsave(&domain->lock, flags); | |
3398 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3399 | spin_unlock_irqrestore(&domain->lock, flags); | |
3400 | ||
3401 | return ret; | |
3402 | } | |
3403 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3404 | ||
3405 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3406 | { | |
399be2f5 JR |
3407 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3408 | ||
22e266c7 JR |
3409 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3410 | true); | |
3411 | } | |
3412 | ||
3413 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3414 | { | |
3f4b87b9 | 3415 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3416 | unsigned long flags; |
3417 | int ret; | |
3418 | ||
3419 | spin_lock_irqsave(&domain->lock, flags); | |
3420 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3421 | spin_unlock_irqrestore(&domain->lock, flags); | |
3422 | ||
3423 | return ret; | |
3424 | } | |
3425 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3426 | ||
b16137b1 JR |
3427 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3428 | { | |
3429 | int index; | |
3430 | u64 *pte; | |
3431 | ||
3432 | while (true) { | |
3433 | ||
3434 | index = (pasid >> (9 * level)) & 0x1ff; | |
3435 | pte = &root[index]; | |
3436 | ||
3437 | if (level == 0) | |
3438 | break; | |
3439 | ||
3440 | if (!(*pte & GCR3_VALID)) { | |
3441 | if (!alloc) | |
3442 | return NULL; | |
3443 | ||
3444 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3445 | if (root == NULL) | |
3446 | return NULL; | |
3447 | ||
3448 | *pte = __pa(root) | GCR3_VALID; | |
3449 | } | |
3450 | ||
3451 | root = __va(*pte & PAGE_MASK); | |
3452 | ||
3453 | level -= 1; | |
3454 | } | |
3455 | ||
3456 | return pte; | |
3457 | } | |
3458 | ||
3459 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3460 | unsigned long cr3) | |
3461 | { | |
3462 | u64 *pte; | |
3463 | ||
3464 | if (domain->mode != PAGE_MODE_NONE) | |
3465 | return -EINVAL; | |
3466 | ||
3467 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3468 | if (pte == NULL) | |
3469 | return -ENOMEM; | |
3470 | ||
3471 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3472 | ||
3473 | return __amd_iommu_flush_tlb(domain, pasid); | |
3474 | } | |
3475 | ||
3476 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3477 | { | |
3478 | u64 *pte; | |
3479 | ||
3480 | if (domain->mode != PAGE_MODE_NONE) | |
3481 | return -EINVAL; | |
3482 | ||
3483 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3484 | if (pte == NULL) | |
3485 | return 0; | |
3486 | ||
3487 | *pte = 0; | |
3488 | ||
3489 | return __amd_iommu_flush_tlb(domain, pasid); | |
3490 | } | |
3491 | ||
3492 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3493 | unsigned long cr3) | |
3494 | { | |
3f4b87b9 | 3495 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3496 | unsigned long flags; |
3497 | int ret; | |
3498 | ||
3499 | spin_lock_irqsave(&domain->lock, flags); | |
3500 | ret = __set_gcr3(domain, pasid, cr3); | |
3501 | spin_unlock_irqrestore(&domain->lock, flags); | |
3502 | ||
3503 | return ret; | |
3504 | } | |
3505 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3506 | ||
3507 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3508 | { | |
3f4b87b9 | 3509 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3510 | unsigned long flags; |
3511 | int ret; | |
3512 | ||
3513 | spin_lock_irqsave(&domain->lock, flags); | |
3514 | ret = __clear_gcr3(domain, pasid); | |
3515 | spin_unlock_irqrestore(&domain->lock, flags); | |
3516 | ||
3517 | return ret; | |
3518 | } | |
3519 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3520 | |
3521 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3522 | int status, int tag) | |
3523 | { | |
3524 | struct iommu_dev_data *dev_data; | |
3525 | struct amd_iommu *iommu; | |
3526 | struct iommu_cmd cmd; | |
3527 | ||
399be2f5 JR |
3528 | INC_STATS_COUNTER(complete_ppr); |
3529 | ||
c99afa25 JR |
3530 | dev_data = get_dev_data(&pdev->dev); |
3531 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3532 | ||
3533 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3534 | tag, dev_data->pri_tlp); | |
3535 | ||
3536 | return iommu_queue_command(iommu, &cmd); | |
3537 | } | |
3538 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3539 | |
3540 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3541 | { | |
3f4b87b9 | 3542 | struct protection_domain *pdomain; |
f3572db8 | 3543 | |
3f4b87b9 JR |
3544 | pdomain = get_domain(&pdev->dev); |
3545 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3546 | return NULL; |
3547 | ||
3548 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3549 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3550 | return NULL; |
3551 | ||
3f4b87b9 | 3552 | return &pdomain->domain; |
f3572db8 JR |
3553 | } |
3554 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3555 | |
3556 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3557 | { | |
3558 | struct iommu_dev_data *dev_data; | |
3559 | ||
3560 | if (!amd_iommu_v2_supported()) | |
3561 | return; | |
3562 | ||
3563 | dev_data = get_dev_data(&pdev->dev); | |
3564 | dev_data->errata |= (1 << erratum); | |
3565 | } | |
3566 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3567 | |
3568 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3569 | struct amd_iommu_device_info *info) | |
3570 | { | |
3571 | int max_pasids; | |
3572 | int pos; | |
3573 | ||
3574 | if (pdev == NULL || info == NULL) | |
3575 | return -EINVAL; | |
3576 | ||
3577 | if (!amd_iommu_v2_supported()) | |
3578 | return -EINVAL; | |
3579 | ||
3580 | memset(info, 0, sizeof(*info)); | |
3581 | ||
3582 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3583 | if (pos) | |
3584 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3585 | ||
3586 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3587 | if (pos) | |
3588 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3589 | ||
3590 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3591 | if (pos) { | |
3592 | int features; | |
3593 | ||
3594 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3595 | max_pasids = min(max_pasids, (1 << 20)); | |
3596 | ||
3597 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3598 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3599 | ||
3600 | features = pci_pasid_features(pdev); | |
3601 | if (features & PCI_PASID_CAP_EXEC) | |
3602 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3603 | if (features & PCI_PASID_CAP_PRIV) | |
3604 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3605 | } | |
3606 | ||
3607 | return 0; | |
3608 | } | |
3609 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3610 | |
3611 | #ifdef CONFIG_IRQ_REMAP | |
3612 | ||
3613 | /***************************************************************************** | |
3614 | * | |
3615 | * Interrupt Remapping Implementation | |
3616 | * | |
3617 | *****************************************************************************/ | |
3618 | ||
3619 | union irte { | |
3620 | u32 val; | |
3621 | struct { | |
3622 | u32 valid : 1, | |
3623 | no_fault : 1, | |
3624 | int_type : 3, | |
3625 | rq_eoi : 1, | |
3626 | dm : 1, | |
3627 | rsvd_1 : 1, | |
3628 | destination : 8, | |
3629 | vector : 8, | |
3630 | rsvd_2 : 8; | |
3631 | } fields; | |
3632 | }; | |
3633 | ||
3634 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3635 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3636 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3637 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3638 | ||
3639 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3640 | { | |
3641 | u64 dte; | |
3642 | ||
3643 | dte = amd_iommu_dev_table[devid].data[2]; | |
3644 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3645 | dte |= virt_to_phys(table->table); | |
3646 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3647 | dte |= DTE_IRQ_TABLE_LEN; | |
3648 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3649 | ||
3650 | amd_iommu_dev_table[devid].data[2] = dte; | |
3651 | } | |
3652 | ||
3653 | #define IRTE_ALLOCATED (~1U) | |
3654 | ||
3655 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3656 | { | |
3657 | struct irq_remap_table *table = NULL; | |
3658 | struct amd_iommu *iommu; | |
3659 | unsigned long flags; | |
3660 | u16 alias; | |
3661 | ||
3662 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3663 | ||
3664 | iommu = amd_iommu_rlookup_table[devid]; | |
3665 | if (!iommu) | |
3666 | goto out_unlock; | |
3667 | ||
3668 | table = irq_lookup_table[devid]; | |
3669 | if (table) | |
3670 | goto out; | |
3671 | ||
3672 | alias = amd_iommu_alias_table[devid]; | |
3673 | table = irq_lookup_table[alias]; | |
3674 | if (table) { | |
3675 | irq_lookup_table[devid] = table; | |
3676 | set_dte_irq_entry(devid, table); | |
3677 | iommu_flush_dte(iommu, devid); | |
3678 | goto out; | |
3679 | } | |
3680 | ||
3681 | /* Nothing there yet, allocate new irq remapping table */ | |
3682 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3683 | if (!table) | |
3684 | goto out; | |
3685 | ||
197887f0 JR |
3686 | /* Initialize table spin-lock */ |
3687 | spin_lock_init(&table->lock); | |
3688 | ||
2b324506 JR |
3689 | if (ioapic) |
3690 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3691 | table->min_index = 32; | |
3692 | ||
3693 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3694 | if (!table->table) { | |
3695 | kfree(table); | |
821f0f68 | 3696 | table = NULL; |
2b324506 JR |
3697 | goto out; |
3698 | } | |
3699 | ||
3700 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3701 | ||
3702 | if (ioapic) { | |
3703 | int i; | |
3704 | ||
3705 | for (i = 0; i < 32; ++i) | |
3706 | table->table[i] = IRTE_ALLOCATED; | |
3707 | } | |
3708 | ||
3709 | irq_lookup_table[devid] = table; | |
3710 | set_dte_irq_entry(devid, table); | |
3711 | iommu_flush_dte(iommu, devid); | |
3712 | if (devid != alias) { | |
3713 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3714 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3715 | iommu_flush_dte(iommu, alias); |
3716 | } | |
3717 | ||
3718 | out: | |
3719 | iommu_completion_wait(iommu); | |
3720 | ||
3721 | out_unlock: | |
3722 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3723 | ||
3724 | return table; | |
3725 | } | |
3726 | ||
3727 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
3728 | { | |
3729 | struct irq_remap_table *table; | |
3730 | unsigned long flags; | |
3731 | int index, c; | |
3732 | ||
3733 | table = get_irq_table(devid, false); | |
3734 | if (!table) | |
3735 | return -ENODEV; | |
3736 | ||
3737 | spin_lock_irqsave(&table->lock, flags); | |
3738 | ||
3739 | /* Scan table for free entries */ | |
3740 | for (c = 0, index = table->min_index; | |
3741 | index < MAX_IRQS_PER_TABLE; | |
3742 | ++index) { | |
3743 | if (table->table[index] == 0) | |
3744 | c += 1; | |
3745 | else | |
3746 | c = 0; | |
3747 | ||
3748 | if (c == count) { | |
0dfedd61 | 3749 | struct irq_2_irte *irte_info; |
2b324506 JR |
3750 | |
3751 | for (; c != 0; --c) | |
3752 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3753 | ||
3754 | index -= count - 1; | |
3755 | ||
9b1b0e42 | 3756 | cfg->remapped = 1; |
0dfedd61 JR |
3757 | irte_info = &cfg->irq_2_irte; |
3758 | irte_info->devid = devid; | |
3759 | irte_info->index = index; | |
2b324506 JR |
3760 | |
3761 | goto out; | |
3762 | } | |
3763 | } | |
3764 | ||
3765 | index = -ENOSPC; | |
3766 | ||
3767 | out: | |
3768 | spin_unlock_irqrestore(&table->lock, flags); | |
3769 | ||
3770 | return index; | |
3771 | } | |
3772 | ||
3773 | static int get_irte(u16 devid, int index, union irte *irte) | |
3774 | { | |
3775 | struct irq_remap_table *table; | |
3776 | unsigned long flags; | |
3777 | ||
3778 | table = get_irq_table(devid, false); | |
3779 | if (!table) | |
3780 | return -ENOMEM; | |
3781 | ||
3782 | spin_lock_irqsave(&table->lock, flags); | |
3783 | irte->val = table->table[index]; | |
3784 | spin_unlock_irqrestore(&table->lock, flags); | |
3785 | ||
3786 | return 0; | |
3787 | } | |
3788 | ||
3789 | static int modify_irte(u16 devid, int index, union irte irte) | |
3790 | { | |
3791 | struct irq_remap_table *table; | |
3792 | struct amd_iommu *iommu; | |
3793 | unsigned long flags; | |
3794 | ||
3795 | iommu = amd_iommu_rlookup_table[devid]; | |
3796 | if (iommu == NULL) | |
3797 | return -EINVAL; | |
3798 | ||
3799 | table = get_irq_table(devid, false); | |
3800 | if (!table) | |
3801 | return -ENOMEM; | |
3802 | ||
3803 | spin_lock_irqsave(&table->lock, flags); | |
3804 | table->table[index] = irte.val; | |
3805 | spin_unlock_irqrestore(&table->lock, flags); | |
3806 | ||
3807 | iommu_flush_irt(iommu, devid); | |
3808 | iommu_completion_wait(iommu); | |
3809 | ||
3810 | return 0; | |
3811 | } | |
3812 | ||
3813 | static void free_irte(u16 devid, int index) | |
3814 | { | |
3815 | struct irq_remap_table *table; | |
3816 | struct amd_iommu *iommu; | |
3817 | unsigned long flags; | |
3818 | ||
3819 | iommu = amd_iommu_rlookup_table[devid]; | |
3820 | if (iommu == NULL) | |
3821 | return; | |
3822 | ||
3823 | table = get_irq_table(devid, false); | |
3824 | if (!table) | |
3825 | return; | |
3826 | ||
3827 | spin_lock_irqsave(&table->lock, flags); | |
3828 | table->table[index] = 0; | |
3829 | spin_unlock_irqrestore(&table->lock, flags); | |
3830 | ||
3831 | iommu_flush_irt(iommu, devid); | |
3832 | iommu_completion_wait(iommu); | |
3833 | } | |
3834 | ||
5527de74 JR |
3835 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
3836 | unsigned int destination, int vector, | |
3837 | struct io_apic_irq_attr *attr) | |
3838 | { | |
3839 | struct irq_remap_table *table; | |
0dfedd61 | 3840 | struct irq_2_irte *irte_info; |
5527de74 JR |
3841 | struct irq_cfg *cfg; |
3842 | union irte irte; | |
3843 | int ioapic_id; | |
3844 | int index; | |
3845 | int devid; | |
3846 | int ret; | |
3847 | ||
719b530c | 3848 | cfg = irq_cfg(irq); |
5527de74 JR |
3849 | if (!cfg) |
3850 | return -EINVAL; | |
3851 | ||
0dfedd61 | 3852 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
3853 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
3854 | devid = get_ioapic_devid(ioapic_id); | |
3855 | ||
3856 | if (devid < 0) | |
3857 | return devid; | |
3858 | ||
3859 | table = get_irq_table(devid, true); | |
3860 | if (table == NULL) | |
3861 | return -ENOMEM; | |
3862 | ||
3863 | index = attr->ioapic_pin; | |
3864 | ||
3865 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 3866 | cfg->remapped = 1; |
0dfedd61 JR |
3867 | irte_info->devid = devid; |
3868 | irte_info->index = index; | |
5527de74 JR |
3869 | |
3870 | /* Setup IRTE for IOMMU */ | |
3871 | irte.val = 0; | |
3872 | irte.fields.vector = vector; | |
3873 | irte.fields.int_type = apic->irq_delivery_mode; | |
3874 | irte.fields.destination = destination; | |
3875 | irte.fields.dm = apic->irq_dest_mode; | |
3876 | irte.fields.valid = 1; | |
3877 | ||
3878 | ret = modify_irte(devid, index, irte); | |
3879 | if (ret) | |
3880 | return ret; | |
3881 | ||
3882 | /* Setup IOAPIC entry */ | |
3883 | memset(entry, 0, sizeof(*entry)); | |
3884 | ||
3885 | entry->vector = index; | |
3886 | entry->mask = 0; | |
3887 | entry->trigger = attr->trigger; | |
3888 | entry->polarity = attr->polarity; | |
3889 | ||
3890 | /* | |
3891 | * Mask level triggered irqs. | |
5527de74 JR |
3892 | */ |
3893 | if (attr->trigger) | |
3894 | entry->mask = 1; | |
3895 | ||
3896 | return 0; | |
3897 | } | |
3898 | ||
3899 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
3900 | bool force) | |
3901 | { | |
0dfedd61 | 3902 | struct irq_2_irte *irte_info; |
5527de74 JR |
3903 | unsigned int dest, irq; |
3904 | struct irq_cfg *cfg; | |
3905 | union irte irte; | |
3906 | int err; | |
3907 | ||
3908 | if (!config_enabled(CONFIG_SMP)) | |
3909 | return -1; | |
3910 | ||
719b530c | 3911 | cfg = irqd_cfg(data); |
5527de74 | 3912 | irq = data->irq; |
0dfedd61 | 3913 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
3914 | |
3915 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
3916 | return -EINVAL; | |
3917 | ||
0dfedd61 | 3918 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
3919 | return -EBUSY; |
3920 | ||
3921 | if (assign_irq_vector(irq, cfg, mask)) | |
3922 | return -EBUSY; | |
3923 | ||
3924 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
3925 | if (err) { | |
3926 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
3927 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
3928 | return err; | |
3929 | } | |
3930 | ||
3931 | irte.fields.vector = cfg->vector; | |
3932 | irte.fields.destination = dest; | |
3933 | ||
0dfedd61 | 3934 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
3935 | |
3936 | if (cfg->move_in_progress) | |
3937 | send_cleanup_vector(cfg); | |
3938 | ||
3939 | cpumask_copy(data->affinity, mask); | |
3940 | ||
3941 | return 0; | |
3942 | } | |
3943 | ||
3944 | static int free_irq(int irq) | |
3945 | { | |
0dfedd61 | 3946 | struct irq_2_irte *irte_info; |
5527de74 JR |
3947 | struct irq_cfg *cfg; |
3948 | ||
719b530c | 3949 | cfg = irq_cfg(irq); |
5527de74 JR |
3950 | if (!cfg) |
3951 | return -EINVAL; | |
3952 | ||
0dfedd61 | 3953 | irte_info = &cfg->irq_2_irte; |
5527de74 | 3954 | |
0dfedd61 | 3955 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
3956 | |
3957 | return 0; | |
3958 | } | |
3959 | ||
0b4d48cb JR |
3960 | static void compose_msi_msg(struct pci_dev *pdev, |
3961 | unsigned int irq, unsigned int dest, | |
3962 | struct msi_msg *msg, u8 hpet_id) | |
3963 | { | |
0dfedd61 | 3964 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
3965 | struct irq_cfg *cfg; |
3966 | union irte irte; | |
3967 | ||
719b530c | 3968 | cfg = irq_cfg(irq); |
0b4d48cb JR |
3969 | if (!cfg) |
3970 | return; | |
3971 | ||
0dfedd61 | 3972 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
3973 | |
3974 | irte.val = 0; | |
3975 | irte.fields.vector = cfg->vector; | |
3976 | irte.fields.int_type = apic->irq_delivery_mode; | |
3977 | irte.fields.destination = dest; | |
3978 | irte.fields.dm = apic->irq_dest_mode; | |
3979 | irte.fields.valid = 1; | |
3980 | ||
0dfedd61 | 3981 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
3982 | |
3983 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3984 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 3985 | msg->data = irte_info->index; |
0b4d48cb JR |
3986 | } |
3987 | ||
3988 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
3989 | { | |
3990 | struct irq_cfg *cfg; | |
3991 | int index; | |
3992 | u16 devid; | |
3993 | ||
3994 | if (!pdev) | |
3995 | return -EINVAL; | |
3996 | ||
719b530c | 3997 | cfg = irq_cfg(irq); |
0b4d48cb JR |
3998 | if (!cfg) |
3999 | return -EINVAL; | |
4000 | ||
4001 | devid = get_device_id(&pdev->dev); | |
4002 | index = alloc_irq_index(cfg, devid, nvec); | |
4003 | ||
4004 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4005 | } | |
4006 | ||
4007 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4008 | int index, int offset) | |
4009 | { | |
0dfedd61 | 4010 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4011 | struct irq_cfg *cfg; |
4012 | u16 devid; | |
4013 | ||
4014 | if (!pdev) | |
4015 | return -EINVAL; | |
4016 | ||
719b530c | 4017 | cfg = irq_cfg(irq); |
0b4d48cb JR |
4018 | if (!cfg) |
4019 | return -EINVAL; | |
4020 | ||
4021 | if (index >= MAX_IRQS_PER_TABLE) | |
4022 | return 0; | |
4023 | ||
4024 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4025 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4026 | |
9b1b0e42 | 4027 | cfg->remapped = 1; |
0dfedd61 JR |
4028 | irte_info->devid = devid; |
4029 | irte_info->index = index + offset; | |
0b4d48cb JR |
4030 | |
4031 | return 0; | |
4032 | } | |
4033 | ||
5fc24d8c | 4034 | static int alloc_hpet_msi(unsigned int irq, unsigned int id) |
d976195c | 4035 | { |
0dfedd61 | 4036 | struct irq_2_irte *irte_info; |
d976195c JR |
4037 | struct irq_cfg *cfg; |
4038 | int index, devid; | |
4039 | ||
719b530c | 4040 | cfg = irq_cfg(irq); |
d976195c JR |
4041 | if (!cfg) |
4042 | return -EINVAL; | |
4043 | ||
0dfedd61 | 4044 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4045 | devid = get_hpet_devid(id); |
4046 | if (devid < 0) | |
4047 | return devid; | |
4048 | ||
4049 | index = alloc_irq_index(cfg, devid, 1); | |
4050 | if (index < 0) | |
4051 | return index; | |
4052 | ||
9b1b0e42 | 4053 | cfg->remapped = 1; |
0dfedd61 JR |
4054 | irte_info->devid = devid; |
4055 | irte_info->index = index; | |
d976195c JR |
4056 | |
4057 | return 0; | |
4058 | } | |
4059 | ||
6b474b82 | 4060 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4061 | .prepare = amd_iommu_prepare, |
4062 | .enable = amd_iommu_enable, | |
4063 | .disable = amd_iommu_disable, | |
4064 | .reenable = amd_iommu_reenable, | |
4065 | .enable_faulting = amd_iommu_enable_faulting, | |
4066 | .setup_ioapic_entry = setup_ioapic_entry, | |
4067 | .set_affinity = set_affinity, | |
4068 | .free_irq = free_irq, | |
4069 | .compose_msi_msg = compose_msi_msg, | |
4070 | .msi_alloc_irq = msi_alloc_irq, | |
4071 | .msi_setup_irq = msi_setup_irq, | |
5fc24d8c | 4072 | .alloc_hpet_msi = alloc_hpet_msi, |
6b474b82 | 4073 | }; |
2b324506 | 4074 | #endif |