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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
17f5b569 | 34 | #include <asm/msidef.h> |
b6c02715 | 35 | #include <asm/proto.h> |
46a7fa27 | 36 | #include <asm/iommu.h> |
1d9b16d1 | 37 | #include <asm/gart.h> |
27c2127a | 38 | #include <asm/dma.h> |
403f81d8 JR |
39 | |
40 | #include "amd_iommu_proto.h" | |
41 | #include "amd_iommu_types.h" | |
b6c02715 JR |
42 | |
43 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
44 | ||
815b33fd | 45 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 46 | |
aa3de9c0 OBC |
47 | /* |
48 | * This bitmap is used to advertise the page sizes our hardware support | |
49 | * to the IOMMU core, which will then use this information to split | |
50 | * physically contiguous memory regions it is mapping into page sizes | |
51 | * that we support. | |
52 | * | |
53 | * Traditionally the IOMMU core just handed us the mappings directly, | |
54 | * after making sure the size is an order of a 4KiB page and that the | |
55 | * mapping has natural alignment. | |
56 | * | |
57 | * To retain this behavior, we currently advertise that we support | |
58 | * all page sizes that are an order of 4KiB. | |
59 | * | |
60 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
61 | * we could change this to advertise the real page sizes we support. | |
62 | */ | |
63 | #define AMD_IOMMU_PGSIZES (~0xFFFUL) | |
64 | ||
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
0feae533 JR |
75 | /* |
76 | * Domain for untranslated devices - only allocated | |
77 | * if iommu=pt passed on kernel cmd line. | |
78 | */ | |
79 | static struct protection_domain *pt_domain; | |
80 | ||
26961efe | 81 | static struct iommu_ops amd_iommu_ops; |
26961efe | 82 | |
72e1dcc4 | 83 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 84 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 85 | |
431b2a20 JR |
86 | /* |
87 | * general struct to manage commands send to an IOMMU | |
88 | */ | |
d6449536 | 89 | struct iommu_cmd { |
b6c02715 JR |
90 | u32 data[4]; |
91 | }; | |
92 | ||
04bfdd84 | 93 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 94 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 95 | |
15898bbc JR |
96 | /**************************************************************************** |
97 | * | |
98 | * Helper functions | |
99 | * | |
100 | ****************************************************************************/ | |
101 | ||
f62dda66 | 102 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
103 | { |
104 | struct iommu_dev_data *dev_data; | |
105 | unsigned long flags; | |
106 | ||
107 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
108 | if (!dev_data) | |
109 | return NULL; | |
110 | ||
f62dda66 | 111 | dev_data->devid = devid; |
8fa5f802 JR |
112 | atomic_set(&dev_data->bind, 0); |
113 | ||
114 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
115 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
116 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
117 | ||
118 | return dev_data; | |
119 | } | |
120 | ||
121 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
122 | { | |
123 | unsigned long flags; | |
124 | ||
125 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
126 | list_del(&dev_data->dev_data_list); | |
127 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
128 | ||
129 | kfree(dev_data); | |
130 | } | |
131 | ||
3b03bb74 JR |
132 | static struct iommu_dev_data *search_dev_data(u16 devid) |
133 | { | |
134 | struct iommu_dev_data *dev_data; | |
135 | unsigned long flags; | |
136 | ||
137 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
138 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
139 | if (dev_data->devid == devid) | |
140 | goto out_unlock; | |
141 | } | |
142 | ||
143 | dev_data = NULL; | |
144 | ||
145 | out_unlock: | |
146 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
147 | ||
148 | return dev_data; | |
149 | } | |
150 | ||
151 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
152 | { | |
153 | struct iommu_dev_data *dev_data; | |
154 | ||
155 | dev_data = search_dev_data(devid); | |
156 | ||
157 | if (dev_data == NULL) | |
158 | dev_data = alloc_dev_data(devid); | |
159 | ||
160 | return dev_data; | |
161 | } | |
162 | ||
15898bbc JR |
163 | static inline u16 get_device_id(struct device *dev) |
164 | { | |
165 | struct pci_dev *pdev = to_pci_dev(dev); | |
166 | ||
167 | return calc_devid(pdev->bus->number, pdev->devfn); | |
168 | } | |
169 | ||
657cbb6b JR |
170 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
171 | { | |
172 | return dev->archdata.iommu; | |
173 | } | |
174 | ||
5abcdba4 JR |
175 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
176 | { | |
177 | static const int caps[] = { | |
178 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
179 | PCI_EXT_CAP_ID_PRI, |
180 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
181 | }; |
182 | int i, pos; | |
183 | ||
184 | for (i = 0; i < 3; ++i) { | |
185 | pos = pci_find_ext_capability(pdev, caps[i]); | |
186 | if (pos == 0) | |
187 | return false; | |
188 | } | |
189 | ||
190 | return true; | |
191 | } | |
192 | ||
6a113ddc JR |
193 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
194 | { | |
195 | struct iommu_dev_data *dev_data; | |
196 | ||
197 | dev_data = get_dev_data(&pdev->dev); | |
198 | ||
199 | return dev_data->errata & (1 << erratum) ? true : false; | |
200 | } | |
201 | ||
71c70984 JR |
202 | /* |
203 | * In this function the list of preallocated protection domains is traversed to | |
204 | * find the domain for a specific device | |
205 | */ | |
206 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
207 | { | |
208 | struct dma_ops_domain *entry, *ret = NULL; | |
209 | unsigned long flags; | |
210 | u16 alias = amd_iommu_alias_table[devid]; | |
211 | ||
212 | if (list_empty(&iommu_pd_list)) | |
213 | return NULL; | |
214 | ||
215 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
216 | ||
217 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
218 | if (entry->target_dev == devid || | |
219 | entry->target_dev == alias) { | |
220 | ret = entry; | |
221 | break; | |
222 | } | |
223 | } | |
224 | ||
225 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
98fc5a69 JR |
230 | /* |
231 | * This function checks if the driver got a valid device from the caller to | |
232 | * avoid dereferencing invalid pointers. | |
233 | */ | |
234 | static bool check_device(struct device *dev) | |
235 | { | |
236 | u16 devid; | |
237 | ||
238 | if (!dev || !dev->dma_mask) | |
239 | return false; | |
240 | ||
241 | /* No device or no PCI device */ | |
339d3261 | 242 | if (dev->bus != &pci_bus_type) |
98fc5a69 JR |
243 | return false; |
244 | ||
245 | devid = get_device_id(dev); | |
246 | ||
247 | /* Out of our scope? */ | |
248 | if (devid > amd_iommu_last_bdf) | |
249 | return false; | |
250 | ||
251 | if (amd_iommu_rlookup_table[devid] == NULL) | |
252 | return false; | |
253 | ||
254 | return true; | |
255 | } | |
256 | ||
657cbb6b JR |
257 | static int iommu_init_device(struct device *dev) |
258 | { | |
9dcd6130 | 259 | struct pci_dev *dma_pdev, *pdev = to_pci_dev(dev); |
657cbb6b | 260 | struct iommu_dev_data *dev_data; |
9dcd6130 | 261 | struct iommu_group *group; |
8fa5f802 | 262 | u16 alias; |
9dcd6130 | 263 | int ret; |
657cbb6b JR |
264 | |
265 | if (dev->archdata.iommu) | |
266 | return 0; | |
267 | ||
3b03bb74 | 268 | dev_data = find_dev_data(get_device_id(dev)); |
657cbb6b JR |
269 | if (!dev_data) |
270 | return -ENOMEM; | |
271 | ||
f62dda66 | 272 | alias = amd_iommu_alias_table[dev_data->devid]; |
2b02b091 | 273 | if (alias != dev_data->devid) { |
71f77580 | 274 | struct iommu_dev_data *alias_data; |
b00d3bcf | 275 | |
71f77580 JR |
276 | alias_data = find_dev_data(alias); |
277 | if (alias_data == NULL) { | |
278 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
279 | dev_name(dev)); | |
2b02b091 JR |
280 | free_dev_data(dev_data); |
281 | return -ENOTSUPP; | |
282 | } | |
71f77580 | 283 | dev_data->alias_data = alias_data; |
9dcd6130 AW |
284 | |
285 | dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); | |
286 | } else | |
287 | dma_pdev = pci_dev_get(pdev); | |
288 | ||
289 | group = iommu_group_get(&dma_pdev->dev); | |
290 | pci_dev_put(dma_pdev); | |
291 | if (!group) { | |
292 | group = iommu_group_alloc(); | |
293 | if (IS_ERR(group)) | |
294 | return PTR_ERR(group); | |
26018874 | 295 | } |
657cbb6b | 296 | |
9dcd6130 AW |
297 | ret = iommu_group_add_device(group, dev); |
298 | ||
299 | iommu_group_put(group); | |
300 | ||
301 | if (ret) | |
302 | return ret; | |
303 | ||
5abcdba4 JR |
304 | if (pci_iommuv2_capable(pdev)) { |
305 | struct amd_iommu *iommu; | |
306 | ||
307 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
308 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
309 | } | |
310 | ||
657cbb6b JR |
311 | dev->archdata.iommu = dev_data; |
312 | ||
657cbb6b JR |
313 | return 0; |
314 | } | |
315 | ||
26018874 JR |
316 | static void iommu_ignore_device(struct device *dev) |
317 | { | |
318 | u16 devid, alias; | |
319 | ||
320 | devid = get_device_id(dev); | |
321 | alias = amd_iommu_alias_table[devid]; | |
322 | ||
323 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
324 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
325 | ||
326 | amd_iommu_rlookup_table[devid] = NULL; | |
327 | amd_iommu_rlookup_table[alias] = NULL; | |
328 | } | |
329 | ||
657cbb6b JR |
330 | static void iommu_uninit_device(struct device *dev) |
331 | { | |
9dcd6130 AW |
332 | iommu_group_remove_device(dev); |
333 | ||
8fa5f802 JR |
334 | /* |
335 | * Nothing to do here - we keep dev_data around for unplugged devices | |
336 | * and reuse it when the device is re-plugged - not doing so would | |
337 | * introduce a ton of races. | |
338 | */ | |
657cbb6b | 339 | } |
b7cc9554 JR |
340 | |
341 | void __init amd_iommu_uninit_devices(void) | |
342 | { | |
8fa5f802 | 343 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
344 | struct pci_dev *pdev = NULL; |
345 | ||
346 | for_each_pci_dev(pdev) { | |
347 | ||
348 | if (!check_device(&pdev->dev)) | |
349 | continue; | |
350 | ||
351 | iommu_uninit_device(&pdev->dev); | |
352 | } | |
8fa5f802 JR |
353 | |
354 | /* Free all of our dev_data structures */ | |
355 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
356 | free_dev_data(dev_data); | |
b7cc9554 JR |
357 | } |
358 | ||
359 | int __init amd_iommu_init_devices(void) | |
360 | { | |
361 | struct pci_dev *pdev = NULL; | |
362 | int ret = 0; | |
363 | ||
364 | for_each_pci_dev(pdev) { | |
365 | ||
366 | if (!check_device(&pdev->dev)) | |
367 | continue; | |
368 | ||
369 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
370 | if (ret == -ENOTSUPP) |
371 | iommu_ignore_device(&pdev->dev); | |
372 | else if (ret) | |
b7cc9554 JR |
373 | goto out_free; |
374 | } | |
375 | ||
376 | return 0; | |
377 | ||
378 | out_free: | |
379 | ||
380 | amd_iommu_uninit_devices(); | |
381 | ||
382 | return ret; | |
383 | } | |
7f26508b JR |
384 | #ifdef CONFIG_AMD_IOMMU_STATS |
385 | ||
386 | /* | |
387 | * Initialization code for statistics collection | |
388 | */ | |
389 | ||
da49f6df | 390 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 391 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 392 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 393 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 394 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 395 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 396 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 397 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 398 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 399 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 400 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 401 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
402 | DECLARE_STATS_COUNTER(complete_ppr); |
403 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
404 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
405 | DECLARE_STATS_COUNTER(pri_requests); | |
406 | ||
da49f6df | 407 | |
7f26508b | 408 | static struct dentry *stats_dir; |
7f26508b JR |
409 | static struct dentry *de_fflush; |
410 | ||
411 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
412 | { | |
413 | if (stats_dir == NULL) | |
414 | return; | |
415 | ||
416 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
417 | &cnt->value); | |
418 | } | |
419 | ||
420 | static void amd_iommu_stats_init(void) | |
421 | { | |
422 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
423 | if (stats_dir == NULL) | |
424 | return; | |
425 | ||
7f26508b JR |
426 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
427 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
428 | |
429 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 430 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 431 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 432 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 433 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 434 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 435 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 436 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 437 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 438 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 439 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 440 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
441 | amd_iommu_stats_add(&complete_ppr); |
442 | amd_iommu_stats_add(&invalidate_iotlb); | |
443 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
444 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
445 | } |
446 | ||
447 | #endif | |
448 | ||
a80dc3e0 JR |
449 | /**************************************************************************** |
450 | * | |
451 | * Interrupt handling functions | |
452 | * | |
453 | ****************************************************************************/ | |
454 | ||
e3e59876 JR |
455 | static void dump_dte_entry(u16 devid) |
456 | { | |
457 | int i; | |
458 | ||
ee6c2868 JR |
459 | for (i = 0; i < 4; ++i) |
460 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
461 | amd_iommu_dev_table[devid].data[i]); |
462 | } | |
463 | ||
945b4ac4 JR |
464 | static void dump_command(unsigned long phys_addr) |
465 | { | |
466 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < 4; ++i) | |
470 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
471 | } | |
472 | ||
a345b23b | 473 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 474 | { |
3d06fca8 JR |
475 | int type, devid, domid, flags; |
476 | volatile u32 *event = __evt; | |
477 | int count = 0; | |
478 | u64 address; | |
479 | ||
480 | retry: | |
481 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
482 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
483 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
484 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
485 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
486 | ||
487 | if (type == 0) { | |
488 | /* Did we hit the erratum? */ | |
489 | if (++count == LOOP_TIMEOUT) { | |
490 | pr_err("AMD-Vi: No event written to event log\n"); | |
491 | return; | |
492 | } | |
493 | udelay(1); | |
494 | goto retry; | |
495 | } | |
90008ee4 | 496 | |
4c6f40d4 | 497 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
498 | |
499 | switch (type) { | |
500 | case EVENT_TYPE_ILL_DEV: | |
501 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
502 | "address=0x%016llx flags=0x%04x]\n", | |
503 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
504 | address, flags); | |
e3e59876 | 505 | dump_dte_entry(devid); |
90008ee4 JR |
506 | break; |
507 | case EVENT_TYPE_IO_FAULT: | |
508 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
509 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
510 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
511 | domid, address, flags); | |
512 | break; | |
513 | case EVENT_TYPE_DEV_TAB_ERR: | |
514 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
515 | "address=0x%016llx flags=0x%04x]\n", | |
516 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
517 | address, flags); | |
518 | break; | |
519 | case EVENT_TYPE_PAGE_TAB_ERR: | |
520 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
521 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
522 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
523 | domid, address, flags); | |
524 | break; | |
525 | case EVENT_TYPE_ILL_CMD: | |
526 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 527 | dump_command(address); |
90008ee4 JR |
528 | break; |
529 | case EVENT_TYPE_CMD_HARD_ERR: | |
530 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
531 | "flags=0x%04x]\n", address, flags); | |
532 | break; | |
533 | case EVENT_TYPE_IOTLB_INV_TO: | |
534 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
535 | "address=0x%016llx]\n", | |
536 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
537 | address); | |
538 | break; | |
539 | case EVENT_TYPE_INV_DEV_REQ: | |
540 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
541 | "address=0x%016llx flags=0x%04x]\n", | |
542 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
543 | address, flags); | |
544 | break; | |
545 | default: | |
546 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
547 | } | |
3d06fca8 JR |
548 | |
549 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
550 | } |
551 | ||
552 | static void iommu_poll_events(struct amd_iommu *iommu) | |
553 | { | |
554 | u32 head, tail; | |
555 | unsigned long flags; | |
556 | ||
557 | spin_lock_irqsave(&iommu->lock, flags); | |
558 | ||
559 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
560 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
561 | ||
562 | while (head != tail) { | |
a345b23b | 563 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
564 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
565 | } | |
566 | ||
567 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
568 | ||
569 | spin_unlock_irqrestore(&iommu->lock, flags); | |
570 | } | |
571 | ||
eee53537 | 572 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
573 | { |
574 | struct amd_iommu_fault fault; | |
72e1dcc4 | 575 | |
399be2f5 JR |
576 | INC_STATS_COUNTER(pri_requests); |
577 | ||
72e1dcc4 JR |
578 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
579 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
580 | return; | |
581 | } | |
582 | ||
583 | fault.address = raw[1]; | |
584 | fault.pasid = PPR_PASID(raw[0]); | |
585 | fault.device_id = PPR_DEVID(raw[0]); | |
586 | fault.tag = PPR_TAG(raw[0]); | |
587 | fault.flags = PPR_FLAGS(raw[0]); | |
588 | ||
72e1dcc4 JR |
589 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
590 | } | |
591 | ||
592 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
593 | { | |
594 | unsigned long flags; | |
595 | u32 head, tail; | |
596 | ||
597 | if (iommu->ppr_log == NULL) | |
598 | return; | |
599 | ||
eee53537 JR |
600 | /* enable ppr interrupts again */ |
601 | writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
602 | ||
72e1dcc4 JR |
603 | spin_lock_irqsave(&iommu->lock, flags); |
604 | ||
605 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
606 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
607 | ||
608 | while (head != tail) { | |
eee53537 JR |
609 | volatile u64 *raw; |
610 | u64 entry[2]; | |
611 | int i; | |
612 | ||
613 | raw = (u64 *)(iommu->ppr_log + head); | |
614 | ||
615 | /* | |
616 | * Hardware bug: Interrupt may arrive before the entry is | |
617 | * written to memory. If this happens we need to wait for the | |
618 | * entry to arrive. | |
619 | */ | |
620 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
621 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
622 | break; | |
623 | udelay(1); | |
624 | } | |
72e1dcc4 | 625 | |
eee53537 JR |
626 | /* Avoid memcpy function-call overhead */ |
627 | entry[0] = raw[0]; | |
628 | entry[1] = raw[1]; | |
72e1dcc4 | 629 | |
eee53537 JR |
630 | /* |
631 | * To detect the hardware bug we need to clear the entry | |
632 | * back to zero. | |
633 | */ | |
634 | raw[0] = raw[1] = 0UL; | |
635 | ||
636 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
637 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
638 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 JR |
639 | |
640 | /* | |
641 | * Release iommu->lock because ppr-handling might need to | |
642 | * re-aquire it | |
643 | */ | |
644 | spin_unlock_irqrestore(&iommu->lock, flags); | |
645 | ||
646 | /* Handle PPR entry */ | |
647 | iommu_handle_ppr_entry(iommu, entry); | |
648 | ||
649 | spin_lock_irqsave(&iommu->lock, flags); | |
650 | ||
651 | /* Refresh ring-buffer information */ | |
652 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
653 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
654 | } | |
655 | ||
72e1dcc4 JR |
656 | spin_unlock_irqrestore(&iommu->lock, flags); |
657 | } | |
658 | ||
72fe00f0 | 659 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 660 | { |
90008ee4 JR |
661 | struct amd_iommu *iommu; |
662 | ||
72e1dcc4 | 663 | for_each_iommu(iommu) { |
90008ee4 | 664 | iommu_poll_events(iommu); |
72e1dcc4 JR |
665 | iommu_poll_ppr_log(iommu); |
666 | } | |
90008ee4 JR |
667 | |
668 | return IRQ_HANDLED; | |
a80dc3e0 JR |
669 | } |
670 | ||
72fe00f0 JR |
671 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
672 | { | |
673 | return IRQ_WAKE_THREAD; | |
674 | } | |
675 | ||
431b2a20 JR |
676 | /**************************************************************************** |
677 | * | |
678 | * IOMMU command queuing functions | |
679 | * | |
680 | ****************************************************************************/ | |
681 | ||
ac0ea6e9 JR |
682 | static int wait_on_sem(volatile u64 *sem) |
683 | { | |
684 | int i = 0; | |
685 | ||
686 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
687 | udelay(1); | |
688 | i += 1; | |
689 | } | |
690 | ||
691 | if (i == LOOP_TIMEOUT) { | |
692 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
693 | return -EIO; | |
694 | } | |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
700 | struct iommu_cmd *cmd, | |
701 | u32 tail) | |
a19ae1ec | 702 | { |
a19ae1ec JR |
703 | u8 *target; |
704 | ||
8a7c5ef3 | 705 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
706 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
707 | ||
708 | /* Copy command to buffer */ | |
709 | memcpy(target, cmd, sizeof(*cmd)); | |
710 | ||
711 | /* Tell the IOMMU about it */ | |
a19ae1ec | 712 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 713 | } |
a19ae1ec | 714 | |
815b33fd | 715 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 716 | { |
815b33fd JR |
717 | WARN_ON(address & 0x7ULL); |
718 | ||
ded46737 | 719 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
720 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
721 | cmd->data[1] = upper_32_bits(__pa(address)); | |
722 | cmd->data[2] = 1; | |
ded46737 JR |
723 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
724 | } | |
725 | ||
94fe79e2 JR |
726 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
727 | { | |
728 | memset(cmd, 0, sizeof(*cmd)); | |
729 | cmd->data[0] = devid; | |
730 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
731 | } | |
732 | ||
11b6402c JR |
733 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
734 | size_t size, u16 domid, int pde) | |
735 | { | |
736 | u64 pages; | |
737 | int s; | |
738 | ||
739 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
740 | s = 0; | |
741 | ||
742 | if (pages > 1) { | |
743 | /* | |
744 | * If we have to flush more than one page, flush all | |
745 | * TLB entries for this domain | |
746 | */ | |
747 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
748 | s = 1; | |
749 | } | |
750 | ||
751 | address &= PAGE_MASK; | |
752 | ||
753 | memset(cmd, 0, sizeof(*cmd)); | |
754 | cmd->data[1] |= domid; | |
755 | cmd->data[2] = lower_32_bits(address); | |
756 | cmd->data[3] = upper_32_bits(address); | |
757 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
758 | if (s) /* size bit - we flush more than one 4kb page */ | |
759 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
760 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
761 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
762 | } | |
763 | ||
cb41ed85 JR |
764 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
765 | u64 address, size_t size) | |
766 | { | |
767 | u64 pages; | |
768 | int s; | |
769 | ||
770 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
771 | s = 0; | |
772 | ||
773 | if (pages > 1) { | |
774 | /* | |
775 | * If we have to flush more than one page, flush all | |
776 | * TLB entries for this domain | |
777 | */ | |
778 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
779 | s = 1; | |
780 | } | |
781 | ||
782 | address &= PAGE_MASK; | |
783 | ||
784 | memset(cmd, 0, sizeof(*cmd)); | |
785 | cmd->data[0] = devid; | |
786 | cmd->data[0] |= (qdep & 0xff) << 24; | |
787 | cmd->data[1] = devid; | |
788 | cmd->data[2] = lower_32_bits(address); | |
789 | cmd->data[3] = upper_32_bits(address); | |
790 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
791 | if (s) | |
792 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
793 | } | |
794 | ||
22e266c7 JR |
795 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
796 | u64 address, bool size) | |
797 | { | |
798 | memset(cmd, 0, sizeof(*cmd)); | |
799 | ||
800 | address &= ~(0xfffULL); | |
801 | ||
802 | cmd->data[0] = pasid & PASID_MASK; | |
803 | cmd->data[1] = domid; | |
804 | cmd->data[2] = lower_32_bits(address); | |
805 | cmd->data[3] = upper_32_bits(address); | |
806 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
807 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
808 | if (size) | |
809 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
810 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
811 | } | |
812 | ||
813 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
814 | int qdep, u64 address, bool size) | |
815 | { | |
816 | memset(cmd, 0, sizeof(*cmd)); | |
817 | ||
818 | address &= ~(0xfffULL); | |
819 | ||
820 | cmd->data[0] = devid; | |
821 | cmd->data[0] |= (pasid & 0xff) << 16; | |
822 | cmd->data[0] |= (qdep & 0xff) << 24; | |
823 | cmd->data[1] = devid; | |
824 | cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16; | |
825 | cmd->data[2] = lower_32_bits(address); | |
826 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
827 | cmd->data[3] = upper_32_bits(address); | |
828 | if (size) | |
829 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
830 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
831 | } | |
832 | ||
c99afa25 JR |
833 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
834 | int status, int tag, bool gn) | |
835 | { | |
836 | memset(cmd, 0, sizeof(*cmd)); | |
837 | ||
838 | cmd->data[0] = devid; | |
839 | if (gn) { | |
840 | cmd->data[1] = pasid & PASID_MASK; | |
841 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; | |
842 | } | |
843 | cmd->data[3] = tag & 0x1ff; | |
844 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
845 | ||
846 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
847 | } | |
848 | ||
58fc7f14 JR |
849 | static void build_inv_all(struct iommu_cmd *cmd) |
850 | { | |
851 | memset(cmd, 0, sizeof(*cmd)); | |
852 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
853 | } |
854 | ||
431b2a20 | 855 | /* |
431b2a20 | 856 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 857 | * hardware about the new command. |
431b2a20 | 858 | */ |
f1ca1512 JR |
859 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
860 | struct iommu_cmd *cmd, | |
861 | bool sync) | |
a19ae1ec | 862 | { |
ac0ea6e9 | 863 | u32 left, tail, head, next_tail; |
a19ae1ec | 864 | unsigned long flags; |
a19ae1ec | 865 | |
549c90dc | 866 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
867 | |
868 | again: | |
a19ae1ec | 869 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 870 | |
ac0ea6e9 JR |
871 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
872 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
873 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
874 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 875 | |
ac0ea6e9 JR |
876 | if (left <= 2) { |
877 | struct iommu_cmd sync_cmd; | |
878 | volatile u64 sem = 0; | |
879 | int ret; | |
8d201968 | 880 | |
ac0ea6e9 JR |
881 | build_completion_wait(&sync_cmd, (u64)&sem); |
882 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 883 | |
ac0ea6e9 JR |
884 | spin_unlock_irqrestore(&iommu->lock, flags); |
885 | ||
886 | if ((ret = wait_on_sem(&sem)) != 0) | |
887 | return ret; | |
888 | ||
889 | goto again; | |
8d201968 JR |
890 | } |
891 | ||
ac0ea6e9 JR |
892 | copy_cmd_to_buffer(iommu, cmd, tail); |
893 | ||
894 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 895 | iommu->need_sync = sync; |
ac0ea6e9 | 896 | |
a19ae1ec | 897 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 898 | |
815b33fd | 899 | return 0; |
8d201968 JR |
900 | } |
901 | ||
f1ca1512 JR |
902 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
903 | { | |
904 | return iommu_queue_command_sync(iommu, cmd, true); | |
905 | } | |
906 | ||
8d201968 JR |
907 | /* |
908 | * This function queues a completion wait command into the command | |
909 | * buffer of an IOMMU | |
910 | */ | |
a19ae1ec | 911 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
912 | { |
913 | struct iommu_cmd cmd; | |
815b33fd | 914 | volatile u64 sem = 0; |
ac0ea6e9 | 915 | int ret; |
8d201968 | 916 | |
09ee17eb | 917 | if (!iommu->need_sync) |
815b33fd | 918 | return 0; |
09ee17eb | 919 | |
815b33fd | 920 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 921 | |
f1ca1512 | 922 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 923 | if (ret) |
815b33fd | 924 | return ret; |
8d201968 | 925 | |
ac0ea6e9 | 926 | return wait_on_sem(&sem); |
8d201968 JR |
927 | } |
928 | ||
d8c13085 | 929 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 930 | { |
d8c13085 | 931 | struct iommu_cmd cmd; |
a19ae1ec | 932 | |
d8c13085 | 933 | build_inv_dte(&cmd, devid); |
7e4f88da | 934 | |
d8c13085 JR |
935 | return iommu_queue_command(iommu, &cmd); |
936 | } | |
09ee17eb | 937 | |
7d0c5cc5 JR |
938 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
939 | { | |
940 | u32 devid; | |
09ee17eb | 941 | |
7d0c5cc5 JR |
942 | for (devid = 0; devid <= 0xffff; ++devid) |
943 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 944 | |
7d0c5cc5 JR |
945 | iommu_completion_wait(iommu); |
946 | } | |
84df8175 | 947 | |
7d0c5cc5 JR |
948 | /* |
949 | * This function uses heavy locking and may disable irqs for some time. But | |
950 | * this is no issue because it is only called during resume. | |
951 | */ | |
952 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
953 | { | |
954 | u32 dom_id; | |
a19ae1ec | 955 | |
7d0c5cc5 JR |
956 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
957 | struct iommu_cmd cmd; | |
958 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
959 | dom_id, 1); | |
960 | iommu_queue_command(iommu, &cmd); | |
961 | } | |
8eed9833 | 962 | |
7d0c5cc5 | 963 | iommu_completion_wait(iommu); |
a19ae1ec JR |
964 | } |
965 | ||
58fc7f14 | 966 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 967 | { |
58fc7f14 | 968 | struct iommu_cmd cmd; |
0518a3a4 | 969 | |
58fc7f14 | 970 | build_inv_all(&cmd); |
0518a3a4 | 971 | |
58fc7f14 JR |
972 | iommu_queue_command(iommu, &cmd); |
973 | iommu_completion_wait(iommu); | |
974 | } | |
975 | ||
7d0c5cc5 JR |
976 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
977 | { | |
58fc7f14 JR |
978 | if (iommu_feature(iommu, FEATURE_IA)) { |
979 | iommu_flush_all(iommu); | |
980 | } else { | |
981 | iommu_flush_dte_all(iommu); | |
982 | iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
983 | } |
984 | } | |
985 | ||
431b2a20 | 986 | /* |
cb41ed85 | 987 | * Command send function for flushing on-device TLB |
431b2a20 | 988 | */ |
6c542047 JR |
989 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
990 | u64 address, size_t size) | |
3fa43655 JR |
991 | { |
992 | struct amd_iommu *iommu; | |
b00d3bcf | 993 | struct iommu_cmd cmd; |
cb41ed85 | 994 | int qdep; |
3fa43655 | 995 | |
ea61cddb JR |
996 | qdep = dev_data->ats.qdep; |
997 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 998 | |
ea61cddb | 999 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1000 | |
1001 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1002 | } |
1003 | ||
431b2a20 | 1004 | /* |
431b2a20 | 1005 | * Command send function for invalidating a device table entry |
431b2a20 | 1006 | */ |
6c542047 | 1007 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1008 | { |
3fa43655 | 1009 | struct amd_iommu *iommu; |
ee2fa743 | 1010 | int ret; |
a19ae1ec | 1011 | |
6c542047 | 1012 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1013 | |
f62dda66 | 1014 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1015 | if (ret) |
1016 | return ret; | |
1017 | ||
ea61cddb | 1018 | if (dev_data->ats.enabled) |
6c542047 | 1019 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1020 | |
ee2fa743 | 1021 | return ret; |
a19ae1ec JR |
1022 | } |
1023 | ||
431b2a20 JR |
1024 | /* |
1025 | * TLB invalidation function which is called from the mapping functions. | |
1026 | * It invalidates a single PTE if the range to flush is within a single | |
1027 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1028 | */ | |
17b124bf JR |
1029 | static void __domain_flush_pages(struct protection_domain *domain, |
1030 | u64 address, size_t size, int pde) | |
a19ae1ec | 1031 | { |
cb41ed85 | 1032 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1033 | struct iommu_cmd cmd; |
1034 | int ret = 0, i; | |
a19ae1ec | 1035 | |
11b6402c | 1036 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1037 | |
6de8ad9b JR |
1038 | for (i = 0; i < amd_iommus_present; ++i) { |
1039 | if (!domain->dev_iommu[i]) | |
1040 | continue; | |
1041 | ||
1042 | /* | |
1043 | * Devices of this domain are behind this IOMMU | |
1044 | * We need a TLB flush | |
1045 | */ | |
11b6402c | 1046 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1047 | } |
1048 | ||
cb41ed85 | 1049 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1050 | |
ea61cddb | 1051 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1052 | continue; |
1053 | ||
6c542047 | 1054 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1055 | } |
1056 | ||
11b6402c | 1057 | WARN_ON(ret); |
6de8ad9b JR |
1058 | } |
1059 | ||
17b124bf JR |
1060 | static void domain_flush_pages(struct protection_domain *domain, |
1061 | u64 address, size_t size) | |
6de8ad9b | 1062 | { |
17b124bf | 1063 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1064 | } |
b6c02715 | 1065 | |
1c655773 | 1066 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1067 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1068 | { |
17b124bf | 1069 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1070 | } |
1071 | ||
42a49f96 | 1072 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1073 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1074 | { |
17b124bf | 1075 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1076 | } |
1077 | ||
17b124bf | 1078 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1079 | { |
17b124bf | 1080 | int i; |
18811f55 | 1081 | |
17b124bf JR |
1082 | for (i = 0; i < amd_iommus_present; ++i) { |
1083 | if (!domain->dev_iommu[i]) | |
1084 | continue; | |
bfd1be18 | 1085 | |
17b124bf JR |
1086 | /* |
1087 | * Devices of this domain are behind this IOMMU | |
1088 | * We need to wait for completion of all commands. | |
1089 | */ | |
1090 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1091 | } |
e394d72a JR |
1092 | } |
1093 | ||
b00d3bcf | 1094 | |
09b42804 | 1095 | /* |
b00d3bcf | 1096 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1097 | */ |
17b124bf | 1098 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1099 | { |
b00d3bcf | 1100 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1101 | |
b00d3bcf | 1102 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1103 | device_flush_dte(dev_data); |
a345b23b JR |
1104 | } |
1105 | ||
431b2a20 JR |
1106 | /**************************************************************************** |
1107 | * | |
1108 | * The functions below are used the create the page table mappings for | |
1109 | * unity mapped regions. | |
1110 | * | |
1111 | ****************************************************************************/ | |
1112 | ||
308973d3 JR |
1113 | /* |
1114 | * This function is used to add another level to an IO page table. Adding | |
1115 | * another level increases the size of the address space by 9 bits to a size up | |
1116 | * to 64 bits. | |
1117 | */ | |
1118 | static bool increase_address_space(struct protection_domain *domain, | |
1119 | gfp_t gfp) | |
1120 | { | |
1121 | u64 *pte; | |
1122 | ||
1123 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1124 | /* address space already 64 bit large */ | |
1125 | return false; | |
1126 | ||
1127 | pte = (void *)get_zeroed_page(gfp); | |
1128 | if (!pte) | |
1129 | return false; | |
1130 | ||
1131 | *pte = PM_LEVEL_PDE(domain->mode, | |
1132 | virt_to_phys(domain->pt_root)); | |
1133 | domain->pt_root = pte; | |
1134 | domain->mode += 1; | |
1135 | domain->updated = true; | |
1136 | ||
1137 | return true; | |
1138 | } | |
1139 | ||
1140 | static u64 *alloc_pte(struct protection_domain *domain, | |
1141 | unsigned long address, | |
cbb9d729 | 1142 | unsigned long page_size, |
308973d3 JR |
1143 | u64 **pte_page, |
1144 | gfp_t gfp) | |
1145 | { | |
cbb9d729 | 1146 | int level, end_lvl; |
308973d3 | 1147 | u64 *pte, *page; |
cbb9d729 JR |
1148 | |
1149 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1150 | |
1151 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1152 | increase_address_space(domain, gfp); | |
1153 | ||
cbb9d729 JR |
1154 | level = domain->mode - 1; |
1155 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1156 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1157 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1158 | |
1159 | while (level > end_lvl) { | |
1160 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1161 | page = (u64 *)get_zeroed_page(gfp); | |
1162 | if (!page) | |
1163 | return NULL; | |
1164 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1165 | } | |
1166 | ||
cbb9d729 JR |
1167 | /* No level skipping support yet */ |
1168 | if (PM_PTE_LEVEL(*pte) != level) | |
1169 | return NULL; | |
1170 | ||
308973d3 JR |
1171 | level -= 1; |
1172 | ||
1173 | pte = IOMMU_PTE_PAGE(*pte); | |
1174 | ||
1175 | if (pte_page && level == end_lvl) | |
1176 | *pte_page = pte; | |
1177 | ||
1178 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1179 | } | |
1180 | ||
1181 | return pte; | |
1182 | } | |
1183 | ||
1184 | /* | |
1185 | * This function checks if there is a PTE for a given dma address. If | |
1186 | * there is one, it returns the pointer to it. | |
1187 | */ | |
24cd7723 | 1188 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1189 | { |
1190 | int level; | |
1191 | u64 *pte; | |
1192 | ||
24cd7723 JR |
1193 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1194 | return NULL; | |
1195 | ||
1196 | level = domain->mode - 1; | |
1197 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1198 | |
24cd7723 JR |
1199 | while (level > 0) { |
1200 | ||
1201 | /* Not Present */ | |
308973d3 JR |
1202 | if (!IOMMU_PTE_PRESENT(*pte)) |
1203 | return NULL; | |
1204 | ||
24cd7723 JR |
1205 | /* Large PTE */ |
1206 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1207 | unsigned long pte_mask, __pte; | |
1208 | ||
1209 | /* | |
1210 | * If we have a series of large PTEs, make | |
1211 | * sure to return a pointer to the first one. | |
1212 | */ | |
1213 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1214 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1215 | __pte = ((unsigned long)pte) & pte_mask; | |
1216 | ||
1217 | return (u64 *)__pte; | |
1218 | } | |
1219 | ||
1220 | /* No level skipping support yet */ | |
1221 | if (PM_PTE_LEVEL(*pte) != level) | |
1222 | return NULL; | |
1223 | ||
308973d3 JR |
1224 | level -= 1; |
1225 | ||
24cd7723 | 1226 | /* Walk to the next level */ |
308973d3 JR |
1227 | pte = IOMMU_PTE_PAGE(*pte); |
1228 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1229 | } |
1230 | ||
1231 | return pte; | |
1232 | } | |
1233 | ||
431b2a20 JR |
1234 | /* |
1235 | * Generic mapping functions. It maps a physical address into a DMA | |
1236 | * address space. It allocates the page table pages if necessary. | |
1237 | * In the future it can be extended to a generic mapping function | |
1238 | * supporting all features of AMD IOMMU page tables like level skipping | |
1239 | * and full 64 bit address spaces. | |
1240 | */ | |
38e817fe JR |
1241 | static int iommu_map_page(struct protection_domain *dom, |
1242 | unsigned long bus_addr, | |
1243 | unsigned long phys_addr, | |
abdc5eb3 | 1244 | int prot, |
cbb9d729 | 1245 | unsigned long page_size) |
bd0e5211 | 1246 | { |
8bda3092 | 1247 | u64 __pte, *pte; |
cbb9d729 | 1248 | int i, count; |
abdc5eb3 | 1249 | |
bad1cac2 | 1250 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1251 | return -EINVAL; |
1252 | ||
cbb9d729 JR |
1253 | bus_addr = PAGE_ALIGN(bus_addr); |
1254 | phys_addr = PAGE_ALIGN(phys_addr); | |
1255 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1256 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1257 | ||
1258 | for (i = 0; i < count; ++i) | |
1259 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1260 | return -EBUSY; | |
bd0e5211 | 1261 | |
cbb9d729 JR |
1262 | if (page_size > PAGE_SIZE) { |
1263 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1264 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1265 | } else | |
1266 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1267 | |
bd0e5211 JR |
1268 | if (prot & IOMMU_PROT_IR) |
1269 | __pte |= IOMMU_PTE_IR; | |
1270 | if (prot & IOMMU_PROT_IW) | |
1271 | __pte |= IOMMU_PTE_IW; | |
1272 | ||
cbb9d729 JR |
1273 | for (i = 0; i < count; ++i) |
1274 | pte[i] = __pte; | |
bd0e5211 | 1275 | |
04bfdd84 JR |
1276 | update_domain(dom); |
1277 | ||
bd0e5211 JR |
1278 | return 0; |
1279 | } | |
1280 | ||
24cd7723 JR |
1281 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1282 | unsigned long bus_addr, | |
1283 | unsigned long page_size) | |
eb74ff6c | 1284 | { |
24cd7723 JR |
1285 | unsigned long long unmap_size, unmapped; |
1286 | u64 *pte; | |
1287 | ||
1288 | BUG_ON(!is_power_of_2(page_size)); | |
1289 | ||
1290 | unmapped = 0; | |
eb74ff6c | 1291 | |
24cd7723 JR |
1292 | while (unmapped < page_size) { |
1293 | ||
1294 | pte = fetch_pte(dom, bus_addr); | |
1295 | ||
1296 | if (!pte) { | |
1297 | /* | |
1298 | * No PTE for this address | |
1299 | * move forward in 4kb steps | |
1300 | */ | |
1301 | unmap_size = PAGE_SIZE; | |
1302 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1303 | /* 4kb PTE found for this address */ | |
1304 | unmap_size = PAGE_SIZE; | |
1305 | *pte = 0ULL; | |
1306 | } else { | |
1307 | int count, i; | |
1308 | ||
1309 | /* Large PTE found which maps this address */ | |
1310 | unmap_size = PTE_PAGE_SIZE(*pte); | |
1311 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
1312 | for (i = 0; i < count; i++) | |
1313 | pte[i] = 0ULL; | |
1314 | } | |
1315 | ||
1316 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1317 | unmapped += unmap_size; | |
1318 | } | |
1319 | ||
1320 | BUG_ON(!is_power_of_2(unmapped)); | |
eb74ff6c | 1321 | |
24cd7723 | 1322 | return unmapped; |
eb74ff6c | 1323 | } |
eb74ff6c | 1324 | |
431b2a20 JR |
1325 | /* |
1326 | * This function checks if a specific unity mapping entry is needed for | |
1327 | * this specific IOMMU. | |
1328 | */ | |
bd0e5211 JR |
1329 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1330 | struct unity_map_entry *entry) | |
1331 | { | |
1332 | u16 bdf, i; | |
1333 | ||
1334 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1335 | bdf = amd_iommu_alias_table[i]; | |
1336 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1337 | return 1; | |
1338 | } | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
431b2a20 JR |
1343 | /* |
1344 | * This function actually applies the mapping to the page table of the | |
1345 | * dma_ops domain. | |
1346 | */ | |
bd0e5211 JR |
1347 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1348 | struct unity_map_entry *e) | |
1349 | { | |
1350 | u64 addr; | |
1351 | int ret; | |
1352 | ||
1353 | for (addr = e->address_start; addr < e->address_end; | |
1354 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1355 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1356 | PAGE_SIZE); |
bd0e5211 JR |
1357 | if (ret) |
1358 | return ret; | |
1359 | /* | |
1360 | * if unity mapping is in aperture range mark the page | |
1361 | * as allocated in the aperture | |
1362 | */ | |
1363 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1364 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1365 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1366 | } |
1367 | ||
1368 | return 0; | |
1369 | } | |
1370 | ||
171e7b37 JR |
1371 | /* |
1372 | * Init the unity mappings for a specific IOMMU in the system | |
1373 | * | |
1374 | * Basically iterates over all unity mapping entries and applies them to | |
1375 | * the default domain DMA of that IOMMU if necessary. | |
1376 | */ | |
1377 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1378 | { | |
1379 | struct unity_map_entry *entry; | |
1380 | int ret; | |
1381 | ||
1382 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1383 | if (!iommu_for_unity_map(iommu, entry)) | |
1384 | continue; | |
1385 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1386 | if (ret) | |
1387 | return ret; | |
1388 | } | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
431b2a20 JR |
1393 | /* |
1394 | * Inits the unity mappings required for a specific device | |
1395 | */ | |
bd0e5211 JR |
1396 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1397 | u16 devid) | |
1398 | { | |
1399 | struct unity_map_entry *e; | |
1400 | int ret; | |
1401 | ||
1402 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1403 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1404 | continue; | |
1405 | ret = dma_ops_unity_map(dma_dom, e); | |
1406 | if (ret) | |
1407 | return ret; | |
1408 | } | |
1409 | ||
1410 | return 0; | |
1411 | } | |
1412 | ||
431b2a20 JR |
1413 | /**************************************************************************** |
1414 | * | |
1415 | * The next functions belong to the address allocator for the dma_ops | |
1416 | * interface functions. They work like the allocators in the other IOMMU | |
1417 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1418 | * the aperture. Maybe it could be enhanced in the future to a more | |
1419 | * efficient allocator. | |
1420 | * | |
1421 | ****************************************************************************/ | |
d3086444 | 1422 | |
431b2a20 | 1423 | /* |
384de729 | 1424 | * The address allocator core functions. |
431b2a20 JR |
1425 | * |
1426 | * called with domain->lock held | |
1427 | */ | |
384de729 | 1428 | |
171e7b37 JR |
1429 | /* |
1430 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1431 | * ranges. | |
1432 | */ | |
1433 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1434 | unsigned long start_page, | |
1435 | unsigned int pages) | |
1436 | { | |
1437 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1438 | ||
1439 | if (start_page + pages > last_page) | |
1440 | pages = last_page - start_page; | |
1441 | ||
1442 | for (i = start_page; i < start_page + pages; ++i) { | |
1443 | int index = i / APERTURE_RANGE_PAGES; | |
1444 | int page = i % APERTURE_RANGE_PAGES; | |
1445 | __set_bit(page, dom->aperture[index]->bitmap); | |
1446 | } | |
1447 | } | |
1448 | ||
9cabe89b JR |
1449 | /* |
1450 | * This function is used to add a new aperture range to an existing | |
1451 | * aperture in case of dma_ops domain allocation or address allocation | |
1452 | * failure. | |
1453 | */ | |
576175c2 | 1454 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1455 | bool populate, gfp_t gfp) |
1456 | { | |
1457 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1458 | struct amd_iommu *iommu; |
17f5b569 | 1459 | unsigned long i, old_size; |
9cabe89b | 1460 | |
f5e9705c JR |
1461 | #ifdef CONFIG_IOMMU_STRESS |
1462 | populate = false; | |
1463 | #endif | |
1464 | ||
9cabe89b JR |
1465 | if (index >= APERTURE_MAX_RANGES) |
1466 | return -ENOMEM; | |
1467 | ||
1468 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1469 | if (!dma_dom->aperture[index]) | |
1470 | return -ENOMEM; | |
1471 | ||
1472 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1473 | if (!dma_dom->aperture[index]->bitmap) | |
1474 | goto out_free; | |
1475 | ||
1476 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1477 | ||
1478 | if (populate) { | |
1479 | unsigned long address = dma_dom->aperture_size; | |
1480 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1481 | u64 *pte, *pte_page; | |
1482 | ||
1483 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1484 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1485 | &pte_page, gfp); |
1486 | if (!pte) | |
1487 | goto out_free; | |
1488 | ||
1489 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1490 | ||
1491 | address += APERTURE_RANGE_SIZE / 64; | |
1492 | } | |
1493 | } | |
1494 | ||
17f5b569 | 1495 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1496 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1497 | ||
17f5b569 JR |
1498 | /* Reserve address range used for MSI messages */ |
1499 | if (old_size < MSI_ADDR_BASE_LO && | |
1500 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1501 | unsigned long spage; | |
1502 | int pages; | |
1503 | ||
1504 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1505 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1506 | ||
1507 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1508 | } | |
1509 | ||
b595076a | 1510 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1511 | for_each_iommu(iommu) { |
1512 | if (iommu->exclusion_start && | |
1513 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1514 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1515 | unsigned long startpage; | |
1516 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1517 | iommu->exclusion_length, | |
1518 | PAGE_SIZE); | |
1519 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1520 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1521 | } | |
00cd122a JR |
1522 | } |
1523 | ||
1524 | /* | |
1525 | * Check for areas already mapped as present in the new aperture | |
1526 | * range and mark those pages as reserved in the allocator. Such | |
1527 | * mappings may already exist as a result of requested unity | |
1528 | * mappings for devices. | |
1529 | */ | |
1530 | for (i = dma_dom->aperture[index]->offset; | |
1531 | i < dma_dom->aperture_size; | |
1532 | i += PAGE_SIZE) { | |
24cd7723 | 1533 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1534 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1535 | continue; | |
1536 | ||
fcd0861d | 1537 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1538 | } |
1539 | ||
04bfdd84 JR |
1540 | update_domain(&dma_dom->domain); |
1541 | ||
9cabe89b JR |
1542 | return 0; |
1543 | ||
1544 | out_free: | |
04bfdd84 JR |
1545 | update_domain(&dma_dom->domain); |
1546 | ||
9cabe89b JR |
1547 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1548 | ||
1549 | kfree(dma_dom->aperture[index]); | |
1550 | dma_dom->aperture[index] = NULL; | |
1551 | ||
1552 | return -ENOMEM; | |
1553 | } | |
1554 | ||
384de729 JR |
1555 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1556 | struct dma_ops_domain *dom, | |
1557 | unsigned int pages, | |
1558 | unsigned long align_mask, | |
1559 | u64 dma_mask, | |
1560 | unsigned long start) | |
1561 | { | |
803b8cb4 | 1562 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1563 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1564 | int i = start >> APERTURE_RANGE_SHIFT; | |
1565 | unsigned long boundary_size; | |
1566 | unsigned long address = -1; | |
1567 | unsigned long limit; | |
1568 | ||
803b8cb4 JR |
1569 | next_bit >>= PAGE_SHIFT; |
1570 | ||
384de729 JR |
1571 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1572 | PAGE_SIZE) >> PAGE_SHIFT; | |
1573 | ||
1574 | for (;i < max_index; ++i) { | |
1575 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1576 | ||
1577 | if (dom->aperture[i]->offset >= dma_mask) | |
1578 | break; | |
1579 | ||
1580 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1581 | dma_mask >> PAGE_SHIFT); | |
1582 | ||
1583 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1584 | limit, next_bit, pages, 0, | |
1585 | boundary_size, align_mask); | |
1586 | if (address != -1) { | |
1587 | address = dom->aperture[i]->offset + | |
1588 | (address << PAGE_SHIFT); | |
803b8cb4 | 1589 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1590 | break; |
1591 | } | |
1592 | ||
1593 | next_bit = 0; | |
1594 | } | |
1595 | ||
1596 | return address; | |
1597 | } | |
1598 | ||
d3086444 JR |
1599 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1600 | struct dma_ops_domain *dom, | |
6d4f343f | 1601 | unsigned int pages, |
832a90c3 JR |
1602 | unsigned long align_mask, |
1603 | u64 dma_mask) | |
d3086444 | 1604 | { |
d3086444 | 1605 | unsigned long address; |
d3086444 | 1606 | |
fe16f088 JR |
1607 | #ifdef CONFIG_IOMMU_STRESS |
1608 | dom->next_address = 0; | |
1609 | dom->need_flush = true; | |
1610 | #endif | |
d3086444 | 1611 | |
384de729 | 1612 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1613 | dma_mask, dom->next_address); |
d3086444 | 1614 | |
1c655773 | 1615 | if (address == -1) { |
803b8cb4 | 1616 | dom->next_address = 0; |
384de729 JR |
1617 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1618 | dma_mask, 0); | |
1c655773 JR |
1619 | dom->need_flush = true; |
1620 | } | |
d3086444 | 1621 | |
384de729 | 1622 | if (unlikely(address == -1)) |
8fd524b3 | 1623 | address = DMA_ERROR_CODE; |
d3086444 JR |
1624 | |
1625 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1626 | ||
1627 | return address; | |
1628 | } | |
1629 | ||
431b2a20 JR |
1630 | /* |
1631 | * The address free function. | |
1632 | * | |
1633 | * called with domain->lock held | |
1634 | */ | |
d3086444 JR |
1635 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1636 | unsigned long address, | |
1637 | unsigned int pages) | |
1638 | { | |
384de729 JR |
1639 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1640 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1641 | |
384de729 JR |
1642 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1643 | ||
47bccd6b JR |
1644 | #ifdef CONFIG_IOMMU_STRESS |
1645 | if (i < 4) | |
1646 | return; | |
1647 | #endif | |
80be308d | 1648 | |
803b8cb4 | 1649 | if (address >= dom->next_address) |
80be308d | 1650 | dom->need_flush = true; |
384de729 JR |
1651 | |
1652 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1653 | |
a66022c4 | 1654 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1655 | |
d3086444 JR |
1656 | } |
1657 | ||
431b2a20 JR |
1658 | /**************************************************************************** |
1659 | * | |
1660 | * The next functions belong to the domain allocation. A domain is | |
1661 | * allocated for every IOMMU as the default domain. If device isolation | |
1662 | * is enabled, every device get its own domain. The most important thing | |
1663 | * about domains is the page table mapping the DMA address space they | |
1664 | * contain. | |
1665 | * | |
1666 | ****************************************************************************/ | |
1667 | ||
aeb26f55 JR |
1668 | /* |
1669 | * This function adds a protection domain to the global protection domain list | |
1670 | */ | |
1671 | static void add_domain_to_list(struct protection_domain *domain) | |
1672 | { | |
1673 | unsigned long flags; | |
1674 | ||
1675 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1676 | list_add(&domain->list, &amd_iommu_pd_list); | |
1677 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1678 | } | |
1679 | ||
1680 | /* | |
1681 | * This function removes a protection domain to the global | |
1682 | * protection domain list | |
1683 | */ | |
1684 | static void del_domain_from_list(struct protection_domain *domain) | |
1685 | { | |
1686 | unsigned long flags; | |
1687 | ||
1688 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1689 | list_del(&domain->list); | |
1690 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1691 | } | |
1692 | ||
ec487d1a JR |
1693 | static u16 domain_id_alloc(void) |
1694 | { | |
1695 | unsigned long flags; | |
1696 | int id; | |
1697 | ||
1698 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1699 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1700 | BUG_ON(id == 0); | |
1701 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1702 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1703 | else | |
1704 | id = 0; | |
1705 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1706 | ||
1707 | return id; | |
1708 | } | |
1709 | ||
a2acfb75 JR |
1710 | static void domain_id_free(int id) |
1711 | { | |
1712 | unsigned long flags; | |
1713 | ||
1714 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1715 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1716 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1717 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1718 | } | |
a2acfb75 | 1719 | |
86db2e5d | 1720 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1721 | { |
1722 | int i, j; | |
1723 | u64 *p1, *p2, *p3; | |
1724 | ||
86db2e5d | 1725 | p1 = domain->pt_root; |
ec487d1a JR |
1726 | |
1727 | if (!p1) | |
1728 | return; | |
1729 | ||
1730 | for (i = 0; i < 512; ++i) { | |
1731 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1732 | continue; | |
1733 | ||
1734 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1735 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1736 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1737 | continue; | |
1738 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1739 | free_page((unsigned long)p3); | |
1740 | } | |
1741 | ||
1742 | free_page((unsigned long)p2); | |
1743 | } | |
1744 | ||
1745 | free_page((unsigned long)p1); | |
86db2e5d JR |
1746 | |
1747 | domain->pt_root = NULL; | |
ec487d1a JR |
1748 | } |
1749 | ||
b16137b1 JR |
1750 | static void free_gcr3_tbl_level1(u64 *tbl) |
1751 | { | |
1752 | u64 *ptr; | |
1753 | int i; | |
1754 | ||
1755 | for (i = 0; i < 512; ++i) { | |
1756 | if (!(tbl[i] & GCR3_VALID)) | |
1757 | continue; | |
1758 | ||
1759 | ptr = __va(tbl[i] & PAGE_MASK); | |
1760 | ||
1761 | free_page((unsigned long)ptr); | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1766 | { | |
1767 | u64 *ptr; | |
1768 | int i; | |
1769 | ||
1770 | for (i = 0; i < 512; ++i) { | |
1771 | if (!(tbl[i] & GCR3_VALID)) | |
1772 | continue; | |
1773 | ||
1774 | ptr = __va(tbl[i] & PAGE_MASK); | |
1775 | ||
1776 | free_gcr3_tbl_level1(ptr); | |
1777 | } | |
1778 | } | |
1779 | ||
52815b75 JR |
1780 | static void free_gcr3_table(struct protection_domain *domain) |
1781 | { | |
b16137b1 JR |
1782 | if (domain->glx == 2) |
1783 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1784 | else if (domain->glx == 1) | |
1785 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
1786 | else if (domain->glx != 0) | |
1787 | BUG(); | |
1788 | ||
52815b75 JR |
1789 | free_page((unsigned long)domain->gcr3_tbl); |
1790 | } | |
1791 | ||
431b2a20 JR |
1792 | /* |
1793 | * Free a domain, only used if something went wrong in the | |
1794 | * allocation path and we need to free an already allocated page table | |
1795 | */ | |
ec487d1a JR |
1796 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1797 | { | |
384de729 JR |
1798 | int i; |
1799 | ||
ec487d1a JR |
1800 | if (!dom) |
1801 | return; | |
1802 | ||
aeb26f55 JR |
1803 | del_domain_from_list(&dom->domain); |
1804 | ||
86db2e5d | 1805 | free_pagetable(&dom->domain); |
ec487d1a | 1806 | |
384de729 JR |
1807 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1808 | if (!dom->aperture[i]) | |
1809 | continue; | |
1810 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1811 | kfree(dom->aperture[i]); | |
1812 | } | |
ec487d1a JR |
1813 | |
1814 | kfree(dom); | |
1815 | } | |
1816 | ||
431b2a20 JR |
1817 | /* |
1818 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1819 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1820 | * structures required for the dma_ops interface |
1821 | */ | |
87a64d52 | 1822 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1823 | { |
1824 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1825 | |
1826 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1827 | if (!dma_dom) | |
1828 | return NULL; | |
1829 | ||
1830 | spin_lock_init(&dma_dom->domain.lock); | |
1831 | ||
1832 | dma_dom->domain.id = domain_id_alloc(); | |
1833 | if (dma_dom->domain.id == 0) | |
1834 | goto free_dma_dom; | |
7c392cbe | 1835 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 1836 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1837 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1838 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1839 | dma_dom->domain.priv = dma_dom; |
1840 | if (!dma_dom->domain.pt_root) | |
1841 | goto free_dma_dom; | |
ec487d1a | 1842 | |
1c655773 | 1843 | dma_dom->need_flush = false; |
bd60b735 | 1844 | dma_dom->target_dev = 0xffff; |
1c655773 | 1845 | |
aeb26f55 JR |
1846 | add_domain_to_list(&dma_dom->domain); |
1847 | ||
576175c2 | 1848 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1849 | goto free_dma_dom; |
ec487d1a | 1850 | |
431b2a20 | 1851 | /* |
ec487d1a JR |
1852 | * mark the first page as allocated so we never return 0 as |
1853 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1854 | */ |
384de729 | 1855 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1856 | dma_dom->next_address = 0; |
ec487d1a | 1857 | |
ec487d1a JR |
1858 | |
1859 | return dma_dom; | |
1860 | ||
1861 | free_dma_dom: | |
1862 | dma_ops_domain_free(dma_dom); | |
1863 | ||
1864 | return NULL; | |
1865 | } | |
1866 | ||
5b28df6f JR |
1867 | /* |
1868 | * little helper function to check whether a given protection domain is a | |
1869 | * dma_ops domain | |
1870 | */ | |
1871 | static bool dma_ops_domain(struct protection_domain *domain) | |
1872 | { | |
1873 | return domain->flags & PD_DMA_OPS_MASK; | |
1874 | } | |
1875 | ||
fd7b5535 | 1876 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1877 | { |
132bd68f | 1878 | u64 pte_root = 0; |
ee6c2868 | 1879 | u64 flags = 0; |
863c74eb | 1880 | |
132bd68f JR |
1881 | if (domain->mode != PAGE_MODE_NONE) |
1882 | pte_root = virt_to_phys(domain->pt_root); | |
1883 | ||
38ddf41b JR |
1884 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1885 | << DEV_ENTRY_MODE_SHIFT; | |
1886 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1887 | |
ee6c2868 JR |
1888 | flags = amd_iommu_dev_table[devid].data[1]; |
1889 | ||
fd7b5535 JR |
1890 | if (ats) |
1891 | flags |= DTE_FLAG_IOTLB; | |
1892 | ||
52815b75 JR |
1893 | if (domain->flags & PD_IOMMUV2_MASK) { |
1894 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1895 | u64 glx = domain->glx; | |
1896 | u64 tmp; | |
1897 | ||
1898 | pte_root |= DTE_FLAG_GV; | |
1899 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1900 | ||
1901 | /* First mask out possible old values for GCR3 table */ | |
1902 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1903 | flags &= ~tmp; | |
1904 | ||
1905 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1906 | flags &= ~tmp; | |
1907 | ||
1908 | /* Encode GCR3 table into DTE */ | |
1909 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1910 | pte_root |= tmp; | |
1911 | ||
1912 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1913 | flags |= tmp; | |
1914 | ||
1915 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1916 | flags |= tmp; | |
1917 | } | |
1918 | ||
ee6c2868 JR |
1919 | flags &= ~(0xffffUL); |
1920 | flags |= domain->id; | |
1921 | ||
1922 | amd_iommu_dev_table[devid].data[1] = flags; | |
1923 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1924 | } |
1925 | ||
1926 | static void clear_dte_entry(u16 devid) | |
1927 | { | |
15898bbc JR |
1928 | /* remove entry from the device table seen by the hardware */ |
1929 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1930 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1931 | |
1932 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1933 | } |
1934 | ||
ec9e79ef JR |
1935 | static void do_attach(struct iommu_dev_data *dev_data, |
1936 | struct protection_domain *domain) | |
7f760ddd | 1937 | { |
7f760ddd | 1938 | struct amd_iommu *iommu; |
ec9e79ef | 1939 | bool ats; |
fd7b5535 | 1940 | |
ec9e79ef JR |
1941 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1942 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1943 | |
1944 | /* Update data structures */ | |
1945 | dev_data->domain = domain; | |
1946 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1947 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1948 | |
1949 | /* Do reference counting */ | |
1950 | domain->dev_iommu[iommu->index] += 1; | |
1951 | domain->dev_cnt += 1; | |
1952 | ||
1953 | /* Flush the DTE entry */ | |
6c542047 | 1954 | device_flush_dte(dev_data); |
7f760ddd JR |
1955 | } |
1956 | ||
ec9e79ef | 1957 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1958 | { |
7f760ddd | 1959 | struct amd_iommu *iommu; |
7f760ddd | 1960 | |
ec9e79ef | 1961 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
1962 | |
1963 | /* decrease reference counters */ | |
7f760ddd JR |
1964 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1965 | dev_data->domain->dev_cnt -= 1; | |
1966 | ||
1967 | /* Update data structures */ | |
1968 | dev_data->domain = NULL; | |
1969 | list_del(&dev_data->list); | |
f62dda66 | 1970 | clear_dte_entry(dev_data->devid); |
15898bbc | 1971 | |
7f760ddd | 1972 | /* Flush the DTE entry */ |
6c542047 | 1973 | device_flush_dte(dev_data); |
2b681faf JR |
1974 | } |
1975 | ||
1976 | /* | |
1977 | * If a device is not yet associated with a domain, this function does | |
1978 | * assigns it visible for the hardware | |
1979 | */ | |
ec9e79ef | 1980 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1981 | struct protection_domain *domain) |
2b681faf | 1982 | { |
84fe6c19 | 1983 | int ret; |
657cbb6b | 1984 | |
2b681faf JR |
1985 | /* lock domain */ |
1986 | spin_lock(&domain->lock); | |
1987 | ||
71f77580 JR |
1988 | if (dev_data->alias_data != NULL) { |
1989 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 1990 | |
2b02b091 JR |
1991 | /* Some sanity checks */ |
1992 | ret = -EBUSY; | |
1993 | if (alias_data->domain != NULL && | |
1994 | alias_data->domain != domain) | |
1995 | goto out_unlock; | |
eba6ac60 | 1996 | |
2b02b091 JR |
1997 | if (dev_data->domain != NULL && |
1998 | dev_data->domain != domain) | |
1999 | goto out_unlock; | |
15898bbc | 2000 | |
2b02b091 | 2001 | /* Do real assignment */ |
7f760ddd | 2002 | if (alias_data->domain == NULL) |
ec9e79ef | 2003 | do_attach(alias_data, domain); |
24100055 JR |
2004 | |
2005 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2006 | } |
15898bbc | 2007 | |
7f760ddd | 2008 | if (dev_data->domain == NULL) |
ec9e79ef | 2009 | do_attach(dev_data, domain); |
eba6ac60 | 2010 | |
24100055 JR |
2011 | atomic_inc(&dev_data->bind); |
2012 | ||
84fe6c19 JL |
2013 | ret = 0; |
2014 | ||
2015 | out_unlock: | |
2016 | ||
eba6ac60 JR |
2017 | /* ready */ |
2018 | spin_unlock(&domain->lock); | |
15898bbc | 2019 | |
84fe6c19 | 2020 | return ret; |
0feae533 | 2021 | } |
b20ac0d4 | 2022 | |
52815b75 JR |
2023 | |
2024 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2025 | { | |
2026 | pci_disable_ats(pdev); | |
2027 | pci_disable_pri(pdev); | |
2028 | pci_disable_pasid(pdev); | |
2029 | } | |
2030 | ||
6a113ddc JR |
2031 | /* FIXME: Change generic reset-function to do the same */ |
2032 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2033 | { | |
2034 | u16 control; | |
2035 | int pos; | |
2036 | ||
46277b75 | 2037 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2038 | if (!pos) |
2039 | return -EINVAL; | |
2040 | ||
46277b75 JR |
2041 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2042 | control |= PCI_PRI_CTRL_RESET; | |
2043 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2044 | |
2045 | return 0; | |
2046 | } | |
2047 | ||
52815b75 JR |
2048 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2049 | { | |
6a113ddc JR |
2050 | bool reset_enable; |
2051 | int reqs, ret; | |
2052 | ||
2053 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2054 | reqs = 32; | |
2055 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2056 | reqs = 1; | |
2057 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2058 | |
2059 | /* Only allow access to user-accessible pages */ | |
2060 | ret = pci_enable_pasid(pdev, 0); | |
2061 | if (ret) | |
2062 | goto out_err; | |
2063 | ||
2064 | /* First reset the PRI state of the device */ | |
2065 | ret = pci_reset_pri(pdev); | |
2066 | if (ret) | |
2067 | goto out_err; | |
2068 | ||
6a113ddc JR |
2069 | /* Enable PRI */ |
2070 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2071 | if (ret) |
2072 | goto out_err; | |
2073 | ||
6a113ddc JR |
2074 | if (reset_enable) { |
2075 | ret = pri_reset_while_enabled(pdev); | |
2076 | if (ret) | |
2077 | goto out_err; | |
2078 | } | |
2079 | ||
52815b75 JR |
2080 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2081 | if (ret) | |
2082 | goto out_err; | |
2083 | ||
2084 | return 0; | |
2085 | ||
2086 | out_err: | |
2087 | pci_disable_pri(pdev); | |
2088 | pci_disable_pasid(pdev); | |
2089 | ||
2090 | return ret; | |
2091 | } | |
2092 | ||
c99afa25 | 2093 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2094 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 JR |
2095 | |
2096 | bool pci_pri_tlp_required(struct pci_dev *pdev) | |
2097 | { | |
a3b93121 | 2098 | u16 status; |
c99afa25 JR |
2099 | int pos; |
2100 | ||
46277b75 | 2101 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2102 | if (!pos) |
2103 | return false; | |
2104 | ||
a3b93121 | 2105 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2106 | |
a3b93121 | 2107 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2108 | } |
2109 | ||
407d733e JR |
2110 | /* |
2111 | * If a device is not yet associated with a domain, this function does | |
2112 | * assigns it visible for the hardware | |
2113 | */ | |
15898bbc JR |
2114 | static int attach_device(struct device *dev, |
2115 | struct protection_domain *domain) | |
0feae533 | 2116 | { |
fd7b5535 | 2117 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2118 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2119 | unsigned long flags; |
15898bbc | 2120 | int ret; |
eba6ac60 | 2121 | |
ea61cddb JR |
2122 | dev_data = get_dev_data(dev); |
2123 | ||
52815b75 JR |
2124 | if (domain->flags & PD_IOMMUV2_MASK) { |
2125 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2126 | return -EINVAL; | |
2127 | ||
2128 | if (pdev_iommuv2_enable(pdev) != 0) | |
2129 | return -EINVAL; | |
2130 | ||
2131 | dev_data->ats.enabled = true; | |
2132 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2133 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2134 | } else if (amd_iommu_iotlb_sup && |
2135 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2136 | dev_data->ats.enabled = true; |
2137 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2138 | } | |
fd7b5535 | 2139 | |
eba6ac60 | 2140 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2141 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2142 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2143 | ||
0feae533 JR |
2144 | /* |
2145 | * We might boot into a crash-kernel here. The crashed kernel | |
2146 | * left the caches in the IOMMU dirty. So we have to flush | |
2147 | * here to evict all dirty stuff. | |
2148 | */ | |
17b124bf | 2149 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2150 | |
2151 | return ret; | |
b20ac0d4 JR |
2152 | } |
2153 | ||
355bf553 JR |
2154 | /* |
2155 | * Removes a device from a protection domain (unlocked) | |
2156 | */ | |
ec9e79ef | 2157 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2158 | { |
2ca76279 | 2159 | struct protection_domain *domain; |
7c392cbe | 2160 | unsigned long flags; |
c4596114 | 2161 | |
7f760ddd | 2162 | BUG_ON(!dev_data->domain); |
355bf553 | 2163 | |
2ca76279 JR |
2164 | domain = dev_data->domain; |
2165 | ||
2166 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2167 | |
71f77580 JR |
2168 | if (dev_data->alias_data != NULL) { |
2169 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2170 | ||
7f760ddd | 2171 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2172 | do_detach(alias_data); |
24100055 JR |
2173 | } |
2174 | ||
7f760ddd | 2175 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2176 | do_detach(dev_data); |
7f760ddd | 2177 | |
2ca76279 | 2178 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2179 | |
2180 | /* | |
2181 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2182 | * passthrough domain if it is detached from any other domain. |
2183 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2184 | */ |
5abcdba4 | 2185 | if (dev_data->passthrough && |
d3ad9373 | 2186 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2187 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2188 | } |
2189 | ||
2190 | /* | |
2191 | * Removes a device from a protection domain (with devtable_lock held) | |
2192 | */ | |
15898bbc | 2193 | static void detach_device(struct device *dev) |
355bf553 | 2194 | { |
52815b75 | 2195 | struct protection_domain *domain; |
ea61cddb | 2196 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2197 | unsigned long flags; |
2198 | ||
ec9e79ef | 2199 | dev_data = get_dev_data(dev); |
52815b75 | 2200 | domain = dev_data->domain; |
ec9e79ef | 2201 | |
355bf553 JR |
2202 | /* lock device table */ |
2203 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2204 | __detach_device(dev_data); |
355bf553 | 2205 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2206 | |
52815b75 JR |
2207 | if (domain->flags & PD_IOMMUV2_MASK) |
2208 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2209 | else if (dev_data->ats.enabled) | |
ea61cddb | 2210 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2211 | |
2212 | dev_data->ats.enabled = false; | |
355bf553 | 2213 | } |
e275a2a0 | 2214 | |
15898bbc JR |
2215 | /* |
2216 | * Find out the protection domain structure for a given PCI device. This | |
2217 | * will give us the pointer to the page table root for example. | |
2218 | */ | |
2219 | static struct protection_domain *domain_for_device(struct device *dev) | |
2220 | { | |
71f77580 | 2221 | struct iommu_dev_data *dev_data; |
2b02b091 | 2222 | struct protection_domain *dom = NULL; |
15898bbc | 2223 | unsigned long flags; |
15898bbc | 2224 | |
657cbb6b | 2225 | dev_data = get_dev_data(dev); |
15898bbc | 2226 | |
2b02b091 JR |
2227 | if (dev_data->domain) |
2228 | return dev_data->domain; | |
15898bbc | 2229 | |
71f77580 JR |
2230 | if (dev_data->alias_data != NULL) { |
2231 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2232 | |
2233 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2234 | if (alias_data->domain != NULL) { | |
2235 | __attach_device(dev_data, alias_data->domain); | |
2236 | dom = alias_data->domain; | |
2237 | } | |
2238 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2239 | } | |
15898bbc JR |
2240 | |
2241 | return dom; | |
2242 | } | |
2243 | ||
e275a2a0 JR |
2244 | static int device_change_notifier(struct notifier_block *nb, |
2245 | unsigned long action, void *data) | |
2246 | { | |
e275a2a0 | 2247 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2248 | struct protection_domain *domain; |
2249 | struct iommu_dev_data *dev_data; | |
2250 | struct device *dev = data; | |
e275a2a0 | 2251 | struct amd_iommu *iommu; |
1ac4cbbc | 2252 | unsigned long flags; |
5abcdba4 | 2253 | u16 devid; |
e275a2a0 | 2254 | |
98fc5a69 JR |
2255 | if (!check_device(dev)) |
2256 | return 0; | |
e275a2a0 | 2257 | |
5abcdba4 JR |
2258 | devid = get_device_id(dev); |
2259 | iommu = amd_iommu_rlookup_table[devid]; | |
2260 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2261 | |
2262 | switch (action) { | |
c1eee67b | 2263 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2264 | |
2265 | domain = domain_for_device(dev); | |
2266 | ||
e275a2a0 JR |
2267 | if (!domain) |
2268 | goto out; | |
5abcdba4 | 2269 | if (dev_data->passthrough) |
a1ca331c | 2270 | break; |
15898bbc | 2271 | detach_device(dev); |
1ac4cbbc JR |
2272 | break; |
2273 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2274 | |
2275 | iommu_init_device(dev); | |
2276 | ||
2277 | domain = domain_for_device(dev); | |
2278 | ||
1ac4cbbc JR |
2279 | /* allocate a protection domain if a device is added */ |
2280 | dma_domain = find_protection_domain(devid); | |
2281 | if (dma_domain) | |
2282 | goto out; | |
87a64d52 | 2283 | dma_domain = dma_ops_domain_alloc(); |
1ac4cbbc JR |
2284 | if (!dma_domain) |
2285 | goto out; | |
2286 | dma_domain->target_dev = devid; | |
2287 | ||
2288 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2289 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2290 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2291 | ||
e275a2a0 | 2292 | break; |
657cbb6b JR |
2293 | case BUS_NOTIFY_DEL_DEVICE: |
2294 | ||
2295 | iommu_uninit_device(dev); | |
2296 | ||
e275a2a0 JR |
2297 | default: |
2298 | goto out; | |
2299 | } | |
2300 | ||
e275a2a0 JR |
2301 | iommu_completion_wait(iommu); |
2302 | ||
2303 | out: | |
2304 | return 0; | |
2305 | } | |
2306 | ||
b25ae679 | 2307 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2308 | .notifier_call = device_change_notifier, |
2309 | }; | |
355bf553 | 2310 | |
8638c491 JR |
2311 | void amd_iommu_init_notifier(void) |
2312 | { | |
2313 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2314 | } | |
2315 | ||
431b2a20 JR |
2316 | /***************************************************************************** |
2317 | * | |
2318 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2319 | * | |
2320 | *****************************************************************************/ | |
2321 | ||
2322 | /* | |
2323 | * In the dma_ops path we only have the struct device. This function | |
2324 | * finds the corresponding IOMMU, the protection domain and the | |
2325 | * requestor id for a given device. | |
2326 | * If the device is not yet associated with a domain this is also done | |
2327 | * in this function. | |
2328 | */ | |
94f6d190 | 2329 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2330 | { |
94f6d190 | 2331 | struct protection_domain *domain; |
b20ac0d4 | 2332 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2333 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2334 | |
f99c0f1c | 2335 | if (!check_device(dev)) |
94f6d190 | 2336 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2337 | |
94f6d190 JR |
2338 | domain = domain_for_device(dev); |
2339 | if (domain != NULL && !dma_ops_domain(domain)) | |
2340 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2341 | |
94f6d190 JR |
2342 | if (domain != NULL) |
2343 | return domain; | |
b20ac0d4 | 2344 | |
15898bbc | 2345 | /* Device not bount yet - bind it */ |
94f6d190 | 2346 | dma_dom = find_protection_domain(devid); |
15898bbc | 2347 | if (!dma_dom) |
94f6d190 JR |
2348 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2349 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2350 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2351 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2352 | |
94f6d190 | 2353 | return &dma_dom->domain; |
b20ac0d4 JR |
2354 | } |
2355 | ||
04bfdd84 JR |
2356 | static void update_device_table(struct protection_domain *domain) |
2357 | { | |
492667da | 2358 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2359 | |
ea61cddb JR |
2360 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2361 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2362 | } |
2363 | ||
2364 | static void update_domain(struct protection_domain *domain) | |
2365 | { | |
2366 | if (!domain->updated) | |
2367 | return; | |
2368 | ||
2369 | update_device_table(domain); | |
17b124bf JR |
2370 | |
2371 | domain_flush_devices(domain); | |
2372 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2373 | |
2374 | domain->updated = false; | |
2375 | } | |
2376 | ||
8bda3092 JR |
2377 | /* |
2378 | * This function fetches the PTE for a given address in the aperture | |
2379 | */ | |
2380 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2381 | unsigned long address) | |
2382 | { | |
384de729 | 2383 | struct aperture_range *aperture; |
8bda3092 JR |
2384 | u64 *pte, *pte_page; |
2385 | ||
384de729 JR |
2386 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2387 | if (!aperture) | |
2388 | return NULL; | |
2389 | ||
2390 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2391 | if (!pte) { |
cbb9d729 | 2392 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2393 | GFP_ATOMIC); |
384de729 JR |
2394 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2395 | } else | |
8c8c143c | 2396 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2397 | |
04bfdd84 | 2398 | update_domain(&dom->domain); |
8bda3092 JR |
2399 | |
2400 | return pte; | |
2401 | } | |
2402 | ||
431b2a20 JR |
2403 | /* |
2404 | * This is the generic map function. It maps one 4kb page at paddr to | |
2405 | * the given address in the DMA address space for the domain. | |
2406 | */ | |
680525e0 | 2407 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2408 | unsigned long address, |
2409 | phys_addr_t paddr, | |
2410 | int direction) | |
2411 | { | |
2412 | u64 *pte, __pte; | |
2413 | ||
2414 | WARN_ON(address > dom->aperture_size); | |
2415 | ||
2416 | paddr &= PAGE_MASK; | |
2417 | ||
8bda3092 | 2418 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2419 | if (!pte) |
8fd524b3 | 2420 | return DMA_ERROR_CODE; |
cb76c322 JR |
2421 | |
2422 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2423 | ||
2424 | if (direction == DMA_TO_DEVICE) | |
2425 | __pte |= IOMMU_PTE_IR; | |
2426 | else if (direction == DMA_FROM_DEVICE) | |
2427 | __pte |= IOMMU_PTE_IW; | |
2428 | else if (direction == DMA_BIDIRECTIONAL) | |
2429 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2430 | ||
2431 | WARN_ON(*pte); | |
2432 | ||
2433 | *pte = __pte; | |
2434 | ||
2435 | return (dma_addr_t)address; | |
2436 | } | |
2437 | ||
431b2a20 JR |
2438 | /* |
2439 | * The generic unmapping function for on page in the DMA address space. | |
2440 | */ | |
680525e0 | 2441 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2442 | unsigned long address) |
2443 | { | |
384de729 | 2444 | struct aperture_range *aperture; |
cb76c322 JR |
2445 | u64 *pte; |
2446 | ||
2447 | if (address >= dom->aperture_size) | |
2448 | return; | |
2449 | ||
384de729 JR |
2450 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2451 | if (!aperture) | |
2452 | return; | |
2453 | ||
2454 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2455 | if (!pte) | |
2456 | return; | |
cb76c322 | 2457 | |
8c8c143c | 2458 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2459 | |
2460 | WARN_ON(!*pte); | |
2461 | ||
2462 | *pte = 0ULL; | |
2463 | } | |
2464 | ||
431b2a20 JR |
2465 | /* |
2466 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2467 | * contiguous memory region into DMA address space. It is used by all |
2468 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2469 | * Must be called with the domain lock held. |
2470 | */ | |
cb76c322 | 2471 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2472 | struct dma_ops_domain *dma_dom, |
2473 | phys_addr_t paddr, | |
2474 | size_t size, | |
6d4f343f | 2475 | int dir, |
832a90c3 JR |
2476 | bool align, |
2477 | u64 dma_mask) | |
cb76c322 JR |
2478 | { |
2479 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2480 | dma_addr_t address, start, ret; |
cb76c322 | 2481 | unsigned int pages; |
6d4f343f | 2482 | unsigned long align_mask = 0; |
cb76c322 JR |
2483 | int i; |
2484 | ||
e3c449f5 | 2485 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2486 | paddr &= PAGE_MASK; |
2487 | ||
8ecaf8f1 JR |
2488 | INC_STATS_COUNTER(total_map_requests); |
2489 | ||
c1858976 JR |
2490 | if (pages > 1) |
2491 | INC_STATS_COUNTER(cross_page); | |
2492 | ||
6d4f343f JR |
2493 | if (align) |
2494 | align_mask = (1UL << get_order(size)) - 1; | |
2495 | ||
11b83888 | 2496 | retry: |
832a90c3 JR |
2497 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2498 | dma_mask); | |
8fd524b3 | 2499 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2500 | /* |
2501 | * setting next_address here will let the address | |
2502 | * allocator only scan the new allocated range in the | |
2503 | * first run. This is a small optimization. | |
2504 | */ | |
2505 | dma_dom->next_address = dma_dom->aperture_size; | |
2506 | ||
576175c2 | 2507 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2508 | goto out; |
2509 | ||
2510 | /* | |
af901ca1 | 2511 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2512 | * allocation again |
2513 | */ | |
2514 | goto retry; | |
2515 | } | |
cb76c322 JR |
2516 | |
2517 | start = address; | |
2518 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2519 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2520 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2521 | goto out_unmap; |
2522 | ||
cb76c322 JR |
2523 | paddr += PAGE_SIZE; |
2524 | start += PAGE_SIZE; | |
2525 | } | |
2526 | address += offset; | |
2527 | ||
5774f7c5 JR |
2528 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2529 | ||
afa9fdc2 | 2530 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2531 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2532 | dma_dom->need_flush = false; |
318afd41 | 2533 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2534 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2535 | |
cb76c322 JR |
2536 | out: |
2537 | return address; | |
53812c11 JR |
2538 | |
2539 | out_unmap: | |
2540 | ||
2541 | for (--i; i >= 0; --i) { | |
2542 | start -= PAGE_SIZE; | |
680525e0 | 2543 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2544 | } |
2545 | ||
2546 | dma_ops_free_addresses(dma_dom, address, pages); | |
2547 | ||
8fd524b3 | 2548 | return DMA_ERROR_CODE; |
cb76c322 JR |
2549 | } |
2550 | ||
431b2a20 JR |
2551 | /* |
2552 | * Does the reverse of the __map_single function. Must be called with | |
2553 | * the domain lock held too | |
2554 | */ | |
cd8c82e8 | 2555 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2556 | dma_addr_t dma_addr, |
2557 | size_t size, | |
2558 | int dir) | |
2559 | { | |
04e0463e | 2560 | dma_addr_t flush_addr; |
cb76c322 JR |
2561 | dma_addr_t i, start; |
2562 | unsigned int pages; | |
2563 | ||
8fd524b3 | 2564 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2565 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2566 | return; |
2567 | ||
04e0463e | 2568 | flush_addr = dma_addr; |
e3c449f5 | 2569 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2570 | dma_addr &= PAGE_MASK; |
2571 | start = dma_addr; | |
2572 | ||
2573 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2574 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2575 | start += PAGE_SIZE; |
2576 | } | |
2577 | ||
5774f7c5 JR |
2578 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2579 | ||
cb76c322 | 2580 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2581 | |
80be308d | 2582 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2583 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2584 | dma_dom->need_flush = false; |
2585 | } | |
cb76c322 JR |
2586 | } |
2587 | ||
431b2a20 JR |
2588 | /* |
2589 | * The exported map_single function for dma_ops. | |
2590 | */ | |
51491367 FT |
2591 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2592 | unsigned long offset, size_t size, | |
2593 | enum dma_data_direction dir, | |
2594 | struct dma_attrs *attrs) | |
4da70b9e JR |
2595 | { |
2596 | unsigned long flags; | |
4da70b9e | 2597 | struct protection_domain *domain; |
4da70b9e | 2598 | dma_addr_t addr; |
832a90c3 | 2599 | u64 dma_mask; |
51491367 | 2600 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2601 | |
0f2a86f2 JR |
2602 | INC_STATS_COUNTER(cnt_map_single); |
2603 | ||
94f6d190 JR |
2604 | domain = get_domain(dev); |
2605 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2606 | return (dma_addr_t)paddr; |
94f6d190 JR |
2607 | else if (IS_ERR(domain)) |
2608 | return DMA_ERROR_CODE; | |
4da70b9e | 2609 | |
f99c0f1c JR |
2610 | dma_mask = *dev->dma_mask; |
2611 | ||
4da70b9e | 2612 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2613 | |
cd8c82e8 | 2614 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2615 | dma_mask); |
8fd524b3 | 2616 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2617 | goto out; |
2618 | ||
17b124bf | 2619 | domain_flush_complete(domain); |
4da70b9e JR |
2620 | |
2621 | out: | |
2622 | spin_unlock_irqrestore(&domain->lock, flags); | |
2623 | ||
2624 | return addr; | |
2625 | } | |
2626 | ||
431b2a20 JR |
2627 | /* |
2628 | * The exported unmap_single function for dma_ops. | |
2629 | */ | |
51491367 FT |
2630 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2631 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2632 | { |
2633 | unsigned long flags; | |
4da70b9e | 2634 | struct protection_domain *domain; |
4da70b9e | 2635 | |
146a6917 JR |
2636 | INC_STATS_COUNTER(cnt_unmap_single); |
2637 | ||
94f6d190 JR |
2638 | domain = get_domain(dev); |
2639 | if (IS_ERR(domain)) | |
5b28df6f JR |
2640 | return; |
2641 | ||
4da70b9e JR |
2642 | spin_lock_irqsave(&domain->lock, flags); |
2643 | ||
cd8c82e8 | 2644 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2645 | |
17b124bf | 2646 | domain_flush_complete(domain); |
4da70b9e JR |
2647 | |
2648 | spin_unlock_irqrestore(&domain->lock, flags); | |
2649 | } | |
2650 | ||
431b2a20 JR |
2651 | /* |
2652 | * This is a special map_sg function which is used if we should map a | |
2653 | * device which is not handled by an AMD IOMMU in the system. | |
2654 | */ | |
65b050ad JR |
2655 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
2656 | int nelems, int dir) | |
2657 | { | |
2658 | struct scatterlist *s; | |
2659 | int i; | |
2660 | ||
2661 | for_each_sg(sglist, s, nelems, i) { | |
2662 | s->dma_address = (dma_addr_t)sg_phys(s); | |
2663 | s->dma_length = s->length; | |
2664 | } | |
2665 | ||
2666 | return nelems; | |
2667 | } | |
2668 | ||
431b2a20 JR |
2669 | /* |
2670 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2671 | * lists). | |
2672 | */ | |
65b050ad | 2673 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2674 | int nelems, enum dma_data_direction dir, |
2675 | struct dma_attrs *attrs) | |
65b050ad JR |
2676 | { |
2677 | unsigned long flags; | |
65b050ad | 2678 | struct protection_domain *domain; |
65b050ad JR |
2679 | int i; |
2680 | struct scatterlist *s; | |
2681 | phys_addr_t paddr; | |
2682 | int mapped_elems = 0; | |
832a90c3 | 2683 | u64 dma_mask; |
65b050ad | 2684 | |
d03f067a JR |
2685 | INC_STATS_COUNTER(cnt_map_sg); |
2686 | ||
94f6d190 JR |
2687 | domain = get_domain(dev); |
2688 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 2689 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
2690 | else if (IS_ERR(domain)) |
2691 | return 0; | |
dbcc112e | 2692 | |
832a90c3 | 2693 | dma_mask = *dev->dma_mask; |
65b050ad | 2694 | |
65b050ad JR |
2695 | spin_lock_irqsave(&domain->lock, flags); |
2696 | ||
2697 | for_each_sg(sglist, s, nelems, i) { | |
2698 | paddr = sg_phys(s); | |
2699 | ||
cd8c82e8 | 2700 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2701 | paddr, s->length, dir, false, |
2702 | dma_mask); | |
65b050ad JR |
2703 | |
2704 | if (s->dma_address) { | |
2705 | s->dma_length = s->length; | |
2706 | mapped_elems++; | |
2707 | } else | |
2708 | goto unmap; | |
65b050ad JR |
2709 | } |
2710 | ||
17b124bf | 2711 | domain_flush_complete(domain); |
65b050ad JR |
2712 | |
2713 | out: | |
2714 | spin_unlock_irqrestore(&domain->lock, flags); | |
2715 | ||
2716 | return mapped_elems; | |
2717 | unmap: | |
2718 | for_each_sg(sglist, s, mapped_elems, i) { | |
2719 | if (s->dma_address) | |
cd8c82e8 | 2720 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2721 | s->dma_length, dir); |
2722 | s->dma_address = s->dma_length = 0; | |
2723 | } | |
2724 | ||
2725 | mapped_elems = 0; | |
2726 | ||
2727 | goto out; | |
2728 | } | |
2729 | ||
431b2a20 JR |
2730 | /* |
2731 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2732 | * lists). | |
2733 | */ | |
65b050ad | 2734 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2735 | int nelems, enum dma_data_direction dir, |
2736 | struct dma_attrs *attrs) | |
65b050ad JR |
2737 | { |
2738 | unsigned long flags; | |
65b050ad JR |
2739 | struct protection_domain *domain; |
2740 | struct scatterlist *s; | |
65b050ad JR |
2741 | int i; |
2742 | ||
55877a6b JR |
2743 | INC_STATS_COUNTER(cnt_unmap_sg); |
2744 | ||
94f6d190 JR |
2745 | domain = get_domain(dev); |
2746 | if (IS_ERR(domain)) | |
5b28df6f JR |
2747 | return; |
2748 | ||
65b050ad JR |
2749 | spin_lock_irqsave(&domain->lock, flags); |
2750 | ||
2751 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2752 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2753 | s->dma_length, dir); |
65b050ad JR |
2754 | s->dma_address = s->dma_length = 0; |
2755 | } | |
2756 | ||
17b124bf | 2757 | domain_flush_complete(domain); |
65b050ad JR |
2758 | |
2759 | spin_unlock_irqrestore(&domain->lock, flags); | |
2760 | } | |
2761 | ||
431b2a20 JR |
2762 | /* |
2763 | * The exported alloc_coherent function for dma_ops. | |
2764 | */ | |
5d8b53cf | 2765 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2766 | dma_addr_t *dma_addr, gfp_t flag, |
2767 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2768 | { |
2769 | unsigned long flags; | |
2770 | void *virt_addr; | |
5d8b53cf | 2771 | struct protection_domain *domain; |
5d8b53cf | 2772 | phys_addr_t paddr; |
832a90c3 | 2773 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2774 | |
c8f0fb36 JR |
2775 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2776 | ||
94f6d190 JR |
2777 | domain = get_domain(dev); |
2778 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2779 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2780 | *dma_addr = __pa(virt_addr); | |
2781 | return virt_addr; | |
94f6d190 JR |
2782 | } else if (IS_ERR(domain)) |
2783 | return NULL; | |
5d8b53cf | 2784 | |
f99c0f1c JR |
2785 | dma_mask = dev->coherent_dma_mask; |
2786 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2787 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2788 | |
2789 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2790 | if (!virt_addr) | |
b25ae679 | 2791 | return NULL; |
5d8b53cf | 2792 | |
5d8b53cf JR |
2793 | paddr = virt_to_phys(virt_addr); |
2794 | ||
832a90c3 JR |
2795 | if (!dma_mask) |
2796 | dma_mask = *dev->dma_mask; | |
2797 | ||
5d8b53cf JR |
2798 | spin_lock_irqsave(&domain->lock, flags); |
2799 | ||
cd8c82e8 | 2800 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2801 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2802 | |
8fd524b3 | 2803 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2804 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2805 | goto out_free; |
367d04c4 | 2806 | } |
5d8b53cf | 2807 | |
17b124bf | 2808 | domain_flush_complete(domain); |
5d8b53cf | 2809 | |
5d8b53cf JR |
2810 | spin_unlock_irqrestore(&domain->lock, flags); |
2811 | ||
2812 | return virt_addr; | |
5b28df6f JR |
2813 | |
2814 | out_free: | |
2815 | ||
2816 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2817 | ||
2818 | return NULL; | |
5d8b53cf JR |
2819 | } |
2820 | ||
431b2a20 JR |
2821 | /* |
2822 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2823 | */ |
5d8b53cf | 2824 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2825 | void *virt_addr, dma_addr_t dma_addr, |
2826 | struct dma_attrs *attrs) | |
5d8b53cf JR |
2827 | { |
2828 | unsigned long flags; | |
5d8b53cf | 2829 | struct protection_domain *domain; |
5d8b53cf | 2830 | |
5d31ee7e JR |
2831 | INC_STATS_COUNTER(cnt_free_coherent); |
2832 | ||
94f6d190 JR |
2833 | domain = get_domain(dev); |
2834 | if (IS_ERR(domain)) | |
5b28df6f JR |
2835 | goto free_mem; |
2836 | ||
5d8b53cf JR |
2837 | spin_lock_irqsave(&domain->lock, flags); |
2838 | ||
cd8c82e8 | 2839 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2840 | |
17b124bf | 2841 | domain_flush_complete(domain); |
5d8b53cf JR |
2842 | |
2843 | spin_unlock_irqrestore(&domain->lock, flags); | |
2844 | ||
2845 | free_mem: | |
2846 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2847 | } | |
2848 | ||
b39ba6ad JR |
2849 | /* |
2850 | * This function is called by the DMA layer to find out if we can handle a | |
2851 | * particular device. It is part of the dma_ops. | |
2852 | */ | |
2853 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2854 | { | |
420aef8a | 2855 | return check_device(dev); |
b39ba6ad JR |
2856 | } |
2857 | ||
c432f3df | 2858 | /* |
431b2a20 JR |
2859 | * The function for pre-allocating protection domains. |
2860 | * | |
c432f3df JR |
2861 | * If the driver core informs the DMA layer if a driver grabs a device |
2862 | * we don't need to preallocate the protection domains anymore. | |
2863 | * For now we have to. | |
2864 | */ | |
943bc7e1 | 2865 | static void __init prealloc_protection_domains(void) |
c432f3df | 2866 | { |
5abcdba4 | 2867 | struct iommu_dev_data *dev_data; |
c432f3df | 2868 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 2869 | struct pci_dev *dev = NULL; |
98fc5a69 | 2870 | u16 devid; |
c432f3df | 2871 | |
d18c69d3 | 2872 | for_each_pci_dev(dev) { |
98fc5a69 JR |
2873 | |
2874 | /* Do we handle this device? */ | |
2875 | if (!check_device(&dev->dev)) | |
c432f3df | 2876 | continue; |
98fc5a69 | 2877 | |
5abcdba4 JR |
2878 | dev_data = get_dev_data(&dev->dev); |
2879 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
2880 | /* Make sure passthrough domain is allocated */ | |
2881 | alloc_passthrough_domain(); | |
2882 | dev_data->passthrough = true; | |
2883 | attach_device(&dev->dev, pt_domain); | |
2884 | pr_info("AMD-Vi: Using passthough domain for device %s\n", | |
2885 | dev_name(&dev->dev)); | |
2886 | } | |
2887 | ||
98fc5a69 | 2888 | /* Is there already any domain for it? */ |
15898bbc | 2889 | if (domain_for_device(&dev->dev)) |
c432f3df | 2890 | continue; |
98fc5a69 JR |
2891 | |
2892 | devid = get_device_id(&dev->dev); | |
2893 | ||
87a64d52 | 2894 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
2895 | if (!dma_dom) |
2896 | continue; | |
2897 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2898 | dma_dom->target_dev = devid; |
2899 | ||
15898bbc | 2900 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2901 | |
bd60b735 | 2902 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2903 | } |
2904 | } | |
2905 | ||
160c1d8e | 2906 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2907 | .alloc = alloc_coherent, |
2908 | .free = free_coherent, | |
51491367 FT |
2909 | .map_page = map_page, |
2910 | .unmap_page = unmap_page, | |
6631ee9d JR |
2911 | .map_sg = map_sg, |
2912 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2913 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2914 | }; |
2915 | ||
27c2127a JR |
2916 | static unsigned device_dma_ops_init(void) |
2917 | { | |
5abcdba4 | 2918 | struct iommu_dev_data *dev_data; |
27c2127a JR |
2919 | struct pci_dev *pdev = NULL; |
2920 | unsigned unhandled = 0; | |
2921 | ||
2922 | for_each_pci_dev(pdev) { | |
2923 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
2924 | |
2925 | iommu_ignore_device(&pdev->dev); | |
2926 | ||
27c2127a JR |
2927 | unhandled += 1; |
2928 | continue; | |
2929 | } | |
2930 | ||
5abcdba4 JR |
2931 | dev_data = get_dev_data(&pdev->dev); |
2932 | ||
2933 | if (!dev_data->passthrough) | |
2934 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
2935 | else | |
2936 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
2937 | } |
2938 | ||
2939 | return unhandled; | |
2940 | } | |
2941 | ||
431b2a20 JR |
2942 | /* |
2943 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2944 | */ | |
f5325094 JR |
2945 | |
2946 | void __init amd_iommu_init_api(void) | |
2947 | { | |
2cc21c42 | 2948 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2949 | } |
2950 | ||
6631ee9d JR |
2951 | int __init amd_iommu_init_dma_ops(void) |
2952 | { | |
2953 | struct amd_iommu *iommu; | |
27c2127a | 2954 | int ret, unhandled; |
6631ee9d | 2955 | |
431b2a20 JR |
2956 | /* |
2957 | * first allocate a default protection domain for every IOMMU we | |
2958 | * found in the system. Devices not assigned to any other | |
2959 | * protection domain will be assigned to the default one. | |
2960 | */ | |
3bd22172 | 2961 | for_each_iommu(iommu) { |
87a64d52 | 2962 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
2963 | if (iommu->default_dom == NULL) |
2964 | return -ENOMEM; | |
e2dc14a2 | 2965 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2966 | ret = iommu_init_unity_mappings(iommu); |
2967 | if (ret) | |
2968 | goto free_domains; | |
2969 | } | |
2970 | ||
431b2a20 | 2971 | /* |
8793abeb | 2972 | * Pre-allocate the protection domains for each device. |
431b2a20 | 2973 | */ |
8793abeb | 2974 | prealloc_protection_domains(); |
6631ee9d JR |
2975 | |
2976 | iommu_detected = 1; | |
75f1cdf1 | 2977 | swiotlb = 0; |
6631ee9d | 2978 | |
431b2a20 | 2979 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
2980 | unhandled = device_dma_ops_init(); |
2981 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
2982 | /* There are unhandled devices - initialize swiotlb for them */ | |
2983 | swiotlb = 1; | |
2984 | } | |
6631ee9d | 2985 | |
7f26508b JR |
2986 | amd_iommu_stats_init(); |
2987 | ||
6631ee9d JR |
2988 | return 0; |
2989 | ||
2990 | free_domains: | |
2991 | ||
3bd22172 | 2992 | for_each_iommu(iommu) { |
6631ee9d JR |
2993 | if (iommu->default_dom) |
2994 | dma_ops_domain_free(iommu->default_dom); | |
2995 | } | |
2996 | ||
2997 | return ret; | |
2998 | } | |
6d98cd80 JR |
2999 | |
3000 | /***************************************************************************** | |
3001 | * | |
3002 | * The following functions belong to the exported interface of AMD IOMMU | |
3003 | * | |
3004 | * This interface allows access to lower level functions of the IOMMU | |
3005 | * like protection domain handling and assignement of devices to domains | |
3006 | * which is not possible with the dma_ops interface. | |
3007 | * | |
3008 | *****************************************************************************/ | |
3009 | ||
6d98cd80 JR |
3010 | static void cleanup_domain(struct protection_domain *domain) |
3011 | { | |
492667da | 3012 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 3013 | unsigned long flags; |
6d98cd80 JR |
3014 | |
3015 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3016 | ||
492667da | 3017 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3018 | __detach_device(dev_data); |
492667da JR |
3019 | atomic_set(&dev_data->bind, 0); |
3020 | } | |
6d98cd80 JR |
3021 | |
3022 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3023 | } | |
3024 | ||
2650815f JR |
3025 | static void protection_domain_free(struct protection_domain *domain) |
3026 | { | |
3027 | if (!domain) | |
3028 | return; | |
3029 | ||
aeb26f55 JR |
3030 | del_domain_from_list(domain); |
3031 | ||
2650815f JR |
3032 | if (domain->id) |
3033 | domain_id_free(domain->id); | |
3034 | ||
3035 | kfree(domain); | |
3036 | } | |
3037 | ||
3038 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3039 | { |
3040 | struct protection_domain *domain; | |
3041 | ||
3042 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3043 | if (!domain) | |
2650815f | 3044 | return NULL; |
c156e347 JR |
3045 | |
3046 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3047 | mutex_init(&domain->api_lock); |
c156e347 JR |
3048 | domain->id = domain_id_alloc(); |
3049 | if (!domain->id) | |
2650815f | 3050 | goto out_err; |
7c392cbe | 3051 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3052 | |
aeb26f55 JR |
3053 | add_domain_to_list(domain); |
3054 | ||
2650815f JR |
3055 | return domain; |
3056 | ||
3057 | out_err: | |
3058 | kfree(domain); | |
3059 | ||
3060 | return NULL; | |
3061 | } | |
3062 | ||
5abcdba4 JR |
3063 | static int __init alloc_passthrough_domain(void) |
3064 | { | |
3065 | if (pt_domain != NULL) | |
3066 | return 0; | |
3067 | ||
3068 | /* allocate passthrough domain */ | |
3069 | pt_domain = protection_domain_alloc(); | |
3070 | if (!pt_domain) | |
3071 | return -ENOMEM; | |
3072 | ||
3073 | pt_domain->mode = PAGE_MODE_NONE; | |
3074 | ||
3075 | return 0; | |
3076 | } | |
2650815f JR |
3077 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3078 | { | |
3079 | struct protection_domain *domain; | |
3080 | ||
3081 | domain = protection_domain_alloc(); | |
3082 | if (!domain) | |
c156e347 | 3083 | goto out_free; |
2650815f JR |
3084 | |
3085 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3086 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3087 | if (!domain->pt_root) | |
3088 | goto out_free; | |
3089 | ||
f3572db8 JR |
3090 | domain->iommu_domain = dom; |
3091 | ||
c156e347 JR |
3092 | dom->priv = domain; |
3093 | ||
3094 | return 0; | |
3095 | ||
3096 | out_free: | |
2650815f | 3097 | protection_domain_free(domain); |
c156e347 JR |
3098 | |
3099 | return -ENOMEM; | |
3100 | } | |
3101 | ||
98383fc3 JR |
3102 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3103 | { | |
3104 | struct protection_domain *domain = dom->priv; | |
3105 | ||
3106 | if (!domain) | |
3107 | return; | |
3108 | ||
3109 | if (domain->dev_cnt > 0) | |
3110 | cleanup_domain(domain); | |
3111 | ||
3112 | BUG_ON(domain->dev_cnt != 0); | |
3113 | ||
132bd68f JR |
3114 | if (domain->mode != PAGE_MODE_NONE) |
3115 | free_pagetable(domain); | |
98383fc3 | 3116 | |
52815b75 JR |
3117 | if (domain->flags & PD_IOMMUV2_MASK) |
3118 | free_gcr3_table(domain); | |
3119 | ||
8b408fe4 | 3120 | protection_domain_free(domain); |
98383fc3 JR |
3121 | |
3122 | dom->priv = NULL; | |
3123 | } | |
3124 | ||
684f2888 JR |
3125 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3126 | struct device *dev) | |
3127 | { | |
657cbb6b | 3128 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3129 | struct amd_iommu *iommu; |
684f2888 JR |
3130 | u16 devid; |
3131 | ||
98fc5a69 | 3132 | if (!check_device(dev)) |
684f2888 JR |
3133 | return; |
3134 | ||
98fc5a69 | 3135 | devid = get_device_id(dev); |
684f2888 | 3136 | |
657cbb6b | 3137 | if (dev_data->domain != NULL) |
15898bbc | 3138 | detach_device(dev); |
684f2888 JR |
3139 | |
3140 | iommu = amd_iommu_rlookup_table[devid]; | |
3141 | if (!iommu) | |
3142 | return; | |
3143 | ||
684f2888 JR |
3144 | iommu_completion_wait(iommu); |
3145 | } | |
3146 | ||
01106066 JR |
3147 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3148 | struct device *dev) | |
3149 | { | |
3150 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3151 | struct iommu_dev_data *dev_data; |
01106066 | 3152 | struct amd_iommu *iommu; |
15898bbc | 3153 | int ret; |
01106066 | 3154 | |
98fc5a69 | 3155 | if (!check_device(dev)) |
01106066 JR |
3156 | return -EINVAL; |
3157 | ||
657cbb6b JR |
3158 | dev_data = dev->archdata.iommu; |
3159 | ||
f62dda66 | 3160 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3161 | if (!iommu) |
3162 | return -EINVAL; | |
3163 | ||
657cbb6b | 3164 | if (dev_data->domain) |
15898bbc | 3165 | detach_device(dev); |
01106066 | 3166 | |
15898bbc | 3167 | ret = attach_device(dev, domain); |
01106066 JR |
3168 | |
3169 | iommu_completion_wait(iommu); | |
3170 | ||
15898bbc | 3171 | return ret; |
01106066 JR |
3172 | } |
3173 | ||
468e2366 | 3174 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3175 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3176 | { |
3177 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3178 | int prot = 0; |
3179 | int ret; | |
3180 | ||
132bd68f JR |
3181 | if (domain->mode == PAGE_MODE_NONE) |
3182 | return -EINVAL; | |
3183 | ||
c6229ca6 JR |
3184 | if (iommu_prot & IOMMU_READ) |
3185 | prot |= IOMMU_PROT_IR; | |
3186 | if (iommu_prot & IOMMU_WRITE) | |
3187 | prot |= IOMMU_PROT_IW; | |
3188 | ||
5d214fe6 | 3189 | mutex_lock(&domain->api_lock); |
795e74f7 | 3190 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3191 | mutex_unlock(&domain->api_lock); |
3192 | ||
795e74f7 | 3193 | return ret; |
c6229ca6 JR |
3194 | } |
3195 | ||
5009065d OBC |
3196 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3197 | size_t page_size) | |
eb74ff6c | 3198 | { |
eb74ff6c | 3199 | struct protection_domain *domain = dom->priv; |
5009065d | 3200 | size_t unmap_size; |
eb74ff6c | 3201 | |
132bd68f JR |
3202 | if (domain->mode == PAGE_MODE_NONE) |
3203 | return -EINVAL; | |
3204 | ||
5d214fe6 | 3205 | mutex_lock(&domain->api_lock); |
468e2366 | 3206 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3207 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3208 | |
17b124bf | 3209 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3210 | |
5009065d | 3211 | return unmap_size; |
eb74ff6c JR |
3212 | } |
3213 | ||
645c4c8d JR |
3214 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
3215 | unsigned long iova) | |
3216 | { | |
3217 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3218 | unsigned long offset_mask; |
645c4c8d | 3219 | phys_addr_t paddr; |
f03152bb | 3220 | u64 *pte, __pte; |
645c4c8d | 3221 | |
132bd68f JR |
3222 | if (domain->mode == PAGE_MODE_NONE) |
3223 | return iova; | |
3224 | ||
24cd7723 | 3225 | pte = fetch_pte(domain, iova); |
645c4c8d | 3226 | |
a6d41a40 | 3227 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3228 | return 0; |
3229 | ||
f03152bb JR |
3230 | if (PM_PTE_LEVEL(*pte) == 0) |
3231 | offset_mask = PAGE_SIZE - 1; | |
3232 | else | |
3233 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3234 | ||
3235 | __pte = *pte & PM_ADDR_MASK; | |
3236 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3237 | |
3238 | return paddr; | |
3239 | } | |
3240 | ||
dbb9fd86 SY |
3241 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3242 | unsigned long cap) | |
3243 | { | |
80a506b8 JR |
3244 | switch (cap) { |
3245 | case IOMMU_CAP_CACHE_COHERENCY: | |
3246 | return 1; | |
3247 | } | |
3248 | ||
dbb9fd86 SY |
3249 | return 0; |
3250 | } | |
3251 | ||
26961efe JR |
3252 | static struct iommu_ops amd_iommu_ops = { |
3253 | .domain_init = amd_iommu_domain_init, | |
3254 | .domain_destroy = amd_iommu_domain_destroy, | |
3255 | .attach_dev = amd_iommu_attach_device, | |
3256 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3257 | .map = amd_iommu_map, |
3258 | .unmap = amd_iommu_unmap, | |
26961efe | 3259 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3260 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3261 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3262 | }; |
3263 | ||
0feae533 JR |
3264 | /***************************************************************************** |
3265 | * | |
3266 | * The next functions do a basic initialization of IOMMU for pass through | |
3267 | * mode | |
3268 | * | |
3269 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3270 | * DMA-API translation. | |
3271 | * | |
3272 | *****************************************************************************/ | |
3273 | ||
3274 | int __init amd_iommu_init_passthrough(void) | |
3275 | { | |
5abcdba4 | 3276 | struct iommu_dev_data *dev_data; |
0feae533 | 3277 | struct pci_dev *dev = NULL; |
5abcdba4 | 3278 | struct amd_iommu *iommu; |
15898bbc | 3279 | u16 devid; |
5abcdba4 | 3280 | int ret; |
0feae533 | 3281 | |
5abcdba4 JR |
3282 | ret = alloc_passthrough_domain(); |
3283 | if (ret) | |
3284 | return ret; | |
0feae533 | 3285 | |
6c54aabd | 3286 | for_each_pci_dev(dev) { |
98fc5a69 | 3287 | if (!check_device(&dev->dev)) |
0feae533 JR |
3288 | continue; |
3289 | ||
5abcdba4 JR |
3290 | dev_data = get_dev_data(&dev->dev); |
3291 | dev_data->passthrough = true; | |
3292 | ||
98fc5a69 JR |
3293 | devid = get_device_id(&dev->dev); |
3294 | ||
15898bbc | 3295 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
3296 | if (!iommu) |
3297 | continue; | |
3298 | ||
15898bbc | 3299 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3300 | } |
3301 | ||
2655d7a2 JR |
3302 | amd_iommu_stats_init(); |
3303 | ||
0feae533 JR |
3304 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3305 | ||
3306 | return 0; | |
3307 | } | |
72e1dcc4 JR |
3308 | |
3309 | /* IOMMUv2 specific functions */ | |
3310 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3311 | { | |
3312 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3313 | } | |
3314 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3315 | ||
3316 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3317 | { | |
3318 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3319 | } | |
3320 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3321 | |
3322 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3323 | { | |
3324 | struct protection_domain *domain = dom->priv; | |
3325 | unsigned long flags; | |
3326 | ||
3327 | spin_lock_irqsave(&domain->lock, flags); | |
3328 | ||
3329 | /* Update data structure */ | |
3330 | domain->mode = PAGE_MODE_NONE; | |
3331 | domain->updated = true; | |
3332 | ||
3333 | /* Make changes visible to IOMMUs */ | |
3334 | update_domain(domain); | |
3335 | ||
3336 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3337 | free_pagetable(domain); | |
3338 | ||
3339 | spin_unlock_irqrestore(&domain->lock, flags); | |
3340 | } | |
3341 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3342 | |
3343 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3344 | { | |
3345 | struct protection_domain *domain = dom->priv; | |
3346 | unsigned long flags; | |
3347 | int levels, ret; | |
3348 | ||
3349 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3350 | return -EINVAL; | |
3351 | ||
3352 | /* Number of GCR3 table levels required */ | |
3353 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3354 | levels += 1; | |
3355 | ||
3356 | if (levels > amd_iommu_max_glx_val) | |
3357 | return -EINVAL; | |
3358 | ||
3359 | spin_lock_irqsave(&domain->lock, flags); | |
3360 | ||
3361 | /* | |
3362 | * Save us all sanity checks whether devices already in the | |
3363 | * domain support IOMMUv2. Just force that the domain has no | |
3364 | * devices attached when it is switched into IOMMUv2 mode. | |
3365 | */ | |
3366 | ret = -EBUSY; | |
3367 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3368 | goto out; | |
3369 | ||
3370 | ret = -ENOMEM; | |
3371 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3372 | if (domain->gcr3_tbl == NULL) | |
3373 | goto out; | |
3374 | ||
3375 | domain->glx = levels; | |
3376 | domain->flags |= PD_IOMMUV2_MASK; | |
3377 | domain->updated = true; | |
3378 | ||
3379 | update_domain(domain); | |
3380 | ||
3381 | ret = 0; | |
3382 | ||
3383 | out: | |
3384 | spin_unlock_irqrestore(&domain->lock, flags); | |
3385 | ||
3386 | return ret; | |
3387 | } | |
3388 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3389 | |
3390 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3391 | u64 address, bool size) | |
3392 | { | |
3393 | struct iommu_dev_data *dev_data; | |
3394 | struct iommu_cmd cmd; | |
3395 | int i, ret; | |
3396 | ||
3397 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3398 | return -EINVAL; | |
3399 | ||
3400 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3401 | ||
3402 | /* | |
3403 | * IOMMU TLB needs to be flushed before Device TLB to | |
3404 | * prevent device TLB refill from IOMMU TLB | |
3405 | */ | |
3406 | for (i = 0; i < amd_iommus_present; ++i) { | |
3407 | if (domain->dev_iommu[i] == 0) | |
3408 | continue; | |
3409 | ||
3410 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3411 | if (ret != 0) | |
3412 | goto out; | |
3413 | } | |
3414 | ||
3415 | /* Wait until IOMMU TLB flushes are complete */ | |
3416 | domain_flush_complete(domain); | |
3417 | ||
3418 | /* Now flush device TLBs */ | |
3419 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3420 | struct amd_iommu *iommu; | |
3421 | int qdep; | |
3422 | ||
3423 | BUG_ON(!dev_data->ats.enabled); | |
3424 | ||
3425 | qdep = dev_data->ats.qdep; | |
3426 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3427 | ||
3428 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3429 | qdep, address, size); | |
3430 | ||
3431 | ret = iommu_queue_command(iommu, &cmd); | |
3432 | if (ret != 0) | |
3433 | goto out; | |
3434 | } | |
3435 | ||
3436 | /* Wait until all device TLBs are flushed */ | |
3437 | domain_flush_complete(domain); | |
3438 | ||
3439 | ret = 0; | |
3440 | ||
3441 | out: | |
3442 | ||
3443 | return ret; | |
3444 | } | |
3445 | ||
3446 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3447 | u64 address) | |
3448 | { | |
399be2f5 JR |
3449 | INC_STATS_COUNTER(invalidate_iotlb); |
3450 | ||
22e266c7 JR |
3451 | return __flush_pasid(domain, pasid, address, false); |
3452 | } | |
3453 | ||
3454 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3455 | u64 address) | |
3456 | { | |
3457 | struct protection_domain *domain = dom->priv; | |
3458 | unsigned long flags; | |
3459 | int ret; | |
3460 | ||
3461 | spin_lock_irqsave(&domain->lock, flags); | |
3462 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3463 | spin_unlock_irqrestore(&domain->lock, flags); | |
3464 | ||
3465 | return ret; | |
3466 | } | |
3467 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3468 | ||
3469 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3470 | { | |
399be2f5 JR |
3471 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3472 | ||
22e266c7 JR |
3473 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3474 | true); | |
3475 | } | |
3476 | ||
3477 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3478 | { | |
3479 | struct protection_domain *domain = dom->priv; | |
3480 | unsigned long flags; | |
3481 | int ret; | |
3482 | ||
3483 | spin_lock_irqsave(&domain->lock, flags); | |
3484 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3485 | spin_unlock_irqrestore(&domain->lock, flags); | |
3486 | ||
3487 | return ret; | |
3488 | } | |
3489 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3490 | ||
b16137b1 JR |
3491 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3492 | { | |
3493 | int index; | |
3494 | u64 *pte; | |
3495 | ||
3496 | while (true) { | |
3497 | ||
3498 | index = (pasid >> (9 * level)) & 0x1ff; | |
3499 | pte = &root[index]; | |
3500 | ||
3501 | if (level == 0) | |
3502 | break; | |
3503 | ||
3504 | if (!(*pte & GCR3_VALID)) { | |
3505 | if (!alloc) | |
3506 | return NULL; | |
3507 | ||
3508 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3509 | if (root == NULL) | |
3510 | return NULL; | |
3511 | ||
3512 | *pte = __pa(root) | GCR3_VALID; | |
3513 | } | |
3514 | ||
3515 | root = __va(*pte & PAGE_MASK); | |
3516 | ||
3517 | level -= 1; | |
3518 | } | |
3519 | ||
3520 | return pte; | |
3521 | } | |
3522 | ||
3523 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3524 | unsigned long cr3) | |
3525 | { | |
3526 | u64 *pte; | |
3527 | ||
3528 | if (domain->mode != PAGE_MODE_NONE) | |
3529 | return -EINVAL; | |
3530 | ||
3531 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3532 | if (pte == NULL) | |
3533 | return -ENOMEM; | |
3534 | ||
3535 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3536 | ||
3537 | return __amd_iommu_flush_tlb(domain, pasid); | |
3538 | } | |
3539 | ||
3540 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3541 | { | |
3542 | u64 *pte; | |
3543 | ||
3544 | if (domain->mode != PAGE_MODE_NONE) | |
3545 | return -EINVAL; | |
3546 | ||
3547 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3548 | if (pte == NULL) | |
3549 | return 0; | |
3550 | ||
3551 | *pte = 0; | |
3552 | ||
3553 | return __amd_iommu_flush_tlb(domain, pasid); | |
3554 | } | |
3555 | ||
3556 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3557 | unsigned long cr3) | |
3558 | { | |
3559 | struct protection_domain *domain = dom->priv; | |
3560 | unsigned long flags; | |
3561 | int ret; | |
3562 | ||
3563 | spin_lock_irqsave(&domain->lock, flags); | |
3564 | ret = __set_gcr3(domain, pasid, cr3); | |
3565 | spin_unlock_irqrestore(&domain->lock, flags); | |
3566 | ||
3567 | return ret; | |
3568 | } | |
3569 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3570 | ||
3571 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3572 | { | |
3573 | struct protection_domain *domain = dom->priv; | |
3574 | unsigned long flags; | |
3575 | int ret; | |
3576 | ||
3577 | spin_lock_irqsave(&domain->lock, flags); | |
3578 | ret = __clear_gcr3(domain, pasid); | |
3579 | spin_unlock_irqrestore(&domain->lock, flags); | |
3580 | ||
3581 | return ret; | |
3582 | } | |
3583 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3584 | |
3585 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3586 | int status, int tag) | |
3587 | { | |
3588 | struct iommu_dev_data *dev_data; | |
3589 | struct amd_iommu *iommu; | |
3590 | struct iommu_cmd cmd; | |
3591 | ||
399be2f5 JR |
3592 | INC_STATS_COUNTER(complete_ppr); |
3593 | ||
c99afa25 JR |
3594 | dev_data = get_dev_data(&pdev->dev); |
3595 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3596 | ||
3597 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3598 | tag, dev_data->pri_tlp); | |
3599 | ||
3600 | return iommu_queue_command(iommu, &cmd); | |
3601 | } | |
3602 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3603 | |
3604 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3605 | { | |
3606 | struct protection_domain *domain; | |
3607 | ||
3608 | domain = get_domain(&pdev->dev); | |
3609 | if (IS_ERR(domain)) | |
3610 | return NULL; | |
3611 | ||
3612 | /* Only return IOMMUv2 domains */ | |
3613 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3614 | return NULL; | |
3615 | ||
3616 | return domain->iommu_domain; | |
3617 | } | |
3618 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3619 | |
3620 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3621 | { | |
3622 | struct iommu_dev_data *dev_data; | |
3623 | ||
3624 | if (!amd_iommu_v2_supported()) | |
3625 | return; | |
3626 | ||
3627 | dev_data = get_dev_data(&pdev->dev); | |
3628 | dev_data->errata |= (1 << erratum); | |
3629 | } | |
3630 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3631 | |
3632 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3633 | struct amd_iommu_device_info *info) | |
3634 | { | |
3635 | int max_pasids; | |
3636 | int pos; | |
3637 | ||
3638 | if (pdev == NULL || info == NULL) | |
3639 | return -EINVAL; | |
3640 | ||
3641 | if (!amd_iommu_v2_supported()) | |
3642 | return -EINVAL; | |
3643 | ||
3644 | memset(info, 0, sizeof(*info)); | |
3645 | ||
3646 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3647 | if (pos) | |
3648 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3649 | ||
3650 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3651 | if (pos) | |
3652 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3653 | ||
3654 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3655 | if (pos) { | |
3656 | int features; | |
3657 | ||
3658 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3659 | max_pasids = min(max_pasids, (1 << 20)); | |
3660 | ||
3661 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3662 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3663 | ||
3664 | features = pci_pasid_features(pdev); | |
3665 | if (features & PCI_PASID_CAP_EXEC) | |
3666 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3667 | if (features & PCI_PASID_CAP_PRIV) | |
3668 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3669 | } | |
3670 | ||
3671 | return 0; | |
3672 | } | |
3673 | EXPORT_SYMBOL(amd_iommu_device_info); |