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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
cb41ed85 | 23 | #include <linux/pci-ats.h> |
a66022c4 | 24 | #include <linux/bitmap.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
7f26508b | 26 | #include <linux/debugfs.h> |
b6c02715 | 27 | #include <linux/scatterlist.h> |
51491367 | 28 | #include <linux/dma-mapping.h> |
b6c02715 | 29 | #include <linux/iommu-helper.h> |
c156e347 | 30 | #include <linux/iommu.h> |
815b33fd | 31 | #include <linux/delay.h> |
403f81d8 | 32 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
33 | #include <linux/notifier.h> |
34 | #include <linux/export.h> | |
2b324506 JR |
35 | #include <linux/irq.h> |
36 | #include <linux/msi.h> | |
3b839a57 | 37 | #include <linux/dma-contiguous.h> |
7c71d306 | 38 | #include <linux/irqdomain.h> |
5f6bed50 | 39 | #include <linux/percpu.h> |
2b324506 JR |
40 | #include <asm/irq_remapping.h> |
41 | #include <asm/io_apic.h> | |
42 | #include <asm/apic.h> | |
43 | #include <asm/hw_irq.h> | |
17f5b569 | 44 | #include <asm/msidef.h> |
b6c02715 | 45 | #include <asm/proto.h> |
46a7fa27 | 46 | #include <asm/iommu.h> |
1d9b16d1 | 47 | #include <asm/gart.h> |
27c2127a | 48 | #include <asm/dma.h> |
403f81d8 JR |
49 | |
50 | #include "amd_iommu_proto.h" | |
51 | #include "amd_iommu_types.h" | |
6b474b82 | 52 | #include "irq_remapping.h" |
b6c02715 JR |
53 | |
54 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
55 | ||
815b33fd | 56 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 57 | |
aa3de9c0 OBC |
58 | /* |
59 | * This bitmap is used to advertise the page sizes our hardware support | |
60 | * to the IOMMU core, which will then use this information to split | |
61 | * physically contiguous memory regions it is mapping into page sizes | |
62 | * that we support. | |
63 | * | |
954e3dd8 | 64 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 65 | */ |
954e3dd8 | 66 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 67 | |
b6c02715 JR |
68 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
69 | ||
8fa5f802 JR |
70 | /* List of all available dev_data structures */ |
71 | static LIST_HEAD(dev_data_list); | |
72 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
73 | ||
6efed63b JR |
74 | LIST_HEAD(ioapic_map); |
75 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 76 | LIST_HEAD(acpihid_map); |
6efed63b | 77 | |
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
b22f6434 | 82 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 83 | |
72e1dcc4 | 84 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 85 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 86 | |
ac1534a5 JR |
87 | static struct dma_map_ops amd_iommu_dma_ops; |
88 | ||
50917e26 JR |
89 | /* |
90 | * This struct contains device specific data for the IOMMU | |
91 | */ | |
92 | struct iommu_dev_data { | |
93 | struct list_head list; /* For domain->dev_list */ | |
94 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 95 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 JR |
96 | u16 devid; /* PCI Device ID */ |
97 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
1e6a7b04 | 98 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
99 | struct { |
100 | bool enabled; | |
101 | int qdep; | |
102 | } ats; /* ATS state */ | |
103 | bool pri_tlp; /* PASID TLB required for | |
104 | PPR completions */ | |
105 | u32 errata; /* Bitmap for errata to apply */ | |
106 | }; | |
107 | ||
431b2a20 JR |
108 | /* |
109 | * general struct to manage commands send to an IOMMU | |
110 | */ | |
d6449536 | 111 | struct iommu_cmd { |
b6c02715 JR |
112 | u32 data[4]; |
113 | }; | |
114 | ||
05152a04 JR |
115 | struct kmem_cache *amd_iommu_irq_cache; |
116 | ||
04bfdd84 | 117 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 118 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 119 | static void detach_device(struct device *dev); |
c1eee67b | 120 | |
007b74ba JR |
121 | /* |
122 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
123 | * DMA address space each. This struct represents one such range. | |
124 | */ | |
125 | struct aperture_range { | |
126 | ||
08c5fb93 JR |
127 | spinlock_t bitmap_lock; |
128 | ||
007b74ba JR |
129 | /* address allocation bitmap */ |
130 | unsigned long *bitmap; | |
ae62d49c | 131 | unsigned long offset; |
60e6a7cb | 132 | unsigned long next_bit; |
007b74ba JR |
133 | |
134 | /* | |
135 | * Array of PTE pages for the aperture. In this array we save all the | |
136 | * leaf pages of the domain page table used for the aperture. This way | |
137 | * we don't need to walk the page table to find a specific PTE. We can | |
138 | * just calculate its address in constant time. | |
139 | */ | |
140 | u64 *pte_pages[64]; | |
007b74ba JR |
141 | }; |
142 | ||
143 | /* | |
144 | * Data container for a dma_ops specific protection domain | |
145 | */ | |
146 | struct dma_ops_domain { | |
147 | /* generic protection domain information */ | |
148 | struct protection_domain domain; | |
149 | ||
150 | /* size of the aperture for the mappings */ | |
151 | unsigned long aperture_size; | |
152 | ||
ebaecb42 | 153 | /* aperture index we start searching for free addresses */ |
5f6bed50 | 154 | u32 __percpu *next_index; |
007b74ba JR |
155 | |
156 | /* address space relevant data */ | |
157 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; | |
007b74ba JR |
158 | }; |
159 | ||
15898bbc JR |
160 | /**************************************************************************** |
161 | * | |
162 | * Helper functions | |
163 | * | |
164 | ****************************************************************************/ | |
165 | ||
3f4b87b9 JR |
166 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
167 | { | |
168 | return container_of(dom, struct protection_domain, domain); | |
169 | } | |
170 | ||
f62dda66 | 171 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
172 | { |
173 | struct iommu_dev_data *dev_data; | |
174 | unsigned long flags; | |
175 | ||
176 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
177 | if (!dev_data) | |
178 | return NULL; | |
179 | ||
f62dda66 | 180 | dev_data->devid = devid; |
8fa5f802 JR |
181 | |
182 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
183 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
184 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
185 | ||
186 | return dev_data; | |
187 | } | |
188 | ||
3b03bb74 JR |
189 | static struct iommu_dev_data *search_dev_data(u16 devid) |
190 | { | |
191 | struct iommu_dev_data *dev_data; | |
192 | unsigned long flags; | |
193 | ||
194 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
195 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
196 | if (dev_data->devid == devid) | |
197 | goto out_unlock; | |
198 | } | |
199 | ||
200 | dev_data = NULL; | |
201 | ||
202 | out_unlock: | |
203 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
204 | ||
205 | return dev_data; | |
206 | } | |
207 | ||
208 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
209 | { | |
210 | struct iommu_dev_data *dev_data; | |
211 | ||
212 | dev_data = search_dev_data(devid); | |
213 | ||
214 | if (dev_data == NULL) | |
215 | dev_data = alloc_dev_data(devid); | |
216 | ||
217 | return dev_data; | |
218 | } | |
219 | ||
2bf9a0a1 WZ |
220 | static inline int match_hid_uid(struct device *dev, |
221 | struct acpihid_map_entry *entry) | |
222 | { | |
223 | const char *hid, *uid; | |
224 | ||
225 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
226 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
227 | ||
228 | if (!hid || !(*hid)) | |
229 | return -ENODEV; | |
230 | ||
231 | if (!uid || !(*uid)) | |
232 | return strcmp(hid, entry->hid); | |
233 | ||
234 | if (!(*entry->uid)) | |
235 | return strcmp(hid, entry->hid); | |
236 | ||
237 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
238 | } | |
239 | ||
240 | static inline u16 get_pci_device_id(struct device *dev) | |
15898bbc JR |
241 | { |
242 | struct pci_dev *pdev = to_pci_dev(dev); | |
243 | ||
6f2729ba | 244 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
245 | } |
246 | ||
2bf9a0a1 WZ |
247 | static inline int get_acpihid_device_id(struct device *dev, |
248 | struct acpihid_map_entry **entry) | |
249 | { | |
250 | struct acpihid_map_entry *p; | |
251 | ||
252 | list_for_each_entry(p, &acpihid_map, list) { | |
253 | if (!match_hid_uid(dev, p)) { | |
254 | if (entry) | |
255 | *entry = p; | |
256 | return p->devid; | |
257 | } | |
258 | } | |
259 | return -EINVAL; | |
260 | } | |
261 | ||
262 | static inline int get_device_id(struct device *dev) | |
263 | { | |
264 | int devid; | |
265 | ||
266 | if (dev_is_pci(dev)) | |
267 | devid = get_pci_device_id(dev); | |
268 | else | |
269 | devid = get_acpihid_device_id(dev, NULL); | |
270 | ||
271 | return devid; | |
272 | } | |
273 | ||
657cbb6b JR |
274 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
275 | { | |
276 | return dev->archdata.iommu; | |
277 | } | |
278 | ||
b097d11a WZ |
279 | /* |
280 | * Find or create an IOMMU group for a acpihid device. | |
281 | */ | |
282 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
283 | { | |
284 | struct acpihid_map_entry *p, *entry = NULL; | |
285 | u16 devid; | |
286 | ||
287 | devid = get_acpihid_device_id(dev, &entry); | |
288 | if (devid < 0) | |
289 | return ERR_PTR(devid); | |
290 | ||
291 | list_for_each_entry(p, &acpihid_map, list) { | |
292 | if ((devid == p->devid) && p->group) | |
293 | entry->group = p->group; | |
294 | } | |
295 | ||
296 | if (!entry->group) | |
297 | entry->group = generic_device_group(dev); | |
298 | ||
299 | return entry->group; | |
300 | } | |
301 | ||
5abcdba4 JR |
302 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
303 | { | |
304 | static const int caps[] = { | |
305 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
306 | PCI_EXT_CAP_ID_PRI, |
307 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
308 | }; |
309 | int i, pos; | |
310 | ||
311 | for (i = 0; i < 3; ++i) { | |
312 | pos = pci_find_ext_capability(pdev, caps[i]); | |
313 | if (pos == 0) | |
314 | return false; | |
315 | } | |
316 | ||
317 | return true; | |
318 | } | |
319 | ||
6a113ddc JR |
320 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
321 | { | |
322 | struct iommu_dev_data *dev_data; | |
323 | ||
324 | dev_data = get_dev_data(&pdev->dev); | |
325 | ||
326 | return dev_data->errata & (1 << erratum) ? true : false; | |
327 | } | |
328 | ||
71c70984 | 329 | /* |
0bb6e243 JR |
330 | * This function actually applies the mapping to the page table of the |
331 | * dma_ops domain. | |
71c70984 | 332 | */ |
0bb6e243 JR |
333 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
334 | struct unity_map_entry *e) | |
71c70984 | 335 | { |
0bb6e243 | 336 | u64 addr; |
71c70984 | 337 | |
0bb6e243 JR |
338 | for (addr = e->address_start; addr < e->address_end; |
339 | addr += PAGE_SIZE) { | |
340 | if (addr < dma_dom->aperture_size) | |
341 | __set_bit(addr >> PAGE_SHIFT, | |
342 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 343 | } |
0bb6e243 | 344 | } |
71c70984 | 345 | |
0bb6e243 JR |
346 | /* |
347 | * Inits the unity mappings required for a specific device | |
348 | */ | |
349 | static void init_unity_mappings_for_device(struct device *dev, | |
350 | struct dma_ops_domain *dma_dom) | |
351 | { | |
352 | struct unity_map_entry *e; | |
7aba6cb9 | 353 | int devid; |
71c70984 | 354 | |
0bb6e243 | 355 | devid = get_device_id(dev); |
7aba6cb9 WZ |
356 | if (IS_ERR_VALUE(devid)) |
357 | return; | |
71c70984 | 358 | |
0bb6e243 JR |
359 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
360 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
361 | continue; | |
362 | alloc_unity_mapping(dma_dom, e); | |
363 | } | |
71c70984 JR |
364 | } |
365 | ||
98fc5a69 JR |
366 | /* |
367 | * This function checks if the driver got a valid device from the caller to | |
368 | * avoid dereferencing invalid pointers. | |
369 | */ | |
370 | static bool check_device(struct device *dev) | |
371 | { | |
7aba6cb9 | 372 | int devid; |
98fc5a69 JR |
373 | |
374 | if (!dev || !dev->dma_mask) | |
375 | return false; | |
376 | ||
98fc5a69 | 377 | devid = get_device_id(dev); |
7aba6cb9 WZ |
378 | if (IS_ERR_VALUE(devid)) |
379 | return false; | |
98fc5a69 JR |
380 | |
381 | /* Out of our scope? */ | |
382 | if (devid > amd_iommu_last_bdf) | |
383 | return false; | |
384 | ||
385 | if (amd_iommu_rlookup_table[devid] == NULL) | |
386 | return false; | |
387 | ||
388 | return true; | |
389 | } | |
390 | ||
25b11ce2 | 391 | static void init_iommu_group(struct device *dev) |
2851db21 | 392 | { |
0bb6e243 JR |
393 | struct dma_ops_domain *dma_domain; |
394 | struct iommu_domain *domain; | |
2851db21 | 395 | struct iommu_group *group; |
2851db21 | 396 | |
65d5352f | 397 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
398 | if (IS_ERR(group)) |
399 | return; | |
400 | ||
401 | domain = iommu_group_default_domain(group); | |
402 | if (!domain) | |
403 | goto out; | |
404 | ||
405 | dma_domain = to_pdomain(domain)->priv; | |
406 | ||
407 | init_unity_mappings_for_device(dev, dma_domain); | |
408 | out: | |
409 | iommu_group_put(group); | |
eb9c9527 AW |
410 | } |
411 | ||
412 | static int iommu_init_device(struct device *dev) | |
413 | { | |
eb9c9527 | 414 | struct iommu_dev_data *dev_data; |
7aba6cb9 | 415 | int devid; |
eb9c9527 AW |
416 | |
417 | if (dev->archdata.iommu) | |
418 | return 0; | |
419 | ||
7aba6cb9 WZ |
420 | devid = get_device_id(dev); |
421 | if (IS_ERR_VALUE(devid)) | |
422 | return devid; | |
423 | ||
424 | dev_data = find_dev_data(devid); | |
eb9c9527 AW |
425 | if (!dev_data) |
426 | return -ENOMEM; | |
427 | ||
2bf9a0a1 | 428 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
429 | struct amd_iommu *iommu; |
430 | ||
2bf9a0a1 | 431 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
432 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
433 | } | |
434 | ||
657cbb6b JR |
435 | dev->archdata.iommu = dev_data; |
436 | ||
066f2e98 AW |
437 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
438 | dev); | |
439 | ||
657cbb6b JR |
440 | return 0; |
441 | } | |
442 | ||
26018874 JR |
443 | static void iommu_ignore_device(struct device *dev) |
444 | { | |
7aba6cb9 WZ |
445 | u16 alias; |
446 | int devid; | |
26018874 JR |
447 | |
448 | devid = get_device_id(dev); | |
7aba6cb9 WZ |
449 | if (IS_ERR_VALUE(devid)) |
450 | return; | |
451 | ||
26018874 JR |
452 | alias = amd_iommu_alias_table[devid]; |
453 | ||
454 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
455 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
456 | ||
457 | amd_iommu_rlookup_table[devid] = NULL; | |
458 | amd_iommu_rlookup_table[alias] = NULL; | |
459 | } | |
460 | ||
657cbb6b JR |
461 | static void iommu_uninit_device(struct device *dev) |
462 | { | |
7aba6cb9 WZ |
463 | int devid; |
464 | struct iommu_dev_data *dev_data; | |
465 | ||
466 | devid = get_device_id(dev); | |
467 | if (IS_ERR_VALUE(devid)) | |
468 | return; | |
c1931090 | 469 | |
7aba6cb9 | 470 | dev_data = search_dev_data(devid); |
c1931090 AW |
471 | if (!dev_data) |
472 | return; | |
473 | ||
b6809ee5 JR |
474 | if (dev_data->domain) |
475 | detach_device(dev); | |
476 | ||
066f2e98 AW |
477 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
478 | dev); | |
479 | ||
9dcd6130 AW |
480 | iommu_group_remove_device(dev); |
481 | ||
aafd8ba0 JR |
482 | /* Remove dma-ops */ |
483 | dev->archdata.dma_ops = NULL; | |
484 | ||
8fa5f802 | 485 | /* |
c1931090 AW |
486 | * We keep dev_data around for unplugged devices and reuse it when the |
487 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 488 | */ |
657cbb6b | 489 | } |
b7cc9554 | 490 | |
7f26508b JR |
491 | #ifdef CONFIG_AMD_IOMMU_STATS |
492 | ||
493 | /* | |
494 | * Initialization code for statistics collection | |
495 | */ | |
496 | ||
da49f6df | 497 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 498 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 499 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 500 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 501 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 502 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 503 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 504 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 505 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 506 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 507 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 508 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
509 | DECLARE_STATS_COUNTER(complete_ppr); |
510 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
511 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
512 | DECLARE_STATS_COUNTER(pri_requests); | |
513 | ||
7f26508b | 514 | static struct dentry *stats_dir; |
7f26508b JR |
515 | static struct dentry *de_fflush; |
516 | ||
517 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
518 | { | |
519 | if (stats_dir == NULL) | |
520 | return; | |
521 | ||
522 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
523 | &cnt->value); | |
524 | } | |
525 | ||
526 | static void amd_iommu_stats_init(void) | |
527 | { | |
528 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
529 | if (stats_dir == NULL) | |
530 | return; | |
531 | ||
7f26508b | 532 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 533 | &amd_iommu_unmap_flush); |
da49f6df JR |
534 | |
535 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 536 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 537 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 538 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 539 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 540 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 541 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 542 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 543 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 544 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 545 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 546 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
547 | amd_iommu_stats_add(&complete_ppr); |
548 | amd_iommu_stats_add(&invalidate_iotlb); | |
549 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
550 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
551 | } |
552 | ||
553 | #endif | |
554 | ||
a80dc3e0 JR |
555 | /**************************************************************************** |
556 | * | |
557 | * Interrupt handling functions | |
558 | * | |
559 | ****************************************************************************/ | |
560 | ||
e3e59876 JR |
561 | static void dump_dte_entry(u16 devid) |
562 | { | |
563 | int i; | |
564 | ||
ee6c2868 JR |
565 | for (i = 0; i < 4; ++i) |
566 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
567 | amd_iommu_dev_table[devid].data[i]); |
568 | } | |
569 | ||
945b4ac4 JR |
570 | static void dump_command(unsigned long phys_addr) |
571 | { | |
572 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
573 | int i; | |
574 | ||
575 | for (i = 0; i < 4; ++i) | |
576 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
577 | } | |
578 | ||
a345b23b | 579 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 580 | { |
3d06fca8 JR |
581 | int type, devid, domid, flags; |
582 | volatile u32 *event = __evt; | |
583 | int count = 0; | |
584 | u64 address; | |
585 | ||
586 | retry: | |
587 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
588 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
589 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
590 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
591 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
592 | ||
593 | if (type == 0) { | |
594 | /* Did we hit the erratum? */ | |
595 | if (++count == LOOP_TIMEOUT) { | |
596 | pr_err("AMD-Vi: No event written to event log\n"); | |
597 | return; | |
598 | } | |
599 | udelay(1); | |
600 | goto retry; | |
601 | } | |
90008ee4 | 602 | |
4c6f40d4 | 603 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
604 | |
605 | switch (type) { | |
606 | case EVENT_TYPE_ILL_DEV: | |
607 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
608 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 609 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 610 | address, flags); |
e3e59876 | 611 | dump_dte_entry(devid); |
90008ee4 JR |
612 | break; |
613 | case EVENT_TYPE_IO_FAULT: | |
614 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
615 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 616 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
617 | domid, address, flags); |
618 | break; | |
619 | case EVENT_TYPE_DEV_TAB_ERR: | |
620 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
621 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 622 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
623 | address, flags); |
624 | break; | |
625 | case EVENT_TYPE_PAGE_TAB_ERR: | |
626 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
627 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 628 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
629 | domid, address, flags); |
630 | break; | |
631 | case EVENT_TYPE_ILL_CMD: | |
632 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 633 | dump_command(address); |
90008ee4 JR |
634 | break; |
635 | case EVENT_TYPE_CMD_HARD_ERR: | |
636 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
637 | "flags=0x%04x]\n", address, flags); | |
638 | break; | |
639 | case EVENT_TYPE_IOTLB_INV_TO: | |
640 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
641 | "address=0x%016llx]\n", | |
c5081cd7 | 642 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
643 | address); |
644 | break; | |
645 | case EVENT_TYPE_INV_DEV_REQ: | |
646 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
647 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 648 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
649 | address, flags); |
650 | break; | |
651 | default: | |
652 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
653 | } | |
3d06fca8 JR |
654 | |
655 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
656 | } |
657 | ||
658 | static void iommu_poll_events(struct amd_iommu *iommu) | |
659 | { | |
660 | u32 head, tail; | |
90008ee4 JR |
661 | |
662 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
663 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
664 | ||
665 | while (head != tail) { | |
a345b23b | 666 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 667 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
668 | } |
669 | ||
670 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
671 | } |
672 | ||
eee53537 | 673 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
674 | { |
675 | struct amd_iommu_fault fault; | |
72e1dcc4 | 676 | |
399be2f5 JR |
677 | INC_STATS_COUNTER(pri_requests); |
678 | ||
72e1dcc4 JR |
679 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
680 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
681 | return; | |
682 | } | |
683 | ||
684 | fault.address = raw[1]; | |
685 | fault.pasid = PPR_PASID(raw[0]); | |
686 | fault.device_id = PPR_DEVID(raw[0]); | |
687 | fault.tag = PPR_TAG(raw[0]); | |
688 | fault.flags = PPR_FLAGS(raw[0]); | |
689 | ||
72e1dcc4 JR |
690 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
691 | } | |
692 | ||
693 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
694 | { | |
72e1dcc4 JR |
695 | u32 head, tail; |
696 | ||
697 | if (iommu->ppr_log == NULL) | |
698 | return; | |
699 | ||
72e1dcc4 JR |
700 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
701 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
702 | ||
703 | while (head != tail) { | |
eee53537 JR |
704 | volatile u64 *raw; |
705 | u64 entry[2]; | |
706 | int i; | |
707 | ||
708 | raw = (u64 *)(iommu->ppr_log + head); | |
709 | ||
710 | /* | |
711 | * Hardware bug: Interrupt may arrive before the entry is | |
712 | * written to memory. If this happens we need to wait for the | |
713 | * entry to arrive. | |
714 | */ | |
715 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
716 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
717 | break; | |
718 | udelay(1); | |
719 | } | |
72e1dcc4 | 720 | |
eee53537 JR |
721 | /* Avoid memcpy function-call overhead */ |
722 | entry[0] = raw[0]; | |
723 | entry[1] = raw[1]; | |
72e1dcc4 | 724 | |
eee53537 JR |
725 | /* |
726 | * To detect the hardware bug we need to clear the entry | |
727 | * back to zero. | |
728 | */ | |
729 | raw[0] = raw[1] = 0UL; | |
730 | ||
731 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
732 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
733 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 734 | |
eee53537 JR |
735 | /* Handle PPR entry */ |
736 | iommu_handle_ppr_entry(iommu, entry); | |
737 | ||
eee53537 JR |
738 | /* Refresh ring-buffer information */ |
739 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
740 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
741 | } | |
72e1dcc4 JR |
742 | } |
743 | ||
72fe00f0 | 744 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 745 | { |
3f398bc7 SS |
746 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
747 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 748 | |
3f398bc7 SS |
749 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
750 | /* Enable EVT and PPR interrupts again */ | |
751 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
752 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 753 | |
3f398bc7 SS |
754 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
755 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
756 | iommu_poll_events(iommu); | |
757 | } | |
90008ee4 | 758 | |
3f398bc7 SS |
759 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
760 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
761 | iommu_poll_ppr_log(iommu); | |
762 | } | |
90008ee4 | 763 | |
3f398bc7 SS |
764 | /* |
765 | * Hardware bug: ERBT1312 | |
766 | * When re-enabling interrupt (by writing 1 | |
767 | * to clear the bit), the hardware might also try to set | |
768 | * the interrupt bit in the event status register. | |
769 | * In this scenario, the bit will be set, and disable | |
770 | * subsequent interrupts. | |
771 | * | |
772 | * Workaround: The IOMMU driver should read back the | |
773 | * status register and check if the interrupt bits are cleared. | |
774 | * If not, driver will need to go through the interrupt handler | |
775 | * again and re-clear the bits | |
776 | */ | |
777 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
778 | } | |
90008ee4 | 779 | return IRQ_HANDLED; |
a80dc3e0 JR |
780 | } |
781 | ||
72fe00f0 JR |
782 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
783 | { | |
784 | return IRQ_WAKE_THREAD; | |
785 | } | |
786 | ||
431b2a20 JR |
787 | /**************************************************************************** |
788 | * | |
789 | * IOMMU command queuing functions | |
790 | * | |
791 | ****************************************************************************/ | |
792 | ||
ac0ea6e9 JR |
793 | static int wait_on_sem(volatile u64 *sem) |
794 | { | |
795 | int i = 0; | |
796 | ||
797 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
798 | udelay(1); | |
799 | i += 1; | |
800 | } | |
801 | ||
802 | if (i == LOOP_TIMEOUT) { | |
803 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
804 | return -EIO; | |
805 | } | |
806 | ||
807 | return 0; | |
808 | } | |
809 | ||
810 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
811 | struct iommu_cmd *cmd, | |
812 | u32 tail) | |
a19ae1ec | 813 | { |
a19ae1ec JR |
814 | u8 *target; |
815 | ||
8a7c5ef3 | 816 | target = iommu->cmd_buf + tail; |
deba4bce | 817 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
818 | |
819 | /* Copy command to buffer */ | |
820 | memcpy(target, cmd, sizeof(*cmd)); | |
821 | ||
822 | /* Tell the IOMMU about it */ | |
a19ae1ec | 823 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 824 | } |
a19ae1ec | 825 | |
815b33fd | 826 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 827 | { |
815b33fd JR |
828 | WARN_ON(address & 0x7ULL); |
829 | ||
ded46737 | 830 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
831 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
832 | cmd->data[1] = upper_32_bits(__pa(address)); | |
833 | cmd->data[2] = 1; | |
ded46737 JR |
834 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
835 | } | |
836 | ||
94fe79e2 JR |
837 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
838 | { | |
839 | memset(cmd, 0, sizeof(*cmd)); | |
840 | cmd->data[0] = devid; | |
841 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
842 | } | |
843 | ||
11b6402c JR |
844 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
845 | size_t size, u16 domid, int pde) | |
846 | { | |
847 | u64 pages; | |
ae0cbbb1 | 848 | bool s; |
11b6402c JR |
849 | |
850 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 851 | s = false; |
11b6402c JR |
852 | |
853 | if (pages > 1) { | |
854 | /* | |
855 | * If we have to flush more than one page, flush all | |
856 | * TLB entries for this domain | |
857 | */ | |
858 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 859 | s = true; |
11b6402c JR |
860 | } |
861 | ||
862 | address &= PAGE_MASK; | |
863 | ||
864 | memset(cmd, 0, sizeof(*cmd)); | |
865 | cmd->data[1] |= domid; | |
866 | cmd->data[2] = lower_32_bits(address); | |
867 | cmd->data[3] = upper_32_bits(address); | |
868 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
869 | if (s) /* size bit - we flush more than one 4kb page */ | |
870 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 871 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
872 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
873 | } | |
874 | ||
cb41ed85 JR |
875 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
876 | u64 address, size_t size) | |
877 | { | |
878 | u64 pages; | |
ae0cbbb1 | 879 | bool s; |
cb41ed85 JR |
880 | |
881 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 882 | s = false; |
cb41ed85 JR |
883 | |
884 | if (pages > 1) { | |
885 | /* | |
886 | * If we have to flush more than one page, flush all | |
887 | * TLB entries for this domain | |
888 | */ | |
889 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 890 | s = true; |
cb41ed85 JR |
891 | } |
892 | ||
893 | address &= PAGE_MASK; | |
894 | ||
895 | memset(cmd, 0, sizeof(*cmd)); | |
896 | cmd->data[0] = devid; | |
897 | cmd->data[0] |= (qdep & 0xff) << 24; | |
898 | cmd->data[1] = devid; | |
899 | cmd->data[2] = lower_32_bits(address); | |
900 | cmd->data[3] = upper_32_bits(address); | |
901 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
902 | if (s) | |
903 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
904 | } | |
905 | ||
22e266c7 JR |
906 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
907 | u64 address, bool size) | |
908 | { | |
909 | memset(cmd, 0, sizeof(*cmd)); | |
910 | ||
911 | address &= ~(0xfffULL); | |
912 | ||
a919a018 | 913 | cmd->data[0] = pasid; |
22e266c7 JR |
914 | cmd->data[1] = domid; |
915 | cmd->data[2] = lower_32_bits(address); | |
916 | cmd->data[3] = upper_32_bits(address); | |
917 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
918 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
919 | if (size) | |
920 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
921 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
922 | } | |
923 | ||
924 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
925 | int qdep, u64 address, bool size) | |
926 | { | |
927 | memset(cmd, 0, sizeof(*cmd)); | |
928 | ||
929 | address &= ~(0xfffULL); | |
930 | ||
931 | cmd->data[0] = devid; | |
e8d2d82d | 932 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
933 | cmd->data[0] |= (qdep & 0xff) << 24; |
934 | cmd->data[1] = devid; | |
e8d2d82d | 935 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
936 | cmd->data[2] = lower_32_bits(address); |
937 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
938 | cmd->data[3] = upper_32_bits(address); | |
939 | if (size) | |
940 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
941 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
942 | } | |
943 | ||
c99afa25 JR |
944 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
945 | int status, int tag, bool gn) | |
946 | { | |
947 | memset(cmd, 0, sizeof(*cmd)); | |
948 | ||
949 | cmd->data[0] = devid; | |
950 | if (gn) { | |
a919a018 | 951 | cmd->data[1] = pasid; |
c99afa25 JR |
952 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
953 | } | |
954 | cmd->data[3] = tag & 0x1ff; | |
955 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
956 | ||
957 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
958 | } | |
959 | ||
58fc7f14 JR |
960 | static void build_inv_all(struct iommu_cmd *cmd) |
961 | { | |
962 | memset(cmd, 0, sizeof(*cmd)); | |
963 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
964 | } |
965 | ||
7ef2798d JR |
966 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
967 | { | |
968 | memset(cmd, 0, sizeof(*cmd)); | |
969 | cmd->data[0] = devid; | |
970 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
971 | } | |
972 | ||
431b2a20 | 973 | /* |
431b2a20 | 974 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 975 | * hardware about the new command. |
431b2a20 | 976 | */ |
f1ca1512 JR |
977 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
978 | struct iommu_cmd *cmd, | |
979 | bool sync) | |
a19ae1ec | 980 | { |
ac0ea6e9 | 981 | u32 left, tail, head, next_tail; |
a19ae1ec | 982 | unsigned long flags; |
a19ae1ec | 983 | |
ac0ea6e9 | 984 | again: |
a19ae1ec | 985 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 986 | |
ac0ea6e9 JR |
987 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
988 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
989 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
990 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 991 | |
ac0ea6e9 JR |
992 | if (left <= 2) { |
993 | struct iommu_cmd sync_cmd; | |
994 | volatile u64 sem = 0; | |
995 | int ret; | |
8d201968 | 996 | |
ac0ea6e9 JR |
997 | build_completion_wait(&sync_cmd, (u64)&sem); |
998 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 999 | |
ac0ea6e9 JR |
1000 | spin_unlock_irqrestore(&iommu->lock, flags); |
1001 | ||
1002 | if ((ret = wait_on_sem(&sem)) != 0) | |
1003 | return ret; | |
1004 | ||
1005 | goto again; | |
8d201968 JR |
1006 | } |
1007 | ||
ac0ea6e9 JR |
1008 | copy_cmd_to_buffer(iommu, cmd, tail); |
1009 | ||
1010 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1011 | iommu->need_sync = sync; |
ac0ea6e9 | 1012 | |
a19ae1ec | 1013 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1014 | |
815b33fd | 1015 | return 0; |
8d201968 JR |
1016 | } |
1017 | ||
f1ca1512 JR |
1018 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1019 | { | |
1020 | return iommu_queue_command_sync(iommu, cmd, true); | |
1021 | } | |
1022 | ||
8d201968 JR |
1023 | /* |
1024 | * This function queues a completion wait command into the command | |
1025 | * buffer of an IOMMU | |
1026 | */ | |
a19ae1ec | 1027 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1028 | { |
1029 | struct iommu_cmd cmd; | |
815b33fd | 1030 | volatile u64 sem = 0; |
ac0ea6e9 | 1031 | int ret; |
8d201968 | 1032 | |
09ee17eb | 1033 | if (!iommu->need_sync) |
815b33fd | 1034 | return 0; |
09ee17eb | 1035 | |
815b33fd | 1036 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1037 | |
f1ca1512 | 1038 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1039 | if (ret) |
815b33fd | 1040 | return ret; |
8d201968 | 1041 | |
ac0ea6e9 | 1042 | return wait_on_sem(&sem); |
8d201968 JR |
1043 | } |
1044 | ||
d8c13085 | 1045 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1046 | { |
d8c13085 | 1047 | struct iommu_cmd cmd; |
a19ae1ec | 1048 | |
d8c13085 | 1049 | build_inv_dte(&cmd, devid); |
7e4f88da | 1050 | |
d8c13085 JR |
1051 | return iommu_queue_command(iommu, &cmd); |
1052 | } | |
09ee17eb | 1053 | |
7d0c5cc5 JR |
1054 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1055 | { | |
1056 | u32 devid; | |
09ee17eb | 1057 | |
7d0c5cc5 JR |
1058 | for (devid = 0; devid <= 0xffff; ++devid) |
1059 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1060 | |
7d0c5cc5 JR |
1061 | iommu_completion_wait(iommu); |
1062 | } | |
84df8175 | 1063 | |
7d0c5cc5 JR |
1064 | /* |
1065 | * This function uses heavy locking and may disable irqs for some time. But | |
1066 | * this is no issue because it is only called during resume. | |
1067 | */ | |
1068 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1069 | { | |
1070 | u32 dom_id; | |
a19ae1ec | 1071 | |
7d0c5cc5 JR |
1072 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1073 | struct iommu_cmd cmd; | |
1074 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1075 | dom_id, 1); | |
1076 | iommu_queue_command(iommu, &cmd); | |
1077 | } | |
8eed9833 | 1078 | |
7d0c5cc5 | 1079 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1080 | } |
1081 | ||
58fc7f14 | 1082 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1083 | { |
58fc7f14 | 1084 | struct iommu_cmd cmd; |
0518a3a4 | 1085 | |
58fc7f14 | 1086 | build_inv_all(&cmd); |
0518a3a4 | 1087 | |
58fc7f14 JR |
1088 | iommu_queue_command(iommu, &cmd); |
1089 | iommu_completion_wait(iommu); | |
1090 | } | |
1091 | ||
7ef2798d JR |
1092 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1093 | { | |
1094 | struct iommu_cmd cmd; | |
1095 | ||
1096 | build_inv_irt(&cmd, devid); | |
1097 | ||
1098 | iommu_queue_command(iommu, &cmd); | |
1099 | } | |
1100 | ||
1101 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1102 | { | |
1103 | u32 devid; | |
1104 | ||
1105 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1106 | iommu_flush_irt(iommu, devid); | |
1107 | ||
1108 | iommu_completion_wait(iommu); | |
1109 | } | |
1110 | ||
7d0c5cc5 JR |
1111 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1112 | { | |
58fc7f14 JR |
1113 | if (iommu_feature(iommu, FEATURE_IA)) { |
1114 | iommu_flush_all(iommu); | |
1115 | } else { | |
1116 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1117 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1118 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1119 | } |
1120 | } | |
1121 | ||
431b2a20 | 1122 | /* |
cb41ed85 | 1123 | * Command send function for flushing on-device TLB |
431b2a20 | 1124 | */ |
6c542047 JR |
1125 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1126 | u64 address, size_t size) | |
3fa43655 JR |
1127 | { |
1128 | struct amd_iommu *iommu; | |
b00d3bcf | 1129 | struct iommu_cmd cmd; |
cb41ed85 | 1130 | int qdep; |
3fa43655 | 1131 | |
ea61cddb JR |
1132 | qdep = dev_data->ats.qdep; |
1133 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1134 | |
ea61cddb | 1135 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1136 | |
1137 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1138 | } |
1139 | ||
431b2a20 | 1140 | /* |
431b2a20 | 1141 | * Command send function for invalidating a device table entry |
431b2a20 | 1142 | */ |
6c542047 | 1143 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1144 | { |
3fa43655 | 1145 | struct amd_iommu *iommu; |
e25bfb56 | 1146 | u16 alias; |
ee2fa743 | 1147 | int ret; |
a19ae1ec | 1148 | |
6c542047 | 1149 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 1150 | alias = amd_iommu_alias_table[dev_data->devid]; |
a19ae1ec | 1151 | |
f62dda66 | 1152 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1153 | if (!ret && alias != dev_data->devid) |
1154 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1155 | if (ret) |
1156 | return ret; | |
1157 | ||
ea61cddb | 1158 | if (dev_data->ats.enabled) |
6c542047 | 1159 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1160 | |
ee2fa743 | 1161 | return ret; |
a19ae1ec JR |
1162 | } |
1163 | ||
431b2a20 JR |
1164 | /* |
1165 | * TLB invalidation function which is called from the mapping functions. | |
1166 | * It invalidates a single PTE if the range to flush is within a single | |
1167 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1168 | */ | |
17b124bf JR |
1169 | static void __domain_flush_pages(struct protection_domain *domain, |
1170 | u64 address, size_t size, int pde) | |
a19ae1ec | 1171 | { |
cb41ed85 | 1172 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1173 | struct iommu_cmd cmd; |
1174 | int ret = 0, i; | |
a19ae1ec | 1175 | |
11b6402c | 1176 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1177 | |
6de8ad9b JR |
1178 | for (i = 0; i < amd_iommus_present; ++i) { |
1179 | if (!domain->dev_iommu[i]) | |
1180 | continue; | |
1181 | ||
1182 | /* | |
1183 | * Devices of this domain are behind this IOMMU | |
1184 | * We need a TLB flush | |
1185 | */ | |
11b6402c | 1186 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1187 | } |
1188 | ||
cb41ed85 | 1189 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1190 | |
ea61cddb | 1191 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1192 | continue; |
1193 | ||
6c542047 | 1194 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1195 | } |
1196 | ||
11b6402c | 1197 | WARN_ON(ret); |
6de8ad9b JR |
1198 | } |
1199 | ||
17b124bf JR |
1200 | static void domain_flush_pages(struct protection_domain *domain, |
1201 | u64 address, size_t size) | |
6de8ad9b | 1202 | { |
17b124bf | 1203 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1204 | } |
b6c02715 | 1205 | |
1c655773 | 1206 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1207 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1208 | { |
17b124bf | 1209 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1210 | } |
1211 | ||
42a49f96 | 1212 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1213 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1214 | { |
17b124bf | 1215 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1216 | } |
1217 | ||
17b124bf | 1218 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1219 | { |
17b124bf | 1220 | int i; |
18811f55 | 1221 | |
17b124bf JR |
1222 | for (i = 0; i < amd_iommus_present; ++i) { |
1223 | if (!domain->dev_iommu[i]) | |
1224 | continue; | |
bfd1be18 | 1225 | |
17b124bf JR |
1226 | /* |
1227 | * Devices of this domain are behind this IOMMU | |
1228 | * We need to wait for completion of all commands. | |
1229 | */ | |
1230 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1231 | } |
e394d72a JR |
1232 | } |
1233 | ||
b00d3bcf | 1234 | |
09b42804 | 1235 | /* |
b00d3bcf | 1236 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1237 | */ |
17b124bf | 1238 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1239 | { |
b00d3bcf | 1240 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1241 | |
b00d3bcf | 1242 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1243 | device_flush_dte(dev_data); |
a345b23b JR |
1244 | } |
1245 | ||
431b2a20 JR |
1246 | /**************************************************************************** |
1247 | * | |
1248 | * The functions below are used the create the page table mappings for | |
1249 | * unity mapped regions. | |
1250 | * | |
1251 | ****************************************************************************/ | |
1252 | ||
308973d3 JR |
1253 | /* |
1254 | * This function is used to add another level to an IO page table. Adding | |
1255 | * another level increases the size of the address space by 9 bits to a size up | |
1256 | * to 64 bits. | |
1257 | */ | |
1258 | static bool increase_address_space(struct protection_domain *domain, | |
1259 | gfp_t gfp) | |
1260 | { | |
1261 | u64 *pte; | |
1262 | ||
1263 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1264 | /* address space already 64 bit large */ | |
1265 | return false; | |
1266 | ||
1267 | pte = (void *)get_zeroed_page(gfp); | |
1268 | if (!pte) | |
1269 | return false; | |
1270 | ||
1271 | *pte = PM_LEVEL_PDE(domain->mode, | |
1272 | virt_to_phys(domain->pt_root)); | |
1273 | domain->pt_root = pte; | |
1274 | domain->mode += 1; | |
1275 | domain->updated = true; | |
1276 | ||
1277 | return true; | |
1278 | } | |
1279 | ||
1280 | static u64 *alloc_pte(struct protection_domain *domain, | |
1281 | unsigned long address, | |
cbb9d729 | 1282 | unsigned long page_size, |
308973d3 JR |
1283 | u64 **pte_page, |
1284 | gfp_t gfp) | |
1285 | { | |
cbb9d729 | 1286 | int level, end_lvl; |
308973d3 | 1287 | u64 *pte, *page; |
cbb9d729 JR |
1288 | |
1289 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1290 | |
1291 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1292 | increase_address_space(domain, gfp); | |
1293 | ||
cbb9d729 JR |
1294 | level = domain->mode - 1; |
1295 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1296 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1297 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1298 | |
1299 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1300 | u64 __pte, __npte; |
1301 | ||
1302 | __pte = *pte; | |
1303 | ||
1304 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1305 | page = (u64 *)get_zeroed_page(gfp); |
1306 | if (!page) | |
1307 | return NULL; | |
7bfa5bd2 JR |
1308 | |
1309 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1310 | ||
1311 | if (cmpxchg64(pte, __pte, __npte)) { | |
1312 | free_page((unsigned long)page); | |
1313 | continue; | |
1314 | } | |
308973d3 JR |
1315 | } |
1316 | ||
cbb9d729 JR |
1317 | /* No level skipping support yet */ |
1318 | if (PM_PTE_LEVEL(*pte) != level) | |
1319 | return NULL; | |
1320 | ||
308973d3 JR |
1321 | level -= 1; |
1322 | ||
1323 | pte = IOMMU_PTE_PAGE(*pte); | |
1324 | ||
1325 | if (pte_page && level == end_lvl) | |
1326 | *pte_page = pte; | |
1327 | ||
1328 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1329 | } | |
1330 | ||
1331 | return pte; | |
1332 | } | |
1333 | ||
1334 | /* | |
1335 | * This function checks if there is a PTE for a given dma address. If | |
1336 | * there is one, it returns the pointer to it. | |
1337 | */ | |
3039ca1b JR |
1338 | static u64 *fetch_pte(struct protection_domain *domain, |
1339 | unsigned long address, | |
1340 | unsigned long *page_size) | |
308973d3 JR |
1341 | { |
1342 | int level; | |
1343 | u64 *pte; | |
1344 | ||
24cd7723 JR |
1345 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1346 | return NULL; | |
1347 | ||
3039ca1b JR |
1348 | level = domain->mode - 1; |
1349 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1350 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1351 | |
24cd7723 JR |
1352 | while (level > 0) { |
1353 | ||
1354 | /* Not Present */ | |
308973d3 JR |
1355 | if (!IOMMU_PTE_PRESENT(*pte)) |
1356 | return NULL; | |
1357 | ||
24cd7723 | 1358 | /* Large PTE */ |
3039ca1b JR |
1359 | if (PM_PTE_LEVEL(*pte) == 7 || |
1360 | PM_PTE_LEVEL(*pte) == 0) | |
1361 | break; | |
24cd7723 JR |
1362 | |
1363 | /* No level skipping support yet */ | |
1364 | if (PM_PTE_LEVEL(*pte) != level) | |
1365 | return NULL; | |
1366 | ||
308973d3 JR |
1367 | level -= 1; |
1368 | ||
24cd7723 | 1369 | /* Walk to the next level */ |
3039ca1b JR |
1370 | pte = IOMMU_PTE_PAGE(*pte); |
1371 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1372 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1373 | } | |
1374 | ||
1375 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1376 | unsigned long pte_mask; | |
1377 | ||
1378 | /* | |
1379 | * If we have a series of large PTEs, make | |
1380 | * sure to return a pointer to the first one. | |
1381 | */ | |
1382 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1383 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1384 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1385 | } |
1386 | ||
1387 | return pte; | |
1388 | } | |
1389 | ||
431b2a20 JR |
1390 | /* |
1391 | * Generic mapping functions. It maps a physical address into a DMA | |
1392 | * address space. It allocates the page table pages if necessary. | |
1393 | * In the future it can be extended to a generic mapping function | |
1394 | * supporting all features of AMD IOMMU page tables like level skipping | |
1395 | * and full 64 bit address spaces. | |
1396 | */ | |
38e817fe JR |
1397 | static int iommu_map_page(struct protection_domain *dom, |
1398 | unsigned long bus_addr, | |
1399 | unsigned long phys_addr, | |
abdc5eb3 | 1400 | int prot, |
cbb9d729 | 1401 | unsigned long page_size) |
bd0e5211 | 1402 | { |
8bda3092 | 1403 | u64 __pte, *pte; |
cbb9d729 | 1404 | int i, count; |
abdc5eb3 | 1405 | |
d4b03664 JR |
1406 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1407 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1408 | ||
bad1cac2 | 1409 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1410 | return -EINVAL; |
1411 | ||
d4b03664 JR |
1412 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1413 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1414 | |
63eaa75e ML |
1415 | if (!pte) |
1416 | return -ENOMEM; | |
1417 | ||
cbb9d729 JR |
1418 | for (i = 0; i < count; ++i) |
1419 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1420 | return -EBUSY; | |
bd0e5211 | 1421 | |
d4b03664 | 1422 | if (count > 1) { |
cbb9d729 JR |
1423 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1424 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1425 | } else | |
1426 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1427 | |
bd0e5211 JR |
1428 | if (prot & IOMMU_PROT_IR) |
1429 | __pte |= IOMMU_PTE_IR; | |
1430 | if (prot & IOMMU_PROT_IW) | |
1431 | __pte |= IOMMU_PTE_IW; | |
1432 | ||
cbb9d729 JR |
1433 | for (i = 0; i < count; ++i) |
1434 | pte[i] = __pte; | |
bd0e5211 | 1435 | |
04bfdd84 JR |
1436 | update_domain(dom); |
1437 | ||
bd0e5211 JR |
1438 | return 0; |
1439 | } | |
1440 | ||
24cd7723 JR |
1441 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1442 | unsigned long bus_addr, | |
1443 | unsigned long page_size) | |
eb74ff6c | 1444 | { |
71b390e9 JR |
1445 | unsigned long long unmapped; |
1446 | unsigned long unmap_size; | |
24cd7723 JR |
1447 | u64 *pte; |
1448 | ||
1449 | BUG_ON(!is_power_of_2(page_size)); | |
1450 | ||
1451 | unmapped = 0; | |
eb74ff6c | 1452 | |
24cd7723 JR |
1453 | while (unmapped < page_size) { |
1454 | ||
71b390e9 JR |
1455 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1456 | ||
1457 | if (pte) { | |
1458 | int i, count; | |
1459 | ||
1460 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1461 | for (i = 0; i < count; i++) |
1462 | pte[i] = 0ULL; | |
1463 | } | |
1464 | ||
1465 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1466 | unmapped += unmap_size; | |
1467 | } | |
1468 | ||
60d0ca3c | 1469 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1470 | |
24cd7723 | 1471 | return unmapped; |
eb74ff6c | 1472 | } |
eb74ff6c | 1473 | |
431b2a20 JR |
1474 | /**************************************************************************** |
1475 | * | |
1476 | * The next functions belong to the address allocator for the dma_ops | |
1477 | * interface functions. They work like the allocators in the other IOMMU | |
1478 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1479 | * the aperture. Maybe it could be enhanced in the future to a more | |
1480 | * efficient allocator. | |
1481 | * | |
1482 | ****************************************************************************/ | |
d3086444 | 1483 | |
431b2a20 | 1484 | /* |
384de729 | 1485 | * The address allocator core functions. |
431b2a20 JR |
1486 | * |
1487 | * called with domain->lock held | |
1488 | */ | |
384de729 | 1489 | |
171e7b37 JR |
1490 | /* |
1491 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1492 | * ranges. | |
1493 | */ | |
1494 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1495 | unsigned long start_page, | |
1496 | unsigned int pages) | |
1497 | { | |
1498 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1499 | ||
1500 | if (start_page + pages > last_page) | |
1501 | pages = last_page - start_page; | |
1502 | ||
1503 | for (i = start_page; i < start_page + pages; ++i) { | |
1504 | int index = i / APERTURE_RANGE_PAGES; | |
1505 | int page = i % APERTURE_RANGE_PAGES; | |
1506 | __set_bit(page, dom->aperture[index]->bitmap); | |
1507 | } | |
1508 | } | |
1509 | ||
9cabe89b JR |
1510 | /* |
1511 | * This function is used to add a new aperture range to an existing | |
1512 | * aperture in case of dma_ops domain allocation or address allocation | |
1513 | * failure. | |
1514 | */ | |
576175c2 | 1515 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1516 | bool populate, gfp_t gfp) |
1517 | { | |
1518 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
5d7c94c3 | 1519 | unsigned long i, old_size, pte_pgsize; |
a73c1566 JR |
1520 | struct aperture_range *range; |
1521 | struct amd_iommu *iommu; | |
1522 | unsigned long flags; | |
9cabe89b | 1523 | |
f5e9705c JR |
1524 | #ifdef CONFIG_IOMMU_STRESS |
1525 | populate = false; | |
1526 | #endif | |
1527 | ||
9cabe89b JR |
1528 | if (index >= APERTURE_MAX_RANGES) |
1529 | return -ENOMEM; | |
1530 | ||
a73c1566 JR |
1531 | range = kzalloc(sizeof(struct aperture_range), gfp); |
1532 | if (!range) | |
9cabe89b JR |
1533 | return -ENOMEM; |
1534 | ||
a73c1566 JR |
1535 | range->bitmap = (void *)get_zeroed_page(gfp); |
1536 | if (!range->bitmap) | |
9cabe89b JR |
1537 | goto out_free; |
1538 | ||
a73c1566 | 1539 | range->offset = dma_dom->aperture_size; |
9cabe89b | 1540 | |
a73c1566 | 1541 | spin_lock_init(&range->bitmap_lock); |
08c5fb93 | 1542 | |
9cabe89b JR |
1543 | if (populate) { |
1544 | unsigned long address = dma_dom->aperture_size; | |
1545 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1546 | u64 *pte, *pte_page; | |
1547 | ||
1548 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1549 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1550 | &pte_page, gfp); |
1551 | if (!pte) | |
1552 | goto out_free; | |
1553 | ||
a73c1566 | 1554 | range->pte_pages[i] = pte_page; |
9cabe89b JR |
1555 | |
1556 | address += APERTURE_RANGE_SIZE / 64; | |
1557 | } | |
1558 | } | |
1559 | ||
92d420ec JR |
1560 | spin_lock_irqsave(&dma_dom->domain.lock, flags); |
1561 | ||
a73c1566 | 1562 | /* First take the bitmap_lock and then publish the range */ |
92d420ec | 1563 | spin_lock(&range->bitmap_lock); |
a73c1566 JR |
1564 | |
1565 | old_size = dma_dom->aperture_size; | |
1566 | dma_dom->aperture[index] = range; | |
1567 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
9cabe89b | 1568 | |
17f5b569 JR |
1569 | /* Reserve address range used for MSI messages */ |
1570 | if (old_size < MSI_ADDR_BASE_LO && | |
1571 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1572 | unsigned long spage; | |
1573 | int pages; | |
1574 | ||
1575 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1576 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1577 | ||
1578 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1579 | } | |
1580 | ||
b595076a | 1581 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1582 | for_each_iommu(iommu) { |
1583 | if (iommu->exclusion_start && | |
1584 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1585 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1586 | unsigned long startpage; | |
1587 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1588 | iommu->exclusion_length, | |
1589 | PAGE_SIZE); | |
1590 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1591 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1592 | } | |
00cd122a JR |
1593 | } |
1594 | ||
1595 | /* | |
1596 | * Check for areas already mapped as present in the new aperture | |
1597 | * range and mark those pages as reserved in the allocator. Such | |
1598 | * mappings may already exist as a result of requested unity | |
1599 | * mappings for devices. | |
1600 | */ | |
1601 | for (i = dma_dom->aperture[index]->offset; | |
1602 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1603 | i += pte_pgsize) { |
3039ca1b | 1604 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1605 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1606 | continue; | |
1607 | ||
5d7c94c3 JR |
1608 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1609 | pte_pgsize >> 12); | |
00cd122a JR |
1610 | } |
1611 | ||
04bfdd84 JR |
1612 | update_domain(&dma_dom->domain); |
1613 | ||
92d420ec JR |
1614 | spin_unlock(&range->bitmap_lock); |
1615 | ||
1616 | spin_unlock_irqrestore(&dma_dom->domain.lock, flags); | |
a73c1566 | 1617 | |
9cabe89b JR |
1618 | return 0; |
1619 | ||
1620 | out_free: | |
04bfdd84 JR |
1621 | update_domain(&dma_dom->domain); |
1622 | ||
a73c1566 | 1623 | free_page((unsigned long)range->bitmap); |
9cabe89b | 1624 | |
a73c1566 | 1625 | kfree(range); |
9cabe89b JR |
1626 | |
1627 | return -ENOMEM; | |
1628 | } | |
1629 | ||
ccb50e03 JR |
1630 | static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom, |
1631 | struct aperture_range *range, | |
a0f51447 | 1632 | unsigned long pages, |
a0f51447 JR |
1633 | unsigned long dma_mask, |
1634 | unsigned long boundary_size, | |
7b5e25b8 JR |
1635 | unsigned long align_mask, |
1636 | bool trylock) | |
a0f51447 JR |
1637 | { |
1638 | unsigned long offset, limit, flags; | |
1639 | dma_addr_t address; | |
ccb50e03 | 1640 | bool flush = false; |
a0f51447 JR |
1641 | |
1642 | offset = range->offset >> PAGE_SHIFT; | |
1643 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1644 | dma_mask >> PAGE_SHIFT); | |
1645 | ||
7b5e25b8 JR |
1646 | if (trylock) { |
1647 | if (!spin_trylock_irqsave(&range->bitmap_lock, flags)) | |
1648 | return -1; | |
1649 | } else { | |
1650 | spin_lock_irqsave(&range->bitmap_lock, flags); | |
1651 | } | |
1652 | ||
60e6a7cb JR |
1653 | address = iommu_area_alloc(range->bitmap, limit, range->next_bit, |
1654 | pages, offset, boundary_size, align_mask); | |
ccb50e03 | 1655 | if (address == -1) { |
60e6a7cb JR |
1656 | /* Nothing found, retry one time */ |
1657 | address = iommu_area_alloc(range->bitmap, limit, | |
1658 | 0, pages, offset, boundary_size, | |
1659 | align_mask); | |
ccb50e03 JR |
1660 | flush = true; |
1661 | } | |
60e6a7cb JR |
1662 | |
1663 | if (address != -1) | |
1664 | range->next_bit = address + pages; | |
1665 | ||
a0f51447 JR |
1666 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
1667 | ||
ccb50e03 JR |
1668 | if (flush) { |
1669 | domain_flush_tlb(&dom->domain); | |
1670 | domain_flush_complete(&dom->domain); | |
1671 | } | |
1672 | ||
a0f51447 JR |
1673 | return address; |
1674 | } | |
1675 | ||
384de729 JR |
1676 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1677 | struct dma_ops_domain *dom, | |
1678 | unsigned int pages, | |
1679 | unsigned long align_mask, | |
05ab49e0 | 1680 | u64 dma_mask) |
384de729 | 1681 | { |
ab7032bb | 1682 | unsigned long boundary_size, mask; |
384de729 | 1683 | unsigned long address = -1; |
7b5e25b8 | 1684 | bool first = true; |
5f6bed50 JR |
1685 | u32 start, i; |
1686 | ||
1687 | preempt_disable(); | |
384de729 | 1688 | |
e6aabee0 JR |
1689 | mask = dma_get_seg_boundary(dev); |
1690 | ||
7b5e25b8 | 1691 | again: |
5f6bed50 JR |
1692 | start = this_cpu_read(*dom->next_index); |
1693 | ||
1694 | /* Sanity check - is it really necessary? */ | |
1695 | if (unlikely(start > APERTURE_MAX_RANGES)) { | |
1696 | start = 0; | |
1697 | this_cpu_write(*dom->next_index, 0); | |
1698 | } | |
1699 | ||
e6aabee0 JR |
1700 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : |
1701 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 | 1702 | |
2a87442c JR |
1703 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1704 | struct aperture_range *range; | |
5f6bed50 JR |
1705 | int index; |
1706 | ||
1707 | index = (start + i) % APERTURE_MAX_RANGES; | |
ccb50e03 | 1708 | |
5f6bed50 | 1709 | range = dom->aperture[index]; |
2a87442c JR |
1710 | |
1711 | if (!range || range->offset >= dma_mask) | |
1712 | continue; | |
384de729 | 1713 | |
2a87442c | 1714 | address = dma_ops_aperture_alloc(dom, range, pages, |
60e6a7cb | 1715 | dma_mask, boundary_size, |
7b5e25b8 | 1716 | align_mask, first); |
384de729 | 1717 | if (address != -1) { |
2a87442c | 1718 | address = range->offset + (address << PAGE_SHIFT); |
5f6bed50 | 1719 | this_cpu_write(*dom->next_index, index); |
384de729 JR |
1720 | break; |
1721 | } | |
384de729 JR |
1722 | } |
1723 | ||
7b5e25b8 JR |
1724 | if (address == -1 && first) { |
1725 | first = false; | |
1726 | goto again; | |
1727 | } | |
1728 | ||
5f6bed50 JR |
1729 | preempt_enable(); |
1730 | ||
384de729 JR |
1731 | return address; |
1732 | } | |
1733 | ||
d3086444 JR |
1734 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1735 | struct dma_ops_domain *dom, | |
6d4f343f | 1736 | unsigned int pages, |
832a90c3 JR |
1737 | unsigned long align_mask, |
1738 | u64 dma_mask) | |
d3086444 | 1739 | { |
266a3bd2 | 1740 | unsigned long address = -1; |
d3086444 | 1741 | |
266a3bd2 JR |
1742 | while (address == -1) { |
1743 | address = dma_ops_area_alloc(dev, dom, pages, | |
1744 | align_mask, dma_mask); | |
1745 | ||
7bfa5bd2 | 1746 | if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC)) |
266a3bd2 JR |
1747 | break; |
1748 | } | |
d3086444 | 1749 | |
384de729 | 1750 | if (unlikely(address == -1)) |
8fd524b3 | 1751 | address = DMA_ERROR_CODE; |
d3086444 JR |
1752 | |
1753 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1754 | ||
1755 | return address; | |
1756 | } | |
1757 | ||
431b2a20 JR |
1758 | /* |
1759 | * The address free function. | |
1760 | * | |
1761 | * called with domain->lock held | |
1762 | */ | |
d3086444 JR |
1763 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1764 | unsigned long address, | |
1765 | unsigned int pages) | |
1766 | { | |
384de729 JR |
1767 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1768 | struct aperture_range *range = dom->aperture[i]; | |
08c5fb93 | 1769 | unsigned long flags; |
80be308d | 1770 | |
384de729 JR |
1771 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1772 | ||
47bccd6b JR |
1773 | #ifdef CONFIG_IOMMU_STRESS |
1774 | if (i < 4) | |
1775 | return; | |
1776 | #endif | |
80be308d | 1777 | |
4eeca8c5 | 1778 | if (amd_iommu_unmap_flush) { |
d41ab098 JR |
1779 | domain_flush_tlb(&dom->domain); |
1780 | domain_flush_complete(&dom->domain); | |
1781 | } | |
384de729 JR |
1782 | |
1783 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1784 | |
08c5fb93 | 1785 | spin_lock_irqsave(&range->bitmap_lock, flags); |
4eeca8c5 JR |
1786 | if (address + pages > range->next_bit) |
1787 | range->next_bit = address + pages; | |
a66022c4 | 1788 | bitmap_clear(range->bitmap, address, pages); |
08c5fb93 | 1789 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
384de729 | 1790 | |
d3086444 JR |
1791 | } |
1792 | ||
431b2a20 JR |
1793 | /**************************************************************************** |
1794 | * | |
1795 | * The next functions belong to the domain allocation. A domain is | |
1796 | * allocated for every IOMMU as the default domain. If device isolation | |
1797 | * is enabled, every device get its own domain. The most important thing | |
1798 | * about domains is the page table mapping the DMA address space they | |
1799 | * contain. | |
1800 | * | |
1801 | ****************************************************************************/ | |
1802 | ||
aeb26f55 JR |
1803 | /* |
1804 | * This function adds a protection domain to the global protection domain list | |
1805 | */ | |
1806 | static void add_domain_to_list(struct protection_domain *domain) | |
1807 | { | |
1808 | unsigned long flags; | |
1809 | ||
1810 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1811 | list_add(&domain->list, &amd_iommu_pd_list); | |
1812 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1813 | } | |
1814 | ||
1815 | /* | |
1816 | * This function removes a protection domain to the global | |
1817 | * protection domain list | |
1818 | */ | |
1819 | static void del_domain_from_list(struct protection_domain *domain) | |
1820 | { | |
1821 | unsigned long flags; | |
1822 | ||
1823 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1824 | list_del(&domain->list); | |
1825 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1826 | } | |
1827 | ||
ec487d1a JR |
1828 | static u16 domain_id_alloc(void) |
1829 | { | |
1830 | unsigned long flags; | |
1831 | int id; | |
1832 | ||
1833 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1834 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1835 | BUG_ON(id == 0); | |
1836 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1837 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1838 | else | |
1839 | id = 0; | |
1840 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1841 | ||
1842 | return id; | |
1843 | } | |
1844 | ||
a2acfb75 JR |
1845 | static void domain_id_free(int id) |
1846 | { | |
1847 | unsigned long flags; | |
1848 | ||
1849 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1850 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1851 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1852 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1853 | } | |
a2acfb75 | 1854 | |
5c34c403 JR |
1855 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1856 | static void free_pt_##LVL (unsigned long __pt) \ | |
1857 | { \ | |
1858 | unsigned long p; \ | |
1859 | u64 *pt; \ | |
1860 | int i; \ | |
1861 | \ | |
1862 | pt = (u64 *)__pt; \ | |
1863 | \ | |
1864 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1865 | /* PTE present? */ \ |
5c34c403 JR |
1866 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1867 | continue; \ | |
1868 | \ | |
0b3fff54 JR |
1869 | /* Large PTE? */ \ |
1870 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1871 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1872 | continue; \ | |
1873 | \ | |
5c34c403 JR |
1874 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1875 | FN(p); \ | |
1876 | } \ | |
1877 | free_page((unsigned long)pt); \ | |
1878 | } | |
1879 | ||
1880 | DEFINE_FREE_PT_FN(l2, free_page) | |
1881 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1882 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1883 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1884 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1885 | ||
86db2e5d | 1886 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1887 | { |
5c34c403 | 1888 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1889 | |
5c34c403 JR |
1890 | switch (domain->mode) { |
1891 | case PAGE_MODE_NONE: | |
1892 | break; | |
1893 | case PAGE_MODE_1_LEVEL: | |
1894 | free_page(root); | |
1895 | break; | |
1896 | case PAGE_MODE_2_LEVEL: | |
1897 | free_pt_l2(root); | |
1898 | break; | |
1899 | case PAGE_MODE_3_LEVEL: | |
1900 | free_pt_l3(root); | |
1901 | break; | |
1902 | case PAGE_MODE_4_LEVEL: | |
1903 | free_pt_l4(root); | |
1904 | break; | |
1905 | case PAGE_MODE_5_LEVEL: | |
1906 | free_pt_l5(root); | |
1907 | break; | |
1908 | case PAGE_MODE_6_LEVEL: | |
1909 | free_pt_l6(root); | |
1910 | break; | |
1911 | default: | |
1912 | BUG(); | |
ec487d1a | 1913 | } |
ec487d1a JR |
1914 | } |
1915 | ||
b16137b1 JR |
1916 | static void free_gcr3_tbl_level1(u64 *tbl) |
1917 | { | |
1918 | u64 *ptr; | |
1919 | int i; | |
1920 | ||
1921 | for (i = 0; i < 512; ++i) { | |
1922 | if (!(tbl[i] & GCR3_VALID)) | |
1923 | continue; | |
1924 | ||
1925 | ptr = __va(tbl[i] & PAGE_MASK); | |
1926 | ||
1927 | free_page((unsigned long)ptr); | |
1928 | } | |
1929 | } | |
1930 | ||
1931 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1932 | { | |
1933 | u64 *ptr; | |
1934 | int i; | |
1935 | ||
1936 | for (i = 0; i < 512; ++i) { | |
1937 | if (!(tbl[i] & GCR3_VALID)) | |
1938 | continue; | |
1939 | ||
1940 | ptr = __va(tbl[i] & PAGE_MASK); | |
1941 | ||
1942 | free_gcr3_tbl_level1(ptr); | |
1943 | } | |
1944 | } | |
1945 | ||
52815b75 JR |
1946 | static void free_gcr3_table(struct protection_domain *domain) |
1947 | { | |
b16137b1 JR |
1948 | if (domain->glx == 2) |
1949 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1950 | else if (domain->glx == 1) | |
1951 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1952 | else |
1953 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1954 | |
52815b75 JR |
1955 | free_page((unsigned long)domain->gcr3_tbl); |
1956 | } | |
1957 | ||
431b2a20 JR |
1958 | /* |
1959 | * Free a domain, only used if something went wrong in the | |
1960 | * allocation path and we need to free an already allocated page table | |
1961 | */ | |
ec487d1a JR |
1962 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1963 | { | |
384de729 JR |
1964 | int i; |
1965 | ||
ec487d1a JR |
1966 | if (!dom) |
1967 | return; | |
1968 | ||
5f6bed50 JR |
1969 | free_percpu(dom->next_index); |
1970 | ||
aeb26f55 JR |
1971 | del_domain_from_list(&dom->domain); |
1972 | ||
86db2e5d | 1973 | free_pagetable(&dom->domain); |
ec487d1a | 1974 | |
384de729 JR |
1975 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1976 | if (!dom->aperture[i]) | |
1977 | continue; | |
1978 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1979 | kfree(dom->aperture[i]); | |
1980 | } | |
ec487d1a JR |
1981 | |
1982 | kfree(dom); | |
1983 | } | |
1984 | ||
a639a8ee JR |
1985 | static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom, |
1986 | int max_apertures) | |
1987 | { | |
1988 | int ret, i, apertures; | |
1989 | ||
1990 | apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
1991 | ret = 0; | |
1992 | ||
1993 | for (i = apertures; i < max_apertures; ++i) { | |
1994 | ret = alloc_new_range(dma_dom, false, GFP_KERNEL); | |
1995 | if (ret) | |
1996 | break; | |
1997 | } | |
1998 | ||
1999 | return ret; | |
2000 | } | |
2001 | ||
431b2a20 JR |
2002 | /* |
2003 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 2004 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
2005 | * structures required for the dma_ops interface |
2006 | */ | |
87a64d52 | 2007 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
2008 | { |
2009 | struct dma_ops_domain *dma_dom; | |
5f6bed50 | 2010 | int cpu; |
ec487d1a JR |
2011 | |
2012 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
2013 | if (!dma_dom) | |
2014 | return NULL; | |
2015 | ||
7a5a566e | 2016 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 2017 | goto free_dma_dom; |
7a5a566e | 2018 | |
5f6bed50 JR |
2019 | dma_dom->next_index = alloc_percpu(u32); |
2020 | if (!dma_dom->next_index) | |
2021 | goto free_dma_dom; | |
2022 | ||
8f7a017c | 2023 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2024 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2025 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2026 | dma_dom->domain.priv = dma_dom; |
2027 | if (!dma_dom->domain.pt_root) | |
2028 | goto free_dma_dom; | |
ec487d1a | 2029 | |
aeb26f55 JR |
2030 | add_domain_to_list(&dma_dom->domain); |
2031 | ||
576175c2 | 2032 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2033 | goto free_dma_dom; |
ec487d1a | 2034 | |
431b2a20 | 2035 | /* |
ec487d1a JR |
2036 | * mark the first page as allocated so we never return 0 as |
2037 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2038 | */ |
384de729 | 2039 | dma_dom->aperture[0]->bitmap[0] = 1; |
ec487d1a | 2040 | |
5f6bed50 JR |
2041 | for_each_possible_cpu(cpu) |
2042 | *per_cpu_ptr(dma_dom->next_index, cpu) = 0; | |
ec487d1a JR |
2043 | |
2044 | return dma_dom; | |
2045 | ||
2046 | free_dma_dom: | |
2047 | dma_ops_domain_free(dma_dom); | |
2048 | ||
2049 | return NULL; | |
2050 | } | |
2051 | ||
5b28df6f JR |
2052 | /* |
2053 | * little helper function to check whether a given protection domain is a | |
2054 | * dma_ops domain | |
2055 | */ | |
2056 | static bool dma_ops_domain(struct protection_domain *domain) | |
2057 | { | |
2058 | return domain->flags & PD_DMA_OPS_MASK; | |
2059 | } | |
2060 | ||
fd7b5535 | 2061 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2062 | { |
132bd68f | 2063 | u64 pte_root = 0; |
ee6c2868 | 2064 | u64 flags = 0; |
863c74eb | 2065 | |
132bd68f JR |
2066 | if (domain->mode != PAGE_MODE_NONE) |
2067 | pte_root = virt_to_phys(domain->pt_root); | |
2068 | ||
38ddf41b JR |
2069 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2070 | << DEV_ENTRY_MODE_SHIFT; | |
2071 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2072 | |
ee6c2868 JR |
2073 | flags = amd_iommu_dev_table[devid].data[1]; |
2074 | ||
fd7b5535 JR |
2075 | if (ats) |
2076 | flags |= DTE_FLAG_IOTLB; | |
2077 | ||
52815b75 JR |
2078 | if (domain->flags & PD_IOMMUV2_MASK) { |
2079 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2080 | u64 glx = domain->glx; | |
2081 | u64 tmp; | |
2082 | ||
2083 | pte_root |= DTE_FLAG_GV; | |
2084 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2085 | ||
2086 | /* First mask out possible old values for GCR3 table */ | |
2087 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2088 | flags &= ~tmp; | |
2089 | ||
2090 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2091 | flags &= ~tmp; | |
2092 | ||
2093 | /* Encode GCR3 table into DTE */ | |
2094 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2095 | pte_root |= tmp; | |
2096 | ||
2097 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2098 | flags |= tmp; | |
2099 | ||
2100 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2101 | flags |= tmp; | |
2102 | } | |
2103 | ||
ee6c2868 JR |
2104 | flags &= ~(0xffffUL); |
2105 | flags |= domain->id; | |
2106 | ||
2107 | amd_iommu_dev_table[devid].data[1] = flags; | |
2108 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2109 | } |
2110 | ||
2111 | static void clear_dte_entry(u16 devid) | |
2112 | { | |
15898bbc | 2113 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
2114 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
2115 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
2116 | |
2117 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2118 | } |
2119 | ||
ec9e79ef JR |
2120 | static void do_attach(struct iommu_dev_data *dev_data, |
2121 | struct protection_domain *domain) | |
7f760ddd | 2122 | { |
7f760ddd | 2123 | struct amd_iommu *iommu; |
e25bfb56 | 2124 | u16 alias; |
ec9e79ef | 2125 | bool ats; |
fd7b5535 | 2126 | |
ec9e79ef | 2127 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 2128 | alias = amd_iommu_alias_table[dev_data->devid]; |
ec9e79ef | 2129 | ats = dev_data->ats.enabled; |
7f760ddd JR |
2130 | |
2131 | /* Update data structures */ | |
2132 | dev_data->domain = domain; | |
2133 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
2134 | |
2135 | /* Do reference counting */ | |
2136 | domain->dev_iommu[iommu->index] += 1; | |
2137 | domain->dev_cnt += 1; | |
2138 | ||
e25bfb56 JR |
2139 | /* Update device table */ |
2140 | set_dte_entry(dev_data->devid, domain, ats); | |
2141 | if (alias != dev_data->devid) | |
9b1a12d2 | 2142 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 2143 | |
6c542047 | 2144 | device_flush_dte(dev_data); |
7f760ddd JR |
2145 | } |
2146 | ||
ec9e79ef | 2147 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2148 | { |
7f760ddd | 2149 | struct amd_iommu *iommu; |
e25bfb56 | 2150 | u16 alias; |
7f760ddd | 2151 | |
5adad991 JR |
2152 | /* |
2153 | * First check if the device is still attached. It might already | |
2154 | * be detached from its domain because the generic | |
2155 | * iommu_detach_group code detached it and we try again here in | |
2156 | * our alias handling. | |
2157 | */ | |
2158 | if (!dev_data->domain) | |
2159 | return; | |
2160 | ||
ec9e79ef | 2161 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e25bfb56 | 2162 | alias = amd_iommu_alias_table[dev_data->devid]; |
15898bbc JR |
2163 | |
2164 | /* decrease reference counters */ | |
7f760ddd JR |
2165 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2166 | dev_data->domain->dev_cnt -= 1; | |
2167 | ||
2168 | /* Update data structures */ | |
2169 | dev_data->domain = NULL; | |
2170 | list_del(&dev_data->list); | |
f62dda66 | 2171 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
2172 | if (alias != dev_data->devid) |
2173 | clear_dte_entry(alias); | |
15898bbc | 2174 | |
7f760ddd | 2175 | /* Flush the DTE entry */ |
6c542047 | 2176 | device_flush_dte(dev_data); |
2b681faf JR |
2177 | } |
2178 | ||
2179 | /* | |
2180 | * If a device is not yet associated with a domain, this function does | |
2181 | * assigns it visible for the hardware | |
2182 | */ | |
ec9e79ef | 2183 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2184 | struct protection_domain *domain) |
2b681faf | 2185 | { |
84fe6c19 | 2186 | int ret; |
657cbb6b | 2187 | |
272e4f99 JR |
2188 | /* |
2189 | * Must be called with IRQs disabled. Warn here to detect early | |
2190 | * when its not. | |
2191 | */ | |
2192 | WARN_ON(!irqs_disabled()); | |
2193 | ||
2b681faf JR |
2194 | /* lock domain */ |
2195 | spin_lock(&domain->lock); | |
2196 | ||
397111ab | 2197 | ret = -EBUSY; |
150952f9 | 2198 | if (dev_data->domain != NULL) |
397111ab | 2199 | goto out_unlock; |
15898bbc | 2200 | |
397111ab | 2201 | /* Attach alias group root */ |
150952f9 | 2202 | do_attach(dev_data, domain); |
24100055 | 2203 | |
84fe6c19 JL |
2204 | ret = 0; |
2205 | ||
2206 | out_unlock: | |
2207 | ||
eba6ac60 JR |
2208 | /* ready */ |
2209 | spin_unlock(&domain->lock); | |
15898bbc | 2210 | |
84fe6c19 | 2211 | return ret; |
0feae533 | 2212 | } |
b20ac0d4 | 2213 | |
52815b75 JR |
2214 | |
2215 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2216 | { | |
2217 | pci_disable_ats(pdev); | |
2218 | pci_disable_pri(pdev); | |
2219 | pci_disable_pasid(pdev); | |
2220 | } | |
2221 | ||
6a113ddc JR |
2222 | /* FIXME: Change generic reset-function to do the same */ |
2223 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2224 | { | |
2225 | u16 control; | |
2226 | int pos; | |
2227 | ||
46277b75 | 2228 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2229 | if (!pos) |
2230 | return -EINVAL; | |
2231 | ||
46277b75 JR |
2232 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2233 | control |= PCI_PRI_CTRL_RESET; | |
2234 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2235 | |
2236 | return 0; | |
2237 | } | |
2238 | ||
52815b75 JR |
2239 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2240 | { | |
6a113ddc JR |
2241 | bool reset_enable; |
2242 | int reqs, ret; | |
2243 | ||
2244 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2245 | reqs = 32; | |
2246 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2247 | reqs = 1; | |
2248 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2249 | |
2250 | /* Only allow access to user-accessible pages */ | |
2251 | ret = pci_enable_pasid(pdev, 0); | |
2252 | if (ret) | |
2253 | goto out_err; | |
2254 | ||
2255 | /* First reset the PRI state of the device */ | |
2256 | ret = pci_reset_pri(pdev); | |
2257 | if (ret) | |
2258 | goto out_err; | |
2259 | ||
6a113ddc JR |
2260 | /* Enable PRI */ |
2261 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2262 | if (ret) |
2263 | goto out_err; | |
2264 | ||
6a113ddc JR |
2265 | if (reset_enable) { |
2266 | ret = pri_reset_while_enabled(pdev); | |
2267 | if (ret) | |
2268 | goto out_err; | |
2269 | } | |
2270 | ||
52815b75 JR |
2271 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2272 | if (ret) | |
2273 | goto out_err; | |
2274 | ||
2275 | return 0; | |
2276 | ||
2277 | out_err: | |
2278 | pci_disable_pri(pdev); | |
2279 | pci_disable_pasid(pdev); | |
2280 | ||
2281 | return ret; | |
2282 | } | |
2283 | ||
c99afa25 | 2284 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2285 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2286 | |
98f1ad25 | 2287 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2288 | { |
a3b93121 | 2289 | u16 status; |
c99afa25 JR |
2290 | int pos; |
2291 | ||
46277b75 | 2292 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2293 | if (!pos) |
2294 | return false; | |
2295 | ||
a3b93121 | 2296 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2297 | |
a3b93121 | 2298 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2299 | } |
2300 | ||
407d733e | 2301 | /* |
df805abb | 2302 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2303 | * assigns it visible for the hardware |
2304 | */ | |
15898bbc JR |
2305 | static int attach_device(struct device *dev, |
2306 | struct protection_domain *domain) | |
0feae533 | 2307 | { |
2bf9a0a1 | 2308 | struct pci_dev *pdev; |
ea61cddb | 2309 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2310 | unsigned long flags; |
15898bbc | 2311 | int ret; |
eba6ac60 | 2312 | |
ea61cddb JR |
2313 | dev_data = get_dev_data(dev); |
2314 | ||
2bf9a0a1 WZ |
2315 | if (!dev_is_pci(dev)) |
2316 | goto skip_ats_check; | |
2317 | ||
2318 | pdev = to_pci_dev(dev); | |
52815b75 | 2319 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2320 | if (!dev_data->passthrough) |
52815b75 JR |
2321 | return -EINVAL; |
2322 | ||
02ca2021 JR |
2323 | if (dev_data->iommu_v2) { |
2324 | if (pdev_iommuv2_enable(pdev) != 0) | |
2325 | return -EINVAL; | |
52815b75 | 2326 | |
02ca2021 JR |
2327 | dev_data->ats.enabled = true; |
2328 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2329 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2330 | } | |
52815b75 JR |
2331 | } else if (amd_iommu_iotlb_sup && |
2332 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2333 | dev_data->ats.enabled = true; |
2334 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2335 | } | |
fd7b5535 | 2336 | |
2bf9a0a1 | 2337 | skip_ats_check: |
eba6ac60 | 2338 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2339 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2340 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2341 | ||
0feae533 JR |
2342 | /* |
2343 | * We might boot into a crash-kernel here. The crashed kernel | |
2344 | * left the caches in the IOMMU dirty. So we have to flush | |
2345 | * here to evict all dirty stuff. | |
2346 | */ | |
17b124bf | 2347 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2348 | |
2349 | return ret; | |
b20ac0d4 JR |
2350 | } |
2351 | ||
355bf553 JR |
2352 | /* |
2353 | * Removes a device from a protection domain (unlocked) | |
2354 | */ | |
ec9e79ef | 2355 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2356 | { |
2ca76279 | 2357 | struct protection_domain *domain; |
c4596114 | 2358 | |
272e4f99 JR |
2359 | /* |
2360 | * Must be called with IRQs disabled. Warn here to detect early | |
2361 | * when its not. | |
2362 | */ | |
2363 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2364 | |
f34c73f5 JR |
2365 | if (WARN_ON(!dev_data->domain)) |
2366 | return; | |
24100055 | 2367 | |
2ca76279 | 2368 | domain = dev_data->domain; |
71f77580 | 2369 | |
f1dd0a8b | 2370 | spin_lock(&domain->lock); |
24100055 | 2371 | |
150952f9 | 2372 | do_detach(dev_data); |
7f760ddd | 2373 | |
f1dd0a8b | 2374 | spin_unlock(&domain->lock); |
355bf553 JR |
2375 | } |
2376 | ||
2377 | /* | |
2378 | * Removes a device from a protection domain (with devtable_lock held) | |
2379 | */ | |
15898bbc | 2380 | static void detach_device(struct device *dev) |
355bf553 | 2381 | { |
52815b75 | 2382 | struct protection_domain *domain; |
ea61cddb | 2383 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2384 | unsigned long flags; |
2385 | ||
ec9e79ef | 2386 | dev_data = get_dev_data(dev); |
52815b75 | 2387 | domain = dev_data->domain; |
ec9e79ef | 2388 | |
355bf553 JR |
2389 | /* lock device table */ |
2390 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2391 | __detach_device(dev_data); |
355bf553 | 2392 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2393 | |
2bf9a0a1 WZ |
2394 | if (!dev_is_pci(dev)) |
2395 | return; | |
2396 | ||
02ca2021 | 2397 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2398 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2399 | else if (dev_data->ats.enabled) | |
ea61cddb | 2400 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2401 | |
2402 | dev_data->ats.enabled = false; | |
355bf553 | 2403 | } |
e275a2a0 | 2404 | |
aafd8ba0 | 2405 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2406 | { |
5abcdba4 | 2407 | struct iommu_dev_data *dev_data; |
07ee8694 | 2408 | struct iommu_domain *domain; |
e275a2a0 | 2409 | struct amd_iommu *iommu; |
7aba6cb9 | 2410 | int ret, devid; |
e275a2a0 | 2411 | |
aafd8ba0 | 2412 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2413 | return 0; |
e275a2a0 | 2414 | |
aafd8ba0 | 2415 | devid = get_device_id(dev); |
7aba6cb9 WZ |
2416 | if (IS_ERR_VALUE(devid)) |
2417 | return devid; | |
2418 | ||
aafd8ba0 | 2419 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2420 | |
aafd8ba0 | 2421 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2422 | if (ret) { |
2423 | if (ret != -ENOTSUPP) | |
2424 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2425 | dev_name(dev)); | |
657cbb6b | 2426 | |
aafd8ba0 | 2427 | iommu_ignore_device(dev); |
343e9cac | 2428 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2429 | goto out; |
2430 | } | |
2431 | init_iommu_group(dev); | |
2c9195e9 | 2432 | |
07ee8694 | 2433 | dev_data = get_dev_data(dev); |
2c9195e9 | 2434 | |
4d58b8a6 | 2435 | BUG_ON(!dev_data); |
657cbb6b | 2436 | |
1e6a7b04 | 2437 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2438 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2439 | |
07ee8694 JR |
2440 | /* Domains are initialized for this device - have a look what we ended up with */ |
2441 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2442 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2443 | dev_data->passthrough = true; |
32302324 | 2444 | else |
2c9195e9 | 2445 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2446 | |
aafd8ba0 | 2447 | out: |
e275a2a0 JR |
2448 | iommu_completion_wait(iommu); |
2449 | ||
e275a2a0 JR |
2450 | return 0; |
2451 | } | |
2452 | ||
aafd8ba0 | 2453 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2454 | { |
aafd8ba0 | 2455 | struct amd_iommu *iommu; |
7aba6cb9 | 2456 | int devid; |
aafd8ba0 JR |
2457 | |
2458 | if (!check_device(dev)) | |
2459 | return; | |
2460 | ||
2461 | devid = get_device_id(dev); | |
7aba6cb9 WZ |
2462 | if (IS_ERR_VALUE(devid)) |
2463 | return; | |
2464 | ||
aafd8ba0 JR |
2465 | iommu = amd_iommu_rlookup_table[devid]; |
2466 | ||
2467 | iommu_uninit_device(dev); | |
2468 | iommu_completion_wait(iommu); | |
8638c491 JR |
2469 | } |
2470 | ||
b097d11a WZ |
2471 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2472 | { | |
2473 | if (dev_is_pci(dev)) | |
2474 | return pci_device_group(dev); | |
2475 | ||
2476 | return acpihid_device_group(dev); | |
2477 | } | |
2478 | ||
431b2a20 JR |
2479 | /***************************************************************************** |
2480 | * | |
2481 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2482 | * | |
2483 | *****************************************************************************/ | |
2484 | ||
2485 | /* | |
2486 | * In the dma_ops path we only have the struct device. This function | |
2487 | * finds the corresponding IOMMU, the protection domain and the | |
2488 | * requestor id for a given device. | |
2489 | * If the device is not yet associated with a domain this is also done | |
2490 | * in this function. | |
2491 | */ | |
94f6d190 | 2492 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2493 | { |
94f6d190 | 2494 | struct protection_domain *domain; |
063071df | 2495 | struct iommu_domain *io_domain; |
b20ac0d4 | 2496 | |
f99c0f1c | 2497 | if (!check_device(dev)) |
94f6d190 | 2498 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2499 | |
063071df | 2500 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2501 | if (!io_domain) |
2502 | return NULL; | |
b20ac0d4 | 2503 | |
0bb6e243 JR |
2504 | domain = to_pdomain(io_domain); |
2505 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2506 | return ERR_PTR(-EBUSY); |
f91ba190 | 2507 | |
0bb6e243 | 2508 | return domain; |
b20ac0d4 JR |
2509 | } |
2510 | ||
04bfdd84 JR |
2511 | static void update_device_table(struct protection_domain *domain) |
2512 | { | |
492667da | 2513 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2514 | |
ea61cddb JR |
2515 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2516 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2517 | } |
2518 | ||
2519 | static void update_domain(struct protection_domain *domain) | |
2520 | { | |
2521 | if (!domain->updated) | |
2522 | return; | |
2523 | ||
2524 | update_device_table(domain); | |
17b124bf JR |
2525 | |
2526 | domain_flush_devices(domain); | |
2527 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2528 | |
2529 | domain->updated = false; | |
2530 | } | |
2531 | ||
8bda3092 JR |
2532 | /* |
2533 | * This function fetches the PTE for a given address in the aperture | |
2534 | */ | |
2535 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2536 | unsigned long address) | |
2537 | { | |
384de729 | 2538 | struct aperture_range *aperture; |
8bda3092 JR |
2539 | u64 *pte, *pte_page; |
2540 | ||
384de729 JR |
2541 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2542 | if (!aperture) | |
2543 | return NULL; | |
2544 | ||
2545 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2546 | if (!pte) { |
cbb9d729 | 2547 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2548 | GFP_ATOMIC); |
384de729 JR |
2549 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2550 | } else | |
8c8c143c | 2551 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2552 | |
04bfdd84 | 2553 | update_domain(&dom->domain); |
8bda3092 JR |
2554 | |
2555 | return pte; | |
2556 | } | |
2557 | ||
431b2a20 JR |
2558 | /* |
2559 | * This is the generic map function. It maps one 4kb page at paddr to | |
2560 | * the given address in the DMA address space for the domain. | |
2561 | */ | |
680525e0 | 2562 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2563 | unsigned long address, |
2564 | phys_addr_t paddr, | |
2565 | int direction) | |
2566 | { | |
2567 | u64 *pte, __pte; | |
2568 | ||
2569 | WARN_ON(address > dom->aperture_size); | |
2570 | ||
2571 | paddr &= PAGE_MASK; | |
2572 | ||
8bda3092 | 2573 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2574 | if (!pte) |
8fd524b3 | 2575 | return DMA_ERROR_CODE; |
cb76c322 JR |
2576 | |
2577 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2578 | ||
2579 | if (direction == DMA_TO_DEVICE) | |
2580 | __pte |= IOMMU_PTE_IR; | |
2581 | else if (direction == DMA_FROM_DEVICE) | |
2582 | __pte |= IOMMU_PTE_IW; | |
2583 | else if (direction == DMA_BIDIRECTIONAL) | |
2584 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2585 | ||
a7fb668f | 2586 | WARN_ON_ONCE(*pte); |
cb76c322 JR |
2587 | |
2588 | *pte = __pte; | |
2589 | ||
2590 | return (dma_addr_t)address; | |
2591 | } | |
2592 | ||
431b2a20 JR |
2593 | /* |
2594 | * The generic unmapping function for on page in the DMA address space. | |
2595 | */ | |
680525e0 | 2596 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2597 | unsigned long address) |
2598 | { | |
384de729 | 2599 | struct aperture_range *aperture; |
cb76c322 JR |
2600 | u64 *pte; |
2601 | ||
2602 | if (address >= dom->aperture_size) | |
2603 | return; | |
2604 | ||
384de729 JR |
2605 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2606 | if (!aperture) | |
2607 | return; | |
2608 | ||
2609 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2610 | if (!pte) | |
2611 | return; | |
cb76c322 | 2612 | |
8c8c143c | 2613 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 | 2614 | |
a7fb668f | 2615 | WARN_ON_ONCE(!*pte); |
cb76c322 JR |
2616 | |
2617 | *pte = 0ULL; | |
2618 | } | |
2619 | ||
431b2a20 JR |
2620 | /* |
2621 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2622 | * contiguous memory region into DMA address space. It is used by all |
2623 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2624 | * Must be called with the domain lock held. |
2625 | */ | |
cb76c322 | 2626 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2627 | struct dma_ops_domain *dma_dom, |
2628 | phys_addr_t paddr, | |
2629 | size_t size, | |
6d4f343f | 2630 | int dir, |
832a90c3 JR |
2631 | bool align, |
2632 | u64 dma_mask) | |
cb76c322 JR |
2633 | { |
2634 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2635 | dma_addr_t address, start, ret; |
cb76c322 | 2636 | unsigned int pages; |
6d4f343f | 2637 | unsigned long align_mask = 0; |
cb76c322 JR |
2638 | int i; |
2639 | ||
e3c449f5 | 2640 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2641 | paddr &= PAGE_MASK; |
2642 | ||
8ecaf8f1 JR |
2643 | INC_STATS_COUNTER(total_map_requests); |
2644 | ||
c1858976 JR |
2645 | if (pages > 1) |
2646 | INC_STATS_COUNTER(cross_page); | |
2647 | ||
6d4f343f JR |
2648 | if (align) |
2649 | align_mask = (1UL << get_order(size)) - 1; | |
2650 | ||
832a90c3 JR |
2651 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2652 | dma_mask); | |
ebaecb42 | 2653 | |
266a3bd2 JR |
2654 | if (address == DMA_ERROR_CODE) |
2655 | goto out; | |
cb76c322 JR |
2656 | |
2657 | start = address; | |
2658 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2659 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2660 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2661 | goto out_unmap; |
2662 | ||
cb76c322 JR |
2663 | paddr += PAGE_SIZE; |
2664 | start += PAGE_SIZE; | |
2665 | } | |
2666 | address += offset; | |
2667 | ||
5774f7c5 JR |
2668 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2669 | ||
ab7032bb | 2670 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2671 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2672 | domain_flush_complete(&dma_dom->domain); |
2673 | } | |
270cab24 | 2674 | |
cb76c322 JR |
2675 | out: |
2676 | return address; | |
53812c11 JR |
2677 | |
2678 | out_unmap: | |
2679 | ||
2680 | for (--i; i >= 0; --i) { | |
2681 | start -= PAGE_SIZE; | |
680525e0 | 2682 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2683 | } |
2684 | ||
2685 | dma_ops_free_addresses(dma_dom, address, pages); | |
2686 | ||
8fd524b3 | 2687 | return DMA_ERROR_CODE; |
cb76c322 JR |
2688 | } |
2689 | ||
431b2a20 JR |
2690 | /* |
2691 | * Does the reverse of the __map_single function. Must be called with | |
2692 | * the domain lock held too | |
2693 | */ | |
cd8c82e8 | 2694 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2695 | dma_addr_t dma_addr, |
2696 | size_t size, | |
2697 | int dir) | |
2698 | { | |
04e0463e | 2699 | dma_addr_t flush_addr; |
cb76c322 JR |
2700 | dma_addr_t i, start; |
2701 | unsigned int pages; | |
2702 | ||
8fd524b3 | 2703 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2704 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2705 | return; |
2706 | ||
04e0463e | 2707 | flush_addr = dma_addr; |
e3c449f5 | 2708 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2709 | dma_addr &= PAGE_MASK; |
2710 | start = dma_addr; | |
2711 | ||
2712 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2713 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2714 | start += PAGE_SIZE; |
2715 | } | |
2716 | ||
84b3a0bc JR |
2717 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2718 | ||
2719 | dma_ops_free_addresses(dma_dom, dma_addr, pages); | |
cb76c322 JR |
2720 | } |
2721 | ||
431b2a20 JR |
2722 | /* |
2723 | * The exported map_single function for dma_ops. | |
2724 | */ | |
51491367 FT |
2725 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2726 | unsigned long offset, size_t size, | |
2727 | enum dma_data_direction dir, | |
2728 | struct dma_attrs *attrs) | |
4da70b9e | 2729 | { |
92d420ec | 2730 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2731 | struct protection_domain *domain; |
832a90c3 | 2732 | u64 dma_mask; |
4da70b9e | 2733 | |
0f2a86f2 JR |
2734 | INC_STATS_COUNTER(cnt_map_single); |
2735 | ||
94f6d190 JR |
2736 | domain = get_domain(dev); |
2737 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2738 | return (dma_addr_t)paddr; |
94f6d190 JR |
2739 | else if (IS_ERR(domain)) |
2740 | return DMA_ERROR_CODE; | |
4da70b9e | 2741 | |
f99c0f1c JR |
2742 | dma_mask = *dev->dma_mask; |
2743 | ||
92d420ec | 2744 | return __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2745 | dma_mask); |
4da70b9e JR |
2746 | } |
2747 | ||
431b2a20 JR |
2748 | /* |
2749 | * The exported unmap_single function for dma_ops. | |
2750 | */ | |
51491367 FT |
2751 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2752 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e | 2753 | { |
4da70b9e | 2754 | struct protection_domain *domain; |
4da70b9e | 2755 | |
146a6917 JR |
2756 | INC_STATS_COUNTER(cnt_unmap_single); |
2757 | ||
94f6d190 JR |
2758 | domain = get_domain(dev); |
2759 | if (IS_ERR(domain)) | |
5b28df6f JR |
2760 | return; |
2761 | ||
cd8c82e8 | 2762 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e JR |
2763 | } |
2764 | ||
431b2a20 JR |
2765 | /* |
2766 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2767 | * lists). | |
2768 | */ | |
65b050ad | 2769 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2770 | int nelems, enum dma_data_direction dir, |
2771 | struct dma_attrs *attrs) | |
65b050ad | 2772 | { |
65b050ad | 2773 | struct protection_domain *domain; |
65b050ad JR |
2774 | int i; |
2775 | struct scatterlist *s; | |
2776 | phys_addr_t paddr; | |
2777 | int mapped_elems = 0; | |
832a90c3 | 2778 | u64 dma_mask; |
65b050ad | 2779 | |
d03f067a JR |
2780 | INC_STATS_COUNTER(cnt_map_sg); |
2781 | ||
94f6d190 | 2782 | domain = get_domain(dev); |
a0e191b2 | 2783 | if (IS_ERR(domain)) |
94f6d190 | 2784 | return 0; |
dbcc112e | 2785 | |
832a90c3 | 2786 | dma_mask = *dev->dma_mask; |
65b050ad | 2787 | |
65b050ad JR |
2788 | for_each_sg(sglist, s, nelems, i) { |
2789 | paddr = sg_phys(s); | |
2790 | ||
cd8c82e8 | 2791 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2792 | paddr, s->length, dir, false, |
2793 | dma_mask); | |
65b050ad JR |
2794 | |
2795 | if (s->dma_address) { | |
2796 | s->dma_length = s->length; | |
2797 | mapped_elems++; | |
2798 | } else | |
2799 | goto unmap; | |
65b050ad JR |
2800 | } |
2801 | ||
65b050ad | 2802 | return mapped_elems; |
92d420ec | 2803 | |
65b050ad JR |
2804 | unmap: |
2805 | for_each_sg(sglist, s, mapped_elems, i) { | |
2806 | if (s->dma_address) | |
cd8c82e8 | 2807 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2808 | s->dma_length, dir); |
2809 | s->dma_address = s->dma_length = 0; | |
2810 | } | |
2811 | ||
92d420ec | 2812 | return 0; |
65b050ad JR |
2813 | } |
2814 | ||
431b2a20 JR |
2815 | /* |
2816 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2817 | * lists). | |
2818 | */ | |
65b050ad | 2819 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2820 | int nelems, enum dma_data_direction dir, |
2821 | struct dma_attrs *attrs) | |
65b050ad | 2822 | { |
65b050ad JR |
2823 | struct protection_domain *domain; |
2824 | struct scatterlist *s; | |
65b050ad JR |
2825 | int i; |
2826 | ||
55877a6b JR |
2827 | INC_STATS_COUNTER(cnt_unmap_sg); |
2828 | ||
94f6d190 JR |
2829 | domain = get_domain(dev); |
2830 | if (IS_ERR(domain)) | |
5b28df6f JR |
2831 | return; |
2832 | ||
65b050ad | 2833 | for_each_sg(sglist, s, nelems, i) { |
cd8c82e8 | 2834 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2835 | s->dma_length, dir); |
65b050ad JR |
2836 | s->dma_address = s->dma_length = 0; |
2837 | } | |
65b050ad JR |
2838 | } |
2839 | ||
431b2a20 JR |
2840 | /* |
2841 | * The exported alloc_coherent function for dma_ops. | |
2842 | */ | |
5d8b53cf | 2843 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2844 | dma_addr_t *dma_addr, gfp_t flag, |
2845 | struct dma_attrs *attrs) | |
5d8b53cf | 2846 | { |
832a90c3 | 2847 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2848 | struct protection_domain *domain; |
3b839a57 | 2849 | struct page *page; |
5d8b53cf | 2850 | |
c8f0fb36 JR |
2851 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2852 | ||
94f6d190 JR |
2853 | domain = get_domain(dev); |
2854 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2855 | page = alloc_pages(flag, get_order(size)); |
2856 | *dma_addr = page_to_phys(page); | |
2857 | return page_address(page); | |
94f6d190 JR |
2858 | } else if (IS_ERR(domain)) |
2859 | return NULL; | |
5d8b53cf | 2860 | |
3b839a57 | 2861 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2862 | dma_mask = dev->coherent_dma_mask; |
2863 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2864 | flag |= __GFP_ZERO; |
5d8b53cf | 2865 | |
3b839a57 JR |
2866 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2867 | if (!page) { | |
d0164adc | 2868 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2869 | return NULL; |
5d8b53cf | 2870 | |
3b839a57 JR |
2871 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2872 | get_order(size)); | |
2873 | if (!page) | |
2874 | return NULL; | |
2875 | } | |
5d8b53cf | 2876 | |
832a90c3 JR |
2877 | if (!dma_mask) |
2878 | dma_mask = *dev->dma_mask; | |
2879 | ||
3b839a57 | 2880 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2881 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2882 | |
92d420ec | 2883 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2884 | goto out_free; |
5d8b53cf | 2885 | |
3b839a57 | 2886 | return page_address(page); |
5b28df6f JR |
2887 | |
2888 | out_free: | |
2889 | ||
3b839a57 JR |
2890 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2891 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2892 | |
2893 | return NULL; | |
5d8b53cf JR |
2894 | } |
2895 | ||
431b2a20 JR |
2896 | /* |
2897 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2898 | */ |
5d8b53cf | 2899 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2900 | void *virt_addr, dma_addr_t dma_addr, |
2901 | struct dma_attrs *attrs) | |
5d8b53cf | 2902 | { |
5d8b53cf | 2903 | struct protection_domain *domain; |
3b839a57 | 2904 | struct page *page; |
5d8b53cf | 2905 | |
5d31ee7e JR |
2906 | INC_STATS_COUNTER(cnt_free_coherent); |
2907 | ||
3b839a57 JR |
2908 | page = virt_to_page(virt_addr); |
2909 | size = PAGE_ALIGN(size); | |
2910 | ||
94f6d190 JR |
2911 | domain = get_domain(dev); |
2912 | if (IS_ERR(domain)) | |
5b28df6f JR |
2913 | goto free_mem; |
2914 | ||
cd8c82e8 | 2915 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2916 | |
5d8b53cf | 2917 | free_mem: |
3b839a57 JR |
2918 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2919 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2920 | } |
2921 | ||
b39ba6ad JR |
2922 | /* |
2923 | * This function is called by the DMA layer to find out if we can handle a | |
2924 | * particular device. It is part of the dma_ops. | |
2925 | */ | |
2926 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2927 | { | |
420aef8a | 2928 | return check_device(dev); |
b39ba6ad JR |
2929 | } |
2930 | ||
a639a8ee JR |
2931 | static int set_dma_mask(struct device *dev, u64 mask) |
2932 | { | |
2933 | struct protection_domain *domain; | |
2934 | int max_apertures = 1; | |
2935 | ||
2936 | domain = get_domain(dev); | |
2937 | if (IS_ERR(domain)) | |
2938 | return PTR_ERR(domain); | |
2939 | ||
2940 | if (mask == DMA_BIT_MASK(64)) | |
2941 | max_apertures = 8; | |
2942 | else if (mask > DMA_BIT_MASK(32)) | |
2943 | max_apertures = 4; | |
2944 | ||
2945 | /* | |
2946 | * To prevent lock contention it doesn't make sense to allocate more | |
2947 | * apertures than online cpus | |
2948 | */ | |
2949 | if (max_apertures > num_online_cpus()) | |
2950 | max_apertures = num_online_cpus(); | |
2951 | ||
2952 | if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures)) | |
2953 | dev_err(dev, "Can't allocate %d iommu apertures\n", | |
2954 | max_apertures); | |
2955 | ||
2956 | return 0; | |
2957 | } | |
2958 | ||
160c1d8e | 2959 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2960 | .alloc = alloc_coherent, |
2961 | .free = free_coherent, | |
2962 | .map_page = map_page, | |
2963 | .unmap_page = unmap_page, | |
2964 | .map_sg = map_sg, | |
2965 | .unmap_sg = unmap_sg, | |
2966 | .dma_supported = amd_iommu_dma_supported, | |
2967 | .set_dma_mask = set_dma_mask, | |
6631ee9d JR |
2968 | }; |
2969 | ||
3a18404c | 2970 | int __init amd_iommu_init_api(void) |
27c2127a | 2971 | { |
3a18404c | 2972 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2973 | } |
2974 | ||
6631ee9d JR |
2975 | int __init amd_iommu_init_dma_ops(void) |
2976 | { | |
32302324 | 2977 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2978 | iommu_detected = 1; |
6631ee9d | 2979 | |
52717828 JR |
2980 | /* |
2981 | * In case we don't initialize SWIOTLB (actually the common case | |
2982 | * when AMD IOMMU is enabled), make sure there are global | |
2983 | * dma_ops set as a fall-back for devices not handled by this | |
2984 | * driver (for example non-PCI devices). | |
2985 | */ | |
2986 | if (!swiotlb) | |
2987 | dma_ops = &nommu_dma_ops; | |
2988 | ||
7f26508b JR |
2989 | amd_iommu_stats_init(); |
2990 | ||
62410eeb JR |
2991 | if (amd_iommu_unmap_flush) |
2992 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2993 | else | |
2994 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2995 | ||
6631ee9d | 2996 | return 0; |
6631ee9d | 2997 | } |
6d98cd80 JR |
2998 | |
2999 | /***************************************************************************** | |
3000 | * | |
3001 | * The following functions belong to the exported interface of AMD IOMMU | |
3002 | * | |
3003 | * This interface allows access to lower level functions of the IOMMU | |
3004 | * like protection domain handling and assignement of devices to domains | |
3005 | * which is not possible with the dma_ops interface. | |
3006 | * | |
3007 | *****************************************************************************/ | |
3008 | ||
6d98cd80 JR |
3009 | static void cleanup_domain(struct protection_domain *domain) |
3010 | { | |
9b29d3c6 | 3011 | struct iommu_dev_data *entry; |
6d98cd80 | 3012 | unsigned long flags; |
6d98cd80 JR |
3013 | |
3014 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3015 | ||
9b29d3c6 JR |
3016 | while (!list_empty(&domain->dev_list)) { |
3017 | entry = list_first_entry(&domain->dev_list, | |
3018 | struct iommu_dev_data, list); | |
3019 | __detach_device(entry); | |
492667da | 3020 | } |
6d98cd80 JR |
3021 | |
3022 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3023 | } | |
3024 | ||
2650815f JR |
3025 | static void protection_domain_free(struct protection_domain *domain) |
3026 | { | |
3027 | if (!domain) | |
3028 | return; | |
3029 | ||
aeb26f55 JR |
3030 | del_domain_from_list(domain); |
3031 | ||
2650815f JR |
3032 | if (domain->id) |
3033 | domain_id_free(domain->id); | |
3034 | ||
3035 | kfree(domain); | |
3036 | } | |
3037 | ||
7a5a566e JR |
3038 | static int protection_domain_init(struct protection_domain *domain) |
3039 | { | |
3040 | spin_lock_init(&domain->lock); | |
3041 | mutex_init(&domain->api_lock); | |
3042 | domain->id = domain_id_alloc(); | |
3043 | if (!domain->id) | |
3044 | return -ENOMEM; | |
3045 | INIT_LIST_HEAD(&domain->dev_list); | |
3046 | ||
3047 | return 0; | |
3048 | } | |
3049 | ||
2650815f | 3050 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
3051 | { |
3052 | struct protection_domain *domain; | |
3053 | ||
3054 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3055 | if (!domain) | |
2650815f | 3056 | return NULL; |
c156e347 | 3057 | |
7a5a566e | 3058 | if (protection_domain_init(domain)) |
2650815f JR |
3059 | goto out_err; |
3060 | ||
aeb26f55 JR |
3061 | add_domain_to_list(domain); |
3062 | ||
2650815f JR |
3063 | return domain; |
3064 | ||
3065 | out_err: | |
3066 | kfree(domain); | |
3067 | ||
3068 | return NULL; | |
3069 | } | |
3070 | ||
3f4b87b9 | 3071 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 3072 | { |
3f4b87b9 | 3073 | struct protection_domain *pdomain; |
0bb6e243 | 3074 | struct dma_ops_domain *dma_domain; |
2650815f | 3075 | |
0bb6e243 JR |
3076 | switch (type) { |
3077 | case IOMMU_DOMAIN_UNMANAGED: | |
3078 | pdomain = protection_domain_alloc(); | |
3079 | if (!pdomain) | |
3080 | return NULL; | |
c156e347 | 3081 | |
0bb6e243 JR |
3082 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3083 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3084 | if (!pdomain->pt_root) { | |
3085 | protection_domain_free(pdomain); | |
3086 | return NULL; | |
3087 | } | |
c156e347 | 3088 | |
0bb6e243 JR |
3089 | pdomain->domain.geometry.aperture_start = 0; |
3090 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3091 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3092 | |
0bb6e243 JR |
3093 | break; |
3094 | case IOMMU_DOMAIN_DMA: | |
3095 | dma_domain = dma_ops_domain_alloc(); | |
3096 | if (!dma_domain) { | |
3097 | pr_err("AMD-Vi: Failed to allocate\n"); | |
3098 | return NULL; | |
3099 | } | |
3100 | pdomain = &dma_domain->domain; | |
3101 | break; | |
07f643a3 JR |
3102 | case IOMMU_DOMAIN_IDENTITY: |
3103 | pdomain = protection_domain_alloc(); | |
3104 | if (!pdomain) | |
3105 | return NULL; | |
c156e347 | 3106 | |
07f643a3 JR |
3107 | pdomain->mode = PAGE_MODE_NONE; |
3108 | break; | |
0bb6e243 JR |
3109 | default: |
3110 | return NULL; | |
3111 | } | |
c156e347 | 3112 | |
3f4b87b9 | 3113 | return &pdomain->domain; |
c156e347 JR |
3114 | } |
3115 | ||
3f4b87b9 | 3116 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3117 | { |
3f4b87b9 | 3118 | struct protection_domain *domain; |
98383fc3 | 3119 | |
3f4b87b9 | 3120 | if (!dom) |
98383fc3 JR |
3121 | return; |
3122 | ||
3f4b87b9 JR |
3123 | domain = to_pdomain(dom); |
3124 | ||
98383fc3 JR |
3125 | if (domain->dev_cnt > 0) |
3126 | cleanup_domain(domain); | |
3127 | ||
3128 | BUG_ON(domain->dev_cnt != 0); | |
3129 | ||
132bd68f JR |
3130 | if (domain->mode != PAGE_MODE_NONE) |
3131 | free_pagetable(domain); | |
98383fc3 | 3132 | |
52815b75 JR |
3133 | if (domain->flags & PD_IOMMUV2_MASK) |
3134 | free_gcr3_table(domain); | |
3135 | ||
8b408fe4 | 3136 | protection_domain_free(domain); |
98383fc3 JR |
3137 | } |
3138 | ||
684f2888 JR |
3139 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3140 | struct device *dev) | |
3141 | { | |
657cbb6b | 3142 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3143 | struct amd_iommu *iommu; |
7aba6cb9 | 3144 | int devid; |
684f2888 | 3145 | |
98fc5a69 | 3146 | if (!check_device(dev)) |
684f2888 JR |
3147 | return; |
3148 | ||
98fc5a69 | 3149 | devid = get_device_id(dev); |
7aba6cb9 WZ |
3150 | if (IS_ERR_VALUE(devid)) |
3151 | return; | |
684f2888 | 3152 | |
657cbb6b | 3153 | if (dev_data->domain != NULL) |
15898bbc | 3154 | detach_device(dev); |
684f2888 JR |
3155 | |
3156 | iommu = amd_iommu_rlookup_table[devid]; | |
3157 | if (!iommu) | |
3158 | return; | |
3159 | ||
684f2888 JR |
3160 | iommu_completion_wait(iommu); |
3161 | } | |
3162 | ||
01106066 JR |
3163 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3164 | struct device *dev) | |
3165 | { | |
3f4b87b9 | 3166 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3167 | struct iommu_dev_data *dev_data; |
01106066 | 3168 | struct amd_iommu *iommu; |
15898bbc | 3169 | int ret; |
01106066 | 3170 | |
98fc5a69 | 3171 | if (!check_device(dev)) |
01106066 JR |
3172 | return -EINVAL; |
3173 | ||
657cbb6b JR |
3174 | dev_data = dev->archdata.iommu; |
3175 | ||
f62dda66 | 3176 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3177 | if (!iommu) |
3178 | return -EINVAL; | |
3179 | ||
657cbb6b | 3180 | if (dev_data->domain) |
15898bbc | 3181 | detach_device(dev); |
01106066 | 3182 | |
15898bbc | 3183 | ret = attach_device(dev, domain); |
01106066 JR |
3184 | |
3185 | iommu_completion_wait(iommu); | |
3186 | ||
15898bbc | 3187 | return ret; |
01106066 JR |
3188 | } |
3189 | ||
468e2366 | 3190 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3191 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3192 | { |
3f4b87b9 | 3193 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3194 | int prot = 0; |
3195 | int ret; | |
3196 | ||
132bd68f JR |
3197 | if (domain->mode == PAGE_MODE_NONE) |
3198 | return -EINVAL; | |
3199 | ||
c6229ca6 JR |
3200 | if (iommu_prot & IOMMU_READ) |
3201 | prot |= IOMMU_PROT_IR; | |
3202 | if (iommu_prot & IOMMU_WRITE) | |
3203 | prot |= IOMMU_PROT_IW; | |
3204 | ||
5d214fe6 | 3205 | mutex_lock(&domain->api_lock); |
795e74f7 | 3206 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3207 | mutex_unlock(&domain->api_lock); |
3208 | ||
795e74f7 | 3209 | return ret; |
c6229ca6 JR |
3210 | } |
3211 | ||
5009065d OBC |
3212 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3213 | size_t page_size) | |
eb74ff6c | 3214 | { |
3f4b87b9 | 3215 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3216 | size_t unmap_size; |
eb74ff6c | 3217 | |
132bd68f JR |
3218 | if (domain->mode == PAGE_MODE_NONE) |
3219 | return -EINVAL; | |
3220 | ||
5d214fe6 | 3221 | mutex_lock(&domain->api_lock); |
468e2366 | 3222 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3223 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3224 | |
17b124bf | 3225 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3226 | |
5009065d | 3227 | return unmap_size; |
eb74ff6c JR |
3228 | } |
3229 | ||
645c4c8d | 3230 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3231 | dma_addr_t iova) |
645c4c8d | 3232 | { |
3f4b87b9 | 3233 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3234 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3235 | u64 *pte, __pte; |
645c4c8d | 3236 | |
132bd68f JR |
3237 | if (domain->mode == PAGE_MODE_NONE) |
3238 | return iova; | |
3239 | ||
3039ca1b | 3240 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3241 | |
a6d41a40 | 3242 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3243 | return 0; |
3244 | ||
b24b1b63 JR |
3245 | offset_mask = pte_pgsize - 1; |
3246 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3247 | |
b24b1b63 | 3248 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3249 | } |
3250 | ||
ab636481 | 3251 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3252 | { |
80a506b8 JR |
3253 | switch (cap) { |
3254 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3255 | return true; |
bdddadcb | 3256 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3257 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3258 | case IOMMU_CAP_NOEXEC: |
3259 | return false; | |
80a506b8 JR |
3260 | } |
3261 | ||
ab636481 | 3262 | return false; |
dbb9fd86 SY |
3263 | } |
3264 | ||
35cf248f JR |
3265 | static void amd_iommu_get_dm_regions(struct device *dev, |
3266 | struct list_head *head) | |
3267 | { | |
3268 | struct unity_map_entry *entry; | |
7aba6cb9 | 3269 | int devid; |
35cf248f JR |
3270 | |
3271 | devid = get_device_id(dev); | |
7aba6cb9 WZ |
3272 | if (IS_ERR_VALUE(devid)) |
3273 | return; | |
35cf248f JR |
3274 | |
3275 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3276 | struct iommu_dm_region *region; | |
3277 | ||
3278 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3279 | continue; | |
3280 | ||
3281 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3282 | if (!region) { | |
3283 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3284 | dev_name(dev)); | |
3285 | return; | |
3286 | } | |
3287 | ||
3288 | region->start = entry->address_start; | |
3289 | region->length = entry->address_end - entry->address_start; | |
3290 | if (entry->prot & IOMMU_PROT_IR) | |
3291 | region->prot |= IOMMU_READ; | |
3292 | if (entry->prot & IOMMU_PROT_IW) | |
3293 | region->prot |= IOMMU_WRITE; | |
3294 | ||
3295 | list_add_tail(®ion->list, head); | |
3296 | } | |
3297 | } | |
3298 | ||
3299 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3300 | struct list_head *head) | |
3301 | { | |
3302 | struct iommu_dm_region *entry, *next; | |
3303 | ||
3304 | list_for_each_entry_safe(entry, next, head, list) | |
3305 | kfree(entry); | |
3306 | } | |
3307 | ||
b22f6434 | 3308 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3309 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3310 | .domain_alloc = amd_iommu_domain_alloc, |
3311 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3312 | .attach_dev = amd_iommu_attach_device, |
3313 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3314 | .map = amd_iommu_map, |
3315 | .unmap = amd_iommu_unmap, | |
315786eb | 3316 | .map_sg = default_iommu_map_sg, |
26961efe | 3317 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3318 | .add_device = amd_iommu_add_device, |
3319 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3320 | .device_group = amd_iommu_device_group, |
35cf248f JR |
3321 | .get_dm_regions = amd_iommu_get_dm_regions, |
3322 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3323 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3324 | }; |
3325 | ||
0feae533 JR |
3326 | /***************************************************************************** |
3327 | * | |
3328 | * The next functions do a basic initialization of IOMMU for pass through | |
3329 | * mode | |
3330 | * | |
3331 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3332 | * DMA-API translation. | |
3333 | * | |
3334 | *****************************************************************************/ | |
3335 | ||
72e1dcc4 JR |
3336 | /* IOMMUv2 specific functions */ |
3337 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3338 | { | |
3339 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3340 | } | |
3341 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3342 | ||
3343 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3344 | { | |
3345 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3346 | } | |
3347 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3348 | |
3349 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3350 | { | |
3f4b87b9 | 3351 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3352 | unsigned long flags; |
3353 | ||
3354 | spin_lock_irqsave(&domain->lock, flags); | |
3355 | ||
3356 | /* Update data structure */ | |
3357 | domain->mode = PAGE_MODE_NONE; | |
3358 | domain->updated = true; | |
3359 | ||
3360 | /* Make changes visible to IOMMUs */ | |
3361 | update_domain(domain); | |
3362 | ||
3363 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3364 | free_pagetable(domain); | |
3365 | ||
3366 | spin_unlock_irqrestore(&domain->lock, flags); | |
3367 | } | |
3368 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3369 | |
3370 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3371 | { | |
3f4b87b9 | 3372 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3373 | unsigned long flags; |
3374 | int levels, ret; | |
3375 | ||
3376 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3377 | return -EINVAL; | |
3378 | ||
3379 | /* Number of GCR3 table levels required */ | |
3380 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3381 | levels += 1; | |
3382 | ||
3383 | if (levels > amd_iommu_max_glx_val) | |
3384 | return -EINVAL; | |
3385 | ||
3386 | spin_lock_irqsave(&domain->lock, flags); | |
3387 | ||
3388 | /* | |
3389 | * Save us all sanity checks whether devices already in the | |
3390 | * domain support IOMMUv2. Just force that the domain has no | |
3391 | * devices attached when it is switched into IOMMUv2 mode. | |
3392 | */ | |
3393 | ret = -EBUSY; | |
3394 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3395 | goto out; | |
3396 | ||
3397 | ret = -ENOMEM; | |
3398 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3399 | if (domain->gcr3_tbl == NULL) | |
3400 | goto out; | |
3401 | ||
3402 | domain->glx = levels; | |
3403 | domain->flags |= PD_IOMMUV2_MASK; | |
3404 | domain->updated = true; | |
3405 | ||
3406 | update_domain(domain); | |
3407 | ||
3408 | ret = 0; | |
3409 | ||
3410 | out: | |
3411 | spin_unlock_irqrestore(&domain->lock, flags); | |
3412 | ||
3413 | return ret; | |
3414 | } | |
3415 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3416 | |
3417 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3418 | u64 address, bool size) | |
3419 | { | |
3420 | struct iommu_dev_data *dev_data; | |
3421 | struct iommu_cmd cmd; | |
3422 | int i, ret; | |
3423 | ||
3424 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3425 | return -EINVAL; | |
3426 | ||
3427 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3428 | ||
3429 | /* | |
3430 | * IOMMU TLB needs to be flushed before Device TLB to | |
3431 | * prevent device TLB refill from IOMMU TLB | |
3432 | */ | |
3433 | for (i = 0; i < amd_iommus_present; ++i) { | |
3434 | if (domain->dev_iommu[i] == 0) | |
3435 | continue; | |
3436 | ||
3437 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3438 | if (ret != 0) | |
3439 | goto out; | |
3440 | } | |
3441 | ||
3442 | /* Wait until IOMMU TLB flushes are complete */ | |
3443 | domain_flush_complete(domain); | |
3444 | ||
3445 | /* Now flush device TLBs */ | |
3446 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3447 | struct amd_iommu *iommu; | |
3448 | int qdep; | |
3449 | ||
1c1cc454 JR |
3450 | /* |
3451 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3452 | * domain. | |
3453 | */ | |
3454 | if (!dev_data->ats.enabled) | |
3455 | continue; | |
22e266c7 JR |
3456 | |
3457 | qdep = dev_data->ats.qdep; | |
3458 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3459 | ||
3460 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3461 | qdep, address, size); | |
3462 | ||
3463 | ret = iommu_queue_command(iommu, &cmd); | |
3464 | if (ret != 0) | |
3465 | goto out; | |
3466 | } | |
3467 | ||
3468 | /* Wait until all device TLBs are flushed */ | |
3469 | domain_flush_complete(domain); | |
3470 | ||
3471 | ret = 0; | |
3472 | ||
3473 | out: | |
3474 | ||
3475 | return ret; | |
3476 | } | |
3477 | ||
3478 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3479 | u64 address) | |
3480 | { | |
399be2f5 JR |
3481 | INC_STATS_COUNTER(invalidate_iotlb); |
3482 | ||
22e266c7 JR |
3483 | return __flush_pasid(domain, pasid, address, false); |
3484 | } | |
3485 | ||
3486 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3487 | u64 address) | |
3488 | { | |
3f4b87b9 | 3489 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3490 | unsigned long flags; |
3491 | int ret; | |
3492 | ||
3493 | spin_lock_irqsave(&domain->lock, flags); | |
3494 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3495 | spin_unlock_irqrestore(&domain->lock, flags); | |
3496 | ||
3497 | return ret; | |
3498 | } | |
3499 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3500 | ||
3501 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3502 | { | |
399be2f5 JR |
3503 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3504 | ||
22e266c7 JR |
3505 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3506 | true); | |
3507 | } | |
3508 | ||
3509 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3510 | { | |
3f4b87b9 | 3511 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3512 | unsigned long flags; |
3513 | int ret; | |
3514 | ||
3515 | spin_lock_irqsave(&domain->lock, flags); | |
3516 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3517 | spin_unlock_irqrestore(&domain->lock, flags); | |
3518 | ||
3519 | return ret; | |
3520 | } | |
3521 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3522 | ||
b16137b1 JR |
3523 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3524 | { | |
3525 | int index; | |
3526 | u64 *pte; | |
3527 | ||
3528 | while (true) { | |
3529 | ||
3530 | index = (pasid >> (9 * level)) & 0x1ff; | |
3531 | pte = &root[index]; | |
3532 | ||
3533 | if (level == 0) | |
3534 | break; | |
3535 | ||
3536 | if (!(*pte & GCR3_VALID)) { | |
3537 | if (!alloc) | |
3538 | return NULL; | |
3539 | ||
3540 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3541 | if (root == NULL) | |
3542 | return NULL; | |
3543 | ||
3544 | *pte = __pa(root) | GCR3_VALID; | |
3545 | } | |
3546 | ||
3547 | root = __va(*pte & PAGE_MASK); | |
3548 | ||
3549 | level -= 1; | |
3550 | } | |
3551 | ||
3552 | return pte; | |
3553 | } | |
3554 | ||
3555 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3556 | unsigned long cr3) | |
3557 | { | |
3558 | u64 *pte; | |
3559 | ||
3560 | if (domain->mode != PAGE_MODE_NONE) | |
3561 | return -EINVAL; | |
3562 | ||
3563 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3564 | if (pte == NULL) | |
3565 | return -ENOMEM; | |
3566 | ||
3567 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3568 | ||
3569 | return __amd_iommu_flush_tlb(domain, pasid); | |
3570 | } | |
3571 | ||
3572 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3573 | { | |
3574 | u64 *pte; | |
3575 | ||
3576 | if (domain->mode != PAGE_MODE_NONE) | |
3577 | return -EINVAL; | |
3578 | ||
3579 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3580 | if (pte == NULL) | |
3581 | return 0; | |
3582 | ||
3583 | *pte = 0; | |
3584 | ||
3585 | return __amd_iommu_flush_tlb(domain, pasid); | |
3586 | } | |
3587 | ||
3588 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3589 | unsigned long cr3) | |
3590 | { | |
3f4b87b9 | 3591 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3592 | unsigned long flags; |
3593 | int ret; | |
3594 | ||
3595 | spin_lock_irqsave(&domain->lock, flags); | |
3596 | ret = __set_gcr3(domain, pasid, cr3); | |
3597 | spin_unlock_irqrestore(&domain->lock, flags); | |
3598 | ||
3599 | return ret; | |
3600 | } | |
3601 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3602 | ||
3603 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3604 | { | |
3f4b87b9 | 3605 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3606 | unsigned long flags; |
3607 | int ret; | |
3608 | ||
3609 | spin_lock_irqsave(&domain->lock, flags); | |
3610 | ret = __clear_gcr3(domain, pasid); | |
3611 | spin_unlock_irqrestore(&domain->lock, flags); | |
3612 | ||
3613 | return ret; | |
3614 | } | |
3615 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3616 | |
3617 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3618 | int status, int tag) | |
3619 | { | |
3620 | struct iommu_dev_data *dev_data; | |
3621 | struct amd_iommu *iommu; | |
3622 | struct iommu_cmd cmd; | |
3623 | ||
399be2f5 JR |
3624 | INC_STATS_COUNTER(complete_ppr); |
3625 | ||
c99afa25 JR |
3626 | dev_data = get_dev_data(&pdev->dev); |
3627 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3628 | ||
3629 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3630 | tag, dev_data->pri_tlp); | |
3631 | ||
3632 | return iommu_queue_command(iommu, &cmd); | |
3633 | } | |
3634 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3635 | |
3636 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3637 | { | |
3f4b87b9 | 3638 | struct protection_domain *pdomain; |
f3572db8 | 3639 | |
3f4b87b9 JR |
3640 | pdomain = get_domain(&pdev->dev); |
3641 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3642 | return NULL; |
3643 | ||
3644 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3645 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3646 | return NULL; |
3647 | ||
3f4b87b9 | 3648 | return &pdomain->domain; |
f3572db8 JR |
3649 | } |
3650 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3651 | |
3652 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3653 | { | |
3654 | struct iommu_dev_data *dev_data; | |
3655 | ||
3656 | if (!amd_iommu_v2_supported()) | |
3657 | return; | |
3658 | ||
3659 | dev_data = get_dev_data(&pdev->dev); | |
3660 | dev_data->errata |= (1 << erratum); | |
3661 | } | |
3662 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3663 | |
3664 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3665 | struct amd_iommu_device_info *info) | |
3666 | { | |
3667 | int max_pasids; | |
3668 | int pos; | |
3669 | ||
3670 | if (pdev == NULL || info == NULL) | |
3671 | return -EINVAL; | |
3672 | ||
3673 | if (!amd_iommu_v2_supported()) | |
3674 | return -EINVAL; | |
3675 | ||
3676 | memset(info, 0, sizeof(*info)); | |
3677 | ||
3678 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3679 | if (pos) | |
3680 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3681 | ||
3682 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3683 | if (pos) | |
3684 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3685 | ||
3686 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3687 | if (pos) { | |
3688 | int features; | |
3689 | ||
3690 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3691 | max_pasids = min(max_pasids, (1 << 20)); | |
3692 | ||
3693 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3694 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3695 | ||
3696 | features = pci_pasid_features(pdev); | |
3697 | if (features & PCI_PASID_CAP_EXEC) | |
3698 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3699 | if (features & PCI_PASID_CAP_PRIV) | |
3700 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3701 | } | |
3702 | ||
3703 | return 0; | |
3704 | } | |
3705 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3706 | |
3707 | #ifdef CONFIG_IRQ_REMAP | |
3708 | ||
3709 | /***************************************************************************** | |
3710 | * | |
3711 | * Interrupt Remapping Implementation | |
3712 | * | |
3713 | *****************************************************************************/ | |
3714 | ||
3715 | union irte { | |
3716 | u32 val; | |
3717 | struct { | |
3718 | u32 valid : 1, | |
3719 | no_fault : 1, | |
3720 | int_type : 3, | |
3721 | rq_eoi : 1, | |
3722 | dm : 1, | |
3723 | rsvd_1 : 1, | |
3724 | destination : 8, | |
3725 | vector : 8, | |
3726 | rsvd_2 : 8; | |
3727 | } fields; | |
3728 | }; | |
3729 | ||
9c724966 JL |
3730 | struct irq_2_irte { |
3731 | u16 devid; /* Device ID for IRTE table */ | |
3732 | u16 index; /* Index into IRTE table*/ | |
3733 | }; | |
3734 | ||
7c71d306 JL |
3735 | struct amd_ir_data { |
3736 | struct irq_2_irte irq_2_irte; | |
3737 | union irte irte_entry; | |
3738 | union { | |
3739 | struct msi_msg msi_entry; | |
3740 | }; | |
3741 | }; | |
3742 | ||
3743 | static struct irq_chip amd_ir_chip; | |
3744 | ||
2b324506 JR |
3745 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3746 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3747 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3748 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3749 | ||
3750 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3751 | { | |
3752 | u64 dte; | |
3753 | ||
3754 | dte = amd_iommu_dev_table[devid].data[2]; | |
3755 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3756 | dte |= virt_to_phys(table->table); | |
3757 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3758 | dte |= DTE_IRQ_TABLE_LEN; | |
3759 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3760 | ||
3761 | amd_iommu_dev_table[devid].data[2] = dte; | |
3762 | } | |
3763 | ||
3764 | #define IRTE_ALLOCATED (~1U) | |
3765 | ||
3766 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3767 | { | |
3768 | struct irq_remap_table *table = NULL; | |
3769 | struct amd_iommu *iommu; | |
3770 | unsigned long flags; | |
3771 | u16 alias; | |
3772 | ||
3773 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3774 | ||
3775 | iommu = amd_iommu_rlookup_table[devid]; | |
3776 | if (!iommu) | |
3777 | goto out_unlock; | |
3778 | ||
3779 | table = irq_lookup_table[devid]; | |
3780 | if (table) | |
3781 | goto out; | |
3782 | ||
3783 | alias = amd_iommu_alias_table[devid]; | |
3784 | table = irq_lookup_table[alias]; | |
3785 | if (table) { | |
3786 | irq_lookup_table[devid] = table; | |
3787 | set_dte_irq_entry(devid, table); | |
3788 | iommu_flush_dte(iommu, devid); | |
3789 | goto out; | |
3790 | } | |
3791 | ||
3792 | /* Nothing there yet, allocate new irq remapping table */ | |
3793 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3794 | if (!table) | |
3795 | goto out; | |
3796 | ||
197887f0 JR |
3797 | /* Initialize table spin-lock */ |
3798 | spin_lock_init(&table->lock); | |
3799 | ||
2b324506 JR |
3800 | if (ioapic) |
3801 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3802 | table->min_index = 32; | |
3803 | ||
3804 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3805 | if (!table->table) { | |
3806 | kfree(table); | |
821f0f68 | 3807 | table = NULL; |
2b324506 JR |
3808 | goto out; |
3809 | } | |
3810 | ||
3811 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3812 | ||
3813 | if (ioapic) { | |
3814 | int i; | |
3815 | ||
3816 | for (i = 0; i < 32; ++i) | |
3817 | table->table[i] = IRTE_ALLOCATED; | |
3818 | } | |
3819 | ||
3820 | irq_lookup_table[devid] = table; | |
3821 | set_dte_irq_entry(devid, table); | |
3822 | iommu_flush_dte(iommu, devid); | |
3823 | if (devid != alias) { | |
3824 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3825 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3826 | iommu_flush_dte(iommu, alias); |
3827 | } | |
3828 | ||
3829 | out: | |
3830 | iommu_completion_wait(iommu); | |
3831 | ||
3832 | out_unlock: | |
3833 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3834 | ||
3835 | return table; | |
3836 | } | |
3837 | ||
3c3d4f90 | 3838 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3839 | { |
3840 | struct irq_remap_table *table; | |
3841 | unsigned long flags; | |
3842 | int index, c; | |
3843 | ||
3844 | table = get_irq_table(devid, false); | |
3845 | if (!table) | |
3846 | return -ENODEV; | |
3847 | ||
3848 | spin_lock_irqsave(&table->lock, flags); | |
3849 | ||
3850 | /* Scan table for free entries */ | |
3851 | for (c = 0, index = table->min_index; | |
3852 | index < MAX_IRQS_PER_TABLE; | |
3853 | ++index) { | |
3854 | if (table->table[index] == 0) | |
3855 | c += 1; | |
3856 | else | |
3857 | c = 0; | |
3858 | ||
3859 | if (c == count) { | |
2b324506 JR |
3860 | for (; c != 0; --c) |
3861 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3862 | ||
3863 | index -= count - 1; | |
2b324506 JR |
3864 | goto out; |
3865 | } | |
3866 | } | |
3867 | ||
3868 | index = -ENOSPC; | |
3869 | ||
3870 | out: | |
3871 | spin_unlock_irqrestore(&table->lock, flags); | |
3872 | ||
3873 | return index; | |
3874 | } | |
3875 | ||
2b324506 JR |
3876 | static int modify_irte(u16 devid, int index, union irte irte) |
3877 | { | |
3878 | struct irq_remap_table *table; | |
3879 | struct amd_iommu *iommu; | |
3880 | unsigned long flags; | |
3881 | ||
3882 | iommu = amd_iommu_rlookup_table[devid]; | |
3883 | if (iommu == NULL) | |
3884 | return -EINVAL; | |
3885 | ||
3886 | table = get_irq_table(devid, false); | |
3887 | if (!table) | |
3888 | return -ENOMEM; | |
3889 | ||
3890 | spin_lock_irqsave(&table->lock, flags); | |
3891 | table->table[index] = irte.val; | |
3892 | spin_unlock_irqrestore(&table->lock, flags); | |
3893 | ||
3894 | iommu_flush_irt(iommu, devid); | |
3895 | iommu_completion_wait(iommu); | |
3896 | ||
3897 | return 0; | |
3898 | } | |
3899 | ||
3900 | static void free_irte(u16 devid, int index) | |
3901 | { | |
3902 | struct irq_remap_table *table; | |
3903 | struct amd_iommu *iommu; | |
3904 | unsigned long flags; | |
3905 | ||
3906 | iommu = amd_iommu_rlookup_table[devid]; | |
3907 | if (iommu == NULL) | |
3908 | return; | |
3909 | ||
3910 | table = get_irq_table(devid, false); | |
3911 | if (!table) | |
3912 | return; | |
3913 | ||
3914 | spin_lock_irqsave(&table->lock, flags); | |
3915 | table->table[index] = 0; | |
3916 | spin_unlock_irqrestore(&table->lock, flags); | |
3917 | ||
3918 | iommu_flush_irt(iommu, devid); | |
3919 | iommu_completion_wait(iommu); | |
3920 | } | |
3921 | ||
7c71d306 | 3922 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3923 | { |
7c71d306 | 3924 | int devid = -1; |
5527de74 | 3925 | |
7c71d306 JL |
3926 | switch (info->type) { |
3927 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3928 | devid = get_ioapic_devid(info->ioapic_id); | |
3929 | break; | |
3930 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3931 | devid = get_hpet_devid(info->hpet_id); | |
3932 | break; | |
3933 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3934 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3935 | devid = get_device_id(&info->msi_dev->dev); | |
3936 | break; | |
3937 | default: | |
3938 | BUG_ON(1); | |
3939 | break; | |
3940 | } | |
5527de74 | 3941 | |
7c71d306 JL |
3942 | return devid; |
3943 | } | |
5527de74 | 3944 | |
7c71d306 JL |
3945 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3946 | { | |
3947 | struct amd_iommu *iommu; | |
3948 | int devid; | |
5527de74 | 3949 | |
7c71d306 JL |
3950 | if (!info) |
3951 | return NULL; | |
5527de74 | 3952 | |
7c71d306 JL |
3953 | devid = get_devid(info); |
3954 | if (devid >= 0) { | |
3955 | iommu = amd_iommu_rlookup_table[devid]; | |
3956 | if (iommu) | |
3957 | return iommu->ir_domain; | |
3958 | } | |
5527de74 | 3959 | |
7c71d306 | 3960 | return NULL; |
5527de74 JR |
3961 | } |
3962 | ||
7c71d306 | 3963 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3964 | { |
7c71d306 JL |
3965 | struct amd_iommu *iommu; |
3966 | int devid; | |
5527de74 | 3967 | |
7c71d306 JL |
3968 | if (!info) |
3969 | return NULL; | |
5527de74 | 3970 | |
7c71d306 JL |
3971 | switch (info->type) { |
3972 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3973 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3974 | devid = get_device_id(&info->msi_dev->dev); | |
7aba6cb9 WZ |
3975 | if (IS_ERR_VALUE(devid)) |
3976 | return NULL; | |
3977 | ||
1fb260bc DC |
3978 | iommu = amd_iommu_rlookup_table[devid]; |
3979 | if (iommu) | |
3980 | return iommu->msi_domain; | |
7c71d306 JL |
3981 | break; |
3982 | default: | |
3983 | break; | |
3984 | } | |
5527de74 | 3985 | |
7c71d306 JL |
3986 | return NULL; |
3987 | } | |
5527de74 | 3988 | |
6b474b82 | 3989 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3990 | .prepare = amd_iommu_prepare, |
3991 | .enable = amd_iommu_enable, | |
3992 | .disable = amd_iommu_disable, | |
3993 | .reenable = amd_iommu_reenable, | |
3994 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3995 | .get_ir_irq_domain = get_ir_irq_domain, |
3996 | .get_irq_domain = get_irq_domain, | |
3997 | }; | |
5527de74 | 3998 | |
7c71d306 JL |
3999 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4000 | struct irq_cfg *irq_cfg, | |
4001 | struct irq_alloc_info *info, | |
4002 | int devid, int index, int sub_handle) | |
4003 | { | |
4004 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4005 | struct msi_msg *msg = &data->msi_entry; | |
4006 | union irte *irte = &data->irte_entry; | |
4007 | struct IO_APIC_route_entry *entry; | |
5527de74 | 4008 | |
7c71d306 JL |
4009 | data->irq_2_irte.devid = devid; |
4010 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 4011 | |
7c71d306 JL |
4012 | /* Setup IRTE for IOMMU */ |
4013 | irte->val = 0; | |
4014 | irte->fields.vector = irq_cfg->vector; | |
4015 | irte->fields.int_type = apic->irq_delivery_mode; | |
4016 | irte->fields.destination = irq_cfg->dest_apicid; | |
4017 | irte->fields.dm = apic->irq_dest_mode; | |
4018 | irte->fields.valid = 1; | |
4019 | ||
4020 | switch (info->type) { | |
4021 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4022 | /* Setup IOAPIC entry */ | |
4023 | entry = info->ioapic_entry; | |
4024 | info->ioapic_entry = NULL; | |
4025 | memset(entry, 0, sizeof(*entry)); | |
4026 | entry->vector = index; | |
4027 | entry->mask = 0; | |
4028 | entry->trigger = info->ioapic_trigger; | |
4029 | entry->polarity = info->ioapic_polarity; | |
4030 | /* Mask level triggered irqs. */ | |
4031 | if (info->ioapic_trigger) | |
4032 | entry->mask = 1; | |
4033 | break; | |
5527de74 | 4034 | |
7c71d306 JL |
4035 | case X86_IRQ_ALLOC_TYPE_HPET: |
4036 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4037 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4038 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4039 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4040 | msg->data = irte_info->index; | |
4041 | break; | |
5527de74 | 4042 | |
7c71d306 JL |
4043 | default: |
4044 | BUG_ON(1); | |
4045 | break; | |
4046 | } | |
5527de74 JR |
4047 | } |
4048 | ||
7c71d306 JL |
4049 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4050 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4051 | { |
7c71d306 JL |
4052 | struct irq_alloc_info *info = arg; |
4053 | struct irq_data *irq_data; | |
4054 | struct amd_ir_data *data; | |
5527de74 | 4055 | struct irq_cfg *cfg; |
7c71d306 JL |
4056 | int i, ret, devid; |
4057 | int index = -1; | |
5527de74 | 4058 | |
7c71d306 JL |
4059 | if (!info) |
4060 | return -EINVAL; | |
4061 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4062 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4063 | return -EINVAL; |
4064 | ||
7c71d306 JL |
4065 | /* |
4066 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4067 | * to support multiple MSI interrupts. | |
4068 | */ | |
4069 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4070 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4071 | |
7c71d306 JL |
4072 | devid = get_devid(info); |
4073 | if (devid < 0) | |
4074 | return -EINVAL; | |
5527de74 | 4075 | |
7c71d306 JL |
4076 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4077 | if (ret < 0) | |
4078 | return ret; | |
0b4d48cb | 4079 | |
7c71d306 JL |
4080 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4081 | if (get_irq_table(devid, true)) | |
4082 | index = info->ioapic_pin; | |
4083 | else | |
4084 | ret = -ENOMEM; | |
4085 | } else { | |
3c3d4f90 | 4086 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4087 | } |
4088 | if (index < 0) { | |
4089 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
4090 | goto out_free_parent; |
4091 | } | |
0b4d48cb | 4092 | |
7c71d306 JL |
4093 | for (i = 0; i < nr_irqs; i++) { |
4094 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4095 | cfg = irqd_cfg(irq_data); | |
4096 | if (!irq_data || !cfg) { | |
4097 | ret = -EINVAL; | |
4098 | goto out_free_data; | |
4099 | } | |
0b4d48cb | 4100 | |
a130e69f JR |
4101 | ret = -ENOMEM; |
4102 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4103 | if (!data) | |
4104 | goto out_free_data; | |
4105 | ||
7c71d306 JL |
4106 | irq_data->hwirq = (devid << 16) + i; |
4107 | irq_data->chip_data = data; | |
4108 | irq_data->chip = &amd_ir_chip; | |
4109 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4110 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4111 | } | |
a130e69f | 4112 | |
7c71d306 | 4113 | return 0; |
0b4d48cb | 4114 | |
7c71d306 JL |
4115 | out_free_data: |
4116 | for (i--; i >= 0; i--) { | |
4117 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4118 | if (irq_data) | |
4119 | kfree(irq_data->chip_data); | |
4120 | } | |
4121 | for (i = 0; i < nr_irqs; i++) | |
4122 | free_irte(devid, index + i); | |
4123 | out_free_parent: | |
4124 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4125 | return ret; | |
0b4d48cb JR |
4126 | } |
4127 | ||
7c71d306 JL |
4128 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4129 | unsigned int nr_irqs) | |
0b4d48cb | 4130 | { |
7c71d306 JL |
4131 | struct irq_2_irte *irte_info; |
4132 | struct irq_data *irq_data; | |
4133 | struct amd_ir_data *data; | |
4134 | int i; | |
0b4d48cb | 4135 | |
7c71d306 JL |
4136 | for (i = 0; i < nr_irqs; i++) { |
4137 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4138 | if (irq_data && irq_data->chip_data) { | |
4139 | data = irq_data->chip_data; | |
4140 | irte_info = &data->irq_2_irte; | |
4141 | free_irte(irte_info->devid, irte_info->index); | |
4142 | kfree(data); | |
4143 | } | |
4144 | } | |
4145 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4146 | } | |
0b4d48cb | 4147 | |
7c71d306 JL |
4148 | static void irq_remapping_activate(struct irq_domain *domain, |
4149 | struct irq_data *irq_data) | |
4150 | { | |
4151 | struct amd_ir_data *data = irq_data->chip_data; | |
4152 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4153 | |
7c71d306 | 4154 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4155 | } |
4156 | ||
7c71d306 JL |
4157 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4158 | struct irq_data *irq_data) | |
0b4d48cb | 4159 | { |
7c71d306 JL |
4160 | struct amd_ir_data *data = irq_data->chip_data; |
4161 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4162 | union irte entry; | |
0b4d48cb | 4163 | |
7c71d306 JL |
4164 | entry.val = 0; |
4165 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4166 | } | |
0b4d48cb | 4167 | |
7c71d306 JL |
4168 | static struct irq_domain_ops amd_ir_domain_ops = { |
4169 | .alloc = irq_remapping_alloc, | |
4170 | .free = irq_remapping_free, | |
4171 | .activate = irq_remapping_activate, | |
4172 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4173 | }; |
0b4d48cb | 4174 | |
7c71d306 JL |
4175 | static int amd_ir_set_affinity(struct irq_data *data, |
4176 | const struct cpumask *mask, bool force) | |
4177 | { | |
4178 | struct amd_ir_data *ir_data = data->chip_data; | |
4179 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4180 | struct irq_cfg *cfg = irqd_cfg(data); | |
4181 | struct irq_data *parent = data->parent_data; | |
4182 | int ret; | |
0b4d48cb | 4183 | |
7c71d306 JL |
4184 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4185 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4186 | return ret; | |
0b4d48cb | 4187 | |
7c71d306 JL |
4188 | /* |
4189 | * Atomically updates the IRTE with the new destination, vector | |
4190 | * and flushes the interrupt entry cache. | |
4191 | */ | |
4192 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4193 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4194 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4195 | |
7c71d306 JL |
4196 | /* |
4197 | * After this point, all the interrupts will start arriving | |
4198 | * at the new destination. So, time to cleanup the previous | |
4199 | * vector allocation. | |
4200 | */ | |
c6c2002b | 4201 | send_cleanup_vector(cfg); |
7c71d306 JL |
4202 | |
4203 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4204 | } |
4205 | ||
7c71d306 | 4206 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4207 | { |
7c71d306 | 4208 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4209 | |
7c71d306 JL |
4210 | *msg = ir_data->msi_entry; |
4211 | } | |
d976195c | 4212 | |
7c71d306 JL |
4213 | static struct irq_chip amd_ir_chip = { |
4214 | .irq_ack = ir_ack_apic_edge, | |
4215 | .irq_set_affinity = amd_ir_set_affinity, | |
4216 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4217 | }; | |
d976195c | 4218 | |
7c71d306 JL |
4219 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4220 | { | |
4221 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4222 | if (!iommu->ir_domain) | |
4223 | return -ENOMEM; | |
d976195c | 4224 | |
7c71d306 JL |
4225 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4226 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4227 | |
4228 | return 0; | |
4229 | } | |
2b324506 | 4230 | #endif |