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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 JR |
56 | |
57 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
58 | ||
815b33fd | 59 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 60 | |
307d5851 JR |
61 | /* IO virtual address start page frame number */ |
62 | #define IOVA_START_PFN (1) | |
63 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
64 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) | |
65 | ||
81cd07b9 JR |
66 | /* Reserved IOVA ranges */ |
67 | #define MSI_RANGE_START (0xfee00000) | |
68 | #define MSI_RANGE_END (0xfeefffff) | |
69 | #define HT_RANGE_START (0xfd00000000ULL) | |
70 | #define HT_RANGE_END (0xffffffffffULL) | |
71 | ||
aa3de9c0 OBC |
72 | /* |
73 | * This bitmap is used to advertise the page sizes our hardware support | |
74 | * to the IOMMU core, which will then use this information to split | |
75 | * physically contiguous memory regions it is mapping into page sizes | |
76 | * that we support. | |
77 | * | |
954e3dd8 | 78 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 79 | */ |
954e3dd8 | 80 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 81 | |
b6c02715 JR |
82 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
83 | ||
8fa5f802 JR |
84 | /* List of all available dev_data structures */ |
85 | static LIST_HEAD(dev_data_list); | |
86 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
87 | ||
6efed63b JR |
88 | LIST_HEAD(ioapic_map); |
89 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 90 | LIST_HEAD(acpihid_map); |
6efed63b | 91 | |
0feae533 JR |
92 | /* |
93 | * Domain for untranslated devices - only allocated | |
94 | * if iommu=pt passed on kernel cmd line. | |
95 | */ | |
b22f6434 | 96 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 97 | |
72e1dcc4 | 98 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 99 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 100 | |
ac1534a5 JR |
101 | static struct dma_map_ops amd_iommu_dma_ops; |
102 | ||
50917e26 JR |
103 | /* |
104 | * This struct contains device specific data for the IOMMU | |
105 | */ | |
106 | struct iommu_dev_data { | |
107 | struct list_head list; /* For domain->dev_list */ | |
108 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 109 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 | 110 | u16 devid; /* PCI Device ID */ |
e3156048 | 111 | u16 alias; /* Alias Device ID */ |
50917e26 | 112 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
1e6a7b04 | 113 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
114 | struct { |
115 | bool enabled; | |
116 | int qdep; | |
117 | } ats; /* ATS state */ | |
118 | bool pri_tlp; /* PASID TLB required for | |
119 | PPR completions */ | |
120 | u32 errata; /* Bitmap for errata to apply */ | |
121 | }; | |
122 | ||
431b2a20 JR |
123 | /* |
124 | * general struct to manage commands send to an IOMMU | |
125 | */ | |
d6449536 | 126 | struct iommu_cmd { |
b6c02715 JR |
127 | u32 data[4]; |
128 | }; | |
129 | ||
05152a04 JR |
130 | struct kmem_cache *amd_iommu_irq_cache; |
131 | ||
04bfdd84 | 132 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 133 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 134 | static void detach_device(struct device *dev); |
c1eee67b | 135 | |
007b74ba JR |
136 | /* |
137 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
138 | * DMA address space each. This struct represents one such range. | |
139 | */ | |
140 | struct aperture_range { | |
141 | ||
08c5fb93 JR |
142 | spinlock_t bitmap_lock; |
143 | ||
007b74ba JR |
144 | /* address allocation bitmap */ |
145 | unsigned long *bitmap; | |
ae62d49c | 146 | unsigned long offset; |
60e6a7cb | 147 | unsigned long next_bit; |
007b74ba JR |
148 | |
149 | /* | |
150 | * Array of PTE pages for the aperture. In this array we save all the | |
151 | * leaf pages of the domain page table used for the aperture. This way | |
152 | * we don't need to walk the page table to find a specific PTE. We can | |
153 | * just calculate its address in constant time. | |
154 | */ | |
155 | u64 *pte_pages[64]; | |
007b74ba JR |
156 | }; |
157 | ||
158 | /* | |
159 | * Data container for a dma_ops specific protection domain | |
160 | */ | |
161 | struct dma_ops_domain { | |
162 | /* generic protection domain information */ | |
163 | struct protection_domain domain; | |
164 | ||
165 | /* size of the aperture for the mappings */ | |
166 | unsigned long aperture_size; | |
167 | ||
ebaecb42 | 168 | /* aperture index we start searching for free addresses */ |
5f6bed50 | 169 | u32 __percpu *next_index; |
007b74ba JR |
170 | |
171 | /* address space relevant data */ | |
172 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; | |
307d5851 JR |
173 | |
174 | /* IOVA RB-Tree */ | |
175 | struct iova_domain iovad; | |
007b74ba JR |
176 | }; |
177 | ||
81cd07b9 JR |
178 | static struct iova_domain reserved_iova_ranges; |
179 | static struct lock_class_key reserved_rbtree_key; | |
180 | ||
15898bbc JR |
181 | /**************************************************************************** |
182 | * | |
183 | * Helper functions | |
184 | * | |
185 | ****************************************************************************/ | |
186 | ||
2bf9a0a1 WZ |
187 | static inline int match_hid_uid(struct device *dev, |
188 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 189 | { |
2bf9a0a1 WZ |
190 | const char *hid, *uid; |
191 | ||
192 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
193 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
194 | ||
195 | if (!hid || !(*hid)) | |
196 | return -ENODEV; | |
197 | ||
198 | if (!uid || !(*uid)) | |
199 | return strcmp(hid, entry->hid); | |
200 | ||
201 | if (!(*entry->uid)) | |
202 | return strcmp(hid, entry->hid); | |
203 | ||
204 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
205 | } |
206 | ||
2bf9a0a1 | 207 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
208 | { |
209 | struct pci_dev *pdev = to_pci_dev(dev); | |
210 | ||
211 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
212 | } | |
213 | ||
2bf9a0a1 WZ |
214 | static inline int get_acpihid_device_id(struct device *dev, |
215 | struct acpihid_map_entry **entry) | |
216 | { | |
217 | struct acpihid_map_entry *p; | |
218 | ||
219 | list_for_each_entry(p, &acpihid_map, list) { | |
220 | if (!match_hid_uid(dev, p)) { | |
221 | if (entry) | |
222 | *entry = p; | |
223 | return p->devid; | |
224 | } | |
225 | } | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | static inline int get_device_id(struct device *dev) | |
230 | { | |
231 | int devid; | |
232 | ||
233 | if (dev_is_pci(dev)) | |
234 | devid = get_pci_device_id(dev); | |
235 | else | |
236 | devid = get_acpihid_device_id(dev, NULL); | |
237 | ||
238 | return devid; | |
239 | } | |
240 | ||
3f4b87b9 JR |
241 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
242 | { | |
243 | return container_of(dom, struct protection_domain, domain); | |
244 | } | |
245 | ||
f62dda66 | 246 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
247 | { |
248 | struct iommu_dev_data *dev_data; | |
249 | unsigned long flags; | |
250 | ||
251 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
252 | if (!dev_data) | |
253 | return NULL; | |
254 | ||
f62dda66 | 255 | dev_data->devid = devid; |
8fa5f802 JR |
256 | |
257 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
258 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
259 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
260 | ||
261 | return dev_data; | |
262 | } | |
263 | ||
3b03bb74 JR |
264 | static struct iommu_dev_data *search_dev_data(u16 devid) |
265 | { | |
266 | struct iommu_dev_data *dev_data; | |
267 | unsigned long flags; | |
268 | ||
269 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
270 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
271 | if (dev_data->devid == devid) | |
272 | goto out_unlock; | |
273 | } | |
274 | ||
275 | dev_data = NULL; | |
276 | ||
277 | out_unlock: | |
278 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
279 | ||
280 | return dev_data; | |
281 | } | |
282 | ||
e3156048 JR |
283 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
284 | { | |
285 | *(u16 *)data = alias; | |
286 | return 0; | |
287 | } | |
288 | ||
289 | static u16 get_alias(struct device *dev) | |
290 | { | |
291 | struct pci_dev *pdev = to_pci_dev(dev); | |
292 | u16 devid, ivrs_alias, pci_alias; | |
293 | ||
6c0b43df | 294 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 JR |
295 | devid = get_device_id(dev); |
296 | ivrs_alias = amd_iommu_alias_table[devid]; | |
297 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
298 | ||
299 | if (ivrs_alias == pci_alias) | |
300 | return ivrs_alias; | |
301 | ||
302 | /* | |
303 | * DMA alias showdown | |
304 | * | |
305 | * The IVRS is fairly reliable in telling us about aliases, but it | |
306 | * can't know about every screwy device. If we don't have an IVRS | |
307 | * reported alias, use the PCI reported alias. In that case we may | |
308 | * still need to initialize the rlookup and dev_table entries if the | |
309 | * alias is to a non-existent device. | |
310 | */ | |
311 | if (ivrs_alias == devid) { | |
312 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
313 | amd_iommu_rlookup_table[pci_alias] = | |
314 | amd_iommu_rlookup_table[devid]; | |
315 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
316 | amd_iommu_dev_table[devid].data, | |
317 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
318 | } | |
319 | ||
320 | return pci_alias; | |
321 | } | |
322 | ||
323 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
324 | "for device %s[%04x:%04x], kernel reported alias " | |
325 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
326 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
327 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
328 | PCI_FUNC(pci_alias)); | |
329 | ||
330 | /* | |
331 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
332 | * bus, then the IVRS table may know about a quirk that we don't. | |
333 | */ | |
334 | if (pci_alias == devid && | |
335 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 336 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
337 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
338 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
339 | dev_name(dev)); | |
340 | } | |
341 | ||
342 | return ivrs_alias; | |
343 | } | |
344 | ||
3b03bb74 JR |
345 | static struct iommu_dev_data *find_dev_data(u16 devid) |
346 | { | |
347 | struct iommu_dev_data *dev_data; | |
348 | ||
349 | dev_data = search_dev_data(devid); | |
350 | ||
351 | if (dev_data == NULL) | |
352 | dev_data = alloc_dev_data(devid); | |
353 | ||
354 | return dev_data; | |
355 | } | |
356 | ||
657cbb6b JR |
357 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
358 | { | |
359 | return dev->archdata.iommu; | |
360 | } | |
361 | ||
b097d11a WZ |
362 | /* |
363 | * Find or create an IOMMU group for a acpihid device. | |
364 | */ | |
365 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 366 | { |
b097d11a | 367 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 368 | int devid; |
b097d11a WZ |
369 | |
370 | devid = get_acpihid_device_id(dev, &entry); | |
371 | if (devid < 0) | |
372 | return ERR_PTR(devid); | |
373 | ||
374 | list_for_each_entry(p, &acpihid_map, list) { | |
375 | if ((devid == p->devid) && p->group) | |
376 | entry->group = p->group; | |
377 | } | |
378 | ||
379 | if (!entry->group) | |
380 | entry->group = generic_device_group(dev); | |
381 | ||
382 | return entry->group; | |
657cbb6b JR |
383 | } |
384 | ||
5abcdba4 JR |
385 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
386 | { | |
387 | static const int caps[] = { | |
388 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
389 | PCI_EXT_CAP_ID_PRI, |
390 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
391 | }; |
392 | int i, pos; | |
393 | ||
394 | for (i = 0; i < 3; ++i) { | |
395 | pos = pci_find_ext_capability(pdev, caps[i]); | |
396 | if (pos == 0) | |
397 | return false; | |
398 | } | |
399 | ||
400 | return true; | |
401 | } | |
402 | ||
6a113ddc JR |
403 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
404 | { | |
405 | struct iommu_dev_data *dev_data; | |
406 | ||
407 | dev_data = get_dev_data(&pdev->dev); | |
408 | ||
409 | return dev_data->errata & (1 << erratum) ? true : false; | |
410 | } | |
411 | ||
71c70984 | 412 | /* |
0bb6e243 JR |
413 | * This function actually applies the mapping to the page table of the |
414 | * dma_ops domain. | |
71c70984 | 415 | */ |
0bb6e243 JR |
416 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
417 | struct unity_map_entry *e) | |
71c70984 | 418 | { |
0bb6e243 | 419 | u64 addr; |
71c70984 | 420 | |
0bb6e243 JR |
421 | for (addr = e->address_start; addr < e->address_end; |
422 | addr += PAGE_SIZE) { | |
423 | if (addr < dma_dom->aperture_size) | |
424 | __set_bit(addr >> PAGE_SHIFT, | |
425 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 426 | } |
0bb6e243 | 427 | } |
71c70984 | 428 | |
0bb6e243 JR |
429 | /* |
430 | * Inits the unity mappings required for a specific device | |
431 | */ | |
432 | static void init_unity_mappings_for_device(struct device *dev, | |
433 | struct dma_ops_domain *dma_dom) | |
434 | { | |
435 | struct unity_map_entry *e; | |
7aba6cb9 | 436 | int devid; |
71c70984 | 437 | |
0bb6e243 | 438 | devid = get_device_id(dev); |
9ee35e4c | 439 | if (devid < 0) |
7aba6cb9 | 440 | return; |
71c70984 | 441 | |
0bb6e243 JR |
442 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
443 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
444 | continue; | |
445 | alloc_unity_mapping(dma_dom, e); | |
446 | } | |
71c70984 JR |
447 | } |
448 | ||
98fc5a69 JR |
449 | /* |
450 | * This function checks if the driver got a valid device from the caller to | |
451 | * avoid dereferencing invalid pointers. | |
452 | */ | |
453 | static bool check_device(struct device *dev) | |
454 | { | |
7aba6cb9 | 455 | int devid; |
98fc5a69 JR |
456 | |
457 | if (!dev || !dev->dma_mask) | |
458 | return false; | |
459 | ||
98fc5a69 | 460 | devid = get_device_id(dev); |
9ee35e4c | 461 | if (devid < 0) |
7aba6cb9 | 462 | return false; |
98fc5a69 JR |
463 | |
464 | /* Out of our scope? */ | |
465 | if (devid > amd_iommu_last_bdf) | |
466 | return false; | |
467 | ||
468 | if (amd_iommu_rlookup_table[devid] == NULL) | |
469 | return false; | |
470 | ||
471 | return true; | |
472 | } | |
473 | ||
25b11ce2 | 474 | static void init_iommu_group(struct device *dev) |
2851db21 | 475 | { |
0bb6e243 JR |
476 | struct dma_ops_domain *dma_domain; |
477 | struct iommu_domain *domain; | |
2851db21 | 478 | struct iommu_group *group; |
2851db21 | 479 | |
65d5352f | 480 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
481 | if (IS_ERR(group)) |
482 | return; | |
483 | ||
484 | domain = iommu_group_default_domain(group); | |
485 | if (!domain) | |
486 | goto out; | |
487 | ||
b548e786 JR |
488 | if (to_pdomain(domain)->flags == PD_DMA_OPS_MASK) { |
489 | dma_domain = to_pdomain(domain)->priv; | |
490 | init_unity_mappings_for_device(dev, dma_domain); | |
491 | } | |
0bb6e243 | 492 | |
0bb6e243 JR |
493 | out: |
494 | iommu_group_put(group); | |
eb9c9527 AW |
495 | } |
496 | ||
497 | static int iommu_init_device(struct device *dev) | |
498 | { | |
eb9c9527 | 499 | struct iommu_dev_data *dev_data; |
7aba6cb9 | 500 | int devid; |
eb9c9527 AW |
501 | |
502 | if (dev->archdata.iommu) | |
503 | return 0; | |
504 | ||
7aba6cb9 | 505 | devid = get_device_id(dev); |
9ee35e4c | 506 | if (devid < 0) |
7aba6cb9 WZ |
507 | return devid; |
508 | ||
509 | dev_data = find_dev_data(devid); | |
eb9c9527 AW |
510 | if (!dev_data) |
511 | return -ENOMEM; | |
512 | ||
e3156048 JR |
513 | dev_data->alias = get_alias(dev); |
514 | ||
2bf9a0a1 | 515 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
516 | struct amd_iommu *iommu; |
517 | ||
2bf9a0a1 | 518 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
519 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
520 | } | |
521 | ||
657cbb6b JR |
522 | dev->archdata.iommu = dev_data; |
523 | ||
066f2e98 AW |
524 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
525 | dev); | |
526 | ||
657cbb6b JR |
527 | return 0; |
528 | } | |
529 | ||
26018874 JR |
530 | static void iommu_ignore_device(struct device *dev) |
531 | { | |
7aba6cb9 WZ |
532 | u16 alias; |
533 | int devid; | |
26018874 JR |
534 | |
535 | devid = get_device_id(dev); | |
9ee35e4c | 536 | if (devid < 0) |
7aba6cb9 WZ |
537 | return; |
538 | ||
e3156048 | 539 | alias = get_alias(dev); |
26018874 JR |
540 | |
541 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
542 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
543 | ||
544 | amd_iommu_rlookup_table[devid] = NULL; | |
545 | amd_iommu_rlookup_table[alias] = NULL; | |
546 | } | |
547 | ||
657cbb6b JR |
548 | static void iommu_uninit_device(struct device *dev) |
549 | { | |
7aba6cb9 WZ |
550 | int devid; |
551 | struct iommu_dev_data *dev_data; | |
c1931090 | 552 | |
7aba6cb9 | 553 | devid = get_device_id(dev); |
9ee35e4c | 554 | if (devid < 0) |
7aba6cb9 | 555 | return; |
c1931090 | 556 | |
7aba6cb9 | 557 | dev_data = search_dev_data(devid); |
c1931090 AW |
558 | if (!dev_data) |
559 | return; | |
560 | ||
b6809ee5 JR |
561 | if (dev_data->domain) |
562 | detach_device(dev); | |
563 | ||
066f2e98 AW |
564 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
565 | dev); | |
566 | ||
9dcd6130 AW |
567 | iommu_group_remove_device(dev); |
568 | ||
aafd8ba0 JR |
569 | /* Remove dma-ops */ |
570 | dev->archdata.dma_ops = NULL; | |
571 | ||
8fa5f802 | 572 | /* |
c1931090 AW |
573 | * We keep dev_data around for unplugged devices and reuse it when the |
574 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 575 | */ |
657cbb6b | 576 | } |
b7cc9554 | 577 | |
a80dc3e0 JR |
578 | /**************************************************************************** |
579 | * | |
580 | * Interrupt handling functions | |
581 | * | |
582 | ****************************************************************************/ | |
583 | ||
e3e59876 JR |
584 | static void dump_dte_entry(u16 devid) |
585 | { | |
586 | int i; | |
587 | ||
ee6c2868 JR |
588 | for (i = 0; i < 4; ++i) |
589 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
590 | amd_iommu_dev_table[devid].data[i]); |
591 | } | |
592 | ||
945b4ac4 JR |
593 | static void dump_command(unsigned long phys_addr) |
594 | { | |
595 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
596 | int i; | |
597 | ||
598 | for (i = 0; i < 4; ++i) | |
599 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
600 | } | |
601 | ||
a345b23b | 602 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 603 | { |
3d06fca8 JR |
604 | int type, devid, domid, flags; |
605 | volatile u32 *event = __evt; | |
606 | int count = 0; | |
607 | u64 address; | |
608 | ||
609 | retry: | |
610 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
611 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
612 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
613 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
614 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
615 | ||
616 | if (type == 0) { | |
617 | /* Did we hit the erratum? */ | |
618 | if (++count == LOOP_TIMEOUT) { | |
619 | pr_err("AMD-Vi: No event written to event log\n"); | |
620 | return; | |
621 | } | |
622 | udelay(1); | |
623 | goto retry; | |
624 | } | |
90008ee4 | 625 | |
4c6f40d4 | 626 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
627 | |
628 | switch (type) { | |
629 | case EVENT_TYPE_ILL_DEV: | |
630 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
631 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 632 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 633 | address, flags); |
e3e59876 | 634 | dump_dte_entry(devid); |
90008ee4 JR |
635 | break; |
636 | case EVENT_TYPE_IO_FAULT: | |
637 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
638 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 639 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
640 | domid, address, flags); |
641 | break; | |
642 | case EVENT_TYPE_DEV_TAB_ERR: | |
643 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
644 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 645 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
646 | address, flags); |
647 | break; | |
648 | case EVENT_TYPE_PAGE_TAB_ERR: | |
649 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
650 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 651 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
652 | domid, address, flags); |
653 | break; | |
654 | case EVENT_TYPE_ILL_CMD: | |
655 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 656 | dump_command(address); |
90008ee4 JR |
657 | break; |
658 | case EVENT_TYPE_CMD_HARD_ERR: | |
659 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
660 | "flags=0x%04x]\n", address, flags); | |
661 | break; | |
662 | case EVENT_TYPE_IOTLB_INV_TO: | |
663 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
664 | "address=0x%016llx]\n", | |
c5081cd7 | 665 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
666 | address); |
667 | break; | |
668 | case EVENT_TYPE_INV_DEV_REQ: | |
669 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
670 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 671 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
672 | address, flags); |
673 | break; | |
674 | default: | |
675 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
676 | } | |
3d06fca8 JR |
677 | |
678 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
679 | } |
680 | ||
681 | static void iommu_poll_events(struct amd_iommu *iommu) | |
682 | { | |
683 | u32 head, tail; | |
90008ee4 JR |
684 | |
685 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
686 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
687 | ||
688 | while (head != tail) { | |
a345b23b | 689 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 690 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
691 | } |
692 | ||
693 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
694 | } |
695 | ||
eee53537 | 696 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
697 | { |
698 | struct amd_iommu_fault fault; | |
72e1dcc4 | 699 | |
72e1dcc4 JR |
700 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
701 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
702 | return; | |
703 | } | |
704 | ||
705 | fault.address = raw[1]; | |
706 | fault.pasid = PPR_PASID(raw[0]); | |
707 | fault.device_id = PPR_DEVID(raw[0]); | |
708 | fault.tag = PPR_TAG(raw[0]); | |
709 | fault.flags = PPR_FLAGS(raw[0]); | |
710 | ||
72e1dcc4 JR |
711 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
712 | } | |
713 | ||
714 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
715 | { | |
72e1dcc4 JR |
716 | u32 head, tail; |
717 | ||
718 | if (iommu->ppr_log == NULL) | |
719 | return; | |
720 | ||
72e1dcc4 JR |
721 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
722 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
723 | ||
724 | while (head != tail) { | |
eee53537 JR |
725 | volatile u64 *raw; |
726 | u64 entry[2]; | |
727 | int i; | |
728 | ||
729 | raw = (u64 *)(iommu->ppr_log + head); | |
730 | ||
731 | /* | |
732 | * Hardware bug: Interrupt may arrive before the entry is | |
733 | * written to memory. If this happens we need to wait for the | |
734 | * entry to arrive. | |
735 | */ | |
736 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
737 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
738 | break; | |
739 | udelay(1); | |
740 | } | |
72e1dcc4 | 741 | |
eee53537 JR |
742 | /* Avoid memcpy function-call overhead */ |
743 | entry[0] = raw[0]; | |
744 | entry[1] = raw[1]; | |
72e1dcc4 | 745 | |
eee53537 JR |
746 | /* |
747 | * To detect the hardware bug we need to clear the entry | |
748 | * back to zero. | |
749 | */ | |
750 | raw[0] = raw[1] = 0UL; | |
751 | ||
752 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
753 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
754 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 755 | |
eee53537 JR |
756 | /* Handle PPR entry */ |
757 | iommu_handle_ppr_entry(iommu, entry); | |
758 | ||
eee53537 JR |
759 | /* Refresh ring-buffer information */ |
760 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
761 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
762 | } | |
72e1dcc4 JR |
763 | } |
764 | ||
72fe00f0 | 765 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 766 | { |
3f398bc7 SS |
767 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
768 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 769 | |
3f398bc7 SS |
770 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
771 | /* Enable EVT and PPR interrupts again */ | |
772 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
773 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 774 | |
3f398bc7 SS |
775 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
776 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
777 | iommu_poll_events(iommu); | |
778 | } | |
90008ee4 | 779 | |
3f398bc7 SS |
780 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
781 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
782 | iommu_poll_ppr_log(iommu); | |
783 | } | |
90008ee4 | 784 | |
3f398bc7 SS |
785 | /* |
786 | * Hardware bug: ERBT1312 | |
787 | * When re-enabling interrupt (by writing 1 | |
788 | * to clear the bit), the hardware might also try to set | |
789 | * the interrupt bit in the event status register. | |
790 | * In this scenario, the bit will be set, and disable | |
791 | * subsequent interrupts. | |
792 | * | |
793 | * Workaround: The IOMMU driver should read back the | |
794 | * status register and check if the interrupt bits are cleared. | |
795 | * If not, driver will need to go through the interrupt handler | |
796 | * again and re-clear the bits | |
797 | */ | |
798 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
799 | } | |
90008ee4 | 800 | return IRQ_HANDLED; |
a80dc3e0 JR |
801 | } |
802 | ||
72fe00f0 JR |
803 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
804 | { | |
805 | return IRQ_WAKE_THREAD; | |
806 | } | |
807 | ||
431b2a20 JR |
808 | /**************************************************************************** |
809 | * | |
810 | * IOMMU command queuing functions | |
811 | * | |
812 | ****************************************************************************/ | |
813 | ||
ac0ea6e9 JR |
814 | static int wait_on_sem(volatile u64 *sem) |
815 | { | |
816 | int i = 0; | |
817 | ||
818 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
819 | udelay(1); | |
820 | i += 1; | |
821 | } | |
822 | ||
823 | if (i == LOOP_TIMEOUT) { | |
824 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
825 | return -EIO; | |
826 | } | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
832 | struct iommu_cmd *cmd, | |
833 | u32 tail) | |
a19ae1ec | 834 | { |
a19ae1ec JR |
835 | u8 *target; |
836 | ||
8a7c5ef3 | 837 | target = iommu->cmd_buf + tail; |
deba4bce | 838 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
839 | |
840 | /* Copy command to buffer */ | |
841 | memcpy(target, cmd, sizeof(*cmd)); | |
842 | ||
843 | /* Tell the IOMMU about it */ | |
a19ae1ec | 844 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 845 | } |
a19ae1ec | 846 | |
815b33fd | 847 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 848 | { |
815b33fd JR |
849 | WARN_ON(address & 0x7ULL); |
850 | ||
ded46737 | 851 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
852 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
853 | cmd->data[1] = upper_32_bits(__pa(address)); | |
854 | cmd->data[2] = 1; | |
ded46737 JR |
855 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
856 | } | |
857 | ||
94fe79e2 JR |
858 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
859 | { | |
860 | memset(cmd, 0, sizeof(*cmd)); | |
861 | cmd->data[0] = devid; | |
862 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
863 | } | |
864 | ||
11b6402c JR |
865 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
866 | size_t size, u16 domid, int pde) | |
867 | { | |
868 | u64 pages; | |
ae0cbbb1 | 869 | bool s; |
11b6402c JR |
870 | |
871 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 872 | s = false; |
11b6402c JR |
873 | |
874 | if (pages > 1) { | |
875 | /* | |
876 | * If we have to flush more than one page, flush all | |
877 | * TLB entries for this domain | |
878 | */ | |
879 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 880 | s = true; |
11b6402c JR |
881 | } |
882 | ||
883 | address &= PAGE_MASK; | |
884 | ||
885 | memset(cmd, 0, sizeof(*cmd)); | |
886 | cmd->data[1] |= domid; | |
887 | cmd->data[2] = lower_32_bits(address); | |
888 | cmd->data[3] = upper_32_bits(address); | |
889 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
890 | if (s) /* size bit - we flush more than one 4kb page */ | |
891 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 892 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
893 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
894 | } | |
895 | ||
cb41ed85 JR |
896 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
897 | u64 address, size_t size) | |
898 | { | |
899 | u64 pages; | |
ae0cbbb1 | 900 | bool s; |
cb41ed85 JR |
901 | |
902 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 903 | s = false; |
cb41ed85 JR |
904 | |
905 | if (pages > 1) { | |
906 | /* | |
907 | * If we have to flush more than one page, flush all | |
908 | * TLB entries for this domain | |
909 | */ | |
910 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 911 | s = true; |
cb41ed85 JR |
912 | } |
913 | ||
914 | address &= PAGE_MASK; | |
915 | ||
916 | memset(cmd, 0, sizeof(*cmd)); | |
917 | cmd->data[0] = devid; | |
918 | cmd->data[0] |= (qdep & 0xff) << 24; | |
919 | cmd->data[1] = devid; | |
920 | cmd->data[2] = lower_32_bits(address); | |
921 | cmd->data[3] = upper_32_bits(address); | |
922 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
923 | if (s) | |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
925 | } | |
926 | ||
22e266c7 JR |
927 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
928 | u64 address, bool size) | |
929 | { | |
930 | memset(cmd, 0, sizeof(*cmd)); | |
931 | ||
932 | address &= ~(0xfffULL); | |
933 | ||
a919a018 | 934 | cmd->data[0] = pasid; |
22e266c7 JR |
935 | cmd->data[1] = domid; |
936 | cmd->data[2] = lower_32_bits(address); | |
937 | cmd->data[3] = upper_32_bits(address); | |
938 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
939 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
940 | if (size) | |
941 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
942 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
943 | } | |
944 | ||
945 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
946 | int qdep, u64 address, bool size) | |
947 | { | |
948 | memset(cmd, 0, sizeof(*cmd)); | |
949 | ||
950 | address &= ~(0xfffULL); | |
951 | ||
952 | cmd->data[0] = devid; | |
e8d2d82d | 953 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
954 | cmd->data[0] |= (qdep & 0xff) << 24; |
955 | cmd->data[1] = devid; | |
e8d2d82d | 956 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
957 | cmd->data[2] = lower_32_bits(address); |
958 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
959 | cmd->data[3] = upper_32_bits(address); | |
960 | if (size) | |
961 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
962 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
963 | } | |
964 | ||
c99afa25 JR |
965 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
966 | int status, int tag, bool gn) | |
967 | { | |
968 | memset(cmd, 0, sizeof(*cmd)); | |
969 | ||
970 | cmd->data[0] = devid; | |
971 | if (gn) { | |
a919a018 | 972 | cmd->data[1] = pasid; |
c99afa25 JR |
973 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
974 | } | |
975 | cmd->data[3] = tag & 0x1ff; | |
976 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
977 | ||
978 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
979 | } | |
980 | ||
58fc7f14 JR |
981 | static void build_inv_all(struct iommu_cmd *cmd) |
982 | { | |
983 | memset(cmd, 0, sizeof(*cmd)); | |
984 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
985 | } |
986 | ||
7ef2798d JR |
987 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
988 | { | |
989 | memset(cmd, 0, sizeof(*cmd)); | |
990 | cmd->data[0] = devid; | |
991 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
992 | } | |
993 | ||
431b2a20 | 994 | /* |
431b2a20 | 995 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 996 | * hardware about the new command. |
431b2a20 | 997 | */ |
f1ca1512 JR |
998 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
999 | struct iommu_cmd *cmd, | |
1000 | bool sync) | |
a19ae1ec | 1001 | { |
ac0ea6e9 | 1002 | u32 left, tail, head, next_tail; |
a19ae1ec | 1003 | unsigned long flags; |
a19ae1ec | 1004 | |
ac0ea6e9 | 1005 | again: |
a19ae1ec | 1006 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 1007 | |
ac0ea6e9 JR |
1008 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
1009 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
1010 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
1011 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 1012 | |
ac0ea6e9 JR |
1013 | if (left <= 2) { |
1014 | struct iommu_cmd sync_cmd; | |
1015 | volatile u64 sem = 0; | |
1016 | int ret; | |
8d201968 | 1017 | |
ac0ea6e9 JR |
1018 | build_completion_wait(&sync_cmd, (u64)&sem); |
1019 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1020 | |
ac0ea6e9 JR |
1021 | spin_unlock_irqrestore(&iommu->lock, flags); |
1022 | ||
1023 | if ((ret = wait_on_sem(&sem)) != 0) | |
1024 | return ret; | |
1025 | ||
1026 | goto again; | |
8d201968 JR |
1027 | } |
1028 | ||
ac0ea6e9 JR |
1029 | copy_cmd_to_buffer(iommu, cmd, tail); |
1030 | ||
1031 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1032 | iommu->need_sync = sync; |
ac0ea6e9 | 1033 | |
a19ae1ec | 1034 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1035 | |
815b33fd | 1036 | return 0; |
8d201968 JR |
1037 | } |
1038 | ||
f1ca1512 JR |
1039 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1040 | { | |
1041 | return iommu_queue_command_sync(iommu, cmd, true); | |
1042 | } | |
1043 | ||
8d201968 JR |
1044 | /* |
1045 | * This function queues a completion wait command into the command | |
1046 | * buffer of an IOMMU | |
1047 | */ | |
a19ae1ec | 1048 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1049 | { |
1050 | struct iommu_cmd cmd; | |
815b33fd | 1051 | volatile u64 sem = 0; |
ac0ea6e9 | 1052 | int ret; |
8d201968 | 1053 | |
09ee17eb | 1054 | if (!iommu->need_sync) |
815b33fd | 1055 | return 0; |
09ee17eb | 1056 | |
815b33fd | 1057 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1058 | |
f1ca1512 | 1059 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1060 | if (ret) |
815b33fd | 1061 | return ret; |
8d201968 | 1062 | |
ac0ea6e9 | 1063 | return wait_on_sem(&sem); |
8d201968 JR |
1064 | } |
1065 | ||
d8c13085 | 1066 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1067 | { |
d8c13085 | 1068 | struct iommu_cmd cmd; |
a19ae1ec | 1069 | |
d8c13085 | 1070 | build_inv_dte(&cmd, devid); |
7e4f88da | 1071 | |
d8c13085 JR |
1072 | return iommu_queue_command(iommu, &cmd); |
1073 | } | |
09ee17eb | 1074 | |
7d0c5cc5 JR |
1075 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1076 | { | |
1077 | u32 devid; | |
09ee17eb | 1078 | |
7d0c5cc5 JR |
1079 | for (devid = 0; devid <= 0xffff; ++devid) |
1080 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1081 | |
7d0c5cc5 JR |
1082 | iommu_completion_wait(iommu); |
1083 | } | |
84df8175 | 1084 | |
7d0c5cc5 JR |
1085 | /* |
1086 | * This function uses heavy locking and may disable irqs for some time. But | |
1087 | * this is no issue because it is only called during resume. | |
1088 | */ | |
1089 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1090 | { | |
1091 | u32 dom_id; | |
a19ae1ec | 1092 | |
7d0c5cc5 JR |
1093 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1094 | struct iommu_cmd cmd; | |
1095 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1096 | dom_id, 1); | |
1097 | iommu_queue_command(iommu, &cmd); | |
1098 | } | |
8eed9833 | 1099 | |
7d0c5cc5 | 1100 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1101 | } |
1102 | ||
58fc7f14 | 1103 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1104 | { |
58fc7f14 | 1105 | struct iommu_cmd cmd; |
0518a3a4 | 1106 | |
58fc7f14 | 1107 | build_inv_all(&cmd); |
0518a3a4 | 1108 | |
58fc7f14 JR |
1109 | iommu_queue_command(iommu, &cmd); |
1110 | iommu_completion_wait(iommu); | |
1111 | } | |
1112 | ||
7ef2798d JR |
1113 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1114 | { | |
1115 | struct iommu_cmd cmd; | |
1116 | ||
1117 | build_inv_irt(&cmd, devid); | |
1118 | ||
1119 | iommu_queue_command(iommu, &cmd); | |
1120 | } | |
1121 | ||
1122 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1123 | { | |
1124 | u32 devid; | |
1125 | ||
1126 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1127 | iommu_flush_irt(iommu, devid); | |
1128 | ||
1129 | iommu_completion_wait(iommu); | |
1130 | } | |
1131 | ||
7d0c5cc5 JR |
1132 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1133 | { | |
58fc7f14 JR |
1134 | if (iommu_feature(iommu, FEATURE_IA)) { |
1135 | iommu_flush_all(iommu); | |
1136 | } else { | |
1137 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1138 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1139 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1140 | } |
1141 | } | |
1142 | ||
431b2a20 | 1143 | /* |
cb41ed85 | 1144 | * Command send function for flushing on-device TLB |
431b2a20 | 1145 | */ |
6c542047 JR |
1146 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1147 | u64 address, size_t size) | |
3fa43655 JR |
1148 | { |
1149 | struct amd_iommu *iommu; | |
b00d3bcf | 1150 | struct iommu_cmd cmd; |
cb41ed85 | 1151 | int qdep; |
3fa43655 | 1152 | |
ea61cddb JR |
1153 | qdep = dev_data->ats.qdep; |
1154 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1155 | |
ea61cddb | 1156 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1157 | |
1158 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1159 | } |
1160 | ||
431b2a20 | 1161 | /* |
431b2a20 | 1162 | * Command send function for invalidating a device table entry |
431b2a20 | 1163 | */ |
6c542047 | 1164 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1165 | { |
3fa43655 | 1166 | struct amd_iommu *iommu; |
e25bfb56 | 1167 | u16 alias; |
ee2fa743 | 1168 | int ret; |
a19ae1ec | 1169 | |
6c542047 | 1170 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1171 | alias = dev_data->alias; |
a19ae1ec | 1172 | |
f62dda66 | 1173 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1174 | if (!ret && alias != dev_data->devid) |
1175 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1176 | if (ret) |
1177 | return ret; | |
1178 | ||
ea61cddb | 1179 | if (dev_data->ats.enabled) |
6c542047 | 1180 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1181 | |
ee2fa743 | 1182 | return ret; |
a19ae1ec JR |
1183 | } |
1184 | ||
431b2a20 JR |
1185 | /* |
1186 | * TLB invalidation function which is called from the mapping functions. | |
1187 | * It invalidates a single PTE if the range to flush is within a single | |
1188 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1189 | */ | |
17b124bf JR |
1190 | static void __domain_flush_pages(struct protection_domain *domain, |
1191 | u64 address, size_t size, int pde) | |
a19ae1ec | 1192 | { |
cb41ed85 | 1193 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1194 | struct iommu_cmd cmd; |
1195 | int ret = 0, i; | |
a19ae1ec | 1196 | |
11b6402c | 1197 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1198 | |
6de8ad9b JR |
1199 | for (i = 0; i < amd_iommus_present; ++i) { |
1200 | if (!domain->dev_iommu[i]) | |
1201 | continue; | |
1202 | ||
1203 | /* | |
1204 | * Devices of this domain are behind this IOMMU | |
1205 | * We need a TLB flush | |
1206 | */ | |
11b6402c | 1207 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1208 | } |
1209 | ||
cb41ed85 | 1210 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1211 | |
ea61cddb | 1212 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1213 | continue; |
1214 | ||
6c542047 | 1215 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1216 | } |
1217 | ||
11b6402c | 1218 | WARN_ON(ret); |
6de8ad9b JR |
1219 | } |
1220 | ||
17b124bf JR |
1221 | static void domain_flush_pages(struct protection_domain *domain, |
1222 | u64 address, size_t size) | |
6de8ad9b | 1223 | { |
17b124bf | 1224 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1225 | } |
b6c02715 | 1226 | |
1c655773 | 1227 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1228 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1229 | { |
17b124bf | 1230 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1231 | } |
1232 | ||
42a49f96 | 1233 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1234 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1235 | { |
17b124bf | 1236 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1237 | } |
1238 | ||
17b124bf | 1239 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1240 | { |
17b124bf | 1241 | int i; |
18811f55 | 1242 | |
17b124bf JR |
1243 | for (i = 0; i < amd_iommus_present; ++i) { |
1244 | if (!domain->dev_iommu[i]) | |
1245 | continue; | |
bfd1be18 | 1246 | |
17b124bf JR |
1247 | /* |
1248 | * Devices of this domain are behind this IOMMU | |
1249 | * We need to wait for completion of all commands. | |
1250 | */ | |
1251 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1252 | } |
e394d72a JR |
1253 | } |
1254 | ||
b00d3bcf | 1255 | |
09b42804 | 1256 | /* |
b00d3bcf | 1257 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1258 | */ |
17b124bf | 1259 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1260 | { |
b00d3bcf | 1261 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1262 | |
b00d3bcf | 1263 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1264 | device_flush_dte(dev_data); |
a345b23b JR |
1265 | } |
1266 | ||
431b2a20 JR |
1267 | /**************************************************************************** |
1268 | * | |
1269 | * The functions below are used the create the page table mappings for | |
1270 | * unity mapped regions. | |
1271 | * | |
1272 | ****************************************************************************/ | |
1273 | ||
308973d3 JR |
1274 | /* |
1275 | * This function is used to add another level to an IO page table. Adding | |
1276 | * another level increases the size of the address space by 9 bits to a size up | |
1277 | * to 64 bits. | |
1278 | */ | |
1279 | static bool increase_address_space(struct protection_domain *domain, | |
1280 | gfp_t gfp) | |
1281 | { | |
1282 | u64 *pte; | |
1283 | ||
1284 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1285 | /* address space already 64 bit large */ | |
1286 | return false; | |
1287 | ||
1288 | pte = (void *)get_zeroed_page(gfp); | |
1289 | if (!pte) | |
1290 | return false; | |
1291 | ||
1292 | *pte = PM_LEVEL_PDE(domain->mode, | |
1293 | virt_to_phys(domain->pt_root)); | |
1294 | domain->pt_root = pte; | |
1295 | domain->mode += 1; | |
1296 | domain->updated = true; | |
1297 | ||
1298 | return true; | |
1299 | } | |
1300 | ||
1301 | static u64 *alloc_pte(struct protection_domain *domain, | |
1302 | unsigned long address, | |
cbb9d729 | 1303 | unsigned long page_size, |
308973d3 JR |
1304 | u64 **pte_page, |
1305 | gfp_t gfp) | |
1306 | { | |
cbb9d729 | 1307 | int level, end_lvl; |
308973d3 | 1308 | u64 *pte, *page; |
cbb9d729 JR |
1309 | |
1310 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1311 | |
1312 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1313 | increase_address_space(domain, gfp); | |
1314 | ||
cbb9d729 JR |
1315 | level = domain->mode - 1; |
1316 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1317 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1318 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1319 | |
1320 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1321 | u64 __pte, __npte; |
1322 | ||
1323 | __pte = *pte; | |
1324 | ||
1325 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1326 | page = (u64 *)get_zeroed_page(gfp); |
1327 | if (!page) | |
1328 | return NULL; | |
7bfa5bd2 JR |
1329 | |
1330 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1331 | ||
1332 | if (cmpxchg64(pte, __pte, __npte)) { | |
1333 | free_page((unsigned long)page); | |
1334 | continue; | |
1335 | } | |
308973d3 JR |
1336 | } |
1337 | ||
cbb9d729 JR |
1338 | /* No level skipping support yet */ |
1339 | if (PM_PTE_LEVEL(*pte) != level) | |
1340 | return NULL; | |
1341 | ||
308973d3 JR |
1342 | level -= 1; |
1343 | ||
1344 | pte = IOMMU_PTE_PAGE(*pte); | |
1345 | ||
1346 | if (pte_page && level == end_lvl) | |
1347 | *pte_page = pte; | |
1348 | ||
1349 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1350 | } | |
1351 | ||
1352 | return pte; | |
1353 | } | |
1354 | ||
1355 | /* | |
1356 | * This function checks if there is a PTE for a given dma address. If | |
1357 | * there is one, it returns the pointer to it. | |
1358 | */ | |
3039ca1b JR |
1359 | static u64 *fetch_pte(struct protection_domain *domain, |
1360 | unsigned long address, | |
1361 | unsigned long *page_size) | |
308973d3 JR |
1362 | { |
1363 | int level; | |
1364 | u64 *pte; | |
1365 | ||
24cd7723 JR |
1366 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1367 | return NULL; | |
1368 | ||
3039ca1b JR |
1369 | level = domain->mode - 1; |
1370 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1371 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1372 | |
24cd7723 JR |
1373 | while (level > 0) { |
1374 | ||
1375 | /* Not Present */ | |
308973d3 JR |
1376 | if (!IOMMU_PTE_PRESENT(*pte)) |
1377 | return NULL; | |
1378 | ||
24cd7723 | 1379 | /* Large PTE */ |
3039ca1b JR |
1380 | if (PM_PTE_LEVEL(*pte) == 7 || |
1381 | PM_PTE_LEVEL(*pte) == 0) | |
1382 | break; | |
24cd7723 JR |
1383 | |
1384 | /* No level skipping support yet */ | |
1385 | if (PM_PTE_LEVEL(*pte) != level) | |
1386 | return NULL; | |
1387 | ||
308973d3 JR |
1388 | level -= 1; |
1389 | ||
24cd7723 | 1390 | /* Walk to the next level */ |
3039ca1b JR |
1391 | pte = IOMMU_PTE_PAGE(*pte); |
1392 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1393 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1394 | } | |
1395 | ||
1396 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1397 | unsigned long pte_mask; | |
1398 | ||
1399 | /* | |
1400 | * If we have a series of large PTEs, make | |
1401 | * sure to return a pointer to the first one. | |
1402 | */ | |
1403 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1404 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1405 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1406 | } |
1407 | ||
1408 | return pte; | |
1409 | } | |
1410 | ||
431b2a20 JR |
1411 | /* |
1412 | * Generic mapping functions. It maps a physical address into a DMA | |
1413 | * address space. It allocates the page table pages if necessary. | |
1414 | * In the future it can be extended to a generic mapping function | |
1415 | * supporting all features of AMD IOMMU page tables like level skipping | |
1416 | * and full 64 bit address spaces. | |
1417 | */ | |
38e817fe JR |
1418 | static int iommu_map_page(struct protection_domain *dom, |
1419 | unsigned long bus_addr, | |
1420 | unsigned long phys_addr, | |
b911b89b | 1421 | unsigned long page_size, |
abdc5eb3 | 1422 | int prot, |
b911b89b | 1423 | gfp_t gfp) |
bd0e5211 | 1424 | { |
8bda3092 | 1425 | u64 __pte, *pte; |
cbb9d729 | 1426 | int i, count; |
abdc5eb3 | 1427 | |
d4b03664 JR |
1428 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1429 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1430 | ||
bad1cac2 | 1431 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1432 | return -EINVAL; |
1433 | ||
d4b03664 | 1434 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1435 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1436 | |
63eaa75e ML |
1437 | if (!pte) |
1438 | return -ENOMEM; | |
1439 | ||
cbb9d729 JR |
1440 | for (i = 0; i < count; ++i) |
1441 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1442 | return -EBUSY; | |
bd0e5211 | 1443 | |
d4b03664 | 1444 | if (count > 1) { |
cbb9d729 JR |
1445 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1446 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1447 | } else | |
1448 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1449 | |
bd0e5211 JR |
1450 | if (prot & IOMMU_PROT_IR) |
1451 | __pte |= IOMMU_PTE_IR; | |
1452 | if (prot & IOMMU_PROT_IW) | |
1453 | __pte |= IOMMU_PTE_IW; | |
1454 | ||
cbb9d729 JR |
1455 | for (i = 0; i < count; ++i) |
1456 | pte[i] = __pte; | |
bd0e5211 | 1457 | |
04bfdd84 JR |
1458 | update_domain(dom); |
1459 | ||
bd0e5211 JR |
1460 | return 0; |
1461 | } | |
1462 | ||
24cd7723 JR |
1463 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1464 | unsigned long bus_addr, | |
1465 | unsigned long page_size) | |
eb74ff6c | 1466 | { |
71b390e9 JR |
1467 | unsigned long long unmapped; |
1468 | unsigned long unmap_size; | |
24cd7723 JR |
1469 | u64 *pte; |
1470 | ||
1471 | BUG_ON(!is_power_of_2(page_size)); | |
1472 | ||
1473 | unmapped = 0; | |
eb74ff6c | 1474 | |
24cd7723 JR |
1475 | while (unmapped < page_size) { |
1476 | ||
71b390e9 JR |
1477 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1478 | ||
1479 | if (pte) { | |
1480 | int i, count; | |
1481 | ||
1482 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1483 | for (i = 0; i < count; i++) |
1484 | pte[i] = 0ULL; | |
1485 | } | |
1486 | ||
1487 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1488 | unmapped += unmap_size; | |
1489 | } | |
1490 | ||
60d0ca3c | 1491 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1492 | |
24cd7723 | 1493 | return unmapped; |
eb74ff6c | 1494 | } |
eb74ff6c | 1495 | |
431b2a20 JR |
1496 | /**************************************************************************** |
1497 | * | |
1498 | * The next functions belong to the address allocator for the dma_ops | |
1499 | * interface functions. They work like the allocators in the other IOMMU | |
1500 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1501 | * the aperture. Maybe it could be enhanced in the future to a more | |
1502 | * efficient allocator. | |
1503 | * | |
1504 | ****************************************************************************/ | |
d3086444 | 1505 | |
431b2a20 | 1506 | /* |
384de729 | 1507 | * The address allocator core functions. |
431b2a20 JR |
1508 | * |
1509 | * called with domain->lock held | |
1510 | */ | |
384de729 | 1511 | |
171e7b37 JR |
1512 | /* |
1513 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1514 | * ranges. | |
1515 | */ | |
1516 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1517 | unsigned long start_page, | |
1518 | unsigned int pages) | |
1519 | { | |
1520 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1521 | ||
1522 | if (start_page + pages > last_page) | |
1523 | pages = last_page - start_page; | |
1524 | ||
1525 | for (i = start_page; i < start_page + pages; ++i) { | |
1526 | int index = i / APERTURE_RANGE_PAGES; | |
1527 | int page = i % APERTURE_RANGE_PAGES; | |
1528 | __set_bit(page, dom->aperture[index]->bitmap); | |
1529 | } | |
1530 | } | |
1531 | ||
9cabe89b JR |
1532 | /* |
1533 | * This function is used to add a new aperture range to an existing | |
1534 | * aperture in case of dma_ops domain allocation or address allocation | |
1535 | * failure. | |
1536 | */ | |
576175c2 | 1537 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1538 | bool populate, gfp_t gfp) |
1539 | { | |
1540 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
5d7c94c3 | 1541 | unsigned long i, old_size, pte_pgsize; |
a73c1566 JR |
1542 | struct aperture_range *range; |
1543 | struct amd_iommu *iommu; | |
1544 | unsigned long flags; | |
9cabe89b | 1545 | |
f5e9705c JR |
1546 | #ifdef CONFIG_IOMMU_STRESS |
1547 | populate = false; | |
1548 | #endif | |
1549 | ||
9cabe89b JR |
1550 | if (index >= APERTURE_MAX_RANGES) |
1551 | return -ENOMEM; | |
1552 | ||
a73c1566 JR |
1553 | range = kzalloc(sizeof(struct aperture_range), gfp); |
1554 | if (!range) | |
9cabe89b JR |
1555 | return -ENOMEM; |
1556 | ||
a73c1566 JR |
1557 | range->bitmap = (void *)get_zeroed_page(gfp); |
1558 | if (!range->bitmap) | |
9cabe89b JR |
1559 | goto out_free; |
1560 | ||
a73c1566 | 1561 | range->offset = dma_dom->aperture_size; |
9cabe89b | 1562 | |
a73c1566 | 1563 | spin_lock_init(&range->bitmap_lock); |
08c5fb93 | 1564 | |
9cabe89b JR |
1565 | if (populate) { |
1566 | unsigned long address = dma_dom->aperture_size; | |
1567 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1568 | u64 *pte, *pte_page; | |
1569 | ||
1570 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1571 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1572 | &pte_page, gfp); |
1573 | if (!pte) | |
1574 | goto out_free; | |
1575 | ||
a73c1566 | 1576 | range->pte_pages[i] = pte_page; |
9cabe89b JR |
1577 | |
1578 | address += APERTURE_RANGE_SIZE / 64; | |
1579 | } | |
1580 | } | |
1581 | ||
92d420ec JR |
1582 | spin_lock_irqsave(&dma_dom->domain.lock, flags); |
1583 | ||
a73c1566 | 1584 | /* First take the bitmap_lock and then publish the range */ |
92d420ec | 1585 | spin_lock(&range->bitmap_lock); |
a73c1566 JR |
1586 | |
1587 | old_size = dma_dom->aperture_size; | |
1588 | dma_dom->aperture[index] = range; | |
1589 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
9cabe89b | 1590 | |
17f5b569 JR |
1591 | /* Reserve address range used for MSI messages */ |
1592 | if (old_size < MSI_ADDR_BASE_LO && | |
1593 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1594 | unsigned long spage; | |
1595 | int pages; | |
1596 | ||
1597 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1598 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1599 | ||
1600 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1601 | } | |
1602 | ||
b595076a | 1603 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1604 | for_each_iommu(iommu) { |
1605 | if (iommu->exclusion_start && | |
1606 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1607 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1608 | unsigned long startpage; | |
1609 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1610 | iommu->exclusion_length, | |
1611 | PAGE_SIZE); | |
1612 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1613 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1614 | } | |
00cd122a JR |
1615 | } |
1616 | ||
1617 | /* | |
1618 | * Check for areas already mapped as present in the new aperture | |
1619 | * range and mark those pages as reserved in the allocator. Such | |
1620 | * mappings may already exist as a result of requested unity | |
1621 | * mappings for devices. | |
1622 | */ | |
1623 | for (i = dma_dom->aperture[index]->offset; | |
1624 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1625 | i += pte_pgsize) { |
3039ca1b | 1626 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1627 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1628 | continue; | |
1629 | ||
5d7c94c3 JR |
1630 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1631 | pte_pgsize >> 12); | |
00cd122a JR |
1632 | } |
1633 | ||
04bfdd84 JR |
1634 | update_domain(&dma_dom->domain); |
1635 | ||
92d420ec JR |
1636 | spin_unlock(&range->bitmap_lock); |
1637 | ||
1638 | spin_unlock_irqrestore(&dma_dom->domain.lock, flags); | |
a73c1566 | 1639 | |
9cabe89b JR |
1640 | return 0; |
1641 | ||
1642 | out_free: | |
04bfdd84 JR |
1643 | update_domain(&dma_dom->domain); |
1644 | ||
a73c1566 | 1645 | free_page((unsigned long)range->bitmap); |
9cabe89b | 1646 | |
a73c1566 | 1647 | kfree(range); |
9cabe89b JR |
1648 | |
1649 | return -ENOMEM; | |
1650 | } | |
1651 | ||
ccb50e03 JR |
1652 | static dma_addr_t dma_ops_aperture_alloc(struct dma_ops_domain *dom, |
1653 | struct aperture_range *range, | |
a0f51447 | 1654 | unsigned long pages, |
a0f51447 JR |
1655 | unsigned long dma_mask, |
1656 | unsigned long boundary_size, | |
7b5e25b8 JR |
1657 | unsigned long align_mask, |
1658 | bool trylock) | |
a0f51447 JR |
1659 | { |
1660 | unsigned long offset, limit, flags; | |
1661 | dma_addr_t address; | |
ccb50e03 | 1662 | bool flush = false; |
a0f51447 JR |
1663 | |
1664 | offset = range->offset >> PAGE_SHIFT; | |
1665 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1666 | dma_mask >> PAGE_SHIFT); | |
1667 | ||
7b5e25b8 JR |
1668 | if (trylock) { |
1669 | if (!spin_trylock_irqsave(&range->bitmap_lock, flags)) | |
1670 | return -1; | |
1671 | } else { | |
1672 | spin_lock_irqsave(&range->bitmap_lock, flags); | |
1673 | } | |
1674 | ||
60e6a7cb JR |
1675 | address = iommu_area_alloc(range->bitmap, limit, range->next_bit, |
1676 | pages, offset, boundary_size, align_mask); | |
ccb50e03 | 1677 | if (address == -1) { |
60e6a7cb JR |
1678 | /* Nothing found, retry one time */ |
1679 | address = iommu_area_alloc(range->bitmap, limit, | |
1680 | 0, pages, offset, boundary_size, | |
1681 | align_mask); | |
ccb50e03 JR |
1682 | flush = true; |
1683 | } | |
60e6a7cb JR |
1684 | |
1685 | if (address != -1) | |
1686 | range->next_bit = address + pages; | |
1687 | ||
a0f51447 JR |
1688 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
1689 | ||
ccb50e03 JR |
1690 | if (flush) { |
1691 | domain_flush_tlb(&dom->domain); | |
1692 | domain_flush_complete(&dom->domain); | |
1693 | } | |
1694 | ||
a0f51447 JR |
1695 | return address; |
1696 | } | |
1697 | ||
384de729 JR |
1698 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1699 | struct dma_ops_domain *dom, | |
1700 | unsigned int pages, | |
1701 | unsigned long align_mask, | |
05ab49e0 | 1702 | u64 dma_mask) |
384de729 | 1703 | { |
ab7032bb | 1704 | unsigned long boundary_size, mask; |
384de729 | 1705 | unsigned long address = -1; |
7b5e25b8 | 1706 | bool first = true; |
5f6bed50 JR |
1707 | u32 start, i; |
1708 | ||
1709 | preempt_disable(); | |
384de729 | 1710 | |
e6aabee0 JR |
1711 | mask = dma_get_seg_boundary(dev); |
1712 | ||
7b5e25b8 | 1713 | again: |
5f6bed50 JR |
1714 | start = this_cpu_read(*dom->next_index); |
1715 | ||
1716 | /* Sanity check - is it really necessary? */ | |
1717 | if (unlikely(start > APERTURE_MAX_RANGES)) { | |
1718 | start = 0; | |
1719 | this_cpu_write(*dom->next_index, 0); | |
1720 | } | |
1721 | ||
e6aabee0 JR |
1722 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : |
1723 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 | 1724 | |
2a87442c JR |
1725 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1726 | struct aperture_range *range; | |
5f6bed50 JR |
1727 | int index; |
1728 | ||
1729 | index = (start + i) % APERTURE_MAX_RANGES; | |
ccb50e03 | 1730 | |
5f6bed50 | 1731 | range = dom->aperture[index]; |
2a87442c JR |
1732 | |
1733 | if (!range || range->offset >= dma_mask) | |
1734 | continue; | |
384de729 | 1735 | |
2a87442c | 1736 | address = dma_ops_aperture_alloc(dom, range, pages, |
60e6a7cb | 1737 | dma_mask, boundary_size, |
7b5e25b8 | 1738 | align_mask, first); |
384de729 | 1739 | if (address != -1) { |
2a87442c | 1740 | address = range->offset + (address << PAGE_SHIFT); |
5f6bed50 | 1741 | this_cpu_write(*dom->next_index, index); |
384de729 JR |
1742 | break; |
1743 | } | |
384de729 JR |
1744 | } |
1745 | ||
7b5e25b8 JR |
1746 | if (address == -1 && first) { |
1747 | first = false; | |
1748 | goto again; | |
1749 | } | |
1750 | ||
5f6bed50 JR |
1751 | preempt_enable(); |
1752 | ||
384de729 JR |
1753 | return address; |
1754 | } | |
1755 | ||
d3086444 JR |
1756 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1757 | struct dma_ops_domain *dom, | |
6d4f343f | 1758 | unsigned int pages, |
832a90c3 JR |
1759 | unsigned long align_mask, |
1760 | u64 dma_mask) | |
d3086444 | 1761 | { |
266a3bd2 | 1762 | unsigned long address = -1; |
d3086444 | 1763 | |
266a3bd2 JR |
1764 | while (address == -1) { |
1765 | address = dma_ops_area_alloc(dev, dom, pages, | |
1766 | align_mask, dma_mask); | |
1767 | ||
7bfa5bd2 | 1768 | if (address == -1 && alloc_new_range(dom, false, GFP_ATOMIC)) |
266a3bd2 JR |
1769 | break; |
1770 | } | |
d3086444 | 1771 | |
384de729 | 1772 | if (unlikely(address == -1)) |
8fd524b3 | 1773 | address = DMA_ERROR_CODE; |
d3086444 JR |
1774 | |
1775 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1776 | ||
1777 | return address; | |
1778 | } | |
1779 | ||
431b2a20 JR |
1780 | /* |
1781 | * The address free function. | |
1782 | * | |
1783 | * called with domain->lock held | |
1784 | */ | |
d3086444 JR |
1785 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1786 | unsigned long address, | |
1787 | unsigned int pages) | |
1788 | { | |
384de729 JR |
1789 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1790 | struct aperture_range *range = dom->aperture[i]; | |
08c5fb93 | 1791 | unsigned long flags; |
80be308d | 1792 | |
384de729 JR |
1793 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1794 | ||
47bccd6b JR |
1795 | #ifdef CONFIG_IOMMU_STRESS |
1796 | if (i < 4) | |
1797 | return; | |
1798 | #endif | |
80be308d | 1799 | |
4eeca8c5 | 1800 | if (amd_iommu_unmap_flush) { |
d41ab098 JR |
1801 | domain_flush_tlb(&dom->domain); |
1802 | domain_flush_complete(&dom->domain); | |
1803 | } | |
384de729 JR |
1804 | |
1805 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1806 | |
08c5fb93 | 1807 | spin_lock_irqsave(&range->bitmap_lock, flags); |
4eeca8c5 JR |
1808 | if (address + pages > range->next_bit) |
1809 | range->next_bit = address + pages; | |
a66022c4 | 1810 | bitmap_clear(range->bitmap, address, pages); |
08c5fb93 | 1811 | spin_unlock_irqrestore(&range->bitmap_lock, flags); |
384de729 | 1812 | |
d3086444 JR |
1813 | } |
1814 | ||
431b2a20 JR |
1815 | /**************************************************************************** |
1816 | * | |
1817 | * The next functions belong to the domain allocation. A domain is | |
1818 | * allocated for every IOMMU as the default domain. If device isolation | |
1819 | * is enabled, every device get its own domain. The most important thing | |
1820 | * about domains is the page table mapping the DMA address space they | |
1821 | * contain. | |
1822 | * | |
1823 | ****************************************************************************/ | |
1824 | ||
aeb26f55 JR |
1825 | /* |
1826 | * This function adds a protection domain to the global protection domain list | |
1827 | */ | |
1828 | static void add_domain_to_list(struct protection_domain *domain) | |
1829 | { | |
1830 | unsigned long flags; | |
1831 | ||
1832 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1833 | list_add(&domain->list, &amd_iommu_pd_list); | |
1834 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1835 | } | |
1836 | ||
1837 | /* | |
1838 | * This function removes a protection domain to the global | |
1839 | * protection domain list | |
1840 | */ | |
1841 | static void del_domain_from_list(struct protection_domain *domain) | |
1842 | { | |
1843 | unsigned long flags; | |
1844 | ||
1845 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1846 | list_del(&domain->list); | |
1847 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1848 | } | |
1849 | ||
ec487d1a JR |
1850 | static u16 domain_id_alloc(void) |
1851 | { | |
1852 | unsigned long flags; | |
1853 | int id; | |
1854 | ||
1855 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1856 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1857 | BUG_ON(id == 0); | |
1858 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1859 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1860 | else | |
1861 | id = 0; | |
1862 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1863 | ||
1864 | return id; | |
1865 | } | |
1866 | ||
a2acfb75 JR |
1867 | static void domain_id_free(int id) |
1868 | { | |
1869 | unsigned long flags; | |
1870 | ||
1871 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1872 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1873 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1874 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1875 | } | |
a2acfb75 | 1876 | |
5c34c403 JR |
1877 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1878 | static void free_pt_##LVL (unsigned long __pt) \ | |
1879 | { \ | |
1880 | unsigned long p; \ | |
1881 | u64 *pt; \ | |
1882 | int i; \ | |
1883 | \ | |
1884 | pt = (u64 *)__pt; \ | |
1885 | \ | |
1886 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1887 | /* PTE present? */ \ |
5c34c403 JR |
1888 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1889 | continue; \ | |
1890 | \ | |
0b3fff54 JR |
1891 | /* Large PTE? */ \ |
1892 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1893 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1894 | continue; \ | |
1895 | \ | |
5c34c403 JR |
1896 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1897 | FN(p); \ | |
1898 | } \ | |
1899 | free_page((unsigned long)pt); \ | |
1900 | } | |
1901 | ||
1902 | DEFINE_FREE_PT_FN(l2, free_page) | |
1903 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1904 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1905 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1906 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1907 | ||
86db2e5d | 1908 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1909 | { |
5c34c403 | 1910 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1911 | |
5c34c403 JR |
1912 | switch (domain->mode) { |
1913 | case PAGE_MODE_NONE: | |
1914 | break; | |
1915 | case PAGE_MODE_1_LEVEL: | |
1916 | free_page(root); | |
1917 | break; | |
1918 | case PAGE_MODE_2_LEVEL: | |
1919 | free_pt_l2(root); | |
1920 | break; | |
1921 | case PAGE_MODE_3_LEVEL: | |
1922 | free_pt_l3(root); | |
1923 | break; | |
1924 | case PAGE_MODE_4_LEVEL: | |
1925 | free_pt_l4(root); | |
1926 | break; | |
1927 | case PAGE_MODE_5_LEVEL: | |
1928 | free_pt_l5(root); | |
1929 | break; | |
1930 | case PAGE_MODE_6_LEVEL: | |
1931 | free_pt_l6(root); | |
1932 | break; | |
1933 | default: | |
1934 | BUG(); | |
ec487d1a | 1935 | } |
ec487d1a JR |
1936 | } |
1937 | ||
b16137b1 JR |
1938 | static void free_gcr3_tbl_level1(u64 *tbl) |
1939 | { | |
1940 | u64 *ptr; | |
1941 | int i; | |
1942 | ||
1943 | for (i = 0; i < 512; ++i) { | |
1944 | if (!(tbl[i] & GCR3_VALID)) | |
1945 | continue; | |
1946 | ||
1947 | ptr = __va(tbl[i] & PAGE_MASK); | |
1948 | ||
1949 | free_page((unsigned long)ptr); | |
1950 | } | |
1951 | } | |
1952 | ||
1953 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1954 | { | |
1955 | u64 *ptr; | |
1956 | int i; | |
1957 | ||
1958 | for (i = 0; i < 512; ++i) { | |
1959 | if (!(tbl[i] & GCR3_VALID)) | |
1960 | continue; | |
1961 | ||
1962 | ptr = __va(tbl[i] & PAGE_MASK); | |
1963 | ||
1964 | free_gcr3_tbl_level1(ptr); | |
1965 | } | |
1966 | } | |
1967 | ||
52815b75 JR |
1968 | static void free_gcr3_table(struct protection_domain *domain) |
1969 | { | |
b16137b1 JR |
1970 | if (domain->glx == 2) |
1971 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1972 | else if (domain->glx == 1) | |
1973 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1974 | else |
1975 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1976 | |
52815b75 JR |
1977 | free_page((unsigned long)domain->gcr3_tbl); |
1978 | } | |
1979 | ||
431b2a20 JR |
1980 | /* |
1981 | * Free a domain, only used if something went wrong in the | |
1982 | * allocation path and we need to free an already allocated page table | |
1983 | */ | |
ec487d1a JR |
1984 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1985 | { | |
384de729 JR |
1986 | int i; |
1987 | ||
ec487d1a JR |
1988 | if (!dom) |
1989 | return; | |
1990 | ||
307d5851 JR |
1991 | put_iova_domain(&dom->iovad); |
1992 | ||
5f6bed50 JR |
1993 | free_percpu(dom->next_index); |
1994 | ||
aeb26f55 JR |
1995 | del_domain_from_list(&dom->domain); |
1996 | ||
86db2e5d | 1997 | free_pagetable(&dom->domain); |
ec487d1a | 1998 | |
384de729 JR |
1999 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
2000 | if (!dom->aperture[i]) | |
2001 | continue; | |
2002 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
2003 | kfree(dom->aperture[i]); | |
2004 | } | |
ec487d1a JR |
2005 | |
2006 | kfree(dom); | |
2007 | } | |
2008 | ||
a639a8ee JR |
2009 | static int dma_ops_domain_alloc_apertures(struct dma_ops_domain *dma_dom, |
2010 | int max_apertures) | |
2011 | { | |
2012 | int ret, i, apertures; | |
2013 | ||
2014 | apertures = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
2015 | ret = 0; | |
2016 | ||
2017 | for (i = apertures; i < max_apertures; ++i) { | |
2018 | ret = alloc_new_range(dma_dom, false, GFP_KERNEL); | |
2019 | if (ret) | |
2020 | break; | |
2021 | } | |
2022 | ||
2023 | return ret; | |
2024 | } | |
2025 | ||
431b2a20 JR |
2026 | /* |
2027 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 2028 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
2029 | * structures required for the dma_ops interface |
2030 | */ | |
87a64d52 | 2031 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
2032 | { |
2033 | struct dma_ops_domain *dma_dom; | |
5f6bed50 | 2034 | int cpu; |
ec487d1a JR |
2035 | |
2036 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
2037 | if (!dma_dom) | |
2038 | return NULL; | |
2039 | ||
7a5a566e | 2040 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 2041 | goto free_dma_dom; |
7a5a566e | 2042 | |
5f6bed50 JR |
2043 | dma_dom->next_index = alloc_percpu(u32); |
2044 | if (!dma_dom->next_index) | |
2045 | goto free_dma_dom; | |
2046 | ||
8f7a017c | 2047 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2048 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2049 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2050 | dma_dom->domain.priv = dma_dom; |
2051 | if (!dma_dom->domain.pt_root) | |
2052 | goto free_dma_dom; | |
ec487d1a | 2053 | |
aeb26f55 JR |
2054 | add_domain_to_list(&dma_dom->domain); |
2055 | ||
576175c2 | 2056 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2057 | goto free_dma_dom; |
ec487d1a | 2058 | |
431b2a20 | 2059 | /* |
ec487d1a JR |
2060 | * mark the first page as allocated so we never return 0 as |
2061 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2062 | */ |
384de729 | 2063 | dma_dom->aperture[0]->bitmap[0] = 1; |
ec487d1a | 2064 | |
5f6bed50 JR |
2065 | for_each_possible_cpu(cpu) |
2066 | *per_cpu_ptr(dma_dom->next_index, cpu) = 0; | |
ec487d1a | 2067 | |
307d5851 JR |
2068 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, |
2069 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2070 | ||
81cd07b9 JR |
2071 | /* Initialize reserved ranges */ |
2072 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
2073 | ||
ec487d1a JR |
2074 | return dma_dom; |
2075 | ||
2076 | free_dma_dom: | |
2077 | dma_ops_domain_free(dma_dom); | |
2078 | ||
2079 | return NULL; | |
2080 | } | |
2081 | ||
5b28df6f JR |
2082 | /* |
2083 | * little helper function to check whether a given protection domain is a | |
2084 | * dma_ops domain | |
2085 | */ | |
2086 | static bool dma_ops_domain(struct protection_domain *domain) | |
2087 | { | |
2088 | return domain->flags & PD_DMA_OPS_MASK; | |
2089 | } | |
2090 | ||
fd7b5535 | 2091 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2092 | { |
132bd68f | 2093 | u64 pte_root = 0; |
ee6c2868 | 2094 | u64 flags = 0; |
863c74eb | 2095 | |
132bd68f JR |
2096 | if (domain->mode != PAGE_MODE_NONE) |
2097 | pte_root = virt_to_phys(domain->pt_root); | |
2098 | ||
38ddf41b JR |
2099 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2100 | << DEV_ENTRY_MODE_SHIFT; | |
2101 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2102 | |
ee6c2868 JR |
2103 | flags = amd_iommu_dev_table[devid].data[1]; |
2104 | ||
fd7b5535 JR |
2105 | if (ats) |
2106 | flags |= DTE_FLAG_IOTLB; | |
2107 | ||
52815b75 JR |
2108 | if (domain->flags & PD_IOMMUV2_MASK) { |
2109 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2110 | u64 glx = domain->glx; | |
2111 | u64 tmp; | |
2112 | ||
2113 | pte_root |= DTE_FLAG_GV; | |
2114 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2115 | ||
2116 | /* First mask out possible old values for GCR3 table */ | |
2117 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2118 | flags &= ~tmp; | |
2119 | ||
2120 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2121 | flags &= ~tmp; | |
2122 | ||
2123 | /* Encode GCR3 table into DTE */ | |
2124 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2125 | pte_root |= tmp; | |
2126 | ||
2127 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2128 | flags |= tmp; | |
2129 | ||
2130 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2131 | flags |= tmp; | |
2132 | } | |
2133 | ||
ee6c2868 JR |
2134 | flags &= ~(0xffffUL); |
2135 | flags |= domain->id; | |
2136 | ||
2137 | amd_iommu_dev_table[devid].data[1] = flags; | |
2138 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2139 | } |
2140 | ||
2141 | static void clear_dte_entry(u16 devid) | |
2142 | { | |
15898bbc | 2143 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
2144 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
2145 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
2146 | |
2147 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2148 | } |
2149 | ||
ec9e79ef JR |
2150 | static void do_attach(struct iommu_dev_data *dev_data, |
2151 | struct protection_domain *domain) | |
7f760ddd | 2152 | { |
7f760ddd | 2153 | struct amd_iommu *iommu; |
e25bfb56 | 2154 | u16 alias; |
ec9e79ef | 2155 | bool ats; |
fd7b5535 | 2156 | |
ec9e79ef | 2157 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 2158 | alias = dev_data->alias; |
ec9e79ef | 2159 | ats = dev_data->ats.enabled; |
7f760ddd JR |
2160 | |
2161 | /* Update data structures */ | |
2162 | dev_data->domain = domain; | |
2163 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
2164 | |
2165 | /* Do reference counting */ | |
2166 | domain->dev_iommu[iommu->index] += 1; | |
2167 | domain->dev_cnt += 1; | |
2168 | ||
e25bfb56 JR |
2169 | /* Update device table */ |
2170 | set_dte_entry(dev_data->devid, domain, ats); | |
2171 | if (alias != dev_data->devid) | |
9b1a12d2 | 2172 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 2173 | |
6c542047 | 2174 | device_flush_dte(dev_data); |
7f760ddd JR |
2175 | } |
2176 | ||
ec9e79ef | 2177 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2178 | { |
7f760ddd | 2179 | struct amd_iommu *iommu; |
e25bfb56 | 2180 | u16 alias; |
7f760ddd | 2181 | |
5adad991 JR |
2182 | /* |
2183 | * First check if the device is still attached. It might already | |
2184 | * be detached from its domain because the generic | |
2185 | * iommu_detach_group code detached it and we try again here in | |
2186 | * our alias handling. | |
2187 | */ | |
2188 | if (!dev_data->domain) | |
2189 | return; | |
2190 | ||
ec9e79ef | 2191 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 2192 | alias = dev_data->alias; |
15898bbc JR |
2193 | |
2194 | /* decrease reference counters */ | |
7f760ddd JR |
2195 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2196 | dev_data->domain->dev_cnt -= 1; | |
2197 | ||
2198 | /* Update data structures */ | |
2199 | dev_data->domain = NULL; | |
2200 | list_del(&dev_data->list); | |
f62dda66 | 2201 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
2202 | if (alias != dev_data->devid) |
2203 | clear_dte_entry(alias); | |
15898bbc | 2204 | |
7f760ddd | 2205 | /* Flush the DTE entry */ |
6c542047 | 2206 | device_flush_dte(dev_data); |
2b681faf JR |
2207 | } |
2208 | ||
2209 | /* | |
2210 | * If a device is not yet associated with a domain, this function does | |
2211 | * assigns it visible for the hardware | |
2212 | */ | |
ec9e79ef | 2213 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2214 | struct protection_domain *domain) |
2b681faf | 2215 | { |
84fe6c19 | 2216 | int ret; |
657cbb6b | 2217 | |
272e4f99 JR |
2218 | /* |
2219 | * Must be called with IRQs disabled. Warn here to detect early | |
2220 | * when its not. | |
2221 | */ | |
2222 | WARN_ON(!irqs_disabled()); | |
2223 | ||
2b681faf JR |
2224 | /* lock domain */ |
2225 | spin_lock(&domain->lock); | |
2226 | ||
397111ab | 2227 | ret = -EBUSY; |
150952f9 | 2228 | if (dev_data->domain != NULL) |
397111ab | 2229 | goto out_unlock; |
15898bbc | 2230 | |
397111ab | 2231 | /* Attach alias group root */ |
150952f9 | 2232 | do_attach(dev_data, domain); |
24100055 | 2233 | |
84fe6c19 JL |
2234 | ret = 0; |
2235 | ||
2236 | out_unlock: | |
2237 | ||
eba6ac60 JR |
2238 | /* ready */ |
2239 | spin_unlock(&domain->lock); | |
15898bbc | 2240 | |
84fe6c19 | 2241 | return ret; |
0feae533 | 2242 | } |
b20ac0d4 | 2243 | |
52815b75 JR |
2244 | |
2245 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2246 | { | |
2247 | pci_disable_ats(pdev); | |
2248 | pci_disable_pri(pdev); | |
2249 | pci_disable_pasid(pdev); | |
2250 | } | |
2251 | ||
6a113ddc JR |
2252 | /* FIXME: Change generic reset-function to do the same */ |
2253 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2254 | { | |
2255 | u16 control; | |
2256 | int pos; | |
2257 | ||
46277b75 | 2258 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2259 | if (!pos) |
2260 | return -EINVAL; | |
2261 | ||
46277b75 JR |
2262 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2263 | control |= PCI_PRI_CTRL_RESET; | |
2264 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2265 | |
2266 | return 0; | |
2267 | } | |
2268 | ||
52815b75 JR |
2269 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2270 | { | |
6a113ddc JR |
2271 | bool reset_enable; |
2272 | int reqs, ret; | |
2273 | ||
2274 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2275 | reqs = 32; | |
2276 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2277 | reqs = 1; | |
2278 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2279 | |
2280 | /* Only allow access to user-accessible pages */ | |
2281 | ret = pci_enable_pasid(pdev, 0); | |
2282 | if (ret) | |
2283 | goto out_err; | |
2284 | ||
2285 | /* First reset the PRI state of the device */ | |
2286 | ret = pci_reset_pri(pdev); | |
2287 | if (ret) | |
2288 | goto out_err; | |
2289 | ||
6a113ddc JR |
2290 | /* Enable PRI */ |
2291 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2292 | if (ret) |
2293 | goto out_err; | |
2294 | ||
6a113ddc JR |
2295 | if (reset_enable) { |
2296 | ret = pri_reset_while_enabled(pdev); | |
2297 | if (ret) | |
2298 | goto out_err; | |
2299 | } | |
2300 | ||
52815b75 JR |
2301 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2302 | if (ret) | |
2303 | goto out_err; | |
2304 | ||
2305 | return 0; | |
2306 | ||
2307 | out_err: | |
2308 | pci_disable_pri(pdev); | |
2309 | pci_disable_pasid(pdev); | |
2310 | ||
2311 | return ret; | |
2312 | } | |
2313 | ||
c99afa25 | 2314 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2315 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2316 | |
98f1ad25 | 2317 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2318 | { |
a3b93121 | 2319 | u16 status; |
c99afa25 JR |
2320 | int pos; |
2321 | ||
46277b75 | 2322 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2323 | if (!pos) |
2324 | return false; | |
2325 | ||
a3b93121 | 2326 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2327 | |
a3b93121 | 2328 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2329 | } |
2330 | ||
407d733e | 2331 | /* |
df805abb | 2332 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2333 | * assigns it visible for the hardware |
2334 | */ | |
15898bbc JR |
2335 | static int attach_device(struct device *dev, |
2336 | struct protection_domain *domain) | |
0feae533 | 2337 | { |
2bf9a0a1 | 2338 | struct pci_dev *pdev; |
ea61cddb | 2339 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2340 | unsigned long flags; |
15898bbc | 2341 | int ret; |
eba6ac60 | 2342 | |
ea61cddb JR |
2343 | dev_data = get_dev_data(dev); |
2344 | ||
2bf9a0a1 WZ |
2345 | if (!dev_is_pci(dev)) |
2346 | goto skip_ats_check; | |
2347 | ||
2348 | pdev = to_pci_dev(dev); | |
52815b75 | 2349 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2350 | if (!dev_data->passthrough) |
52815b75 JR |
2351 | return -EINVAL; |
2352 | ||
02ca2021 JR |
2353 | if (dev_data->iommu_v2) { |
2354 | if (pdev_iommuv2_enable(pdev) != 0) | |
2355 | return -EINVAL; | |
52815b75 | 2356 | |
02ca2021 JR |
2357 | dev_data->ats.enabled = true; |
2358 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2359 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2360 | } | |
52815b75 JR |
2361 | } else if (amd_iommu_iotlb_sup && |
2362 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2363 | dev_data->ats.enabled = true; |
2364 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2365 | } | |
fd7b5535 | 2366 | |
2bf9a0a1 | 2367 | skip_ats_check: |
eba6ac60 | 2368 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2369 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2370 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2371 | ||
0feae533 JR |
2372 | /* |
2373 | * We might boot into a crash-kernel here. The crashed kernel | |
2374 | * left the caches in the IOMMU dirty. So we have to flush | |
2375 | * here to evict all dirty stuff. | |
2376 | */ | |
17b124bf | 2377 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2378 | |
2379 | return ret; | |
b20ac0d4 JR |
2380 | } |
2381 | ||
355bf553 JR |
2382 | /* |
2383 | * Removes a device from a protection domain (unlocked) | |
2384 | */ | |
ec9e79ef | 2385 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2386 | { |
2ca76279 | 2387 | struct protection_domain *domain; |
c4596114 | 2388 | |
272e4f99 JR |
2389 | /* |
2390 | * Must be called with IRQs disabled. Warn here to detect early | |
2391 | * when its not. | |
2392 | */ | |
2393 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2394 | |
f34c73f5 JR |
2395 | if (WARN_ON(!dev_data->domain)) |
2396 | return; | |
24100055 | 2397 | |
2ca76279 | 2398 | domain = dev_data->domain; |
71f77580 | 2399 | |
f1dd0a8b | 2400 | spin_lock(&domain->lock); |
24100055 | 2401 | |
150952f9 | 2402 | do_detach(dev_data); |
7f760ddd | 2403 | |
f1dd0a8b | 2404 | spin_unlock(&domain->lock); |
355bf553 JR |
2405 | } |
2406 | ||
2407 | /* | |
2408 | * Removes a device from a protection domain (with devtable_lock held) | |
2409 | */ | |
15898bbc | 2410 | static void detach_device(struct device *dev) |
355bf553 | 2411 | { |
52815b75 | 2412 | struct protection_domain *domain; |
ea61cddb | 2413 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2414 | unsigned long flags; |
2415 | ||
ec9e79ef | 2416 | dev_data = get_dev_data(dev); |
52815b75 | 2417 | domain = dev_data->domain; |
ec9e79ef | 2418 | |
355bf553 JR |
2419 | /* lock device table */ |
2420 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2421 | __detach_device(dev_data); |
355bf553 | 2422 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2423 | |
2bf9a0a1 WZ |
2424 | if (!dev_is_pci(dev)) |
2425 | return; | |
2426 | ||
02ca2021 | 2427 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2428 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2429 | else if (dev_data->ats.enabled) | |
ea61cddb | 2430 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2431 | |
2432 | dev_data->ats.enabled = false; | |
355bf553 | 2433 | } |
e275a2a0 | 2434 | |
aafd8ba0 | 2435 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2436 | { |
5abcdba4 | 2437 | struct iommu_dev_data *dev_data; |
07ee8694 | 2438 | struct iommu_domain *domain; |
e275a2a0 | 2439 | struct amd_iommu *iommu; |
7aba6cb9 | 2440 | int ret, devid; |
e275a2a0 | 2441 | |
aafd8ba0 | 2442 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2443 | return 0; |
e275a2a0 | 2444 | |
aafd8ba0 | 2445 | devid = get_device_id(dev); |
9ee35e4c | 2446 | if (devid < 0) |
7aba6cb9 WZ |
2447 | return devid; |
2448 | ||
aafd8ba0 | 2449 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2450 | |
aafd8ba0 | 2451 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2452 | if (ret) { |
2453 | if (ret != -ENOTSUPP) | |
2454 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2455 | dev_name(dev)); | |
657cbb6b | 2456 | |
aafd8ba0 | 2457 | iommu_ignore_device(dev); |
343e9cac | 2458 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2459 | goto out; |
2460 | } | |
2461 | init_iommu_group(dev); | |
2c9195e9 | 2462 | |
07ee8694 | 2463 | dev_data = get_dev_data(dev); |
2c9195e9 | 2464 | |
4d58b8a6 | 2465 | BUG_ON(!dev_data); |
657cbb6b | 2466 | |
1e6a7b04 | 2467 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2468 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2469 | |
07ee8694 JR |
2470 | /* Domains are initialized for this device - have a look what we ended up with */ |
2471 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2472 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2473 | dev_data->passthrough = true; |
32302324 | 2474 | else |
2c9195e9 | 2475 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2476 | |
aafd8ba0 | 2477 | out: |
e275a2a0 JR |
2478 | iommu_completion_wait(iommu); |
2479 | ||
e275a2a0 JR |
2480 | return 0; |
2481 | } | |
2482 | ||
aafd8ba0 | 2483 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2484 | { |
aafd8ba0 | 2485 | struct amd_iommu *iommu; |
7aba6cb9 | 2486 | int devid; |
aafd8ba0 JR |
2487 | |
2488 | if (!check_device(dev)) | |
2489 | return; | |
2490 | ||
2491 | devid = get_device_id(dev); | |
9ee35e4c | 2492 | if (devid < 0) |
7aba6cb9 WZ |
2493 | return; |
2494 | ||
aafd8ba0 JR |
2495 | iommu = amd_iommu_rlookup_table[devid]; |
2496 | ||
2497 | iommu_uninit_device(dev); | |
2498 | iommu_completion_wait(iommu); | |
8638c491 JR |
2499 | } |
2500 | ||
b097d11a WZ |
2501 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2502 | { | |
2503 | if (dev_is_pci(dev)) | |
2504 | return pci_device_group(dev); | |
2505 | ||
2506 | return acpihid_device_group(dev); | |
2507 | } | |
2508 | ||
431b2a20 JR |
2509 | /***************************************************************************** |
2510 | * | |
2511 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2512 | * | |
2513 | *****************************************************************************/ | |
2514 | ||
2515 | /* | |
2516 | * In the dma_ops path we only have the struct device. This function | |
2517 | * finds the corresponding IOMMU, the protection domain and the | |
2518 | * requestor id for a given device. | |
2519 | * If the device is not yet associated with a domain this is also done | |
2520 | * in this function. | |
2521 | */ | |
94f6d190 | 2522 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2523 | { |
94f6d190 | 2524 | struct protection_domain *domain; |
063071df | 2525 | struct iommu_domain *io_domain; |
b20ac0d4 | 2526 | |
f99c0f1c | 2527 | if (!check_device(dev)) |
94f6d190 | 2528 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2529 | |
063071df | 2530 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2531 | if (!io_domain) |
2532 | return NULL; | |
b20ac0d4 | 2533 | |
0bb6e243 JR |
2534 | domain = to_pdomain(io_domain); |
2535 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2536 | return ERR_PTR(-EBUSY); |
f91ba190 | 2537 | |
0bb6e243 | 2538 | return domain; |
b20ac0d4 JR |
2539 | } |
2540 | ||
04bfdd84 JR |
2541 | static void update_device_table(struct protection_domain *domain) |
2542 | { | |
492667da | 2543 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2544 | |
ea61cddb JR |
2545 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2546 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2547 | } |
2548 | ||
2549 | static void update_domain(struct protection_domain *domain) | |
2550 | { | |
2551 | if (!domain->updated) | |
2552 | return; | |
2553 | ||
2554 | update_device_table(domain); | |
17b124bf JR |
2555 | |
2556 | domain_flush_devices(domain); | |
2557 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2558 | |
2559 | domain->updated = false; | |
2560 | } | |
2561 | ||
8bda3092 JR |
2562 | /* |
2563 | * This function fetches the PTE for a given address in the aperture | |
2564 | */ | |
2565 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2566 | unsigned long address) | |
2567 | { | |
384de729 | 2568 | struct aperture_range *aperture; |
8bda3092 JR |
2569 | u64 *pte, *pte_page; |
2570 | ||
384de729 JR |
2571 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2572 | if (!aperture) | |
2573 | return NULL; | |
2574 | ||
2575 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2576 | if (!pte) { |
cbb9d729 | 2577 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2578 | GFP_ATOMIC); |
384de729 JR |
2579 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2580 | } else | |
8c8c143c | 2581 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2582 | |
04bfdd84 | 2583 | update_domain(&dom->domain); |
8bda3092 JR |
2584 | |
2585 | return pte; | |
2586 | } | |
2587 | ||
431b2a20 JR |
2588 | /* |
2589 | * This is the generic map function. It maps one 4kb page at paddr to | |
2590 | * the given address in the DMA address space for the domain. | |
2591 | */ | |
680525e0 | 2592 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2593 | unsigned long address, |
2594 | phys_addr_t paddr, | |
2595 | int direction) | |
2596 | { | |
2597 | u64 *pte, __pte; | |
2598 | ||
2599 | WARN_ON(address > dom->aperture_size); | |
2600 | ||
2601 | paddr &= PAGE_MASK; | |
2602 | ||
8bda3092 | 2603 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2604 | if (!pte) |
8fd524b3 | 2605 | return DMA_ERROR_CODE; |
cb76c322 JR |
2606 | |
2607 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2608 | ||
2609 | if (direction == DMA_TO_DEVICE) | |
2610 | __pte |= IOMMU_PTE_IR; | |
2611 | else if (direction == DMA_FROM_DEVICE) | |
2612 | __pte |= IOMMU_PTE_IW; | |
2613 | else if (direction == DMA_BIDIRECTIONAL) | |
2614 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2615 | ||
a7fb668f | 2616 | WARN_ON_ONCE(*pte); |
cb76c322 JR |
2617 | |
2618 | *pte = __pte; | |
2619 | ||
2620 | return (dma_addr_t)address; | |
2621 | } | |
2622 | ||
431b2a20 JR |
2623 | /* |
2624 | * The generic unmapping function for on page in the DMA address space. | |
2625 | */ | |
680525e0 | 2626 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2627 | unsigned long address) |
2628 | { | |
384de729 | 2629 | struct aperture_range *aperture; |
cb76c322 JR |
2630 | u64 *pte; |
2631 | ||
2632 | if (address >= dom->aperture_size) | |
2633 | return; | |
2634 | ||
384de729 JR |
2635 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2636 | if (!aperture) | |
2637 | return; | |
2638 | ||
2639 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2640 | if (!pte) | |
2641 | return; | |
cb76c322 | 2642 | |
8c8c143c | 2643 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 | 2644 | |
a7fb668f | 2645 | WARN_ON_ONCE(!*pte); |
cb76c322 JR |
2646 | |
2647 | *pte = 0ULL; | |
2648 | } | |
2649 | ||
431b2a20 JR |
2650 | /* |
2651 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2652 | * contiguous memory region into DMA address space. It is used by all |
2653 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2654 | * Must be called with the domain lock held. |
2655 | */ | |
cb76c322 | 2656 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2657 | struct dma_ops_domain *dma_dom, |
2658 | phys_addr_t paddr, | |
2659 | size_t size, | |
6d4f343f | 2660 | int dir, |
832a90c3 JR |
2661 | bool align, |
2662 | u64 dma_mask) | |
cb76c322 JR |
2663 | { |
2664 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2665 | dma_addr_t address, start, ret; |
cb76c322 | 2666 | unsigned int pages; |
6d4f343f | 2667 | unsigned long align_mask = 0; |
cb76c322 JR |
2668 | int i; |
2669 | ||
e3c449f5 | 2670 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2671 | paddr &= PAGE_MASK; |
2672 | ||
6d4f343f JR |
2673 | if (align) |
2674 | align_mask = (1UL << get_order(size)) - 1; | |
2675 | ||
832a90c3 JR |
2676 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2677 | dma_mask); | |
ebaecb42 | 2678 | |
266a3bd2 JR |
2679 | if (address == DMA_ERROR_CODE) |
2680 | goto out; | |
cb76c322 JR |
2681 | |
2682 | start = address; | |
2683 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2684 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2685 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2686 | goto out_unmap; |
2687 | ||
cb76c322 JR |
2688 | paddr += PAGE_SIZE; |
2689 | start += PAGE_SIZE; | |
2690 | } | |
2691 | address += offset; | |
2692 | ||
ab7032bb | 2693 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2694 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2695 | domain_flush_complete(&dma_dom->domain); |
2696 | } | |
270cab24 | 2697 | |
cb76c322 JR |
2698 | out: |
2699 | return address; | |
53812c11 JR |
2700 | |
2701 | out_unmap: | |
2702 | ||
2703 | for (--i; i >= 0; --i) { | |
2704 | start -= PAGE_SIZE; | |
680525e0 | 2705 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2706 | } |
2707 | ||
2708 | dma_ops_free_addresses(dma_dom, address, pages); | |
2709 | ||
8fd524b3 | 2710 | return DMA_ERROR_CODE; |
cb76c322 JR |
2711 | } |
2712 | ||
431b2a20 JR |
2713 | /* |
2714 | * Does the reverse of the __map_single function. Must be called with | |
2715 | * the domain lock held too | |
2716 | */ | |
cd8c82e8 | 2717 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2718 | dma_addr_t dma_addr, |
2719 | size_t size, | |
2720 | int dir) | |
2721 | { | |
04e0463e | 2722 | dma_addr_t flush_addr; |
cb76c322 JR |
2723 | dma_addr_t i, start; |
2724 | unsigned int pages; | |
2725 | ||
8fd524b3 | 2726 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2727 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2728 | return; |
2729 | ||
04e0463e | 2730 | flush_addr = dma_addr; |
e3c449f5 | 2731 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2732 | dma_addr &= PAGE_MASK; |
2733 | start = dma_addr; | |
2734 | ||
2735 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2736 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2737 | start += PAGE_SIZE; |
2738 | } | |
2739 | ||
84b3a0bc | 2740 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
cb76c322 JR |
2741 | } |
2742 | ||
431b2a20 JR |
2743 | /* |
2744 | * The exported map_single function for dma_ops. | |
2745 | */ | |
51491367 FT |
2746 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2747 | unsigned long offset, size_t size, | |
2748 | enum dma_data_direction dir, | |
2749 | struct dma_attrs *attrs) | |
4da70b9e | 2750 | { |
92d420ec | 2751 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2752 | struct protection_domain *domain; |
832a90c3 | 2753 | u64 dma_mask; |
4da70b9e | 2754 | |
94f6d190 JR |
2755 | domain = get_domain(dev); |
2756 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2757 | return (dma_addr_t)paddr; |
94f6d190 JR |
2758 | else if (IS_ERR(domain)) |
2759 | return DMA_ERROR_CODE; | |
4da70b9e | 2760 | |
f99c0f1c JR |
2761 | dma_mask = *dev->dma_mask; |
2762 | ||
92d420ec | 2763 | return __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2764 | dma_mask); |
4da70b9e JR |
2765 | } |
2766 | ||
431b2a20 JR |
2767 | /* |
2768 | * The exported unmap_single function for dma_ops. | |
2769 | */ | |
51491367 FT |
2770 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2771 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e | 2772 | { |
4da70b9e | 2773 | struct protection_domain *domain; |
4da70b9e | 2774 | |
94f6d190 JR |
2775 | domain = get_domain(dev); |
2776 | if (IS_ERR(domain)) | |
5b28df6f JR |
2777 | return; |
2778 | ||
cd8c82e8 | 2779 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e JR |
2780 | } |
2781 | ||
431b2a20 JR |
2782 | /* |
2783 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2784 | * lists). | |
2785 | */ | |
65b050ad | 2786 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2787 | int nelems, enum dma_data_direction dir, |
2788 | struct dma_attrs *attrs) | |
65b050ad | 2789 | { |
65b050ad | 2790 | struct protection_domain *domain; |
65b050ad JR |
2791 | int i; |
2792 | struct scatterlist *s; | |
2793 | phys_addr_t paddr; | |
2794 | int mapped_elems = 0; | |
832a90c3 | 2795 | u64 dma_mask; |
65b050ad | 2796 | |
94f6d190 | 2797 | domain = get_domain(dev); |
a0e191b2 | 2798 | if (IS_ERR(domain)) |
94f6d190 | 2799 | return 0; |
dbcc112e | 2800 | |
832a90c3 | 2801 | dma_mask = *dev->dma_mask; |
65b050ad | 2802 | |
65b050ad JR |
2803 | for_each_sg(sglist, s, nelems, i) { |
2804 | paddr = sg_phys(s); | |
2805 | ||
cd8c82e8 | 2806 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2807 | paddr, s->length, dir, false, |
2808 | dma_mask); | |
65b050ad JR |
2809 | |
2810 | if (s->dma_address) { | |
2811 | s->dma_length = s->length; | |
2812 | mapped_elems++; | |
2813 | } else | |
2814 | goto unmap; | |
65b050ad JR |
2815 | } |
2816 | ||
65b050ad | 2817 | return mapped_elems; |
92d420ec | 2818 | |
65b050ad JR |
2819 | unmap: |
2820 | for_each_sg(sglist, s, mapped_elems, i) { | |
2821 | if (s->dma_address) | |
cd8c82e8 | 2822 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2823 | s->dma_length, dir); |
2824 | s->dma_address = s->dma_length = 0; | |
2825 | } | |
2826 | ||
92d420ec | 2827 | return 0; |
65b050ad JR |
2828 | } |
2829 | ||
431b2a20 JR |
2830 | /* |
2831 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2832 | * lists). | |
2833 | */ | |
65b050ad | 2834 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2835 | int nelems, enum dma_data_direction dir, |
2836 | struct dma_attrs *attrs) | |
65b050ad | 2837 | { |
65b050ad JR |
2838 | struct protection_domain *domain; |
2839 | struct scatterlist *s; | |
65b050ad JR |
2840 | int i; |
2841 | ||
94f6d190 JR |
2842 | domain = get_domain(dev); |
2843 | if (IS_ERR(domain)) | |
5b28df6f JR |
2844 | return; |
2845 | ||
65b050ad | 2846 | for_each_sg(sglist, s, nelems, i) { |
cd8c82e8 | 2847 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2848 | s->dma_length, dir); |
65b050ad JR |
2849 | s->dma_address = s->dma_length = 0; |
2850 | } | |
65b050ad JR |
2851 | } |
2852 | ||
431b2a20 JR |
2853 | /* |
2854 | * The exported alloc_coherent function for dma_ops. | |
2855 | */ | |
5d8b53cf | 2856 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2857 | dma_addr_t *dma_addr, gfp_t flag, |
2858 | struct dma_attrs *attrs) | |
5d8b53cf | 2859 | { |
832a90c3 | 2860 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2861 | struct protection_domain *domain; |
3b839a57 | 2862 | struct page *page; |
5d8b53cf | 2863 | |
94f6d190 JR |
2864 | domain = get_domain(dev); |
2865 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2866 | page = alloc_pages(flag, get_order(size)); |
2867 | *dma_addr = page_to_phys(page); | |
2868 | return page_address(page); | |
94f6d190 JR |
2869 | } else if (IS_ERR(domain)) |
2870 | return NULL; | |
5d8b53cf | 2871 | |
3b839a57 | 2872 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2873 | dma_mask = dev->coherent_dma_mask; |
2874 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2875 | flag |= __GFP_ZERO; |
5d8b53cf | 2876 | |
3b839a57 JR |
2877 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2878 | if (!page) { | |
d0164adc | 2879 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2880 | return NULL; |
5d8b53cf | 2881 | |
3b839a57 JR |
2882 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2883 | get_order(size)); | |
2884 | if (!page) | |
2885 | return NULL; | |
2886 | } | |
5d8b53cf | 2887 | |
832a90c3 JR |
2888 | if (!dma_mask) |
2889 | dma_mask = *dev->dma_mask; | |
2890 | ||
3b839a57 | 2891 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2892 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2893 | |
92d420ec | 2894 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2895 | goto out_free; |
5d8b53cf | 2896 | |
3b839a57 | 2897 | return page_address(page); |
5b28df6f JR |
2898 | |
2899 | out_free: | |
2900 | ||
3b839a57 JR |
2901 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2902 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2903 | |
2904 | return NULL; | |
5d8b53cf JR |
2905 | } |
2906 | ||
431b2a20 JR |
2907 | /* |
2908 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2909 | */ |
5d8b53cf | 2910 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2911 | void *virt_addr, dma_addr_t dma_addr, |
2912 | struct dma_attrs *attrs) | |
5d8b53cf | 2913 | { |
5d8b53cf | 2914 | struct protection_domain *domain; |
3b839a57 | 2915 | struct page *page; |
5d8b53cf | 2916 | |
3b839a57 JR |
2917 | page = virt_to_page(virt_addr); |
2918 | size = PAGE_ALIGN(size); | |
2919 | ||
94f6d190 JR |
2920 | domain = get_domain(dev); |
2921 | if (IS_ERR(domain)) | |
5b28df6f JR |
2922 | goto free_mem; |
2923 | ||
cd8c82e8 | 2924 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2925 | |
5d8b53cf | 2926 | free_mem: |
3b839a57 JR |
2927 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2928 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2929 | } |
2930 | ||
b39ba6ad JR |
2931 | /* |
2932 | * This function is called by the DMA layer to find out if we can handle a | |
2933 | * particular device. It is part of the dma_ops. | |
2934 | */ | |
2935 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2936 | { | |
420aef8a | 2937 | return check_device(dev); |
b39ba6ad JR |
2938 | } |
2939 | ||
a639a8ee JR |
2940 | static int set_dma_mask(struct device *dev, u64 mask) |
2941 | { | |
2942 | struct protection_domain *domain; | |
2943 | int max_apertures = 1; | |
2944 | ||
2945 | domain = get_domain(dev); | |
2946 | if (IS_ERR(domain)) | |
2947 | return PTR_ERR(domain); | |
2948 | ||
2949 | if (mask == DMA_BIT_MASK(64)) | |
2950 | max_apertures = 8; | |
2951 | else if (mask > DMA_BIT_MASK(32)) | |
2952 | max_apertures = 4; | |
2953 | ||
2954 | /* | |
2955 | * To prevent lock contention it doesn't make sense to allocate more | |
2956 | * apertures than online cpus | |
2957 | */ | |
2958 | if (max_apertures > num_online_cpus()) | |
2959 | max_apertures = num_online_cpus(); | |
2960 | ||
2961 | if (dma_ops_domain_alloc_apertures(domain->priv, max_apertures)) | |
2962 | dev_err(dev, "Can't allocate %d iommu apertures\n", | |
2963 | max_apertures); | |
2964 | ||
2965 | return 0; | |
2966 | } | |
2967 | ||
160c1d8e | 2968 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2969 | .alloc = alloc_coherent, |
2970 | .free = free_coherent, | |
2971 | .map_page = map_page, | |
2972 | .unmap_page = unmap_page, | |
2973 | .map_sg = map_sg, | |
2974 | .unmap_sg = unmap_sg, | |
2975 | .dma_supported = amd_iommu_dma_supported, | |
2976 | .set_dma_mask = set_dma_mask, | |
6631ee9d JR |
2977 | }; |
2978 | ||
81cd07b9 JR |
2979 | static int init_reserved_iova_ranges(void) |
2980 | { | |
2981 | struct pci_dev *pdev = NULL; | |
2982 | struct iova *val; | |
2983 | ||
2984 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, | |
2985 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2986 | ||
2987 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2988 | &reserved_rbtree_key); | |
2989 | ||
2990 | /* MSI memory range */ | |
2991 | val = reserve_iova(&reserved_iova_ranges, | |
2992 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2993 | if (!val) { | |
2994 | pr_err("Reserving MSI range failed\n"); | |
2995 | return -ENOMEM; | |
2996 | } | |
2997 | ||
2998 | /* HT memory range */ | |
2999 | val = reserve_iova(&reserved_iova_ranges, | |
3000 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
3001 | if (!val) { | |
3002 | pr_err("Reserving HT range failed\n"); | |
3003 | return -ENOMEM; | |
3004 | } | |
3005 | ||
3006 | /* | |
3007 | * Memory used for PCI resources | |
3008 | * FIXME: Check whether we can reserve the PCI-hole completly | |
3009 | */ | |
3010 | for_each_pci_dev(pdev) { | |
3011 | int i; | |
3012 | ||
3013 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
3014 | struct resource *r = &pdev->resource[i]; | |
3015 | ||
3016 | if (!(r->flags & IORESOURCE_MEM)) | |
3017 | continue; | |
3018 | ||
3019 | val = reserve_iova(&reserved_iova_ranges, | |
3020 | IOVA_PFN(r->start), | |
3021 | IOVA_PFN(r->end)); | |
3022 | if (!val) { | |
3023 | pr_err("Reserve pci-resource range failed\n"); | |
3024 | return -ENOMEM; | |
3025 | } | |
3026 | } | |
3027 | } | |
3028 | ||
3029 | return 0; | |
3030 | } | |
3031 | ||
3a18404c | 3032 | int __init amd_iommu_init_api(void) |
27c2127a | 3033 | { |
307d5851 JR |
3034 | int ret, err = 0; |
3035 | ||
3036 | ret = iova_cache_get(); | |
3037 | if (ret) | |
3038 | return ret; | |
9a4d3bf5 | 3039 | |
81cd07b9 JR |
3040 | ret = init_reserved_iova_ranges(); |
3041 | if (ret) | |
3042 | return ret; | |
3043 | ||
9a4d3bf5 WZ |
3044 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
3045 | if (err) | |
3046 | return err; | |
3047 | #ifdef CONFIG_ARM_AMBA | |
3048 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
3049 | if (err) | |
3050 | return err; | |
3051 | #endif | |
0076cd3d WZ |
3052 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
3053 | if (err) | |
3054 | return err; | |
9a4d3bf5 | 3055 | return 0; |
f5325094 JR |
3056 | } |
3057 | ||
6631ee9d JR |
3058 | int __init amd_iommu_init_dma_ops(void) |
3059 | { | |
32302324 | 3060 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 3061 | iommu_detected = 1; |
6631ee9d | 3062 | |
52717828 JR |
3063 | /* |
3064 | * In case we don't initialize SWIOTLB (actually the common case | |
3065 | * when AMD IOMMU is enabled), make sure there are global | |
3066 | * dma_ops set as a fall-back for devices not handled by this | |
3067 | * driver (for example non-PCI devices). | |
3068 | */ | |
3069 | if (!swiotlb) | |
3070 | dma_ops = &nommu_dma_ops; | |
3071 | ||
62410eeb JR |
3072 | if (amd_iommu_unmap_flush) |
3073 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3074 | else | |
3075 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3076 | ||
6631ee9d | 3077 | return 0; |
6631ee9d | 3078 | } |
6d98cd80 JR |
3079 | |
3080 | /***************************************************************************** | |
3081 | * | |
3082 | * The following functions belong to the exported interface of AMD IOMMU | |
3083 | * | |
3084 | * This interface allows access to lower level functions of the IOMMU | |
3085 | * like protection domain handling and assignement of devices to domains | |
3086 | * which is not possible with the dma_ops interface. | |
3087 | * | |
3088 | *****************************************************************************/ | |
3089 | ||
6d98cd80 JR |
3090 | static void cleanup_domain(struct protection_domain *domain) |
3091 | { | |
9b29d3c6 | 3092 | struct iommu_dev_data *entry; |
6d98cd80 | 3093 | unsigned long flags; |
6d98cd80 JR |
3094 | |
3095 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3096 | ||
9b29d3c6 JR |
3097 | while (!list_empty(&domain->dev_list)) { |
3098 | entry = list_first_entry(&domain->dev_list, | |
3099 | struct iommu_dev_data, list); | |
3100 | __detach_device(entry); | |
492667da | 3101 | } |
6d98cd80 JR |
3102 | |
3103 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3104 | } | |
3105 | ||
2650815f JR |
3106 | static void protection_domain_free(struct protection_domain *domain) |
3107 | { | |
3108 | if (!domain) | |
3109 | return; | |
3110 | ||
aeb26f55 JR |
3111 | del_domain_from_list(domain); |
3112 | ||
2650815f JR |
3113 | if (domain->id) |
3114 | domain_id_free(domain->id); | |
3115 | ||
3116 | kfree(domain); | |
3117 | } | |
3118 | ||
7a5a566e JR |
3119 | static int protection_domain_init(struct protection_domain *domain) |
3120 | { | |
3121 | spin_lock_init(&domain->lock); | |
3122 | mutex_init(&domain->api_lock); | |
3123 | domain->id = domain_id_alloc(); | |
3124 | if (!domain->id) | |
3125 | return -ENOMEM; | |
3126 | INIT_LIST_HEAD(&domain->dev_list); | |
3127 | ||
3128 | return 0; | |
3129 | } | |
3130 | ||
2650815f | 3131 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
3132 | { |
3133 | struct protection_domain *domain; | |
3134 | ||
3135 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3136 | if (!domain) | |
2650815f | 3137 | return NULL; |
c156e347 | 3138 | |
7a5a566e | 3139 | if (protection_domain_init(domain)) |
2650815f JR |
3140 | goto out_err; |
3141 | ||
aeb26f55 JR |
3142 | add_domain_to_list(domain); |
3143 | ||
2650815f JR |
3144 | return domain; |
3145 | ||
3146 | out_err: | |
3147 | kfree(domain); | |
3148 | ||
3149 | return NULL; | |
3150 | } | |
3151 | ||
3f4b87b9 | 3152 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 3153 | { |
3f4b87b9 | 3154 | struct protection_domain *pdomain; |
0bb6e243 | 3155 | struct dma_ops_domain *dma_domain; |
2650815f | 3156 | |
0bb6e243 JR |
3157 | switch (type) { |
3158 | case IOMMU_DOMAIN_UNMANAGED: | |
3159 | pdomain = protection_domain_alloc(); | |
3160 | if (!pdomain) | |
3161 | return NULL; | |
c156e347 | 3162 | |
0bb6e243 JR |
3163 | pdomain->mode = PAGE_MODE_3_LEVEL; |
3164 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
3165 | if (!pdomain->pt_root) { | |
3166 | protection_domain_free(pdomain); | |
3167 | return NULL; | |
3168 | } | |
c156e347 | 3169 | |
0bb6e243 JR |
3170 | pdomain->domain.geometry.aperture_start = 0; |
3171 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
3172 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 3173 | |
0bb6e243 JR |
3174 | break; |
3175 | case IOMMU_DOMAIN_DMA: | |
3176 | dma_domain = dma_ops_domain_alloc(); | |
3177 | if (!dma_domain) { | |
3178 | pr_err("AMD-Vi: Failed to allocate\n"); | |
3179 | return NULL; | |
3180 | } | |
3181 | pdomain = &dma_domain->domain; | |
3182 | break; | |
07f643a3 JR |
3183 | case IOMMU_DOMAIN_IDENTITY: |
3184 | pdomain = protection_domain_alloc(); | |
3185 | if (!pdomain) | |
3186 | return NULL; | |
c156e347 | 3187 | |
07f643a3 JR |
3188 | pdomain->mode = PAGE_MODE_NONE; |
3189 | break; | |
0bb6e243 JR |
3190 | default: |
3191 | return NULL; | |
3192 | } | |
c156e347 | 3193 | |
3f4b87b9 | 3194 | return &pdomain->domain; |
c156e347 JR |
3195 | } |
3196 | ||
3f4b87b9 | 3197 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 3198 | { |
3f4b87b9 | 3199 | struct protection_domain *domain; |
98383fc3 | 3200 | |
3f4b87b9 | 3201 | if (!dom) |
98383fc3 JR |
3202 | return; |
3203 | ||
3f4b87b9 JR |
3204 | domain = to_pdomain(dom); |
3205 | ||
98383fc3 JR |
3206 | if (domain->dev_cnt > 0) |
3207 | cleanup_domain(domain); | |
3208 | ||
3209 | BUG_ON(domain->dev_cnt != 0); | |
3210 | ||
132bd68f JR |
3211 | if (domain->mode != PAGE_MODE_NONE) |
3212 | free_pagetable(domain); | |
98383fc3 | 3213 | |
52815b75 JR |
3214 | if (domain->flags & PD_IOMMUV2_MASK) |
3215 | free_gcr3_table(domain); | |
3216 | ||
8b408fe4 | 3217 | protection_domain_free(domain); |
98383fc3 JR |
3218 | } |
3219 | ||
684f2888 JR |
3220 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3221 | struct device *dev) | |
3222 | { | |
657cbb6b | 3223 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3224 | struct amd_iommu *iommu; |
7aba6cb9 | 3225 | int devid; |
684f2888 | 3226 | |
98fc5a69 | 3227 | if (!check_device(dev)) |
684f2888 JR |
3228 | return; |
3229 | ||
98fc5a69 | 3230 | devid = get_device_id(dev); |
9ee35e4c | 3231 | if (devid < 0) |
7aba6cb9 | 3232 | return; |
684f2888 | 3233 | |
657cbb6b | 3234 | if (dev_data->domain != NULL) |
15898bbc | 3235 | detach_device(dev); |
684f2888 JR |
3236 | |
3237 | iommu = amd_iommu_rlookup_table[devid]; | |
3238 | if (!iommu) | |
3239 | return; | |
3240 | ||
684f2888 JR |
3241 | iommu_completion_wait(iommu); |
3242 | } | |
3243 | ||
01106066 JR |
3244 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3245 | struct device *dev) | |
3246 | { | |
3f4b87b9 | 3247 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3248 | struct iommu_dev_data *dev_data; |
01106066 | 3249 | struct amd_iommu *iommu; |
15898bbc | 3250 | int ret; |
01106066 | 3251 | |
98fc5a69 | 3252 | if (!check_device(dev)) |
01106066 JR |
3253 | return -EINVAL; |
3254 | ||
657cbb6b JR |
3255 | dev_data = dev->archdata.iommu; |
3256 | ||
f62dda66 | 3257 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3258 | if (!iommu) |
3259 | return -EINVAL; | |
3260 | ||
657cbb6b | 3261 | if (dev_data->domain) |
15898bbc | 3262 | detach_device(dev); |
01106066 | 3263 | |
15898bbc | 3264 | ret = attach_device(dev, domain); |
01106066 JR |
3265 | |
3266 | iommu_completion_wait(iommu); | |
3267 | ||
15898bbc | 3268 | return ret; |
01106066 JR |
3269 | } |
3270 | ||
468e2366 | 3271 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3272 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3273 | { |
3f4b87b9 | 3274 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3275 | int prot = 0; |
3276 | int ret; | |
3277 | ||
132bd68f JR |
3278 | if (domain->mode == PAGE_MODE_NONE) |
3279 | return -EINVAL; | |
3280 | ||
c6229ca6 JR |
3281 | if (iommu_prot & IOMMU_READ) |
3282 | prot |= IOMMU_PROT_IR; | |
3283 | if (iommu_prot & IOMMU_WRITE) | |
3284 | prot |= IOMMU_PROT_IW; | |
3285 | ||
5d214fe6 | 3286 | mutex_lock(&domain->api_lock); |
b911b89b | 3287 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3288 | mutex_unlock(&domain->api_lock); |
3289 | ||
795e74f7 | 3290 | return ret; |
c6229ca6 JR |
3291 | } |
3292 | ||
5009065d OBC |
3293 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3294 | size_t page_size) | |
eb74ff6c | 3295 | { |
3f4b87b9 | 3296 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3297 | size_t unmap_size; |
eb74ff6c | 3298 | |
132bd68f JR |
3299 | if (domain->mode == PAGE_MODE_NONE) |
3300 | return -EINVAL; | |
3301 | ||
5d214fe6 | 3302 | mutex_lock(&domain->api_lock); |
468e2366 | 3303 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3304 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3305 | |
17b124bf | 3306 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3307 | |
5009065d | 3308 | return unmap_size; |
eb74ff6c JR |
3309 | } |
3310 | ||
645c4c8d | 3311 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3312 | dma_addr_t iova) |
645c4c8d | 3313 | { |
3f4b87b9 | 3314 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3315 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3316 | u64 *pte, __pte; |
645c4c8d | 3317 | |
132bd68f JR |
3318 | if (domain->mode == PAGE_MODE_NONE) |
3319 | return iova; | |
3320 | ||
3039ca1b | 3321 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3322 | |
a6d41a40 | 3323 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3324 | return 0; |
3325 | ||
b24b1b63 JR |
3326 | offset_mask = pte_pgsize - 1; |
3327 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3328 | |
b24b1b63 | 3329 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3330 | } |
3331 | ||
ab636481 | 3332 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3333 | { |
80a506b8 JR |
3334 | switch (cap) { |
3335 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3336 | return true; |
bdddadcb | 3337 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3338 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3339 | case IOMMU_CAP_NOEXEC: |
3340 | return false; | |
80a506b8 JR |
3341 | } |
3342 | ||
ab636481 | 3343 | return false; |
dbb9fd86 SY |
3344 | } |
3345 | ||
35cf248f JR |
3346 | static void amd_iommu_get_dm_regions(struct device *dev, |
3347 | struct list_head *head) | |
3348 | { | |
3349 | struct unity_map_entry *entry; | |
7aba6cb9 | 3350 | int devid; |
35cf248f JR |
3351 | |
3352 | devid = get_device_id(dev); | |
9ee35e4c | 3353 | if (devid < 0) |
7aba6cb9 | 3354 | return; |
35cf248f JR |
3355 | |
3356 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3357 | struct iommu_dm_region *region; | |
3358 | ||
3359 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3360 | continue; | |
3361 | ||
3362 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3363 | if (!region) { | |
3364 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3365 | dev_name(dev)); | |
3366 | return; | |
3367 | } | |
3368 | ||
3369 | region->start = entry->address_start; | |
3370 | region->length = entry->address_end - entry->address_start; | |
3371 | if (entry->prot & IOMMU_PROT_IR) | |
3372 | region->prot |= IOMMU_READ; | |
3373 | if (entry->prot & IOMMU_PROT_IW) | |
3374 | region->prot |= IOMMU_WRITE; | |
3375 | ||
3376 | list_add_tail(®ion->list, head); | |
3377 | } | |
3378 | } | |
3379 | ||
3380 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3381 | struct list_head *head) | |
3382 | { | |
3383 | struct iommu_dm_region *entry, *next; | |
3384 | ||
3385 | list_for_each_entry_safe(entry, next, head, list) | |
3386 | kfree(entry); | |
3387 | } | |
3388 | ||
8d54d6c8 JR |
3389 | static void amd_iommu_apply_dm_region(struct device *dev, |
3390 | struct iommu_domain *domain, | |
3391 | struct iommu_dm_region *region) | |
3392 | { | |
3393 | struct protection_domain *pdomain = to_pdomain(domain); | |
3394 | struct dma_ops_domain *dma_dom = pdomain->priv; | |
3395 | unsigned long start, end; | |
3396 | ||
3397 | start = IOVA_PFN(region->start); | |
3398 | end = IOVA_PFN(region->start + region->length); | |
3399 | ||
3400 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3401 | } | |
3402 | ||
b22f6434 | 3403 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3404 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3405 | .domain_alloc = amd_iommu_domain_alloc, |
3406 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3407 | .attach_dev = amd_iommu_attach_device, |
3408 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3409 | .map = amd_iommu_map, |
3410 | .unmap = amd_iommu_unmap, | |
315786eb | 3411 | .map_sg = default_iommu_map_sg, |
26961efe | 3412 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3413 | .add_device = amd_iommu_add_device, |
3414 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3415 | .device_group = amd_iommu_device_group, |
35cf248f JR |
3416 | .get_dm_regions = amd_iommu_get_dm_regions, |
3417 | .put_dm_regions = amd_iommu_put_dm_regions, | |
8d54d6c8 | 3418 | .apply_dm_region = amd_iommu_apply_dm_region, |
aa3de9c0 | 3419 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3420 | }; |
3421 | ||
0feae533 JR |
3422 | /***************************************************************************** |
3423 | * | |
3424 | * The next functions do a basic initialization of IOMMU for pass through | |
3425 | * mode | |
3426 | * | |
3427 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3428 | * DMA-API translation. | |
3429 | * | |
3430 | *****************************************************************************/ | |
3431 | ||
72e1dcc4 JR |
3432 | /* IOMMUv2 specific functions */ |
3433 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3434 | { | |
3435 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3436 | } | |
3437 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3438 | ||
3439 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3440 | { | |
3441 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3442 | } | |
3443 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3444 | |
3445 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3446 | { | |
3f4b87b9 | 3447 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3448 | unsigned long flags; |
3449 | ||
3450 | spin_lock_irqsave(&domain->lock, flags); | |
3451 | ||
3452 | /* Update data structure */ | |
3453 | domain->mode = PAGE_MODE_NONE; | |
3454 | domain->updated = true; | |
3455 | ||
3456 | /* Make changes visible to IOMMUs */ | |
3457 | update_domain(domain); | |
3458 | ||
3459 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3460 | free_pagetable(domain); | |
3461 | ||
3462 | spin_unlock_irqrestore(&domain->lock, flags); | |
3463 | } | |
3464 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3465 | |
3466 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3467 | { | |
3f4b87b9 | 3468 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3469 | unsigned long flags; |
3470 | int levels, ret; | |
3471 | ||
3472 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3473 | return -EINVAL; | |
3474 | ||
3475 | /* Number of GCR3 table levels required */ | |
3476 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3477 | levels += 1; | |
3478 | ||
3479 | if (levels > amd_iommu_max_glx_val) | |
3480 | return -EINVAL; | |
3481 | ||
3482 | spin_lock_irqsave(&domain->lock, flags); | |
3483 | ||
3484 | /* | |
3485 | * Save us all sanity checks whether devices already in the | |
3486 | * domain support IOMMUv2. Just force that the domain has no | |
3487 | * devices attached when it is switched into IOMMUv2 mode. | |
3488 | */ | |
3489 | ret = -EBUSY; | |
3490 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3491 | goto out; | |
3492 | ||
3493 | ret = -ENOMEM; | |
3494 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3495 | if (domain->gcr3_tbl == NULL) | |
3496 | goto out; | |
3497 | ||
3498 | domain->glx = levels; | |
3499 | domain->flags |= PD_IOMMUV2_MASK; | |
3500 | domain->updated = true; | |
3501 | ||
3502 | update_domain(domain); | |
3503 | ||
3504 | ret = 0; | |
3505 | ||
3506 | out: | |
3507 | spin_unlock_irqrestore(&domain->lock, flags); | |
3508 | ||
3509 | return ret; | |
3510 | } | |
3511 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3512 | |
3513 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3514 | u64 address, bool size) | |
3515 | { | |
3516 | struct iommu_dev_data *dev_data; | |
3517 | struct iommu_cmd cmd; | |
3518 | int i, ret; | |
3519 | ||
3520 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3521 | return -EINVAL; | |
3522 | ||
3523 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3524 | ||
3525 | /* | |
3526 | * IOMMU TLB needs to be flushed before Device TLB to | |
3527 | * prevent device TLB refill from IOMMU TLB | |
3528 | */ | |
3529 | for (i = 0; i < amd_iommus_present; ++i) { | |
3530 | if (domain->dev_iommu[i] == 0) | |
3531 | continue; | |
3532 | ||
3533 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3534 | if (ret != 0) | |
3535 | goto out; | |
3536 | } | |
3537 | ||
3538 | /* Wait until IOMMU TLB flushes are complete */ | |
3539 | domain_flush_complete(domain); | |
3540 | ||
3541 | /* Now flush device TLBs */ | |
3542 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3543 | struct amd_iommu *iommu; | |
3544 | int qdep; | |
3545 | ||
1c1cc454 JR |
3546 | /* |
3547 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3548 | * domain. | |
3549 | */ | |
3550 | if (!dev_data->ats.enabled) | |
3551 | continue; | |
22e266c7 JR |
3552 | |
3553 | qdep = dev_data->ats.qdep; | |
3554 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3555 | ||
3556 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3557 | qdep, address, size); | |
3558 | ||
3559 | ret = iommu_queue_command(iommu, &cmd); | |
3560 | if (ret != 0) | |
3561 | goto out; | |
3562 | } | |
3563 | ||
3564 | /* Wait until all device TLBs are flushed */ | |
3565 | domain_flush_complete(domain); | |
3566 | ||
3567 | ret = 0; | |
3568 | ||
3569 | out: | |
3570 | ||
3571 | return ret; | |
3572 | } | |
3573 | ||
3574 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3575 | u64 address) | |
3576 | { | |
3577 | return __flush_pasid(domain, pasid, address, false); | |
3578 | } | |
3579 | ||
3580 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3581 | u64 address) | |
3582 | { | |
3f4b87b9 | 3583 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3584 | unsigned long flags; |
3585 | int ret; | |
3586 | ||
3587 | spin_lock_irqsave(&domain->lock, flags); | |
3588 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3589 | spin_unlock_irqrestore(&domain->lock, flags); | |
3590 | ||
3591 | return ret; | |
3592 | } | |
3593 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3594 | ||
3595 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3596 | { | |
3597 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3598 | true); | |
3599 | } | |
3600 | ||
3601 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3602 | { | |
3f4b87b9 | 3603 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3604 | unsigned long flags; |
3605 | int ret; | |
3606 | ||
3607 | spin_lock_irqsave(&domain->lock, flags); | |
3608 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3609 | spin_unlock_irqrestore(&domain->lock, flags); | |
3610 | ||
3611 | return ret; | |
3612 | } | |
3613 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3614 | ||
b16137b1 JR |
3615 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3616 | { | |
3617 | int index; | |
3618 | u64 *pte; | |
3619 | ||
3620 | while (true) { | |
3621 | ||
3622 | index = (pasid >> (9 * level)) & 0x1ff; | |
3623 | pte = &root[index]; | |
3624 | ||
3625 | if (level == 0) | |
3626 | break; | |
3627 | ||
3628 | if (!(*pte & GCR3_VALID)) { | |
3629 | if (!alloc) | |
3630 | return NULL; | |
3631 | ||
3632 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3633 | if (root == NULL) | |
3634 | return NULL; | |
3635 | ||
3636 | *pte = __pa(root) | GCR3_VALID; | |
3637 | } | |
3638 | ||
3639 | root = __va(*pte & PAGE_MASK); | |
3640 | ||
3641 | level -= 1; | |
3642 | } | |
3643 | ||
3644 | return pte; | |
3645 | } | |
3646 | ||
3647 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3648 | unsigned long cr3) | |
3649 | { | |
3650 | u64 *pte; | |
3651 | ||
3652 | if (domain->mode != PAGE_MODE_NONE) | |
3653 | return -EINVAL; | |
3654 | ||
3655 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3656 | if (pte == NULL) | |
3657 | return -ENOMEM; | |
3658 | ||
3659 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3660 | ||
3661 | return __amd_iommu_flush_tlb(domain, pasid); | |
3662 | } | |
3663 | ||
3664 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3665 | { | |
3666 | u64 *pte; | |
3667 | ||
3668 | if (domain->mode != PAGE_MODE_NONE) | |
3669 | return -EINVAL; | |
3670 | ||
3671 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3672 | if (pte == NULL) | |
3673 | return 0; | |
3674 | ||
3675 | *pte = 0; | |
3676 | ||
3677 | return __amd_iommu_flush_tlb(domain, pasid); | |
3678 | } | |
3679 | ||
3680 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3681 | unsigned long cr3) | |
3682 | { | |
3f4b87b9 | 3683 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3684 | unsigned long flags; |
3685 | int ret; | |
3686 | ||
3687 | spin_lock_irqsave(&domain->lock, flags); | |
3688 | ret = __set_gcr3(domain, pasid, cr3); | |
3689 | spin_unlock_irqrestore(&domain->lock, flags); | |
3690 | ||
3691 | return ret; | |
3692 | } | |
3693 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3694 | ||
3695 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3696 | { | |
3f4b87b9 | 3697 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3698 | unsigned long flags; |
3699 | int ret; | |
3700 | ||
3701 | spin_lock_irqsave(&domain->lock, flags); | |
3702 | ret = __clear_gcr3(domain, pasid); | |
3703 | spin_unlock_irqrestore(&domain->lock, flags); | |
3704 | ||
3705 | return ret; | |
3706 | } | |
3707 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3708 | |
3709 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3710 | int status, int tag) | |
3711 | { | |
3712 | struct iommu_dev_data *dev_data; | |
3713 | struct amd_iommu *iommu; | |
3714 | struct iommu_cmd cmd; | |
3715 | ||
3716 | dev_data = get_dev_data(&pdev->dev); | |
3717 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3718 | ||
3719 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3720 | tag, dev_data->pri_tlp); | |
3721 | ||
3722 | return iommu_queue_command(iommu, &cmd); | |
3723 | } | |
3724 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3725 | |
3726 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3727 | { | |
3f4b87b9 | 3728 | struct protection_domain *pdomain; |
f3572db8 | 3729 | |
3f4b87b9 JR |
3730 | pdomain = get_domain(&pdev->dev); |
3731 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3732 | return NULL; |
3733 | ||
3734 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3735 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3736 | return NULL; |
3737 | ||
3f4b87b9 | 3738 | return &pdomain->domain; |
f3572db8 JR |
3739 | } |
3740 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3741 | |
3742 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3743 | { | |
3744 | struct iommu_dev_data *dev_data; | |
3745 | ||
3746 | if (!amd_iommu_v2_supported()) | |
3747 | return; | |
3748 | ||
3749 | dev_data = get_dev_data(&pdev->dev); | |
3750 | dev_data->errata |= (1 << erratum); | |
3751 | } | |
3752 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3753 | |
3754 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3755 | struct amd_iommu_device_info *info) | |
3756 | { | |
3757 | int max_pasids; | |
3758 | int pos; | |
3759 | ||
3760 | if (pdev == NULL || info == NULL) | |
3761 | return -EINVAL; | |
3762 | ||
3763 | if (!amd_iommu_v2_supported()) | |
3764 | return -EINVAL; | |
3765 | ||
3766 | memset(info, 0, sizeof(*info)); | |
3767 | ||
3768 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3769 | if (pos) | |
3770 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3771 | ||
3772 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3773 | if (pos) | |
3774 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3775 | ||
3776 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3777 | if (pos) { | |
3778 | int features; | |
3779 | ||
3780 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3781 | max_pasids = min(max_pasids, (1 << 20)); | |
3782 | ||
3783 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3784 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3785 | ||
3786 | features = pci_pasid_features(pdev); | |
3787 | if (features & PCI_PASID_CAP_EXEC) | |
3788 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3789 | if (features & PCI_PASID_CAP_PRIV) | |
3790 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3791 | } | |
3792 | ||
3793 | return 0; | |
3794 | } | |
3795 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3796 | |
3797 | #ifdef CONFIG_IRQ_REMAP | |
3798 | ||
3799 | /***************************************************************************** | |
3800 | * | |
3801 | * Interrupt Remapping Implementation | |
3802 | * | |
3803 | *****************************************************************************/ | |
3804 | ||
3805 | union irte { | |
3806 | u32 val; | |
3807 | struct { | |
3808 | u32 valid : 1, | |
3809 | no_fault : 1, | |
3810 | int_type : 3, | |
3811 | rq_eoi : 1, | |
3812 | dm : 1, | |
3813 | rsvd_1 : 1, | |
3814 | destination : 8, | |
3815 | vector : 8, | |
3816 | rsvd_2 : 8; | |
3817 | } fields; | |
3818 | }; | |
3819 | ||
9c724966 JL |
3820 | struct irq_2_irte { |
3821 | u16 devid; /* Device ID for IRTE table */ | |
3822 | u16 index; /* Index into IRTE table*/ | |
3823 | }; | |
3824 | ||
7c71d306 JL |
3825 | struct amd_ir_data { |
3826 | struct irq_2_irte irq_2_irte; | |
3827 | union irte irte_entry; | |
3828 | union { | |
3829 | struct msi_msg msi_entry; | |
3830 | }; | |
3831 | }; | |
3832 | ||
3833 | static struct irq_chip amd_ir_chip; | |
3834 | ||
2b324506 JR |
3835 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3836 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3837 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3838 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3839 | ||
3840 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3841 | { | |
3842 | u64 dte; | |
3843 | ||
3844 | dte = amd_iommu_dev_table[devid].data[2]; | |
3845 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3846 | dte |= virt_to_phys(table->table); | |
3847 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3848 | dte |= DTE_IRQ_TABLE_LEN; | |
3849 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3850 | ||
3851 | amd_iommu_dev_table[devid].data[2] = dte; | |
3852 | } | |
3853 | ||
3854 | #define IRTE_ALLOCATED (~1U) | |
3855 | ||
3856 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3857 | { | |
3858 | struct irq_remap_table *table = NULL; | |
3859 | struct amd_iommu *iommu; | |
3860 | unsigned long flags; | |
3861 | u16 alias; | |
3862 | ||
3863 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3864 | ||
3865 | iommu = amd_iommu_rlookup_table[devid]; | |
3866 | if (!iommu) | |
3867 | goto out_unlock; | |
3868 | ||
3869 | table = irq_lookup_table[devid]; | |
3870 | if (table) | |
3871 | goto out; | |
3872 | ||
3873 | alias = amd_iommu_alias_table[devid]; | |
3874 | table = irq_lookup_table[alias]; | |
3875 | if (table) { | |
3876 | irq_lookup_table[devid] = table; | |
3877 | set_dte_irq_entry(devid, table); | |
3878 | iommu_flush_dte(iommu, devid); | |
3879 | goto out; | |
3880 | } | |
3881 | ||
3882 | /* Nothing there yet, allocate new irq remapping table */ | |
3883 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3884 | if (!table) | |
3885 | goto out; | |
3886 | ||
197887f0 JR |
3887 | /* Initialize table spin-lock */ |
3888 | spin_lock_init(&table->lock); | |
3889 | ||
2b324506 JR |
3890 | if (ioapic) |
3891 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3892 | table->min_index = 32; | |
3893 | ||
3894 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3895 | if (!table->table) { | |
3896 | kfree(table); | |
821f0f68 | 3897 | table = NULL; |
2b324506 JR |
3898 | goto out; |
3899 | } | |
3900 | ||
3901 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3902 | ||
3903 | if (ioapic) { | |
3904 | int i; | |
3905 | ||
3906 | for (i = 0; i < 32; ++i) | |
3907 | table->table[i] = IRTE_ALLOCATED; | |
3908 | } | |
3909 | ||
3910 | irq_lookup_table[devid] = table; | |
3911 | set_dte_irq_entry(devid, table); | |
3912 | iommu_flush_dte(iommu, devid); | |
3913 | if (devid != alias) { | |
3914 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3915 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3916 | iommu_flush_dte(iommu, alias); |
3917 | } | |
3918 | ||
3919 | out: | |
3920 | iommu_completion_wait(iommu); | |
3921 | ||
3922 | out_unlock: | |
3923 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3924 | ||
3925 | return table; | |
3926 | } | |
3927 | ||
3c3d4f90 | 3928 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3929 | { |
3930 | struct irq_remap_table *table; | |
3931 | unsigned long flags; | |
3932 | int index, c; | |
3933 | ||
3934 | table = get_irq_table(devid, false); | |
3935 | if (!table) | |
3936 | return -ENODEV; | |
3937 | ||
3938 | spin_lock_irqsave(&table->lock, flags); | |
3939 | ||
3940 | /* Scan table for free entries */ | |
3941 | for (c = 0, index = table->min_index; | |
3942 | index < MAX_IRQS_PER_TABLE; | |
3943 | ++index) { | |
3944 | if (table->table[index] == 0) | |
3945 | c += 1; | |
3946 | else | |
3947 | c = 0; | |
3948 | ||
3949 | if (c == count) { | |
2b324506 JR |
3950 | for (; c != 0; --c) |
3951 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3952 | ||
3953 | index -= count - 1; | |
2b324506 JR |
3954 | goto out; |
3955 | } | |
3956 | } | |
3957 | ||
3958 | index = -ENOSPC; | |
3959 | ||
3960 | out: | |
3961 | spin_unlock_irqrestore(&table->lock, flags); | |
3962 | ||
3963 | return index; | |
3964 | } | |
3965 | ||
2b324506 JR |
3966 | static int modify_irte(u16 devid, int index, union irte irte) |
3967 | { | |
3968 | struct irq_remap_table *table; | |
3969 | struct amd_iommu *iommu; | |
3970 | unsigned long flags; | |
3971 | ||
3972 | iommu = amd_iommu_rlookup_table[devid]; | |
3973 | if (iommu == NULL) | |
3974 | return -EINVAL; | |
3975 | ||
3976 | table = get_irq_table(devid, false); | |
3977 | if (!table) | |
3978 | return -ENOMEM; | |
3979 | ||
3980 | spin_lock_irqsave(&table->lock, flags); | |
3981 | table->table[index] = irte.val; | |
3982 | spin_unlock_irqrestore(&table->lock, flags); | |
3983 | ||
3984 | iommu_flush_irt(iommu, devid); | |
3985 | iommu_completion_wait(iommu); | |
3986 | ||
3987 | return 0; | |
3988 | } | |
3989 | ||
3990 | static void free_irte(u16 devid, int index) | |
3991 | { | |
3992 | struct irq_remap_table *table; | |
3993 | struct amd_iommu *iommu; | |
3994 | unsigned long flags; | |
3995 | ||
3996 | iommu = amd_iommu_rlookup_table[devid]; | |
3997 | if (iommu == NULL) | |
3998 | return; | |
3999 | ||
4000 | table = get_irq_table(devid, false); | |
4001 | if (!table) | |
4002 | return; | |
4003 | ||
4004 | spin_lock_irqsave(&table->lock, flags); | |
4005 | table->table[index] = 0; | |
4006 | spin_unlock_irqrestore(&table->lock, flags); | |
4007 | ||
4008 | iommu_flush_irt(iommu, devid); | |
4009 | iommu_completion_wait(iommu); | |
4010 | } | |
4011 | ||
7c71d306 | 4012 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 4013 | { |
7c71d306 | 4014 | int devid = -1; |
5527de74 | 4015 | |
7c71d306 JL |
4016 | switch (info->type) { |
4017 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4018 | devid = get_ioapic_devid(info->ioapic_id); | |
4019 | break; | |
4020 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4021 | devid = get_hpet_devid(info->hpet_id); | |
4022 | break; | |
4023 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4024 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4025 | devid = get_device_id(&info->msi_dev->dev); | |
4026 | break; | |
4027 | default: | |
4028 | BUG_ON(1); | |
4029 | break; | |
4030 | } | |
5527de74 | 4031 | |
7c71d306 JL |
4032 | return devid; |
4033 | } | |
5527de74 | 4034 | |
7c71d306 JL |
4035 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4036 | { | |
4037 | struct amd_iommu *iommu; | |
4038 | int devid; | |
5527de74 | 4039 | |
7c71d306 JL |
4040 | if (!info) |
4041 | return NULL; | |
5527de74 | 4042 | |
7c71d306 JL |
4043 | devid = get_devid(info); |
4044 | if (devid >= 0) { | |
4045 | iommu = amd_iommu_rlookup_table[devid]; | |
4046 | if (iommu) | |
4047 | return iommu->ir_domain; | |
4048 | } | |
5527de74 | 4049 | |
7c71d306 | 4050 | return NULL; |
5527de74 JR |
4051 | } |
4052 | ||
7c71d306 | 4053 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4054 | { |
7c71d306 JL |
4055 | struct amd_iommu *iommu; |
4056 | int devid; | |
5527de74 | 4057 | |
7c71d306 JL |
4058 | if (!info) |
4059 | return NULL; | |
5527de74 | 4060 | |
7c71d306 JL |
4061 | switch (info->type) { |
4062 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4063 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4064 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 4065 | if (devid < 0) |
7aba6cb9 WZ |
4066 | return NULL; |
4067 | ||
1fb260bc DC |
4068 | iommu = amd_iommu_rlookup_table[devid]; |
4069 | if (iommu) | |
4070 | return iommu->msi_domain; | |
7c71d306 JL |
4071 | break; |
4072 | default: | |
4073 | break; | |
4074 | } | |
5527de74 | 4075 | |
7c71d306 JL |
4076 | return NULL; |
4077 | } | |
5527de74 | 4078 | |
6b474b82 | 4079 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4080 | .prepare = amd_iommu_prepare, |
4081 | .enable = amd_iommu_enable, | |
4082 | .disable = amd_iommu_disable, | |
4083 | .reenable = amd_iommu_reenable, | |
4084 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4085 | .get_ir_irq_domain = get_ir_irq_domain, |
4086 | .get_irq_domain = get_irq_domain, | |
4087 | }; | |
5527de74 | 4088 | |
7c71d306 JL |
4089 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4090 | struct irq_cfg *irq_cfg, | |
4091 | struct irq_alloc_info *info, | |
4092 | int devid, int index, int sub_handle) | |
4093 | { | |
4094 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4095 | struct msi_msg *msg = &data->msi_entry; | |
4096 | union irte *irte = &data->irte_entry; | |
4097 | struct IO_APIC_route_entry *entry; | |
5527de74 | 4098 | |
7c71d306 JL |
4099 | data->irq_2_irte.devid = devid; |
4100 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 4101 | |
7c71d306 JL |
4102 | /* Setup IRTE for IOMMU */ |
4103 | irte->val = 0; | |
4104 | irte->fields.vector = irq_cfg->vector; | |
4105 | irte->fields.int_type = apic->irq_delivery_mode; | |
4106 | irte->fields.destination = irq_cfg->dest_apicid; | |
4107 | irte->fields.dm = apic->irq_dest_mode; | |
4108 | irte->fields.valid = 1; | |
4109 | ||
4110 | switch (info->type) { | |
4111 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4112 | /* Setup IOAPIC entry */ | |
4113 | entry = info->ioapic_entry; | |
4114 | info->ioapic_entry = NULL; | |
4115 | memset(entry, 0, sizeof(*entry)); | |
4116 | entry->vector = index; | |
4117 | entry->mask = 0; | |
4118 | entry->trigger = info->ioapic_trigger; | |
4119 | entry->polarity = info->ioapic_polarity; | |
4120 | /* Mask level triggered irqs. */ | |
4121 | if (info->ioapic_trigger) | |
4122 | entry->mask = 1; | |
4123 | break; | |
5527de74 | 4124 | |
7c71d306 JL |
4125 | case X86_IRQ_ALLOC_TYPE_HPET: |
4126 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4127 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4128 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4129 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4130 | msg->data = irte_info->index; | |
4131 | break; | |
5527de74 | 4132 | |
7c71d306 JL |
4133 | default: |
4134 | BUG_ON(1); | |
4135 | break; | |
4136 | } | |
5527de74 JR |
4137 | } |
4138 | ||
7c71d306 JL |
4139 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4140 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4141 | { |
7c71d306 JL |
4142 | struct irq_alloc_info *info = arg; |
4143 | struct irq_data *irq_data; | |
4144 | struct amd_ir_data *data; | |
5527de74 | 4145 | struct irq_cfg *cfg; |
7c71d306 JL |
4146 | int i, ret, devid; |
4147 | int index = -1; | |
5527de74 | 4148 | |
7c71d306 JL |
4149 | if (!info) |
4150 | return -EINVAL; | |
4151 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4152 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4153 | return -EINVAL; |
4154 | ||
7c71d306 JL |
4155 | /* |
4156 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4157 | * to support multiple MSI interrupts. | |
4158 | */ | |
4159 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4160 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4161 | |
7c71d306 JL |
4162 | devid = get_devid(info); |
4163 | if (devid < 0) | |
4164 | return -EINVAL; | |
5527de74 | 4165 | |
7c71d306 JL |
4166 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4167 | if (ret < 0) | |
4168 | return ret; | |
0b4d48cb | 4169 | |
7c71d306 JL |
4170 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4171 | if (get_irq_table(devid, true)) | |
4172 | index = info->ioapic_pin; | |
4173 | else | |
4174 | ret = -ENOMEM; | |
4175 | } else { | |
3c3d4f90 | 4176 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4177 | } |
4178 | if (index < 0) { | |
4179 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
4180 | goto out_free_parent; |
4181 | } | |
0b4d48cb | 4182 | |
7c71d306 JL |
4183 | for (i = 0; i < nr_irqs; i++) { |
4184 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4185 | cfg = irqd_cfg(irq_data); | |
4186 | if (!irq_data || !cfg) { | |
4187 | ret = -EINVAL; | |
4188 | goto out_free_data; | |
4189 | } | |
0b4d48cb | 4190 | |
a130e69f JR |
4191 | ret = -ENOMEM; |
4192 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4193 | if (!data) | |
4194 | goto out_free_data; | |
4195 | ||
7c71d306 JL |
4196 | irq_data->hwirq = (devid << 16) + i; |
4197 | irq_data->chip_data = data; | |
4198 | irq_data->chip = &amd_ir_chip; | |
4199 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4200 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4201 | } | |
a130e69f | 4202 | |
7c71d306 | 4203 | return 0; |
0b4d48cb | 4204 | |
7c71d306 JL |
4205 | out_free_data: |
4206 | for (i--; i >= 0; i--) { | |
4207 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4208 | if (irq_data) | |
4209 | kfree(irq_data->chip_data); | |
4210 | } | |
4211 | for (i = 0; i < nr_irqs; i++) | |
4212 | free_irte(devid, index + i); | |
4213 | out_free_parent: | |
4214 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4215 | return ret; | |
0b4d48cb JR |
4216 | } |
4217 | ||
7c71d306 JL |
4218 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4219 | unsigned int nr_irqs) | |
0b4d48cb | 4220 | { |
7c71d306 JL |
4221 | struct irq_2_irte *irte_info; |
4222 | struct irq_data *irq_data; | |
4223 | struct amd_ir_data *data; | |
4224 | int i; | |
0b4d48cb | 4225 | |
7c71d306 JL |
4226 | for (i = 0; i < nr_irqs; i++) { |
4227 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4228 | if (irq_data && irq_data->chip_data) { | |
4229 | data = irq_data->chip_data; | |
4230 | irte_info = &data->irq_2_irte; | |
4231 | free_irte(irte_info->devid, irte_info->index); | |
4232 | kfree(data); | |
4233 | } | |
4234 | } | |
4235 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4236 | } | |
0b4d48cb | 4237 | |
7c71d306 JL |
4238 | static void irq_remapping_activate(struct irq_domain *domain, |
4239 | struct irq_data *irq_data) | |
4240 | { | |
4241 | struct amd_ir_data *data = irq_data->chip_data; | |
4242 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4243 | |
7c71d306 | 4244 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4245 | } |
4246 | ||
7c71d306 JL |
4247 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4248 | struct irq_data *irq_data) | |
0b4d48cb | 4249 | { |
7c71d306 JL |
4250 | struct amd_ir_data *data = irq_data->chip_data; |
4251 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4252 | union irte entry; | |
0b4d48cb | 4253 | |
7c71d306 JL |
4254 | entry.val = 0; |
4255 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4256 | } | |
0b4d48cb | 4257 | |
7c71d306 JL |
4258 | static struct irq_domain_ops amd_ir_domain_ops = { |
4259 | .alloc = irq_remapping_alloc, | |
4260 | .free = irq_remapping_free, | |
4261 | .activate = irq_remapping_activate, | |
4262 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4263 | }; |
0b4d48cb | 4264 | |
7c71d306 JL |
4265 | static int amd_ir_set_affinity(struct irq_data *data, |
4266 | const struct cpumask *mask, bool force) | |
4267 | { | |
4268 | struct amd_ir_data *ir_data = data->chip_data; | |
4269 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4270 | struct irq_cfg *cfg = irqd_cfg(data); | |
4271 | struct irq_data *parent = data->parent_data; | |
4272 | int ret; | |
0b4d48cb | 4273 | |
7c71d306 JL |
4274 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4275 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4276 | return ret; | |
0b4d48cb | 4277 | |
7c71d306 JL |
4278 | /* |
4279 | * Atomically updates the IRTE with the new destination, vector | |
4280 | * and flushes the interrupt entry cache. | |
4281 | */ | |
4282 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4283 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4284 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4285 | |
7c71d306 JL |
4286 | /* |
4287 | * After this point, all the interrupts will start arriving | |
4288 | * at the new destination. So, time to cleanup the previous | |
4289 | * vector allocation. | |
4290 | */ | |
c6c2002b | 4291 | send_cleanup_vector(cfg); |
7c71d306 JL |
4292 | |
4293 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4294 | } |
4295 | ||
7c71d306 | 4296 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4297 | { |
7c71d306 | 4298 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4299 | |
7c71d306 JL |
4300 | *msg = ir_data->msi_entry; |
4301 | } | |
d976195c | 4302 | |
7c71d306 JL |
4303 | static struct irq_chip amd_ir_chip = { |
4304 | .irq_ack = ir_ack_apic_edge, | |
4305 | .irq_set_affinity = amd_ir_set_affinity, | |
4306 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4307 | }; | |
d976195c | 4308 | |
7c71d306 JL |
4309 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4310 | { | |
4311 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4312 | if (!iommu->ir_domain) | |
4313 | return -ENOMEM; | |
d976195c | 4314 | |
7c71d306 JL |
4315 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4316 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4317 | |
4318 | return 0; | |
4319 | } | |
2b324506 | 4320 | #endif |