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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 JR |
56 | |
57 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
58 | ||
815b33fd | 59 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 60 | |
307d5851 JR |
61 | /* IO virtual address start page frame number */ |
62 | #define IOVA_START_PFN (1) | |
63 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
64 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) | |
65 | ||
81cd07b9 JR |
66 | /* Reserved IOVA ranges */ |
67 | #define MSI_RANGE_START (0xfee00000) | |
68 | #define MSI_RANGE_END (0xfeefffff) | |
69 | #define HT_RANGE_START (0xfd00000000ULL) | |
70 | #define HT_RANGE_END (0xffffffffffULL) | |
71 | ||
aa3de9c0 OBC |
72 | /* |
73 | * This bitmap is used to advertise the page sizes our hardware support | |
74 | * to the IOMMU core, which will then use this information to split | |
75 | * physically contiguous memory regions it is mapping into page sizes | |
76 | * that we support. | |
77 | * | |
954e3dd8 | 78 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 79 | */ |
954e3dd8 | 80 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 81 | |
b6c02715 JR |
82 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
83 | ||
8fa5f802 JR |
84 | /* List of all available dev_data structures */ |
85 | static LIST_HEAD(dev_data_list); | |
86 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
87 | ||
6efed63b JR |
88 | LIST_HEAD(ioapic_map); |
89 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 90 | LIST_HEAD(acpihid_map); |
6efed63b | 91 | |
c5b5da9c JR |
92 | #define FLUSH_QUEUE_SIZE 256 |
93 | ||
94 | struct flush_queue_entry { | |
95 | unsigned long iova_pfn; | |
96 | unsigned long pages; | |
97 | struct dma_ops_domain *dma_dom; | |
98 | }; | |
99 | ||
100 | struct flush_queue { | |
101 | spinlock_t lock; | |
102 | unsigned next; | |
103 | struct flush_queue_entry *entries; | |
104 | }; | |
105 | ||
106 | DEFINE_PER_CPU(struct flush_queue, flush_queue); | |
107 | ||
bb279475 JR |
108 | static atomic_t queue_timer_on; |
109 | static struct timer_list queue_timer; | |
110 | ||
0feae533 JR |
111 | /* |
112 | * Domain for untranslated devices - only allocated | |
113 | * if iommu=pt passed on kernel cmd line. | |
114 | */ | |
b22f6434 | 115 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 116 | |
72e1dcc4 | 117 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 118 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 119 | |
ac1534a5 JR |
120 | static struct dma_map_ops amd_iommu_dma_ops; |
121 | ||
50917e26 JR |
122 | /* |
123 | * This struct contains device specific data for the IOMMU | |
124 | */ | |
125 | struct iommu_dev_data { | |
126 | struct list_head list; /* For domain->dev_list */ | |
127 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 128 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 | 129 | u16 devid; /* PCI Device ID */ |
e3156048 | 130 | u16 alias; /* Alias Device ID */ |
50917e26 | 131 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
1e6a7b04 | 132 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
133 | struct { |
134 | bool enabled; | |
135 | int qdep; | |
136 | } ats; /* ATS state */ | |
137 | bool pri_tlp; /* PASID TLB required for | |
138 | PPR completions */ | |
139 | u32 errata; /* Bitmap for errata to apply */ | |
140 | }; | |
141 | ||
431b2a20 JR |
142 | /* |
143 | * general struct to manage commands send to an IOMMU | |
144 | */ | |
d6449536 | 145 | struct iommu_cmd { |
b6c02715 JR |
146 | u32 data[4]; |
147 | }; | |
148 | ||
05152a04 JR |
149 | struct kmem_cache *amd_iommu_irq_cache; |
150 | ||
04bfdd84 | 151 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 152 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 153 | static void detach_device(struct device *dev); |
c1eee67b | 154 | |
007b74ba JR |
155 | /* |
156 | * Data container for a dma_ops specific protection domain | |
157 | */ | |
158 | struct dma_ops_domain { | |
159 | /* generic protection domain information */ | |
160 | struct protection_domain domain; | |
161 | ||
307d5851 JR |
162 | /* IOVA RB-Tree */ |
163 | struct iova_domain iovad; | |
007b74ba JR |
164 | }; |
165 | ||
81cd07b9 JR |
166 | static struct iova_domain reserved_iova_ranges; |
167 | static struct lock_class_key reserved_rbtree_key; | |
168 | ||
15898bbc JR |
169 | /**************************************************************************** |
170 | * | |
171 | * Helper functions | |
172 | * | |
173 | ****************************************************************************/ | |
174 | ||
2bf9a0a1 WZ |
175 | static inline int match_hid_uid(struct device *dev, |
176 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 177 | { |
2bf9a0a1 WZ |
178 | const char *hid, *uid; |
179 | ||
180 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
181 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
182 | ||
183 | if (!hid || !(*hid)) | |
184 | return -ENODEV; | |
185 | ||
186 | if (!uid || !(*uid)) | |
187 | return strcmp(hid, entry->hid); | |
188 | ||
189 | if (!(*entry->uid)) | |
190 | return strcmp(hid, entry->hid); | |
191 | ||
192 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
193 | } |
194 | ||
2bf9a0a1 | 195 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
196 | { |
197 | struct pci_dev *pdev = to_pci_dev(dev); | |
198 | ||
199 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
200 | } | |
201 | ||
2bf9a0a1 WZ |
202 | static inline int get_acpihid_device_id(struct device *dev, |
203 | struct acpihid_map_entry **entry) | |
204 | { | |
205 | struct acpihid_map_entry *p; | |
206 | ||
207 | list_for_each_entry(p, &acpihid_map, list) { | |
208 | if (!match_hid_uid(dev, p)) { | |
209 | if (entry) | |
210 | *entry = p; | |
211 | return p->devid; | |
212 | } | |
213 | } | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
217 | static inline int get_device_id(struct device *dev) | |
218 | { | |
219 | int devid; | |
220 | ||
221 | if (dev_is_pci(dev)) | |
222 | devid = get_pci_device_id(dev); | |
223 | else | |
224 | devid = get_acpihid_device_id(dev, NULL); | |
225 | ||
226 | return devid; | |
227 | } | |
228 | ||
3f4b87b9 JR |
229 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
230 | { | |
231 | return container_of(dom, struct protection_domain, domain); | |
232 | } | |
233 | ||
b3311b06 JR |
234 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
235 | { | |
236 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
237 | return container_of(domain, struct dma_ops_domain, domain); | |
238 | } | |
239 | ||
f62dda66 | 240 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
241 | { |
242 | struct iommu_dev_data *dev_data; | |
243 | unsigned long flags; | |
244 | ||
245 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
246 | if (!dev_data) | |
247 | return NULL; | |
248 | ||
f62dda66 | 249 | dev_data->devid = devid; |
8fa5f802 JR |
250 | |
251 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
252 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
253 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
254 | ||
255 | return dev_data; | |
256 | } | |
257 | ||
3b03bb74 JR |
258 | static struct iommu_dev_data *search_dev_data(u16 devid) |
259 | { | |
260 | struct iommu_dev_data *dev_data; | |
261 | unsigned long flags; | |
262 | ||
263 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
264 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
265 | if (dev_data->devid == devid) | |
266 | goto out_unlock; | |
267 | } | |
268 | ||
269 | dev_data = NULL; | |
270 | ||
271 | out_unlock: | |
272 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
273 | ||
274 | return dev_data; | |
275 | } | |
276 | ||
e3156048 JR |
277 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
278 | { | |
279 | *(u16 *)data = alias; | |
280 | return 0; | |
281 | } | |
282 | ||
283 | static u16 get_alias(struct device *dev) | |
284 | { | |
285 | struct pci_dev *pdev = to_pci_dev(dev); | |
286 | u16 devid, ivrs_alias, pci_alias; | |
287 | ||
6c0b43df | 288 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 JR |
289 | devid = get_device_id(dev); |
290 | ivrs_alias = amd_iommu_alias_table[devid]; | |
291 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
292 | ||
293 | if (ivrs_alias == pci_alias) | |
294 | return ivrs_alias; | |
295 | ||
296 | /* | |
297 | * DMA alias showdown | |
298 | * | |
299 | * The IVRS is fairly reliable in telling us about aliases, but it | |
300 | * can't know about every screwy device. If we don't have an IVRS | |
301 | * reported alias, use the PCI reported alias. In that case we may | |
302 | * still need to initialize the rlookup and dev_table entries if the | |
303 | * alias is to a non-existent device. | |
304 | */ | |
305 | if (ivrs_alias == devid) { | |
306 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
307 | amd_iommu_rlookup_table[pci_alias] = | |
308 | amd_iommu_rlookup_table[devid]; | |
309 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
310 | amd_iommu_dev_table[devid].data, | |
311 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
312 | } | |
313 | ||
314 | return pci_alias; | |
315 | } | |
316 | ||
317 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
318 | "for device %s[%04x:%04x], kernel reported alias " | |
319 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
320 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
321 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
322 | PCI_FUNC(pci_alias)); | |
323 | ||
324 | /* | |
325 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
326 | * bus, then the IVRS table may know about a quirk that we don't. | |
327 | */ | |
328 | if (pci_alias == devid && | |
329 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 330 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
331 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
332 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
333 | dev_name(dev)); | |
334 | } | |
335 | ||
336 | return ivrs_alias; | |
337 | } | |
338 | ||
3b03bb74 JR |
339 | static struct iommu_dev_data *find_dev_data(u16 devid) |
340 | { | |
341 | struct iommu_dev_data *dev_data; | |
342 | ||
343 | dev_data = search_dev_data(devid); | |
344 | ||
345 | if (dev_data == NULL) | |
346 | dev_data = alloc_dev_data(devid); | |
347 | ||
348 | return dev_data; | |
349 | } | |
350 | ||
657cbb6b JR |
351 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
352 | { | |
353 | return dev->archdata.iommu; | |
354 | } | |
355 | ||
b097d11a WZ |
356 | /* |
357 | * Find or create an IOMMU group for a acpihid device. | |
358 | */ | |
359 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 360 | { |
b097d11a | 361 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 362 | int devid; |
b097d11a WZ |
363 | |
364 | devid = get_acpihid_device_id(dev, &entry); | |
365 | if (devid < 0) | |
366 | return ERR_PTR(devid); | |
367 | ||
368 | list_for_each_entry(p, &acpihid_map, list) { | |
369 | if ((devid == p->devid) && p->group) | |
370 | entry->group = p->group; | |
371 | } | |
372 | ||
373 | if (!entry->group) | |
374 | entry->group = generic_device_group(dev); | |
375 | ||
376 | return entry->group; | |
657cbb6b JR |
377 | } |
378 | ||
5abcdba4 JR |
379 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
380 | { | |
381 | static const int caps[] = { | |
382 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
383 | PCI_EXT_CAP_ID_PRI, |
384 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
385 | }; |
386 | int i, pos; | |
387 | ||
388 | for (i = 0; i < 3; ++i) { | |
389 | pos = pci_find_ext_capability(pdev, caps[i]); | |
390 | if (pos == 0) | |
391 | return false; | |
392 | } | |
393 | ||
394 | return true; | |
395 | } | |
396 | ||
6a113ddc JR |
397 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
398 | { | |
399 | struct iommu_dev_data *dev_data; | |
400 | ||
401 | dev_data = get_dev_data(&pdev->dev); | |
402 | ||
403 | return dev_data->errata & (1 << erratum) ? true : false; | |
404 | } | |
405 | ||
98fc5a69 JR |
406 | /* |
407 | * This function checks if the driver got a valid device from the caller to | |
408 | * avoid dereferencing invalid pointers. | |
409 | */ | |
410 | static bool check_device(struct device *dev) | |
411 | { | |
7aba6cb9 | 412 | int devid; |
98fc5a69 JR |
413 | |
414 | if (!dev || !dev->dma_mask) | |
415 | return false; | |
416 | ||
98fc5a69 | 417 | devid = get_device_id(dev); |
9ee35e4c | 418 | if (devid < 0) |
7aba6cb9 | 419 | return false; |
98fc5a69 JR |
420 | |
421 | /* Out of our scope? */ | |
422 | if (devid > amd_iommu_last_bdf) | |
423 | return false; | |
424 | ||
425 | if (amd_iommu_rlookup_table[devid] == NULL) | |
426 | return false; | |
427 | ||
428 | return true; | |
429 | } | |
430 | ||
25b11ce2 | 431 | static void init_iommu_group(struct device *dev) |
2851db21 | 432 | { |
2851db21 | 433 | struct iommu_group *group; |
2851db21 | 434 | |
65d5352f | 435 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
436 | if (IS_ERR(group)) |
437 | return; | |
438 | ||
0bb6e243 | 439 | iommu_group_put(group); |
eb9c9527 AW |
440 | } |
441 | ||
442 | static int iommu_init_device(struct device *dev) | |
443 | { | |
eb9c9527 | 444 | struct iommu_dev_data *dev_data; |
7aba6cb9 | 445 | int devid; |
eb9c9527 AW |
446 | |
447 | if (dev->archdata.iommu) | |
448 | return 0; | |
449 | ||
7aba6cb9 | 450 | devid = get_device_id(dev); |
9ee35e4c | 451 | if (devid < 0) |
7aba6cb9 WZ |
452 | return devid; |
453 | ||
454 | dev_data = find_dev_data(devid); | |
eb9c9527 AW |
455 | if (!dev_data) |
456 | return -ENOMEM; | |
457 | ||
e3156048 JR |
458 | dev_data->alias = get_alias(dev); |
459 | ||
2bf9a0a1 | 460 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
461 | struct amd_iommu *iommu; |
462 | ||
2bf9a0a1 | 463 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
464 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
465 | } | |
466 | ||
657cbb6b JR |
467 | dev->archdata.iommu = dev_data; |
468 | ||
066f2e98 AW |
469 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
470 | dev); | |
471 | ||
657cbb6b JR |
472 | return 0; |
473 | } | |
474 | ||
26018874 JR |
475 | static void iommu_ignore_device(struct device *dev) |
476 | { | |
7aba6cb9 WZ |
477 | u16 alias; |
478 | int devid; | |
26018874 JR |
479 | |
480 | devid = get_device_id(dev); | |
9ee35e4c | 481 | if (devid < 0) |
7aba6cb9 WZ |
482 | return; |
483 | ||
e3156048 | 484 | alias = get_alias(dev); |
26018874 JR |
485 | |
486 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
487 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
488 | ||
489 | amd_iommu_rlookup_table[devid] = NULL; | |
490 | amd_iommu_rlookup_table[alias] = NULL; | |
491 | } | |
492 | ||
657cbb6b JR |
493 | static void iommu_uninit_device(struct device *dev) |
494 | { | |
7aba6cb9 WZ |
495 | int devid; |
496 | struct iommu_dev_data *dev_data; | |
c1931090 | 497 | |
7aba6cb9 | 498 | devid = get_device_id(dev); |
9ee35e4c | 499 | if (devid < 0) |
7aba6cb9 | 500 | return; |
c1931090 | 501 | |
7aba6cb9 | 502 | dev_data = search_dev_data(devid); |
c1931090 AW |
503 | if (!dev_data) |
504 | return; | |
505 | ||
b6809ee5 JR |
506 | if (dev_data->domain) |
507 | detach_device(dev); | |
508 | ||
066f2e98 AW |
509 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
510 | dev); | |
511 | ||
9dcd6130 AW |
512 | iommu_group_remove_device(dev); |
513 | ||
aafd8ba0 JR |
514 | /* Remove dma-ops */ |
515 | dev->archdata.dma_ops = NULL; | |
516 | ||
8fa5f802 | 517 | /* |
c1931090 AW |
518 | * We keep dev_data around for unplugged devices and reuse it when the |
519 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 520 | */ |
657cbb6b | 521 | } |
b7cc9554 | 522 | |
a80dc3e0 JR |
523 | /**************************************************************************** |
524 | * | |
525 | * Interrupt handling functions | |
526 | * | |
527 | ****************************************************************************/ | |
528 | ||
e3e59876 JR |
529 | static void dump_dte_entry(u16 devid) |
530 | { | |
531 | int i; | |
532 | ||
ee6c2868 JR |
533 | for (i = 0; i < 4; ++i) |
534 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
535 | amd_iommu_dev_table[devid].data[i]); |
536 | } | |
537 | ||
945b4ac4 JR |
538 | static void dump_command(unsigned long phys_addr) |
539 | { | |
540 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
541 | int i; | |
542 | ||
543 | for (i = 0; i < 4; ++i) | |
544 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
545 | } | |
546 | ||
a345b23b | 547 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 548 | { |
3d06fca8 JR |
549 | int type, devid, domid, flags; |
550 | volatile u32 *event = __evt; | |
551 | int count = 0; | |
552 | u64 address; | |
553 | ||
554 | retry: | |
555 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
556 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
557 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
558 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
559 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
560 | ||
561 | if (type == 0) { | |
562 | /* Did we hit the erratum? */ | |
563 | if (++count == LOOP_TIMEOUT) { | |
564 | pr_err("AMD-Vi: No event written to event log\n"); | |
565 | return; | |
566 | } | |
567 | udelay(1); | |
568 | goto retry; | |
569 | } | |
90008ee4 | 570 | |
4c6f40d4 | 571 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
572 | |
573 | switch (type) { | |
574 | case EVENT_TYPE_ILL_DEV: | |
575 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
576 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 577 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 578 | address, flags); |
e3e59876 | 579 | dump_dte_entry(devid); |
90008ee4 JR |
580 | break; |
581 | case EVENT_TYPE_IO_FAULT: | |
582 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
583 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 584 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
585 | domid, address, flags); |
586 | break; | |
587 | case EVENT_TYPE_DEV_TAB_ERR: | |
588 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
589 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 590 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
591 | address, flags); |
592 | break; | |
593 | case EVENT_TYPE_PAGE_TAB_ERR: | |
594 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
595 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 596 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
597 | domid, address, flags); |
598 | break; | |
599 | case EVENT_TYPE_ILL_CMD: | |
600 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 601 | dump_command(address); |
90008ee4 JR |
602 | break; |
603 | case EVENT_TYPE_CMD_HARD_ERR: | |
604 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
605 | "flags=0x%04x]\n", address, flags); | |
606 | break; | |
607 | case EVENT_TYPE_IOTLB_INV_TO: | |
608 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
609 | "address=0x%016llx]\n", | |
c5081cd7 | 610 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
611 | address); |
612 | break; | |
613 | case EVENT_TYPE_INV_DEV_REQ: | |
614 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
615 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 616 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
617 | address, flags); |
618 | break; | |
619 | default: | |
620 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
621 | } | |
3d06fca8 JR |
622 | |
623 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
624 | } |
625 | ||
626 | static void iommu_poll_events(struct amd_iommu *iommu) | |
627 | { | |
628 | u32 head, tail; | |
90008ee4 JR |
629 | |
630 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
631 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
632 | ||
633 | while (head != tail) { | |
a345b23b | 634 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 635 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
636 | } |
637 | ||
638 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
639 | } |
640 | ||
eee53537 | 641 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
642 | { |
643 | struct amd_iommu_fault fault; | |
72e1dcc4 | 644 | |
72e1dcc4 JR |
645 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
646 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
647 | return; | |
648 | } | |
649 | ||
650 | fault.address = raw[1]; | |
651 | fault.pasid = PPR_PASID(raw[0]); | |
652 | fault.device_id = PPR_DEVID(raw[0]); | |
653 | fault.tag = PPR_TAG(raw[0]); | |
654 | fault.flags = PPR_FLAGS(raw[0]); | |
655 | ||
72e1dcc4 JR |
656 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
657 | } | |
658 | ||
659 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
660 | { | |
72e1dcc4 JR |
661 | u32 head, tail; |
662 | ||
663 | if (iommu->ppr_log == NULL) | |
664 | return; | |
665 | ||
72e1dcc4 JR |
666 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
667 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
668 | ||
669 | while (head != tail) { | |
eee53537 JR |
670 | volatile u64 *raw; |
671 | u64 entry[2]; | |
672 | int i; | |
673 | ||
674 | raw = (u64 *)(iommu->ppr_log + head); | |
675 | ||
676 | /* | |
677 | * Hardware bug: Interrupt may arrive before the entry is | |
678 | * written to memory. If this happens we need to wait for the | |
679 | * entry to arrive. | |
680 | */ | |
681 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
682 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
683 | break; | |
684 | udelay(1); | |
685 | } | |
72e1dcc4 | 686 | |
eee53537 JR |
687 | /* Avoid memcpy function-call overhead */ |
688 | entry[0] = raw[0]; | |
689 | entry[1] = raw[1]; | |
72e1dcc4 | 690 | |
eee53537 JR |
691 | /* |
692 | * To detect the hardware bug we need to clear the entry | |
693 | * back to zero. | |
694 | */ | |
695 | raw[0] = raw[1] = 0UL; | |
696 | ||
697 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
698 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
699 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 700 | |
eee53537 JR |
701 | /* Handle PPR entry */ |
702 | iommu_handle_ppr_entry(iommu, entry); | |
703 | ||
eee53537 JR |
704 | /* Refresh ring-buffer information */ |
705 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
706 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
707 | } | |
72e1dcc4 JR |
708 | } |
709 | ||
bd6fcefc SS |
710 | #ifdef CONFIG_IRQ_REMAP |
711 | static int (*iommu_ga_log_notifier)(u32); | |
712 | ||
713 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
714 | { | |
715 | iommu_ga_log_notifier = notifier; | |
716 | ||
717 | return 0; | |
718 | } | |
719 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
720 | ||
721 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
722 | { | |
723 | u32 head, tail, cnt = 0; | |
724 | ||
725 | if (iommu->ga_log == NULL) | |
726 | return; | |
727 | ||
728 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
729 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
730 | ||
731 | while (head != tail) { | |
732 | volatile u64 *raw; | |
733 | u64 log_entry; | |
734 | ||
735 | raw = (u64 *)(iommu->ga_log + head); | |
736 | cnt++; | |
737 | ||
738 | /* Avoid memcpy function-call overhead */ | |
739 | log_entry = *raw; | |
740 | ||
741 | /* Update head pointer of hardware ring-buffer */ | |
742 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
743 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
744 | ||
745 | /* Handle GA entry */ | |
746 | switch (GA_REQ_TYPE(log_entry)) { | |
747 | case GA_GUEST_NR: | |
748 | if (!iommu_ga_log_notifier) | |
749 | break; | |
750 | ||
751 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", | |
752 | __func__, GA_DEVID(log_entry), | |
753 | GA_TAG(log_entry)); | |
754 | ||
755 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
756 | pr_err("AMD-Vi: GA log notifier failed.\n"); | |
757 | break; | |
758 | default: | |
759 | break; | |
760 | } | |
761 | } | |
762 | } | |
763 | #endif /* CONFIG_IRQ_REMAP */ | |
764 | ||
765 | #define AMD_IOMMU_INT_MASK \ | |
766 | (MMIO_STATUS_EVT_INT_MASK | \ | |
767 | MMIO_STATUS_PPR_INT_MASK | \ | |
768 | MMIO_STATUS_GALOG_INT_MASK) | |
769 | ||
72fe00f0 | 770 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 771 | { |
3f398bc7 SS |
772 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
773 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 774 | |
bd6fcefc SS |
775 | while (status & AMD_IOMMU_INT_MASK) { |
776 | /* Enable EVT and PPR and GA interrupts again */ | |
777 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 778 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 779 | |
3f398bc7 SS |
780 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
781 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
782 | iommu_poll_events(iommu); | |
783 | } | |
90008ee4 | 784 | |
3f398bc7 SS |
785 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
786 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
787 | iommu_poll_ppr_log(iommu); | |
788 | } | |
90008ee4 | 789 | |
bd6fcefc SS |
790 | #ifdef CONFIG_IRQ_REMAP |
791 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
792 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); | |
793 | iommu_poll_ga_log(iommu); | |
794 | } | |
795 | #endif | |
796 | ||
3f398bc7 SS |
797 | /* |
798 | * Hardware bug: ERBT1312 | |
799 | * When re-enabling interrupt (by writing 1 | |
800 | * to clear the bit), the hardware might also try to set | |
801 | * the interrupt bit in the event status register. | |
802 | * In this scenario, the bit will be set, and disable | |
803 | * subsequent interrupts. | |
804 | * | |
805 | * Workaround: The IOMMU driver should read back the | |
806 | * status register and check if the interrupt bits are cleared. | |
807 | * If not, driver will need to go through the interrupt handler | |
808 | * again and re-clear the bits | |
809 | */ | |
810 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
811 | } | |
90008ee4 | 812 | return IRQ_HANDLED; |
a80dc3e0 JR |
813 | } |
814 | ||
72fe00f0 JR |
815 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
816 | { | |
817 | return IRQ_WAKE_THREAD; | |
818 | } | |
819 | ||
431b2a20 JR |
820 | /**************************************************************************** |
821 | * | |
822 | * IOMMU command queuing functions | |
823 | * | |
824 | ****************************************************************************/ | |
825 | ||
ac0ea6e9 JR |
826 | static int wait_on_sem(volatile u64 *sem) |
827 | { | |
828 | int i = 0; | |
829 | ||
830 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
831 | udelay(1); | |
832 | i += 1; | |
833 | } | |
834 | ||
835 | if (i == LOOP_TIMEOUT) { | |
836 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
837 | return -EIO; | |
838 | } | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
844 | struct iommu_cmd *cmd, | |
845 | u32 tail) | |
a19ae1ec | 846 | { |
a19ae1ec JR |
847 | u8 *target; |
848 | ||
8a7c5ef3 | 849 | target = iommu->cmd_buf + tail; |
deba4bce | 850 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
851 | |
852 | /* Copy command to buffer */ | |
853 | memcpy(target, cmd, sizeof(*cmd)); | |
854 | ||
855 | /* Tell the IOMMU about it */ | |
a19ae1ec | 856 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 857 | } |
a19ae1ec | 858 | |
815b33fd | 859 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 860 | { |
815b33fd JR |
861 | WARN_ON(address & 0x7ULL); |
862 | ||
ded46737 | 863 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
864 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
865 | cmd->data[1] = upper_32_bits(__pa(address)); | |
866 | cmd->data[2] = 1; | |
ded46737 JR |
867 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
868 | } | |
869 | ||
94fe79e2 JR |
870 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
871 | { | |
872 | memset(cmd, 0, sizeof(*cmd)); | |
873 | cmd->data[0] = devid; | |
874 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
875 | } | |
876 | ||
11b6402c JR |
877 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
878 | size_t size, u16 domid, int pde) | |
879 | { | |
880 | u64 pages; | |
ae0cbbb1 | 881 | bool s; |
11b6402c JR |
882 | |
883 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 884 | s = false; |
11b6402c JR |
885 | |
886 | if (pages > 1) { | |
887 | /* | |
888 | * If we have to flush more than one page, flush all | |
889 | * TLB entries for this domain | |
890 | */ | |
891 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 892 | s = true; |
11b6402c JR |
893 | } |
894 | ||
895 | address &= PAGE_MASK; | |
896 | ||
897 | memset(cmd, 0, sizeof(*cmd)); | |
898 | cmd->data[1] |= domid; | |
899 | cmd->data[2] = lower_32_bits(address); | |
900 | cmd->data[3] = upper_32_bits(address); | |
901 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
902 | if (s) /* size bit - we flush more than one 4kb page */ | |
903 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 904 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
905 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
906 | } | |
907 | ||
cb41ed85 JR |
908 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
909 | u64 address, size_t size) | |
910 | { | |
911 | u64 pages; | |
ae0cbbb1 | 912 | bool s; |
cb41ed85 JR |
913 | |
914 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 915 | s = false; |
cb41ed85 JR |
916 | |
917 | if (pages > 1) { | |
918 | /* | |
919 | * If we have to flush more than one page, flush all | |
920 | * TLB entries for this domain | |
921 | */ | |
922 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 923 | s = true; |
cb41ed85 JR |
924 | } |
925 | ||
926 | address &= PAGE_MASK; | |
927 | ||
928 | memset(cmd, 0, sizeof(*cmd)); | |
929 | cmd->data[0] = devid; | |
930 | cmd->data[0] |= (qdep & 0xff) << 24; | |
931 | cmd->data[1] = devid; | |
932 | cmd->data[2] = lower_32_bits(address); | |
933 | cmd->data[3] = upper_32_bits(address); | |
934 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
935 | if (s) | |
936 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
937 | } | |
938 | ||
22e266c7 JR |
939 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
940 | u64 address, bool size) | |
941 | { | |
942 | memset(cmd, 0, sizeof(*cmd)); | |
943 | ||
944 | address &= ~(0xfffULL); | |
945 | ||
a919a018 | 946 | cmd->data[0] = pasid; |
22e266c7 JR |
947 | cmd->data[1] = domid; |
948 | cmd->data[2] = lower_32_bits(address); | |
949 | cmd->data[3] = upper_32_bits(address); | |
950 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
951 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
952 | if (size) | |
953 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
954 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
955 | } | |
956 | ||
957 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
958 | int qdep, u64 address, bool size) | |
959 | { | |
960 | memset(cmd, 0, sizeof(*cmd)); | |
961 | ||
962 | address &= ~(0xfffULL); | |
963 | ||
964 | cmd->data[0] = devid; | |
e8d2d82d | 965 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
966 | cmd->data[0] |= (qdep & 0xff) << 24; |
967 | cmd->data[1] = devid; | |
e8d2d82d | 968 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
969 | cmd->data[2] = lower_32_bits(address); |
970 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
971 | cmd->data[3] = upper_32_bits(address); | |
972 | if (size) | |
973 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
974 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
975 | } | |
976 | ||
c99afa25 JR |
977 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
978 | int status, int tag, bool gn) | |
979 | { | |
980 | memset(cmd, 0, sizeof(*cmd)); | |
981 | ||
982 | cmd->data[0] = devid; | |
983 | if (gn) { | |
a919a018 | 984 | cmd->data[1] = pasid; |
c99afa25 JR |
985 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
986 | } | |
987 | cmd->data[3] = tag & 0x1ff; | |
988 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
989 | ||
990 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
991 | } | |
992 | ||
58fc7f14 JR |
993 | static void build_inv_all(struct iommu_cmd *cmd) |
994 | { | |
995 | memset(cmd, 0, sizeof(*cmd)); | |
996 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
997 | } |
998 | ||
7ef2798d JR |
999 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1000 | { | |
1001 | memset(cmd, 0, sizeof(*cmd)); | |
1002 | cmd->data[0] = devid; | |
1003 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1004 | } | |
1005 | ||
431b2a20 | 1006 | /* |
431b2a20 | 1007 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1008 | * hardware about the new command. |
431b2a20 | 1009 | */ |
f1ca1512 JR |
1010 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
1011 | struct iommu_cmd *cmd, | |
1012 | bool sync) | |
a19ae1ec | 1013 | { |
ac0ea6e9 | 1014 | u32 left, tail, head, next_tail; |
a19ae1ec | 1015 | unsigned long flags; |
a19ae1ec | 1016 | |
ac0ea6e9 | 1017 | again: |
a19ae1ec | 1018 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 1019 | |
ac0ea6e9 JR |
1020 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
1021 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
1022 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
1023 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 1024 | |
ac0ea6e9 JR |
1025 | if (left <= 2) { |
1026 | struct iommu_cmd sync_cmd; | |
1027 | volatile u64 sem = 0; | |
1028 | int ret; | |
8d201968 | 1029 | |
ac0ea6e9 JR |
1030 | build_completion_wait(&sync_cmd, (u64)&sem); |
1031 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1032 | |
ac0ea6e9 JR |
1033 | spin_unlock_irqrestore(&iommu->lock, flags); |
1034 | ||
1035 | if ((ret = wait_on_sem(&sem)) != 0) | |
1036 | return ret; | |
1037 | ||
1038 | goto again; | |
8d201968 JR |
1039 | } |
1040 | ||
ac0ea6e9 JR |
1041 | copy_cmd_to_buffer(iommu, cmd, tail); |
1042 | ||
1043 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1044 | iommu->need_sync = sync; |
ac0ea6e9 | 1045 | |
a19ae1ec | 1046 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1047 | |
815b33fd | 1048 | return 0; |
8d201968 JR |
1049 | } |
1050 | ||
f1ca1512 JR |
1051 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1052 | { | |
1053 | return iommu_queue_command_sync(iommu, cmd, true); | |
1054 | } | |
1055 | ||
8d201968 JR |
1056 | /* |
1057 | * This function queues a completion wait command into the command | |
1058 | * buffer of an IOMMU | |
1059 | */ | |
a19ae1ec | 1060 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1061 | { |
1062 | struct iommu_cmd cmd; | |
815b33fd | 1063 | volatile u64 sem = 0; |
ac0ea6e9 | 1064 | int ret; |
8d201968 | 1065 | |
09ee17eb | 1066 | if (!iommu->need_sync) |
815b33fd | 1067 | return 0; |
09ee17eb | 1068 | |
815b33fd | 1069 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1070 | |
f1ca1512 | 1071 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1072 | if (ret) |
815b33fd | 1073 | return ret; |
8d201968 | 1074 | |
ac0ea6e9 | 1075 | return wait_on_sem(&sem); |
8d201968 JR |
1076 | } |
1077 | ||
d8c13085 | 1078 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1079 | { |
d8c13085 | 1080 | struct iommu_cmd cmd; |
a19ae1ec | 1081 | |
d8c13085 | 1082 | build_inv_dte(&cmd, devid); |
7e4f88da | 1083 | |
d8c13085 JR |
1084 | return iommu_queue_command(iommu, &cmd); |
1085 | } | |
09ee17eb | 1086 | |
7d0c5cc5 JR |
1087 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1088 | { | |
1089 | u32 devid; | |
09ee17eb | 1090 | |
7d0c5cc5 JR |
1091 | for (devid = 0; devid <= 0xffff; ++devid) |
1092 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1093 | |
7d0c5cc5 JR |
1094 | iommu_completion_wait(iommu); |
1095 | } | |
84df8175 | 1096 | |
7d0c5cc5 JR |
1097 | /* |
1098 | * This function uses heavy locking and may disable irqs for some time. But | |
1099 | * this is no issue because it is only called during resume. | |
1100 | */ | |
1101 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1102 | { | |
1103 | u32 dom_id; | |
a19ae1ec | 1104 | |
7d0c5cc5 JR |
1105 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1106 | struct iommu_cmd cmd; | |
1107 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1108 | dom_id, 1); | |
1109 | iommu_queue_command(iommu, &cmd); | |
1110 | } | |
8eed9833 | 1111 | |
7d0c5cc5 | 1112 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1113 | } |
1114 | ||
58fc7f14 | 1115 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1116 | { |
58fc7f14 | 1117 | struct iommu_cmd cmd; |
0518a3a4 | 1118 | |
58fc7f14 | 1119 | build_inv_all(&cmd); |
0518a3a4 | 1120 | |
58fc7f14 JR |
1121 | iommu_queue_command(iommu, &cmd); |
1122 | iommu_completion_wait(iommu); | |
1123 | } | |
1124 | ||
7ef2798d JR |
1125 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1126 | { | |
1127 | struct iommu_cmd cmd; | |
1128 | ||
1129 | build_inv_irt(&cmd, devid); | |
1130 | ||
1131 | iommu_queue_command(iommu, &cmd); | |
1132 | } | |
1133 | ||
1134 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1135 | { | |
1136 | u32 devid; | |
1137 | ||
1138 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1139 | iommu_flush_irt(iommu, devid); | |
1140 | ||
1141 | iommu_completion_wait(iommu); | |
1142 | } | |
1143 | ||
7d0c5cc5 JR |
1144 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1145 | { | |
58fc7f14 JR |
1146 | if (iommu_feature(iommu, FEATURE_IA)) { |
1147 | iommu_flush_all(iommu); | |
1148 | } else { | |
1149 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1150 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1151 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1152 | } |
1153 | } | |
1154 | ||
431b2a20 | 1155 | /* |
cb41ed85 | 1156 | * Command send function for flushing on-device TLB |
431b2a20 | 1157 | */ |
6c542047 JR |
1158 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1159 | u64 address, size_t size) | |
3fa43655 JR |
1160 | { |
1161 | struct amd_iommu *iommu; | |
b00d3bcf | 1162 | struct iommu_cmd cmd; |
cb41ed85 | 1163 | int qdep; |
3fa43655 | 1164 | |
ea61cddb JR |
1165 | qdep = dev_data->ats.qdep; |
1166 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1167 | |
ea61cddb | 1168 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1169 | |
1170 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1171 | } |
1172 | ||
431b2a20 | 1173 | /* |
431b2a20 | 1174 | * Command send function for invalidating a device table entry |
431b2a20 | 1175 | */ |
6c542047 | 1176 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1177 | { |
3fa43655 | 1178 | struct amd_iommu *iommu; |
e25bfb56 | 1179 | u16 alias; |
ee2fa743 | 1180 | int ret; |
a19ae1ec | 1181 | |
6c542047 | 1182 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1183 | alias = dev_data->alias; |
a19ae1ec | 1184 | |
f62dda66 | 1185 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1186 | if (!ret && alias != dev_data->devid) |
1187 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1188 | if (ret) |
1189 | return ret; | |
1190 | ||
ea61cddb | 1191 | if (dev_data->ats.enabled) |
6c542047 | 1192 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1193 | |
ee2fa743 | 1194 | return ret; |
a19ae1ec JR |
1195 | } |
1196 | ||
431b2a20 JR |
1197 | /* |
1198 | * TLB invalidation function which is called from the mapping functions. | |
1199 | * It invalidates a single PTE if the range to flush is within a single | |
1200 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1201 | */ | |
17b124bf JR |
1202 | static void __domain_flush_pages(struct protection_domain *domain, |
1203 | u64 address, size_t size, int pde) | |
a19ae1ec | 1204 | { |
cb41ed85 | 1205 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1206 | struct iommu_cmd cmd; |
1207 | int ret = 0, i; | |
a19ae1ec | 1208 | |
11b6402c | 1209 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1210 | |
6de8ad9b JR |
1211 | for (i = 0; i < amd_iommus_present; ++i) { |
1212 | if (!domain->dev_iommu[i]) | |
1213 | continue; | |
1214 | ||
1215 | /* | |
1216 | * Devices of this domain are behind this IOMMU | |
1217 | * We need a TLB flush | |
1218 | */ | |
11b6402c | 1219 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1220 | } |
1221 | ||
cb41ed85 | 1222 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1223 | |
ea61cddb | 1224 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1225 | continue; |
1226 | ||
6c542047 | 1227 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1228 | } |
1229 | ||
11b6402c | 1230 | WARN_ON(ret); |
6de8ad9b JR |
1231 | } |
1232 | ||
17b124bf JR |
1233 | static void domain_flush_pages(struct protection_domain *domain, |
1234 | u64 address, size_t size) | |
6de8ad9b | 1235 | { |
17b124bf | 1236 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1237 | } |
b6c02715 | 1238 | |
1c655773 | 1239 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1240 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1241 | { |
17b124bf | 1242 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1243 | } |
1244 | ||
42a49f96 | 1245 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1246 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1247 | { |
17b124bf | 1248 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1249 | } |
1250 | ||
17b124bf | 1251 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1252 | { |
17b124bf | 1253 | int i; |
18811f55 | 1254 | |
17b124bf | 1255 | for (i = 0; i < amd_iommus_present; ++i) { |
f1eae7c5 | 1256 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1257 | continue; |
bfd1be18 | 1258 | |
17b124bf JR |
1259 | /* |
1260 | * Devices of this domain are behind this IOMMU | |
1261 | * We need to wait for completion of all commands. | |
1262 | */ | |
1263 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1264 | } |
e394d72a JR |
1265 | } |
1266 | ||
b00d3bcf | 1267 | |
09b42804 | 1268 | /* |
b00d3bcf | 1269 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1270 | */ |
17b124bf | 1271 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1272 | { |
b00d3bcf | 1273 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1274 | |
b00d3bcf | 1275 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1276 | device_flush_dte(dev_data); |
a345b23b JR |
1277 | } |
1278 | ||
431b2a20 JR |
1279 | /**************************************************************************** |
1280 | * | |
1281 | * The functions below are used the create the page table mappings for | |
1282 | * unity mapped regions. | |
1283 | * | |
1284 | ****************************************************************************/ | |
1285 | ||
308973d3 JR |
1286 | /* |
1287 | * This function is used to add another level to an IO page table. Adding | |
1288 | * another level increases the size of the address space by 9 bits to a size up | |
1289 | * to 64 bits. | |
1290 | */ | |
1291 | static bool increase_address_space(struct protection_domain *domain, | |
1292 | gfp_t gfp) | |
1293 | { | |
1294 | u64 *pte; | |
1295 | ||
1296 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1297 | /* address space already 64 bit large */ | |
1298 | return false; | |
1299 | ||
1300 | pte = (void *)get_zeroed_page(gfp); | |
1301 | if (!pte) | |
1302 | return false; | |
1303 | ||
1304 | *pte = PM_LEVEL_PDE(domain->mode, | |
1305 | virt_to_phys(domain->pt_root)); | |
1306 | domain->pt_root = pte; | |
1307 | domain->mode += 1; | |
1308 | domain->updated = true; | |
1309 | ||
1310 | return true; | |
1311 | } | |
1312 | ||
1313 | static u64 *alloc_pte(struct protection_domain *domain, | |
1314 | unsigned long address, | |
cbb9d729 | 1315 | unsigned long page_size, |
308973d3 JR |
1316 | u64 **pte_page, |
1317 | gfp_t gfp) | |
1318 | { | |
cbb9d729 | 1319 | int level, end_lvl; |
308973d3 | 1320 | u64 *pte, *page; |
cbb9d729 JR |
1321 | |
1322 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1323 | |
1324 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1325 | increase_address_space(domain, gfp); | |
1326 | ||
cbb9d729 JR |
1327 | level = domain->mode - 1; |
1328 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1329 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1330 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1331 | |
1332 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1333 | u64 __pte, __npte; |
1334 | ||
1335 | __pte = *pte; | |
1336 | ||
1337 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1338 | page = (u64 *)get_zeroed_page(gfp); |
1339 | if (!page) | |
1340 | return NULL; | |
7bfa5bd2 JR |
1341 | |
1342 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1343 | ||
1344 | if (cmpxchg64(pte, __pte, __npte)) { | |
1345 | free_page((unsigned long)page); | |
1346 | continue; | |
1347 | } | |
308973d3 JR |
1348 | } |
1349 | ||
cbb9d729 JR |
1350 | /* No level skipping support yet */ |
1351 | if (PM_PTE_LEVEL(*pte) != level) | |
1352 | return NULL; | |
1353 | ||
308973d3 JR |
1354 | level -= 1; |
1355 | ||
1356 | pte = IOMMU_PTE_PAGE(*pte); | |
1357 | ||
1358 | if (pte_page && level == end_lvl) | |
1359 | *pte_page = pte; | |
1360 | ||
1361 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1362 | } | |
1363 | ||
1364 | return pte; | |
1365 | } | |
1366 | ||
1367 | /* | |
1368 | * This function checks if there is a PTE for a given dma address. If | |
1369 | * there is one, it returns the pointer to it. | |
1370 | */ | |
3039ca1b JR |
1371 | static u64 *fetch_pte(struct protection_domain *domain, |
1372 | unsigned long address, | |
1373 | unsigned long *page_size) | |
308973d3 JR |
1374 | { |
1375 | int level; | |
1376 | u64 *pte; | |
1377 | ||
24cd7723 JR |
1378 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1379 | return NULL; | |
1380 | ||
3039ca1b JR |
1381 | level = domain->mode - 1; |
1382 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1383 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1384 | |
24cd7723 JR |
1385 | while (level > 0) { |
1386 | ||
1387 | /* Not Present */ | |
308973d3 JR |
1388 | if (!IOMMU_PTE_PRESENT(*pte)) |
1389 | return NULL; | |
1390 | ||
24cd7723 | 1391 | /* Large PTE */ |
3039ca1b JR |
1392 | if (PM_PTE_LEVEL(*pte) == 7 || |
1393 | PM_PTE_LEVEL(*pte) == 0) | |
1394 | break; | |
24cd7723 JR |
1395 | |
1396 | /* No level skipping support yet */ | |
1397 | if (PM_PTE_LEVEL(*pte) != level) | |
1398 | return NULL; | |
1399 | ||
308973d3 JR |
1400 | level -= 1; |
1401 | ||
24cd7723 | 1402 | /* Walk to the next level */ |
3039ca1b JR |
1403 | pte = IOMMU_PTE_PAGE(*pte); |
1404 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1405 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1406 | } | |
1407 | ||
1408 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1409 | unsigned long pte_mask; | |
1410 | ||
1411 | /* | |
1412 | * If we have a series of large PTEs, make | |
1413 | * sure to return a pointer to the first one. | |
1414 | */ | |
1415 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1416 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1417 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1418 | } |
1419 | ||
1420 | return pte; | |
1421 | } | |
1422 | ||
431b2a20 JR |
1423 | /* |
1424 | * Generic mapping functions. It maps a physical address into a DMA | |
1425 | * address space. It allocates the page table pages if necessary. | |
1426 | * In the future it can be extended to a generic mapping function | |
1427 | * supporting all features of AMD IOMMU page tables like level skipping | |
1428 | * and full 64 bit address spaces. | |
1429 | */ | |
38e817fe JR |
1430 | static int iommu_map_page(struct protection_domain *dom, |
1431 | unsigned long bus_addr, | |
1432 | unsigned long phys_addr, | |
b911b89b | 1433 | unsigned long page_size, |
abdc5eb3 | 1434 | int prot, |
b911b89b | 1435 | gfp_t gfp) |
bd0e5211 | 1436 | { |
8bda3092 | 1437 | u64 __pte, *pte; |
cbb9d729 | 1438 | int i, count; |
abdc5eb3 | 1439 | |
d4b03664 JR |
1440 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1441 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1442 | ||
bad1cac2 | 1443 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1444 | return -EINVAL; |
1445 | ||
d4b03664 | 1446 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1447 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1448 | |
63eaa75e ML |
1449 | if (!pte) |
1450 | return -ENOMEM; | |
1451 | ||
cbb9d729 JR |
1452 | for (i = 0; i < count; ++i) |
1453 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1454 | return -EBUSY; | |
bd0e5211 | 1455 | |
d4b03664 | 1456 | if (count > 1) { |
cbb9d729 JR |
1457 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1458 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1459 | } else | |
1460 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1461 | |
bd0e5211 JR |
1462 | if (prot & IOMMU_PROT_IR) |
1463 | __pte |= IOMMU_PTE_IR; | |
1464 | if (prot & IOMMU_PROT_IW) | |
1465 | __pte |= IOMMU_PTE_IW; | |
1466 | ||
cbb9d729 JR |
1467 | for (i = 0; i < count; ++i) |
1468 | pte[i] = __pte; | |
bd0e5211 | 1469 | |
04bfdd84 JR |
1470 | update_domain(dom); |
1471 | ||
bd0e5211 JR |
1472 | return 0; |
1473 | } | |
1474 | ||
24cd7723 JR |
1475 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1476 | unsigned long bus_addr, | |
1477 | unsigned long page_size) | |
eb74ff6c | 1478 | { |
71b390e9 JR |
1479 | unsigned long long unmapped; |
1480 | unsigned long unmap_size; | |
24cd7723 JR |
1481 | u64 *pte; |
1482 | ||
1483 | BUG_ON(!is_power_of_2(page_size)); | |
1484 | ||
1485 | unmapped = 0; | |
eb74ff6c | 1486 | |
24cd7723 JR |
1487 | while (unmapped < page_size) { |
1488 | ||
71b390e9 JR |
1489 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1490 | ||
1491 | if (pte) { | |
1492 | int i, count; | |
1493 | ||
1494 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1495 | for (i = 0; i < count; i++) |
1496 | pte[i] = 0ULL; | |
1497 | } | |
1498 | ||
1499 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1500 | unmapped += unmap_size; | |
1501 | } | |
1502 | ||
60d0ca3c | 1503 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1504 | |
24cd7723 | 1505 | return unmapped; |
eb74ff6c | 1506 | } |
eb74ff6c | 1507 | |
431b2a20 JR |
1508 | /**************************************************************************** |
1509 | * | |
1510 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1511 | * interface functions. |
431b2a20 JR |
1512 | * |
1513 | ****************************************************************************/ | |
d3086444 | 1514 | |
9cabe89b | 1515 | |
256e4621 JR |
1516 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1517 | struct dma_ops_domain *dma_dom, | |
1518 | unsigned int pages, u64 dma_mask) | |
384de729 | 1519 | { |
256e4621 | 1520 | unsigned long pfn = 0; |
384de729 | 1521 | |
256e4621 | 1522 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1523 | |
256e4621 JR |
1524 | if (dma_mask > DMA_BIT_MASK(32)) |
1525 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
1526 | IOVA_PFN(DMA_BIT_MASK(32))); | |
7b5e25b8 | 1527 | |
256e4621 JR |
1528 | if (!pfn) |
1529 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask)); | |
5f6bed50 | 1530 | |
256e4621 | 1531 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1532 | } |
1533 | ||
256e4621 JR |
1534 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1535 | unsigned long address, | |
1536 | unsigned int pages) | |
d3086444 | 1537 | { |
256e4621 JR |
1538 | pages = __roundup_pow_of_two(pages); |
1539 | address >>= PAGE_SHIFT; | |
384de729 | 1540 | |
256e4621 | 1541 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1542 | } |
1543 | ||
431b2a20 JR |
1544 | /**************************************************************************** |
1545 | * | |
1546 | * The next functions belong to the domain allocation. A domain is | |
1547 | * allocated for every IOMMU as the default domain. If device isolation | |
1548 | * is enabled, every device get its own domain. The most important thing | |
1549 | * about domains is the page table mapping the DMA address space they | |
1550 | * contain. | |
1551 | * | |
1552 | ****************************************************************************/ | |
1553 | ||
aeb26f55 JR |
1554 | /* |
1555 | * This function adds a protection domain to the global protection domain list | |
1556 | */ | |
1557 | static void add_domain_to_list(struct protection_domain *domain) | |
1558 | { | |
1559 | unsigned long flags; | |
1560 | ||
1561 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1562 | list_add(&domain->list, &amd_iommu_pd_list); | |
1563 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1564 | } | |
1565 | ||
1566 | /* | |
1567 | * This function removes a protection domain to the global | |
1568 | * protection domain list | |
1569 | */ | |
1570 | static void del_domain_from_list(struct protection_domain *domain) | |
1571 | { | |
1572 | unsigned long flags; | |
1573 | ||
1574 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1575 | list_del(&domain->list); | |
1576 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1577 | } | |
1578 | ||
ec487d1a JR |
1579 | static u16 domain_id_alloc(void) |
1580 | { | |
1581 | unsigned long flags; | |
1582 | int id; | |
1583 | ||
1584 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1585 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1586 | BUG_ON(id == 0); | |
1587 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1588 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1589 | else | |
1590 | id = 0; | |
1591 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1592 | ||
1593 | return id; | |
1594 | } | |
1595 | ||
a2acfb75 JR |
1596 | static void domain_id_free(int id) |
1597 | { | |
1598 | unsigned long flags; | |
1599 | ||
1600 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1601 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1602 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1603 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1604 | } | |
a2acfb75 | 1605 | |
5c34c403 JR |
1606 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1607 | static void free_pt_##LVL (unsigned long __pt) \ | |
1608 | { \ | |
1609 | unsigned long p; \ | |
1610 | u64 *pt; \ | |
1611 | int i; \ | |
1612 | \ | |
1613 | pt = (u64 *)__pt; \ | |
1614 | \ | |
1615 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1616 | /* PTE present? */ \ |
5c34c403 JR |
1617 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1618 | continue; \ | |
1619 | \ | |
0b3fff54 JR |
1620 | /* Large PTE? */ \ |
1621 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1622 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1623 | continue; \ | |
1624 | \ | |
5c34c403 JR |
1625 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1626 | FN(p); \ | |
1627 | } \ | |
1628 | free_page((unsigned long)pt); \ | |
1629 | } | |
1630 | ||
1631 | DEFINE_FREE_PT_FN(l2, free_page) | |
1632 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1633 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1634 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1635 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1636 | ||
86db2e5d | 1637 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1638 | { |
5c34c403 | 1639 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1640 | |
5c34c403 JR |
1641 | switch (domain->mode) { |
1642 | case PAGE_MODE_NONE: | |
1643 | break; | |
1644 | case PAGE_MODE_1_LEVEL: | |
1645 | free_page(root); | |
1646 | break; | |
1647 | case PAGE_MODE_2_LEVEL: | |
1648 | free_pt_l2(root); | |
1649 | break; | |
1650 | case PAGE_MODE_3_LEVEL: | |
1651 | free_pt_l3(root); | |
1652 | break; | |
1653 | case PAGE_MODE_4_LEVEL: | |
1654 | free_pt_l4(root); | |
1655 | break; | |
1656 | case PAGE_MODE_5_LEVEL: | |
1657 | free_pt_l5(root); | |
1658 | break; | |
1659 | case PAGE_MODE_6_LEVEL: | |
1660 | free_pt_l6(root); | |
1661 | break; | |
1662 | default: | |
1663 | BUG(); | |
ec487d1a | 1664 | } |
ec487d1a JR |
1665 | } |
1666 | ||
b16137b1 JR |
1667 | static void free_gcr3_tbl_level1(u64 *tbl) |
1668 | { | |
1669 | u64 *ptr; | |
1670 | int i; | |
1671 | ||
1672 | for (i = 0; i < 512; ++i) { | |
1673 | if (!(tbl[i] & GCR3_VALID)) | |
1674 | continue; | |
1675 | ||
1676 | ptr = __va(tbl[i] & PAGE_MASK); | |
1677 | ||
1678 | free_page((unsigned long)ptr); | |
1679 | } | |
1680 | } | |
1681 | ||
1682 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1683 | { | |
1684 | u64 *ptr; | |
1685 | int i; | |
1686 | ||
1687 | for (i = 0; i < 512; ++i) { | |
1688 | if (!(tbl[i] & GCR3_VALID)) | |
1689 | continue; | |
1690 | ||
1691 | ptr = __va(tbl[i] & PAGE_MASK); | |
1692 | ||
1693 | free_gcr3_tbl_level1(ptr); | |
1694 | } | |
1695 | } | |
1696 | ||
52815b75 JR |
1697 | static void free_gcr3_table(struct protection_domain *domain) |
1698 | { | |
b16137b1 JR |
1699 | if (domain->glx == 2) |
1700 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1701 | else if (domain->glx == 1) | |
1702 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1703 | else |
1704 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1705 | |
52815b75 JR |
1706 | free_page((unsigned long)domain->gcr3_tbl); |
1707 | } | |
1708 | ||
431b2a20 JR |
1709 | /* |
1710 | * Free a domain, only used if something went wrong in the | |
1711 | * allocation path and we need to free an already allocated page table | |
1712 | */ | |
ec487d1a JR |
1713 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1714 | { | |
1715 | if (!dom) | |
1716 | return; | |
1717 | ||
aeb26f55 JR |
1718 | del_domain_from_list(&dom->domain); |
1719 | ||
2d4c515b | 1720 | put_iova_domain(&dom->iovad); |
ec487d1a | 1721 | |
2d4c515b | 1722 | free_pagetable(&dom->domain); |
ec487d1a JR |
1723 | |
1724 | kfree(dom); | |
1725 | } | |
1726 | ||
431b2a20 JR |
1727 | /* |
1728 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1729 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1730 | * structures required for the dma_ops interface |
1731 | */ | |
87a64d52 | 1732 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1733 | { |
1734 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1735 | |
1736 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1737 | if (!dma_dom) | |
1738 | return NULL; | |
1739 | ||
7a5a566e | 1740 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1741 | goto free_dma_dom; |
7a5a566e | 1742 | |
ffec2197 | 1743 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1744 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1745 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1746 | if (!dma_dom->domain.pt_root) |
1747 | goto free_dma_dom; | |
ec487d1a | 1748 | |
307d5851 JR |
1749 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, |
1750 | IOVA_START_PFN, DMA_32BIT_PFN); | |
1751 | ||
81cd07b9 JR |
1752 | /* Initialize reserved ranges */ |
1753 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
1754 | ||
2d4c515b JR |
1755 | add_domain_to_list(&dma_dom->domain); |
1756 | ||
ec487d1a JR |
1757 | return dma_dom; |
1758 | ||
1759 | free_dma_dom: | |
1760 | dma_ops_domain_free(dma_dom); | |
1761 | ||
1762 | return NULL; | |
1763 | } | |
1764 | ||
5b28df6f JR |
1765 | /* |
1766 | * little helper function to check whether a given protection domain is a | |
1767 | * dma_ops domain | |
1768 | */ | |
1769 | static bool dma_ops_domain(struct protection_domain *domain) | |
1770 | { | |
1771 | return domain->flags & PD_DMA_OPS_MASK; | |
1772 | } | |
1773 | ||
fd7b5535 | 1774 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1775 | { |
132bd68f | 1776 | u64 pte_root = 0; |
ee6c2868 | 1777 | u64 flags = 0; |
863c74eb | 1778 | |
132bd68f JR |
1779 | if (domain->mode != PAGE_MODE_NONE) |
1780 | pte_root = virt_to_phys(domain->pt_root); | |
1781 | ||
38ddf41b JR |
1782 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1783 | << DEV_ENTRY_MODE_SHIFT; | |
1784 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1785 | |
ee6c2868 JR |
1786 | flags = amd_iommu_dev_table[devid].data[1]; |
1787 | ||
fd7b5535 JR |
1788 | if (ats) |
1789 | flags |= DTE_FLAG_IOTLB; | |
1790 | ||
52815b75 JR |
1791 | if (domain->flags & PD_IOMMUV2_MASK) { |
1792 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1793 | u64 glx = domain->glx; | |
1794 | u64 tmp; | |
1795 | ||
1796 | pte_root |= DTE_FLAG_GV; | |
1797 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1798 | ||
1799 | /* First mask out possible old values for GCR3 table */ | |
1800 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1801 | flags &= ~tmp; | |
1802 | ||
1803 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1804 | flags &= ~tmp; | |
1805 | ||
1806 | /* Encode GCR3 table into DTE */ | |
1807 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1808 | pte_root |= tmp; | |
1809 | ||
1810 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1811 | flags |= tmp; | |
1812 | ||
1813 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1814 | flags |= tmp; | |
1815 | } | |
1816 | ||
ee6c2868 JR |
1817 | flags &= ~(0xffffUL); |
1818 | flags |= domain->id; | |
1819 | ||
1820 | amd_iommu_dev_table[devid].data[1] = flags; | |
1821 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1822 | } |
1823 | ||
1824 | static void clear_dte_entry(u16 devid) | |
1825 | { | |
15898bbc | 1826 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
1827 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
1828 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
1829 | |
1830 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1831 | } |
1832 | ||
ec9e79ef JR |
1833 | static void do_attach(struct iommu_dev_data *dev_data, |
1834 | struct protection_domain *domain) | |
7f760ddd | 1835 | { |
7f760ddd | 1836 | struct amd_iommu *iommu; |
e25bfb56 | 1837 | u16 alias; |
ec9e79ef | 1838 | bool ats; |
fd7b5535 | 1839 | |
ec9e79ef | 1840 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1841 | alias = dev_data->alias; |
ec9e79ef | 1842 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1843 | |
1844 | /* Update data structures */ | |
1845 | dev_data->domain = domain; | |
1846 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1847 | |
1848 | /* Do reference counting */ | |
1849 | domain->dev_iommu[iommu->index] += 1; | |
1850 | domain->dev_cnt += 1; | |
1851 | ||
e25bfb56 JR |
1852 | /* Update device table */ |
1853 | set_dte_entry(dev_data->devid, domain, ats); | |
1854 | if (alias != dev_data->devid) | |
9b1a12d2 | 1855 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 1856 | |
6c542047 | 1857 | device_flush_dte(dev_data); |
7f760ddd JR |
1858 | } |
1859 | ||
ec9e79ef | 1860 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1861 | { |
7f760ddd | 1862 | struct amd_iommu *iommu; |
e25bfb56 | 1863 | u16 alias; |
7f760ddd | 1864 | |
5adad991 JR |
1865 | /* |
1866 | * First check if the device is still attached. It might already | |
1867 | * be detached from its domain because the generic | |
1868 | * iommu_detach_group code detached it and we try again here in | |
1869 | * our alias handling. | |
1870 | */ | |
1871 | if (!dev_data->domain) | |
1872 | return; | |
1873 | ||
ec9e79ef | 1874 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1875 | alias = dev_data->alias; |
15898bbc JR |
1876 | |
1877 | /* decrease reference counters */ | |
7f760ddd JR |
1878 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1879 | dev_data->domain->dev_cnt -= 1; | |
1880 | ||
1881 | /* Update data structures */ | |
1882 | dev_data->domain = NULL; | |
1883 | list_del(&dev_data->list); | |
f62dda66 | 1884 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1885 | if (alias != dev_data->devid) |
1886 | clear_dte_entry(alias); | |
15898bbc | 1887 | |
7f760ddd | 1888 | /* Flush the DTE entry */ |
6c542047 | 1889 | device_flush_dte(dev_data); |
2b681faf JR |
1890 | } |
1891 | ||
1892 | /* | |
1893 | * If a device is not yet associated with a domain, this function does | |
1894 | * assigns it visible for the hardware | |
1895 | */ | |
ec9e79ef | 1896 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1897 | struct protection_domain *domain) |
2b681faf | 1898 | { |
84fe6c19 | 1899 | int ret; |
657cbb6b | 1900 | |
272e4f99 JR |
1901 | /* |
1902 | * Must be called with IRQs disabled. Warn here to detect early | |
1903 | * when its not. | |
1904 | */ | |
1905 | WARN_ON(!irqs_disabled()); | |
1906 | ||
2b681faf JR |
1907 | /* lock domain */ |
1908 | spin_lock(&domain->lock); | |
1909 | ||
397111ab | 1910 | ret = -EBUSY; |
150952f9 | 1911 | if (dev_data->domain != NULL) |
397111ab | 1912 | goto out_unlock; |
15898bbc | 1913 | |
397111ab | 1914 | /* Attach alias group root */ |
150952f9 | 1915 | do_attach(dev_data, domain); |
24100055 | 1916 | |
84fe6c19 JL |
1917 | ret = 0; |
1918 | ||
1919 | out_unlock: | |
1920 | ||
eba6ac60 JR |
1921 | /* ready */ |
1922 | spin_unlock(&domain->lock); | |
15898bbc | 1923 | |
84fe6c19 | 1924 | return ret; |
0feae533 | 1925 | } |
b20ac0d4 | 1926 | |
52815b75 JR |
1927 | |
1928 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1929 | { | |
1930 | pci_disable_ats(pdev); | |
1931 | pci_disable_pri(pdev); | |
1932 | pci_disable_pasid(pdev); | |
1933 | } | |
1934 | ||
6a113ddc JR |
1935 | /* FIXME: Change generic reset-function to do the same */ |
1936 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1937 | { | |
1938 | u16 control; | |
1939 | int pos; | |
1940 | ||
46277b75 | 1941 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
1942 | if (!pos) |
1943 | return -EINVAL; | |
1944 | ||
46277b75 JR |
1945 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
1946 | control |= PCI_PRI_CTRL_RESET; | |
1947 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
1948 | |
1949 | return 0; | |
1950 | } | |
1951 | ||
52815b75 JR |
1952 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
1953 | { | |
6a113ddc JR |
1954 | bool reset_enable; |
1955 | int reqs, ret; | |
1956 | ||
1957 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1958 | reqs = 32; | |
1959 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
1960 | reqs = 1; | |
1961 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
1962 | |
1963 | /* Only allow access to user-accessible pages */ | |
1964 | ret = pci_enable_pasid(pdev, 0); | |
1965 | if (ret) | |
1966 | goto out_err; | |
1967 | ||
1968 | /* First reset the PRI state of the device */ | |
1969 | ret = pci_reset_pri(pdev); | |
1970 | if (ret) | |
1971 | goto out_err; | |
1972 | ||
6a113ddc JR |
1973 | /* Enable PRI */ |
1974 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
1975 | if (ret) |
1976 | goto out_err; | |
1977 | ||
6a113ddc JR |
1978 | if (reset_enable) { |
1979 | ret = pri_reset_while_enabled(pdev); | |
1980 | if (ret) | |
1981 | goto out_err; | |
1982 | } | |
1983 | ||
52815b75 JR |
1984 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
1985 | if (ret) | |
1986 | goto out_err; | |
1987 | ||
1988 | return 0; | |
1989 | ||
1990 | out_err: | |
1991 | pci_disable_pri(pdev); | |
1992 | pci_disable_pasid(pdev); | |
1993 | ||
1994 | return ret; | |
1995 | } | |
1996 | ||
c99afa25 | 1997 | /* FIXME: Move this to PCI code */ |
a3b93121 | 1998 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 1999 | |
98f1ad25 | 2000 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2001 | { |
a3b93121 | 2002 | u16 status; |
c99afa25 JR |
2003 | int pos; |
2004 | ||
46277b75 | 2005 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2006 | if (!pos) |
2007 | return false; | |
2008 | ||
a3b93121 | 2009 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2010 | |
a3b93121 | 2011 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2012 | } |
2013 | ||
407d733e | 2014 | /* |
df805abb | 2015 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2016 | * assigns it visible for the hardware |
2017 | */ | |
15898bbc JR |
2018 | static int attach_device(struct device *dev, |
2019 | struct protection_domain *domain) | |
0feae533 | 2020 | { |
2bf9a0a1 | 2021 | struct pci_dev *pdev; |
ea61cddb | 2022 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2023 | unsigned long flags; |
15898bbc | 2024 | int ret; |
eba6ac60 | 2025 | |
ea61cddb JR |
2026 | dev_data = get_dev_data(dev); |
2027 | ||
2bf9a0a1 WZ |
2028 | if (!dev_is_pci(dev)) |
2029 | goto skip_ats_check; | |
2030 | ||
2031 | pdev = to_pci_dev(dev); | |
52815b75 | 2032 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2033 | if (!dev_data->passthrough) |
52815b75 JR |
2034 | return -EINVAL; |
2035 | ||
02ca2021 JR |
2036 | if (dev_data->iommu_v2) { |
2037 | if (pdev_iommuv2_enable(pdev) != 0) | |
2038 | return -EINVAL; | |
52815b75 | 2039 | |
02ca2021 JR |
2040 | dev_data->ats.enabled = true; |
2041 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2042 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2043 | } | |
52815b75 JR |
2044 | } else if (amd_iommu_iotlb_sup && |
2045 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2046 | dev_data->ats.enabled = true; |
2047 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2048 | } | |
fd7b5535 | 2049 | |
2bf9a0a1 | 2050 | skip_ats_check: |
eba6ac60 | 2051 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2052 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2053 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2054 | ||
0feae533 JR |
2055 | /* |
2056 | * We might boot into a crash-kernel here. The crashed kernel | |
2057 | * left the caches in the IOMMU dirty. So we have to flush | |
2058 | * here to evict all dirty stuff. | |
2059 | */ | |
17b124bf | 2060 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2061 | |
2062 | return ret; | |
b20ac0d4 JR |
2063 | } |
2064 | ||
355bf553 JR |
2065 | /* |
2066 | * Removes a device from a protection domain (unlocked) | |
2067 | */ | |
ec9e79ef | 2068 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2069 | { |
2ca76279 | 2070 | struct protection_domain *domain; |
c4596114 | 2071 | |
272e4f99 JR |
2072 | /* |
2073 | * Must be called with IRQs disabled. Warn here to detect early | |
2074 | * when its not. | |
2075 | */ | |
2076 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2077 | |
f34c73f5 JR |
2078 | if (WARN_ON(!dev_data->domain)) |
2079 | return; | |
24100055 | 2080 | |
2ca76279 | 2081 | domain = dev_data->domain; |
71f77580 | 2082 | |
f1dd0a8b | 2083 | spin_lock(&domain->lock); |
24100055 | 2084 | |
150952f9 | 2085 | do_detach(dev_data); |
7f760ddd | 2086 | |
f1dd0a8b | 2087 | spin_unlock(&domain->lock); |
355bf553 JR |
2088 | } |
2089 | ||
2090 | /* | |
2091 | * Removes a device from a protection domain (with devtable_lock held) | |
2092 | */ | |
15898bbc | 2093 | static void detach_device(struct device *dev) |
355bf553 | 2094 | { |
52815b75 | 2095 | struct protection_domain *domain; |
ea61cddb | 2096 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2097 | unsigned long flags; |
2098 | ||
ec9e79ef | 2099 | dev_data = get_dev_data(dev); |
52815b75 | 2100 | domain = dev_data->domain; |
ec9e79ef | 2101 | |
355bf553 JR |
2102 | /* lock device table */ |
2103 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2104 | __detach_device(dev_data); |
355bf553 | 2105 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2106 | |
2bf9a0a1 WZ |
2107 | if (!dev_is_pci(dev)) |
2108 | return; | |
2109 | ||
02ca2021 | 2110 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2111 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2112 | else if (dev_data->ats.enabled) | |
ea61cddb | 2113 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2114 | |
2115 | dev_data->ats.enabled = false; | |
355bf553 | 2116 | } |
e275a2a0 | 2117 | |
aafd8ba0 | 2118 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2119 | { |
5abcdba4 | 2120 | struct iommu_dev_data *dev_data; |
07ee8694 | 2121 | struct iommu_domain *domain; |
e275a2a0 | 2122 | struct amd_iommu *iommu; |
7aba6cb9 | 2123 | int ret, devid; |
e275a2a0 | 2124 | |
aafd8ba0 | 2125 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2126 | return 0; |
e275a2a0 | 2127 | |
aafd8ba0 | 2128 | devid = get_device_id(dev); |
9ee35e4c | 2129 | if (devid < 0) |
7aba6cb9 WZ |
2130 | return devid; |
2131 | ||
aafd8ba0 | 2132 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2133 | |
aafd8ba0 | 2134 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2135 | if (ret) { |
2136 | if (ret != -ENOTSUPP) | |
2137 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2138 | dev_name(dev)); | |
657cbb6b | 2139 | |
aafd8ba0 | 2140 | iommu_ignore_device(dev); |
343e9cac | 2141 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2142 | goto out; |
2143 | } | |
2144 | init_iommu_group(dev); | |
2c9195e9 | 2145 | |
07ee8694 | 2146 | dev_data = get_dev_data(dev); |
2c9195e9 | 2147 | |
4d58b8a6 | 2148 | BUG_ON(!dev_data); |
657cbb6b | 2149 | |
1e6a7b04 | 2150 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2151 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2152 | |
07ee8694 JR |
2153 | /* Domains are initialized for this device - have a look what we ended up with */ |
2154 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2155 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2156 | dev_data->passthrough = true; |
32302324 | 2157 | else |
2c9195e9 | 2158 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2159 | |
aafd8ba0 | 2160 | out: |
e275a2a0 JR |
2161 | iommu_completion_wait(iommu); |
2162 | ||
e275a2a0 JR |
2163 | return 0; |
2164 | } | |
2165 | ||
aafd8ba0 | 2166 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2167 | { |
aafd8ba0 | 2168 | struct amd_iommu *iommu; |
7aba6cb9 | 2169 | int devid; |
aafd8ba0 JR |
2170 | |
2171 | if (!check_device(dev)) | |
2172 | return; | |
2173 | ||
2174 | devid = get_device_id(dev); | |
9ee35e4c | 2175 | if (devid < 0) |
7aba6cb9 WZ |
2176 | return; |
2177 | ||
aafd8ba0 JR |
2178 | iommu = amd_iommu_rlookup_table[devid]; |
2179 | ||
2180 | iommu_uninit_device(dev); | |
2181 | iommu_completion_wait(iommu); | |
8638c491 JR |
2182 | } |
2183 | ||
b097d11a WZ |
2184 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2185 | { | |
2186 | if (dev_is_pci(dev)) | |
2187 | return pci_device_group(dev); | |
2188 | ||
2189 | return acpihid_device_group(dev); | |
2190 | } | |
2191 | ||
431b2a20 JR |
2192 | /***************************************************************************** |
2193 | * | |
2194 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2195 | * | |
2196 | *****************************************************************************/ | |
2197 | ||
b1516a14 JR |
2198 | static void __queue_flush(struct flush_queue *queue) |
2199 | { | |
2200 | struct protection_domain *domain; | |
2201 | unsigned long flags; | |
2202 | int idx; | |
2203 | ||
2204 | /* First flush TLB of all known domains */ | |
2205 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
2206 | list_for_each_entry(domain, &amd_iommu_pd_list, list) | |
2207 | domain_flush_tlb(domain); | |
2208 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
2209 | ||
2210 | /* Wait until flushes have completed */ | |
2211 | domain_flush_complete(NULL); | |
2212 | ||
2213 | for (idx = 0; idx < queue->next; ++idx) { | |
2214 | struct flush_queue_entry *entry; | |
2215 | ||
2216 | entry = queue->entries + idx; | |
2217 | ||
2218 | free_iova_fast(&entry->dma_dom->iovad, | |
2219 | entry->iova_pfn, | |
2220 | entry->pages); | |
2221 | ||
2222 | /* Not really necessary, just to make sure we catch any bugs */ | |
2223 | entry->dma_dom = NULL; | |
2224 | } | |
2225 | ||
2226 | queue->next = 0; | |
2227 | } | |
2228 | ||
281e8ccb | 2229 | static void queue_flush_all(void) |
bb279475 JR |
2230 | { |
2231 | int cpu; | |
2232 | ||
bb279475 JR |
2233 | for_each_possible_cpu(cpu) { |
2234 | struct flush_queue *queue; | |
2235 | unsigned long flags; | |
2236 | ||
2237 | queue = per_cpu_ptr(&flush_queue, cpu); | |
2238 | spin_lock_irqsave(&queue->lock, flags); | |
2239 | if (queue->next > 0) | |
2240 | __queue_flush(queue); | |
2241 | spin_unlock_irqrestore(&queue->lock, flags); | |
2242 | } | |
2243 | } | |
2244 | ||
281e8ccb JR |
2245 | static void queue_flush_timeout(unsigned long unsused) |
2246 | { | |
2247 | atomic_set(&queue_timer_on, 0); | |
2248 | queue_flush_all(); | |
2249 | } | |
2250 | ||
b1516a14 JR |
2251 | static void queue_add(struct dma_ops_domain *dma_dom, |
2252 | unsigned long address, unsigned long pages) | |
2253 | { | |
2254 | struct flush_queue_entry *entry; | |
2255 | struct flush_queue *queue; | |
2256 | unsigned long flags; | |
2257 | int idx; | |
2258 | ||
2259 | pages = __roundup_pow_of_two(pages); | |
2260 | address >>= PAGE_SHIFT; | |
2261 | ||
2262 | queue = get_cpu_ptr(&flush_queue); | |
2263 | spin_lock_irqsave(&queue->lock, flags); | |
2264 | ||
2265 | if (queue->next == FLUSH_QUEUE_SIZE) | |
2266 | __queue_flush(queue); | |
2267 | ||
2268 | idx = queue->next++; | |
2269 | entry = queue->entries + idx; | |
2270 | ||
2271 | entry->iova_pfn = address; | |
2272 | entry->pages = pages; | |
2273 | entry->dma_dom = dma_dom; | |
2274 | ||
2275 | spin_unlock_irqrestore(&queue->lock, flags); | |
bb279475 JR |
2276 | |
2277 | if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0) | |
2278 | mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10)); | |
2279 | ||
b1516a14 JR |
2280 | put_cpu_ptr(&flush_queue); |
2281 | } | |
2282 | ||
2283 | ||
431b2a20 JR |
2284 | /* |
2285 | * In the dma_ops path we only have the struct device. This function | |
2286 | * finds the corresponding IOMMU, the protection domain and the | |
2287 | * requestor id for a given device. | |
2288 | * If the device is not yet associated with a domain this is also done | |
2289 | * in this function. | |
2290 | */ | |
94f6d190 | 2291 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2292 | { |
94f6d190 | 2293 | struct protection_domain *domain; |
b20ac0d4 | 2294 | |
f99c0f1c | 2295 | if (!check_device(dev)) |
94f6d190 | 2296 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2297 | |
d26592a9 | 2298 | domain = get_dev_data(dev)->domain; |
0bb6e243 | 2299 | if (!dma_ops_domain(domain)) |
94f6d190 | 2300 | return ERR_PTR(-EBUSY); |
f91ba190 | 2301 | |
0bb6e243 | 2302 | return domain; |
b20ac0d4 JR |
2303 | } |
2304 | ||
04bfdd84 JR |
2305 | static void update_device_table(struct protection_domain *domain) |
2306 | { | |
492667da | 2307 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2308 | |
3254de6b | 2309 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ea61cddb | 2310 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); |
3254de6b JR |
2311 | |
2312 | if (dev_data->devid == dev_data->alias) | |
2313 | continue; | |
2314 | ||
2315 | /* There is an alias, update device table entry for it */ | |
2316 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled); | |
2317 | } | |
04bfdd84 JR |
2318 | } |
2319 | ||
2320 | static void update_domain(struct protection_domain *domain) | |
2321 | { | |
2322 | if (!domain->updated) | |
2323 | return; | |
2324 | ||
2325 | update_device_table(domain); | |
17b124bf JR |
2326 | |
2327 | domain_flush_devices(domain); | |
2328 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2329 | |
2330 | domain->updated = false; | |
2331 | } | |
2332 | ||
f37f7f33 JR |
2333 | static int dir2prot(enum dma_data_direction direction) |
2334 | { | |
2335 | if (direction == DMA_TO_DEVICE) | |
2336 | return IOMMU_PROT_IR; | |
2337 | else if (direction == DMA_FROM_DEVICE) | |
2338 | return IOMMU_PROT_IW; | |
2339 | else if (direction == DMA_BIDIRECTIONAL) | |
2340 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2341 | else | |
2342 | return 0; | |
2343 | } | |
431b2a20 JR |
2344 | /* |
2345 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2346 | * contiguous memory region into DMA address space. It is used by all |
2347 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2348 | * Must be called with the domain lock held. |
2349 | */ | |
cb76c322 | 2350 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2351 | struct dma_ops_domain *dma_dom, |
2352 | phys_addr_t paddr, | |
2353 | size_t size, | |
f37f7f33 | 2354 | enum dma_data_direction direction, |
832a90c3 | 2355 | u64 dma_mask) |
cb76c322 JR |
2356 | { |
2357 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2358 | dma_addr_t address, start, ret; |
cb76c322 | 2359 | unsigned int pages; |
518d9b45 | 2360 | int prot = 0; |
cb76c322 JR |
2361 | int i; |
2362 | ||
e3c449f5 | 2363 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2364 | paddr &= PAGE_MASK; |
2365 | ||
256e4621 | 2366 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
266a3bd2 JR |
2367 | if (address == DMA_ERROR_CODE) |
2368 | goto out; | |
cb76c322 | 2369 | |
f37f7f33 | 2370 | prot = dir2prot(direction); |
518d9b45 | 2371 | |
cb76c322 JR |
2372 | start = address; |
2373 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2374 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2375 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2376 | if (ret) | |
53812c11 JR |
2377 | goto out_unmap; |
2378 | ||
cb76c322 JR |
2379 | paddr += PAGE_SIZE; |
2380 | start += PAGE_SIZE; | |
2381 | } | |
2382 | address += offset; | |
2383 | ||
ab7032bb | 2384 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2385 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2386 | domain_flush_complete(&dma_dom->domain); |
2387 | } | |
270cab24 | 2388 | |
cb76c322 JR |
2389 | out: |
2390 | return address; | |
53812c11 JR |
2391 | |
2392 | out_unmap: | |
2393 | ||
2394 | for (--i; i >= 0; --i) { | |
2395 | start -= PAGE_SIZE; | |
518d9b45 | 2396 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2397 | } |
2398 | ||
256e4621 JR |
2399 | domain_flush_tlb(&dma_dom->domain); |
2400 | domain_flush_complete(&dma_dom->domain); | |
2401 | ||
2402 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2403 | |
8fd524b3 | 2404 | return DMA_ERROR_CODE; |
cb76c322 JR |
2405 | } |
2406 | ||
431b2a20 JR |
2407 | /* |
2408 | * Does the reverse of the __map_single function. Must be called with | |
2409 | * the domain lock held too | |
2410 | */ | |
cd8c82e8 | 2411 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2412 | dma_addr_t dma_addr, |
2413 | size_t size, | |
2414 | int dir) | |
2415 | { | |
04e0463e | 2416 | dma_addr_t flush_addr; |
cb76c322 JR |
2417 | dma_addr_t i, start; |
2418 | unsigned int pages; | |
2419 | ||
04e0463e | 2420 | flush_addr = dma_addr; |
e3c449f5 | 2421 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2422 | dma_addr &= PAGE_MASK; |
2423 | start = dma_addr; | |
2424 | ||
2425 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2426 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2427 | start += PAGE_SIZE; |
2428 | } | |
2429 | ||
b1516a14 JR |
2430 | if (amd_iommu_unmap_flush) { |
2431 | dma_ops_free_iova(dma_dom, dma_addr, pages); | |
2432 | domain_flush_tlb(&dma_dom->domain); | |
2433 | domain_flush_complete(&dma_dom->domain); | |
2434 | } else { | |
2435 | queue_add(dma_dom, dma_addr, pages); | |
2436 | } | |
cb76c322 JR |
2437 | } |
2438 | ||
431b2a20 JR |
2439 | /* |
2440 | * The exported map_single function for dma_ops. | |
2441 | */ | |
51491367 FT |
2442 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2443 | unsigned long offset, size_t size, | |
2444 | enum dma_data_direction dir, | |
00085f1e | 2445 | unsigned long attrs) |
4da70b9e | 2446 | { |
92d420ec | 2447 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2448 | struct protection_domain *domain; |
b3311b06 | 2449 | struct dma_ops_domain *dma_dom; |
832a90c3 | 2450 | u64 dma_mask; |
4da70b9e | 2451 | |
94f6d190 JR |
2452 | domain = get_domain(dev); |
2453 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2454 | return (dma_addr_t)paddr; |
94f6d190 JR |
2455 | else if (IS_ERR(domain)) |
2456 | return DMA_ERROR_CODE; | |
4da70b9e | 2457 | |
f99c0f1c | 2458 | dma_mask = *dev->dma_mask; |
b3311b06 | 2459 | dma_dom = to_dma_ops_domain(domain); |
f99c0f1c | 2460 | |
b3311b06 | 2461 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2462 | } |
2463 | ||
431b2a20 JR |
2464 | /* |
2465 | * The exported unmap_single function for dma_ops. | |
2466 | */ | |
51491367 | 2467 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2468 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2469 | { |
4da70b9e | 2470 | struct protection_domain *domain; |
b3311b06 | 2471 | struct dma_ops_domain *dma_dom; |
4da70b9e | 2472 | |
94f6d190 JR |
2473 | domain = get_domain(dev); |
2474 | if (IS_ERR(domain)) | |
5b28df6f JR |
2475 | return; |
2476 | ||
b3311b06 JR |
2477 | dma_dom = to_dma_ops_domain(domain); |
2478 | ||
2479 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2480 | } |
2481 | ||
80187fd3 JR |
2482 | static int sg_num_pages(struct device *dev, |
2483 | struct scatterlist *sglist, | |
2484 | int nelems) | |
2485 | { | |
2486 | unsigned long mask, boundary_size; | |
2487 | struct scatterlist *s; | |
2488 | int i, npages = 0; | |
2489 | ||
2490 | mask = dma_get_seg_boundary(dev); | |
2491 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2492 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2493 | ||
2494 | for_each_sg(sglist, s, nelems, i) { | |
2495 | int p, n; | |
2496 | ||
2497 | s->dma_address = npages << PAGE_SHIFT; | |
2498 | p = npages % boundary_size; | |
2499 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2500 | if (p + n > boundary_size) | |
2501 | npages += boundary_size - p; | |
2502 | npages += n; | |
2503 | } | |
2504 | ||
2505 | return npages; | |
2506 | } | |
2507 | ||
431b2a20 JR |
2508 | /* |
2509 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2510 | * lists). | |
2511 | */ | |
65b050ad | 2512 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2513 | int nelems, enum dma_data_direction direction, |
00085f1e | 2514 | unsigned long attrs) |
65b050ad | 2515 | { |
80187fd3 | 2516 | int mapped_pages = 0, npages = 0, prot = 0, i; |
65b050ad | 2517 | struct protection_domain *domain; |
80187fd3 | 2518 | struct dma_ops_domain *dma_dom; |
65b050ad | 2519 | struct scatterlist *s; |
80187fd3 | 2520 | unsigned long address; |
832a90c3 | 2521 | u64 dma_mask; |
65b050ad | 2522 | |
94f6d190 | 2523 | domain = get_domain(dev); |
a0e191b2 | 2524 | if (IS_ERR(domain)) |
94f6d190 | 2525 | return 0; |
dbcc112e | 2526 | |
b3311b06 | 2527 | dma_dom = to_dma_ops_domain(domain); |
832a90c3 | 2528 | dma_mask = *dev->dma_mask; |
65b050ad | 2529 | |
80187fd3 JR |
2530 | npages = sg_num_pages(dev, sglist, nelems); |
2531 | ||
2532 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
2533 | if (address == DMA_ERROR_CODE) | |
2534 | goto out_err; | |
2535 | ||
2536 | prot = dir2prot(direction); | |
2537 | ||
2538 | /* Map all sg entries */ | |
65b050ad | 2539 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2540 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2541 | ||
2542 | for (j = 0; j < pages; ++j) { | |
2543 | unsigned long bus_addr, phys_addr; | |
2544 | int ret; | |
65b050ad | 2545 | |
80187fd3 JR |
2546 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2547 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2548 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2549 | if (ret) | |
2550 | goto out_unmap; | |
65b050ad | 2551 | |
80187fd3 JR |
2552 | mapped_pages += 1; |
2553 | } | |
65b050ad JR |
2554 | } |
2555 | ||
80187fd3 JR |
2556 | /* Everything is mapped - write the right values into s->dma_address */ |
2557 | for_each_sg(sglist, s, nelems, i) { | |
2558 | s->dma_address += address + s->offset; | |
2559 | s->dma_length = s->length; | |
2560 | } | |
2561 | ||
2562 | return nelems; | |
2563 | ||
2564 | out_unmap: | |
2565 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2566 | dev_name(dev), npages); | |
2567 | ||
2568 | for_each_sg(sglist, s, nelems, i) { | |
2569 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2570 | ||
2571 | for (j = 0; j < pages; ++j) { | |
2572 | unsigned long bus_addr; | |
92d420ec | 2573 | |
80187fd3 JR |
2574 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2575 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2576 | ||
2577 | if (--mapped_pages) | |
2578 | goto out_free_iova; | |
2579 | } | |
65b050ad JR |
2580 | } |
2581 | ||
80187fd3 JR |
2582 | out_free_iova: |
2583 | free_iova_fast(&dma_dom->iovad, address, npages); | |
2584 | ||
2585 | out_err: | |
92d420ec | 2586 | return 0; |
65b050ad JR |
2587 | } |
2588 | ||
431b2a20 JR |
2589 | /* |
2590 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2591 | * lists). | |
2592 | */ | |
65b050ad | 2593 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2594 | int nelems, enum dma_data_direction dir, |
00085f1e | 2595 | unsigned long attrs) |
65b050ad | 2596 | { |
65b050ad | 2597 | struct protection_domain *domain; |
b3311b06 | 2598 | struct dma_ops_domain *dma_dom; |
80187fd3 JR |
2599 | unsigned long startaddr; |
2600 | int npages = 2; | |
65b050ad | 2601 | |
94f6d190 JR |
2602 | domain = get_domain(dev); |
2603 | if (IS_ERR(domain)) | |
5b28df6f JR |
2604 | return; |
2605 | ||
80187fd3 | 2606 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
b3311b06 | 2607 | dma_dom = to_dma_ops_domain(domain); |
80187fd3 JR |
2608 | npages = sg_num_pages(dev, sglist, nelems); |
2609 | ||
b3311b06 | 2610 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2611 | } |
2612 | ||
431b2a20 JR |
2613 | /* |
2614 | * The exported alloc_coherent function for dma_ops. | |
2615 | */ | |
5d8b53cf | 2616 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2617 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2618 | unsigned long attrs) |
5d8b53cf | 2619 | { |
832a90c3 | 2620 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2621 | struct protection_domain *domain; |
b3311b06 | 2622 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2623 | struct page *page; |
5d8b53cf | 2624 | |
94f6d190 JR |
2625 | domain = get_domain(dev); |
2626 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2627 | page = alloc_pages(flag, get_order(size)); |
2628 | *dma_addr = page_to_phys(page); | |
2629 | return page_address(page); | |
94f6d190 JR |
2630 | } else if (IS_ERR(domain)) |
2631 | return NULL; | |
5d8b53cf | 2632 | |
b3311b06 | 2633 | dma_dom = to_dma_ops_domain(domain); |
3b839a57 | 2634 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2635 | dma_mask = dev->coherent_dma_mask; |
2636 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2637 | flag |= __GFP_ZERO; |
5d8b53cf | 2638 | |
3b839a57 JR |
2639 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2640 | if (!page) { | |
d0164adc | 2641 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2642 | return NULL; |
5d8b53cf | 2643 | |
3b839a57 JR |
2644 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2645 | get_order(size)); | |
2646 | if (!page) | |
2647 | return NULL; | |
2648 | } | |
5d8b53cf | 2649 | |
832a90c3 JR |
2650 | if (!dma_mask) |
2651 | dma_mask = *dev->dma_mask; | |
2652 | ||
b3311b06 | 2653 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
bda350db | 2654 | size, DMA_BIDIRECTIONAL, dma_mask); |
5d8b53cf | 2655 | |
92d420ec | 2656 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2657 | goto out_free; |
5d8b53cf | 2658 | |
3b839a57 | 2659 | return page_address(page); |
5b28df6f JR |
2660 | |
2661 | out_free: | |
2662 | ||
3b839a57 JR |
2663 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2664 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2665 | |
2666 | return NULL; | |
5d8b53cf JR |
2667 | } |
2668 | ||
431b2a20 JR |
2669 | /* |
2670 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2671 | */ |
5d8b53cf | 2672 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2673 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2674 | unsigned long attrs) |
5d8b53cf | 2675 | { |
5d8b53cf | 2676 | struct protection_domain *domain; |
b3311b06 | 2677 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2678 | struct page *page; |
5d8b53cf | 2679 | |
3b839a57 JR |
2680 | page = virt_to_page(virt_addr); |
2681 | size = PAGE_ALIGN(size); | |
2682 | ||
94f6d190 JR |
2683 | domain = get_domain(dev); |
2684 | if (IS_ERR(domain)) | |
5b28df6f JR |
2685 | goto free_mem; |
2686 | ||
b3311b06 JR |
2687 | dma_dom = to_dma_ops_domain(domain); |
2688 | ||
2689 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2690 | |
5d8b53cf | 2691 | free_mem: |
3b839a57 JR |
2692 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2693 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2694 | } |
2695 | ||
b39ba6ad JR |
2696 | /* |
2697 | * This function is called by the DMA layer to find out if we can handle a | |
2698 | * particular device. It is part of the dma_ops. | |
2699 | */ | |
2700 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2701 | { | |
420aef8a | 2702 | return check_device(dev); |
b39ba6ad JR |
2703 | } |
2704 | ||
160c1d8e | 2705 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2706 | .alloc = alloc_coherent, |
2707 | .free = free_coherent, | |
2708 | .map_page = map_page, | |
2709 | .unmap_page = unmap_page, | |
2710 | .map_sg = map_sg, | |
2711 | .unmap_sg = unmap_sg, | |
2712 | .dma_supported = amd_iommu_dma_supported, | |
6631ee9d JR |
2713 | }; |
2714 | ||
81cd07b9 JR |
2715 | static int init_reserved_iova_ranges(void) |
2716 | { | |
2717 | struct pci_dev *pdev = NULL; | |
2718 | struct iova *val; | |
2719 | ||
2720 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, | |
2721 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2722 | ||
2723 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2724 | &reserved_rbtree_key); | |
2725 | ||
2726 | /* MSI memory range */ | |
2727 | val = reserve_iova(&reserved_iova_ranges, | |
2728 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2729 | if (!val) { | |
2730 | pr_err("Reserving MSI range failed\n"); | |
2731 | return -ENOMEM; | |
2732 | } | |
2733 | ||
2734 | /* HT memory range */ | |
2735 | val = reserve_iova(&reserved_iova_ranges, | |
2736 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2737 | if (!val) { | |
2738 | pr_err("Reserving HT range failed\n"); | |
2739 | return -ENOMEM; | |
2740 | } | |
2741 | ||
2742 | /* | |
2743 | * Memory used for PCI resources | |
2744 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2745 | */ | |
2746 | for_each_pci_dev(pdev) { | |
2747 | int i; | |
2748 | ||
2749 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2750 | struct resource *r = &pdev->resource[i]; | |
2751 | ||
2752 | if (!(r->flags & IORESOURCE_MEM)) | |
2753 | continue; | |
2754 | ||
2755 | val = reserve_iova(&reserved_iova_ranges, | |
2756 | IOVA_PFN(r->start), | |
2757 | IOVA_PFN(r->end)); | |
2758 | if (!val) { | |
2759 | pr_err("Reserve pci-resource range failed\n"); | |
2760 | return -ENOMEM; | |
2761 | } | |
2762 | } | |
2763 | } | |
2764 | ||
2765 | return 0; | |
2766 | } | |
2767 | ||
3a18404c | 2768 | int __init amd_iommu_init_api(void) |
27c2127a | 2769 | { |
c5b5da9c | 2770 | int ret, cpu, err = 0; |
307d5851 JR |
2771 | |
2772 | ret = iova_cache_get(); | |
2773 | if (ret) | |
2774 | return ret; | |
9a4d3bf5 | 2775 | |
81cd07b9 JR |
2776 | ret = init_reserved_iova_ranges(); |
2777 | if (ret) | |
2778 | return ret; | |
2779 | ||
c5b5da9c JR |
2780 | for_each_possible_cpu(cpu) { |
2781 | struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu); | |
2782 | ||
2783 | queue->entries = kzalloc(FLUSH_QUEUE_SIZE * | |
2784 | sizeof(*queue->entries), | |
2785 | GFP_KERNEL); | |
2786 | if (!queue->entries) | |
2787 | goto out_put_iova; | |
2788 | ||
2789 | spin_lock_init(&queue->lock); | |
2790 | } | |
2791 | ||
9a4d3bf5 WZ |
2792 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2793 | if (err) | |
2794 | return err; | |
2795 | #ifdef CONFIG_ARM_AMBA | |
2796 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2797 | if (err) | |
2798 | return err; | |
2799 | #endif | |
0076cd3d WZ |
2800 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2801 | if (err) | |
2802 | return err; | |
9a4d3bf5 | 2803 | return 0; |
c5b5da9c JR |
2804 | |
2805 | out_put_iova: | |
2806 | for_each_possible_cpu(cpu) { | |
2807 | struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu); | |
2808 | ||
2809 | kfree(queue->entries); | |
2810 | } | |
2811 | ||
2812 | return -ENOMEM; | |
f5325094 JR |
2813 | } |
2814 | ||
6631ee9d JR |
2815 | int __init amd_iommu_init_dma_ops(void) |
2816 | { | |
bb279475 JR |
2817 | setup_timer(&queue_timer, queue_flush_timeout, 0); |
2818 | atomic_set(&queue_timer_on, 0); | |
2819 | ||
32302324 | 2820 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2821 | iommu_detected = 1; |
6631ee9d | 2822 | |
52717828 JR |
2823 | /* |
2824 | * In case we don't initialize SWIOTLB (actually the common case | |
2825 | * when AMD IOMMU is enabled), make sure there are global | |
2826 | * dma_ops set as a fall-back for devices not handled by this | |
2827 | * driver (for example non-PCI devices). | |
2828 | */ | |
2829 | if (!swiotlb) | |
2830 | dma_ops = &nommu_dma_ops; | |
2831 | ||
62410eeb JR |
2832 | if (amd_iommu_unmap_flush) |
2833 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2834 | else | |
2835 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2836 | ||
6631ee9d | 2837 | return 0; |
c5b5da9c | 2838 | |
6631ee9d | 2839 | } |
6d98cd80 JR |
2840 | |
2841 | /***************************************************************************** | |
2842 | * | |
2843 | * The following functions belong to the exported interface of AMD IOMMU | |
2844 | * | |
2845 | * This interface allows access to lower level functions of the IOMMU | |
2846 | * like protection domain handling and assignement of devices to domains | |
2847 | * which is not possible with the dma_ops interface. | |
2848 | * | |
2849 | *****************************************************************************/ | |
2850 | ||
6d98cd80 JR |
2851 | static void cleanup_domain(struct protection_domain *domain) |
2852 | { | |
9b29d3c6 | 2853 | struct iommu_dev_data *entry; |
6d98cd80 | 2854 | unsigned long flags; |
6d98cd80 JR |
2855 | |
2856 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2857 | ||
9b29d3c6 JR |
2858 | while (!list_empty(&domain->dev_list)) { |
2859 | entry = list_first_entry(&domain->dev_list, | |
2860 | struct iommu_dev_data, list); | |
2861 | __detach_device(entry); | |
492667da | 2862 | } |
6d98cd80 JR |
2863 | |
2864 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2865 | } | |
2866 | ||
2650815f JR |
2867 | static void protection_domain_free(struct protection_domain *domain) |
2868 | { | |
2869 | if (!domain) | |
2870 | return; | |
2871 | ||
aeb26f55 JR |
2872 | del_domain_from_list(domain); |
2873 | ||
2650815f JR |
2874 | if (domain->id) |
2875 | domain_id_free(domain->id); | |
2876 | ||
2877 | kfree(domain); | |
2878 | } | |
2879 | ||
7a5a566e JR |
2880 | static int protection_domain_init(struct protection_domain *domain) |
2881 | { | |
2882 | spin_lock_init(&domain->lock); | |
2883 | mutex_init(&domain->api_lock); | |
2884 | domain->id = domain_id_alloc(); | |
2885 | if (!domain->id) | |
2886 | return -ENOMEM; | |
2887 | INIT_LIST_HEAD(&domain->dev_list); | |
2888 | ||
2889 | return 0; | |
2890 | } | |
2891 | ||
2650815f | 2892 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2893 | { |
2894 | struct protection_domain *domain; | |
2895 | ||
2896 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2897 | if (!domain) | |
2650815f | 2898 | return NULL; |
c156e347 | 2899 | |
7a5a566e | 2900 | if (protection_domain_init(domain)) |
2650815f JR |
2901 | goto out_err; |
2902 | ||
aeb26f55 JR |
2903 | add_domain_to_list(domain); |
2904 | ||
2650815f JR |
2905 | return domain; |
2906 | ||
2907 | out_err: | |
2908 | kfree(domain); | |
2909 | ||
2910 | return NULL; | |
2911 | } | |
2912 | ||
3f4b87b9 | 2913 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2914 | { |
3f4b87b9 | 2915 | struct protection_domain *pdomain; |
0bb6e243 | 2916 | struct dma_ops_domain *dma_domain; |
2650815f | 2917 | |
0bb6e243 JR |
2918 | switch (type) { |
2919 | case IOMMU_DOMAIN_UNMANAGED: | |
2920 | pdomain = protection_domain_alloc(); | |
2921 | if (!pdomain) | |
2922 | return NULL; | |
c156e347 | 2923 | |
0bb6e243 JR |
2924 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2925 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2926 | if (!pdomain->pt_root) { | |
2927 | protection_domain_free(pdomain); | |
2928 | return NULL; | |
2929 | } | |
c156e347 | 2930 | |
0bb6e243 JR |
2931 | pdomain->domain.geometry.aperture_start = 0; |
2932 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2933 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2934 | |
0bb6e243 JR |
2935 | break; |
2936 | case IOMMU_DOMAIN_DMA: | |
2937 | dma_domain = dma_ops_domain_alloc(); | |
2938 | if (!dma_domain) { | |
2939 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2940 | return NULL; | |
2941 | } | |
2942 | pdomain = &dma_domain->domain; | |
2943 | break; | |
07f643a3 JR |
2944 | case IOMMU_DOMAIN_IDENTITY: |
2945 | pdomain = protection_domain_alloc(); | |
2946 | if (!pdomain) | |
2947 | return NULL; | |
c156e347 | 2948 | |
07f643a3 JR |
2949 | pdomain->mode = PAGE_MODE_NONE; |
2950 | break; | |
0bb6e243 JR |
2951 | default: |
2952 | return NULL; | |
2953 | } | |
c156e347 | 2954 | |
3f4b87b9 | 2955 | return &pdomain->domain; |
c156e347 JR |
2956 | } |
2957 | ||
3f4b87b9 | 2958 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2959 | { |
3f4b87b9 | 2960 | struct protection_domain *domain; |
cda7005b | 2961 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2962 | |
3f4b87b9 JR |
2963 | domain = to_pdomain(dom); |
2964 | ||
98383fc3 JR |
2965 | if (domain->dev_cnt > 0) |
2966 | cleanup_domain(domain); | |
2967 | ||
2968 | BUG_ON(domain->dev_cnt != 0); | |
2969 | ||
cda7005b JR |
2970 | if (!dom) |
2971 | return; | |
98383fc3 | 2972 | |
cda7005b JR |
2973 | switch (dom->type) { |
2974 | case IOMMU_DOMAIN_DMA: | |
281e8ccb JR |
2975 | /* |
2976 | * First make sure the domain is no longer referenced from the | |
2977 | * flush queue | |
2978 | */ | |
2979 | queue_flush_all(); | |
2980 | ||
2981 | /* Now release the domain */ | |
b3311b06 | 2982 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
2983 | dma_ops_domain_free(dma_dom); |
2984 | break; | |
2985 | default: | |
2986 | if (domain->mode != PAGE_MODE_NONE) | |
2987 | free_pagetable(domain); | |
52815b75 | 2988 | |
cda7005b JR |
2989 | if (domain->flags & PD_IOMMUV2_MASK) |
2990 | free_gcr3_table(domain); | |
2991 | ||
2992 | protection_domain_free(domain); | |
2993 | break; | |
2994 | } | |
98383fc3 JR |
2995 | } |
2996 | ||
684f2888 JR |
2997 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2998 | struct device *dev) | |
2999 | { | |
657cbb6b | 3000 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3001 | struct amd_iommu *iommu; |
7aba6cb9 | 3002 | int devid; |
684f2888 | 3003 | |
98fc5a69 | 3004 | if (!check_device(dev)) |
684f2888 JR |
3005 | return; |
3006 | ||
98fc5a69 | 3007 | devid = get_device_id(dev); |
9ee35e4c | 3008 | if (devid < 0) |
7aba6cb9 | 3009 | return; |
684f2888 | 3010 | |
657cbb6b | 3011 | if (dev_data->domain != NULL) |
15898bbc | 3012 | detach_device(dev); |
684f2888 JR |
3013 | |
3014 | iommu = amd_iommu_rlookup_table[devid]; | |
3015 | if (!iommu) | |
3016 | return; | |
3017 | ||
684f2888 JR |
3018 | iommu_completion_wait(iommu); |
3019 | } | |
3020 | ||
01106066 JR |
3021 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3022 | struct device *dev) | |
3023 | { | |
3f4b87b9 | 3024 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3025 | struct iommu_dev_data *dev_data; |
01106066 | 3026 | struct amd_iommu *iommu; |
15898bbc | 3027 | int ret; |
01106066 | 3028 | |
98fc5a69 | 3029 | if (!check_device(dev)) |
01106066 JR |
3030 | return -EINVAL; |
3031 | ||
657cbb6b JR |
3032 | dev_data = dev->archdata.iommu; |
3033 | ||
f62dda66 | 3034 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3035 | if (!iommu) |
3036 | return -EINVAL; | |
3037 | ||
657cbb6b | 3038 | if (dev_data->domain) |
15898bbc | 3039 | detach_device(dev); |
01106066 | 3040 | |
15898bbc | 3041 | ret = attach_device(dev, domain); |
01106066 JR |
3042 | |
3043 | iommu_completion_wait(iommu); | |
3044 | ||
15898bbc | 3045 | return ret; |
01106066 JR |
3046 | } |
3047 | ||
468e2366 | 3048 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3049 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3050 | { |
3f4b87b9 | 3051 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3052 | int prot = 0; |
3053 | int ret; | |
3054 | ||
132bd68f JR |
3055 | if (domain->mode == PAGE_MODE_NONE) |
3056 | return -EINVAL; | |
3057 | ||
c6229ca6 JR |
3058 | if (iommu_prot & IOMMU_READ) |
3059 | prot |= IOMMU_PROT_IR; | |
3060 | if (iommu_prot & IOMMU_WRITE) | |
3061 | prot |= IOMMU_PROT_IW; | |
3062 | ||
5d214fe6 | 3063 | mutex_lock(&domain->api_lock); |
b911b89b | 3064 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3065 | mutex_unlock(&domain->api_lock); |
3066 | ||
795e74f7 | 3067 | return ret; |
c6229ca6 JR |
3068 | } |
3069 | ||
5009065d OBC |
3070 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3071 | size_t page_size) | |
eb74ff6c | 3072 | { |
3f4b87b9 | 3073 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3074 | size_t unmap_size; |
eb74ff6c | 3075 | |
132bd68f JR |
3076 | if (domain->mode == PAGE_MODE_NONE) |
3077 | return -EINVAL; | |
3078 | ||
5d214fe6 | 3079 | mutex_lock(&domain->api_lock); |
468e2366 | 3080 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3081 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3082 | |
17b124bf | 3083 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3084 | |
5009065d | 3085 | return unmap_size; |
eb74ff6c JR |
3086 | } |
3087 | ||
645c4c8d | 3088 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3089 | dma_addr_t iova) |
645c4c8d | 3090 | { |
3f4b87b9 | 3091 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3092 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3093 | u64 *pte, __pte; |
645c4c8d | 3094 | |
132bd68f JR |
3095 | if (domain->mode == PAGE_MODE_NONE) |
3096 | return iova; | |
3097 | ||
3039ca1b | 3098 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3099 | |
a6d41a40 | 3100 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3101 | return 0; |
3102 | ||
b24b1b63 JR |
3103 | offset_mask = pte_pgsize - 1; |
3104 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3105 | |
b24b1b63 | 3106 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3107 | } |
3108 | ||
ab636481 | 3109 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3110 | { |
80a506b8 JR |
3111 | switch (cap) { |
3112 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3113 | return true; |
bdddadcb | 3114 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3115 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3116 | case IOMMU_CAP_NOEXEC: |
3117 | return false; | |
80a506b8 JR |
3118 | } |
3119 | ||
ab636481 | 3120 | return false; |
dbb9fd86 SY |
3121 | } |
3122 | ||
35cf248f JR |
3123 | static void amd_iommu_get_dm_regions(struct device *dev, |
3124 | struct list_head *head) | |
3125 | { | |
3126 | struct unity_map_entry *entry; | |
7aba6cb9 | 3127 | int devid; |
35cf248f JR |
3128 | |
3129 | devid = get_device_id(dev); | |
9ee35e4c | 3130 | if (devid < 0) |
7aba6cb9 | 3131 | return; |
35cf248f JR |
3132 | |
3133 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3134 | struct iommu_dm_region *region; | |
3135 | ||
3136 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3137 | continue; | |
3138 | ||
3139 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3140 | if (!region) { | |
3141 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3142 | dev_name(dev)); | |
3143 | return; | |
3144 | } | |
3145 | ||
3146 | region->start = entry->address_start; | |
3147 | region->length = entry->address_end - entry->address_start; | |
3148 | if (entry->prot & IOMMU_PROT_IR) | |
3149 | region->prot |= IOMMU_READ; | |
3150 | if (entry->prot & IOMMU_PROT_IW) | |
3151 | region->prot |= IOMMU_WRITE; | |
3152 | ||
3153 | list_add_tail(®ion->list, head); | |
3154 | } | |
3155 | } | |
3156 | ||
3157 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3158 | struct list_head *head) | |
3159 | { | |
3160 | struct iommu_dm_region *entry, *next; | |
3161 | ||
3162 | list_for_each_entry_safe(entry, next, head, list) | |
3163 | kfree(entry); | |
3164 | } | |
3165 | ||
8d54d6c8 JR |
3166 | static void amd_iommu_apply_dm_region(struct device *dev, |
3167 | struct iommu_domain *domain, | |
3168 | struct iommu_dm_region *region) | |
3169 | { | |
b3311b06 | 3170 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3171 | unsigned long start, end; |
3172 | ||
3173 | start = IOVA_PFN(region->start); | |
3174 | end = IOVA_PFN(region->start + region->length); | |
3175 | ||
3176 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3177 | } | |
3178 | ||
b22f6434 | 3179 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3180 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3181 | .domain_alloc = amd_iommu_domain_alloc, |
3182 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3183 | .attach_dev = amd_iommu_attach_device, |
3184 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3185 | .map = amd_iommu_map, |
3186 | .unmap = amd_iommu_unmap, | |
315786eb | 3187 | .map_sg = default_iommu_map_sg, |
26961efe | 3188 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3189 | .add_device = amd_iommu_add_device, |
3190 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3191 | .device_group = amd_iommu_device_group, |
35cf248f JR |
3192 | .get_dm_regions = amd_iommu_get_dm_regions, |
3193 | .put_dm_regions = amd_iommu_put_dm_regions, | |
8d54d6c8 | 3194 | .apply_dm_region = amd_iommu_apply_dm_region, |
aa3de9c0 | 3195 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3196 | }; |
3197 | ||
0feae533 JR |
3198 | /***************************************************************************** |
3199 | * | |
3200 | * The next functions do a basic initialization of IOMMU for pass through | |
3201 | * mode | |
3202 | * | |
3203 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3204 | * DMA-API translation. | |
3205 | * | |
3206 | *****************************************************************************/ | |
3207 | ||
72e1dcc4 JR |
3208 | /* IOMMUv2 specific functions */ |
3209 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3210 | { | |
3211 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3212 | } | |
3213 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3214 | ||
3215 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3216 | { | |
3217 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3218 | } | |
3219 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3220 | |
3221 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3222 | { | |
3f4b87b9 | 3223 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3224 | unsigned long flags; |
3225 | ||
3226 | spin_lock_irqsave(&domain->lock, flags); | |
3227 | ||
3228 | /* Update data structure */ | |
3229 | domain->mode = PAGE_MODE_NONE; | |
3230 | domain->updated = true; | |
3231 | ||
3232 | /* Make changes visible to IOMMUs */ | |
3233 | update_domain(domain); | |
3234 | ||
3235 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3236 | free_pagetable(domain); | |
3237 | ||
3238 | spin_unlock_irqrestore(&domain->lock, flags); | |
3239 | } | |
3240 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3241 | |
3242 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3243 | { | |
3f4b87b9 | 3244 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3245 | unsigned long flags; |
3246 | int levels, ret; | |
3247 | ||
3248 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3249 | return -EINVAL; | |
3250 | ||
3251 | /* Number of GCR3 table levels required */ | |
3252 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3253 | levels += 1; | |
3254 | ||
3255 | if (levels > amd_iommu_max_glx_val) | |
3256 | return -EINVAL; | |
3257 | ||
3258 | spin_lock_irqsave(&domain->lock, flags); | |
3259 | ||
3260 | /* | |
3261 | * Save us all sanity checks whether devices already in the | |
3262 | * domain support IOMMUv2. Just force that the domain has no | |
3263 | * devices attached when it is switched into IOMMUv2 mode. | |
3264 | */ | |
3265 | ret = -EBUSY; | |
3266 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3267 | goto out; | |
3268 | ||
3269 | ret = -ENOMEM; | |
3270 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3271 | if (domain->gcr3_tbl == NULL) | |
3272 | goto out; | |
3273 | ||
3274 | domain->glx = levels; | |
3275 | domain->flags |= PD_IOMMUV2_MASK; | |
3276 | domain->updated = true; | |
3277 | ||
3278 | update_domain(domain); | |
3279 | ||
3280 | ret = 0; | |
3281 | ||
3282 | out: | |
3283 | spin_unlock_irqrestore(&domain->lock, flags); | |
3284 | ||
3285 | return ret; | |
3286 | } | |
3287 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3288 | |
3289 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3290 | u64 address, bool size) | |
3291 | { | |
3292 | struct iommu_dev_data *dev_data; | |
3293 | struct iommu_cmd cmd; | |
3294 | int i, ret; | |
3295 | ||
3296 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3297 | return -EINVAL; | |
3298 | ||
3299 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3300 | ||
3301 | /* | |
3302 | * IOMMU TLB needs to be flushed before Device TLB to | |
3303 | * prevent device TLB refill from IOMMU TLB | |
3304 | */ | |
3305 | for (i = 0; i < amd_iommus_present; ++i) { | |
3306 | if (domain->dev_iommu[i] == 0) | |
3307 | continue; | |
3308 | ||
3309 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3310 | if (ret != 0) | |
3311 | goto out; | |
3312 | } | |
3313 | ||
3314 | /* Wait until IOMMU TLB flushes are complete */ | |
3315 | domain_flush_complete(domain); | |
3316 | ||
3317 | /* Now flush device TLBs */ | |
3318 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3319 | struct amd_iommu *iommu; | |
3320 | int qdep; | |
3321 | ||
1c1cc454 JR |
3322 | /* |
3323 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3324 | * domain. | |
3325 | */ | |
3326 | if (!dev_data->ats.enabled) | |
3327 | continue; | |
22e266c7 JR |
3328 | |
3329 | qdep = dev_data->ats.qdep; | |
3330 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3331 | ||
3332 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3333 | qdep, address, size); | |
3334 | ||
3335 | ret = iommu_queue_command(iommu, &cmd); | |
3336 | if (ret != 0) | |
3337 | goto out; | |
3338 | } | |
3339 | ||
3340 | /* Wait until all device TLBs are flushed */ | |
3341 | domain_flush_complete(domain); | |
3342 | ||
3343 | ret = 0; | |
3344 | ||
3345 | out: | |
3346 | ||
3347 | return ret; | |
3348 | } | |
3349 | ||
3350 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3351 | u64 address) | |
3352 | { | |
3353 | return __flush_pasid(domain, pasid, address, false); | |
3354 | } | |
3355 | ||
3356 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3357 | u64 address) | |
3358 | { | |
3f4b87b9 | 3359 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3360 | unsigned long flags; |
3361 | int ret; | |
3362 | ||
3363 | spin_lock_irqsave(&domain->lock, flags); | |
3364 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3365 | spin_unlock_irqrestore(&domain->lock, flags); | |
3366 | ||
3367 | return ret; | |
3368 | } | |
3369 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3370 | ||
3371 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3372 | { | |
3373 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3374 | true); | |
3375 | } | |
3376 | ||
3377 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3378 | { | |
3f4b87b9 | 3379 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3380 | unsigned long flags; |
3381 | int ret; | |
3382 | ||
3383 | spin_lock_irqsave(&domain->lock, flags); | |
3384 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3385 | spin_unlock_irqrestore(&domain->lock, flags); | |
3386 | ||
3387 | return ret; | |
3388 | } | |
3389 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3390 | ||
b16137b1 JR |
3391 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3392 | { | |
3393 | int index; | |
3394 | u64 *pte; | |
3395 | ||
3396 | while (true) { | |
3397 | ||
3398 | index = (pasid >> (9 * level)) & 0x1ff; | |
3399 | pte = &root[index]; | |
3400 | ||
3401 | if (level == 0) | |
3402 | break; | |
3403 | ||
3404 | if (!(*pte & GCR3_VALID)) { | |
3405 | if (!alloc) | |
3406 | return NULL; | |
3407 | ||
3408 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3409 | if (root == NULL) | |
3410 | return NULL; | |
3411 | ||
3412 | *pte = __pa(root) | GCR3_VALID; | |
3413 | } | |
3414 | ||
3415 | root = __va(*pte & PAGE_MASK); | |
3416 | ||
3417 | level -= 1; | |
3418 | } | |
3419 | ||
3420 | return pte; | |
3421 | } | |
3422 | ||
3423 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3424 | unsigned long cr3) | |
3425 | { | |
3426 | u64 *pte; | |
3427 | ||
3428 | if (domain->mode != PAGE_MODE_NONE) | |
3429 | return -EINVAL; | |
3430 | ||
3431 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3432 | if (pte == NULL) | |
3433 | return -ENOMEM; | |
3434 | ||
3435 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3436 | ||
3437 | return __amd_iommu_flush_tlb(domain, pasid); | |
3438 | } | |
3439 | ||
3440 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3441 | { | |
3442 | u64 *pte; | |
3443 | ||
3444 | if (domain->mode != PAGE_MODE_NONE) | |
3445 | return -EINVAL; | |
3446 | ||
3447 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3448 | if (pte == NULL) | |
3449 | return 0; | |
3450 | ||
3451 | *pte = 0; | |
3452 | ||
3453 | return __amd_iommu_flush_tlb(domain, pasid); | |
3454 | } | |
3455 | ||
3456 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3457 | unsigned long cr3) | |
3458 | { | |
3f4b87b9 | 3459 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3460 | unsigned long flags; |
3461 | int ret; | |
3462 | ||
3463 | spin_lock_irqsave(&domain->lock, flags); | |
3464 | ret = __set_gcr3(domain, pasid, cr3); | |
3465 | spin_unlock_irqrestore(&domain->lock, flags); | |
3466 | ||
3467 | return ret; | |
3468 | } | |
3469 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3470 | ||
3471 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3472 | { | |
3f4b87b9 | 3473 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3474 | unsigned long flags; |
3475 | int ret; | |
3476 | ||
3477 | spin_lock_irqsave(&domain->lock, flags); | |
3478 | ret = __clear_gcr3(domain, pasid); | |
3479 | spin_unlock_irqrestore(&domain->lock, flags); | |
3480 | ||
3481 | return ret; | |
3482 | } | |
3483 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3484 | |
3485 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3486 | int status, int tag) | |
3487 | { | |
3488 | struct iommu_dev_data *dev_data; | |
3489 | struct amd_iommu *iommu; | |
3490 | struct iommu_cmd cmd; | |
3491 | ||
3492 | dev_data = get_dev_data(&pdev->dev); | |
3493 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3494 | ||
3495 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3496 | tag, dev_data->pri_tlp); | |
3497 | ||
3498 | return iommu_queue_command(iommu, &cmd); | |
3499 | } | |
3500 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3501 | |
3502 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3503 | { | |
3f4b87b9 | 3504 | struct protection_domain *pdomain; |
f3572db8 | 3505 | |
3f4b87b9 JR |
3506 | pdomain = get_domain(&pdev->dev); |
3507 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3508 | return NULL; |
3509 | ||
3510 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3511 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3512 | return NULL; |
3513 | ||
3f4b87b9 | 3514 | return &pdomain->domain; |
f3572db8 JR |
3515 | } |
3516 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3517 | |
3518 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3519 | { | |
3520 | struct iommu_dev_data *dev_data; | |
3521 | ||
3522 | if (!amd_iommu_v2_supported()) | |
3523 | return; | |
3524 | ||
3525 | dev_data = get_dev_data(&pdev->dev); | |
3526 | dev_data->errata |= (1 << erratum); | |
3527 | } | |
3528 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3529 | |
3530 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3531 | struct amd_iommu_device_info *info) | |
3532 | { | |
3533 | int max_pasids; | |
3534 | int pos; | |
3535 | ||
3536 | if (pdev == NULL || info == NULL) | |
3537 | return -EINVAL; | |
3538 | ||
3539 | if (!amd_iommu_v2_supported()) | |
3540 | return -EINVAL; | |
3541 | ||
3542 | memset(info, 0, sizeof(*info)); | |
3543 | ||
3544 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3545 | if (pos) | |
3546 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3547 | ||
3548 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3549 | if (pos) | |
3550 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3551 | ||
3552 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3553 | if (pos) { | |
3554 | int features; | |
3555 | ||
3556 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3557 | max_pasids = min(max_pasids, (1 << 20)); | |
3558 | ||
3559 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3560 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3561 | ||
3562 | features = pci_pasid_features(pdev); | |
3563 | if (features & PCI_PASID_CAP_EXEC) | |
3564 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3565 | if (features & PCI_PASID_CAP_PRIV) | |
3566 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3567 | } | |
3568 | ||
3569 | return 0; | |
3570 | } | |
3571 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3572 | |
3573 | #ifdef CONFIG_IRQ_REMAP | |
3574 | ||
3575 | /***************************************************************************** | |
3576 | * | |
3577 | * Interrupt Remapping Implementation | |
3578 | * | |
3579 | *****************************************************************************/ | |
3580 | ||
7c71d306 JL |
3581 | static struct irq_chip amd_ir_chip; |
3582 | ||
2b324506 JR |
3583 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3584 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3585 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3586 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3587 | ||
3588 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3589 | { | |
3590 | u64 dte; | |
3591 | ||
3592 | dte = amd_iommu_dev_table[devid].data[2]; | |
3593 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3594 | dte |= virt_to_phys(table->table); | |
3595 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3596 | dte |= DTE_IRQ_TABLE_LEN; | |
3597 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3598 | ||
3599 | amd_iommu_dev_table[devid].data[2] = dte; | |
3600 | } | |
3601 | ||
2b324506 JR |
3602 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) |
3603 | { | |
3604 | struct irq_remap_table *table = NULL; | |
3605 | struct amd_iommu *iommu; | |
3606 | unsigned long flags; | |
3607 | u16 alias; | |
3608 | ||
3609 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3610 | ||
3611 | iommu = amd_iommu_rlookup_table[devid]; | |
3612 | if (!iommu) | |
3613 | goto out_unlock; | |
3614 | ||
3615 | table = irq_lookup_table[devid]; | |
3616 | if (table) | |
3617 | goto out; | |
3618 | ||
3619 | alias = amd_iommu_alias_table[devid]; | |
3620 | table = irq_lookup_table[alias]; | |
3621 | if (table) { | |
3622 | irq_lookup_table[devid] = table; | |
3623 | set_dte_irq_entry(devid, table); | |
3624 | iommu_flush_dte(iommu, devid); | |
3625 | goto out; | |
3626 | } | |
3627 | ||
3628 | /* Nothing there yet, allocate new irq remapping table */ | |
3629 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3630 | if (!table) | |
3631 | goto out; | |
3632 | ||
197887f0 JR |
3633 | /* Initialize table spin-lock */ |
3634 | spin_lock_init(&table->lock); | |
3635 | ||
2b324506 JR |
3636 | if (ioapic) |
3637 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3638 | table->min_index = 32; | |
3639 | ||
3640 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3641 | if (!table->table) { | |
3642 | kfree(table); | |
821f0f68 | 3643 | table = NULL; |
2b324506 JR |
3644 | goto out; |
3645 | } | |
3646 | ||
77bdab46 SS |
3647 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3648 | memset(table->table, 0, | |
3649 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3650 | else | |
3651 | memset(table->table, 0, | |
3652 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
2b324506 JR |
3653 | |
3654 | if (ioapic) { | |
3655 | int i; | |
3656 | ||
3657 | for (i = 0; i < 32; ++i) | |
77bdab46 | 3658 | iommu->irte_ops->set_allocated(table, i); |
2b324506 JR |
3659 | } |
3660 | ||
3661 | irq_lookup_table[devid] = table; | |
3662 | set_dte_irq_entry(devid, table); | |
3663 | iommu_flush_dte(iommu, devid); | |
3664 | if (devid != alias) { | |
3665 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3666 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3667 | iommu_flush_dte(iommu, alias); |
3668 | } | |
3669 | ||
3670 | out: | |
3671 | iommu_completion_wait(iommu); | |
3672 | ||
3673 | out_unlock: | |
3674 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3675 | ||
3676 | return table; | |
3677 | } | |
3678 | ||
3c3d4f90 | 3679 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3680 | { |
3681 | struct irq_remap_table *table; | |
3682 | unsigned long flags; | |
3683 | int index, c; | |
77bdab46 SS |
3684 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3685 | ||
3686 | if (!iommu) | |
3687 | return -ENODEV; | |
2b324506 JR |
3688 | |
3689 | table = get_irq_table(devid, false); | |
3690 | if (!table) | |
3691 | return -ENODEV; | |
3692 | ||
3693 | spin_lock_irqsave(&table->lock, flags); | |
3694 | ||
3695 | /* Scan table for free entries */ | |
3696 | for (c = 0, index = table->min_index; | |
3697 | index < MAX_IRQS_PER_TABLE; | |
3698 | ++index) { | |
77bdab46 | 3699 | if (!iommu->irte_ops->is_allocated(table, index)) |
2b324506 JR |
3700 | c += 1; |
3701 | else | |
3702 | c = 0; | |
3703 | ||
3704 | if (c == count) { | |
2b324506 | 3705 | for (; c != 0; --c) |
77bdab46 | 3706 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3707 | |
3708 | index -= count - 1; | |
2b324506 JR |
3709 | goto out; |
3710 | } | |
3711 | } | |
3712 | ||
3713 | index = -ENOSPC; | |
3714 | ||
3715 | out: | |
3716 | spin_unlock_irqrestore(&table->lock, flags); | |
3717 | ||
3718 | return index; | |
3719 | } | |
3720 | ||
b9fc6b56 SS |
3721 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3722 | struct amd_ir_data *data) | |
2b324506 JR |
3723 | { |
3724 | struct irq_remap_table *table; | |
3725 | struct amd_iommu *iommu; | |
3726 | unsigned long flags; | |
880ac60e | 3727 | struct irte_ga *entry; |
2b324506 JR |
3728 | |
3729 | iommu = amd_iommu_rlookup_table[devid]; | |
3730 | if (iommu == NULL) | |
3731 | return -EINVAL; | |
3732 | ||
3733 | table = get_irq_table(devid, false); | |
3734 | if (!table) | |
3735 | return -ENOMEM; | |
3736 | ||
3737 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e SS |
3738 | |
3739 | entry = (struct irte_ga *)table->table; | |
3740 | entry = &entry[index]; | |
3741 | entry->lo.fields_remap.valid = 0; | |
3742 | entry->hi.val = irte->hi.val; | |
3743 | entry->lo.val = irte->lo.val; | |
3744 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3745 | if (data) |
3746 | data->ref = entry; | |
880ac60e SS |
3747 | |
3748 | spin_unlock_irqrestore(&table->lock, flags); | |
3749 | ||
3750 | iommu_flush_irt(iommu, devid); | |
3751 | iommu_completion_wait(iommu); | |
3752 | ||
3753 | return 0; | |
3754 | } | |
3755 | ||
3756 | static int modify_irte(u16 devid, int index, union irte *irte) | |
3757 | { | |
3758 | struct irq_remap_table *table; | |
3759 | struct amd_iommu *iommu; | |
3760 | unsigned long flags; | |
3761 | ||
3762 | iommu = amd_iommu_rlookup_table[devid]; | |
3763 | if (iommu == NULL) | |
3764 | return -EINVAL; | |
3765 | ||
3766 | table = get_irq_table(devid, false); | |
3767 | if (!table) | |
3768 | return -ENOMEM; | |
3769 | ||
3770 | spin_lock_irqsave(&table->lock, flags); | |
3771 | table->table[index] = irte->val; | |
2b324506 JR |
3772 | spin_unlock_irqrestore(&table->lock, flags); |
3773 | ||
3774 | iommu_flush_irt(iommu, devid); | |
3775 | iommu_completion_wait(iommu); | |
3776 | ||
3777 | return 0; | |
3778 | } | |
3779 | ||
3780 | static void free_irte(u16 devid, int index) | |
3781 | { | |
3782 | struct irq_remap_table *table; | |
3783 | struct amd_iommu *iommu; | |
3784 | unsigned long flags; | |
3785 | ||
3786 | iommu = amd_iommu_rlookup_table[devid]; | |
3787 | if (iommu == NULL) | |
3788 | return; | |
3789 | ||
3790 | table = get_irq_table(devid, false); | |
3791 | if (!table) | |
3792 | return; | |
3793 | ||
3794 | spin_lock_irqsave(&table->lock, flags); | |
77bdab46 | 3795 | iommu->irte_ops->clear_allocated(table, index); |
2b324506 JR |
3796 | spin_unlock_irqrestore(&table->lock, flags); |
3797 | ||
3798 | iommu_flush_irt(iommu, devid); | |
3799 | iommu_completion_wait(iommu); | |
3800 | } | |
3801 | ||
880ac60e SS |
3802 | static void irte_prepare(void *entry, |
3803 | u32 delivery_mode, u32 dest_mode, | |
3804 | u8 vector, u32 dest_apicid) | |
3805 | { | |
3806 | union irte *irte = (union irte *) entry; | |
3807 | ||
3808 | irte->val = 0; | |
3809 | irte->fields.vector = vector; | |
3810 | irte->fields.int_type = delivery_mode; | |
3811 | irte->fields.destination = dest_apicid; | |
3812 | irte->fields.dm = dest_mode; | |
3813 | irte->fields.valid = 1; | |
3814 | } | |
3815 | ||
3816 | static void irte_ga_prepare(void *entry, | |
3817 | u32 delivery_mode, u32 dest_mode, | |
3818 | u8 vector, u32 dest_apicid) | |
3819 | { | |
3820 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3821 | ||
3822 | irte->lo.val = 0; | |
3823 | irte->hi.val = 0; | |
3824 | irte->lo.fields_remap.guest_mode = 0; | |
3825 | irte->lo.fields_remap.int_type = delivery_mode; | |
3826 | irte->lo.fields_remap.dm = dest_mode; | |
3827 | irte->hi.fields.vector = vector; | |
3828 | irte->lo.fields_remap.destination = dest_apicid; | |
3829 | irte->lo.fields_remap.valid = 1; | |
3830 | } | |
3831 | ||
3832 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3833 | { | |
3834 | union irte *irte = (union irte *) entry; | |
3835 | ||
3836 | irte->fields.valid = 1; | |
3837 | modify_irte(devid, index, irte); | |
3838 | } | |
3839 | ||
3840 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3841 | { | |
3842 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3843 | ||
3844 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3845 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3846 | } |
3847 | ||
3848 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3849 | { | |
3850 | union irte *irte = (union irte *) entry; | |
3851 | ||
3852 | irte->fields.valid = 0; | |
3853 | modify_irte(devid, index, irte); | |
3854 | } | |
3855 | ||
3856 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3857 | { | |
3858 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3859 | ||
3860 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3861 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3862 | } |
3863 | ||
3864 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3865 | u8 vector, u32 dest_apicid) | |
3866 | { | |
3867 | union irte *irte = (union irte *) entry; | |
3868 | ||
3869 | irte->fields.vector = vector; | |
3870 | irte->fields.destination = dest_apicid; | |
3871 | modify_irte(devid, index, irte); | |
3872 | } | |
3873 | ||
3874 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3875 | u8 vector, u32 dest_apicid) | |
3876 | { | |
3877 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3878 | ||
3879 | irte->hi.fields.vector = vector; | |
3880 | irte->lo.fields_remap.destination = dest_apicid; | |
3881 | irte->lo.fields_remap.guest_mode = 0; | |
b9fc6b56 | 3882 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3883 | } |
3884 | ||
77bdab46 | 3885 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3886 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3887 | { | |
3888 | table->table[index] = IRTE_ALLOCATED; | |
3889 | } | |
3890 | ||
3891 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3892 | { | |
3893 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3894 | struct irte_ga *irte = &ptr[index]; | |
3895 | ||
3896 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3897 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3898 | irte->hi.fields.vector = 0xff; | |
3899 | } | |
3900 | ||
3901 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3902 | { | |
3903 | union irte *ptr = (union irte *)table->table; | |
3904 | union irte *irte = &ptr[index]; | |
3905 | ||
3906 | return irte->val != 0; | |
3907 | } | |
3908 | ||
3909 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3910 | { | |
3911 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3912 | struct irte_ga *irte = &ptr[index]; | |
3913 | ||
3914 | return irte->hi.fields.vector != 0; | |
3915 | } | |
3916 | ||
3917 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3918 | { | |
3919 | table->table[index] = 0; | |
3920 | } | |
3921 | ||
3922 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3923 | { | |
3924 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3925 | struct irte_ga *irte = &ptr[index]; | |
3926 | ||
3927 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3928 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3929 | } | |
3930 | ||
7c71d306 | 3931 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3932 | { |
7c71d306 | 3933 | int devid = -1; |
5527de74 | 3934 | |
7c71d306 JL |
3935 | switch (info->type) { |
3936 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3937 | devid = get_ioapic_devid(info->ioapic_id); | |
3938 | break; | |
3939 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3940 | devid = get_hpet_devid(info->hpet_id); | |
3941 | break; | |
3942 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3943 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3944 | devid = get_device_id(&info->msi_dev->dev); | |
3945 | break; | |
3946 | default: | |
3947 | BUG_ON(1); | |
3948 | break; | |
3949 | } | |
5527de74 | 3950 | |
7c71d306 JL |
3951 | return devid; |
3952 | } | |
5527de74 | 3953 | |
7c71d306 JL |
3954 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3955 | { | |
3956 | struct amd_iommu *iommu; | |
3957 | int devid; | |
5527de74 | 3958 | |
7c71d306 JL |
3959 | if (!info) |
3960 | return NULL; | |
5527de74 | 3961 | |
7c71d306 JL |
3962 | devid = get_devid(info); |
3963 | if (devid >= 0) { | |
3964 | iommu = amd_iommu_rlookup_table[devid]; | |
3965 | if (iommu) | |
3966 | return iommu->ir_domain; | |
3967 | } | |
5527de74 | 3968 | |
7c71d306 | 3969 | return NULL; |
5527de74 JR |
3970 | } |
3971 | ||
7c71d306 | 3972 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3973 | { |
7c71d306 JL |
3974 | struct amd_iommu *iommu; |
3975 | int devid; | |
5527de74 | 3976 | |
7c71d306 JL |
3977 | if (!info) |
3978 | return NULL; | |
5527de74 | 3979 | |
7c71d306 JL |
3980 | switch (info->type) { |
3981 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3982 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3983 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 3984 | if (devid < 0) |
7aba6cb9 WZ |
3985 | return NULL; |
3986 | ||
1fb260bc DC |
3987 | iommu = amd_iommu_rlookup_table[devid]; |
3988 | if (iommu) | |
3989 | return iommu->msi_domain; | |
7c71d306 JL |
3990 | break; |
3991 | default: | |
3992 | break; | |
3993 | } | |
5527de74 | 3994 | |
7c71d306 JL |
3995 | return NULL; |
3996 | } | |
5527de74 | 3997 | |
6b474b82 | 3998 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3999 | .prepare = amd_iommu_prepare, |
4000 | .enable = amd_iommu_enable, | |
4001 | .disable = amd_iommu_disable, | |
4002 | .reenable = amd_iommu_reenable, | |
4003 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4004 | .get_ir_irq_domain = get_ir_irq_domain, |
4005 | .get_irq_domain = get_irq_domain, | |
4006 | }; | |
5527de74 | 4007 | |
7c71d306 JL |
4008 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4009 | struct irq_cfg *irq_cfg, | |
4010 | struct irq_alloc_info *info, | |
4011 | int devid, int index, int sub_handle) | |
4012 | { | |
4013 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4014 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4015 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4016 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4017 | ||
4018 | if (!iommu) | |
4019 | return; | |
5527de74 | 4020 | |
7c71d306 JL |
4021 | data->irq_2_irte.devid = devid; |
4022 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4023 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4024 | apic->irq_dest_mode, irq_cfg->vector, | |
4025 | irq_cfg->dest_apicid); | |
7c71d306 JL |
4026 | |
4027 | switch (info->type) { | |
4028 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4029 | /* Setup IOAPIC entry */ | |
4030 | entry = info->ioapic_entry; | |
4031 | info->ioapic_entry = NULL; | |
4032 | memset(entry, 0, sizeof(*entry)); | |
4033 | entry->vector = index; | |
4034 | entry->mask = 0; | |
4035 | entry->trigger = info->ioapic_trigger; | |
4036 | entry->polarity = info->ioapic_polarity; | |
4037 | /* Mask level triggered irqs. */ | |
4038 | if (info->ioapic_trigger) | |
4039 | entry->mask = 1; | |
4040 | break; | |
5527de74 | 4041 | |
7c71d306 JL |
4042 | case X86_IRQ_ALLOC_TYPE_HPET: |
4043 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4044 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4045 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4046 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4047 | msg->data = irte_info->index; | |
4048 | break; | |
5527de74 | 4049 | |
7c71d306 JL |
4050 | default: |
4051 | BUG_ON(1); | |
4052 | break; | |
4053 | } | |
5527de74 JR |
4054 | } |
4055 | ||
880ac60e SS |
4056 | struct amd_irte_ops irte_32_ops = { |
4057 | .prepare = irte_prepare, | |
4058 | .activate = irte_activate, | |
4059 | .deactivate = irte_deactivate, | |
4060 | .set_affinity = irte_set_affinity, | |
4061 | .set_allocated = irte_set_allocated, | |
4062 | .is_allocated = irte_is_allocated, | |
4063 | .clear_allocated = irte_clear_allocated, | |
4064 | }; | |
4065 | ||
4066 | struct amd_irte_ops irte_128_ops = { | |
4067 | .prepare = irte_ga_prepare, | |
4068 | .activate = irte_ga_activate, | |
4069 | .deactivate = irte_ga_deactivate, | |
4070 | .set_affinity = irte_ga_set_affinity, | |
4071 | .set_allocated = irte_ga_set_allocated, | |
4072 | .is_allocated = irte_ga_is_allocated, | |
4073 | .clear_allocated = irte_ga_clear_allocated, | |
4074 | }; | |
4075 | ||
7c71d306 JL |
4076 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4077 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4078 | { |
7c71d306 JL |
4079 | struct irq_alloc_info *info = arg; |
4080 | struct irq_data *irq_data; | |
77bdab46 | 4081 | struct amd_ir_data *data = NULL; |
5527de74 | 4082 | struct irq_cfg *cfg; |
7c71d306 JL |
4083 | int i, ret, devid; |
4084 | int index = -1; | |
5527de74 | 4085 | |
7c71d306 JL |
4086 | if (!info) |
4087 | return -EINVAL; | |
4088 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4089 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4090 | return -EINVAL; |
4091 | ||
7c71d306 JL |
4092 | /* |
4093 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4094 | * to support multiple MSI interrupts. | |
4095 | */ | |
4096 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4097 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4098 | |
7c71d306 JL |
4099 | devid = get_devid(info); |
4100 | if (devid < 0) | |
4101 | return -EINVAL; | |
5527de74 | 4102 | |
7c71d306 JL |
4103 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4104 | if (ret < 0) | |
4105 | return ret; | |
0b4d48cb | 4106 | |
7c71d306 JL |
4107 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4108 | if (get_irq_table(devid, true)) | |
4109 | index = info->ioapic_pin; | |
4110 | else | |
4111 | ret = -ENOMEM; | |
4112 | } else { | |
3c3d4f90 | 4113 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
4114 | } |
4115 | if (index < 0) { | |
4116 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
4117 | goto out_free_parent; |
4118 | } | |
0b4d48cb | 4119 | |
7c71d306 JL |
4120 | for (i = 0; i < nr_irqs; i++) { |
4121 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4122 | cfg = irqd_cfg(irq_data); | |
4123 | if (!irq_data || !cfg) { | |
4124 | ret = -EINVAL; | |
4125 | goto out_free_data; | |
4126 | } | |
0b4d48cb | 4127 | |
a130e69f JR |
4128 | ret = -ENOMEM; |
4129 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4130 | if (!data) | |
4131 | goto out_free_data; | |
4132 | ||
77bdab46 SS |
4133 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4134 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4135 | else | |
4136 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4137 | GFP_KERNEL); | |
4138 | if (!data->entry) { | |
4139 | kfree(data); | |
4140 | goto out_free_data; | |
4141 | } | |
4142 | ||
7c71d306 JL |
4143 | irq_data->hwirq = (devid << 16) + i; |
4144 | irq_data->chip_data = data; | |
4145 | irq_data->chip = &amd_ir_chip; | |
4146 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4147 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4148 | } | |
a130e69f | 4149 | |
7c71d306 | 4150 | return 0; |
0b4d48cb | 4151 | |
7c71d306 JL |
4152 | out_free_data: |
4153 | for (i--; i >= 0; i--) { | |
4154 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4155 | if (irq_data) | |
4156 | kfree(irq_data->chip_data); | |
4157 | } | |
4158 | for (i = 0; i < nr_irqs; i++) | |
4159 | free_irte(devid, index + i); | |
4160 | out_free_parent: | |
4161 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4162 | return ret; | |
0b4d48cb JR |
4163 | } |
4164 | ||
7c71d306 JL |
4165 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4166 | unsigned int nr_irqs) | |
0b4d48cb | 4167 | { |
7c71d306 JL |
4168 | struct irq_2_irte *irte_info; |
4169 | struct irq_data *irq_data; | |
4170 | struct amd_ir_data *data; | |
4171 | int i; | |
0b4d48cb | 4172 | |
7c71d306 JL |
4173 | for (i = 0; i < nr_irqs; i++) { |
4174 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4175 | if (irq_data && irq_data->chip_data) { | |
4176 | data = irq_data->chip_data; | |
4177 | irte_info = &data->irq_2_irte; | |
4178 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4179 | kfree(data->entry); |
7c71d306 JL |
4180 | kfree(data); |
4181 | } | |
4182 | } | |
4183 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4184 | } | |
0b4d48cb | 4185 | |
7c71d306 JL |
4186 | static void irq_remapping_activate(struct irq_domain *domain, |
4187 | struct irq_data *irq_data) | |
4188 | { | |
4189 | struct amd_ir_data *data = irq_data->chip_data; | |
4190 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4191 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4192 | |
77bdab46 SS |
4193 | if (iommu) |
4194 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4195 | irte_info->index); | |
0b4d48cb JR |
4196 | } |
4197 | ||
7c71d306 JL |
4198 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4199 | struct irq_data *irq_data) | |
0b4d48cb | 4200 | { |
7c71d306 JL |
4201 | struct amd_ir_data *data = irq_data->chip_data; |
4202 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4203 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4204 | |
77bdab46 SS |
4205 | if (iommu) |
4206 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4207 | irte_info->index); | |
7c71d306 | 4208 | } |
0b4d48cb | 4209 | |
7c71d306 JL |
4210 | static struct irq_domain_ops amd_ir_domain_ops = { |
4211 | .alloc = irq_remapping_alloc, | |
4212 | .free = irq_remapping_free, | |
4213 | .activate = irq_remapping_activate, | |
4214 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4215 | }; |
0b4d48cb | 4216 | |
b9fc6b56 SS |
4217 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4218 | { | |
4219 | struct amd_iommu *iommu; | |
4220 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4221 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4222 | struct amd_ir_data *ir_data = data->chip_data; | |
4223 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4224 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4225 | ||
4226 | pi_data->ir_data = ir_data; | |
4227 | ||
4228 | /* Note: | |
4229 | * SVM tries to set up for VAPIC mode, but we are in | |
4230 | * legacy mode. So, we force legacy mode instead. | |
4231 | */ | |
4232 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
4233 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", | |
4234 | __func__); | |
4235 | pi_data->is_guest_mode = false; | |
4236 | } | |
4237 | ||
4238 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4239 | if (iommu == NULL) | |
4240 | return -EINVAL; | |
4241 | ||
4242 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4243 | if (pi_data->is_guest_mode) { | |
4244 | /* Setting */ | |
4245 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4246 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
4247 | irte->lo.fields_vapic.guest_mode = 1; | |
4248 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4249 | ||
4250 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4251 | } else { | |
4252 | /* Un-Setting */ | |
4253 | struct irq_cfg *cfg = irqd_cfg(data); | |
4254 | ||
4255 | irte->hi.val = 0; | |
4256 | irte->lo.val = 0; | |
4257 | irte->hi.fields.vector = cfg->vector; | |
4258 | irte->lo.fields_remap.guest_mode = 0; | |
4259 | irte->lo.fields_remap.destination = cfg->dest_apicid; | |
4260 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; | |
4261 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4262 | ||
4263 | /* | |
4264 | * This communicates the ga_tag back to the caller | |
4265 | * so that it can do all the necessary clean up. | |
4266 | */ | |
4267 | ir_data->cached_ga_tag = 0; | |
4268 | } | |
4269 | ||
4270 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4271 | } | |
4272 | ||
7c71d306 JL |
4273 | static int amd_ir_set_affinity(struct irq_data *data, |
4274 | const struct cpumask *mask, bool force) | |
4275 | { | |
4276 | struct amd_ir_data *ir_data = data->chip_data; | |
4277 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4278 | struct irq_cfg *cfg = irqd_cfg(data); | |
4279 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4280 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4281 | int ret; |
0b4d48cb | 4282 | |
77bdab46 SS |
4283 | if (!iommu) |
4284 | return -ENODEV; | |
4285 | ||
7c71d306 JL |
4286 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4287 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4288 | return ret; | |
0b4d48cb | 4289 | |
7c71d306 JL |
4290 | /* |
4291 | * Atomically updates the IRTE with the new destination, vector | |
4292 | * and flushes the interrupt entry cache. | |
4293 | */ | |
77bdab46 SS |
4294 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, |
4295 | irte_info->index, cfg->vector, cfg->dest_apicid); | |
0b4d48cb | 4296 | |
7c71d306 JL |
4297 | /* |
4298 | * After this point, all the interrupts will start arriving | |
4299 | * at the new destination. So, time to cleanup the previous | |
4300 | * vector allocation. | |
4301 | */ | |
c6c2002b | 4302 | send_cleanup_vector(cfg); |
7c71d306 JL |
4303 | |
4304 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4305 | } |
4306 | ||
7c71d306 | 4307 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4308 | { |
7c71d306 | 4309 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4310 | |
7c71d306 JL |
4311 | *msg = ir_data->msi_entry; |
4312 | } | |
d976195c | 4313 | |
7c71d306 JL |
4314 | static struct irq_chip amd_ir_chip = { |
4315 | .irq_ack = ir_ack_apic_edge, | |
4316 | .irq_set_affinity = amd_ir_set_affinity, | |
b9fc6b56 | 4317 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, |
7c71d306 JL |
4318 | .irq_compose_msi_msg = ir_compose_msi_msg, |
4319 | }; | |
d976195c | 4320 | |
7c71d306 JL |
4321 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4322 | { | |
4323 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4324 | if (!iommu->ir_domain) | |
4325 | return -ENOMEM; | |
d976195c | 4326 | |
7c71d306 JL |
4327 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4328 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4329 | |
4330 | return 0; | |
4331 | } | |
8dbea3fd SS |
4332 | |
4333 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4334 | { | |
4335 | unsigned long flags; | |
4336 | struct amd_iommu *iommu; | |
4337 | struct irq_remap_table *irt; | |
4338 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
4339 | int devid = ir_data->irq_2_irte.devid; | |
4340 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4341 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4342 | ||
4343 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4344 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4345 | return 0; | |
4346 | ||
4347 | iommu = amd_iommu_rlookup_table[devid]; | |
4348 | if (!iommu) | |
4349 | return -ENODEV; | |
4350 | ||
4351 | irt = get_irq_table(devid, false); | |
4352 | if (!irt) | |
4353 | return -ENODEV; | |
4354 | ||
4355 | spin_lock_irqsave(&irt->lock, flags); | |
4356 | ||
4357 | if (ref->lo.fields_vapic.guest_mode) { | |
4358 | if (cpu >= 0) | |
4359 | ref->lo.fields_vapic.destination = cpu; | |
4360 | ref->lo.fields_vapic.is_run = is_run; | |
4361 | barrier(); | |
4362 | } | |
4363 | ||
4364 | spin_unlock_irqrestore(&irt->lock, flags); | |
4365 | ||
4366 | iommu_flush_irt(iommu, devid); | |
4367 | iommu_completion_wait(iommu); | |
4368 | return 0; | |
4369 | } | |
4370 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4371 | #endif |