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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 JR |
56 | |
57 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
58 | ||
815b33fd | 59 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 60 | |
307d5851 JR |
61 | /* IO virtual address start page frame number */ |
62 | #define IOVA_START_PFN (1) | |
63 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
64 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) | |
65 | ||
81cd07b9 JR |
66 | /* Reserved IOVA ranges */ |
67 | #define MSI_RANGE_START (0xfee00000) | |
68 | #define MSI_RANGE_END (0xfeefffff) | |
69 | #define HT_RANGE_START (0xfd00000000ULL) | |
70 | #define HT_RANGE_END (0xffffffffffULL) | |
71 | ||
aa3de9c0 OBC |
72 | /* |
73 | * This bitmap is used to advertise the page sizes our hardware support | |
74 | * to the IOMMU core, which will then use this information to split | |
75 | * physically contiguous memory regions it is mapping into page sizes | |
76 | * that we support. | |
77 | * | |
954e3dd8 | 78 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 79 | */ |
954e3dd8 | 80 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 81 | |
b6c02715 JR |
82 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
83 | ||
8fa5f802 JR |
84 | /* List of all available dev_data structures */ |
85 | static LIST_HEAD(dev_data_list); | |
86 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
87 | ||
6efed63b JR |
88 | LIST_HEAD(ioapic_map); |
89 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 90 | LIST_HEAD(acpihid_map); |
6efed63b | 91 | |
0feae533 JR |
92 | /* |
93 | * Domain for untranslated devices - only allocated | |
94 | * if iommu=pt passed on kernel cmd line. | |
95 | */ | |
b22f6434 | 96 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 97 | |
72e1dcc4 | 98 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 99 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 100 | |
ac1534a5 JR |
101 | static struct dma_map_ops amd_iommu_dma_ops; |
102 | ||
50917e26 JR |
103 | /* |
104 | * This struct contains device specific data for the IOMMU | |
105 | */ | |
106 | struct iommu_dev_data { | |
107 | struct list_head list; /* For domain->dev_list */ | |
108 | struct list_head dev_data_list; /* For global dev_data_list */ | |
50917e26 | 109 | struct protection_domain *domain; /* Domain the device is bound to */ |
50917e26 | 110 | u16 devid; /* PCI Device ID */ |
e3156048 | 111 | u16 alias; /* Alias Device ID */ |
50917e26 | 112 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
1e6a7b04 | 113 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
114 | struct { |
115 | bool enabled; | |
116 | int qdep; | |
117 | } ats; /* ATS state */ | |
118 | bool pri_tlp; /* PASID TLB required for | |
119 | PPR completions */ | |
120 | u32 errata; /* Bitmap for errata to apply */ | |
121 | }; | |
122 | ||
431b2a20 JR |
123 | /* |
124 | * general struct to manage commands send to an IOMMU | |
125 | */ | |
d6449536 | 126 | struct iommu_cmd { |
b6c02715 JR |
127 | u32 data[4]; |
128 | }; | |
129 | ||
05152a04 JR |
130 | struct kmem_cache *amd_iommu_irq_cache; |
131 | ||
04bfdd84 | 132 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 133 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 134 | static void detach_device(struct device *dev); |
c1eee67b | 135 | |
007b74ba JR |
136 | /* |
137 | * Data container for a dma_ops specific protection domain | |
138 | */ | |
139 | struct dma_ops_domain { | |
140 | /* generic protection domain information */ | |
141 | struct protection_domain domain; | |
142 | ||
307d5851 JR |
143 | /* IOVA RB-Tree */ |
144 | struct iova_domain iovad; | |
007b74ba JR |
145 | }; |
146 | ||
81cd07b9 JR |
147 | static struct iova_domain reserved_iova_ranges; |
148 | static struct lock_class_key reserved_rbtree_key; | |
149 | ||
15898bbc JR |
150 | /**************************************************************************** |
151 | * | |
152 | * Helper functions | |
153 | * | |
154 | ****************************************************************************/ | |
155 | ||
2bf9a0a1 WZ |
156 | static inline int match_hid_uid(struct device *dev, |
157 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 158 | { |
2bf9a0a1 WZ |
159 | const char *hid, *uid; |
160 | ||
161 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
162 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
163 | ||
164 | if (!hid || !(*hid)) | |
165 | return -ENODEV; | |
166 | ||
167 | if (!uid || !(*uid)) | |
168 | return strcmp(hid, entry->hid); | |
169 | ||
170 | if (!(*entry->uid)) | |
171 | return strcmp(hid, entry->hid); | |
172 | ||
173 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
174 | } |
175 | ||
2bf9a0a1 | 176 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
177 | { |
178 | struct pci_dev *pdev = to_pci_dev(dev); | |
179 | ||
180 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
181 | } | |
182 | ||
2bf9a0a1 WZ |
183 | static inline int get_acpihid_device_id(struct device *dev, |
184 | struct acpihid_map_entry **entry) | |
185 | { | |
186 | struct acpihid_map_entry *p; | |
187 | ||
188 | list_for_each_entry(p, &acpihid_map, list) { | |
189 | if (!match_hid_uid(dev, p)) { | |
190 | if (entry) | |
191 | *entry = p; | |
192 | return p->devid; | |
193 | } | |
194 | } | |
195 | return -EINVAL; | |
196 | } | |
197 | ||
198 | static inline int get_device_id(struct device *dev) | |
199 | { | |
200 | int devid; | |
201 | ||
202 | if (dev_is_pci(dev)) | |
203 | devid = get_pci_device_id(dev); | |
204 | else | |
205 | devid = get_acpihid_device_id(dev, NULL); | |
206 | ||
207 | return devid; | |
208 | } | |
209 | ||
3f4b87b9 JR |
210 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
211 | { | |
212 | return container_of(dom, struct protection_domain, domain); | |
213 | } | |
214 | ||
f62dda66 | 215 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
216 | { |
217 | struct iommu_dev_data *dev_data; | |
218 | unsigned long flags; | |
219 | ||
220 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
221 | if (!dev_data) | |
222 | return NULL; | |
223 | ||
f62dda66 | 224 | dev_data->devid = devid; |
8fa5f802 JR |
225 | |
226 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
227 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
228 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
229 | ||
230 | return dev_data; | |
231 | } | |
232 | ||
3b03bb74 JR |
233 | static struct iommu_dev_data *search_dev_data(u16 devid) |
234 | { | |
235 | struct iommu_dev_data *dev_data; | |
236 | unsigned long flags; | |
237 | ||
238 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
239 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
240 | if (dev_data->devid == devid) | |
241 | goto out_unlock; | |
242 | } | |
243 | ||
244 | dev_data = NULL; | |
245 | ||
246 | out_unlock: | |
247 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
248 | ||
249 | return dev_data; | |
250 | } | |
251 | ||
e3156048 JR |
252 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
253 | { | |
254 | *(u16 *)data = alias; | |
255 | return 0; | |
256 | } | |
257 | ||
258 | static u16 get_alias(struct device *dev) | |
259 | { | |
260 | struct pci_dev *pdev = to_pci_dev(dev); | |
261 | u16 devid, ivrs_alias, pci_alias; | |
262 | ||
6c0b43df | 263 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 JR |
264 | devid = get_device_id(dev); |
265 | ivrs_alias = amd_iommu_alias_table[devid]; | |
266 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
267 | ||
268 | if (ivrs_alias == pci_alias) | |
269 | return ivrs_alias; | |
270 | ||
271 | /* | |
272 | * DMA alias showdown | |
273 | * | |
274 | * The IVRS is fairly reliable in telling us about aliases, but it | |
275 | * can't know about every screwy device. If we don't have an IVRS | |
276 | * reported alias, use the PCI reported alias. In that case we may | |
277 | * still need to initialize the rlookup and dev_table entries if the | |
278 | * alias is to a non-existent device. | |
279 | */ | |
280 | if (ivrs_alias == devid) { | |
281 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
282 | amd_iommu_rlookup_table[pci_alias] = | |
283 | amd_iommu_rlookup_table[devid]; | |
284 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
285 | amd_iommu_dev_table[devid].data, | |
286 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
287 | } | |
288 | ||
289 | return pci_alias; | |
290 | } | |
291 | ||
292 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
293 | "for device %s[%04x:%04x], kernel reported alias " | |
294 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
295 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
296 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
297 | PCI_FUNC(pci_alias)); | |
298 | ||
299 | /* | |
300 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
301 | * bus, then the IVRS table may know about a quirk that we don't. | |
302 | */ | |
303 | if (pci_alias == devid && | |
304 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 305 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
306 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
307 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
308 | dev_name(dev)); | |
309 | } | |
310 | ||
311 | return ivrs_alias; | |
312 | } | |
313 | ||
3b03bb74 JR |
314 | static struct iommu_dev_data *find_dev_data(u16 devid) |
315 | { | |
316 | struct iommu_dev_data *dev_data; | |
317 | ||
318 | dev_data = search_dev_data(devid); | |
319 | ||
320 | if (dev_data == NULL) | |
321 | dev_data = alloc_dev_data(devid); | |
322 | ||
323 | return dev_data; | |
324 | } | |
325 | ||
657cbb6b JR |
326 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
327 | { | |
328 | return dev->archdata.iommu; | |
329 | } | |
330 | ||
b097d11a WZ |
331 | /* |
332 | * Find or create an IOMMU group for a acpihid device. | |
333 | */ | |
334 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 335 | { |
b097d11a | 336 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 337 | int devid; |
b097d11a WZ |
338 | |
339 | devid = get_acpihid_device_id(dev, &entry); | |
340 | if (devid < 0) | |
341 | return ERR_PTR(devid); | |
342 | ||
343 | list_for_each_entry(p, &acpihid_map, list) { | |
344 | if ((devid == p->devid) && p->group) | |
345 | entry->group = p->group; | |
346 | } | |
347 | ||
348 | if (!entry->group) | |
349 | entry->group = generic_device_group(dev); | |
350 | ||
351 | return entry->group; | |
657cbb6b JR |
352 | } |
353 | ||
5abcdba4 JR |
354 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
355 | { | |
356 | static const int caps[] = { | |
357 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
358 | PCI_EXT_CAP_ID_PRI, |
359 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
360 | }; |
361 | int i, pos; | |
362 | ||
363 | for (i = 0; i < 3; ++i) { | |
364 | pos = pci_find_ext_capability(pdev, caps[i]); | |
365 | if (pos == 0) | |
366 | return false; | |
367 | } | |
368 | ||
369 | return true; | |
370 | } | |
371 | ||
6a113ddc JR |
372 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
373 | { | |
374 | struct iommu_dev_data *dev_data; | |
375 | ||
376 | dev_data = get_dev_data(&pdev->dev); | |
377 | ||
378 | return dev_data->errata & (1 << erratum) ? true : false; | |
379 | } | |
380 | ||
98fc5a69 JR |
381 | /* |
382 | * This function checks if the driver got a valid device from the caller to | |
383 | * avoid dereferencing invalid pointers. | |
384 | */ | |
385 | static bool check_device(struct device *dev) | |
386 | { | |
7aba6cb9 | 387 | int devid; |
98fc5a69 JR |
388 | |
389 | if (!dev || !dev->dma_mask) | |
390 | return false; | |
391 | ||
98fc5a69 | 392 | devid = get_device_id(dev); |
9ee35e4c | 393 | if (devid < 0) |
7aba6cb9 | 394 | return false; |
98fc5a69 JR |
395 | |
396 | /* Out of our scope? */ | |
397 | if (devid > amd_iommu_last_bdf) | |
398 | return false; | |
399 | ||
400 | if (amd_iommu_rlookup_table[devid] == NULL) | |
401 | return false; | |
402 | ||
403 | return true; | |
404 | } | |
405 | ||
25b11ce2 | 406 | static void init_iommu_group(struct device *dev) |
2851db21 | 407 | { |
2851db21 | 408 | struct iommu_group *group; |
2851db21 | 409 | |
65d5352f | 410 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
411 | if (IS_ERR(group)) |
412 | return; | |
413 | ||
0bb6e243 | 414 | iommu_group_put(group); |
eb9c9527 AW |
415 | } |
416 | ||
417 | static int iommu_init_device(struct device *dev) | |
418 | { | |
eb9c9527 | 419 | struct iommu_dev_data *dev_data; |
7aba6cb9 | 420 | int devid; |
eb9c9527 AW |
421 | |
422 | if (dev->archdata.iommu) | |
423 | return 0; | |
424 | ||
7aba6cb9 | 425 | devid = get_device_id(dev); |
9ee35e4c | 426 | if (devid < 0) |
7aba6cb9 WZ |
427 | return devid; |
428 | ||
429 | dev_data = find_dev_data(devid); | |
eb9c9527 AW |
430 | if (!dev_data) |
431 | return -ENOMEM; | |
432 | ||
e3156048 JR |
433 | dev_data->alias = get_alias(dev); |
434 | ||
2bf9a0a1 | 435 | if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { |
5abcdba4 JR |
436 | struct amd_iommu *iommu; |
437 | ||
2bf9a0a1 | 438 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
439 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
440 | } | |
441 | ||
657cbb6b JR |
442 | dev->archdata.iommu = dev_data; |
443 | ||
066f2e98 AW |
444 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
445 | dev); | |
446 | ||
657cbb6b JR |
447 | return 0; |
448 | } | |
449 | ||
26018874 JR |
450 | static void iommu_ignore_device(struct device *dev) |
451 | { | |
7aba6cb9 WZ |
452 | u16 alias; |
453 | int devid; | |
26018874 JR |
454 | |
455 | devid = get_device_id(dev); | |
9ee35e4c | 456 | if (devid < 0) |
7aba6cb9 WZ |
457 | return; |
458 | ||
e3156048 | 459 | alias = get_alias(dev); |
26018874 JR |
460 | |
461 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
462 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
463 | ||
464 | amd_iommu_rlookup_table[devid] = NULL; | |
465 | amd_iommu_rlookup_table[alias] = NULL; | |
466 | } | |
467 | ||
657cbb6b JR |
468 | static void iommu_uninit_device(struct device *dev) |
469 | { | |
7aba6cb9 WZ |
470 | int devid; |
471 | struct iommu_dev_data *dev_data; | |
c1931090 | 472 | |
7aba6cb9 | 473 | devid = get_device_id(dev); |
9ee35e4c | 474 | if (devid < 0) |
7aba6cb9 | 475 | return; |
c1931090 | 476 | |
7aba6cb9 | 477 | dev_data = search_dev_data(devid); |
c1931090 AW |
478 | if (!dev_data) |
479 | return; | |
480 | ||
b6809ee5 JR |
481 | if (dev_data->domain) |
482 | detach_device(dev); | |
483 | ||
066f2e98 AW |
484 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
485 | dev); | |
486 | ||
9dcd6130 AW |
487 | iommu_group_remove_device(dev); |
488 | ||
aafd8ba0 JR |
489 | /* Remove dma-ops */ |
490 | dev->archdata.dma_ops = NULL; | |
491 | ||
8fa5f802 | 492 | /* |
c1931090 AW |
493 | * We keep dev_data around for unplugged devices and reuse it when the |
494 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 495 | */ |
657cbb6b | 496 | } |
b7cc9554 | 497 | |
a80dc3e0 JR |
498 | /**************************************************************************** |
499 | * | |
500 | * Interrupt handling functions | |
501 | * | |
502 | ****************************************************************************/ | |
503 | ||
e3e59876 JR |
504 | static void dump_dte_entry(u16 devid) |
505 | { | |
506 | int i; | |
507 | ||
ee6c2868 JR |
508 | for (i = 0; i < 4; ++i) |
509 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
510 | amd_iommu_dev_table[devid].data[i]); |
511 | } | |
512 | ||
945b4ac4 JR |
513 | static void dump_command(unsigned long phys_addr) |
514 | { | |
515 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
516 | int i; | |
517 | ||
518 | for (i = 0; i < 4; ++i) | |
519 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
520 | } | |
521 | ||
a345b23b | 522 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 523 | { |
3d06fca8 JR |
524 | int type, devid, domid, flags; |
525 | volatile u32 *event = __evt; | |
526 | int count = 0; | |
527 | u64 address; | |
528 | ||
529 | retry: | |
530 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
531 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
532 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
533 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
534 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
535 | ||
536 | if (type == 0) { | |
537 | /* Did we hit the erratum? */ | |
538 | if (++count == LOOP_TIMEOUT) { | |
539 | pr_err("AMD-Vi: No event written to event log\n"); | |
540 | return; | |
541 | } | |
542 | udelay(1); | |
543 | goto retry; | |
544 | } | |
90008ee4 | 545 | |
4c6f40d4 | 546 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
547 | |
548 | switch (type) { | |
549 | case EVENT_TYPE_ILL_DEV: | |
550 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
551 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 552 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 553 | address, flags); |
e3e59876 | 554 | dump_dte_entry(devid); |
90008ee4 JR |
555 | break; |
556 | case EVENT_TYPE_IO_FAULT: | |
557 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
558 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 559 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
560 | domid, address, flags); |
561 | break; | |
562 | case EVENT_TYPE_DEV_TAB_ERR: | |
563 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
564 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 565 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
566 | address, flags); |
567 | break; | |
568 | case EVENT_TYPE_PAGE_TAB_ERR: | |
569 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
570 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 571 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
572 | domid, address, flags); |
573 | break; | |
574 | case EVENT_TYPE_ILL_CMD: | |
575 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 576 | dump_command(address); |
90008ee4 JR |
577 | break; |
578 | case EVENT_TYPE_CMD_HARD_ERR: | |
579 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
580 | "flags=0x%04x]\n", address, flags); | |
581 | break; | |
582 | case EVENT_TYPE_IOTLB_INV_TO: | |
583 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
584 | "address=0x%016llx]\n", | |
c5081cd7 | 585 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
586 | address); |
587 | break; | |
588 | case EVENT_TYPE_INV_DEV_REQ: | |
589 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
590 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 591 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
592 | address, flags); |
593 | break; | |
594 | default: | |
595 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
596 | } | |
3d06fca8 JR |
597 | |
598 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
599 | } |
600 | ||
601 | static void iommu_poll_events(struct amd_iommu *iommu) | |
602 | { | |
603 | u32 head, tail; | |
90008ee4 JR |
604 | |
605 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
606 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
607 | ||
608 | while (head != tail) { | |
a345b23b | 609 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 610 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
611 | } |
612 | ||
613 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
614 | } |
615 | ||
eee53537 | 616 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
617 | { |
618 | struct amd_iommu_fault fault; | |
72e1dcc4 | 619 | |
72e1dcc4 JR |
620 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
621 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
622 | return; | |
623 | } | |
624 | ||
625 | fault.address = raw[1]; | |
626 | fault.pasid = PPR_PASID(raw[0]); | |
627 | fault.device_id = PPR_DEVID(raw[0]); | |
628 | fault.tag = PPR_TAG(raw[0]); | |
629 | fault.flags = PPR_FLAGS(raw[0]); | |
630 | ||
72e1dcc4 JR |
631 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
632 | } | |
633 | ||
634 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
635 | { | |
72e1dcc4 JR |
636 | u32 head, tail; |
637 | ||
638 | if (iommu->ppr_log == NULL) | |
639 | return; | |
640 | ||
72e1dcc4 JR |
641 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
642 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
643 | ||
644 | while (head != tail) { | |
eee53537 JR |
645 | volatile u64 *raw; |
646 | u64 entry[2]; | |
647 | int i; | |
648 | ||
649 | raw = (u64 *)(iommu->ppr_log + head); | |
650 | ||
651 | /* | |
652 | * Hardware bug: Interrupt may arrive before the entry is | |
653 | * written to memory. If this happens we need to wait for the | |
654 | * entry to arrive. | |
655 | */ | |
656 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
657 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
658 | break; | |
659 | udelay(1); | |
660 | } | |
72e1dcc4 | 661 | |
eee53537 JR |
662 | /* Avoid memcpy function-call overhead */ |
663 | entry[0] = raw[0]; | |
664 | entry[1] = raw[1]; | |
72e1dcc4 | 665 | |
eee53537 JR |
666 | /* |
667 | * To detect the hardware bug we need to clear the entry | |
668 | * back to zero. | |
669 | */ | |
670 | raw[0] = raw[1] = 0UL; | |
671 | ||
672 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
673 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
674 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 675 | |
eee53537 JR |
676 | /* Handle PPR entry */ |
677 | iommu_handle_ppr_entry(iommu, entry); | |
678 | ||
eee53537 JR |
679 | /* Refresh ring-buffer information */ |
680 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
681 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
682 | } | |
72e1dcc4 JR |
683 | } |
684 | ||
72fe00f0 | 685 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 686 | { |
3f398bc7 SS |
687 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
688 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 689 | |
3f398bc7 SS |
690 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
691 | /* Enable EVT and PPR interrupts again */ | |
692 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
693 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 694 | |
3f398bc7 SS |
695 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
696 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
697 | iommu_poll_events(iommu); | |
698 | } | |
90008ee4 | 699 | |
3f398bc7 SS |
700 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
701 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
702 | iommu_poll_ppr_log(iommu); | |
703 | } | |
90008ee4 | 704 | |
3f398bc7 SS |
705 | /* |
706 | * Hardware bug: ERBT1312 | |
707 | * When re-enabling interrupt (by writing 1 | |
708 | * to clear the bit), the hardware might also try to set | |
709 | * the interrupt bit in the event status register. | |
710 | * In this scenario, the bit will be set, and disable | |
711 | * subsequent interrupts. | |
712 | * | |
713 | * Workaround: The IOMMU driver should read back the | |
714 | * status register and check if the interrupt bits are cleared. | |
715 | * If not, driver will need to go through the interrupt handler | |
716 | * again and re-clear the bits | |
717 | */ | |
718 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
719 | } | |
90008ee4 | 720 | return IRQ_HANDLED; |
a80dc3e0 JR |
721 | } |
722 | ||
72fe00f0 JR |
723 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
724 | { | |
725 | return IRQ_WAKE_THREAD; | |
726 | } | |
727 | ||
431b2a20 JR |
728 | /**************************************************************************** |
729 | * | |
730 | * IOMMU command queuing functions | |
731 | * | |
732 | ****************************************************************************/ | |
733 | ||
ac0ea6e9 JR |
734 | static int wait_on_sem(volatile u64 *sem) |
735 | { | |
736 | int i = 0; | |
737 | ||
738 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
739 | udelay(1); | |
740 | i += 1; | |
741 | } | |
742 | ||
743 | if (i == LOOP_TIMEOUT) { | |
744 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
745 | return -EIO; | |
746 | } | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
751 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
752 | struct iommu_cmd *cmd, | |
753 | u32 tail) | |
a19ae1ec | 754 | { |
a19ae1ec JR |
755 | u8 *target; |
756 | ||
8a7c5ef3 | 757 | target = iommu->cmd_buf + tail; |
deba4bce | 758 | tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 JR |
759 | |
760 | /* Copy command to buffer */ | |
761 | memcpy(target, cmd, sizeof(*cmd)); | |
762 | ||
763 | /* Tell the IOMMU about it */ | |
a19ae1ec | 764 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 765 | } |
a19ae1ec | 766 | |
815b33fd | 767 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 768 | { |
815b33fd JR |
769 | WARN_ON(address & 0x7ULL); |
770 | ||
ded46737 | 771 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
772 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
773 | cmd->data[1] = upper_32_bits(__pa(address)); | |
774 | cmd->data[2] = 1; | |
ded46737 JR |
775 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
776 | } | |
777 | ||
94fe79e2 JR |
778 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
779 | { | |
780 | memset(cmd, 0, sizeof(*cmd)); | |
781 | cmd->data[0] = devid; | |
782 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
783 | } | |
784 | ||
11b6402c JR |
785 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
786 | size_t size, u16 domid, int pde) | |
787 | { | |
788 | u64 pages; | |
ae0cbbb1 | 789 | bool s; |
11b6402c JR |
790 | |
791 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 792 | s = false; |
11b6402c JR |
793 | |
794 | if (pages > 1) { | |
795 | /* | |
796 | * If we have to flush more than one page, flush all | |
797 | * TLB entries for this domain | |
798 | */ | |
799 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 800 | s = true; |
11b6402c JR |
801 | } |
802 | ||
803 | address &= PAGE_MASK; | |
804 | ||
805 | memset(cmd, 0, sizeof(*cmd)); | |
806 | cmd->data[1] |= domid; | |
807 | cmd->data[2] = lower_32_bits(address); | |
808 | cmd->data[3] = upper_32_bits(address); | |
809 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
810 | if (s) /* size bit - we flush more than one 4kb page */ | |
811 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 812 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
813 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
814 | } | |
815 | ||
cb41ed85 JR |
816 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
817 | u64 address, size_t size) | |
818 | { | |
819 | u64 pages; | |
ae0cbbb1 | 820 | bool s; |
cb41ed85 JR |
821 | |
822 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 823 | s = false; |
cb41ed85 JR |
824 | |
825 | if (pages > 1) { | |
826 | /* | |
827 | * If we have to flush more than one page, flush all | |
828 | * TLB entries for this domain | |
829 | */ | |
830 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 831 | s = true; |
cb41ed85 JR |
832 | } |
833 | ||
834 | address &= PAGE_MASK; | |
835 | ||
836 | memset(cmd, 0, sizeof(*cmd)); | |
837 | cmd->data[0] = devid; | |
838 | cmd->data[0] |= (qdep & 0xff) << 24; | |
839 | cmd->data[1] = devid; | |
840 | cmd->data[2] = lower_32_bits(address); | |
841 | cmd->data[3] = upper_32_bits(address); | |
842 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
843 | if (s) | |
844 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
845 | } | |
846 | ||
22e266c7 JR |
847 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
848 | u64 address, bool size) | |
849 | { | |
850 | memset(cmd, 0, sizeof(*cmd)); | |
851 | ||
852 | address &= ~(0xfffULL); | |
853 | ||
a919a018 | 854 | cmd->data[0] = pasid; |
22e266c7 JR |
855 | cmd->data[1] = domid; |
856 | cmd->data[2] = lower_32_bits(address); | |
857 | cmd->data[3] = upper_32_bits(address); | |
858 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
859 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
860 | if (size) | |
861 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
862 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
863 | } | |
864 | ||
865 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
866 | int qdep, u64 address, bool size) | |
867 | { | |
868 | memset(cmd, 0, sizeof(*cmd)); | |
869 | ||
870 | address &= ~(0xfffULL); | |
871 | ||
872 | cmd->data[0] = devid; | |
e8d2d82d | 873 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
874 | cmd->data[0] |= (qdep & 0xff) << 24; |
875 | cmd->data[1] = devid; | |
e8d2d82d | 876 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
877 | cmd->data[2] = lower_32_bits(address); |
878 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
879 | cmd->data[3] = upper_32_bits(address); | |
880 | if (size) | |
881 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
882 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
883 | } | |
884 | ||
c99afa25 JR |
885 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
886 | int status, int tag, bool gn) | |
887 | { | |
888 | memset(cmd, 0, sizeof(*cmd)); | |
889 | ||
890 | cmd->data[0] = devid; | |
891 | if (gn) { | |
a919a018 | 892 | cmd->data[1] = pasid; |
c99afa25 JR |
893 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
894 | } | |
895 | cmd->data[3] = tag & 0x1ff; | |
896 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
897 | ||
898 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
899 | } | |
900 | ||
58fc7f14 JR |
901 | static void build_inv_all(struct iommu_cmd *cmd) |
902 | { | |
903 | memset(cmd, 0, sizeof(*cmd)); | |
904 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
905 | } |
906 | ||
7ef2798d JR |
907 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
908 | { | |
909 | memset(cmd, 0, sizeof(*cmd)); | |
910 | cmd->data[0] = devid; | |
911 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
912 | } | |
913 | ||
431b2a20 | 914 | /* |
431b2a20 | 915 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 916 | * hardware about the new command. |
431b2a20 | 917 | */ |
f1ca1512 JR |
918 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
919 | struct iommu_cmd *cmd, | |
920 | bool sync) | |
a19ae1ec | 921 | { |
ac0ea6e9 | 922 | u32 left, tail, head, next_tail; |
a19ae1ec | 923 | unsigned long flags; |
a19ae1ec | 924 | |
ac0ea6e9 | 925 | again: |
a19ae1ec | 926 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 927 | |
ac0ea6e9 JR |
928 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
929 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
deba4bce JR |
930 | next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
931 | left = (head - next_tail) % CMD_BUFFER_SIZE; | |
a19ae1ec | 932 | |
ac0ea6e9 JR |
933 | if (left <= 2) { |
934 | struct iommu_cmd sync_cmd; | |
935 | volatile u64 sem = 0; | |
936 | int ret; | |
8d201968 | 937 | |
ac0ea6e9 JR |
938 | build_completion_wait(&sync_cmd, (u64)&sem); |
939 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 940 | |
ac0ea6e9 JR |
941 | spin_unlock_irqrestore(&iommu->lock, flags); |
942 | ||
943 | if ((ret = wait_on_sem(&sem)) != 0) | |
944 | return ret; | |
945 | ||
946 | goto again; | |
8d201968 JR |
947 | } |
948 | ||
ac0ea6e9 JR |
949 | copy_cmd_to_buffer(iommu, cmd, tail); |
950 | ||
951 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 952 | iommu->need_sync = sync; |
ac0ea6e9 | 953 | |
a19ae1ec | 954 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 955 | |
815b33fd | 956 | return 0; |
8d201968 JR |
957 | } |
958 | ||
f1ca1512 JR |
959 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
960 | { | |
961 | return iommu_queue_command_sync(iommu, cmd, true); | |
962 | } | |
963 | ||
8d201968 JR |
964 | /* |
965 | * This function queues a completion wait command into the command | |
966 | * buffer of an IOMMU | |
967 | */ | |
a19ae1ec | 968 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
969 | { |
970 | struct iommu_cmd cmd; | |
815b33fd | 971 | volatile u64 sem = 0; |
ac0ea6e9 | 972 | int ret; |
8d201968 | 973 | |
09ee17eb | 974 | if (!iommu->need_sync) |
815b33fd | 975 | return 0; |
09ee17eb | 976 | |
815b33fd | 977 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 978 | |
f1ca1512 | 979 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 980 | if (ret) |
815b33fd | 981 | return ret; |
8d201968 | 982 | |
ac0ea6e9 | 983 | return wait_on_sem(&sem); |
8d201968 JR |
984 | } |
985 | ||
d8c13085 | 986 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 987 | { |
d8c13085 | 988 | struct iommu_cmd cmd; |
a19ae1ec | 989 | |
d8c13085 | 990 | build_inv_dte(&cmd, devid); |
7e4f88da | 991 | |
d8c13085 JR |
992 | return iommu_queue_command(iommu, &cmd); |
993 | } | |
09ee17eb | 994 | |
7d0c5cc5 JR |
995 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
996 | { | |
997 | u32 devid; | |
09ee17eb | 998 | |
7d0c5cc5 JR |
999 | for (devid = 0; devid <= 0xffff; ++devid) |
1000 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1001 | |
7d0c5cc5 JR |
1002 | iommu_completion_wait(iommu); |
1003 | } | |
84df8175 | 1004 | |
7d0c5cc5 JR |
1005 | /* |
1006 | * This function uses heavy locking and may disable irqs for some time. But | |
1007 | * this is no issue because it is only called during resume. | |
1008 | */ | |
1009 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1010 | { | |
1011 | u32 dom_id; | |
a19ae1ec | 1012 | |
7d0c5cc5 JR |
1013 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1014 | struct iommu_cmd cmd; | |
1015 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1016 | dom_id, 1); | |
1017 | iommu_queue_command(iommu, &cmd); | |
1018 | } | |
8eed9833 | 1019 | |
7d0c5cc5 | 1020 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1021 | } |
1022 | ||
58fc7f14 | 1023 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1024 | { |
58fc7f14 | 1025 | struct iommu_cmd cmd; |
0518a3a4 | 1026 | |
58fc7f14 | 1027 | build_inv_all(&cmd); |
0518a3a4 | 1028 | |
58fc7f14 JR |
1029 | iommu_queue_command(iommu, &cmd); |
1030 | iommu_completion_wait(iommu); | |
1031 | } | |
1032 | ||
7ef2798d JR |
1033 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1034 | { | |
1035 | struct iommu_cmd cmd; | |
1036 | ||
1037 | build_inv_irt(&cmd, devid); | |
1038 | ||
1039 | iommu_queue_command(iommu, &cmd); | |
1040 | } | |
1041 | ||
1042 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1043 | { | |
1044 | u32 devid; | |
1045 | ||
1046 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1047 | iommu_flush_irt(iommu, devid); | |
1048 | ||
1049 | iommu_completion_wait(iommu); | |
1050 | } | |
1051 | ||
7d0c5cc5 JR |
1052 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1053 | { | |
58fc7f14 JR |
1054 | if (iommu_feature(iommu, FEATURE_IA)) { |
1055 | iommu_flush_all(iommu); | |
1056 | } else { | |
1057 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1058 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1059 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1060 | } |
1061 | } | |
1062 | ||
431b2a20 | 1063 | /* |
cb41ed85 | 1064 | * Command send function for flushing on-device TLB |
431b2a20 | 1065 | */ |
6c542047 JR |
1066 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1067 | u64 address, size_t size) | |
3fa43655 JR |
1068 | { |
1069 | struct amd_iommu *iommu; | |
b00d3bcf | 1070 | struct iommu_cmd cmd; |
cb41ed85 | 1071 | int qdep; |
3fa43655 | 1072 | |
ea61cddb JR |
1073 | qdep = dev_data->ats.qdep; |
1074 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1075 | |
ea61cddb | 1076 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1077 | |
1078 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1079 | } |
1080 | ||
431b2a20 | 1081 | /* |
431b2a20 | 1082 | * Command send function for invalidating a device table entry |
431b2a20 | 1083 | */ |
6c542047 | 1084 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1085 | { |
3fa43655 | 1086 | struct amd_iommu *iommu; |
e25bfb56 | 1087 | u16 alias; |
ee2fa743 | 1088 | int ret; |
a19ae1ec | 1089 | |
6c542047 | 1090 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1091 | alias = dev_data->alias; |
a19ae1ec | 1092 | |
f62dda66 | 1093 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1094 | if (!ret && alias != dev_data->devid) |
1095 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1096 | if (ret) |
1097 | return ret; | |
1098 | ||
ea61cddb | 1099 | if (dev_data->ats.enabled) |
6c542047 | 1100 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1101 | |
ee2fa743 | 1102 | return ret; |
a19ae1ec JR |
1103 | } |
1104 | ||
431b2a20 JR |
1105 | /* |
1106 | * TLB invalidation function which is called from the mapping functions. | |
1107 | * It invalidates a single PTE if the range to flush is within a single | |
1108 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1109 | */ | |
17b124bf JR |
1110 | static void __domain_flush_pages(struct protection_domain *domain, |
1111 | u64 address, size_t size, int pde) | |
a19ae1ec | 1112 | { |
cb41ed85 | 1113 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1114 | struct iommu_cmd cmd; |
1115 | int ret = 0, i; | |
a19ae1ec | 1116 | |
11b6402c | 1117 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1118 | |
6de8ad9b JR |
1119 | for (i = 0; i < amd_iommus_present; ++i) { |
1120 | if (!domain->dev_iommu[i]) | |
1121 | continue; | |
1122 | ||
1123 | /* | |
1124 | * Devices of this domain are behind this IOMMU | |
1125 | * We need a TLB flush | |
1126 | */ | |
11b6402c | 1127 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1128 | } |
1129 | ||
cb41ed85 | 1130 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1131 | |
ea61cddb | 1132 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1133 | continue; |
1134 | ||
6c542047 | 1135 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1136 | } |
1137 | ||
11b6402c | 1138 | WARN_ON(ret); |
6de8ad9b JR |
1139 | } |
1140 | ||
17b124bf JR |
1141 | static void domain_flush_pages(struct protection_domain *domain, |
1142 | u64 address, size_t size) | |
6de8ad9b | 1143 | { |
17b124bf | 1144 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1145 | } |
b6c02715 | 1146 | |
1c655773 | 1147 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1148 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1149 | { |
17b124bf | 1150 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1151 | } |
1152 | ||
42a49f96 | 1153 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1154 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1155 | { |
17b124bf | 1156 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1157 | } |
1158 | ||
17b124bf | 1159 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1160 | { |
17b124bf | 1161 | int i; |
18811f55 | 1162 | |
17b124bf JR |
1163 | for (i = 0; i < amd_iommus_present; ++i) { |
1164 | if (!domain->dev_iommu[i]) | |
1165 | continue; | |
bfd1be18 | 1166 | |
17b124bf JR |
1167 | /* |
1168 | * Devices of this domain are behind this IOMMU | |
1169 | * We need to wait for completion of all commands. | |
1170 | */ | |
1171 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1172 | } |
e394d72a JR |
1173 | } |
1174 | ||
b00d3bcf | 1175 | |
09b42804 | 1176 | /* |
b00d3bcf | 1177 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1178 | */ |
17b124bf | 1179 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1180 | { |
b00d3bcf | 1181 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1182 | |
b00d3bcf | 1183 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1184 | device_flush_dte(dev_data); |
a345b23b JR |
1185 | } |
1186 | ||
431b2a20 JR |
1187 | /**************************************************************************** |
1188 | * | |
1189 | * The functions below are used the create the page table mappings for | |
1190 | * unity mapped regions. | |
1191 | * | |
1192 | ****************************************************************************/ | |
1193 | ||
308973d3 JR |
1194 | /* |
1195 | * This function is used to add another level to an IO page table. Adding | |
1196 | * another level increases the size of the address space by 9 bits to a size up | |
1197 | * to 64 bits. | |
1198 | */ | |
1199 | static bool increase_address_space(struct protection_domain *domain, | |
1200 | gfp_t gfp) | |
1201 | { | |
1202 | u64 *pte; | |
1203 | ||
1204 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1205 | /* address space already 64 bit large */ | |
1206 | return false; | |
1207 | ||
1208 | pte = (void *)get_zeroed_page(gfp); | |
1209 | if (!pte) | |
1210 | return false; | |
1211 | ||
1212 | *pte = PM_LEVEL_PDE(domain->mode, | |
1213 | virt_to_phys(domain->pt_root)); | |
1214 | domain->pt_root = pte; | |
1215 | domain->mode += 1; | |
1216 | domain->updated = true; | |
1217 | ||
1218 | return true; | |
1219 | } | |
1220 | ||
1221 | static u64 *alloc_pte(struct protection_domain *domain, | |
1222 | unsigned long address, | |
cbb9d729 | 1223 | unsigned long page_size, |
308973d3 JR |
1224 | u64 **pte_page, |
1225 | gfp_t gfp) | |
1226 | { | |
cbb9d729 | 1227 | int level, end_lvl; |
308973d3 | 1228 | u64 *pte, *page; |
cbb9d729 JR |
1229 | |
1230 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1231 | |
1232 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1233 | increase_address_space(domain, gfp); | |
1234 | ||
cbb9d729 JR |
1235 | level = domain->mode - 1; |
1236 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1237 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1238 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1239 | |
1240 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1241 | u64 __pte, __npte; |
1242 | ||
1243 | __pte = *pte; | |
1244 | ||
1245 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1246 | page = (u64 *)get_zeroed_page(gfp); |
1247 | if (!page) | |
1248 | return NULL; | |
7bfa5bd2 JR |
1249 | |
1250 | __npte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1251 | ||
1252 | if (cmpxchg64(pte, __pte, __npte)) { | |
1253 | free_page((unsigned long)page); | |
1254 | continue; | |
1255 | } | |
308973d3 JR |
1256 | } |
1257 | ||
cbb9d729 JR |
1258 | /* No level skipping support yet */ |
1259 | if (PM_PTE_LEVEL(*pte) != level) | |
1260 | return NULL; | |
1261 | ||
308973d3 JR |
1262 | level -= 1; |
1263 | ||
1264 | pte = IOMMU_PTE_PAGE(*pte); | |
1265 | ||
1266 | if (pte_page && level == end_lvl) | |
1267 | *pte_page = pte; | |
1268 | ||
1269 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1270 | } | |
1271 | ||
1272 | return pte; | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * This function checks if there is a PTE for a given dma address. If | |
1277 | * there is one, it returns the pointer to it. | |
1278 | */ | |
3039ca1b JR |
1279 | static u64 *fetch_pte(struct protection_domain *domain, |
1280 | unsigned long address, | |
1281 | unsigned long *page_size) | |
308973d3 JR |
1282 | { |
1283 | int level; | |
1284 | u64 *pte; | |
1285 | ||
24cd7723 JR |
1286 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1287 | return NULL; | |
1288 | ||
3039ca1b JR |
1289 | level = domain->mode - 1; |
1290 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1291 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1292 | |
24cd7723 JR |
1293 | while (level > 0) { |
1294 | ||
1295 | /* Not Present */ | |
308973d3 JR |
1296 | if (!IOMMU_PTE_PRESENT(*pte)) |
1297 | return NULL; | |
1298 | ||
24cd7723 | 1299 | /* Large PTE */ |
3039ca1b JR |
1300 | if (PM_PTE_LEVEL(*pte) == 7 || |
1301 | PM_PTE_LEVEL(*pte) == 0) | |
1302 | break; | |
24cd7723 JR |
1303 | |
1304 | /* No level skipping support yet */ | |
1305 | if (PM_PTE_LEVEL(*pte) != level) | |
1306 | return NULL; | |
1307 | ||
308973d3 JR |
1308 | level -= 1; |
1309 | ||
24cd7723 | 1310 | /* Walk to the next level */ |
3039ca1b JR |
1311 | pte = IOMMU_PTE_PAGE(*pte); |
1312 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1313 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1314 | } | |
1315 | ||
1316 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1317 | unsigned long pte_mask; | |
1318 | ||
1319 | /* | |
1320 | * If we have a series of large PTEs, make | |
1321 | * sure to return a pointer to the first one. | |
1322 | */ | |
1323 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1324 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1325 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1326 | } |
1327 | ||
1328 | return pte; | |
1329 | } | |
1330 | ||
431b2a20 JR |
1331 | /* |
1332 | * Generic mapping functions. It maps a physical address into a DMA | |
1333 | * address space. It allocates the page table pages if necessary. | |
1334 | * In the future it can be extended to a generic mapping function | |
1335 | * supporting all features of AMD IOMMU page tables like level skipping | |
1336 | * and full 64 bit address spaces. | |
1337 | */ | |
38e817fe JR |
1338 | static int iommu_map_page(struct protection_domain *dom, |
1339 | unsigned long bus_addr, | |
1340 | unsigned long phys_addr, | |
b911b89b | 1341 | unsigned long page_size, |
abdc5eb3 | 1342 | int prot, |
b911b89b | 1343 | gfp_t gfp) |
bd0e5211 | 1344 | { |
8bda3092 | 1345 | u64 __pte, *pte; |
cbb9d729 | 1346 | int i, count; |
abdc5eb3 | 1347 | |
d4b03664 JR |
1348 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1349 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1350 | ||
bad1cac2 | 1351 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1352 | return -EINVAL; |
1353 | ||
d4b03664 | 1354 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1355 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1356 | |
63eaa75e ML |
1357 | if (!pte) |
1358 | return -ENOMEM; | |
1359 | ||
cbb9d729 JR |
1360 | for (i = 0; i < count; ++i) |
1361 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1362 | return -EBUSY; | |
bd0e5211 | 1363 | |
d4b03664 | 1364 | if (count > 1) { |
cbb9d729 JR |
1365 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1366 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1367 | } else | |
1368 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1369 | |
bd0e5211 JR |
1370 | if (prot & IOMMU_PROT_IR) |
1371 | __pte |= IOMMU_PTE_IR; | |
1372 | if (prot & IOMMU_PROT_IW) | |
1373 | __pte |= IOMMU_PTE_IW; | |
1374 | ||
cbb9d729 JR |
1375 | for (i = 0; i < count; ++i) |
1376 | pte[i] = __pte; | |
bd0e5211 | 1377 | |
04bfdd84 JR |
1378 | update_domain(dom); |
1379 | ||
bd0e5211 JR |
1380 | return 0; |
1381 | } | |
1382 | ||
24cd7723 JR |
1383 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1384 | unsigned long bus_addr, | |
1385 | unsigned long page_size) | |
eb74ff6c | 1386 | { |
71b390e9 JR |
1387 | unsigned long long unmapped; |
1388 | unsigned long unmap_size; | |
24cd7723 JR |
1389 | u64 *pte; |
1390 | ||
1391 | BUG_ON(!is_power_of_2(page_size)); | |
1392 | ||
1393 | unmapped = 0; | |
eb74ff6c | 1394 | |
24cd7723 JR |
1395 | while (unmapped < page_size) { |
1396 | ||
71b390e9 JR |
1397 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1398 | ||
1399 | if (pte) { | |
1400 | int i, count; | |
1401 | ||
1402 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1403 | for (i = 0; i < count; i++) |
1404 | pte[i] = 0ULL; | |
1405 | } | |
1406 | ||
1407 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1408 | unmapped += unmap_size; | |
1409 | } | |
1410 | ||
60d0ca3c | 1411 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1412 | |
24cd7723 | 1413 | return unmapped; |
eb74ff6c | 1414 | } |
eb74ff6c | 1415 | |
431b2a20 JR |
1416 | /**************************************************************************** |
1417 | * | |
1418 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1419 | * interface functions. |
431b2a20 JR |
1420 | * |
1421 | ****************************************************************************/ | |
d3086444 | 1422 | |
9cabe89b | 1423 | |
256e4621 JR |
1424 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1425 | struct dma_ops_domain *dma_dom, | |
1426 | unsigned int pages, u64 dma_mask) | |
384de729 | 1427 | { |
256e4621 | 1428 | unsigned long pfn = 0; |
384de729 | 1429 | |
256e4621 | 1430 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1431 | |
256e4621 JR |
1432 | if (dma_mask > DMA_BIT_MASK(32)) |
1433 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
1434 | IOVA_PFN(DMA_BIT_MASK(32))); | |
7b5e25b8 | 1435 | |
256e4621 JR |
1436 | if (!pfn) |
1437 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask)); | |
5f6bed50 | 1438 | |
256e4621 | 1439 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1440 | } |
1441 | ||
256e4621 JR |
1442 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1443 | unsigned long address, | |
1444 | unsigned int pages) | |
d3086444 | 1445 | { |
256e4621 JR |
1446 | pages = __roundup_pow_of_two(pages); |
1447 | address >>= PAGE_SHIFT; | |
384de729 | 1448 | |
256e4621 | 1449 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1450 | } |
1451 | ||
431b2a20 JR |
1452 | /**************************************************************************** |
1453 | * | |
1454 | * The next functions belong to the domain allocation. A domain is | |
1455 | * allocated for every IOMMU as the default domain. If device isolation | |
1456 | * is enabled, every device get its own domain. The most important thing | |
1457 | * about domains is the page table mapping the DMA address space they | |
1458 | * contain. | |
1459 | * | |
1460 | ****************************************************************************/ | |
1461 | ||
aeb26f55 JR |
1462 | /* |
1463 | * This function adds a protection domain to the global protection domain list | |
1464 | */ | |
1465 | static void add_domain_to_list(struct protection_domain *domain) | |
1466 | { | |
1467 | unsigned long flags; | |
1468 | ||
1469 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1470 | list_add(&domain->list, &amd_iommu_pd_list); | |
1471 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1472 | } | |
1473 | ||
1474 | /* | |
1475 | * This function removes a protection domain to the global | |
1476 | * protection domain list | |
1477 | */ | |
1478 | static void del_domain_from_list(struct protection_domain *domain) | |
1479 | { | |
1480 | unsigned long flags; | |
1481 | ||
1482 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1483 | list_del(&domain->list); | |
1484 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1485 | } | |
1486 | ||
ec487d1a JR |
1487 | static u16 domain_id_alloc(void) |
1488 | { | |
1489 | unsigned long flags; | |
1490 | int id; | |
1491 | ||
1492 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1493 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1494 | BUG_ON(id == 0); | |
1495 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1496 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1497 | else | |
1498 | id = 0; | |
1499 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1500 | ||
1501 | return id; | |
1502 | } | |
1503 | ||
a2acfb75 JR |
1504 | static void domain_id_free(int id) |
1505 | { | |
1506 | unsigned long flags; | |
1507 | ||
1508 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1509 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1510 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1511 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1512 | } | |
a2acfb75 | 1513 | |
5c34c403 JR |
1514 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1515 | static void free_pt_##LVL (unsigned long __pt) \ | |
1516 | { \ | |
1517 | unsigned long p; \ | |
1518 | u64 *pt; \ | |
1519 | int i; \ | |
1520 | \ | |
1521 | pt = (u64 *)__pt; \ | |
1522 | \ | |
1523 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1524 | /* PTE present? */ \ |
5c34c403 JR |
1525 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1526 | continue; \ | |
1527 | \ | |
0b3fff54 JR |
1528 | /* Large PTE? */ \ |
1529 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1530 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1531 | continue; \ | |
1532 | \ | |
5c34c403 JR |
1533 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1534 | FN(p); \ | |
1535 | } \ | |
1536 | free_page((unsigned long)pt); \ | |
1537 | } | |
1538 | ||
1539 | DEFINE_FREE_PT_FN(l2, free_page) | |
1540 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1541 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1542 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1543 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1544 | ||
86db2e5d | 1545 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1546 | { |
5c34c403 | 1547 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1548 | |
5c34c403 JR |
1549 | switch (domain->mode) { |
1550 | case PAGE_MODE_NONE: | |
1551 | break; | |
1552 | case PAGE_MODE_1_LEVEL: | |
1553 | free_page(root); | |
1554 | break; | |
1555 | case PAGE_MODE_2_LEVEL: | |
1556 | free_pt_l2(root); | |
1557 | break; | |
1558 | case PAGE_MODE_3_LEVEL: | |
1559 | free_pt_l3(root); | |
1560 | break; | |
1561 | case PAGE_MODE_4_LEVEL: | |
1562 | free_pt_l4(root); | |
1563 | break; | |
1564 | case PAGE_MODE_5_LEVEL: | |
1565 | free_pt_l5(root); | |
1566 | break; | |
1567 | case PAGE_MODE_6_LEVEL: | |
1568 | free_pt_l6(root); | |
1569 | break; | |
1570 | default: | |
1571 | BUG(); | |
ec487d1a | 1572 | } |
ec487d1a JR |
1573 | } |
1574 | ||
b16137b1 JR |
1575 | static void free_gcr3_tbl_level1(u64 *tbl) |
1576 | { | |
1577 | u64 *ptr; | |
1578 | int i; | |
1579 | ||
1580 | for (i = 0; i < 512; ++i) { | |
1581 | if (!(tbl[i] & GCR3_VALID)) | |
1582 | continue; | |
1583 | ||
1584 | ptr = __va(tbl[i] & PAGE_MASK); | |
1585 | ||
1586 | free_page((unsigned long)ptr); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1591 | { | |
1592 | u64 *ptr; | |
1593 | int i; | |
1594 | ||
1595 | for (i = 0; i < 512; ++i) { | |
1596 | if (!(tbl[i] & GCR3_VALID)) | |
1597 | continue; | |
1598 | ||
1599 | ptr = __va(tbl[i] & PAGE_MASK); | |
1600 | ||
1601 | free_gcr3_tbl_level1(ptr); | |
1602 | } | |
1603 | } | |
1604 | ||
52815b75 JR |
1605 | static void free_gcr3_table(struct protection_domain *domain) |
1606 | { | |
b16137b1 JR |
1607 | if (domain->glx == 2) |
1608 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1609 | else if (domain->glx == 1) | |
1610 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1611 | else |
1612 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1613 | |
52815b75 JR |
1614 | free_page((unsigned long)domain->gcr3_tbl); |
1615 | } | |
1616 | ||
431b2a20 JR |
1617 | /* |
1618 | * Free a domain, only used if something went wrong in the | |
1619 | * allocation path and we need to free an already allocated page table | |
1620 | */ | |
ec487d1a JR |
1621 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1622 | { | |
1623 | if (!dom) | |
1624 | return; | |
1625 | ||
aeb26f55 JR |
1626 | del_domain_from_list(&dom->domain); |
1627 | ||
2d4c515b | 1628 | put_iova_domain(&dom->iovad); |
ec487d1a | 1629 | |
2d4c515b | 1630 | free_pagetable(&dom->domain); |
ec487d1a JR |
1631 | |
1632 | kfree(dom); | |
1633 | } | |
1634 | ||
431b2a20 JR |
1635 | /* |
1636 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1637 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1638 | * structures required for the dma_ops interface |
1639 | */ | |
87a64d52 | 1640 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1641 | { |
1642 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1643 | |
1644 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1645 | if (!dma_dom) | |
1646 | return NULL; | |
1647 | ||
7a5a566e | 1648 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1649 | goto free_dma_dom; |
7a5a566e | 1650 | |
8f7a017c | 1651 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1652 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1653 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1654 | dma_dom->domain.priv = dma_dom; |
1655 | if (!dma_dom->domain.pt_root) | |
1656 | goto free_dma_dom; | |
ec487d1a | 1657 | |
307d5851 JR |
1658 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, |
1659 | IOVA_START_PFN, DMA_32BIT_PFN); | |
1660 | ||
81cd07b9 JR |
1661 | /* Initialize reserved ranges */ |
1662 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
1663 | ||
2d4c515b JR |
1664 | add_domain_to_list(&dma_dom->domain); |
1665 | ||
ec487d1a JR |
1666 | return dma_dom; |
1667 | ||
1668 | free_dma_dom: | |
1669 | dma_ops_domain_free(dma_dom); | |
1670 | ||
1671 | return NULL; | |
1672 | } | |
1673 | ||
5b28df6f JR |
1674 | /* |
1675 | * little helper function to check whether a given protection domain is a | |
1676 | * dma_ops domain | |
1677 | */ | |
1678 | static bool dma_ops_domain(struct protection_domain *domain) | |
1679 | { | |
1680 | return domain->flags & PD_DMA_OPS_MASK; | |
1681 | } | |
1682 | ||
fd7b5535 | 1683 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1684 | { |
132bd68f | 1685 | u64 pte_root = 0; |
ee6c2868 | 1686 | u64 flags = 0; |
863c74eb | 1687 | |
132bd68f JR |
1688 | if (domain->mode != PAGE_MODE_NONE) |
1689 | pte_root = virt_to_phys(domain->pt_root); | |
1690 | ||
38ddf41b JR |
1691 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1692 | << DEV_ENTRY_MODE_SHIFT; | |
1693 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1694 | |
ee6c2868 JR |
1695 | flags = amd_iommu_dev_table[devid].data[1]; |
1696 | ||
fd7b5535 JR |
1697 | if (ats) |
1698 | flags |= DTE_FLAG_IOTLB; | |
1699 | ||
52815b75 JR |
1700 | if (domain->flags & PD_IOMMUV2_MASK) { |
1701 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1702 | u64 glx = domain->glx; | |
1703 | u64 tmp; | |
1704 | ||
1705 | pte_root |= DTE_FLAG_GV; | |
1706 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1707 | ||
1708 | /* First mask out possible old values for GCR3 table */ | |
1709 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1710 | flags &= ~tmp; | |
1711 | ||
1712 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1713 | flags &= ~tmp; | |
1714 | ||
1715 | /* Encode GCR3 table into DTE */ | |
1716 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1717 | pte_root |= tmp; | |
1718 | ||
1719 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1720 | flags |= tmp; | |
1721 | ||
1722 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1723 | flags |= tmp; | |
1724 | } | |
1725 | ||
ee6c2868 JR |
1726 | flags &= ~(0xffffUL); |
1727 | flags |= domain->id; | |
1728 | ||
1729 | amd_iommu_dev_table[devid].data[1] = flags; | |
1730 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1731 | } |
1732 | ||
1733 | static void clear_dte_entry(u16 devid) | |
1734 | { | |
15898bbc | 1735 | /* remove entry from the device table seen by the hardware */ |
cbf3ccd0 JR |
1736 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; |
1737 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; | |
15898bbc JR |
1738 | |
1739 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1740 | } |
1741 | ||
ec9e79ef JR |
1742 | static void do_attach(struct iommu_dev_data *dev_data, |
1743 | struct protection_domain *domain) | |
7f760ddd | 1744 | { |
7f760ddd | 1745 | struct amd_iommu *iommu; |
e25bfb56 | 1746 | u16 alias; |
ec9e79ef | 1747 | bool ats; |
fd7b5535 | 1748 | |
ec9e79ef | 1749 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1750 | alias = dev_data->alias; |
ec9e79ef | 1751 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1752 | |
1753 | /* Update data structures */ | |
1754 | dev_data->domain = domain; | |
1755 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1756 | |
1757 | /* Do reference counting */ | |
1758 | domain->dev_iommu[iommu->index] += 1; | |
1759 | domain->dev_cnt += 1; | |
1760 | ||
e25bfb56 JR |
1761 | /* Update device table */ |
1762 | set_dte_entry(dev_data->devid, domain, ats); | |
1763 | if (alias != dev_data->devid) | |
9b1a12d2 | 1764 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 1765 | |
6c542047 | 1766 | device_flush_dte(dev_data); |
7f760ddd JR |
1767 | } |
1768 | ||
ec9e79ef | 1769 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1770 | { |
7f760ddd | 1771 | struct amd_iommu *iommu; |
e25bfb56 | 1772 | u16 alias; |
7f760ddd | 1773 | |
5adad991 JR |
1774 | /* |
1775 | * First check if the device is still attached. It might already | |
1776 | * be detached from its domain because the generic | |
1777 | * iommu_detach_group code detached it and we try again here in | |
1778 | * our alias handling. | |
1779 | */ | |
1780 | if (!dev_data->domain) | |
1781 | return; | |
1782 | ||
ec9e79ef | 1783 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1784 | alias = dev_data->alias; |
15898bbc JR |
1785 | |
1786 | /* decrease reference counters */ | |
7f760ddd JR |
1787 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
1788 | dev_data->domain->dev_cnt -= 1; | |
1789 | ||
1790 | /* Update data structures */ | |
1791 | dev_data->domain = NULL; | |
1792 | list_del(&dev_data->list); | |
f62dda66 | 1793 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1794 | if (alias != dev_data->devid) |
1795 | clear_dte_entry(alias); | |
15898bbc | 1796 | |
7f760ddd | 1797 | /* Flush the DTE entry */ |
6c542047 | 1798 | device_flush_dte(dev_data); |
2b681faf JR |
1799 | } |
1800 | ||
1801 | /* | |
1802 | * If a device is not yet associated with a domain, this function does | |
1803 | * assigns it visible for the hardware | |
1804 | */ | |
ec9e79ef | 1805 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1806 | struct protection_domain *domain) |
2b681faf | 1807 | { |
84fe6c19 | 1808 | int ret; |
657cbb6b | 1809 | |
272e4f99 JR |
1810 | /* |
1811 | * Must be called with IRQs disabled. Warn here to detect early | |
1812 | * when its not. | |
1813 | */ | |
1814 | WARN_ON(!irqs_disabled()); | |
1815 | ||
2b681faf JR |
1816 | /* lock domain */ |
1817 | spin_lock(&domain->lock); | |
1818 | ||
397111ab | 1819 | ret = -EBUSY; |
150952f9 | 1820 | if (dev_data->domain != NULL) |
397111ab | 1821 | goto out_unlock; |
15898bbc | 1822 | |
397111ab | 1823 | /* Attach alias group root */ |
150952f9 | 1824 | do_attach(dev_data, domain); |
24100055 | 1825 | |
84fe6c19 JL |
1826 | ret = 0; |
1827 | ||
1828 | out_unlock: | |
1829 | ||
eba6ac60 JR |
1830 | /* ready */ |
1831 | spin_unlock(&domain->lock); | |
15898bbc | 1832 | |
84fe6c19 | 1833 | return ret; |
0feae533 | 1834 | } |
b20ac0d4 | 1835 | |
52815b75 JR |
1836 | |
1837 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
1838 | { | |
1839 | pci_disable_ats(pdev); | |
1840 | pci_disable_pri(pdev); | |
1841 | pci_disable_pasid(pdev); | |
1842 | } | |
1843 | ||
6a113ddc JR |
1844 | /* FIXME: Change generic reset-function to do the same */ |
1845 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
1846 | { | |
1847 | u16 control; | |
1848 | int pos; | |
1849 | ||
46277b75 | 1850 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
1851 | if (!pos) |
1852 | return -EINVAL; | |
1853 | ||
46277b75 JR |
1854 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
1855 | control |= PCI_PRI_CTRL_RESET; | |
1856 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
1857 | |
1858 | return 0; | |
1859 | } | |
1860 | ||
52815b75 JR |
1861 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
1862 | { | |
6a113ddc JR |
1863 | bool reset_enable; |
1864 | int reqs, ret; | |
1865 | ||
1866 | /* FIXME: Hardcode number of outstanding requests for now */ | |
1867 | reqs = 32; | |
1868 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
1869 | reqs = 1; | |
1870 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
1871 | |
1872 | /* Only allow access to user-accessible pages */ | |
1873 | ret = pci_enable_pasid(pdev, 0); | |
1874 | if (ret) | |
1875 | goto out_err; | |
1876 | ||
1877 | /* First reset the PRI state of the device */ | |
1878 | ret = pci_reset_pri(pdev); | |
1879 | if (ret) | |
1880 | goto out_err; | |
1881 | ||
6a113ddc JR |
1882 | /* Enable PRI */ |
1883 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
1884 | if (ret) |
1885 | goto out_err; | |
1886 | ||
6a113ddc JR |
1887 | if (reset_enable) { |
1888 | ret = pri_reset_while_enabled(pdev); | |
1889 | if (ret) | |
1890 | goto out_err; | |
1891 | } | |
1892 | ||
52815b75 JR |
1893 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
1894 | if (ret) | |
1895 | goto out_err; | |
1896 | ||
1897 | return 0; | |
1898 | ||
1899 | out_err: | |
1900 | pci_disable_pri(pdev); | |
1901 | pci_disable_pasid(pdev); | |
1902 | ||
1903 | return ret; | |
1904 | } | |
1905 | ||
c99afa25 | 1906 | /* FIXME: Move this to PCI code */ |
a3b93121 | 1907 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 1908 | |
98f1ad25 | 1909 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 1910 | { |
a3b93121 | 1911 | u16 status; |
c99afa25 JR |
1912 | int pos; |
1913 | ||
46277b75 | 1914 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
1915 | if (!pos) |
1916 | return false; | |
1917 | ||
a3b93121 | 1918 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 1919 | |
a3b93121 | 1920 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
1921 | } |
1922 | ||
407d733e | 1923 | /* |
df805abb | 1924 | * If a device is not yet associated with a domain, this function |
407d733e JR |
1925 | * assigns it visible for the hardware |
1926 | */ | |
15898bbc JR |
1927 | static int attach_device(struct device *dev, |
1928 | struct protection_domain *domain) | |
0feae533 | 1929 | { |
2bf9a0a1 | 1930 | struct pci_dev *pdev; |
ea61cddb | 1931 | struct iommu_dev_data *dev_data; |
eba6ac60 | 1932 | unsigned long flags; |
15898bbc | 1933 | int ret; |
eba6ac60 | 1934 | |
ea61cddb JR |
1935 | dev_data = get_dev_data(dev); |
1936 | ||
2bf9a0a1 WZ |
1937 | if (!dev_is_pci(dev)) |
1938 | goto skip_ats_check; | |
1939 | ||
1940 | pdev = to_pci_dev(dev); | |
52815b75 | 1941 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 1942 | if (!dev_data->passthrough) |
52815b75 JR |
1943 | return -EINVAL; |
1944 | ||
02ca2021 JR |
1945 | if (dev_data->iommu_v2) { |
1946 | if (pdev_iommuv2_enable(pdev) != 0) | |
1947 | return -EINVAL; | |
52815b75 | 1948 | |
02ca2021 JR |
1949 | dev_data->ats.enabled = true; |
1950 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1951 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
1952 | } | |
52815b75 JR |
1953 | } else if (amd_iommu_iotlb_sup && |
1954 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
1955 | dev_data->ats.enabled = true; |
1956 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
1957 | } | |
fd7b5535 | 1958 | |
2bf9a0a1 | 1959 | skip_ats_check: |
eba6ac60 | 1960 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 1961 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
1962 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1963 | ||
0feae533 JR |
1964 | /* |
1965 | * We might boot into a crash-kernel here. The crashed kernel | |
1966 | * left the caches in the IOMMU dirty. So we have to flush | |
1967 | * here to evict all dirty stuff. | |
1968 | */ | |
17b124bf | 1969 | domain_flush_tlb_pde(domain); |
15898bbc JR |
1970 | |
1971 | return ret; | |
b20ac0d4 JR |
1972 | } |
1973 | ||
355bf553 JR |
1974 | /* |
1975 | * Removes a device from a protection domain (unlocked) | |
1976 | */ | |
ec9e79ef | 1977 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 1978 | { |
2ca76279 | 1979 | struct protection_domain *domain; |
c4596114 | 1980 | |
272e4f99 JR |
1981 | /* |
1982 | * Must be called with IRQs disabled. Warn here to detect early | |
1983 | * when its not. | |
1984 | */ | |
1985 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 1986 | |
f34c73f5 JR |
1987 | if (WARN_ON(!dev_data->domain)) |
1988 | return; | |
24100055 | 1989 | |
2ca76279 | 1990 | domain = dev_data->domain; |
71f77580 | 1991 | |
f1dd0a8b | 1992 | spin_lock(&domain->lock); |
24100055 | 1993 | |
150952f9 | 1994 | do_detach(dev_data); |
7f760ddd | 1995 | |
f1dd0a8b | 1996 | spin_unlock(&domain->lock); |
355bf553 JR |
1997 | } |
1998 | ||
1999 | /* | |
2000 | * Removes a device from a protection domain (with devtable_lock held) | |
2001 | */ | |
15898bbc | 2002 | static void detach_device(struct device *dev) |
355bf553 | 2003 | { |
52815b75 | 2004 | struct protection_domain *domain; |
ea61cddb | 2005 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2006 | unsigned long flags; |
2007 | ||
ec9e79ef | 2008 | dev_data = get_dev_data(dev); |
52815b75 | 2009 | domain = dev_data->domain; |
ec9e79ef | 2010 | |
355bf553 JR |
2011 | /* lock device table */ |
2012 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2013 | __detach_device(dev_data); |
355bf553 | 2014 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2015 | |
2bf9a0a1 WZ |
2016 | if (!dev_is_pci(dev)) |
2017 | return; | |
2018 | ||
02ca2021 | 2019 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2020 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2021 | else if (dev_data->ats.enabled) | |
ea61cddb | 2022 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2023 | |
2024 | dev_data->ats.enabled = false; | |
355bf553 | 2025 | } |
e275a2a0 | 2026 | |
aafd8ba0 | 2027 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2028 | { |
5abcdba4 | 2029 | struct iommu_dev_data *dev_data; |
07ee8694 | 2030 | struct iommu_domain *domain; |
e275a2a0 | 2031 | struct amd_iommu *iommu; |
7aba6cb9 | 2032 | int ret, devid; |
e275a2a0 | 2033 | |
aafd8ba0 | 2034 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2035 | return 0; |
e275a2a0 | 2036 | |
aafd8ba0 | 2037 | devid = get_device_id(dev); |
9ee35e4c | 2038 | if (devid < 0) |
7aba6cb9 WZ |
2039 | return devid; |
2040 | ||
aafd8ba0 | 2041 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2042 | |
aafd8ba0 | 2043 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2044 | if (ret) { |
2045 | if (ret != -ENOTSUPP) | |
2046 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2047 | dev_name(dev)); | |
657cbb6b | 2048 | |
aafd8ba0 | 2049 | iommu_ignore_device(dev); |
343e9cac | 2050 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2051 | goto out; |
2052 | } | |
2053 | init_iommu_group(dev); | |
2c9195e9 | 2054 | |
07ee8694 | 2055 | dev_data = get_dev_data(dev); |
2c9195e9 | 2056 | |
4d58b8a6 | 2057 | BUG_ON(!dev_data); |
657cbb6b | 2058 | |
1e6a7b04 | 2059 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2060 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2061 | |
07ee8694 JR |
2062 | /* Domains are initialized for this device - have a look what we ended up with */ |
2063 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2064 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2065 | dev_data->passthrough = true; |
32302324 | 2066 | else |
2c9195e9 | 2067 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2068 | |
aafd8ba0 | 2069 | out: |
e275a2a0 JR |
2070 | iommu_completion_wait(iommu); |
2071 | ||
e275a2a0 JR |
2072 | return 0; |
2073 | } | |
2074 | ||
aafd8ba0 | 2075 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2076 | { |
aafd8ba0 | 2077 | struct amd_iommu *iommu; |
7aba6cb9 | 2078 | int devid; |
aafd8ba0 JR |
2079 | |
2080 | if (!check_device(dev)) | |
2081 | return; | |
2082 | ||
2083 | devid = get_device_id(dev); | |
9ee35e4c | 2084 | if (devid < 0) |
7aba6cb9 WZ |
2085 | return; |
2086 | ||
aafd8ba0 JR |
2087 | iommu = amd_iommu_rlookup_table[devid]; |
2088 | ||
2089 | iommu_uninit_device(dev); | |
2090 | iommu_completion_wait(iommu); | |
8638c491 JR |
2091 | } |
2092 | ||
b097d11a WZ |
2093 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2094 | { | |
2095 | if (dev_is_pci(dev)) | |
2096 | return pci_device_group(dev); | |
2097 | ||
2098 | return acpihid_device_group(dev); | |
2099 | } | |
2100 | ||
431b2a20 JR |
2101 | /***************************************************************************** |
2102 | * | |
2103 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2104 | * | |
2105 | *****************************************************************************/ | |
2106 | ||
2107 | /* | |
2108 | * In the dma_ops path we only have the struct device. This function | |
2109 | * finds the corresponding IOMMU, the protection domain and the | |
2110 | * requestor id for a given device. | |
2111 | * If the device is not yet associated with a domain this is also done | |
2112 | * in this function. | |
2113 | */ | |
94f6d190 | 2114 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2115 | { |
94f6d190 | 2116 | struct protection_domain *domain; |
063071df | 2117 | struct iommu_domain *io_domain; |
b20ac0d4 | 2118 | |
f99c0f1c | 2119 | if (!check_device(dev)) |
94f6d190 | 2120 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2121 | |
063071df | 2122 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2123 | if (!io_domain) |
2124 | return NULL; | |
b20ac0d4 | 2125 | |
0bb6e243 JR |
2126 | domain = to_pdomain(io_domain); |
2127 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2128 | return ERR_PTR(-EBUSY); |
f91ba190 | 2129 | |
0bb6e243 | 2130 | return domain; |
b20ac0d4 JR |
2131 | } |
2132 | ||
04bfdd84 JR |
2133 | static void update_device_table(struct protection_domain *domain) |
2134 | { | |
492667da | 2135 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2136 | |
ea61cddb JR |
2137 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2138 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2139 | } |
2140 | ||
2141 | static void update_domain(struct protection_domain *domain) | |
2142 | { | |
2143 | if (!domain->updated) | |
2144 | return; | |
2145 | ||
2146 | update_device_table(domain); | |
17b124bf JR |
2147 | |
2148 | domain_flush_devices(domain); | |
2149 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2150 | |
2151 | domain->updated = false; | |
2152 | } | |
2153 | ||
431b2a20 JR |
2154 | /* |
2155 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2156 | * contiguous memory region into DMA address space. It is used by all |
2157 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2158 | * Must be called with the domain lock held. |
2159 | */ | |
cb76c322 | 2160 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2161 | struct dma_ops_domain *dma_dom, |
2162 | phys_addr_t paddr, | |
2163 | size_t size, | |
518d9b45 | 2164 | int direction, |
832a90c3 | 2165 | u64 dma_mask) |
cb76c322 JR |
2166 | { |
2167 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2168 | dma_addr_t address, start, ret; |
cb76c322 | 2169 | unsigned int pages; |
518d9b45 | 2170 | int prot = 0; |
cb76c322 JR |
2171 | int i; |
2172 | ||
e3c449f5 | 2173 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2174 | paddr &= PAGE_MASK; |
2175 | ||
256e4621 | 2176 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
266a3bd2 JR |
2177 | if (address == DMA_ERROR_CODE) |
2178 | goto out; | |
cb76c322 | 2179 | |
518d9b45 JR |
2180 | if (direction == DMA_TO_DEVICE) |
2181 | prot = IOMMU_PROT_IR; | |
2182 | else if (direction == DMA_FROM_DEVICE) | |
2183 | prot = IOMMU_PROT_IW; | |
2184 | else if (direction == DMA_BIDIRECTIONAL) | |
2185 | prot = IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2186 | ||
cb76c322 JR |
2187 | start = address; |
2188 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2189 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2190 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2191 | if (ret) | |
53812c11 JR |
2192 | goto out_unmap; |
2193 | ||
cb76c322 JR |
2194 | paddr += PAGE_SIZE; |
2195 | start += PAGE_SIZE; | |
2196 | } | |
2197 | address += offset; | |
2198 | ||
ab7032bb | 2199 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2200 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2201 | domain_flush_complete(&dma_dom->domain); |
2202 | } | |
270cab24 | 2203 | |
cb76c322 JR |
2204 | out: |
2205 | return address; | |
53812c11 JR |
2206 | |
2207 | out_unmap: | |
2208 | ||
2209 | for (--i; i >= 0; --i) { | |
2210 | start -= PAGE_SIZE; | |
518d9b45 | 2211 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2212 | } |
2213 | ||
256e4621 JR |
2214 | domain_flush_tlb(&dma_dom->domain); |
2215 | domain_flush_complete(&dma_dom->domain); | |
2216 | ||
2217 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2218 | |
8fd524b3 | 2219 | return DMA_ERROR_CODE; |
cb76c322 JR |
2220 | } |
2221 | ||
431b2a20 JR |
2222 | /* |
2223 | * Does the reverse of the __map_single function. Must be called with | |
2224 | * the domain lock held too | |
2225 | */ | |
cd8c82e8 | 2226 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2227 | dma_addr_t dma_addr, |
2228 | size_t size, | |
2229 | int dir) | |
2230 | { | |
04e0463e | 2231 | dma_addr_t flush_addr; |
cb76c322 JR |
2232 | dma_addr_t i, start; |
2233 | unsigned int pages; | |
2234 | ||
04e0463e | 2235 | flush_addr = dma_addr; |
e3c449f5 | 2236 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2237 | dma_addr &= PAGE_MASK; |
2238 | start = dma_addr; | |
2239 | ||
2240 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2241 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2242 | start += PAGE_SIZE; |
2243 | } | |
2244 | ||
256e4621 JR |
2245 | domain_flush_tlb(&dma_dom->domain); |
2246 | domain_flush_complete(&dma_dom->domain); | |
2247 | ||
2248 | dma_ops_free_iova(dma_dom, dma_addr, pages); | |
cb76c322 JR |
2249 | } |
2250 | ||
431b2a20 JR |
2251 | /* |
2252 | * The exported map_single function for dma_ops. | |
2253 | */ | |
51491367 FT |
2254 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2255 | unsigned long offset, size_t size, | |
2256 | enum dma_data_direction dir, | |
2257 | struct dma_attrs *attrs) | |
4da70b9e | 2258 | { |
92d420ec | 2259 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2260 | struct protection_domain *domain; |
832a90c3 | 2261 | u64 dma_mask; |
4da70b9e | 2262 | |
94f6d190 JR |
2263 | domain = get_domain(dev); |
2264 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2265 | return (dma_addr_t)paddr; |
94f6d190 JR |
2266 | else if (IS_ERR(domain)) |
2267 | return DMA_ERROR_CODE; | |
4da70b9e | 2268 | |
f99c0f1c JR |
2269 | dma_mask = *dev->dma_mask; |
2270 | ||
bda350db | 2271 | return __map_single(dev, domain->priv, paddr, size, dir, dma_mask); |
4da70b9e JR |
2272 | } |
2273 | ||
431b2a20 JR |
2274 | /* |
2275 | * The exported unmap_single function for dma_ops. | |
2276 | */ | |
51491367 FT |
2277 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2278 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e | 2279 | { |
4da70b9e | 2280 | struct protection_domain *domain; |
4da70b9e | 2281 | |
94f6d190 JR |
2282 | domain = get_domain(dev); |
2283 | if (IS_ERR(domain)) | |
5b28df6f JR |
2284 | return; |
2285 | ||
cd8c82e8 | 2286 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e JR |
2287 | } |
2288 | ||
431b2a20 JR |
2289 | /* |
2290 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2291 | * lists). | |
2292 | */ | |
65b050ad | 2293 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2294 | int nelems, enum dma_data_direction dir, |
2295 | struct dma_attrs *attrs) | |
65b050ad | 2296 | { |
65b050ad | 2297 | struct protection_domain *domain; |
65b050ad JR |
2298 | int i; |
2299 | struct scatterlist *s; | |
2300 | phys_addr_t paddr; | |
2301 | int mapped_elems = 0; | |
832a90c3 | 2302 | u64 dma_mask; |
65b050ad | 2303 | |
94f6d190 | 2304 | domain = get_domain(dev); |
a0e191b2 | 2305 | if (IS_ERR(domain)) |
94f6d190 | 2306 | return 0; |
dbcc112e | 2307 | |
832a90c3 | 2308 | dma_mask = *dev->dma_mask; |
65b050ad | 2309 | |
65b050ad JR |
2310 | for_each_sg(sglist, s, nelems, i) { |
2311 | paddr = sg_phys(s); | |
2312 | ||
cd8c82e8 | 2313 | s->dma_address = __map_single(dev, domain->priv, |
bda350db | 2314 | paddr, s->length, dir, dma_mask); |
65b050ad JR |
2315 | |
2316 | if (s->dma_address) { | |
2317 | s->dma_length = s->length; | |
2318 | mapped_elems++; | |
2319 | } else | |
2320 | goto unmap; | |
65b050ad JR |
2321 | } |
2322 | ||
65b050ad | 2323 | return mapped_elems; |
92d420ec | 2324 | |
65b050ad JR |
2325 | unmap: |
2326 | for_each_sg(sglist, s, mapped_elems, i) { | |
2327 | if (s->dma_address) | |
cd8c82e8 | 2328 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2329 | s->dma_length, dir); |
2330 | s->dma_address = s->dma_length = 0; | |
2331 | } | |
2332 | ||
92d420ec | 2333 | return 0; |
65b050ad JR |
2334 | } |
2335 | ||
431b2a20 JR |
2336 | /* |
2337 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2338 | * lists). | |
2339 | */ | |
65b050ad | 2340 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2341 | int nelems, enum dma_data_direction dir, |
2342 | struct dma_attrs *attrs) | |
65b050ad | 2343 | { |
65b050ad JR |
2344 | struct protection_domain *domain; |
2345 | struct scatterlist *s; | |
65b050ad JR |
2346 | int i; |
2347 | ||
94f6d190 JR |
2348 | domain = get_domain(dev); |
2349 | if (IS_ERR(domain)) | |
5b28df6f JR |
2350 | return; |
2351 | ||
65b050ad | 2352 | for_each_sg(sglist, s, nelems, i) { |
cd8c82e8 | 2353 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2354 | s->dma_length, dir); |
65b050ad JR |
2355 | s->dma_address = s->dma_length = 0; |
2356 | } | |
65b050ad JR |
2357 | } |
2358 | ||
431b2a20 JR |
2359 | /* |
2360 | * The exported alloc_coherent function for dma_ops. | |
2361 | */ | |
5d8b53cf | 2362 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2363 | dma_addr_t *dma_addr, gfp_t flag, |
2364 | struct dma_attrs *attrs) | |
5d8b53cf | 2365 | { |
832a90c3 | 2366 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2367 | struct protection_domain *domain; |
3b839a57 | 2368 | struct page *page; |
5d8b53cf | 2369 | |
94f6d190 JR |
2370 | domain = get_domain(dev); |
2371 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2372 | page = alloc_pages(flag, get_order(size)); |
2373 | *dma_addr = page_to_phys(page); | |
2374 | return page_address(page); | |
94f6d190 JR |
2375 | } else if (IS_ERR(domain)) |
2376 | return NULL; | |
5d8b53cf | 2377 | |
3b839a57 | 2378 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2379 | dma_mask = dev->coherent_dma_mask; |
2380 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2381 | flag |= __GFP_ZERO; |
5d8b53cf | 2382 | |
3b839a57 JR |
2383 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2384 | if (!page) { | |
d0164adc | 2385 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2386 | return NULL; |
5d8b53cf | 2387 | |
3b839a57 JR |
2388 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2389 | get_order(size)); | |
2390 | if (!page) | |
2391 | return NULL; | |
2392 | } | |
5d8b53cf | 2393 | |
832a90c3 JR |
2394 | if (!dma_mask) |
2395 | dma_mask = *dev->dma_mask; | |
2396 | ||
3b839a57 | 2397 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
bda350db | 2398 | size, DMA_BIDIRECTIONAL, dma_mask); |
5d8b53cf | 2399 | |
92d420ec | 2400 | if (*dma_addr == DMA_ERROR_CODE) |
5b28df6f | 2401 | goto out_free; |
5d8b53cf | 2402 | |
3b839a57 | 2403 | return page_address(page); |
5b28df6f JR |
2404 | |
2405 | out_free: | |
2406 | ||
3b839a57 JR |
2407 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2408 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2409 | |
2410 | return NULL; | |
5d8b53cf JR |
2411 | } |
2412 | ||
431b2a20 JR |
2413 | /* |
2414 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2415 | */ |
5d8b53cf | 2416 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2417 | void *virt_addr, dma_addr_t dma_addr, |
2418 | struct dma_attrs *attrs) | |
5d8b53cf | 2419 | { |
5d8b53cf | 2420 | struct protection_domain *domain; |
3b839a57 | 2421 | struct page *page; |
5d8b53cf | 2422 | |
3b839a57 JR |
2423 | page = virt_to_page(virt_addr); |
2424 | size = PAGE_ALIGN(size); | |
2425 | ||
94f6d190 JR |
2426 | domain = get_domain(dev); |
2427 | if (IS_ERR(domain)) | |
5b28df6f JR |
2428 | goto free_mem; |
2429 | ||
cd8c82e8 | 2430 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2431 | |
5d8b53cf | 2432 | free_mem: |
3b839a57 JR |
2433 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2434 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2435 | } |
2436 | ||
b39ba6ad JR |
2437 | /* |
2438 | * This function is called by the DMA layer to find out if we can handle a | |
2439 | * particular device. It is part of the dma_ops. | |
2440 | */ | |
2441 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2442 | { | |
420aef8a | 2443 | return check_device(dev); |
b39ba6ad JR |
2444 | } |
2445 | ||
160c1d8e | 2446 | static struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2447 | .alloc = alloc_coherent, |
2448 | .free = free_coherent, | |
2449 | .map_page = map_page, | |
2450 | .unmap_page = unmap_page, | |
2451 | .map_sg = map_sg, | |
2452 | .unmap_sg = unmap_sg, | |
2453 | .dma_supported = amd_iommu_dma_supported, | |
6631ee9d JR |
2454 | }; |
2455 | ||
81cd07b9 JR |
2456 | static int init_reserved_iova_ranges(void) |
2457 | { | |
2458 | struct pci_dev *pdev = NULL; | |
2459 | struct iova *val; | |
2460 | ||
2461 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, | |
2462 | IOVA_START_PFN, DMA_32BIT_PFN); | |
2463 | ||
2464 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2465 | &reserved_rbtree_key); | |
2466 | ||
2467 | /* MSI memory range */ | |
2468 | val = reserve_iova(&reserved_iova_ranges, | |
2469 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2470 | if (!val) { | |
2471 | pr_err("Reserving MSI range failed\n"); | |
2472 | return -ENOMEM; | |
2473 | } | |
2474 | ||
2475 | /* HT memory range */ | |
2476 | val = reserve_iova(&reserved_iova_ranges, | |
2477 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2478 | if (!val) { | |
2479 | pr_err("Reserving HT range failed\n"); | |
2480 | return -ENOMEM; | |
2481 | } | |
2482 | ||
2483 | /* | |
2484 | * Memory used for PCI resources | |
2485 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2486 | */ | |
2487 | for_each_pci_dev(pdev) { | |
2488 | int i; | |
2489 | ||
2490 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2491 | struct resource *r = &pdev->resource[i]; | |
2492 | ||
2493 | if (!(r->flags & IORESOURCE_MEM)) | |
2494 | continue; | |
2495 | ||
2496 | val = reserve_iova(&reserved_iova_ranges, | |
2497 | IOVA_PFN(r->start), | |
2498 | IOVA_PFN(r->end)); | |
2499 | if (!val) { | |
2500 | pr_err("Reserve pci-resource range failed\n"); | |
2501 | return -ENOMEM; | |
2502 | } | |
2503 | } | |
2504 | } | |
2505 | ||
2506 | return 0; | |
2507 | } | |
2508 | ||
3a18404c | 2509 | int __init amd_iommu_init_api(void) |
27c2127a | 2510 | { |
307d5851 JR |
2511 | int ret, err = 0; |
2512 | ||
2513 | ret = iova_cache_get(); | |
2514 | if (ret) | |
2515 | return ret; | |
9a4d3bf5 | 2516 | |
81cd07b9 JR |
2517 | ret = init_reserved_iova_ranges(); |
2518 | if (ret) | |
2519 | return ret; | |
2520 | ||
9a4d3bf5 WZ |
2521 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2522 | if (err) | |
2523 | return err; | |
2524 | #ifdef CONFIG_ARM_AMBA | |
2525 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2526 | if (err) | |
2527 | return err; | |
2528 | #endif | |
0076cd3d WZ |
2529 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2530 | if (err) | |
2531 | return err; | |
9a4d3bf5 | 2532 | return 0; |
f5325094 JR |
2533 | } |
2534 | ||
6631ee9d JR |
2535 | int __init amd_iommu_init_dma_ops(void) |
2536 | { | |
32302324 | 2537 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2538 | iommu_detected = 1; |
6631ee9d | 2539 | |
52717828 JR |
2540 | /* |
2541 | * In case we don't initialize SWIOTLB (actually the common case | |
2542 | * when AMD IOMMU is enabled), make sure there are global | |
2543 | * dma_ops set as a fall-back for devices not handled by this | |
2544 | * driver (for example non-PCI devices). | |
2545 | */ | |
2546 | if (!swiotlb) | |
2547 | dma_ops = &nommu_dma_ops; | |
2548 | ||
62410eeb JR |
2549 | if (amd_iommu_unmap_flush) |
2550 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2551 | else | |
2552 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2553 | ||
6631ee9d | 2554 | return 0; |
6631ee9d | 2555 | } |
6d98cd80 JR |
2556 | |
2557 | /***************************************************************************** | |
2558 | * | |
2559 | * The following functions belong to the exported interface of AMD IOMMU | |
2560 | * | |
2561 | * This interface allows access to lower level functions of the IOMMU | |
2562 | * like protection domain handling and assignement of devices to domains | |
2563 | * which is not possible with the dma_ops interface. | |
2564 | * | |
2565 | *****************************************************************************/ | |
2566 | ||
6d98cd80 JR |
2567 | static void cleanup_domain(struct protection_domain *domain) |
2568 | { | |
9b29d3c6 | 2569 | struct iommu_dev_data *entry; |
6d98cd80 | 2570 | unsigned long flags; |
6d98cd80 JR |
2571 | |
2572 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2573 | ||
9b29d3c6 JR |
2574 | while (!list_empty(&domain->dev_list)) { |
2575 | entry = list_first_entry(&domain->dev_list, | |
2576 | struct iommu_dev_data, list); | |
2577 | __detach_device(entry); | |
492667da | 2578 | } |
6d98cd80 JR |
2579 | |
2580 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2581 | } | |
2582 | ||
2650815f JR |
2583 | static void protection_domain_free(struct protection_domain *domain) |
2584 | { | |
2585 | if (!domain) | |
2586 | return; | |
2587 | ||
aeb26f55 JR |
2588 | del_domain_from_list(domain); |
2589 | ||
2650815f JR |
2590 | if (domain->id) |
2591 | domain_id_free(domain->id); | |
2592 | ||
2593 | kfree(domain); | |
2594 | } | |
2595 | ||
7a5a566e JR |
2596 | static int protection_domain_init(struct protection_domain *domain) |
2597 | { | |
2598 | spin_lock_init(&domain->lock); | |
2599 | mutex_init(&domain->api_lock); | |
2600 | domain->id = domain_id_alloc(); | |
2601 | if (!domain->id) | |
2602 | return -ENOMEM; | |
2603 | INIT_LIST_HEAD(&domain->dev_list); | |
2604 | ||
2605 | return 0; | |
2606 | } | |
2607 | ||
2650815f | 2608 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2609 | { |
2610 | struct protection_domain *domain; | |
2611 | ||
2612 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2613 | if (!domain) | |
2650815f | 2614 | return NULL; |
c156e347 | 2615 | |
7a5a566e | 2616 | if (protection_domain_init(domain)) |
2650815f JR |
2617 | goto out_err; |
2618 | ||
aeb26f55 JR |
2619 | add_domain_to_list(domain); |
2620 | ||
2650815f JR |
2621 | return domain; |
2622 | ||
2623 | out_err: | |
2624 | kfree(domain); | |
2625 | ||
2626 | return NULL; | |
2627 | } | |
2628 | ||
3f4b87b9 | 2629 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2630 | { |
3f4b87b9 | 2631 | struct protection_domain *pdomain; |
0bb6e243 | 2632 | struct dma_ops_domain *dma_domain; |
2650815f | 2633 | |
0bb6e243 JR |
2634 | switch (type) { |
2635 | case IOMMU_DOMAIN_UNMANAGED: | |
2636 | pdomain = protection_domain_alloc(); | |
2637 | if (!pdomain) | |
2638 | return NULL; | |
c156e347 | 2639 | |
0bb6e243 JR |
2640 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2641 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2642 | if (!pdomain->pt_root) { | |
2643 | protection_domain_free(pdomain); | |
2644 | return NULL; | |
2645 | } | |
c156e347 | 2646 | |
0bb6e243 JR |
2647 | pdomain->domain.geometry.aperture_start = 0; |
2648 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2649 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2650 | |
0bb6e243 JR |
2651 | break; |
2652 | case IOMMU_DOMAIN_DMA: | |
2653 | dma_domain = dma_ops_domain_alloc(); | |
2654 | if (!dma_domain) { | |
2655 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2656 | return NULL; | |
2657 | } | |
2658 | pdomain = &dma_domain->domain; | |
2659 | break; | |
07f643a3 JR |
2660 | case IOMMU_DOMAIN_IDENTITY: |
2661 | pdomain = protection_domain_alloc(); | |
2662 | if (!pdomain) | |
2663 | return NULL; | |
c156e347 | 2664 | |
07f643a3 JR |
2665 | pdomain->mode = PAGE_MODE_NONE; |
2666 | break; | |
0bb6e243 JR |
2667 | default: |
2668 | return NULL; | |
2669 | } | |
c156e347 | 2670 | |
3f4b87b9 | 2671 | return &pdomain->domain; |
c156e347 JR |
2672 | } |
2673 | ||
3f4b87b9 | 2674 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2675 | { |
3f4b87b9 | 2676 | struct protection_domain *domain; |
98383fc3 | 2677 | |
3f4b87b9 | 2678 | if (!dom) |
98383fc3 JR |
2679 | return; |
2680 | ||
3f4b87b9 JR |
2681 | domain = to_pdomain(dom); |
2682 | ||
98383fc3 JR |
2683 | if (domain->dev_cnt > 0) |
2684 | cleanup_domain(domain); | |
2685 | ||
2686 | BUG_ON(domain->dev_cnt != 0); | |
2687 | ||
132bd68f JR |
2688 | if (domain->mode != PAGE_MODE_NONE) |
2689 | free_pagetable(domain); | |
98383fc3 | 2690 | |
52815b75 JR |
2691 | if (domain->flags & PD_IOMMUV2_MASK) |
2692 | free_gcr3_table(domain); | |
2693 | ||
8b408fe4 | 2694 | protection_domain_free(domain); |
98383fc3 JR |
2695 | } |
2696 | ||
684f2888 JR |
2697 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2698 | struct device *dev) | |
2699 | { | |
657cbb6b | 2700 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2701 | struct amd_iommu *iommu; |
7aba6cb9 | 2702 | int devid; |
684f2888 | 2703 | |
98fc5a69 | 2704 | if (!check_device(dev)) |
684f2888 JR |
2705 | return; |
2706 | ||
98fc5a69 | 2707 | devid = get_device_id(dev); |
9ee35e4c | 2708 | if (devid < 0) |
7aba6cb9 | 2709 | return; |
684f2888 | 2710 | |
657cbb6b | 2711 | if (dev_data->domain != NULL) |
15898bbc | 2712 | detach_device(dev); |
684f2888 JR |
2713 | |
2714 | iommu = amd_iommu_rlookup_table[devid]; | |
2715 | if (!iommu) | |
2716 | return; | |
2717 | ||
684f2888 JR |
2718 | iommu_completion_wait(iommu); |
2719 | } | |
2720 | ||
01106066 JR |
2721 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2722 | struct device *dev) | |
2723 | { | |
3f4b87b9 | 2724 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 2725 | struct iommu_dev_data *dev_data; |
01106066 | 2726 | struct amd_iommu *iommu; |
15898bbc | 2727 | int ret; |
01106066 | 2728 | |
98fc5a69 | 2729 | if (!check_device(dev)) |
01106066 JR |
2730 | return -EINVAL; |
2731 | ||
657cbb6b JR |
2732 | dev_data = dev->archdata.iommu; |
2733 | ||
f62dda66 | 2734 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
2735 | if (!iommu) |
2736 | return -EINVAL; | |
2737 | ||
657cbb6b | 2738 | if (dev_data->domain) |
15898bbc | 2739 | detach_device(dev); |
01106066 | 2740 | |
15898bbc | 2741 | ret = attach_device(dev, domain); |
01106066 JR |
2742 | |
2743 | iommu_completion_wait(iommu); | |
2744 | ||
15898bbc | 2745 | return ret; |
01106066 JR |
2746 | } |
2747 | ||
468e2366 | 2748 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 2749 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 2750 | { |
3f4b87b9 | 2751 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
2752 | int prot = 0; |
2753 | int ret; | |
2754 | ||
132bd68f JR |
2755 | if (domain->mode == PAGE_MODE_NONE) |
2756 | return -EINVAL; | |
2757 | ||
c6229ca6 JR |
2758 | if (iommu_prot & IOMMU_READ) |
2759 | prot |= IOMMU_PROT_IR; | |
2760 | if (iommu_prot & IOMMU_WRITE) | |
2761 | prot |= IOMMU_PROT_IW; | |
2762 | ||
5d214fe6 | 2763 | mutex_lock(&domain->api_lock); |
b911b89b | 2764 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
2765 | mutex_unlock(&domain->api_lock); |
2766 | ||
795e74f7 | 2767 | return ret; |
c6229ca6 JR |
2768 | } |
2769 | ||
5009065d OBC |
2770 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
2771 | size_t page_size) | |
eb74ff6c | 2772 | { |
3f4b87b9 | 2773 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 2774 | size_t unmap_size; |
eb74ff6c | 2775 | |
132bd68f JR |
2776 | if (domain->mode == PAGE_MODE_NONE) |
2777 | return -EINVAL; | |
2778 | ||
5d214fe6 | 2779 | mutex_lock(&domain->api_lock); |
468e2366 | 2780 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 2781 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 2782 | |
17b124bf | 2783 | domain_flush_tlb_pde(domain); |
5d214fe6 | 2784 | |
5009065d | 2785 | return unmap_size; |
eb74ff6c JR |
2786 | } |
2787 | ||
645c4c8d | 2788 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 2789 | dma_addr_t iova) |
645c4c8d | 2790 | { |
3f4b87b9 | 2791 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 2792 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 2793 | u64 *pte, __pte; |
645c4c8d | 2794 | |
132bd68f JR |
2795 | if (domain->mode == PAGE_MODE_NONE) |
2796 | return iova; | |
2797 | ||
3039ca1b | 2798 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 2799 | |
a6d41a40 | 2800 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2801 | return 0; |
2802 | ||
b24b1b63 JR |
2803 | offset_mask = pte_pgsize - 1; |
2804 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 2805 | |
b24b1b63 | 2806 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
2807 | } |
2808 | ||
ab636481 | 2809 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 2810 | { |
80a506b8 JR |
2811 | switch (cap) { |
2812 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 2813 | return true; |
bdddadcb | 2814 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 2815 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
2816 | case IOMMU_CAP_NOEXEC: |
2817 | return false; | |
80a506b8 JR |
2818 | } |
2819 | ||
ab636481 | 2820 | return false; |
dbb9fd86 SY |
2821 | } |
2822 | ||
35cf248f JR |
2823 | static void amd_iommu_get_dm_regions(struct device *dev, |
2824 | struct list_head *head) | |
2825 | { | |
2826 | struct unity_map_entry *entry; | |
7aba6cb9 | 2827 | int devid; |
35cf248f JR |
2828 | |
2829 | devid = get_device_id(dev); | |
9ee35e4c | 2830 | if (devid < 0) |
7aba6cb9 | 2831 | return; |
35cf248f JR |
2832 | |
2833 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
2834 | struct iommu_dm_region *region; | |
2835 | ||
2836 | if (devid < entry->devid_start || devid > entry->devid_end) | |
2837 | continue; | |
2838 | ||
2839 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
2840 | if (!region) { | |
2841 | pr_err("Out of memory allocating dm-regions for %s\n", | |
2842 | dev_name(dev)); | |
2843 | return; | |
2844 | } | |
2845 | ||
2846 | region->start = entry->address_start; | |
2847 | region->length = entry->address_end - entry->address_start; | |
2848 | if (entry->prot & IOMMU_PROT_IR) | |
2849 | region->prot |= IOMMU_READ; | |
2850 | if (entry->prot & IOMMU_PROT_IW) | |
2851 | region->prot |= IOMMU_WRITE; | |
2852 | ||
2853 | list_add_tail(®ion->list, head); | |
2854 | } | |
2855 | } | |
2856 | ||
2857 | static void amd_iommu_put_dm_regions(struct device *dev, | |
2858 | struct list_head *head) | |
2859 | { | |
2860 | struct iommu_dm_region *entry, *next; | |
2861 | ||
2862 | list_for_each_entry_safe(entry, next, head, list) | |
2863 | kfree(entry); | |
2864 | } | |
2865 | ||
8d54d6c8 JR |
2866 | static void amd_iommu_apply_dm_region(struct device *dev, |
2867 | struct iommu_domain *domain, | |
2868 | struct iommu_dm_region *region) | |
2869 | { | |
2870 | struct protection_domain *pdomain = to_pdomain(domain); | |
2871 | struct dma_ops_domain *dma_dom = pdomain->priv; | |
2872 | unsigned long start, end; | |
2873 | ||
2874 | start = IOVA_PFN(region->start); | |
2875 | end = IOVA_PFN(region->start + region->length); | |
2876 | ||
2877 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
2878 | } | |
2879 | ||
b22f6434 | 2880 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 2881 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
2882 | .domain_alloc = amd_iommu_domain_alloc, |
2883 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
2884 | .attach_dev = amd_iommu_attach_device, |
2885 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
2886 | .map = amd_iommu_map, |
2887 | .unmap = amd_iommu_unmap, | |
315786eb | 2888 | .map_sg = default_iommu_map_sg, |
26961efe | 2889 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
2890 | .add_device = amd_iommu_add_device, |
2891 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 2892 | .device_group = amd_iommu_device_group, |
35cf248f JR |
2893 | .get_dm_regions = amd_iommu_get_dm_regions, |
2894 | .put_dm_regions = amd_iommu_put_dm_regions, | |
8d54d6c8 | 2895 | .apply_dm_region = amd_iommu_apply_dm_region, |
aa3de9c0 | 2896 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
2897 | }; |
2898 | ||
0feae533 JR |
2899 | /***************************************************************************** |
2900 | * | |
2901 | * The next functions do a basic initialization of IOMMU for pass through | |
2902 | * mode | |
2903 | * | |
2904 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2905 | * DMA-API translation. | |
2906 | * | |
2907 | *****************************************************************************/ | |
2908 | ||
72e1dcc4 JR |
2909 | /* IOMMUv2 specific functions */ |
2910 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
2911 | { | |
2912 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
2913 | } | |
2914 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
2915 | ||
2916 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
2917 | { | |
2918 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
2919 | } | |
2920 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
2921 | |
2922 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
2923 | { | |
3f4b87b9 | 2924 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
2925 | unsigned long flags; |
2926 | ||
2927 | spin_lock_irqsave(&domain->lock, flags); | |
2928 | ||
2929 | /* Update data structure */ | |
2930 | domain->mode = PAGE_MODE_NONE; | |
2931 | domain->updated = true; | |
2932 | ||
2933 | /* Make changes visible to IOMMUs */ | |
2934 | update_domain(domain); | |
2935 | ||
2936 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
2937 | free_pagetable(domain); | |
2938 | ||
2939 | spin_unlock_irqrestore(&domain->lock, flags); | |
2940 | } | |
2941 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
2942 | |
2943 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
2944 | { | |
3f4b87b9 | 2945 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
2946 | unsigned long flags; |
2947 | int levels, ret; | |
2948 | ||
2949 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
2950 | return -EINVAL; | |
2951 | ||
2952 | /* Number of GCR3 table levels required */ | |
2953 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
2954 | levels += 1; | |
2955 | ||
2956 | if (levels > amd_iommu_max_glx_val) | |
2957 | return -EINVAL; | |
2958 | ||
2959 | spin_lock_irqsave(&domain->lock, flags); | |
2960 | ||
2961 | /* | |
2962 | * Save us all sanity checks whether devices already in the | |
2963 | * domain support IOMMUv2. Just force that the domain has no | |
2964 | * devices attached when it is switched into IOMMUv2 mode. | |
2965 | */ | |
2966 | ret = -EBUSY; | |
2967 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
2968 | goto out; | |
2969 | ||
2970 | ret = -ENOMEM; | |
2971 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
2972 | if (domain->gcr3_tbl == NULL) | |
2973 | goto out; | |
2974 | ||
2975 | domain->glx = levels; | |
2976 | domain->flags |= PD_IOMMUV2_MASK; | |
2977 | domain->updated = true; | |
2978 | ||
2979 | update_domain(domain); | |
2980 | ||
2981 | ret = 0; | |
2982 | ||
2983 | out: | |
2984 | spin_unlock_irqrestore(&domain->lock, flags); | |
2985 | ||
2986 | return ret; | |
2987 | } | |
2988 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
2989 | |
2990 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
2991 | u64 address, bool size) | |
2992 | { | |
2993 | struct iommu_dev_data *dev_data; | |
2994 | struct iommu_cmd cmd; | |
2995 | int i, ret; | |
2996 | ||
2997 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
2998 | return -EINVAL; | |
2999 | ||
3000 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3001 | ||
3002 | /* | |
3003 | * IOMMU TLB needs to be flushed before Device TLB to | |
3004 | * prevent device TLB refill from IOMMU TLB | |
3005 | */ | |
3006 | for (i = 0; i < amd_iommus_present; ++i) { | |
3007 | if (domain->dev_iommu[i] == 0) | |
3008 | continue; | |
3009 | ||
3010 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3011 | if (ret != 0) | |
3012 | goto out; | |
3013 | } | |
3014 | ||
3015 | /* Wait until IOMMU TLB flushes are complete */ | |
3016 | domain_flush_complete(domain); | |
3017 | ||
3018 | /* Now flush device TLBs */ | |
3019 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3020 | struct amd_iommu *iommu; | |
3021 | int qdep; | |
3022 | ||
1c1cc454 JR |
3023 | /* |
3024 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3025 | * domain. | |
3026 | */ | |
3027 | if (!dev_data->ats.enabled) | |
3028 | continue; | |
22e266c7 JR |
3029 | |
3030 | qdep = dev_data->ats.qdep; | |
3031 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3032 | ||
3033 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3034 | qdep, address, size); | |
3035 | ||
3036 | ret = iommu_queue_command(iommu, &cmd); | |
3037 | if (ret != 0) | |
3038 | goto out; | |
3039 | } | |
3040 | ||
3041 | /* Wait until all device TLBs are flushed */ | |
3042 | domain_flush_complete(domain); | |
3043 | ||
3044 | ret = 0; | |
3045 | ||
3046 | out: | |
3047 | ||
3048 | return ret; | |
3049 | } | |
3050 | ||
3051 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3052 | u64 address) | |
3053 | { | |
3054 | return __flush_pasid(domain, pasid, address, false); | |
3055 | } | |
3056 | ||
3057 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3058 | u64 address) | |
3059 | { | |
3f4b87b9 | 3060 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3061 | unsigned long flags; |
3062 | int ret; | |
3063 | ||
3064 | spin_lock_irqsave(&domain->lock, flags); | |
3065 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3066 | spin_unlock_irqrestore(&domain->lock, flags); | |
3067 | ||
3068 | return ret; | |
3069 | } | |
3070 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3071 | ||
3072 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3073 | { | |
3074 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3075 | true); | |
3076 | } | |
3077 | ||
3078 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3079 | { | |
3f4b87b9 | 3080 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3081 | unsigned long flags; |
3082 | int ret; | |
3083 | ||
3084 | spin_lock_irqsave(&domain->lock, flags); | |
3085 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3086 | spin_unlock_irqrestore(&domain->lock, flags); | |
3087 | ||
3088 | return ret; | |
3089 | } | |
3090 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3091 | ||
b16137b1 JR |
3092 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3093 | { | |
3094 | int index; | |
3095 | u64 *pte; | |
3096 | ||
3097 | while (true) { | |
3098 | ||
3099 | index = (pasid >> (9 * level)) & 0x1ff; | |
3100 | pte = &root[index]; | |
3101 | ||
3102 | if (level == 0) | |
3103 | break; | |
3104 | ||
3105 | if (!(*pte & GCR3_VALID)) { | |
3106 | if (!alloc) | |
3107 | return NULL; | |
3108 | ||
3109 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3110 | if (root == NULL) | |
3111 | return NULL; | |
3112 | ||
3113 | *pte = __pa(root) | GCR3_VALID; | |
3114 | } | |
3115 | ||
3116 | root = __va(*pte & PAGE_MASK); | |
3117 | ||
3118 | level -= 1; | |
3119 | } | |
3120 | ||
3121 | return pte; | |
3122 | } | |
3123 | ||
3124 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3125 | unsigned long cr3) | |
3126 | { | |
3127 | u64 *pte; | |
3128 | ||
3129 | if (domain->mode != PAGE_MODE_NONE) | |
3130 | return -EINVAL; | |
3131 | ||
3132 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3133 | if (pte == NULL) | |
3134 | return -ENOMEM; | |
3135 | ||
3136 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3137 | ||
3138 | return __amd_iommu_flush_tlb(domain, pasid); | |
3139 | } | |
3140 | ||
3141 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3142 | { | |
3143 | u64 *pte; | |
3144 | ||
3145 | if (domain->mode != PAGE_MODE_NONE) | |
3146 | return -EINVAL; | |
3147 | ||
3148 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3149 | if (pte == NULL) | |
3150 | return 0; | |
3151 | ||
3152 | *pte = 0; | |
3153 | ||
3154 | return __amd_iommu_flush_tlb(domain, pasid); | |
3155 | } | |
3156 | ||
3157 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3158 | unsigned long cr3) | |
3159 | { | |
3f4b87b9 | 3160 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3161 | unsigned long flags; |
3162 | int ret; | |
3163 | ||
3164 | spin_lock_irqsave(&domain->lock, flags); | |
3165 | ret = __set_gcr3(domain, pasid, cr3); | |
3166 | spin_unlock_irqrestore(&domain->lock, flags); | |
3167 | ||
3168 | return ret; | |
3169 | } | |
3170 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3171 | ||
3172 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3173 | { | |
3f4b87b9 | 3174 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3175 | unsigned long flags; |
3176 | int ret; | |
3177 | ||
3178 | spin_lock_irqsave(&domain->lock, flags); | |
3179 | ret = __clear_gcr3(domain, pasid); | |
3180 | spin_unlock_irqrestore(&domain->lock, flags); | |
3181 | ||
3182 | return ret; | |
3183 | } | |
3184 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3185 | |
3186 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3187 | int status, int tag) | |
3188 | { | |
3189 | struct iommu_dev_data *dev_data; | |
3190 | struct amd_iommu *iommu; | |
3191 | struct iommu_cmd cmd; | |
3192 | ||
3193 | dev_data = get_dev_data(&pdev->dev); | |
3194 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3195 | ||
3196 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3197 | tag, dev_data->pri_tlp); | |
3198 | ||
3199 | return iommu_queue_command(iommu, &cmd); | |
3200 | } | |
3201 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3202 | |
3203 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3204 | { | |
3f4b87b9 | 3205 | struct protection_domain *pdomain; |
f3572db8 | 3206 | |
3f4b87b9 JR |
3207 | pdomain = get_domain(&pdev->dev); |
3208 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3209 | return NULL; |
3210 | ||
3211 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3212 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3213 | return NULL; |
3214 | ||
3f4b87b9 | 3215 | return &pdomain->domain; |
f3572db8 JR |
3216 | } |
3217 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3218 | |
3219 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3220 | { | |
3221 | struct iommu_dev_data *dev_data; | |
3222 | ||
3223 | if (!amd_iommu_v2_supported()) | |
3224 | return; | |
3225 | ||
3226 | dev_data = get_dev_data(&pdev->dev); | |
3227 | dev_data->errata |= (1 << erratum); | |
3228 | } | |
3229 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3230 | |
3231 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3232 | struct amd_iommu_device_info *info) | |
3233 | { | |
3234 | int max_pasids; | |
3235 | int pos; | |
3236 | ||
3237 | if (pdev == NULL || info == NULL) | |
3238 | return -EINVAL; | |
3239 | ||
3240 | if (!amd_iommu_v2_supported()) | |
3241 | return -EINVAL; | |
3242 | ||
3243 | memset(info, 0, sizeof(*info)); | |
3244 | ||
3245 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3246 | if (pos) | |
3247 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3248 | ||
3249 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3250 | if (pos) | |
3251 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3252 | ||
3253 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3254 | if (pos) { | |
3255 | int features; | |
3256 | ||
3257 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3258 | max_pasids = min(max_pasids, (1 << 20)); | |
3259 | ||
3260 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3261 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3262 | ||
3263 | features = pci_pasid_features(pdev); | |
3264 | if (features & PCI_PASID_CAP_EXEC) | |
3265 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3266 | if (features & PCI_PASID_CAP_PRIV) | |
3267 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3268 | } | |
3269 | ||
3270 | return 0; | |
3271 | } | |
3272 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3273 | |
3274 | #ifdef CONFIG_IRQ_REMAP | |
3275 | ||
3276 | /***************************************************************************** | |
3277 | * | |
3278 | * Interrupt Remapping Implementation | |
3279 | * | |
3280 | *****************************************************************************/ | |
3281 | ||
3282 | union irte { | |
3283 | u32 val; | |
3284 | struct { | |
3285 | u32 valid : 1, | |
3286 | no_fault : 1, | |
3287 | int_type : 3, | |
3288 | rq_eoi : 1, | |
3289 | dm : 1, | |
3290 | rsvd_1 : 1, | |
3291 | destination : 8, | |
3292 | vector : 8, | |
3293 | rsvd_2 : 8; | |
3294 | } fields; | |
3295 | }; | |
3296 | ||
9c724966 JL |
3297 | struct irq_2_irte { |
3298 | u16 devid; /* Device ID for IRTE table */ | |
3299 | u16 index; /* Index into IRTE table*/ | |
3300 | }; | |
3301 | ||
7c71d306 JL |
3302 | struct amd_ir_data { |
3303 | struct irq_2_irte irq_2_irte; | |
3304 | union irte irte_entry; | |
3305 | union { | |
3306 | struct msi_msg msi_entry; | |
3307 | }; | |
3308 | }; | |
3309 | ||
3310 | static struct irq_chip amd_ir_chip; | |
3311 | ||
2b324506 JR |
3312 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3313 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3314 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3315 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3316 | ||
3317 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3318 | { | |
3319 | u64 dte; | |
3320 | ||
3321 | dte = amd_iommu_dev_table[devid].data[2]; | |
3322 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3323 | dte |= virt_to_phys(table->table); | |
3324 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3325 | dte |= DTE_IRQ_TABLE_LEN; | |
3326 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3327 | ||
3328 | amd_iommu_dev_table[devid].data[2] = dte; | |
3329 | } | |
3330 | ||
3331 | #define IRTE_ALLOCATED (~1U) | |
3332 | ||
3333 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3334 | { | |
3335 | struct irq_remap_table *table = NULL; | |
3336 | struct amd_iommu *iommu; | |
3337 | unsigned long flags; | |
3338 | u16 alias; | |
3339 | ||
3340 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3341 | ||
3342 | iommu = amd_iommu_rlookup_table[devid]; | |
3343 | if (!iommu) | |
3344 | goto out_unlock; | |
3345 | ||
3346 | table = irq_lookup_table[devid]; | |
3347 | if (table) | |
3348 | goto out; | |
3349 | ||
3350 | alias = amd_iommu_alias_table[devid]; | |
3351 | table = irq_lookup_table[alias]; | |
3352 | if (table) { | |
3353 | irq_lookup_table[devid] = table; | |
3354 | set_dte_irq_entry(devid, table); | |
3355 | iommu_flush_dte(iommu, devid); | |
3356 | goto out; | |
3357 | } | |
3358 | ||
3359 | /* Nothing there yet, allocate new irq remapping table */ | |
3360 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3361 | if (!table) | |
3362 | goto out; | |
3363 | ||
197887f0 JR |
3364 | /* Initialize table spin-lock */ |
3365 | spin_lock_init(&table->lock); | |
3366 | ||
2b324506 JR |
3367 | if (ioapic) |
3368 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3369 | table->min_index = 32; | |
3370 | ||
3371 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3372 | if (!table->table) { | |
3373 | kfree(table); | |
821f0f68 | 3374 | table = NULL; |
2b324506 JR |
3375 | goto out; |
3376 | } | |
3377 | ||
3378 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3379 | ||
3380 | if (ioapic) { | |
3381 | int i; | |
3382 | ||
3383 | for (i = 0; i < 32; ++i) | |
3384 | table->table[i] = IRTE_ALLOCATED; | |
3385 | } | |
3386 | ||
3387 | irq_lookup_table[devid] = table; | |
3388 | set_dte_irq_entry(devid, table); | |
3389 | iommu_flush_dte(iommu, devid); | |
3390 | if (devid != alias) { | |
3391 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3392 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3393 | iommu_flush_dte(iommu, alias); |
3394 | } | |
3395 | ||
3396 | out: | |
3397 | iommu_completion_wait(iommu); | |
3398 | ||
3399 | out_unlock: | |
3400 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3401 | ||
3402 | return table; | |
3403 | } | |
3404 | ||
3c3d4f90 | 3405 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3406 | { |
3407 | struct irq_remap_table *table; | |
3408 | unsigned long flags; | |
3409 | int index, c; | |
3410 | ||
3411 | table = get_irq_table(devid, false); | |
3412 | if (!table) | |
3413 | return -ENODEV; | |
3414 | ||
3415 | spin_lock_irqsave(&table->lock, flags); | |
3416 | ||
3417 | /* Scan table for free entries */ | |
3418 | for (c = 0, index = table->min_index; | |
3419 | index < MAX_IRQS_PER_TABLE; | |
3420 | ++index) { | |
3421 | if (table->table[index] == 0) | |
3422 | c += 1; | |
3423 | else | |
3424 | c = 0; | |
3425 | ||
3426 | if (c == count) { | |
2b324506 JR |
3427 | for (; c != 0; --c) |
3428 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3429 | ||
3430 | index -= count - 1; | |
2b324506 JR |
3431 | goto out; |
3432 | } | |
3433 | } | |
3434 | ||
3435 | index = -ENOSPC; | |
3436 | ||
3437 | out: | |
3438 | spin_unlock_irqrestore(&table->lock, flags); | |
3439 | ||
3440 | return index; | |
3441 | } | |
3442 | ||
2b324506 JR |
3443 | static int modify_irte(u16 devid, int index, union irte irte) |
3444 | { | |
3445 | struct irq_remap_table *table; | |
3446 | struct amd_iommu *iommu; | |
3447 | unsigned long flags; | |
3448 | ||
3449 | iommu = amd_iommu_rlookup_table[devid]; | |
3450 | if (iommu == NULL) | |
3451 | return -EINVAL; | |
3452 | ||
3453 | table = get_irq_table(devid, false); | |
3454 | if (!table) | |
3455 | return -ENOMEM; | |
3456 | ||
3457 | spin_lock_irqsave(&table->lock, flags); | |
3458 | table->table[index] = irte.val; | |
3459 | spin_unlock_irqrestore(&table->lock, flags); | |
3460 | ||
3461 | iommu_flush_irt(iommu, devid); | |
3462 | iommu_completion_wait(iommu); | |
3463 | ||
3464 | return 0; | |
3465 | } | |
3466 | ||
3467 | static void free_irte(u16 devid, int index) | |
3468 | { | |
3469 | struct irq_remap_table *table; | |
3470 | struct amd_iommu *iommu; | |
3471 | unsigned long flags; | |
3472 | ||
3473 | iommu = amd_iommu_rlookup_table[devid]; | |
3474 | if (iommu == NULL) | |
3475 | return; | |
3476 | ||
3477 | table = get_irq_table(devid, false); | |
3478 | if (!table) | |
3479 | return; | |
3480 | ||
3481 | spin_lock_irqsave(&table->lock, flags); | |
3482 | table->table[index] = 0; | |
3483 | spin_unlock_irqrestore(&table->lock, flags); | |
3484 | ||
3485 | iommu_flush_irt(iommu, devid); | |
3486 | iommu_completion_wait(iommu); | |
3487 | } | |
3488 | ||
7c71d306 | 3489 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3490 | { |
7c71d306 | 3491 | int devid = -1; |
5527de74 | 3492 | |
7c71d306 JL |
3493 | switch (info->type) { |
3494 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3495 | devid = get_ioapic_devid(info->ioapic_id); | |
3496 | break; | |
3497 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3498 | devid = get_hpet_devid(info->hpet_id); | |
3499 | break; | |
3500 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3501 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3502 | devid = get_device_id(&info->msi_dev->dev); | |
3503 | break; | |
3504 | default: | |
3505 | BUG_ON(1); | |
3506 | break; | |
3507 | } | |
5527de74 | 3508 | |
7c71d306 JL |
3509 | return devid; |
3510 | } | |
5527de74 | 3511 | |
7c71d306 JL |
3512 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3513 | { | |
3514 | struct amd_iommu *iommu; | |
3515 | int devid; | |
5527de74 | 3516 | |
7c71d306 JL |
3517 | if (!info) |
3518 | return NULL; | |
5527de74 | 3519 | |
7c71d306 JL |
3520 | devid = get_devid(info); |
3521 | if (devid >= 0) { | |
3522 | iommu = amd_iommu_rlookup_table[devid]; | |
3523 | if (iommu) | |
3524 | return iommu->ir_domain; | |
3525 | } | |
5527de74 | 3526 | |
7c71d306 | 3527 | return NULL; |
5527de74 JR |
3528 | } |
3529 | ||
7c71d306 | 3530 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3531 | { |
7c71d306 JL |
3532 | struct amd_iommu *iommu; |
3533 | int devid; | |
5527de74 | 3534 | |
7c71d306 JL |
3535 | if (!info) |
3536 | return NULL; | |
5527de74 | 3537 | |
7c71d306 JL |
3538 | switch (info->type) { |
3539 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3540 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3541 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 3542 | if (devid < 0) |
7aba6cb9 WZ |
3543 | return NULL; |
3544 | ||
1fb260bc DC |
3545 | iommu = amd_iommu_rlookup_table[devid]; |
3546 | if (iommu) | |
3547 | return iommu->msi_domain; | |
7c71d306 JL |
3548 | break; |
3549 | default: | |
3550 | break; | |
3551 | } | |
5527de74 | 3552 | |
7c71d306 JL |
3553 | return NULL; |
3554 | } | |
5527de74 | 3555 | |
6b474b82 | 3556 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3557 | .prepare = amd_iommu_prepare, |
3558 | .enable = amd_iommu_enable, | |
3559 | .disable = amd_iommu_disable, | |
3560 | .reenable = amd_iommu_reenable, | |
3561 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3562 | .get_ir_irq_domain = get_ir_irq_domain, |
3563 | .get_irq_domain = get_irq_domain, | |
3564 | }; | |
5527de74 | 3565 | |
7c71d306 JL |
3566 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3567 | struct irq_cfg *irq_cfg, | |
3568 | struct irq_alloc_info *info, | |
3569 | int devid, int index, int sub_handle) | |
3570 | { | |
3571 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3572 | struct msi_msg *msg = &data->msi_entry; | |
3573 | union irte *irte = &data->irte_entry; | |
3574 | struct IO_APIC_route_entry *entry; | |
5527de74 | 3575 | |
7c71d306 JL |
3576 | data->irq_2_irte.devid = devid; |
3577 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 3578 | |
7c71d306 JL |
3579 | /* Setup IRTE for IOMMU */ |
3580 | irte->val = 0; | |
3581 | irte->fields.vector = irq_cfg->vector; | |
3582 | irte->fields.int_type = apic->irq_delivery_mode; | |
3583 | irte->fields.destination = irq_cfg->dest_apicid; | |
3584 | irte->fields.dm = apic->irq_dest_mode; | |
3585 | irte->fields.valid = 1; | |
3586 | ||
3587 | switch (info->type) { | |
3588 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3589 | /* Setup IOAPIC entry */ | |
3590 | entry = info->ioapic_entry; | |
3591 | info->ioapic_entry = NULL; | |
3592 | memset(entry, 0, sizeof(*entry)); | |
3593 | entry->vector = index; | |
3594 | entry->mask = 0; | |
3595 | entry->trigger = info->ioapic_trigger; | |
3596 | entry->polarity = info->ioapic_polarity; | |
3597 | /* Mask level triggered irqs. */ | |
3598 | if (info->ioapic_trigger) | |
3599 | entry->mask = 1; | |
3600 | break; | |
5527de74 | 3601 | |
7c71d306 JL |
3602 | case X86_IRQ_ALLOC_TYPE_HPET: |
3603 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3604 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3605 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3606 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3607 | msg->data = irte_info->index; | |
3608 | break; | |
5527de74 | 3609 | |
7c71d306 JL |
3610 | default: |
3611 | BUG_ON(1); | |
3612 | break; | |
3613 | } | |
5527de74 JR |
3614 | } |
3615 | ||
7c71d306 JL |
3616 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3617 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3618 | { |
7c71d306 JL |
3619 | struct irq_alloc_info *info = arg; |
3620 | struct irq_data *irq_data; | |
3621 | struct amd_ir_data *data; | |
5527de74 | 3622 | struct irq_cfg *cfg; |
7c71d306 JL |
3623 | int i, ret, devid; |
3624 | int index = -1; | |
5527de74 | 3625 | |
7c71d306 JL |
3626 | if (!info) |
3627 | return -EINVAL; | |
3628 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
3629 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
3630 | return -EINVAL; |
3631 | ||
7c71d306 JL |
3632 | /* |
3633 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3634 | * to support multiple MSI interrupts. | |
3635 | */ | |
3636 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
3637 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 3638 | |
7c71d306 JL |
3639 | devid = get_devid(info); |
3640 | if (devid < 0) | |
3641 | return -EINVAL; | |
5527de74 | 3642 | |
7c71d306 JL |
3643 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3644 | if (ret < 0) | |
3645 | return ret; | |
0b4d48cb | 3646 | |
7c71d306 JL |
3647 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
3648 | if (get_irq_table(devid, true)) | |
3649 | index = info->ioapic_pin; | |
3650 | else | |
3651 | ret = -ENOMEM; | |
3652 | } else { | |
3c3d4f90 | 3653 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
3654 | } |
3655 | if (index < 0) { | |
3656 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
3657 | goto out_free_parent; |
3658 | } | |
0b4d48cb | 3659 | |
7c71d306 JL |
3660 | for (i = 0; i < nr_irqs; i++) { |
3661 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3662 | cfg = irqd_cfg(irq_data); | |
3663 | if (!irq_data || !cfg) { | |
3664 | ret = -EINVAL; | |
3665 | goto out_free_data; | |
3666 | } | |
0b4d48cb | 3667 | |
a130e69f JR |
3668 | ret = -ENOMEM; |
3669 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3670 | if (!data) | |
3671 | goto out_free_data; | |
3672 | ||
7c71d306 JL |
3673 | irq_data->hwirq = (devid << 16) + i; |
3674 | irq_data->chip_data = data; | |
3675 | irq_data->chip = &amd_ir_chip; | |
3676 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
3677 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
3678 | } | |
a130e69f | 3679 | |
7c71d306 | 3680 | return 0; |
0b4d48cb | 3681 | |
7c71d306 JL |
3682 | out_free_data: |
3683 | for (i--; i >= 0; i--) { | |
3684 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3685 | if (irq_data) | |
3686 | kfree(irq_data->chip_data); | |
3687 | } | |
3688 | for (i = 0; i < nr_irqs; i++) | |
3689 | free_irte(devid, index + i); | |
3690 | out_free_parent: | |
3691 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3692 | return ret; | |
0b4d48cb JR |
3693 | } |
3694 | ||
7c71d306 JL |
3695 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
3696 | unsigned int nr_irqs) | |
0b4d48cb | 3697 | { |
7c71d306 JL |
3698 | struct irq_2_irte *irte_info; |
3699 | struct irq_data *irq_data; | |
3700 | struct amd_ir_data *data; | |
3701 | int i; | |
0b4d48cb | 3702 | |
7c71d306 JL |
3703 | for (i = 0; i < nr_irqs; i++) { |
3704 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3705 | if (irq_data && irq_data->chip_data) { | |
3706 | data = irq_data->chip_data; | |
3707 | irte_info = &data->irq_2_irte; | |
3708 | free_irte(irte_info->devid, irte_info->index); | |
3709 | kfree(data); | |
3710 | } | |
3711 | } | |
3712 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3713 | } | |
0b4d48cb | 3714 | |
7c71d306 JL |
3715 | static void irq_remapping_activate(struct irq_domain *domain, |
3716 | struct irq_data *irq_data) | |
3717 | { | |
3718 | struct amd_ir_data *data = irq_data->chip_data; | |
3719 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 3720 | |
7c71d306 | 3721 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
3722 | } |
3723 | ||
7c71d306 JL |
3724 | static void irq_remapping_deactivate(struct irq_domain *domain, |
3725 | struct irq_data *irq_data) | |
0b4d48cb | 3726 | { |
7c71d306 JL |
3727 | struct amd_ir_data *data = irq_data->chip_data; |
3728 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3729 | union irte entry; | |
0b4d48cb | 3730 | |
7c71d306 JL |
3731 | entry.val = 0; |
3732 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
3733 | } | |
0b4d48cb | 3734 | |
7c71d306 JL |
3735 | static struct irq_domain_ops amd_ir_domain_ops = { |
3736 | .alloc = irq_remapping_alloc, | |
3737 | .free = irq_remapping_free, | |
3738 | .activate = irq_remapping_activate, | |
3739 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 3740 | }; |
0b4d48cb | 3741 | |
7c71d306 JL |
3742 | static int amd_ir_set_affinity(struct irq_data *data, |
3743 | const struct cpumask *mask, bool force) | |
3744 | { | |
3745 | struct amd_ir_data *ir_data = data->chip_data; | |
3746 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
3747 | struct irq_cfg *cfg = irqd_cfg(data); | |
3748 | struct irq_data *parent = data->parent_data; | |
3749 | int ret; | |
0b4d48cb | 3750 | |
7c71d306 JL |
3751 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
3752 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
3753 | return ret; | |
0b4d48cb | 3754 | |
7c71d306 JL |
3755 | /* |
3756 | * Atomically updates the IRTE with the new destination, vector | |
3757 | * and flushes the interrupt entry cache. | |
3758 | */ | |
3759 | ir_data->irte_entry.fields.vector = cfg->vector; | |
3760 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
3761 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 3762 | |
7c71d306 JL |
3763 | /* |
3764 | * After this point, all the interrupts will start arriving | |
3765 | * at the new destination. So, time to cleanup the previous | |
3766 | * vector allocation. | |
3767 | */ | |
c6c2002b | 3768 | send_cleanup_vector(cfg); |
7c71d306 JL |
3769 | |
3770 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
3771 | } |
3772 | ||
7c71d306 | 3773 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 3774 | { |
7c71d306 | 3775 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 3776 | |
7c71d306 JL |
3777 | *msg = ir_data->msi_entry; |
3778 | } | |
d976195c | 3779 | |
7c71d306 JL |
3780 | static struct irq_chip amd_ir_chip = { |
3781 | .irq_ack = ir_ack_apic_edge, | |
3782 | .irq_set_affinity = amd_ir_set_affinity, | |
3783 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
3784 | }; | |
d976195c | 3785 | |
7c71d306 JL |
3786 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
3787 | { | |
3788 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
3789 | if (!iommu->ir_domain) | |
3790 | return -ENOMEM; | |
d976195c | 3791 | |
7c71d306 JL |
3792 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3793 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
3794 | |
3795 | return 0; | |
3796 | } | |
2b324506 | 3797 | #endif |