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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
36 | #include <asm/irq_remapping.h> | |
37 | #include <asm/io_apic.h> | |
38 | #include <asm/apic.h> | |
39 | #include <asm/hw_irq.h> | |
17f5b569 | 40 | #include <asm/msidef.h> |
b6c02715 | 41 | #include <asm/proto.h> |
46a7fa27 | 42 | #include <asm/iommu.h> |
1d9b16d1 | 43 | #include <asm/gart.h> |
27c2127a | 44 | #include <asm/dma.h> |
403f81d8 JR |
45 | |
46 | #include "amd_iommu_proto.h" | |
47 | #include "amd_iommu_types.h" | |
6b474b82 | 48 | #include "irq_remapping.h" |
61e015ac | 49 | #include "pci.h" |
b6c02715 JR |
50 | |
51 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
52 | ||
815b33fd | 53 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 54 | |
aa3de9c0 OBC |
55 | /* |
56 | * This bitmap is used to advertise the page sizes our hardware support | |
57 | * to the IOMMU core, which will then use this information to split | |
58 | * physically contiguous memory regions it is mapping into page sizes | |
59 | * that we support. | |
60 | * | |
954e3dd8 | 61 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 62 | */ |
954e3dd8 | 63 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 64 | |
b6c02715 JR |
65 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
66 | ||
bd60b735 JR |
67 | /* A list of preallocated protection domains */ |
68 | static LIST_HEAD(iommu_pd_list); | |
69 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
70 | ||
8fa5f802 JR |
71 | /* List of all available dev_data structures */ |
72 | static LIST_HEAD(dev_data_list); | |
73 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
74 | ||
6efed63b JR |
75 | LIST_HEAD(ioapic_map); |
76 | LIST_HEAD(hpet_map); | |
77 | ||
0feae533 JR |
78 | /* |
79 | * Domain for untranslated devices - only allocated | |
80 | * if iommu=pt passed on kernel cmd line. | |
81 | */ | |
82 | static struct protection_domain *pt_domain; | |
83 | ||
26961efe | 84 | static struct iommu_ops amd_iommu_ops; |
26961efe | 85 | |
72e1dcc4 | 86 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 87 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 88 | |
ac1534a5 JR |
89 | static struct dma_map_ops amd_iommu_dma_ops; |
90 | ||
431b2a20 JR |
91 | /* |
92 | * general struct to manage commands send to an IOMMU | |
93 | */ | |
d6449536 | 94 | struct iommu_cmd { |
b6c02715 JR |
95 | u32 data[4]; |
96 | }; | |
97 | ||
05152a04 JR |
98 | struct kmem_cache *amd_iommu_irq_cache; |
99 | ||
04bfdd84 | 100 | static void update_domain(struct protection_domain *domain); |
5abcdba4 | 101 | static int __init alloc_passthrough_domain(void); |
c1eee67b | 102 | |
15898bbc JR |
103 | /**************************************************************************** |
104 | * | |
105 | * Helper functions | |
106 | * | |
107 | ****************************************************************************/ | |
108 | ||
f62dda66 | 109 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
110 | { |
111 | struct iommu_dev_data *dev_data; | |
112 | unsigned long flags; | |
113 | ||
114 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
115 | if (!dev_data) | |
116 | return NULL; | |
117 | ||
f62dda66 | 118 | dev_data->devid = devid; |
8fa5f802 JR |
119 | atomic_set(&dev_data->bind, 0); |
120 | ||
121 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
122 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
123 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
124 | ||
125 | return dev_data; | |
126 | } | |
127 | ||
128 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
133 | list_del(&dev_data->dev_data_list); | |
134 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
135 | ||
78bfa9f3 AW |
136 | if (dev_data->group) |
137 | iommu_group_put(dev_data->group); | |
138 | ||
8fa5f802 JR |
139 | kfree(dev_data); |
140 | } | |
141 | ||
3b03bb74 JR |
142 | static struct iommu_dev_data *search_dev_data(u16 devid) |
143 | { | |
144 | struct iommu_dev_data *dev_data; | |
145 | unsigned long flags; | |
146 | ||
147 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
148 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
149 | if (dev_data->devid == devid) | |
150 | goto out_unlock; | |
151 | } | |
152 | ||
153 | dev_data = NULL; | |
154 | ||
155 | out_unlock: | |
156 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
157 | ||
158 | return dev_data; | |
159 | } | |
160 | ||
161 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
162 | { | |
163 | struct iommu_dev_data *dev_data; | |
164 | ||
165 | dev_data = search_dev_data(devid); | |
166 | ||
167 | if (dev_data == NULL) | |
168 | dev_data = alloc_dev_data(devid); | |
169 | ||
170 | return dev_data; | |
171 | } | |
172 | ||
15898bbc JR |
173 | static inline u16 get_device_id(struct device *dev) |
174 | { | |
175 | struct pci_dev *pdev = to_pci_dev(dev); | |
176 | ||
6f2729ba | 177 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
178 | } |
179 | ||
657cbb6b JR |
180 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
181 | { | |
182 | return dev->archdata.iommu; | |
183 | } | |
184 | ||
5abcdba4 JR |
185 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
186 | { | |
187 | static const int caps[] = { | |
188 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
189 | PCI_EXT_CAP_ID_PRI, |
190 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
191 | }; |
192 | int i, pos; | |
193 | ||
194 | for (i = 0; i < 3; ++i) { | |
195 | pos = pci_find_ext_capability(pdev, caps[i]); | |
196 | if (pos == 0) | |
197 | return false; | |
198 | } | |
199 | ||
200 | return true; | |
201 | } | |
202 | ||
6a113ddc JR |
203 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
204 | { | |
205 | struct iommu_dev_data *dev_data; | |
206 | ||
207 | dev_data = get_dev_data(&pdev->dev); | |
208 | ||
209 | return dev_data->errata & (1 << erratum) ? true : false; | |
210 | } | |
211 | ||
71c70984 JR |
212 | /* |
213 | * In this function the list of preallocated protection domains is traversed to | |
214 | * find the domain for a specific device | |
215 | */ | |
216 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
217 | { | |
218 | struct dma_ops_domain *entry, *ret = NULL; | |
219 | unsigned long flags; | |
220 | u16 alias = amd_iommu_alias_table[devid]; | |
221 | ||
222 | if (list_empty(&iommu_pd_list)) | |
223 | return NULL; | |
224 | ||
225 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
226 | ||
227 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
228 | if (entry->target_dev == devid || | |
229 | entry->target_dev == alias) { | |
230 | ret = entry; | |
231 | break; | |
232 | } | |
233 | } | |
234 | ||
235 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
236 | ||
237 | return ret; | |
238 | } | |
239 | ||
98fc5a69 JR |
240 | /* |
241 | * This function checks if the driver got a valid device from the caller to | |
242 | * avoid dereferencing invalid pointers. | |
243 | */ | |
244 | static bool check_device(struct device *dev) | |
245 | { | |
246 | u16 devid; | |
247 | ||
248 | if (!dev || !dev->dma_mask) | |
249 | return false; | |
250 | ||
b82a2272 YW |
251 | /* No PCI device */ |
252 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
253 | return false; |
254 | ||
255 | devid = get_device_id(dev); | |
256 | ||
257 | /* Out of our scope? */ | |
258 | if (devid > amd_iommu_last_bdf) | |
259 | return false; | |
260 | ||
261 | if (amd_iommu_rlookup_table[devid] == NULL) | |
262 | return false; | |
263 | ||
264 | return true; | |
265 | } | |
266 | ||
2bff6a50 AW |
267 | static struct pci_bus *find_hosted_bus(struct pci_bus *bus) |
268 | { | |
269 | while (!bus->self) { | |
270 | if (!pci_is_root_bus(bus)) | |
271 | bus = bus->parent; | |
272 | else | |
273 | return ERR_PTR(-ENODEV); | |
274 | } | |
275 | ||
276 | return bus; | |
277 | } | |
278 | ||
664b6003 AW |
279 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
280 | ||
2851db21 | 281 | static struct pci_dev *get_isolation_root(struct pci_dev *pdev) |
657cbb6b | 282 | { |
2851db21 | 283 | struct pci_dev *dma_pdev = pdev; |
9dcd6130 | 284 | |
31fe9435 | 285 | /* Account for quirked devices */ |
664b6003 AW |
286 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
287 | ||
31fe9435 AW |
288 | /* |
289 | * If it's a multifunction device that does not support our | |
c14d2690 AW |
290 | * required ACS flags, add to the same group as lowest numbered |
291 | * function that also does not suport the required ACS flags. | |
31fe9435 | 292 | */ |
664b6003 | 293 | if (dma_pdev->multifunction && |
c14d2690 AW |
294 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) { |
295 | u8 i, slot = PCI_SLOT(dma_pdev->devfn); | |
296 | ||
297 | for (i = 0; i < 8; i++) { | |
298 | struct pci_dev *tmp; | |
299 | ||
300 | tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i)); | |
301 | if (!tmp) | |
302 | continue; | |
303 | ||
304 | if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) { | |
305 | swap_pci_ref(&dma_pdev, tmp); | |
306 | break; | |
307 | } | |
308 | pci_dev_put(tmp); | |
309 | } | |
310 | } | |
664b6003 | 311 | |
31fe9435 AW |
312 | /* |
313 | * Devices on the root bus go through the iommu. If that's not us, | |
314 | * find the next upstream device and test ACS up to the root bus. | |
315 | * Finding the next device may require skipping virtual buses. | |
316 | */ | |
664b6003 | 317 | while (!pci_is_root_bus(dma_pdev->bus)) { |
2bff6a50 AW |
318 | struct pci_bus *bus = find_hosted_bus(dma_pdev->bus); |
319 | if (IS_ERR(bus)) | |
320 | break; | |
31fe9435 AW |
321 | |
322 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
664b6003 AW |
323 | break; |
324 | ||
31fe9435 | 325 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
664b6003 AW |
326 | } |
327 | ||
2851db21 AW |
328 | return dma_pdev; |
329 | } | |
330 | ||
ce7ac4ab AW |
331 | static int use_pdev_iommu_group(struct pci_dev *pdev, struct device *dev) |
332 | { | |
333 | struct iommu_group *group = iommu_group_get(&pdev->dev); | |
334 | int ret; | |
335 | ||
336 | if (!group) { | |
337 | group = iommu_group_alloc(); | |
338 | if (IS_ERR(group)) | |
339 | return PTR_ERR(group); | |
340 | ||
341 | WARN_ON(&pdev->dev != dev); | |
342 | } | |
343 | ||
344 | ret = iommu_group_add_device(group, dev); | |
345 | iommu_group_put(group); | |
346 | return ret; | |
347 | } | |
348 | ||
78bfa9f3 AW |
349 | static int use_dev_data_iommu_group(struct iommu_dev_data *dev_data, |
350 | struct device *dev) | |
351 | { | |
352 | if (!dev_data->group) { | |
353 | struct iommu_group *group = iommu_group_alloc(); | |
354 | if (IS_ERR(group)) | |
355 | return PTR_ERR(group); | |
356 | ||
357 | dev_data->group = group; | |
358 | } | |
359 | ||
360 | return iommu_group_add_device(dev_data->group, dev); | |
361 | } | |
362 | ||
2851db21 AW |
363 | static int init_iommu_group(struct device *dev) |
364 | { | |
365 | struct iommu_dev_data *dev_data; | |
366 | struct iommu_group *group; | |
78bfa9f3 | 367 | struct pci_dev *dma_pdev; |
2851db21 AW |
368 | int ret; |
369 | ||
370 | group = iommu_group_get(dev); | |
371 | if (group) { | |
372 | iommu_group_put(group); | |
373 | return 0; | |
374 | } | |
375 | ||
376 | dev_data = find_dev_data(get_device_id(dev)); | |
377 | if (!dev_data) | |
378 | return -ENOMEM; | |
379 | ||
380 | if (dev_data->alias_data) { | |
381 | u16 alias; | |
78bfa9f3 AW |
382 | struct pci_bus *bus; |
383 | ||
384 | if (dev_data->alias_data->group) | |
385 | goto use_group; | |
2851db21 | 386 | |
78bfa9f3 AW |
387 | /* |
388 | * If the alias device exists, it's effectively just a first | |
389 | * level quirk for finding the DMA source. | |
390 | */ | |
2851db21 AW |
391 | alias = amd_iommu_alias_table[dev_data->devid]; |
392 | dma_pdev = pci_get_bus_and_slot(alias >> 8, alias & 0xff); | |
78bfa9f3 AW |
393 | if (dma_pdev) { |
394 | dma_pdev = get_isolation_root(dma_pdev); | |
395 | goto use_pdev; | |
396 | } | |
2851db21 | 397 | |
78bfa9f3 AW |
398 | /* |
399 | * If the alias is virtual, try to find a parent device | |
400 | * and test whether the IOMMU group is actualy rooted above | |
401 | * the alias. Be careful to also test the parent device if | |
402 | * we think the alias is the root of the group. | |
403 | */ | |
404 | bus = pci_find_bus(0, alias >> 8); | |
405 | if (!bus) | |
406 | goto use_group; | |
407 | ||
408 | bus = find_hosted_bus(bus); | |
409 | if (IS_ERR(bus) || !bus->self) | |
410 | goto use_group; | |
411 | ||
412 | dma_pdev = get_isolation_root(pci_dev_get(bus->self)); | |
413 | if (dma_pdev != bus->self || (dma_pdev->multifunction && | |
414 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS))) | |
415 | goto use_pdev; | |
416 | ||
417 | pci_dev_put(dma_pdev); | |
418 | goto use_group; | |
419 | } | |
2851db21 | 420 | |
78bfa9f3 AW |
421 | dma_pdev = get_isolation_root(pci_dev_get(to_pci_dev(dev))); |
422 | use_pdev: | |
ce7ac4ab | 423 | ret = use_pdev_iommu_group(dma_pdev, dev); |
9dcd6130 | 424 | pci_dev_put(dma_pdev); |
eb9c9527 | 425 | return ret; |
78bfa9f3 AW |
426 | use_group: |
427 | return use_dev_data_iommu_group(dev_data->alias_data, dev); | |
eb9c9527 AW |
428 | } |
429 | ||
c1931090 AW |
430 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
431 | { | |
432 | *(u16 *)data = alias; | |
433 | return 0; | |
434 | } | |
435 | ||
436 | static u16 get_alias(struct device *dev) | |
437 | { | |
438 | struct pci_dev *pdev = to_pci_dev(dev); | |
439 | u16 devid, ivrs_alias, pci_alias; | |
440 | ||
441 | devid = get_device_id(dev); | |
442 | ivrs_alias = amd_iommu_alias_table[devid]; | |
443 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
444 | ||
445 | if (ivrs_alias == pci_alias) | |
446 | return ivrs_alias; | |
447 | ||
448 | /* | |
449 | * DMA alias showdown | |
450 | * | |
451 | * The IVRS is fairly reliable in telling us about aliases, but it | |
452 | * can't know about every screwy device. If we don't have an IVRS | |
453 | * reported alias, use the PCI reported alias. In that case we may | |
454 | * still need to initialize the rlookup and dev_table entries if the | |
455 | * alias is to a non-existent device. | |
456 | */ | |
457 | if (ivrs_alias == devid) { | |
458 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
459 | amd_iommu_rlookup_table[pci_alias] = | |
460 | amd_iommu_rlookup_table[devid]; | |
461 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
462 | amd_iommu_dev_table[devid].data, | |
463 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
464 | } | |
465 | ||
466 | return pci_alias; | |
467 | } | |
468 | ||
469 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
470 | "for device %s[%04x:%04x], kernel reported alias " | |
471 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
472 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
473 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
474 | PCI_FUNC(pci_alias)); | |
475 | ||
476 | /* | |
477 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
478 | * bus, then the IVRS table may know about a quirk that we don't. | |
479 | */ | |
480 | if (pci_alias == devid && | |
481 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
482 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
483 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
484 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
485 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
486 | dev_name(dev)); | |
487 | } | |
488 | ||
489 | return ivrs_alias; | |
490 | } | |
491 | ||
eb9c9527 AW |
492 | static int iommu_init_device(struct device *dev) |
493 | { | |
494 | struct pci_dev *pdev = to_pci_dev(dev); | |
495 | struct iommu_dev_data *dev_data; | |
496 | u16 alias; | |
497 | int ret; | |
498 | ||
499 | if (dev->archdata.iommu) | |
500 | return 0; | |
501 | ||
502 | dev_data = find_dev_data(get_device_id(dev)); | |
503 | if (!dev_data) | |
504 | return -ENOMEM; | |
505 | ||
c1931090 AW |
506 | alias = get_alias(dev); |
507 | ||
eb9c9527 AW |
508 | if (alias != dev_data->devid) { |
509 | struct iommu_dev_data *alias_data; | |
510 | ||
511 | alias_data = find_dev_data(alias); | |
512 | if (alias_data == NULL) { | |
513 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
514 | dev_name(dev)); | |
515 | free_dev_data(dev_data); | |
516 | return -ENOTSUPP; | |
517 | } | |
518 | dev_data->alias_data = alias_data; | |
519 | } | |
520 | ||
521 | ret = init_iommu_group(dev); | |
e644a013 RK |
522 | if (ret) { |
523 | free_dev_data(dev_data); | |
9dcd6130 | 524 | return ret; |
e644a013 | 525 | } |
9dcd6130 | 526 | |
5abcdba4 JR |
527 | if (pci_iommuv2_capable(pdev)) { |
528 | struct amd_iommu *iommu; | |
529 | ||
530 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
531 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
532 | } | |
533 | ||
657cbb6b JR |
534 | dev->archdata.iommu = dev_data; |
535 | ||
657cbb6b JR |
536 | return 0; |
537 | } | |
538 | ||
26018874 JR |
539 | static void iommu_ignore_device(struct device *dev) |
540 | { | |
541 | u16 devid, alias; | |
542 | ||
543 | devid = get_device_id(dev); | |
544 | alias = amd_iommu_alias_table[devid]; | |
545 | ||
546 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
547 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
548 | ||
549 | amd_iommu_rlookup_table[devid] = NULL; | |
550 | amd_iommu_rlookup_table[alias] = NULL; | |
551 | } | |
552 | ||
657cbb6b JR |
553 | static void iommu_uninit_device(struct device *dev) |
554 | { | |
c1931090 AW |
555 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
556 | ||
557 | if (!dev_data) | |
558 | return; | |
559 | ||
9dcd6130 AW |
560 | iommu_group_remove_device(dev); |
561 | ||
c1931090 AW |
562 | /* Unlink from alias, it may change if another device is re-plugged */ |
563 | dev_data->alias_data = NULL; | |
564 | ||
8fa5f802 | 565 | /* |
c1931090 AW |
566 | * We keep dev_data around for unplugged devices and reuse it when the |
567 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 568 | */ |
657cbb6b | 569 | } |
b7cc9554 JR |
570 | |
571 | void __init amd_iommu_uninit_devices(void) | |
572 | { | |
8fa5f802 | 573 | struct iommu_dev_data *dev_data, *n; |
b7cc9554 JR |
574 | struct pci_dev *pdev = NULL; |
575 | ||
576 | for_each_pci_dev(pdev) { | |
577 | ||
578 | if (!check_device(&pdev->dev)) | |
579 | continue; | |
580 | ||
581 | iommu_uninit_device(&pdev->dev); | |
582 | } | |
8fa5f802 JR |
583 | |
584 | /* Free all of our dev_data structures */ | |
585 | list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list) | |
586 | free_dev_data(dev_data); | |
b7cc9554 JR |
587 | } |
588 | ||
589 | int __init amd_iommu_init_devices(void) | |
590 | { | |
591 | struct pci_dev *pdev = NULL; | |
592 | int ret = 0; | |
593 | ||
594 | for_each_pci_dev(pdev) { | |
595 | ||
596 | if (!check_device(&pdev->dev)) | |
597 | continue; | |
598 | ||
599 | ret = iommu_init_device(&pdev->dev); | |
26018874 JR |
600 | if (ret == -ENOTSUPP) |
601 | iommu_ignore_device(&pdev->dev); | |
602 | else if (ret) | |
b7cc9554 JR |
603 | goto out_free; |
604 | } | |
605 | ||
606 | return 0; | |
607 | ||
608 | out_free: | |
609 | ||
610 | amd_iommu_uninit_devices(); | |
611 | ||
612 | return ret; | |
613 | } | |
7f26508b JR |
614 | #ifdef CONFIG_AMD_IOMMU_STATS |
615 | ||
616 | /* | |
617 | * Initialization code for statistics collection | |
618 | */ | |
619 | ||
da49f6df | 620 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 621 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 622 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 623 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 624 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 625 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 626 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 627 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 628 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 629 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 630 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 631 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
632 | DECLARE_STATS_COUNTER(complete_ppr); |
633 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
634 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
635 | DECLARE_STATS_COUNTER(pri_requests); | |
636 | ||
7f26508b | 637 | static struct dentry *stats_dir; |
7f26508b JR |
638 | static struct dentry *de_fflush; |
639 | ||
640 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
641 | { | |
642 | if (stats_dir == NULL) | |
643 | return; | |
644 | ||
645 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
646 | &cnt->value); | |
647 | } | |
648 | ||
649 | static void amd_iommu_stats_init(void) | |
650 | { | |
651 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
652 | if (stats_dir == NULL) | |
653 | return; | |
654 | ||
7f26508b | 655 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 656 | &amd_iommu_unmap_flush); |
da49f6df JR |
657 | |
658 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 659 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 660 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 661 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 662 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 663 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 664 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 665 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 666 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 667 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 668 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 669 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
670 | amd_iommu_stats_add(&complete_ppr); |
671 | amd_iommu_stats_add(&invalidate_iotlb); | |
672 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
673 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
674 | } |
675 | ||
676 | #endif | |
677 | ||
a80dc3e0 JR |
678 | /**************************************************************************** |
679 | * | |
680 | * Interrupt handling functions | |
681 | * | |
682 | ****************************************************************************/ | |
683 | ||
e3e59876 JR |
684 | static void dump_dte_entry(u16 devid) |
685 | { | |
686 | int i; | |
687 | ||
ee6c2868 JR |
688 | for (i = 0; i < 4; ++i) |
689 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
690 | amd_iommu_dev_table[devid].data[i]); |
691 | } | |
692 | ||
945b4ac4 JR |
693 | static void dump_command(unsigned long phys_addr) |
694 | { | |
695 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
696 | int i; | |
697 | ||
698 | for (i = 0; i < 4; ++i) | |
699 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
700 | } | |
701 | ||
a345b23b | 702 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 703 | { |
3d06fca8 JR |
704 | int type, devid, domid, flags; |
705 | volatile u32 *event = __evt; | |
706 | int count = 0; | |
707 | u64 address; | |
708 | ||
709 | retry: | |
710 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
711 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
712 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
713 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
714 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
715 | ||
716 | if (type == 0) { | |
717 | /* Did we hit the erratum? */ | |
718 | if (++count == LOOP_TIMEOUT) { | |
719 | pr_err("AMD-Vi: No event written to event log\n"); | |
720 | return; | |
721 | } | |
722 | udelay(1); | |
723 | goto retry; | |
724 | } | |
90008ee4 | 725 | |
4c6f40d4 | 726 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
727 | |
728 | switch (type) { | |
729 | case EVENT_TYPE_ILL_DEV: | |
730 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
731 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 732 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 733 | address, flags); |
e3e59876 | 734 | dump_dte_entry(devid); |
90008ee4 JR |
735 | break; |
736 | case EVENT_TYPE_IO_FAULT: | |
737 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
738 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 739 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
740 | domid, address, flags); |
741 | break; | |
742 | case EVENT_TYPE_DEV_TAB_ERR: | |
743 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
744 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 745 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
746 | address, flags); |
747 | break; | |
748 | case EVENT_TYPE_PAGE_TAB_ERR: | |
749 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
750 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 751 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
752 | domid, address, flags); |
753 | break; | |
754 | case EVENT_TYPE_ILL_CMD: | |
755 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 756 | dump_command(address); |
90008ee4 JR |
757 | break; |
758 | case EVENT_TYPE_CMD_HARD_ERR: | |
759 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
760 | "flags=0x%04x]\n", address, flags); | |
761 | break; | |
762 | case EVENT_TYPE_IOTLB_INV_TO: | |
763 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
764 | "address=0x%016llx]\n", | |
c5081cd7 | 765 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
766 | address); |
767 | break; | |
768 | case EVENT_TYPE_INV_DEV_REQ: | |
769 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
770 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 771 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
772 | address, flags); |
773 | break; | |
774 | default: | |
775 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
776 | } | |
3d06fca8 JR |
777 | |
778 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
779 | } |
780 | ||
781 | static void iommu_poll_events(struct amd_iommu *iommu) | |
782 | { | |
783 | u32 head, tail; | |
90008ee4 JR |
784 | |
785 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
786 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
787 | ||
788 | while (head != tail) { | |
a345b23b | 789 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
790 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
791 | } | |
792 | ||
793 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
794 | } |
795 | ||
eee53537 | 796 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
797 | { |
798 | struct amd_iommu_fault fault; | |
72e1dcc4 | 799 | |
399be2f5 JR |
800 | INC_STATS_COUNTER(pri_requests); |
801 | ||
72e1dcc4 JR |
802 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
803 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
804 | return; | |
805 | } | |
806 | ||
807 | fault.address = raw[1]; | |
808 | fault.pasid = PPR_PASID(raw[0]); | |
809 | fault.device_id = PPR_DEVID(raw[0]); | |
810 | fault.tag = PPR_TAG(raw[0]); | |
811 | fault.flags = PPR_FLAGS(raw[0]); | |
812 | ||
72e1dcc4 JR |
813 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
814 | } | |
815 | ||
816 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
817 | { | |
72e1dcc4 JR |
818 | u32 head, tail; |
819 | ||
820 | if (iommu->ppr_log == NULL) | |
821 | return; | |
822 | ||
72e1dcc4 JR |
823 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
824 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
825 | ||
826 | while (head != tail) { | |
eee53537 JR |
827 | volatile u64 *raw; |
828 | u64 entry[2]; | |
829 | int i; | |
830 | ||
831 | raw = (u64 *)(iommu->ppr_log + head); | |
832 | ||
833 | /* | |
834 | * Hardware bug: Interrupt may arrive before the entry is | |
835 | * written to memory. If this happens we need to wait for the | |
836 | * entry to arrive. | |
837 | */ | |
838 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
839 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
840 | break; | |
841 | udelay(1); | |
842 | } | |
72e1dcc4 | 843 | |
eee53537 JR |
844 | /* Avoid memcpy function-call overhead */ |
845 | entry[0] = raw[0]; | |
846 | entry[1] = raw[1]; | |
72e1dcc4 | 847 | |
eee53537 JR |
848 | /* |
849 | * To detect the hardware bug we need to clear the entry | |
850 | * back to zero. | |
851 | */ | |
852 | raw[0] = raw[1] = 0UL; | |
853 | ||
854 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
855 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
856 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 857 | |
eee53537 JR |
858 | /* Handle PPR entry */ |
859 | iommu_handle_ppr_entry(iommu, entry); | |
860 | ||
eee53537 JR |
861 | /* Refresh ring-buffer information */ |
862 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
863 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
864 | } | |
72e1dcc4 JR |
865 | } |
866 | ||
72fe00f0 | 867 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 868 | { |
3f398bc7 SS |
869 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
870 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 871 | |
3f398bc7 SS |
872 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
873 | /* Enable EVT and PPR interrupts again */ | |
874 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
875 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 876 | |
3f398bc7 SS |
877 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
878 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
879 | iommu_poll_events(iommu); | |
880 | } | |
90008ee4 | 881 | |
3f398bc7 SS |
882 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
883 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
884 | iommu_poll_ppr_log(iommu); | |
885 | } | |
90008ee4 | 886 | |
3f398bc7 SS |
887 | /* |
888 | * Hardware bug: ERBT1312 | |
889 | * When re-enabling interrupt (by writing 1 | |
890 | * to clear the bit), the hardware might also try to set | |
891 | * the interrupt bit in the event status register. | |
892 | * In this scenario, the bit will be set, and disable | |
893 | * subsequent interrupts. | |
894 | * | |
895 | * Workaround: The IOMMU driver should read back the | |
896 | * status register and check if the interrupt bits are cleared. | |
897 | * If not, driver will need to go through the interrupt handler | |
898 | * again and re-clear the bits | |
899 | */ | |
900 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
901 | } | |
90008ee4 | 902 | return IRQ_HANDLED; |
a80dc3e0 JR |
903 | } |
904 | ||
72fe00f0 JR |
905 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
906 | { | |
907 | return IRQ_WAKE_THREAD; | |
908 | } | |
909 | ||
431b2a20 JR |
910 | /**************************************************************************** |
911 | * | |
912 | * IOMMU command queuing functions | |
913 | * | |
914 | ****************************************************************************/ | |
915 | ||
ac0ea6e9 JR |
916 | static int wait_on_sem(volatile u64 *sem) |
917 | { | |
918 | int i = 0; | |
919 | ||
920 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
921 | udelay(1); | |
922 | i += 1; | |
923 | } | |
924 | ||
925 | if (i == LOOP_TIMEOUT) { | |
926 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
927 | return -EIO; | |
928 | } | |
929 | ||
930 | return 0; | |
931 | } | |
932 | ||
933 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
934 | struct iommu_cmd *cmd, | |
935 | u32 tail) | |
a19ae1ec | 936 | { |
a19ae1ec JR |
937 | u8 *target; |
938 | ||
8a7c5ef3 | 939 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
940 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
941 | ||
942 | /* Copy command to buffer */ | |
943 | memcpy(target, cmd, sizeof(*cmd)); | |
944 | ||
945 | /* Tell the IOMMU about it */ | |
a19ae1ec | 946 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 947 | } |
a19ae1ec | 948 | |
815b33fd | 949 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 950 | { |
815b33fd JR |
951 | WARN_ON(address & 0x7ULL); |
952 | ||
ded46737 | 953 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
954 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
955 | cmd->data[1] = upper_32_bits(__pa(address)); | |
956 | cmd->data[2] = 1; | |
ded46737 JR |
957 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
958 | } | |
959 | ||
94fe79e2 JR |
960 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
961 | { | |
962 | memset(cmd, 0, sizeof(*cmd)); | |
963 | cmd->data[0] = devid; | |
964 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
965 | } | |
966 | ||
11b6402c JR |
967 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
968 | size_t size, u16 domid, int pde) | |
969 | { | |
970 | u64 pages; | |
971 | int s; | |
972 | ||
973 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
974 | s = 0; | |
975 | ||
976 | if (pages > 1) { | |
977 | /* | |
978 | * If we have to flush more than one page, flush all | |
979 | * TLB entries for this domain | |
980 | */ | |
981 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
982 | s = 1; | |
983 | } | |
984 | ||
985 | address &= PAGE_MASK; | |
986 | ||
987 | memset(cmd, 0, sizeof(*cmd)); | |
988 | cmd->data[1] |= domid; | |
989 | cmd->data[2] = lower_32_bits(address); | |
990 | cmd->data[3] = upper_32_bits(address); | |
991 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
992 | if (s) /* size bit - we flush more than one 4kb page */ | |
993 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 994 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
995 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
996 | } | |
997 | ||
cb41ed85 JR |
998 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
999 | u64 address, size_t size) | |
1000 | { | |
1001 | u64 pages; | |
1002 | int s; | |
1003 | ||
1004 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
1005 | s = 0; | |
1006 | ||
1007 | if (pages > 1) { | |
1008 | /* | |
1009 | * If we have to flush more than one page, flush all | |
1010 | * TLB entries for this domain | |
1011 | */ | |
1012 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
1013 | s = 1; | |
1014 | } | |
1015 | ||
1016 | address &= PAGE_MASK; | |
1017 | ||
1018 | memset(cmd, 0, sizeof(*cmd)); | |
1019 | cmd->data[0] = devid; | |
1020 | cmd->data[0] |= (qdep & 0xff) << 24; | |
1021 | cmd->data[1] = devid; | |
1022 | cmd->data[2] = lower_32_bits(address); | |
1023 | cmd->data[3] = upper_32_bits(address); | |
1024 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
1025 | if (s) | |
1026 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1027 | } | |
1028 | ||
22e266c7 JR |
1029 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
1030 | u64 address, bool size) | |
1031 | { | |
1032 | memset(cmd, 0, sizeof(*cmd)); | |
1033 | ||
1034 | address &= ~(0xfffULL); | |
1035 | ||
a919a018 | 1036 | cmd->data[0] = pasid; |
22e266c7 JR |
1037 | cmd->data[1] = domid; |
1038 | cmd->data[2] = lower_32_bits(address); | |
1039 | cmd->data[3] = upper_32_bits(address); | |
1040 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
1041 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1042 | if (size) | |
1043 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1044 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
1045 | } | |
1046 | ||
1047 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
1048 | int qdep, u64 address, bool size) | |
1049 | { | |
1050 | memset(cmd, 0, sizeof(*cmd)); | |
1051 | ||
1052 | address &= ~(0xfffULL); | |
1053 | ||
1054 | cmd->data[0] = devid; | |
e8d2d82d | 1055 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
1056 | cmd->data[0] |= (qdep & 0xff) << 24; |
1057 | cmd->data[1] = devid; | |
e8d2d82d | 1058 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
1059 | cmd->data[2] = lower_32_bits(address); |
1060 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
1061 | cmd->data[3] = upper_32_bits(address); | |
1062 | if (size) | |
1063 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
1064 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
1065 | } | |
1066 | ||
c99afa25 JR |
1067 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
1068 | int status, int tag, bool gn) | |
1069 | { | |
1070 | memset(cmd, 0, sizeof(*cmd)); | |
1071 | ||
1072 | cmd->data[0] = devid; | |
1073 | if (gn) { | |
a919a018 | 1074 | cmd->data[1] = pasid; |
c99afa25 JR |
1075 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
1076 | } | |
1077 | cmd->data[3] = tag & 0x1ff; | |
1078 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1079 | ||
1080 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1081 | } | |
1082 | ||
58fc7f14 JR |
1083 | static void build_inv_all(struct iommu_cmd *cmd) |
1084 | { | |
1085 | memset(cmd, 0, sizeof(*cmd)); | |
1086 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1087 | } |
1088 | ||
7ef2798d JR |
1089 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1090 | { | |
1091 | memset(cmd, 0, sizeof(*cmd)); | |
1092 | cmd->data[0] = devid; | |
1093 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1094 | } | |
1095 | ||
431b2a20 | 1096 | /* |
431b2a20 | 1097 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1098 | * hardware about the new command. |
431b2a20 | 1099 | */ |
f1ca1512 JR |
1100 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
1101 | struct iommu_cmd *cmd, | |
1102 | bool sync) | |
a19ae1ec | 1103 | { |
ac0ea6e9 | 1104 | u32 left, tail, head, next_tail; |
a19ae1ec | 1105 | unsigned long flags; |
a19ae1ec | 1106 | |
549c90dc | 1107 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
1108 | |
1109 | again: | |
a19ae1ec | 1110 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 1111 | |
ac0ea6e9 JR |
1112 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
1113 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
1114 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
1115 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 1116 | |
ac0ea6e9 JR |
1117 | if (left <= 2) { |
1118 | struct iommu_cmd sync_cmd; | |
1119 | volatile u64 sem = 0; | |
1120 | int ret; | |
8d201968 | 1121 | |
ac0ea6e9 JR |
1122 | build_completion_wait(&sync_cmd, (u64)&sem); |
1123 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 1124 | |
ac0ea6e9 JR |
1125 | spin_unlock_irqrestore(&iommu->lock, flags); |
1126 | ||
1127 | if ((ret = wait_on_sem(&sem)) != 0) | |
1128 | return ret; | |
1129 | ||
1130 | goto again; | |
8d201968 JR |
1131 | } |
1132 | ||
ac0ea6e9 JR |
1133 | copy_cmd_to_buffer(iommu, cmd, tail); |
1134 | ||
1135 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 1136 | iommu->need_sync = sync; |
ac0ea6e9 | 1137 | |
a19ae1ec | 1138 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1139 | |
815b33fd | 1140 | return 0; |
8d201968 JR |
1141 | } |
1142 | ||
f1ca1512 JR |
1143 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1144 | { | |
1145 | return iommu_queue_command_sync(iommu, cmd, true); | |
1146 | } | |
1147 | ||
8d201968 JR |
1148 | /* |
1149 | * This function queues a completion wait command into the command | |
1150 | * buffer of an IOMMU | |
1151 | */ | |
a19ae1ec | 1152 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1153 | { |
1154 | struct iommu_cmd cmd; | |
815b33fd | 1155 | volatile u64 sem = 0; |
ac0ea6e9 | 1156 | int ret; |
8d201968 | 1157 | |
09ee17eb | 1158 | if (!iommu->need_sync) |
815b33fd | 1159 | return 0; |
09ee17eb | 1160 | |
815b33fd | 1161 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1162 | |
f1ca1512 | 1163 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1164 | if (ret) |
815b33fd | 1165 | return ret; |
8d201968 | 1166 | |
ac0ea6e9 | 1167 | return wait_on_sem(&sem); |
8d201968 JR |
1168 | } |
1169 | ||
d8c13085 | 1170 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1171 | { |
d8c13085 | 1172 | struct iommu_cmd cmd; |
a19ae1ec | 1173 | |
d8c13085 | 1174 | build_inv_dte(&cmd, devid); |
7e4f88da | 1175 | |
d8c13085 JR |
1176 | return iommu_queue_command(iommu, &cmd); |
1177 | } | |
09ee17eb | 1178 | |
7d0c5cc5 JR |
1179 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1180 | { | |
1181 | u32 devid; | |
09ee17eb | 1182 | |
7d0c5cc5 JR |
1183 | for (devid = 0; devid <= 0xffff; ++devid) |
1184 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1185 | |
7d0c5cc5 JR |
1186 | iommu_completion_wait(iommu); |
1187 | } | |
84df8175 | 1188 | |
7d0c5cc5 JR |
1189 | /* |
1190 | * This function uses heavy locking and may disable irqs for some time. But | |
1191 | * this is no issue because it is only called during resume. | |
1192 | */ | |
1193 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1194 | { | |
1195 | u32 dom_id; | |
a19ae1ec | 1196 | |
7d0c5cc5 JR |
1197 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1198 | struct iommu_cmd cmd; | |
1199 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1200 | dom_id, 1); | |
1201 | iommu_queue_command(iommu, &cmd); | |
1202 | } | |
8eed9833 | 1203 | |
7d0c5cc5 | 1204 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1205 | } |
1206 | ||
58fc7f14 | 1207 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1208 | { |
58fc7f14 | 1209 | struct iommu_cmd cmd; |
0518a3a4 | 1210 | |
58fc7f14 | 1211 | build_inv_all(&cmd); |
0518a3a4 | 1212 | |
58fc7f14 JR |
1213 | iommu_queue_command(iommu, &cmd); |
1214 | iommu_completion_wait(iommu); | |
1215 | } | |
1216 | ||
7ef2798d JR |
1217 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1218 | { | |
1219 | struct iommu_cmd cmd; | |
1220 | ||
1221 | build_inv_irt(&cmd, devid); | |
1222 | ||
1223 | iommu_queue_command(iommu, &cmd); | |
1224 | } | |
1225 | ||
1226 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1227 | { | |
1228 | u32 devid; | |
1229 | ||
1230 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1231 | iommu_flush_irt(iommu, devid); | |
1232 | ||
1233 | iommu_completion_wait(iommu); | |
1234 | } | |
1235 | ||
7d0c5cc5 JR |
1236 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1237 | { | |
58fc7f14 JR |
1238 | if (iommu_feature(iommu, FEATURE_IA)) { |
1239 | iommu_flush_all(iommu); | |
1240 | } else { | |
1241 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1242 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1243 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1244 | } |
1245 | } | |
1246 | ||
431b2a20 | 1247 | /* |
cb41ed85 | 1248 | * Command send function for flushing on-device TLB |
431b2a20 | 1249 | */ |
6c542047 JR |
1250 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1251 | u64 address, size_t size) | |
3fa43655 JR |
1252 | { |
1253 | struct amd_iommu *iommu; | |
b00d3bcf | 1254 | struct iommu_cmd cmd; |
cb41ed85 | 1255 | int qdep; |
3fa43655 | 1256 | |
ea61cddb JR |
1257 | qdep = dev_data->ats.qdep; |
1258 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1259 | |
ea61cddb | 1260 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1261 | |
1262 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1263 | } |
1264 | ||
431b2a20 | 1265 | /* |
431b2a20 | 1266 | * Command send function for invalidating a device table entry |
431b2a20 | 1267 | */ |
6c542047 | 1268 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1269 | { |
3fa43655 | 1270 | struct amd_iommu *iommu; |
ee2fa743 | 1271 | int ret; |
a19ae1ec | 1272 | |
6c542047 | 1273 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1274 | |
f62dda66 | 1275 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1276 | if (ret) |
1277 | return ret; | |
1278 | ||
ea61cddb | 1279 | if (dev_data->ats.enabled) |
6c542047 | 1280 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1281 | |
ee2fa743 | 1282 | return ret; |
a19ae1ec JR |
1283 | } |
1284 | ||
431b2a20 JR |
1285 | /* |
1286 | * TLB invalidation function which is called from the mapping functions. | |
1287 | * It invalidates a single PTE if the range to flush is within a single | |
1288 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1289 | */ | |
17b124bf JR |
1290 | static void __domain_flush_pages(struct protection_domain *domain, |
1291 | u64 address, size_t size, int pde) | |
a19ae1ec | 1292 | { |
cb41ed85 | 1293 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1294 | struct iommu_cmd cmd; |
1295 | int ret = 0, i; | |
a19ae1ec | 1296 | |
11b6402c | 1297 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1298 | |
6de8ad9b JR |
1299 | for (i = 0; i < amd_iommus_present; ++i) { |
1300 | if (!domain->dev_iommu[i]) | |
1301 | continue; | |
1302 | ||
1303 | /* | |
1304 | * Devices of this domain are behind this IOMMU | |
1305 | * We need a TLB flush | |
1306 | */ | |
11b6402c | 1307 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1308 | } |
1309 | ||
cb41ed85 | 1310 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1311 | |
ea61cddb | 1312 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1313 | continue; |
1314 | ||
6c542047 | 1315 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1316 | } |
1317 | ||
11b6402c | 1318 | WARN_ON(ret); |
6de8ad9b JR |
1319 | } |
1320 | ||
17b124bf JR |
1321 | static void domain_flush_pages(struct protection_domain *domain, |
1322 | u64 address, size_t size) | |
6de8ad9b | 1323 | { |
17b124bf | 1324 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1325 | } |
b6c02715 | 1326 | |
1c655773 | 1327 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1328 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1329 | { |
17b124bf | 1330 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1331 | } |
1332 | ||
42a49f96 | 1333 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1334 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1335 | { |
17b124bf | 1336 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1337 | } |
1338 | ||
17b124bf | 1339 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1340 | { |
17b124bf | 1341 | int i; |
18811f55 | 1342 | |
17b124bf JR |
1343 | for (i = 0; i < amd_iommus_present; ++i) { |
1344 | if (!domain->dev_iommu[i]) | |
1345 | continue; | |
bfd1be18 | 1346 | |
17b124bf JR |
1347 | /* |
1348 | * Devices of this domain are behind this IOMMU | |
1349 | * We need to wait for completion of all commands. | |
1350 | */ | |
1351 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1352 | } |
e394d72a JR |
1353 | } |
1354 | ||
b00d3bcf | 1355 | |
09b42804 | 1356 | /* |
b00d3bcf | 1357 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1358 | */ |
17b124bf | 1359 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1360 | { |
b00d3bcf | 1361 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1362 | |
b00d3bcf | 1363 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1364 | device_flush_dte(dev_data); |
a345b23b JR |
1365 | } |
1366 | ||
431b2a20 JR |
1367 | /**************************************************************************** |
1368 | * | |
1369 | * The functions below are used the create the page table mappings for | |
1370 | * unity mapped regions. | |
1371 | * | |
1372 | ****************************************************************************/ | |
1373 | ||
308973d3 JR |
1374 | /* |
1375 | * This function is used to add another level to an IO page table. Adding | |
1376 | * another level increases the size of the address space by 9 bits to a size up | |
1377 | * to 64 bits. | |
1378 | */ | |
1379 | static bool increase_address_space(struct protection_domain *domain, | |
1380 | gfp_t gfp) | |
1381 | { | |
1382 | u64 *pte; | |
1383 | ||
1384 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1385 | /* address space already 64 bit large */ | |
1386 | return false; | |
1387 | ||
1388 | pte = (void *)get_zeroed_page(gfp); | |
1389 | if (!pte) | |
1390 | return false; | |
1391 | ||
1392 | *pte = PM_LEVEL_PDE(domain->mode, | |
1393 | virt_to_phys(domain->pt_root)); | |
1394 | domain->pt_root = pte; | |
1395 | domain->mode += 1; | |
1396 | domain->updated = true; | |
1397 | ||
1398 | return true; | |
1399 | } | |
1400 | ||
1401 | static u64 *alloc_pte(struct protection_domain *domain, | |
1402 | unsigned long address, | |
cbb9d729 | 1403 | unsigned long page_size, |
308973d3 JR |
1404 | u64 **pte_page, |
1405 | gfp_t gfp) | |
1406 | { | |
cbb9d729 | 1407 | int level, end_lvl; |
308973d3 | 1408 | u64 *pte, *page; |
cbb9d729 JR |
1409 | |
1410 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1411 | |
1412 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1413 | increase_address_space(domain, gfp); | |
1414 | ||
cbb9d729 JR |
1415 | level = domain->mode - 1; |
1416 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1417 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1418 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1419 | |
1420 | while (level > end_lvl) { | |
1421 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1422 | page = (u64 *)get_zeroed_page(gfp); | |
1423 | if (!page) | |
1424 | return NULL; | |
1425 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1426 | } | |
1427 | ||
cbb9d729 JR |
1428 | /* No level skipping support yet */ |
1429 | if (PM_PTE_LEVEL(*pte) != level) | |
1430 | return NULL; | |
1431 | ||
308973d3 JR |
1432 | level -= 1; |
1433 | ||
1434 | pte = IOMMU_PTE_PAGE(*pte); | |
1435 | ||
1436 | if (pte_page && level == end_lvl) | |
1437 | *pte_page = pte; | |
1438 | ||
1439 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1440 | } | |
1441 | ||
1442 | return pte; | |
1443 | } | |
1444 | ||
1445 | /* | |
1446 | * This function checks if there is a PTE for a given dma address. If | |
1447 | * there is one, it returns the pointer to it. | |
1448 | */ | |
24cd7723 | 1449 | static u64 *fetch_pte(struct protection_domain *domain, unsigned long address) |
308973d3 JR |
1450 | { |
1451 | int level; | |
1452 | u64 *pte; | |
1453 | ||
24cd7723 JR |
1454 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1455 | return NULL; | |
1456 | ||
1457 | level = domain->mode - 1; | |
1458 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
308973d3 | 1459 | |
24cd7723 JR |
1460 | while (level > 0) { |
1461 | ||
1462 | /* Not Present */ | |
308973d3 JR |
1463 | if (!IOMMU_PTE_PRESENT(*pte)) |
1464 | return NULL; | |
1465 | ||
24cd7723 JR |
1466 | /* Large PTE */ |
1467 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1468 | unsigned long pte_mask, __pte; | |
1469 | ||
1470 | /* | |
1471 | * If we have a series of large PTEs, make | |
1472 | * sure to return a pointer to the first one. | |
1473 | */ | |
1474 | pte_mask = PTE_PAGE_SIZE(*pte); | |
1475 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1476 | __pte = ((unsigned long)pte) & pte_mask; | |
1477 | ||
1478 | return (u64 *)__pte; | |
1479 | } | |
1480 | ||
1481 | /* No level skipping support yet */ | |
1482 | if (PM_PTE_LEVEL(*pte) != level) | |
1483 | return NULL; | |
1484 | ||
308973d3 JR |
1485 | level -= 1; |
1486 | ||
24cd7723 | 1487 | /* Walk to the next level */ |
308973d3 JR |
1488 | pte = IOMMU_PTE_PAGE(*pte); |
1489 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
308973d3 JR |
1490 | } |
1491 | ||
1492 | return pte; | |
1493 | } | |
1494 | ||
431b2a20 JR |
1495 | /* |
1496 | * Generic mapping functions. It maps a physical address into a DMA | |
1497 | * address space. It allocates the page table pages if necessary. | |
1498 | * In the future it can be extended to a generic mapping function | |
1499 | * supporting all features of AMD IOMMU page tables like level skipping | |
1500 | * and full 64 bit address spaces. | |
1501 | */ | |
38e817fe JR |
1502 | static int iommu_map_page(struct protection_domain *dom, |
1503 | unsigned long bus_addr, | |
1504 | unsigned long phys_addr, | |
abdc5eb3 | 1505 | int prot, |
cbb9d729 | 1506 | unsigned long page_size) |
bd0e5211 | 1507 | { |
8bda3092 | 1508 | u64 __pte, *pte; |
cbb9d729 | 1509 | int i, count; |
abdc5eb3 | 1510 | |
bad1cac2 | 1511 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1512 | return -EINVAL; |
1513 | ||
cbb9d729 JR |
1514 | bus_addr = PAGE_ALIGN(bus_addr); |
1515 | phys_addr = PAGE_ALIGN(phys_addr); | |
1516 | count = PAGE_SIZE_PTE_COUNT(page_size); | |
1517 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
1518 | ||
1519 | for (i = 0; i < count; ++i) | |
1520 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1521 | return -EBUSY; | |
bd0e5211 | 1522 | |
cbb9d729 JR |
1523 | if (page_size > PAGE_SIZE) { |
1524 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); | |
1525 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1526 | } else | |
1527 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1528 | |
bd0e5211 JR |
1529 | if (prot & IOMMU_PROT_IR) |
1530 | __pte |= IOMMU_PTE_IR; | |
1531 | if (prot & IOMMU_PROT_IW) | |
1532 | __pte |= IOMMU_PTE_IW; | |
1533 | ||
cbb9d729 JR |
1534 | for (i = 0; i < count; ++i) |
1535 | pte[i] = __pte; | |
bd0e5211 | 1536 | |
04bfdd84 JR |
1537 | update_domain(dom); |
1538 | ||
bd0e5211 JR |
1539 | return 0; |
1540 | } | |
1541 | ||
24cd7723 JR |
1542 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1543 | unsigned long bus_addr, | |
1544 | unsigned long page_size) | |
eb74ff6c | 1545 | { |
24cd7723 JR |
1546 | unsigned long long unmap_size, unmapped; |
1547 | u64 *pte; | |
1548 | ||
1549 | BUG_ON(!is_power_of_2(page_size)); | |
1550 | ||
1551 | unmapped = 0; | |
eb74ff6c | 1552 | |
24cd7723 JR |
1553 | while (unmapped < page_size) { |
1554 | ||
1555 | pte = fetch_pte(dom, bus_addr); | |
1556 | ||
1557 | if (!pte) { | |
1558 | /* | |
1559 | * No PTE for this address | |
1560 | * move forward in 4kb steps | |
1561 | */ | |
1562 | unmap_size = PAGE_SIZE; | |
1563 | } else if (PM_PTE_LEVEL(*pte) == 0) { | |
1564 | /* 4kb PTE found for this address */ | |
1565 | unmap_size = PAGE_SIZE; | |
1566 | *pte = 0ULL; | |
1567 | } else { | |
1568 | int count, i; | |
1569 | ||
1570 | /* Large PTE found which maps this address */ | |
1571 | unmap_size = PTE_PAGE_SIZE(*pte); | |
60d0ca3c AW |
1572 | |
1573 | /* Only unmap from the first pte in the page */ | |
1574 | if ((unmap_size - 1) & bus_addr) | |
1575 | break; | |
24cd7723 JR |
1576 | count = PAGE_SIZE_PTE_COUNT(unmap_size); |
1577 | for (i = 0; i < count; i++) | |
1578 | pte[i] = 0ULL; | |
1579 | } | |
1580 | ||
1581 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1582 | unmapped += unmap_size; | |
1583 | } | |
1584 | ||
60d0ca3c | 1585 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1586 | |
24cd7723 | 1587 | return unmapped; |
eb74ff6c | 1588 | } |
eb74ff6c | 1589 | |
431b2a20 JR |
1590 | /* |
1591 | * This function checks if a specific unity mapping entry is needed for | |
1592 | * this specific IOMMU. | |
1593 | */ | |
bd0e5211 JR |
1594 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
1595 | struct unity_map_entry *entry) | |
1596 | { | |
1597 | u16 bdf, i; | |
1598 | ||
1599 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
1600 | bdf = amd_iommu_alias_table[i]; | |
1601 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
1602 | return 1; | |
1603 | } | |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
431b2a20 JR |
1608 | /* |
1609 | * This function actually applies the mapping to the page table of the | |
1610 | * dma_ops domain. | |
1611 | */ | |
bd0e5211 JR |
1612 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
1613 | struct unity_map_entry *e) | |
1614 | { | |
1615 | u64 addr; | |
1616 | int ret; | |
1617 | ||
1618 | for (addr = e->address_start; addr < e->address_end; | |
1619 | addr += PAGE_SIZE) { | |
abdc5eb3 | 1620 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
cbb9d729 | 1621 | PAGE_SIZE); |
bd0e5211 JR |
1622 | if (ret) |
1623 | return ret; | |
1624 | /* | |
1625 | * if unity mapping is in aperture range mark the page | |
1626 | * as allocated in the aperture | |
1627 | */ | |
1628 | if (addr < dma_dom->aperture_size) | |
c3239567 | 1629 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 1630 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
1631 | } |
1632 | ||
1633 | return 0; | |
1634 | } | |
1635 | ||
171e7b37 JR |
1636 | /* |
1637 | * Init the unity mappings for a specific IOMMU in the system | |
1638 | * | |
1639 | * Basically iterates over all unity mapping entries and applies them to | |
1640 | * the default domain DMA of that IOMMU if necessary. | |
1641 | */ | |
1642 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) | |
1643 | { | |
1644 | struct unity_map_entry *entry; | |
1645 | int ret; | |
1646 | ||
1647 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
1648 | if (!iommu_for_unity_map(iommu, entry)) | |
1649 | continue; | |
1650 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
1651 | if (ret) | |
1652 | return ret; | |
1653 | } | |
1654 | ||
1655 | return 0; | |
1656 | } | |
1657 | ||
431b2a20 JR |
1658 | /* |
1659 | * Inits the unity mappings required for a specific device | |
1660 | */ | |
bd0e5211 JR |
1661 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
1662 | u16 devid) | |
1663 | { | |
1664 | struct unity_map_entry *e; | |
1665 | int ret; | |
1666 | ||
1667 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
1668 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
1669 | continue; | |
1670 | ret = dma_ops_unity_map(dma_dom, e); | |
1671 | if (ret) | |
1672 | return ret; | |
1673 | } | |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
431b2a20 JR |
1678 | /**************************************************************************** |
1679 | * | |
1680 | * The next functions belong to the address allocator for the dma_ops | |
1681 | * interface functions. They work like the allocators in the other IOMMU | |
1682 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1683 | * the aperture. Maybe it could be enhanced in the future to a more | |
1684 | * efficient allocator. | |
1685 | * | |
1686 | ****************************************************************************/ | |
d3086444 | 1687 | |
431b2a20 | 1688 | /* |
384de729 | 1689 | * The address allocator core functions. |
431b2a20 JR |
1690 | * |
1691 | * called with domain->lock held | |
1692 | */ | |
384de729 | 1693 | |
171e7b37 JR |
1694 | /* |
1695 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1696 | * ranges. | |
1697 | */ | |
1698 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1699 | unsigned long start_page, | |
1700 | unsigned int pages) | |
1701 | { | |
1702 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1703 | ||
1704 | if (start_page + pages > last_page) | |
1705 | pages = last_page - start_page; | |
1706 | ||
1707 | for (i = start_page; i < start_page + pages; ++i) { | |
1708 | int index = i / APERTURE_RANGE_PAGES; | |
1709 | int page = i % APERTURE_RANGE_PAGES; | |
1710 | __set_bit(page, dom->aperture[index]->bitmap); | |
1711 | } | |
1712 | } | |
1713 | ||
9cabe89b JR |
1714 | /* |
1715 | * This function is used to add a new aperture range to an existing | |
1716 | * aperture in case of dma_ops domain allocation or address allocation | |
1717 | * failure. | |
1718 | */ | |
576175c2 | 1719 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1720 | bool populate, gfp_t gfp) |
1721 | { | |
1722 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1723 | struct amd_iommu *iommu; |
17f5b569 | 1724 | unsigned long i, old_size; |
9cabe89b | 1725 | |
f5e9705c JR |
1726 | #ifdef CONFIG_IOMMU_STRESS |
1727 | populate = false; | |
1728 | #endif | |
1729 | ||
9cabe89b JR |
1730 | if (index >= APERTURE_MAX_RANGES) |
1731 | return -ENOMEM; | |
1732 | ||
1733 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1734 | if (!dma_dom->aperture[index]) | |
1735 | return -ENOMEM; | |
1736 | ||
1737 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1738 | if (!dma_dom->aperture[index]->bitmap) | |
1739 | goto out_free; | |
1740 | ||
1741 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1742 | ||
1743 | if (populate) { | |
1744 | unsigned long address = dma_dom->aperture_size; | |
1745 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1746 | u64 *pte, *pte_page; | |
1747 | ||
1748 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1749 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1750 | &pte_page, gfp); |
1751 | if (!pte) | |
1752 | goto out_free; | |
1753 | ||
1754 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1755 | ||
1756 | address += APERTURE_RANGE_SIZE / 64; | |
1757 | } | |
1758 | } | |
1759 | ||
17f5b569 | 1760 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1761 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1762 | ||
17f5b569 JR |
1763 | /* Reserve address range used for MSI messages */ |
1764 | if (old_size < MSI_ADDR_BASE_LO && | |
1765 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1766 | unsigned long spage; | |
1767 | int pages; | |
1768 | ||
1769 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1770 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1771 | ||
1772 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1773 | } | |
1774 | ||
b595076a | 1775 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1776 | for_each_iommu(iommu) { |
1777 | if (iommu->exclusion_start && | |
1778 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1779 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1780 | unsigned long startpage; | |
1781 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1782 | iommu->exclusion_length, | |
1783 | PAGE_SIZE); | |
1784 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1785 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1786 | } | |
00cd122a JR |
1787 | } |
1788 | ||
1789 | /* | |
1790 | * Check for areas already mapped as present in the new aperture | |
1791 | * range and mark those pages as reserved in the allocator. Such | |
1792 | * mappings may already exist as a result of requested unity | |
1793 | * mappings for devices. | |
1794 | */ | |
1795 | for (i = dma_dom->aperture[index]->offset; | |
1796 | i < dma_dom->aperture_size; | |
1797 | i += PAGE_SIZE) { | |
24cd7723 | 1798 | u64 *pte = fetch_pte(&dma_dom->domain, i); |
00cd122a JR |
1799 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1800 | continue; | |
1801 | ||
fcd0861d | 1802 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1); |
00cd122a JR |
1803 | } |
1804 | ||
04bfdd84 JR |
1805 | update_domain(&dma_dom->domain); |
1806 | ||
9cabe89b JR |
1807 | return 0; |
1808 | ||
1809 | out_free: | |
04bfdd84 JR |
1810 | update_domain(&dma_dom->domain); |
1811 | ||
9cabe89b JR |
1812 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1813 | ||
1814 | kfree(dma_dom->aperture[index]); | |
1815 | dma_dom->aperture[index] = NULL; | |
1816 | ||
1817 | return -ENOMEM; | |
1818 | } | |
1819 | ||
384de729 JR |
1820 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1821 | struct dma_ops_domain *dom, | |
1822 | unsigned int pages, | |
1823 | unsigned long align_mask, | |
1824 | u64 dma_mask, | |
1825 | unsigned long start) | |
1826 | { | |
803b8cb4 | 1827 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1828 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1829 | int i = start >> APERTURE_RANGE_SHIFT; | |
1830 | unsigned long boundary_size; | |
1831 | unsigned long address = -1; | |
1832 | unsigned long limit; | |
1833 | ||
803b8cb4 JR |
1834 | next_bit >>= PAGE_SHIFT; |
1835 | ||
384de729 JR |
1836 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
1837 | PAGE_SIZE) >> PAGE_SHIFT; | |
1838 | ||
1839 | for (;i < max_index; ++i) { | |
1840 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1841 | ||
1842 | if (dom->aperture[i]->offset >= dma_mask) | |
1843 | break; | |
1844 | ||
1845 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1846 | dma_mask >> PAGE_SHIFT); | |
1847 | ||
1848 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1849 | limit, next_bit, pages, 0, | |
1850 | boundary_size, align_mask); | |
1851 | if (address != -1) { | |
1852 | address = dom->aperture[i]->offset + | |
1853 | (address << PAGE_SHIFT); | |
803b8cb4 | 1854 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1855 | break; |
1856 | } | |
1857 | ||
1858 | next_bit = 0; | |
1859 | } | |
1860 | ||
1861 | return address; | |
1862 | } | |
1863 | ||
d3086444 JR |
1864 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1865 | struct dma_ops_domain *dom, | |
6d4f343f | 1866 | unsigned int pages, |
832a90c3 JR |
1867 | unsigned long align_mask, |
1868 | u64 dma_mask) | |
d3086444 | 1869 | { |
d3086444 | 1870 | unsigned long address; |
d3086444 | 1871 | |
fe16f088 JR |
1872 | #ifdef CONFIG_IOMMU_STRESS |
1873 | dom->next_address = 0; | |
1874 | dom->need_flush = true; | |
1875 | #endif | |
d3086444 | 1876 | |
384de729 | 1877 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1878 | dma_mask, dom->next_address); |
d3086444 | 1879 | |
1c655773 | 1880 | if (address == -1) { |
803b8cb4 | 1881 | dom->next_address = 0; |
384de729 JR |
1882 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1883 | dma_mask, 0); | |
1c655773 JR |
1884 | dom->need_flush = true; |
1885 | } | |
d3086444 | 1886 | |
384de729 | 1887 | if (unlikely(address == -1)) |
8fd524b3 | 1888 | address = DMA_ERROR_CODE; |
d3086444 JR |
1889 | |
1890 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1891 | ||
1892 | return address; | |
1893 | } | |
1894 | ||
431b2a20 JR |
1895 | /* |
1896 | * The address free function. | |
1897 | * | |
1898 | * called with domain->lock held | |
1899 | */ | |
d3086444 JR |
1900 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1901 | unsigned long address, | |
1902 | unsigned int pages) | |
1903 | { | |
384de729 JR |
1904 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1905 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1906 | |
384de729 JR |
1907 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1908 | ||
47bccd6b JR |
1909 | #ifdef CONFIG_IOMMU_STRESS |
1910 | if (i < 4) | |
1911 | return; | |
1912 | #endif | |
80be308d | 1913 | |
803b8cb4 | 1914 | if (address >= dom->next_address) |
80be308d | 1915 | dom->need_flush = true; |
384de729 JR |
1916 | |
1917 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1918 | |
a66022c4 | 1919 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1920 | |
d3086444 JR |
1921 | } |
1922 | ||
431b2a20 JR |
1923 | /**************************************************************************** |
1924 | * | |
1925 | * The next functions belong to the domain allocation. A domain is | |
1926 | * allocated for every IOMMU as the default domain. If device isolation | |
1927 | * is enabled, every device get its own domain. The most important thing | |
1928 | * about domains is the page table mapping the DMA address space they | |
1929 | * contain. | |
1930 | * | |
1931 | ****************************************************************************/ | |
1932 | ||
aeb26f55 JR |
1933 | /* |
1934 | * This function adds a protection domain to the global protection domain list | |
1935 | */ | |
1936 | static void add_domain_to_list(struct protection_domain *domain) | |
1937 | { | |
1938 | unsigned long flags; | |
1939 | ||
1940 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1941 | list_add(&domain->list, &amd_iommu_pd_list); | |
1942 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1943 | } | |
1944 | ||
1945 | /* | |
1946 | * This function removes a protection domain to the global | |
1947 | * protection domain list | |
1948 | */ | |
1949 | static void del_domain_from_list(struct protection_domain *domain) | |
1950 | { | |
1951 | unsigned long flags; | |
1952 | ||
1953 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1954 | list_del(&domain->list); | |
1955 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1956 | } | |
1957 | ||
ec487d1a JR |
1958 | static u16 domain_id_alloc(void) |
1959 | { | |
1960 | unsigned long flags; | |
1961 | int id; | |
1962 | ||
1963 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1964 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1965 | BUG_ON(id == 0); | |
1966 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1967 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1968 | else | |
1969 | id = 0; | |
1970 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1971 | ||
1972 | return id; | |
1973 | } | |
1974 | ||
a2acfb75 JR |
1975 | static void domain_id_free(int id) |
1976 | { | |
1977 | unsigned long flags; | |
1978 | ||
1979 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1980 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1981 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1982 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1983 | } | |
a2acfb75 | 1984 | |
5c34c403 JR |
1985 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1986 | static void free_pt_##LVL (unsigned long __pt) \ | |
1987 | { \ | |
1988 | unsigned long p; \ | |
1989 | u64 *pt; \ | |
1990 | int i; \ | |
1991 | \ | |
1992 | pt = (u64 *)__pt; \ | |
1993 | \ | |
1994 | for (i = 0; i < 512; ++i) { \ | |
1995 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1996 | continue; \ | |
1997 | \ | |
1998 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1999 | FN(p); \ | |
2000 | } \ | |
2001 | free_page((unsigned long)pt); \ | |
2002 | } | |
2003 | ||
2004 | DEFINE_FREE_PT_FN(l2, free_page) | |
2005 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
2006 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
2007 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
2008 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
2009 | ||
86db2e5d | 2010 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 2011 | { |
5c34c403 | 2012 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 2013 | |
5c34c403 JR |
2014 | switch (domain->mode) { |
2015 | case PAGE_MODE_NONE: | |
2016 | break; | |
2017 | case PAGE_MODE_1_LEVEL: | |
2018 | free_page(root); | |
2019 | break; | |
2020 | case PAGE_MODE_2_LEVEL: | |
2021 | free_pt_l2(root); | |
2022 | break; | |
2023 | case PAGE_MODE_3_LEVEL: | |
2024 | free_pt_l3(root); | |
2025 | break; | |
2026 | case PAGE_MODE_4_LEVEL: | |
2027 | free_pt_l4(root); | |
2028 | break; | |
2029 | case PAGE_MODE_5_LEVEL: | |
2030 | free_pt_l5(root); | |
2031 | break; | |
2032 | case PAGE_MODE_6_LEVEL: | |
2033 | free_pt_l6(root); | |
2034 | break; | |
2035 | default: | |
2036 | BUG(); | |
ec487d1a | 2037 | } |
ec487d1a JR |
2038 | } |
2039 | ||
b16137b1 JR |
2040 | static void free_gcr3_tbl_level1(u64 *tbl) |
2041 | { | |
2042 | u64 *ptr; | |
2043 | int i; | |
2044 | ||
2045 | for (i = 0; i < 512; ++i) { | |
2046 | if (!(tbl[i] & GCR3_VALID)) | |
2047 | continue; | |
2048 | ||
2049 | ptr = __va(tbl[i] & PAGE_MASK); | |
2050 | ||
2051 | free_page((unsigned long)ptr); | |
2052 | } | |
2053 | } | |
2054 | ||
2055 | static void free_gcr3_tbl_level2(u64 *tbl) | |
2056 | { | |
2057 | u64 *ptr; | |
2058 | int i; | |
2059 | ||
2060 | for (i = 0; i < 512; ++i) { | |
2061 | if (!(tbl[i] & GCR3_VALID)) | |
2062 | continue; | |
2063 | ||
2064 | ptr = __va(tbl[i] & PAGE_MASK); | |
2065 | ||
2066 | free_gcr3_tbl_level1(ptr); | |
2067 | } | |
2068 | } | |
2069 | ||
52815b75 JR |
2070 | static void free_gcr3_table(struct protection_domain *domain) |
2071 | { | |
b16137b1 JR |
2072 | if (domain->glx == 2) |
2073 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
2074 | else if (domain->glx == 1) | |
2075 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
2076 | else if (domain->glx != 0) | |
2077 | BUG(); | |
2078 | ||
52815b75 JR |
2079 | free_page((unsigned long)domain->gcr3_tbl); |
2080 | } | |
2081 | ||
431b2a20 JR |
2082 | /* |
2083 | * Free a domain, only used if something went wrong in the | |
2084 | * allocation path and we need to free an already allocated page table | |
2085 | */ | |
ec487d1a JR |
2086 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
2087 | { | |
384de729 JR |
2088 | int i; |
2089 | ||
ec487d1a JR |
2090 | if (!dom) |
2091 | return; | |
2092 | ||
aeb26f55 JR |
2093 | del_domain_from_list(&dom->domain); |
2094 | ||
86db2e5d | 2095 | free_pagetable(&dom->domain); |
ec487d1a | 2096 | |
384de729 JR |
2097 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
2098 | if (!dom->aperture[i]) | |
2099 | continue; | |
2100 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
2101 | kfree(dom->aperture[i]); | |
2102 | } | |
ec487d1a JR |
2103 | |
2104 | kfree(dom); | |
2105 | } | |
2106 | ||
431b2a20 JR |
2107 | /* |
2108 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 2109 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
2110 | * structures required for the dma_ops interface |
2111 | */ | |
87a64d52 | 2112 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
2113 | { |
2114 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
2115 | |
2116 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
2117 | if (!dma_dom) | |
2118 | return NULL; | |
2119 | ||
2120 | spin_lock_init(&dma_dom->domain.lock); | |
2121 | ||
2122 | dma_dom->domain.id = domain_id_alloc(); | |
2123 | if (dma_dom->domain.id == 0) | |
2124 | goto free_dma_dom; | |
7c392cbe | 2125 | INIT_LIST_HEAD(&dma_dom->domain.dev_list); |
8f7a017c | 2126 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 2127 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 2128 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
2129 | dma_dom->domain.priv = dma_dom; |
2130 | if (!dma_dom->domain.pt_root) | |
2131 | goto free_dma_dom; | |
ec487d1a | 2132 | |
1c655773 | 2133 | dma_dom->need_flush = false; |
bd60b735 | 2134 | dma_dom->target_dev = 0xffff; |
1c655773 | 2135 | |
aeb26f55 JR |
2136 | add_domain_to_list(&dma_dom->domain); |
2137 | ||
576175c2 | 2138 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 2139 | goto free_dma_dom; |
ec487d1a | 2140 | |
431b2a20 | 2141 | /* |
ec487d1a JR |
2142 | * mark the first page as allocated so we never return 0 as |
2143 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 2144 | */ |
384de729 | 2145 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 2146 | dma_dom->next_address = 0; |
ec487d1a | 2147 | |
ec487d1a JR |
2148 | |
2149 | return dma_dom; | |
2150 | ||
2151 | free_dma_dom: | |
2152 | dma_ops_domain_free(dma_dom); | |
2153 | ||
2154 | return NULL; | |
2155 | } | |
2156 | ||
5b28df6f JR |
2157 | /* |
2158 | * little helper function to check whether a given protection domain is a | |
2159 | * dma_ops domain | |
2160 | */ | |
2161 | static bool dma_ops_domain(struct protection_domain *domain) | |
2162 | { | |
2163 | return domain->flags & PD_DMA_OPS_MASK; | |
2164 | } | |
2165 | ||
fd7b5535 | 2166 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 2167 | { |
132bd68f | 2168 | u64 pte_root = 0; |
ee6c2868 | 2169 | u64 flags = 0; |
863c74eb | 2170 | |
132bd68f JR |
2171 | if (domain->mode != PAGE_MODE_NONE) |
2172 | pte_root = virt_to_phys(domain->pt_root); | |
2173 | ||
38ddf41b JR |
2174 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
2175 | << DEV_ENTRY_MODE_SHIFT; | |
2176 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 2177 | |
ee6c2868 JR |
2178 | flags = amd_iommu_dev_table[devid].data[1]; |
2179 | ||
fd7b5535 JR |
2180 | if (ats) |
2181 | flags |= DTE_FLAG_IOTLB; | |
2182 | ||
52815b75 JR |
2183 | if (domain->flags & PD_IOMMUV2_MASK) { |
2184 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
2185 | u64 glx = domain->glx; | |
2186 | u64 tmp; | |
2187 | ||
2188 | pte_root |= DTE_FLAG_GV; | |
2189 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
2190 | ||
2191 | /* First mask out possible old values for GCR3 table */ | |
2192 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
2193 | flags &= ~tmp; | |
2194 | ||
2195 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
2196 | flags &= ~tmp; | |
2197 | ||
2198 | /* Encode GCR3 table into DTE */ | |
2199 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
2200 | pte_root |= tmp; | |
2201 | ||
2202 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
2203 | flags |= tmp; | |
2204 | ||
2205 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
2206 | flags |= tmp; | |
2207 | } | |
2208 | ||
ee6c2868 JR |
2209 | flags &= ~(0xffffUL); |
2210 | flags |= domain->id; | |
2211 | ||
2212 | amd_iommu_dev_table[devid].data[1] = flags; | |
2213 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
2214 | } |
2215 | ||
2216 | static void clear_dte_entry(u16 devid) | |
2217 | { | |
15898bbc JR |
2218 | /* remove entry from the device table seen by the hardware */ |
2219 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
2220 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
2221 | |
2222 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
2223 | } |
2224 | ||
ec9e79ef JR |
2225 | static void do_attach(struct iommu_dev_data *dev_data, |
2226 | struct protection_domain *domain) | |
7f760ddd | 2227 | { |
7f760ddd | 2228 | struct amd_iommu *iommu; |
ec9e79ef | 2229 | bool ats; |
fd7b5535 | 2230 | |
ec9e79ef JR |
2231 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
2232 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
2233 | |
2234 | /* Update data structures */ | |
2235 | dev_data->domain = domain; | |
2236 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 2237 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
2238 | |
2239 | /* Do reference counting */ | |
2240 | domain->dev_iommu[iommu->index] += 1; | |
2241 | domain->dev_cnt += 1; | |
2242 | ||
2243 | /* Flush the DTE entry */ | |
6c542047 | 2244 | device_flush_dte(dev_data); |
7f760ddd JR |
2245 | } |
2246 | ||
ec9e79ef | 2247 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2248 | { |
7f760ddd | 2249 | struct amd_iommu *iommu; |
7f760ddd | 2250 | |
ec9e79ef | 2251 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2252 | |
2253 | /* decrease reference counters */ | |
7f760ddd JR |
2254 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2255 | dev_data->domain->dev_cnt -= 1; | |
2256 | ||
2257 | /* Update data structures */ | |
2258 | dev_data->domain = NULL; | |
2259 | list_del(&dev_data->list); | |
f62dda66 | 2260 | clear_dte_entry(dev_data->devid); |
15898bbc | 2261 | |
7f760ddd | 2262 | /* Flush the DTE entry */ |
6c542047 | 2263 | device_flush_dte(dev_data); |
2b681faf JR |
2264 | } |
2265 | ||
2266 | /* | |
2267 | * If a device is not yet associated with a domain, this function does | |
2268 | * assigns it visible for the hardware | |
2269 | */ | |
ec9e79ef | 2270 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2271 | struct protection_domain *domain) |
2b681faf | 2272 | { |
84fe6c19 | 2273 | int ret; |
657cbb6b | 2274 | |
2b681faf JR |
2275 | /* lock domain */ |
2276 | spin_lock(&domain->lock); | |
2277 | ||
71f77580 JR |
2278 | if (dev_data->alias_data != NULL) { |
2279 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
15898bbc | 2280 | |
2b02b091 JR |
2281 | /* Some sanity checks */ |
2282 | ret = -EBUSY; | |
2283 | if (alias_data->domain != NULL && | |
2284 | alias_data->domain != domain) | |
2285 | goto out_unlock; | |
eba6ac60 | 2286 | |
2b02b091 JR |
2287 | if (dev_data->domain != NULL && |
2288 | dev_data->domain != domain) | |
2289 | goto out_unlock; | |
15898bbc | 2290 | |
2b02b091 | 2291 | /* Do real assignment */ |
7f760ddd | 2292 | if (alias_data->domain == NULL) |
ec9e79ef | 2293 | do_attach(alias_data, domain); |
24100055 JR |
2294 | |
2295 | atomic_inc(&alias_data->bind); | |
657cbb6b | 2296 | } |
15898bbc | 2297 | |
7f760ddd | 2298 | if (dev_data->domain == NULL) |
ec9e79ef | 2299 | do_attach(dev_data, domain); |
eba6ac60 | 2300 | |
24100055 JR |
2301 | atomic_inc(&dev_data->bind); |
2302 | ||
84fe6c19 JL |
2303 | ret = 0; |
2304 | ||
2305 | out_unlock: | |
2306 | ||
eba6ac60 JR |
2307 | /* ready */ |
2308 | spin_unlock(&domain->lock); | |
15898bbc | 2309 | |
84fe6c19 | 2310 | return ret; |
0feae533 | 2311 | } |
b20ac0d4 | 2312 | |
52815b75 JR |
2313 | |
2314 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2315 | { | |
2316 | pci_disable_ats(pdev); | |
2317 | pci_disable_pri(pdev); | |
2318 | pci_disable_pasid(pdev); | |
2319 | } | |
2320 | ||
6a113ddc JR |
2321 | /* FIXME: Change generic reset-function to do the same */ |
2322 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2323 | { | |
2324 | u16 control; | |
2325 | int pos; | |
2326 | ||
46277b75 | 2327 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2328 | if (!pos) |
2329 | return -EINVAL; | |
2330 | ||
46277b75 JR |
2331 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2332 | control |= PCI_PRI_CTRL_RESET; | |
2333 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2334 | |
2335 | return 0; | |
2336 | } | |
2337 | ||
52815b75 JR |
2338 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2339 | { | |
6a113ddc JR |
2340 | bool reset_enable; |
2341 | int reqs, ret; | |
2342 | ||
2343 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2344 | reqs = 32; | |
2345 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2346 | reqs = 1; | |
2347 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2348 | |
2349 | /* Only allow access to user-accessible pages */ | |
2350 | ret = pci_enable_pasid(pdev, 0); | |
2351 | if (ret) | |
2352 | goto out_err; | |
2353 | ||
2354 | /* First reset the PRI state of the device */ | |
2355 | ret = pci_reset_pri(pdev); | |
2356 | if (ret) | |
2357 | goto out_err; | |
2358 | ||
6a113ddc JR |
2359 | /* Enable PRI */ |
2360 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2361 | if (ret) |
2362 | goto out_err; | |
2363 | ||
6a113ddc JR |
2364 | if (reset_enable) { |
2365 | ret = pri_reset_while_enabled(pdev); | |
2366 | if (ret) | |
2367 | goto out_err; | |
2368 | } | |
2369 | ||
52815b75 JR |
2370 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2371 | if (ret) | |
2372 | goto out_err; | |
2373 | ||
2374 | return 0; | |
2375 | ||
2376 | out_err: | |
2377 | pci_disable_pri(pdev); | |
2378 | pci_disable_pasid(pdev); | |
2379 | ||
2380 | return ret; | |
2381 | } | |
2382 | ||
c99afa25 | 2383 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2384 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2385 | |
98f1ad25 | 2386 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2387 | { |
a3b93121 | 2388 | u16 status; |
c99afa25 JR |
2389 | int pos; |
2390 | ||
46277b75 | 2391 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2392 | if (!pos) |
2393 | return false; | |
2394 | ||
a3b93121 | 2395 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2396 | |
a3b93121 | 2397 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2398 | } |
2399 | ||
407d733e | 2400 | /* |
df805abb | 2401 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2402 | * assigns it visible for the hardware |
2403 | */ | |
15898bbc JR |
2404 | static int attach_device(struct device *dev, |
2405 | struct protection_domain *domain) | |
0feae533 | 2406 | { |
fd7b5535 | 2407 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2408 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2409 | unsigned long flags; |
15898bbc | 2410 | int ret; |
eba6ac60 | 2411 | |
ea61cddb JR |
2412 | dev_data = get_dev_data(dev); |
2413 | ||
52815b75 JR |
2414 | if (domain->flags & PD_IOMMUV2_MASK) { |
2415 | if (!dev_data->iommu_v2 || !dev_data->passthrough) | |
2416 | return -EINVAL; | |
2417 | ||
2418 | if (pdev_iommuv2_enable(pdev) != 0) | |
2419 | return -EINVAL; | |
2420 | ||
2421 | dev_data->ats.enabled = true; | |
2422 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
c99afa25 | 2423 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); |
52815b75 JR |
2424 | } else if (amd_iommu_iotlb_sup && |
2425 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2426 | dev_data->ats.enabled = true; |
2427 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2428 | } | |
fd7b5535 | 2429 | |
eba6ac60 | 2430 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2431 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2432 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2433 | ||
0feae533 JR |
2434 | /* |
2435 | * We might boot into a crash-kernel here. The crashed kernel | |
2436 | * left the caches in the IOMMU dirty. So we have to flush | |
2437 | * here to evict all dirty stuff. | |
2438 | */ | |
17b124bf | 2439 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2440 | |
2441 | return ret; | |
b20ac0d4 JR |
2442 | } |
2443 | ||
355bf553 JR |
2444 | /* |
2445 | * Removes a device from a protection domain (unlocked) | |
2446 | */ | |
ec9e79ef | 2447 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2448 | { |
2ca76279 | 2449 | struct protection_domain *domain; |
7c392cbe | 2450 | unsigned long flags; |
c4596114 | 2451 | |
7f760ddd | 2452 | BUG_ON(!dev_data->domain); |
355bf553 | 2453 | |
2ca76279 JR |
2454 | domain = dev_data->domain; |
2455 | ||
2456 | spin_lock_irqsave(&domain->lock, flags); | |
24100055 | 2457 | |
71f77580 JR |
2458 | if (dev_data->alias_data != NULL) { |
2459 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2460 | ||
7f760ddd | 2461 | if (atomic_dec_and_test(&alias_data->bind)) |
ec9e79ef | 2462 | do_detach(alias_data); |
24100055 JR |
2463 | } |
2464 | ||
7f760ddd | 2465 | if (atomic_dec_and_test(&dev_data->bind)) |
ec9e79ef | 2466 | do_detach(dev_data); |
7f760ddd | 2467 | |
2ca76279 | 2468 | spin_unlock_irqrestore(&domain->lock, flags); |
21129f78 JR |
2469 | |
2470 | /* | |
2471 | * If we run in passthrough mode the device must be assigned to the | |
d3ad9373 JR |
2472 | * passthrough domain if it is detached from any other domain. |
2473 | * Make sure we can deassign from the pt_domain itself. | |
21129f78 | 2474 | */ |
5abcdba4 | 2475 | if (dev_data->passthrough && |
d3ad9373 | 2476 | (dev_data->domain == NULL && domain != pt_domain)) |
ec9e79ef | 2477 | __attach_device(dev_data, pt_domain); |
355bf553 JR |
2478 | } |
2479 | ||
2480 | /* | |
2481 | * Removes a device from a protection domain (with devtable_lock held) | |
2482 | */ | |
15898bbc | 2483 | static void detach_device(struct device *dev) |
355bf553 | 2484 | { |
52815b75 | 2485 | struct protection_domain *domain; |
ea61cddb | 2486 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2487 | unsigned long flags; |
2488 | ||
ec9e79ef | 2489 | dev_data = get_dev_data(dev); |
52815b75 | 2490 | domain = dev_data->domain; |
ec9e79ef | 2491 | |
355bf553 JR |
2492 | /* lock device table */ |
2493 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2494 | __detach_device(dev_data); |
355bf553 | 2495 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2496 | |
52815b75 JR |
2497 | if (domain->flags & PD_IOMMUV2_MASK) |
2498 | pdev_iommuv2_disable(to_pci_dev(dev)); | |
2499 | else if (dev_data->ats.enabled) | |
ea61cddb | 2500 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2501 | |
2502 | dev_data->ats.enabled = false; | |
355bf553 | 2503 | } |
e275a2a0 | 2504 | |
15898bbc JR |
2505 | /* |
2506 | * Find out the protection domain structure for a given PCI device. This | |
2507 | * will give us the pointer to the page table root for example. | |
2508 | */ | |
2509 | static struct protection_domain *domain_for_device(struct device *dev) | |
2510 | { | |
71f77580 | 2511 | struct iommu_dev_data *dev_data; |
2b02b091 | 2512 | struct protection_domain *dom = NULL; |
15898bbc | 2513 | unsigned long flags; |
15898bbc | 2514 | |
657cbb6b | 2515 | dev_data = get_dev_data(dev); |
15898bbc | 2516 | |
2b02b091 JR |
2517 | if (dev_data->domain) |
2518 | return dev_data->domain; | |
15898bbc | 2519 | |
71f77580 JR |
2520 | if (dev_data->alias_data != NULL) { |
2521 | struct iommu_dev_data *alias_data = dev_data->alias_data; | |
2b02b091 JR |
2522 | |
2523 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2524 | if (alias_data->domain != NULL) { | |
2525 | __attach_device(dev_data, alias_data->domain); | |
2526 | dom = alias_data->domain; | |
2527 | } | |
2528 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2529 | } | |
15898bbc JR |
2530 | |
2531 | return dom; | |
2532 | } | |
2533 | ||
e275a2a0 JR |
2534 | static int device_change_notifier(struct notifier_block *nb, |
2535 | unsigned long action, void *data) | |
2536 | { | |
e275a2a0 | 2537 | struct dma_ops_domain *dma_domain; |
5abcdba4 JR |
2538 | struct protection_domain *domain; |
2539 | struct iommu_dev_data *dev_data; | |
2540 | struct device *dev = data; | |
e275a2a0 | 2541 | struct amd_iommu *iommu; |
1ac4cbbc | 2542 | unsigned long flags; |
5abcdba4 | 2543 | u16 devid; |
e275a2a0 | 2544 | |
98fc5a69 JR |
2545 | if (!check_device(dev)) |
2546 | return 0; | |
e275a2a0 | 2547 | |
5abcdba4 JR |
2548 | devid = get_device_id(dev); |
2549 | iommu = amd_iommu_rlookup_table[devid]; | |
2550 | dev_data = get_dev_data(dev); | |
e275a2a0 JR |
2551 | |
2552 | switch (action) { | |
c1eee67b | 2553 | case BUS_NOTIFY_UNBOUND_DRIVER: |
657cbb6b JR |
2554 | |
2555 | domain = domain_for_device(dev); | |
2556 | ||
e275a2a0 JR |
2557 | if (!domain) |
2558 | goto out; | |
5abcdba4 | 2559 | if (dev_data->passthrough) |
a1ca331c | 2560 | break; |
15898bbc | 2561 | detach_device(dev); |
1ac4cbbc JR |
2562 | break; |
2563 | case BUS_NOTIFY_ADD_DEVICE: | |
657cbb6b JR |
2564 | |
2565 | iommu_init_device(dev); | |
2566 | ||
2c9195e9 JR |
2567 | /* |
2568 | * dev_data is still NULL and | |
2569 | * got initialized in iommu_init_device | |
2570 | */ | |
2571 | dev_data = get_dev_data(dev); | |
2572 | ||
2573 | if (iommu_pass_through || dev_data->iommu_v2) { | |
2574 | dev_data->passthrough = true; | |
2575 | attach_device(dev, pt_domain); | |
2576 | break; | |
2577 | } | |
2578 | ||
657cbb6b JR |
2579 | domain = domain_for_device(dev); |
2580 | ||
1ac4cbbc JR |
2581 | /* allocate a protection domain if a device is added */ |
2582 | dma_domain = find_protection_domain(devid); | |
c2a2876e JR |
2583 | if (!dma_domain) { |
2584 | dma_domain = dma_ops_domain_alloc(); | |
2585 | if (!dma_domain) | |
2586 | goto out; | |
2587 | dma_domain->target_dev = devid; | |
2588 | ||
2589 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
2590 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
2591 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
2592 | } | |
ac1534a5 | 2593 | |
2c9195e9 | 2594 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
ac1534a5 | 2595 | |
e275a2a0 | 2596 | break; |
657cbb6b JR |
2597 | case BUS_NOTIFY_DEL_DEVICE: |
2598 | ||
2599 | iommu_uninit_device(dev); | |
2600 | ||
e275a2a0 JR |
2601 | default: |
2602 | goto out; | |
2603 | } | |
2604 | ||
e275a2a0 JR |
2605 | iommu_completion_wait(iommu); |
2606 | ||
2607 | out: | |
2608 | return 0; | |
2609 | } | |
2610 | ||
b25ae679 | 2611 | static struct notifier_block device_nb = { |
e275a2a0 JR |
2612 | .notifier_call = device_change_notifier, |
2613 | }; | |
355bf553 | 2614 | |
8638c491 JR |
2615 | void amd_iommu_init_notifier(void) |
2616 | { | |
2617 | bus_register_notifier(&pci_bus_type, &device_nb); | |
2618 | } | |
2619 | ||
431b2a20 JR |
2620 | /***************************************************************************** |
2621 | * | |
2622 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2623 | * | |
2624 | *****************************************************************************/ | |
2625 | ||
2626 | /* | |
2627 | * In the dma_ops path we only have the struct device. This function | |
2628 | * finds the corresponding IOMMU, the protection domain and the | |
2629 | * requestor id for a given device. | |
2630 | * If the device is not yet associated with a domain this is also done | |
2631 | * in this function. | |
2632 | */ | |
94f6d190 | 2633 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2634 | { |
94f6d190 | 2635 | struct protection_domain *domain; |
b20ac0d4 | 2636 | struct dma_ops_domain *dma_dom; |
94f6d190 | 2637 | u16 devid = get_device_id(dev); |
b20ac0d4 | 2638 | |
f99c0f1c | 2639 | if (!check_device(dev)) |
94f6d190 | 2640 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2641 | |
94f6d190 JR |
2642 | domain = domain_for_device(dev); |
2643 | if (domain != NULL && !dma_ops_domain(domain)) | |
2644 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 2645 | |
94f6d190 JR |
2646 | if (domain != NULL) |
2647 | return domain; | |
b20ac0d4 | 2648 | |
df805abb | 2649 | /* Device not bound yet - bind it */ |
94f6d190 | 2650 | dma_dom = find_protection_domain(devid); |
15898bbc | 2651 | if (!dma_dom) |
94f6d190 JR |
2652 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
2653 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 2654 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 2655 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 2656 | |
94f6d190 | 2657 | return &dma_dom->domain; |
b20ac0d4 JR |
2658 | } |
2659 | ||
04bfdd84 JR |
2660 | static void update_device_table(struct protection_domain *domain) |
2661 | { | |
492667da | 2662 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2663 | |
ea61cddb JR |
2664 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2665 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2666 | } |
2667 | ||
2668 | static void update_domain(struct protection_domain *domain) | |
2669 | { | |
2670 | if (!domain->updated) | |
2671 | return; | |
2672 | ||
2673 | update_device_table(domain); | |
17b124bf JR |
2674 | |
2675 | domain_flush_devices(domain); | |
2676 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2677 | |
2678 | domain->updated = false; | |
2679 | } | |
2680 | ||
8bda3092 JR |
2681 | /* |
2682 | * This function fetches the PTE for a given address in the aperture | |
2683 | */ | |
2684 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2685 | unsigned long address) | |
2686 | { | |
384de729 | 2687 | struct aperture_range *aperture; |
8bda3092 JR |
2688 | u64 *pte, *pte_page; |
2689 | ||
384de729 JR |
2690 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2691 | if (!aperture) | |
2692 | return NULL; | |
2693 | ||
2694 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2695 | if (!pte) { |
cbb9d729 | 2696 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2697 | GFP_ATOMIC); |
384de729 JR |
2698 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2699 | } else | |
8c8c143c | 2700 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2701 | |
04bfdd84 | 2702 | update_domain(&dom->domain); |
8bda3092 JR |
2703 | |
2704 | return pte; | |
2705 | } | |
2706 | ||
431b2a20 JR |
2707 | /* |
2708 | * This is the generic map function. It maps one 4kb page at paddr to | |
2709 | * the given address in the DMA address space for the domain. | |
2710 | */ | |
680525e0 | 2711 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2712 | unsigned long address, |
2713 | phys_addr_t paddr, | |
2714 | int direction) | |
2715 | { | |
2716 | u64 *pte, __pte; | |
2717 | ||
2718 | WARN_ON(address > dom->aperture_size); | |
2719 | ||
2720 | paddr &= PAGE_MASK; | |
2721 | ||
8bda3092 | 2722 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2723 | if (!pte) |
8fd524b3 | 2724 | return DMA_ERROR_CODE; |
cb76c322 JR |
2725 | |
2726 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2727 | ||
2728 | if (direction == DMA_TO_DEVICE) | |
2729 | __pte |= IOMMU_PTE_IR; | |
2730 | else if (direction == DMA_FROM_DEVICE) | |
2731 | __pte |= IOMMU_PTE_IW; | |
2732 | else if (direction == DMA_BIDIRECTIONAL) | |
2733 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2734 | ||
2735 | WARN_ON(*pte); | |
2736 | ||
2737 | *pte = __pte; | |
2738 | ||
2739 | return (dma_addr_t)address; | |
2740 | } | |
2741 | ||
431b2a20 JR |
2742 | /* |
2743 | * The generic unmapping function for on page in the DMA address space. | |
2744 | */ | |
680525e0 | 2745 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2746 | unsigned long address) |
2747 | { | |
384de729 | 2748 | struct aperture_range *aperture; |
cb76c322 JR |
2749 | u64 *pte; |
2750 | ||
2751 | if (address >= dom->aperture_size) | |
2752 | return; | |
2753 | ||
384de729 JR |
2754 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2755 | if (!aperture) | |
2756 | return; | |
2757 | ||
2758 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2759 | if (!pte) | |
2760 | return; | |
cb76c322 | 2761 | |
8c8c143c | 2762 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2763 | |
2764 | WARN_ON(!*pte); | |
2765 | ||
2766 | *pte = 0ULL; | |
2767 | } | |
2768 | ||
431b2a20 JR |
2769 | /* |
2770 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2771 | * contiguous memory region into DMA address space. It is used by all |
2772 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2773 | * Must be called with the domain lock held. |
2774 | */ | |
cb76c322 | 2775 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2776 | struct dma_ops_domain *dma_dom, |
2777 | phys_addr_t paddr, | |
2778 | size_t size, | |
6d4f343f | 2779 | int dir, |
832a90c3 JR |
2780 | bool align, |
2781 | u64 dma_mask) | |
cb76c322 JR |
2782 | { |
2783 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2784 | dma_addr_t address, start, ret; |
cb76c322 | 2785 | unsigned int pages; |
6d4f343f | 2786 | unsigned long align_mask = 0; |
cb76c322 JR |
2787 | int i; |
2788 | ||
e3c449f5 | 2789 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2790 | paddr &= PAGE_MASK; |
2791 | ||
8ecaf8f1 JR |
2792 | INC_STATS_COUNTER(total_map_requests); |
2793 | ||
c1858976 JR |
2794 | if (pages > 1) |
2795 | INC_STATS_COUNTER(cross_page); | |
2796 | ||
6d4f343f JR |
2797 | if (align) |
2798 | align_mask = (1UL << get_order(size)) - 1; | |
2799 | ||
11b83888 | 2800 | retry: |
832a90c3 JR |
2801 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2802 | dma_mask); | |
8fd524b3 | 2803 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2804 | /* |
2805 | * setting next_address here will let the address | |
2806 | * allocator only scan the new allocated range in the | |
2807 | * first run. This is a small optimization. | |
2808 | */ | |
2809 | dma_dom->next_address = dma_dom->aperture_size; | |
2810 | ||
576175c2 | 2811 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2812 | goto out; |
2813 | ||
2814 | /* | |
af901ca1 | 2815 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2816 | * allocation again |
2817 | */ | |
2818 | goto retry; | |
2819 | } | |
cb76c322 JR |
2820 | |
2821 | start = address; | |
2822 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2823 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2824 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2825 | goto out_unmap; |
2826 | ||
cb76c322 JR |
2827 | paddr += PAGE_SIZE; |
2828 | start += PAGE_SIZE; | |
2829 | } | |
2830 | address += offset; | |
2831 | ||
5774f7c5 JR |
2832 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2833 | ||
afa9fdc2 | 2834 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2835 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2836 | dma_dom->need_flush = false; |
318afd41 | 2837 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2838 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2839 | |
cb76c322 JR |
2840 | out: |
2841 | return address; | |
53812c11 JR |
2842 | |
2843 | out_unmap: | |
2844 | ||
2845 | for (--i; i >= 0; --i) { | |
2846 | start -= PAGE_SIZE; | |
680525e0 | 2847 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2848 | } |
2849 | ||
2850 | dma_ops_free_addresses(dma_dom, address, pages); | |
2851 | ||
8fd524b3 | 2852 | return DMA_ERROR_CODE; |
cb76c322 JR |
2853 | } |
2854 | ||
431b2a20 JR |
2855 | /* |
2856 | * Does the reverse of the __map_single function. Must be called with | |
2857 | * the domain lock held too | |
2858 | */ | |
cd8c82e8 | 2859 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2860 | dma_addr_t dma_addr, |
2861 | size_t size, | |
2862 | int dir) | |
2863 | { | |
04e0463e | 2864 | dma_addr_t flush_addr; |
cb76c322 JR |
2865 | dma_addr_t i, start; |
2866 | unsigned int pages; | |
2867 | ||
8fd524b3 | 2868 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2869 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2870 | return; |
2871 | ||
04e0463e | 2872 | flush_addr = dma_addr; |
e3c449f5 | 2873 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2874 | dma_addr &= PAGE_MASK; |
2875 | start = dma_addr; | |
2876 | ||
2877 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2878 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2879 | start += PAGE_SIZE; |
2880 | } | |
2881 | ||
5774f7c5 JR |
2882 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2883 | ||
cb76c322 | 2884 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2885 | |
80be308d | 2886 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2887 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2888 | dma_dom->need_flush = false; |
2889 | } | |
cb76c322 JR |
2890 | } |
2891 | ||
431b2a20 JR |
2892 | /* |
2893 | * The exported map_single function for dma_ops. | |
2894 | */ | |
51491367 FT |
2895 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2896 | unsigned long offset, size_t size, | |
2897 | enum dma_data_direction dir, | |
2898 | struct dma_attrs *attrs) | |
4da70b9e JR |
2899 | { |
2900 | unsigned long flags; | |
4da70b9e | 2901 | struct protection_domain *domain; |
4da70b9e | 2902 | dma_addr_t addr; |
832a90c3 | 2903 | u64 dma_mask; |
51491367 | 2904 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2905 | |
0f2a86f2 JR |
2906 | INC_STATS_COUNTER(cnt_map_single); |
2907 | ||
94f6d190 JR |
2908 | domain = get_domain(dev); |
2909 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2910 | return (dma_addr_t)paddr; |
94f6d190 JR |
2911 | else if (IS_ERR(domain)) |
2912 | return DMA_ERROR_CODE; | |
4da70b9e | 2913 | |
f99c0f1c JR |
2914 | dma_mask = *dev->dma_mask; |
2915 | ||
4da70b9e | 2916 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2917 | |
cd8c82e8 | 2918 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2919 | dma_mask); |
8fd524b3 | 2920 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2921 | goto out; |
2922 | ||
17b124bf | 2923 | domain_flush_complete(domain); |
4da70b9e JR |
2924 | |
2925 | out: | |
2926 | spin_unlock_irqrestore(&domain->lock, flags); | |
2927 | ||
2928 | return addr; | |
2929 | } | |
2930 | ||
431b2a20 JR |
2931 | /* |
2932 | * The exported unmap_single function for dma_ops. | |
2933 | */ | |
51491367 FT |
2934 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2935 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2936 | { |
2937 | unsigned long flags; | |
4da70b9e | 2938 | struct protection_domain *domain; |
4da70b9e | 2939 | |
146a6917 JR |
2940 | INC_STATS_COUNTER(cnt_unmap_single); |
2941 | ||
94f6d190 JR |
2942 | domain = get_domain(dev); |
2943 | if (IS_ERR(domain)) | |
5b28df6f JR |
2944 | return; |
2945 | ||
4da70b9e JR |
2946 | spin_lock_irqsave(&domain->lock, flags); |
2947 | ||
cd8c82e8 | 2948 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2949 | |
17b124bf | 2950 | domain_flush_complete(domain); |
4da70b9e JR |
2951 | |
2952 | spin_unlock_irqrestore(&domain->lock, flags); | |
2953 | } | |
2954 | ||
431b2a20 JR |
2955 | /* |
2956 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2957 | * lists). | |
2958 | */ | |
65b050ad | 2959 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2960 | int nelems, enum dma_data_direction dir, |
2961 | struct dma_attrs *attrs) | |
65b050ad JR |
2962 | { |
2963 | unsigned long flags; | |
65b050ad | 2964 | struct protection_domain *domain; |
65b050ad JR |
2965 | int i; |
2966 | struct scatterlist *s; | |
2967 | phys_addr_t paddr; | |
2968 | int mapped_elems = 0; | |
832a90c3 | 2969 | u64 dma_mask; |
65b050ad | 2970 | |
d03f067a JR |
2971 | INC_STATS_COUNTER(cnt_map_sg); |
2972 | ||
94f6d190 | 2973 | domain = get_domain(dev); |
a0e191b2 | 2974 | if (IS_ERR(domain)) |
94f6d190 | 2975 | return 0; |
dbcc112e | 2976 | |
832a90c3 | 2977 | dma_mask = *dev->dma_mask; |
65b050ad | 2978 | |
65b050ad JR |
2979 | spin_lock_irqsave(&domain->lock, flags); |
2980 | ||
2981 | for_each_sg(sglist, s, nelems, i) { | |
2982 | paddr = sg_phys(s); | |
2983 | ||
cd8c82e8 | 2984 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2985 | paddr, s->length, dir, false, |
2986 | dma_mask); | |
65b050ad JR |
2987 | |
2988 | if (s->dma_address) { | |
2989 | s->dma_length = s->length; | |
2990 | mapped_elems++; | |
2991 | } else | |
2992 | goto unmap; | |
65b050ad JR |
2993 | } |
2994 | ||
17b124bf | 2995 | domain_flush_complete(domain); |
65b050ad JR |
2996 | |
2997 | out: | |
2998 | spin_unlock_irqrestore(&domain->lock, flags); | |
2999 | ||
3000 | return mapped_elems; | |
3001 | unmap: | |
3002 | for_each_sg(sglist, s, mapped_elems, i) { | |
3003 | if (s->dma_address) | |
cd8c82e8 | 3004 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
3005 | s->dma_length, dir); |
3006 | s->dma_address = s->dma_length = 0; | |
3007 | } | |
3008 | ||
3009 | mapped_elems = 0; | |
3010 | ||
3011 | goto out; | |
3012 | } | |
3013 | ||
431b2a20 JR |
3014 | /* |
3015 | * The exported map_sg function for dma_ops (handles scatter-gather | |
3016 | * lists). | |
3017 | */ | |
65b050ad | 3018 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
3019 | int nelems, enum dma_data_direction dir, |
3020 | struct dma_attrs *attrs) | |
65b050ad JR |
3021 | { |
3022 | unsigned long flags; | |
65b050ad JR |
3023 | struct protection_domain *domain; |
3024 | struct scatterlist *s; | |
65b050ad JR |
3025 | int i; |
3026 | ||
55877a6b JR |
3027 | INC_STATS_COUNTER(cnt_unmap_sg); |
3028 | ||
94f6d190 JR |
3029 | domain = get_domain(dev); |
3030 | if (IS_ERR(domain)) | |
5b28df6f JR |
3031 | return; |
3032 | ||
65b050ad JR |
3033 | spin_lock_irqsave(&domain->lock, flags); |
3034 | ||
3035 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 3036 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 3037 | s->dma_length, dir); |
65b050ad JR |
3038 | s->dma_address = s->dma_length = 0; |
3039 | } | |
3040 | ||
17b124bf | 3041 | domain_flush_complete(domain); |
65b050ad JR |
3042 | |
3043 | spin_unlock_irqrestore(&domain->lock, flags); | |
3044 | } | |
3045 | ||
431b2a20 JR |
3046 | /* |
3047 | * The exported alloc_coherent function for dma_ops. | |
3048 | */ | |
5d8b53cf | 3049 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
3050 | dma_addr_t *dma_addr, gfp_t flag, |
3051 | struct dma_attrs *attrs) | |
5d8b53cf JR |
3052 | { |
3053 | unsigned long flags; | |
3054 | void *virt_addr; | |
5d8b53cf | 3055 | struct protection_domain *domain; |
5d8b53cf | 3056 | phys_addr_t paddr; |
832a90c3 | 3057 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 3058 | |
c8f0fb36 JR |
3059 | INC_STATS_COUNTER(cnt_alloc_coherent); |
3060 | ||
94f6d190 JR |
3061 | domain = get_domain(dev); |
3062 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
3063 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
3064 | *dma_addr = __pa(virt_addr); | |
3065 | return virt_addr; | |
94f6d190 JR |
3066 | } else if (IS_ERR(domain)) |
3067 | return NULL; | |
5d8b53cf | 3068 | |
f99c0f1c JR |
3069 | dma_mask = dev->coherent_dma_mask; |
3070 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
3071 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
3072 | |
3073 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
3074 | if (!virt_addr) | |
b25ae679 | 3075 | return NULL; |
5d8b53cf | 3076 | |
5d8b53cf JR |
3077 | paddr = virt_to_phys(virt_addr); |
3078 | ||
832a90c3 JR |
3079 | if (!dma_mask) |
3080 | dma_mask = *dev->dma_mask; | |
3081 | ||
5d8b53cf JR |
3082 | spin_lock_irqsave(&domain->lock, flags); |
3083 | ||
cd8c82e8 | 3084 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 3085 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 3086 | |
8fd524b3 | 3087 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 3088 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 3089 | goto out_free; |
367d04c4 | 3090 | } |
5d8b53cf | 3091 | |
17b124bf | 3092 | domain_flush_complete(domain); |
5d8b53cf | 3093 | |
5d8b53cf JR |
3094 | spin_unlock_irqrestore(&domain->lock, flags); |
3095 | ||
3096 | return virt_addr; | |
5b28df6f JR |
3097 | |
3098 | out_free: | |
3099 | ||
3100 | free_pages((unsigned long)virt_addr, get_order(size)); | |
3101 | ||
3102 | return NULL; | |
5d8b53cf JR |
3103 | } |
3104 | ||
431b2a20 JR |
3105 | /* |
3106 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 3107 | */ |
5d8b53cf | 3108 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
3109 | void *virt_addr, dma_addr_t dma_addr, |
3110 | struct dma_attrs *attrs) | |
5d8b53cf JR |
3111 | { |
3112 | unsigned long flags; | |
5d8b53cf | 3113 | struct protection_domain *domain; |
5d8b53cf | 3114 | |
5d31ee7e JR |
3115 | INC_STATS_COUNTER(cnt_free_coherent); |
3116 | ||
94f6d190 JR |
3117 | domain = get_domain(dev); |
3118 | if (IS_ERR(domain)) | |
5b28df6f JR |
3119 | goto free_mem; |
3120 | ||
5d8b53cf JR |
3121 | spin_lock_irqsave(&domain->lock, flags); |
3122 | ||
cd8c82e8 | 3123 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 3124 | |
17b124bf | 3125 | domain_flush_complete(domain); |
5d8b53cf JR |
3126 | |
3127 | spin_unlock_irqrestore(&domain->lock, flags); | |
3128 | ||
3129 | free_mem: | |
3130 | free_pages((unsigned long)virt_addr, get_order(size)); | |
3131 | } | |
3132 | ||
b39ba6ad JR |
3133 | /* |
3134 | * This function is called by the DMA layer to find out if we can handle a | |
3135 | * particular device. It is part of the dma_ops. | |
3136 | */ | |
3137 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
3138 | { | |
420aef8a | 3139 | return check_device(dev); |
b39ba6ad JR |
3140 | } |
3141 | ||
c432f3df | 3142 | /* |
431b2a20 JR |
3143 | * The function for pre-allocating protection domains. |
3144 | * | |
c432f3df JR |
3145 | * If the driver core informs the DMA layer if a driver grabs a device |
3146 | * we don't need to preallocate the protection domains anymore. | |
3147 | * For now we have to. | |
3148 | */ | |
943bc7e1 | 3149 | static void __init prealloc_protection_domains(void) |
c432f3df | 3150 | { |
5abcdba4 | 3151 | struct iommu_dev_data *dev_data; |
c432f3df | 3152 | struct dma_ops_domain *dma_dom; |
5abcdba4 | 3153 | struct pci_dev *dev = NULL; |
98fc5a69 | 3154 | u16 devid; |
c432f3df | 3155 | |
d18c69d3 | 3156 | for_each_pci_dev(dev) { |
98fc5a69 JR |
3157 | |
3158 | /* Do we handle this device? */ | |
3159 | if (!check_device(&dev->dev)) | |
c432f3df | 3160 | continue; |
98fc5a69 | 3161 | |
5abcdba4 JR |
3162 | dev_data = get_dev_data(&dev->dev); |
3163 | if (!amd_iommu_force_isolation && dev_data->iommu_v2) { | |
3164 | /* Make sure passthrough domain is allocated */ | |
3165 | alloc_passthrough_domain(); | |
3166 | dev_data->passthrough = true; | |
3167 | attach_device(&dev->dev, pt_domain); | |
df805abb | 3168 | pr_info("AMD-Vi: Using passthrough domain for device %s\n", |
5abcdba4 JR |
3169 | dev_name(&dev->dev)); |
3170 | } | |
3171 | ||
98fc5a69 | 3172 | /* Is there already any domain for it? */ |
15898bbc | 3173 | if (domain_for_device(&dev->dev)) |
c432f3df | 3174 | continue; |
98fc5a69 JR |
3175 | |
3176 | devid = get_device_id(&dev->dev); | |
3177 | ||
87a64d52 | 3178 | dma_dom = dma_ops_domain_alloc(); |
c432f3df JR |
3179 | if (!dma_dom) |
3180 | continue; | |
3181 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
3182 | dma_dom->target_dev = devid; |
3183 | ||
15898bbc | 3184 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 3185 | |
bd60b735 | 3186 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
3187 | } |
3188 | } | |
3189 | ||
160c1d8e | 3190 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
3191 | .alloc = alloc_coherent, |
3192 | .free = free_coherent, | |
51491367 FT |
3193 | .map_page = map_page, |
3194 | .unmap_page = unmap_page, | |
6631ee9d JR |
3195 | .map_sg = map_sg, |
3196 | .unmap_sg = unmap_sg, | |
b39ba6ad | 3197 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
3198 | }; |
3199 | ||
27c2127a JR |
3200 | static unsigned device_dma_ops_init(void) |
3201 | { | |
5abcdba4 | 3202 | struct iommu_dev_data *dev_data; |
27c2127a JR |
3203 | struct pci_dev *pdev = NULL; |
3204 | unsigned unhandled = 0; | |
3205 | ||
3206 | for_each_pci_dev(pdev) { | |
3207 | if (!check_device(&pdev->dev)) { | |
af1be049 JR |
3208 | |
3209 | iommu_ignore_device(&pdev->dev); | |
3210 | ||
27c2127a JR |
3211 | unhandled += 1; |
3212 | continue; | |
3213 | } | |
3214 | ||
5abcdba4 JR |
3215 | dev_data = get_dev_data(&pdev->dev); |
3216 | ||
3217 | if (!dev_data->passthrough) | |
3218 | pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops; | |
3219 | else | |
3220 | pdev->dev.archdata.dma_ops = &nommu_dma_ops; | |
27c2127a JR |
3221 | } |
3222 | ||
3223 | return unhandled; | |
3224 | } | |
3225 | ||
431b2a20 JR |
3226 | /* |
3227 | * The function which clues the AMD IOMMU driver into dma_ops. | |
3228 | */ | |
f5325094 JR |
3229 | |
3230 | void __init amd_iommu_init_api(void) | |
3231 | { | |
2cc21c42 | 3232 | bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
3233 | } |
3234 | ||
6631ee9d JR |
3235 | int __init amd_iommu_init_dma_ops(void) |
3236 | { | |
3237 | struct amd_iommu *iommu; | |
27c2127a | 3238 | int ret, unhandled; |
6631ee9d | 3239 | |
431b2a20 JR |
3240 | /* |
3241 | * first allocate a default protection domain for every IOMMU we | |
3242 | * found in the system. Devices not assigned to any other | |
3243 | * protection domain will be assigned to the default one. | |
3244 | */ | |
3bd22172 | 3245 | for_each_iommu(iommu) { |
87a64d52 | 3246 | iommu->default_dom = dma_ops_domain_alloc(); |
6631ee9d JR |
3247 | if (iommu->default_dom == NULL) |
3248 | return -ENOMEM; | |
e2dc14a2 | 3249 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
3250 | ret = iommu_init_unity_mappings(iommu); |
3251 | if (ret) | |
3252 | goto free_domains; | |
3253 | } | |
3254 | ||
431b2a20 | 3255 | /* |
8793abeb | 3256 | * Pre-allocate the protection domains for each device. |
431b2a20 | 3257 | */ |
8793abeb | 3258 | prealloc_protection_domains(); |
6631ee9d JR |
3259 | |
3260 | iommu_detected = 1; | |
75f1cdf1 | 3261 | swiotlb = 0; |
6631ee9d | 3262 | |
431b2a20 | 3263 | /* Make the driver finally visible to the drivers */ |
27c2127a JR |
3264 | unhandled = device_dma_ops_init(); |
3265 | if (unhandled && max_pfn > MAX_DMA32_PFN) { | |
3266 | /* There are unhandled devices - initialize swiotlb for them */ | |
3267 | swiotlb = 1; | |
3268 | } | |
6631ee9d | 3269 | |
7f26508b JR |
3270 | amd_iommu_stats_init(); |
3271 | ||
62410eeb JR |
3272 | if (amd_iommu_unmap_flush) |
3273 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
3274 | else | |
3275 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
3276 | ||
6631ee9d JR |
3277 | return 0; |
3278 | ||
3279 | free_domains: | |
3280 | ||
3bd22172 | 3281 | for_each_iommu(iommu) { |
91457df7 | 3282 | dma_ops_domain_free(iommu->default_dom); |
6631ee9d JR |
3283 | } |
3284 | ||
3285 | return ret; | |
3286 | } | |
6d98cd80 JR |
3287 | |
3288 | /***************************************************************************** | |
3289 | * | |
3290 | * The following functions belong to the exported interface of AMD IOMMU | |
3291 | * | |
3292 | * This interface allows access to lower level functions of the IOMMU | |
3293 | * like protection domain handling and assignement of devices to domains | |
3294 | * which is not possible with the dma_ops interface. | |
3295 | * | |
3296 | *****************************************************************************/ | |
3297 | ||
6d98cd80 JR |
3298 | static void cleanup_domain(struct protection_domain *domain) |
3299 | { | |
492667da | 3300 | struct iommu_dev_data *dev_data, *next; |
6d98cd80 | 3301 | unsigned long flags; |
6d98cd80 JR |
3302 | |
3303 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3304 | ||
492667da | 3305 | list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) { |
ec9e79ef | 3306 | __detach_device(dev_data); |
492667da JR |
3307 | atomic_set(&dev_data->bind, 0); |
3308 | } | |
6d98cd80 JR |
3309 | |
3310 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3311 | } | |
3312 | ||
2650815f JR |
3313 | static void protection_domain_free(struct protection_domain *domain) |
3314 | { | |
3315 | if (!domain) | |
3316 | return; | |
3317 | ||
aeb26f55 JR |
3318 | del_domain_from_list(domain); |
3319 | ||
2650815f JR |
3320 | if (domain->id) |
3321 | domain_id_free(domain->id); | |
3322 | ||
3323 | kfree(domain); | |
3324 | } | |
3325 | ||
3326 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
3327 | { |
3328 | struct protection_domain *domain; | |
3329 | ||
3330 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
3331 | if (!domain) | |
2650815f | 3332 | return NULL; |
c156e347 JR |
3333 | |
3334 | spin_lock_init(&domain->lock); | |
5d214fe6 | 3335 | mutex_init(&domain->api_lock); |
c156e347 JR |
3336 | domain->id = domain_id_alloc(); |
3337 | if (!domain->id) | |
2650815f | 3338 | goto out_err; |
7c392cbe | 3339 | INIT_LIST_HEAD(&domain->dev_list); |
2650815f | 3340 | |
aeb26f55 JR |
3341 | add_domain_to_list(domain); |
3342 | ||
2650815f JR |
3343 | return domain; |
3344 | ||
3345 | out_err: | |
3346 | kfree(domain); | |
3347 | ||
3348 | return NULL; | |
3349 | } | |
3350 | ||
5abcdba4 JR |
3351 | static int __init alloc_passthrough_domain(void) |
3352 | { | |
3353 | if (pt_domain != NULL) | |
3354 | return 0; | |
3355 | ||
3356 | /* allocate passthrough domain */ | |
3357 | pt_domain = protection_domain_alloc(); | |
3358 | if (!pt_domain) | |
3359 | return -ENOMEM; | |
3360 | ||
3361 | pt_domain->mode = PAGE_MODE_NONE; | |
3362 | ||
3363 | return 0; | |
3364 | } | |
2650815f JR |
3365 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
3366 | { | |
3367 | struct protection_domain *domain; | |
3368 | ||
3369 | domain = protection_domain_alloc(); | |
3370 | if (!domain) | |
c156e347 | 3371 | goto out_free; |
2650815f JR |
3372 | |
3373 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
3374 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
3375 | if (!domain->pt_root) | |
3376 | goto out_free; | |
3377 | ||
f3572db8 JR |
3378 | domain->iommu_domain = dom; |
3379 | ||
c156e347 JR |
3380 | dom->priv = domain; |
3381 | ||
0ff64f80 JR |
3382 | dom->geometry.aperture_start = 0; |
3383 | dom->geometry.aperture_end = ~0ULL; | |
3384 | dom->geometry.force_aperture = true; | |
3385 | ||
c156e347 JR |
3386 | return 0; |
3387 | ||
3388 | out_free: | |
2650815f | 3389 | protection_domain_free(domain); |
c156e347 JR |
3390 | |
3391 | return -ENOMEM; | |
3392 | } | |
3393 | ||
98383fc3 JR |
3394 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
3395 | { | |
3396 | struct protection_domain *domain = dom->priv; | |
3397 | ||
3398 | if (!domain) | |
3399 | return; | |
3400 | ||
3401 | if (domain->dev_cnt > 0) | |
3402 | cleanup_domain(domain); | |
3403 | ||
3404 | BUG_ON(domain->dev_cnt != 0); | |
3405 | ||
132bd68f JR |
3406 | if (domain->mode != PAGE_MODE_NONE) |
3407 | free_pagetable(domain); | |
98383fc3 | 3408 | |
52815b75 JR |
3409 | if (domain->flags & PD_IOMMUV2_MASK) |
3410 | free_gcr3_table(domain); | |
3411 | ||
8b408fe4 | 3412 | protection_domain_free(domain); |
98383fc3 JR |
3413 | |
3414 | dom->priv = NULL; | |
3415 | } | |
3416 | ||
684f2888 JR |
3417 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3418 | struct device *dev) | |
3419 | { | |
657cbb6b | 3420 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3421 | struct amd_iommu *iommu; |
684f2888 JR |
3422 | u16 devid; |
3423 | ||
98fc5a69 | 3424 | if (!check_device(dev)) |
684f2888 JR |
3425 | return; |
3426 | ||
98fc5a69 | 3427 | devid = get_device_id(dev); |
684f2888 | 3428 | |
657cbb6b | 3429 | if (dev_data->domain != NULL) |
15898bbc | 3430 | detach_device(dev); |
684f2888 JR |
3431 | |
3432 | iommu = amd_iommu_rlookup_table[devid]; | |
3433 | if (!iommu) | |
3434 | return; | |
3435 | ||
684f2888 JR |
3436 | iommu_completion_wait(iommu); |
3437 | } | |
3438 | ||
01106066 JR |
3439 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3440 | struct device *dev) | |
3441 | { | |
3442 | struct protection_domain *domain = dom->priv; | |
657cbb6b | 3443 | struct iommu_dev_data *dev_data; |
01106066 | 3444 | struct amd_iommu *iommu; |
15898bbc | 3445 | int ret; |
01106066 | 3446 | |
98fc5a69 | 3447 | if (!check_device(dev)) |
01106066 JR |
3448 | return -EINVAL; |
3449 | ||
657cbb6b JR |
3450 | dev_data = dev->archdata.iommu; |
3451 | ||
f62dda66 | 3452 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3453 | if (!iommu) |
3454 | return -EINVAL; | |
3455 | ||
657cbb6b | 3456 | if (dev_data->domain) |
15898bbc | 3457 | detach_device(dev); |
01106066 | 3458 | |
15898bbc | 3459 | ret = attach_device(dev, domain); |
01106066 JR |
3460 | |
3461 | iommu_completion_wait(iommu); | |
3462 | ||
15898bbc | 3463 | return ret; |
01106066 JR |
3464 | } |
3465 | ||
468e2366 | 3466 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3467 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 JR |
3468 | { |
3469 | struct protection_domain *domain = dom->priv; | |
c6229ca6 JR |
3470 | int prot = 0; |
3471 | int ret; | |
3472 | ||
132bd68f JR |
3473 | if (domain->mode == PAGE_MODE_NONE) |
3474 | return -EINVAL; | |
3475 | ||
c6229ca6 JR |
3476 | if (iommu_prot & IOMMU_READ) |
3477 | prot |= IOMMU_PROT_IR; | |
3478 | if (iommu_prot & IOMMU_WRITE) | |
3479 | prot |= IOMMU_PROT_IW; | |
3480 | ||
5d214fe6 | 3481 | mutex_lock(&domain->api_lock); |
795e74f7 | 3482 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3483 | mutex_unlock(&domain->api_lock); |
3484 | ||
795e74f7 | 3485 | return ret; |
c6229ca6 JR |
3486 | } |
3487 | ||
5009065d OBC |
3488 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3489 | size_t page_size) | |
eb74ff6c | 3490 | { |
eb74ff6c | 3491 | struct protection_domain *domain = dom->priv; |
5009065d | 3492 | size_t unmap_size; |
eb74ff6c | 3493 | |
132bd68f JR |
3494 | if (domain->mode == PAGE_MODE_NONE) |
3495 | return -EINVAL; | |
3496 | ||
5d214fe6 | 3497 | mutex_lock(&domain->api_lock); |
468e2366 | 3498 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3499 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3500 | |
17b124bf | 3501 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3502 | |
5009065d | 3503 | return unmap_size; |
eb74ff6c JR |
3504 | } |
3505 | ||
645c4c8d | 3506 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3507 | dma_addr_t iova) |
645c4c8d JR |
3508 | { |
3509 | struct protection_domain *domain = dom->priv; | |
f03152bb | 3510 | unsigned long offset_mask; |
645c4c8d | 3511 | phys_addr_t paddr; |
f03152bb | 3512 | u64 *pte, __pte; |
645c4c8d | 3513 | |
132bd68f JR |
3514 | if (domain->mode == PAGE_MODE_NONE) |
3515 | return iova; | |
3516 | ||
24cd7723 | 3517 | pte = fetch_pte(domain, iova); |
645c4c8d | 3518 | |
a6d41a40 | 3519 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3520 | return 0; |
3521 | ||
f03152bb JR |
3522 | if (PM_PTE_LEVEL(*pte) == 0) |
3523 | offset_mask = PAGE_SIZE - 1; | |
3524 | else | |
3525 | offset_mask = PTE_PAGE_SIZE(*pte) - 1; | |
3526 | ||
3527 | __pte = *pte & PM_ADDR_MASK; | |
3528 | paddr = (__pte & ~offset_mask) | (iova & offset_mask); | |
645c4c8d JR |
3529 | |
3530 | return paddr; | |
3531 | } | |
3532 | ||
dbb9fd86 SY |
3533 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
3534 | unsigned long cap) | |
3535 | { | |
80a506b8 JR |
3536 | switch (cap) { |
3537 | case IOMMU_CAP_CACHE_COHERENCY: | |
3538 | return 1; | |
bdddadcb JR |
3539 | case IOMMU_CAP_INTR_REMAP: |
3540 | return irq_remapping_enabled; | |
80a506b8 JR |
3541 | } |
3542 | ||
dbb9fd86 SY |
3543 | return 0; |
3544 | } | |
3545 | ||
26961efe JR |
3546 | static struct iommu_ops amd_iommu_ops = { |
3547 | .domain_init = amd_iommu_domain_init, | |
3548 | .domain_destroy = amd_iommu_domain_destroy, | |
3549 | .attach_dev = amd_iommu_attach_device, | |
3550 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3551 | .map = amd_iommu_map, |
3552 | .unmap = amd_iommu_unmap, | |
26961efe | 3553 | .iova_to_phys = amd_iommu_iova_to_phys, |
dbb9fd86 | 3554 | .domain_has_cap = amd_iommu_domain_has_cap, |
aa3de9c0 | 3555 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3556 | }; |
3557 | ||
0feae533 JR |
3558 | /***************************************************************************** |
3559 | * | |
3560 | * The next functions do a basic initialization of IOMMU for pass through | |
3561 | * mode | |
3562 | * | |
3563 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3564 | * DMA-API translation. | |
3565 | * | |
3566 | *****************************************************************************/ | |
3567 | ||
3568 | int __init amd_iommu_init_passthrough(void) | |
3569 | { | |
5abcdba4 | 3570 | struct iommu_dev_data *dev_data; |
0feae533 | 3571 | struct pci_dev *dev = NULL; |
5abcdba4 | 3572 | int ret; |
0feae533 | 3573 | |
5abcdba4 JR |
3574 | ret = alloc_passthrough_domain(); |
3575 | if (ret) | |
3576 | return ret; | |
0feae533 | 3577 | |
6c54aabd | 3578 | for_each_pci_dev(dev) { |
98fc5a69 | 3579 | if (!check_device(&dev->dev)) |
0feae533 JR |
3580 | continue; |
3581 | ||
5abcdba4 JR |
3582 | dev_data = get_dev_data(&dev->dev); |
3583 | dev_data->passthrough = true; | |
3584 | ||
15898bbc | 3585 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
3586 | } |
3587 | ||
2655d7a2 JR |
3588 | amd_iommu_stats_init(); |
3589 | ||
0feae533 JR |
3590 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); |
3591 | ||
3592 | return 0; | |
3593 | } | |
72e1dcc4 JR |
3594 | |
3595 | /* IOMMUv2 specific functions */ | |
3596 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3597 | { | |
3598 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3599 | } | |
3600 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3601 | ||
3602 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3603 | { | |
3604 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3605 | } | |
3606 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3607 | |
3608 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3609 | { | |
3610 | struct protection_domain *domain = dom->priv; | |
3611 | unsigned long flags; | |
3612 | ||
3613 | spin_lock_irqsave(&domain->lock, flags); | |
3614 | ||
3615 | /* Update data structure */ | |
3616 | domain->mode = PAGE_MODE_NONE; | |
3617 | domain->updated = true; | |
3618 | ||
3619 | /* Make changes visible to IOMMUs */ | |
3620 | update_domain(domain); | |
3621 | ||
3622 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3623 | free_pagetable(domain); | |
3624 | ||
3625 | spin_unlock_irqrestore(&domain->lock, flags); | |
3626 | } | |
3627 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3628 | |
3629 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3630 | { | |
3631 | struct protection_domain *domain = dom->priv; | |
3632 | unsigned long flags; | |
3633 | int levels, ret; | |
3634 | ||
3635 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3636 | return -EINVAL; | |
3637 | ||
3638 | /* Number of GCR3 table levels required */ | |
3639 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3640 | levels += 1; | |
3641 | ||
3642 | if (levels > amd_iommu_max_glx_val) | |
3643 | return -EINVAL; | |
3644 | ||
3645 | spin_lock_irqsave(&domain->lock, flags); | |
3646 | ||
3647 | /* | |
3648 | * Save us all sanity checks whether devices already in the | |
3649 | * domain support IOMMUv2. Just force that the domain has no | |
3650 | * devices attached when it is switched into IOMMUv2 mode. | |
3651 | */ | |
3652 | ret = -EBUSY; | |
3653 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3654 | goto out; | |
3655 | ||
3656 | ret = -ENOMEM; | |
3657 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3658 | if (domain->gcr3_tbl == NULL) | |
3659 | goto out; | |
3660 | ||
3661 | domain->glx = levels; | |
3662 | domain->flags |= PD_IOMMUV2_MASK; | |
3663 | domain->updated = true; | |
3664 | ||
3665 | update_domain(domain); | |
3666 | ||
3667 | ret = 0; | |
3668 | ||
3669 | out: | |
3670 | spin_unlock_irqrestore(&domain->lock, flags); | |
3671 | ||
3672 | return ret; | |
3673 | } | |
3674 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3675 | |
3676 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3677 | u64 address, bool size) | |
3678 | { | |
3679 | struct iommu_dev_data *dev_data; | |
3680 | struct iommu_cmd cmd; | |
3681 | int i, ret; | |
3682 | ||
3683 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3684 | return -EINVAL; | |
3685 | ||
3686 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3687 | ||
3688 | /* | |
3689 | * IOMMU TLB needs to be flushed before Device TLB to | |
3690 | * prevent device TLB refill from IOMMU TLB | |
3691 | */ | |
3692 | for (i = 0; i < amd_iommus_present; ++i) { | |
3693 | if (domain->dev_iommu[i] == 0) | |
3694 | continue; | |
3695 | ||
3696 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3697 | if (ret != 0) | |
3698 | goto out; | |
3699 | } | |
3700 | ||
3701 | /* Wait until IOMMU TLB flushes are complete */ | |
3702 | domain_flush_complete(domain); | |
3703 | ||
3704 | /* Now flush device TLBs */ | |
3705 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3706 | struct amd_iommu *iommu; | |
3707 | int qdep; | |
3708 | ||
3709 | BUG_ON(!dev_data->ats.enabled); | |
3710 | ||
3711 | qdep = dev_data->ats.qdep; | |
3712 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3713 | ||
3714 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3715 | qdep, address, size); | |
3716 | ||
3717 | ret = iommu_queue_command(iommu, &cmd); | |
3718 | if (ret != 0) | |
3719 | goto out; | |
3720 | } | |
3721 | ||
3722 | /* Wait until all device TLBs are flushed */ | |
3723 | domain_flush_complete(domain); | |
3724 | ||
3725 | ret = 0; | |
3726 | ||
3727 | out: | |
3728 | ||
3729 | return ret; | |
3730 | } | |
3731 | ||
3732 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3733 | u64 address) | |
3734 | { | |
399be2f5 JR |
3735 | INC_STATS_COUNTER(invalidate_iotlb); |
3736 | ||
22e266c7 JR |
3737 | return __flush_pasid(domain, pasid, address, false); |
3738 | } | |
3739 | ||
3740 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3741 | u64 address) | |
3742 | { | |
3743 | struct protection_domain *domain = dom->priv; | |
3744 | unsigned long flags; | |
3745 | int ret; | |
3746 | ||
3747 | spin_lock_irqsave(&domain->lock, flags); | |
3748 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3749 | spin_unlock_irqrestore(&domain->lock, flags); | |
3750 | ||
3751 | return ret; | |
3752 | } | |
3753 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3754 | ||
3755 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3756 | { | |
399be2f5 JR |
3757 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3758 | ||
22e266c7 JR |
3759 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3760 | true); | |
3761 | } | |
3762 | ||
3763 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3764 | { | |
3765 | struct protection_domain *domain = dom->priv; | |
3766 | unsigned long flags; | |
3767 | int ret; | |
3768 | ||
3769 | spin_lock_irqsave(&domain->lock, flags); | |
3770 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3771 | spin_unlock_irqrestore(&domain->lock, flags); | |
3772 | ||
3773 | return ret; | |
3774 | } | |
3775 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3776 | ||
b16137b1 JR |
3777 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3778 | { | |
3779 | int index; | |
3780 | u64 *pte; | |
3781 | ||
3782 | while (true) { | |
3783 | ||
3784 | index = (pasid >> (9 * level)) & 0x1ff; | |
3785 | pte = &root[index]; | |
3786 | ||
3787 | if (level == 0) | |
3788 | break; | |
3789 | ||
3790 | if (!(*pte & GCR3_VALID)) { | |
3791 | if (!alloc) | |
3792 | return NULL; | |
3793 | ||
3794 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3795 | if (root == NULL) | |
3796 | return NULL; | |
3797 | ||
3798 | *pte = __pa(root) | GCR3_VALID; | |
3799 | } | |
3800 | ||
3801 | root = __va(*pte & PAGE_MASK); | |
3802 | ||
3803 | level -= 1; | |
3804 | } | |
3805 | ||
3806 | return pte; | |
3807 | } | |
3808 | ||
3809 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3810 | unsigned long cr3) | |
3811 | { | |
3812 | u64 *pte; | |
3813 | ||
3814 | if (domain->mode != PAGE_MODE_NONE) | |
3815 | return -EINVAL; | |
3816 | ||
3817 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3818 | if (pte == NULL) | |
3819 | return -ENOMEM; | |
3820 | ||
3821 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3822 | ||
3823 | return __amd_iommu_flush_tlb(domain, pasid); | |
3824 | } | |
3825 | ||
3826 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3827 | { | |
3828 | u64 *pte; | |
3829 | ||
3830 | if (domain->mode != PAGE_MODE_NONE) | |
3831 | return -EINVAL; | |
3832 | ||
3833 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3834 | if (pte == NULL) | |
3835 | return 0; | |
3836 | ||
3837 | *pte = 0; | |
3838 | ||
3839 | return __amd_iommu_flush_tlb(domain, pasid); | |
3840 | } | |
3841 | ||
3842 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3843 | unsigned long cr3) | |
3844 | { | |
3845 | struct protection_domain *domain = dom->priv; | |
3846 | unsigned long flags; | |
3847 | int ret; | |
3848 | ||
3849 | spin_lock_irqsave(&domain->lock, flags); | |
3850 | ret = __set_gcr3(domain, pasid, cr3); | |
3851 | spin_unlock_irqrestore(&domain->lock, flags); | |
3852 | ||
3853 | return ret; | |
3854 | } | |
3855 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3856 | ||
3857 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3858 | { | |
3859 | struct protection_domain *domain = dom->priv; | |
3860 | unsigned long flags; | |
3861 | int ret; | |
3862 | ||
3863 | spin_lock_irqsave(&domain->lock, flags); | |
3864 | ret = __clear_gcr3(domain, pasid); | |
3865 | spin_unlock_irqrestore(&domain->lock, flags); | |
3866 | ||
3867 | return ret; | |
3868 | } | |
3869 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3870 | |
3871 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3872 | int status, int tag) | |
3873 | { | |
3874 | struct iommu_dev_data *dev_data; | |
3875 | struct amd_iommu *iommu; | |
3876 | struct iommu_cmd cmd; | |
3877 | ||
399be2f5 JR |
3878 | INC_STATS_COUNTER(complete_ppr); |
3879 | ||
c99afa25 JR |
3880 | dev_data = get_dev_data(&pdev->dev); |
3881 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3882 | ||
3883 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3884 | tag, dev_data->pri_tlp); | |
3885 | ||
3886 | return iommu_queue_command(iommu, &cmd); | |
3887 | } | |
3888 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3889 | |
3890 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3891 | { | |
3892 | struct protection_domain *domain; | |
3893 | ||
3894 | domain = get_domain(&pdev->dev); | |
3895 | if (IS_ERR(domain)) | |
3896 | return NULL; | |
3897 | ||
3898 | /* Only return IOMMUv2 domains */ | |
3899 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3900 | return NULL; | |
3901 | ||
3902 | return domain->iommu_domain; | |
3903 | } | |
3904 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3905 | |
3906 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3907 | { | |
3908 | struct iommu_dev_data *dev_data; | |
3909 | ||
3910 | if (!amd_iommu_v2_supported()) | |
3911 | return; | |
3912 | ||
3913 | dev_data = get_dev_data(&pdev->dev); | |
3914 | dev_data->errata |= (1 << erratum); | |
3915 | } | |
3916 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3917 | |
3918 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3919 | struct amd_iommu_device_info *info) | |
3920 | { | |
3921 | int max_pasids; | |
3922 | int pos; | |
3923 | ||
3924 | if (pdev == NULL || info == NULL) | |
3925 | return -EINVAL; | |
3926 | ||
3927 | if (!amd_iommu_v2_supported()) | |
3928 | return -EINVAL; | |
3929 | ||
3930 | memset(info, 0, sizeof(*info)); | |
3931 | ||
3932 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3933 | if (pos) | |
3934 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3935 | ||
3936 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3937 | if (pos) | |
3938 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3939 | ||
3940 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3941 | if (pos) { | |
3942 | int features; | |
3943 | ||
3944 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3945 | max_pasids = min(max_pasids, (1 << 20)); | |
3946 | ||
3947 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3948 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3949 | ||
3950 | features = pci_pasid_features(pdev); | |
3951 | if (features & PCI_PASID_CAP_EXEC) | |
3952 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3953 | if (features & PCI_PASID_CAP_PRIV) | |
3954 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3955 | } | |
3956 | ||
3957 | return 0; | |
3958 | } | |
3959 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3960 | |
3961 | #ifdef CONFIG_IRQ_REMAP | |
3962 | ||
3963 | /***************************************************************************** | |
3964 | * | |
3965 | * Interrupt Remapping Implementation | |
3966 | * | |
3967 | *****************************************************************************/ | |
3968 | ||
3969 | union irte { | |
3970 | u32 val; | |
3971 | struct { | |
3972 | u32 valid : 1, | |
3973 | no_fault : 1, | |
3974 | int_type : 3, | |
3975 | rq_eoi : 1, | |
3976 | dm : 1, | |
3977 | rsvd_1 : 1, | |
3978 | destination : 8, | |
3979 | vector : 8, | |
3980 | rsvd_2 : 8; | |
3981 | } fields; | |
3982 | }; | |
3983 | ||
3984 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) | |
3985 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3986 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3987 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3988 | ||
3989 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3990 | { | |
3991 | u64 dte; | |
3992 | ||
3993 | dte = amd_iommu_dev_table[devid].data[2]; | |
3994 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3995 | dte |= virt_to_phys(table->table); | |
3996 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3997 | dte |= DTE_IRQ_TABLE_LEN; | |
3998 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3999 | ||
4000 | amd_iommu_dev_table[devid].data[2] = dte; | |
4001 | } | |
4002 | ||
4003 | #define IRTE_ALLOCATED (~1U) | |
4004 | ||
4005 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
4006 | { | |
4007 | struct irq_remap_table *table = NULL; | |
4008 | struct amd_iommu *iommu; | |
4009 | unsigned long flags; | |
4010 | u16 alias; | |
4011 | ||
4012 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
4013 | ||
4014 | iommu = amd_iommu_rlookup_table[devid]; | |
4015 | if (!iommu) | |
4016 | goto out_unlock; | |
4017 | ||
4018 | table = irq_lookup_table[devid]; | |
4019 | if (table) | |
4020 | goto out; | |
4021 | ||
4022 | alias = amd_iommu_alias_table[devid]; | |
4023 | table = irq_lookup_table[alias]; | |
4024 | if (table) { | |
4025 | irq_lookup_table[devid] = table; | |
4026 | set_dte_irq_entry(devid, table); | |
4027 | iommu_flush_dte(iommu, devid); | |
4028 | goto out; | |
4029 | } | |
4030 | ||
4031 | /* Nothing there yet, allocate new irq remapping table */ | |
4032 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
4033 | if (!table) | |
4034 | goto out; | |
4035 | ||
197887f0 JR |
4036 | /* Initialize table spin-lock */ |
4037 | spin_lock_init(&table->lock); | |
4038 | ||
2b324506 JR |
4039 | if (ioapic) |
4040 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
4041 | table->min_index = 32; | |
4042 | ||
4043 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
4044 | if (!table->table) { | |
4045 | kfree(table); | |
821f0f68 | 4046 | table = NULL; |
2b324506 JR |
4047 | goto out; |
4048 | } | |
4049 | ||
4050 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
4051 | ||
4052 | if (ioapic) { | |
4053 | int i; | |
4054 | ||
4055 | for (i = 0; i < 32; ++i) | |
4056 | table->table[i] = IRTE_ALLOCATED; | |
4057 | } | |
4058 | ||
4059 | irq_lookup_table[devid] = table; | |
4060 | set_dte_irq_entry(devid, table); | |
4061 | iommu_flush_dte(iommu, devid); | |
4062 | if (devid != alias) { | |
4063 | irq_lookup_table[alias] = table; | |
e028a9e6 | 4064 | set_dte_irq_entry(alias, table); |
2b324506 JR |
4065 | iommu_flush_dte(iommu, alias); |
4066 | } | |
4067 | ||
4068 | out: | |
4069 | iommu_completion_wait(iommu); | |
4070 | ||
4071 | out_unlock: | |
4072 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
4073 | ||
4074 | return table; | |
4075 | } | |
4076 | ||
4077 | static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count) | |
4078 | { | |
4079 | struct irq_remap_table *table; | |
4080 | unsigned long flags; | |
4081 | int index, c; | |
4082 | ||
4083 | table = get_irq_table(devid, false); | |
4084 | if (!table) | |
4085 | return -ENODEV; | |
4086 | ||
4087 | spin_lock_irqsave(&table->lock, flags); | |
4088 | ||
4089 | /* Scan table for free entries */ | |
4090 | for (c = 0, index = table->min_index; | |
4091 | index < MAX_IRQS_PER_TABLE; | |
4092 | ++index) { | |
4093 | if (table->table[index] == 0) | |
4094 | c += 1; | |
4095 | else | |
4096 | c = 0; | |
4097 | ||
4098 | if (c == count) { | |
0dfedd61 | 4099 | struct irq_2_irte *irte_info; |
2b324506 JR |
4100 | |
4101 | for (; c != 0; --c) | |
4102 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
4103 | ||
4104 | index -= count - 1; | |
4105 | ||
9b1b0e42 | 4106 | cfg->remapped = 1; |
0dfedd61 JR |
4107 | irte_info = &cfg->irq_2_irte; |
4108 | irte_info->devid = devid; | |
4109 | irte_info->index = index; | |
2b324506 JR |
4110 | |
4111 | goto out; | |
4112 | } | |
4113 | } | |
4114 | ||
4115 | index = -ENOSPC; | |
4116 | ||
4117 | out: | |
4118 | spin_unlock_irqrestore(&table->lock, flags); | |
4119 | ||
4120 | return index; | |
4121 | } | |
4122 | ||
4123 | static int get_irte(u16 devid, int index, union irte *irte) | |
4124 | { | |
4125 | struct irq_remap_table *table; | |
4126 | unsigned long flags; | |
4127 | ||
4128 | table = get_irq_table(devid, false); | |
4129 | if (!table) | |
4130 | return -ENOMEM; | |
4131 | ||
4132 | spin_lock_irqsave(&table->lock, flags); | |
4133 | irte->val = table->table[index]; | |
4134 | spin_unlock_irqrestore(&table->lock, flags); | |
4135 | ||
4136 | return 0; | |
4137 | } | |
4138 | ||
4139 | static int modify_irte(u16 devid, int index, union irte irte) | |
4140 | { | |
4141 | struct irq_remap_table *table; | |
4142 | struct amd_iommu *iommu; | |
4143 | unsigned long flags; | |
4144 | ||
4145 | iommu = amd_iommu_rlookup_table[devid]; | |
4146 | if (iommu == NULL) | |
4147 | return -EINVAL; | |
4148 | ||
4149 | table = get_irq_table(devid, false); | |
4150 | if (!table) | |
4151 | return -ENOMEM; | |
4152 | ||
4153 | spin_lock_irqsave(&table->lock, flags); | |
4154 | table->table[index] = irte.val; | |
4155 | spin_unlock_irqrestore(&table->lock, flags); | |
4156 | ||
4157 | iommu_flush_irt(iommu, devid); | |
4158 | iommu_completion_wait(iommu); | |
4159 | ||
4160 | return 0; | |
4161 | } | |
4162 | ||
4163 | static void free_irte(u16 devid, int index) | |
4164 | { | |
4165 | struct irq_remap_table *table; | |
4166 | struct amd_iommu *iommu; | |
4167 | unsigned long flags; | |
4168 | ||
4169 | iommu = amd_iommu_rlookup_table[devid]; | |
4170 | if (iommu == NULL) | |
4171 | return; | |
4172 | ||
4173 | table = get_irq_table(devid, false); | |
4174 | if (!table) | |
4175 | return; | |
4176 | ||
4177 | spin_lock_irqsave(&table->lock, flags); | |
4178 | table->table[index] = 0; | |
4179 | spin_unlock_irqrestore(&table->lock, flags); | |
4180 | ||
4181 | iommu_flush_irt(iommu, devid); | |
4182 | iommu_completion_wait(iommu); | |
4183 | } | |
4184 | ||
5527de74 JR |
4185 | static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
4186 | unsigned int destination, int vector, | |
4187 | struct io_apic_irq_attr *attr) | |
4188 | { | |
4189 | struct irq_remap_table *table; | |
0dfedd61 | 4190 | struct irq_2_irte *irte_info; |
5527de74 JR |
4191 | struct irq_cfg *cfg; |
4192 | union irte irte; | |
4193 | int ioapic_id; | |
4194 | int index; | |
4195 | int devid; | |
4196 | int ret; | |
4197 | ||
4198 | cfg = irq_get_chip_data(irq); | |
4199 | if (!cfg) | |
4200 | return -EINVAL; | |
4201 | ||
0dfedd61 | 4202 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4203 | ioapic_id = mpc_ioapic_id(attr->ioapic); |
4204 | devid = get_ioapic_devid(ioapic_id); | |
4205 | ||
4206 | if (devid < 0) | |
4207 | return devid; | |
4208 | ||
4209 | table = get_irq_table(devid, true); | |
4210 | if (table == NULL) | |
4211 | return -ENOMEM; | |
4212 | ||
4213 | index = attr->ioapic_pin; | |
4214 | ||
4215 | /* Setup IRQ remapping info */ | |
9b1b0e42 | 4216 | cfg->remapped = 1; |
0dfedd61 JR |
4217 | irte_info->devid = devid; |
4218 | irte_info->index = index; | |
5527de74 JR |
4219 | |
4220 | /* Setup IRTE for IOMMU */ | |
4221 | irte.val = 0; | |
4222 | irte.fields.vector = vector; | |
4223 | irte.fields.int_type = apic->irq_delivery_mode; | |
4224 | irte.fields.destination = destination; | |
4225 | irte.fields.dm = apic->irq_dest_mode; | |
4226 | irte.fields.valid = 1; | |
4227 | ||
4228 | ret = modify_irte(devid, index, irte); | |
4229 | if (ret) | |
4230 | return ret; | |
4231 | ||
4232 | /* Setup IOAPIC entry */ | |
4233 | memset(entry, 0, sizeof(*entry)); | |
4234 | ||
4235 | entry->vector = index; | |
4236 | entry->mask = 0; | |
4237 | entry->trigger = attr->trigger; | |
4238 | entry->polarity = attr->polarity; | |
4239 | ||
4240 | /* | |
4241 | * Mask level triggered irqs. | |
5527de74 JR |
4242 | */ |
4243 | if (attr->trigger) | |
4244 | entry->mask = 1; | |
4245 | ||
4246 | return 0; | |
4247 | } | |
4248 | ||
4249 | static int set_affinity(struct irq_data *data, const struct cpumask *mask, | |
4250 | bool force) | |
4251 | { | |
0dfedd61 | 4252 | struct irq_2_irte *irte_info; |
5527de74 JR |
4253 | unsigned int dest, irq; |
4254 | struct irq_cfg *cfg; | |
4255 | union irte irte; | |
4256 | int err; | |
4257 | ||
4258 | if (!config_enabled(CONFIG_SMP)) | |
4259 | return -1; | |
4260 | ||
4261 | cfg = data->chip_data; | |
4262 | irq = data->irq; | |
0dfedd61 | 4263 | irte_info = &cfg->irq_2_irte; |
5527de74 JR |
4264 | |
4265 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
4266 | return -EINVAL; | |
4267 | ||
0dfedd61 | 4268 | if (get_irte(irte_info->devid, irte_info->index, &irte)) |
5527de74 JR |
4269 | return -EBUSY; |
4270 | ||
4271 | if (assign_irq_vector(irq, cfg, mask)) | |
4272 | return -EBUSY; | |
4273 | ||
4274 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); | |
4275 | if (err) { | |
4276 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
4277 | pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq); | |
4278 | return err; | |
4279 | } | |
4280 | ||
4281 | irte.fields.vector = cfg->vector; | |
4282 | irte.fields.destination = dest; | |
4283 | ||
0dfedd61 | 4284 | modify_irte(irte_info->devid, irte_info->index, irte); |
5527de74 JR |
4285 | |
4286 | if (cfg->move_in_progress) | |
4287 | send_cleanup_vector(cfg); | |
4288 | ||
4289 | cpumask_copy(data->affinity, mask); | |
4290 | ||
4291 | return 0; | |
4292 | } | |
4293 | ||
4294 | static int free_irq(int irq) | |
4295 | { | |
0dfedd61 | 4296 | struct irq_2_irte *irte_info; |
5527de74 JR |
4297 | struct irq_cfg *cfg; |
4298 | ||
4299 | cfg = irq_get_chip_data(irq); | |
4300 | if (!cfg) | |
4301 | return -EINVAL; | |
4302 | ||
0dfedd61 | 4303 | irte_info = &cfg->irq_2_irte; |
5527de74 | 4304 | |
0dfedd61 | 4305 | free_irte(irte_info->devid, irte_info->index); |
5527de74 JR |
4306 | |
4307 | return 0; | |
4308 | } | |
4309 | ||
0b4d48cb JR |
4310 | static void compose_msi_msg(struct pci_dev *pdev, |
4311 | unsigned int irq, unsigned int dest, | |
4312 | struct msi_msg *msg, u8 hpet_id) | |
4313 | { | |
0dfedd61 | 4314 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4315 | struct irq_cfg *cfg; |
4316 | union irte irte; | |
4317 | ||
4318 | cfg = irq_get_chip_data(irq); | |
4319 | if (!cfg) | |
4320 | return; | |
4321 | ||
0dfedd61 | 4322 | irte_info = &cfg->irq_2_irte; |
0b4d48cb JR |
4323 | |
4324 | irte.val = 0; | |
4325 | irte.fields.vector = cfg->vector; | |
4326 | irte.fields.int_type = apic->irq_delivery_mode; | |
4327 | irte.fields.destination = dest; | |
4328 | irte.fields.dm = apic->irq_dest_mode; | |
4329 | irte.fields.valid = 1; | |
4330 | ||
0dfedd61 | 4331 | modify_irte(irte_info->devid, irte_info->index, irte); |
0b4d48cb JR |
4332 | |
4333 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4334 | msg->address_lo = MSI_ADDR_BASE_LO; | |
0dfedd61 | 4335 | msg->data = irte_info->index; |
0b4d48cb JR |
4336 | } |
4337 | ||
4338 | static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec) | |
4339 | { | |
4340 | struct irq_cfg *cfg; | |
4341 | int index; | |
4342 | u16 devid; | |
4343 | ||
4344 | if (!pdev) | |
4345 | return -EINVAL; | |
4346 | ||
4347 | cfg = irq_get_chip_data(irq); | |
4348 | if (!cfg) | |
4349 | return -EINVAL; | |
4350 | ||
4351 | devid = get_device_id(&pdev->dev); | |
4352 | index = alloc_irq_index(cfg, devid, nvec); | |
4353 | ||
4354 | return index < 0 ? MAX_IRQS_PER_TABLE : index; | |
4355 | } | |
4356 | ||
4357 | static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
4358 | int index, int offset) | |
4359 | { | |
0dfedd61 | 4360 | struct irq_2_irte *irte_info; |
0b4d48cb JR |
4361 | struct irq_cfg *cfg; |
4362 | u16 devid; | |
4363 | ||
4364 | if (!pdev) | |
4365 | return -EINVAL; | |
4366 | ||
4367 | cfg = irq_get_chip_data(irq); | |
4368 | if (!cfg) | |
4369 | return -EINVAL; | |
4370 | ||
4371 | if (index >= MAX_IRQS_PER_TABLE) | |
4372 | return 0; | |
4373 | ||
4374 | devid = get_device_id(&pdev->dev); | |
0dfedd61 | 4375 | irte_info = &cfg->irq_2_irte; |
0b4d48cb | 4376 | |
9b1b0e42 | 4377 | cfg->remapped = 1; |
0dfedd61 JR |
4378 | irte_info->devid = devid; |
4379 | irte_info->index = index + offset; | |
0b4d48cb JR |
4380 | |
4381 | return 0; | |
4382 | } | |
4383 | ||
d976195c JR |
4384 | static int setup_hpet_msi(unsigned int irq, unsigned int id) |
4385 | { | |
0dfedd61 | 4386 | struct irq_2_irte *irte_info; |
d976195c JR |
4387 | struct irq_cfg *cfg; |
4388 | int index, devid; | |
4389 | ||
4390 | cfg = irq_get_chip_data(irq); | |
4391 | if (!cfg) | |
4392 | return -EINVAL; | |
4393 | ||
0dfedd61 | 4394 | irte_info = &cfg->irq_2_irte; |
d976195c JR |
4395 | devid = get_hpet_devid(id); |
4396 | if (devid < 0) | |
4397 | return devid; | |
4398 | ||
4399 | index = alloc_irq_index(cfg, devid, 1); | |
4400 | if (index < 0) | |
4401 | return index; | |
4402 | ||
9b1b0e42 | 4403 | cfg->remapped = 1; |
0dfedd61 JR |
4404 | irte_info->devid = devid; |
4405 | irte_info->index = index; | |
d976195c JR |
4406 | |
4407 | return 0; | |
4408 | } | |
4409 | ||
6b474b82 JR |
4410 | struct irq_remap_ops amd_iommu_irq_ops = { |
4411 | .supported = amd_iommu_supported, | |
4412 | .prepare = amd_iommu_prepare, | |
4413 | .enable = amd_iommu_enable, | |
4414 | .disable = amd_iommu_disable, | |
4415 | .reenable = amd_iommu_reenable, | |
4416 | .enable_faulting = amd_iommu_enable_faulting, | |
4417 | .setup_ioapic_entry = setup_ioapic_entry, | |
4418 | .set_affinity = set_affinity, | |
4419 | .free_irq = free_irq, | |
4420 | .compose_msi_msg = compose_msi_msg, | |
4421 | .msi_alloc_irq = msi_alloc_irq, | |
4422 | .msi_setup_irq = msi_setup_irq, | |
4423 | .setup_hpet_msi = setup_hpet_msi, | |
4424 | }; | |
2b324506 | 4425 | #endif |