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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
101fa037 JR |
20 | #define pr_fmt(fmt) "AMD-Vi: " fmt |
21 | ||
72e1dcc4 | 22 | #include <linux/ratelimit.h> |
b6c02715 | 23 | #include <linux/pci.h> |
2bf9a0a1 | 24 | #include <linux/acpi.h> |
9a4d3bf5 | 25 | #include <linux/amba/bus.h> |
0076cd3d | 26 | #include <linux/platform_device.h> |
cb41ed85 | 27 | #include <linux/pci-ats.h> |
a66022c4 | 28 | #include <linux/bitmap.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
7f26508b | 30 | #include <linux/debugfs.h> |
b6c02715 | 31 | #include <linux/scatterlist.h> |
51491367 | 32 | #include <linux/dma-mapping.h> |
fec777c3 | 33 | #include <linux/dma-direct.h> |
b6c02715 | 34 | #include <linux/iommu-helper.h> |
c156e347 | 35 | #include <linux/iommu.h> |
815b33fd | 36 | #include <linux/delay.h> |
403f81d8 | 37 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
38 | #include <linux/notifier.h> |
39 | #include <linux/export.h> | |
2b324506 JR |
40 | #include <linux/irq.h> |
41 | #include <linux/msi.h> | |
3b839a57 | 42 | #include <linux/dma-contiguous.h> |
7c71d306 | 43 | #include <linux/irqdomain.h> |
5f6bed50 | 44 | #include <linux/percpu.h> |
307d5851 | 45 | #include <linux/iova.h> |
2b324506 JR |
46 | #include <asm/irq_remapping.h> |
47 | #include <asm/io_apic.h> | |
48 | #include <asm/apic.h> | |
49 | #include <asm/hw_irq.h> | |
17f5b569 | 50 | #include <asm/msidef.h> |
b6c02715 | 51 | #include <asm/proto.h> |
46a7fa27 | 52 | #include <asm/iommu.h> |
1d9b16d1 | 53 | #include <asm/gart.h> |
27c2127a | 54 | #include <asm/dma.h> |
403f81d8 JR |
55 | |
56 | #include "amd_iommu_proto.h" | |
57 | #include "amd_iommu_types.h" | |
6b474b82 | 58 | #include "irq_remapping.h" |
b6c02715 JR |
59 | |
60 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
61 | ||
815b33fd | 62 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 63 | |
307d5851 JR |
64 | /* IO virtual address start page frame number */ |
65 | #define IOVA_START_PFN (1) | |
66 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 67 | |
81cd07b9 JR |
68 | /* Reserved IOVA ranges */ |
69 | #define MSI_RANGE_START (0xfee00000) | |
70 | #define MSI_RANGE_END (0xfeefffff) | |
71 | #define HT_RANGE_START (0xfd00000000ULL) | |
72 | #define HT_RANGE_END (0xffffffffffULL) | |
73 | ||
aa3de9c0 OBC |
74 | /* |
75 | * This bitmap is used to advertise the page sizes our hardware support | |
76 | * to the IOMMU core, which will then use this information to split | |
77 | * physically contiguous memory regions it is mapping into page sizes | |
78 | * that we support. | |
79 | * | |
954e3dd8 | 80 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 81 | */ |
954e3dd8 | 82 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 83 | |
2cd1083d | 84 | static DEFINE_SPINLOCK(amd_iommu_devtable_lock); |
2bc00180 | 85 | static DEFINE_SPINLOCK(pd_bitmap_lock); |
b6c02715 | 86 | |
8fa5f802 | 87 | /* List of all available dev_data structures */ |
779da732 | 88 | static LLIST_HEAD(dev_data_list); |
8fa5f802 | 89 | |
6efed63b JR |
90 | LIST_HEAD(ioapic_map); |
91 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 92 | LIST_HEAD(acpihid_map); |
6efed63b | 93 | |
0feae533 JR |
94 | /* |
95 | * Domain for untranslated devices - only allocated | |
96 | * if iommu=pt passed on kernel cmd line. | |
97 | */ | |
b0119e87 | 98 | const struct iommu_ops amd_iommu_ops; |
26961efe | 99 | |
72e1dcc4 | 100 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 101 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 102 | |
5299709d | 103 | static const struct dma_map_ops amd_iommu_dma_ops; |
ac1534a5 | 104 | |
431b2a20 JR |
105 | /* |
106 | * general struct to manage commands send to an IOMMU | |
107 | */ | |
d6449536 | 108 | struct iommu_cmd { |
b6c02715 JR |
109 | u32 data[4]; |
110 | }; | |
111 | ||
05152a04 JR |
112 | struct kmem_cache *amd_iommu_irq_cache; |
113 | ||
04bfdd84 | 114 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 115 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 116 | static void detach_device(struct device *dev); |
9003d618 | 117 | static void iova_domain_flush_tlb(struct iova_domain *iovad); |
d4241a27 | 118 | |
007b74ba JR |
119 | /* |
120 | * Data container for a dma_ops specific protection domain | |
121 | */ | |
122 | struct dma_ops_domain { | |
123 | /* generic protection domain information */ | |
124 | struct protection_domain domain; | |
125 | ||
307d5851 JR |
126 | /* IOVA RB-Tree */ |
127 | struct iova_domain iovad; | |
007b74ba JR |
128 | }; |
129 | ||
81cd07b9 JR |
130 | static struct iova_domain reserved_iova_ranges; |
131 | static struct lock_class_key reserved_rbtree_key; | |
132 | ||
15898bbc JR |
133 | /**************************************************************************** |
134 | * | |
135 | * Helper functions | |
136 | * | |
137 | ****************************************************************************/ | |
138 | ||
2bf9a0a1 WZ |
139 | static inline int match_hid_uid(struct device *dev, |
140 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 141 | { |
2bf9a0a1 WZ |
142 | const char *hid, *uid; |
143 | ||
144 | hid = acpi_device_hid(ACPI_COMPANION(dev)); | |
145 | uid = acpi_device_uid(ACPI_COMPANION(dev)); | |
146 | ||
147 | if (!hid || !(*hid)) | |
148 | return -ENODEV; | |
149 | ||
150 | if (!uid || !(*uid)) | |
151 | return strcmp(hid, entry->hid); | |
152 | ||
153 | if (!(*entry->uid)) | |
154 | return strcmp(hid, entry->hid); | |
155 | ||
156 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
157 | } |
158 | ||
2bf9a0a1 | 159 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
160 | { |
161 | struct pci_dev *pdev = to_pci_dev(dev); | |
162 | ||
163 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
164 | } | |
165 | ||
2bf9a0a1 WZ |
166 | static inline int get_acpihid_device_id(struct device *dev, |
167 | struct acpihid_map_entry **entry) | |
168 | { | |
169 | struct acpihid_map_entry *p; | |
170 | ||
171 | list_for_each_entry(p, &acpihid_map, list) { | |
172 | if (!match_hid_uid(dev, p)) { | |
173 | if (entry) | |
174 | *entry = p; | |
175 | return p->devid; | |
176 | } | |
177 | } | |
178 | return -EINVAL; | |
179 | } | |
180 | ||
181 | static inline int get_device_id(struct device *dev) | |
182 | { | |
183 | int devid; | |
184 | ||
185 | if (dev_is_pci(dev)) | |
186 | devid = get_pci_device_id(dev); | |
187 | else | |
188 | devid = get_acpihid_device_id(dev, NULL); | |
189 | ||
190 | return devid; | |
191 | } | |
192 | ||
3f4b87b9 JR |
193 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
194 | { | |
195 | return container_of(dom, struct protection_domain, domain); | |
196 | } | |
197 | ||
b3311b06 JR |
198 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
199 | { | |
200 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
201 | return container_of(domain, struct dma_ops_domain, domain); | |
202 | } | |
203 | ||
f62dda66 | 204 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
205 | { |
206 | struct iommu_dev_data *dev_data; | |
8fa5f802 JR |
207 | |
208 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
209 | if (!dev_data) | |
210 | return NULL; | |
211 | ||
f62dda66 | 212 | dev_data->devid = devid; |
30bf2df6 JR |
213 | ratelimit_default_init(&dev_data->rs); |
214 | ||
779da732 | 215 | llist_add(&dev_data->dev_data_list, &dev_data_list); |
8fa5f802 JR |
216 | return dev_data; |
217 | } | |
218 | ||
3b03bb74 JR |
219 | static struct iommu_dev_data *search_dev_data(u16 devid) |
220 | { | |
221 | struct iommu_dev_data *dev_data; | |
779da732 | 222 | struct llist_node *node; |
3b03bb74 | 223 | |
779da732 SAS |
224 | if (llist_empty(&dev_data_list)) |
225 | return NULL; | |
3b03bb74 | 226 | |
779da732 SAS |
227 | node = dev_data_list.first; |
228 | llist_for_each_entry(dev_data, node, dev_data_list) { | |
3b03bb74 | 229 | if (dev_data->devid == devid) |
779da732 | 230 | return dev_data; |
3b03bb74 JR |
231 | } |
232 | ||
779da732 | 233 | return NULL; |
3b03bb74 JR |
234 | } |
235 | ||
e3156048 JR |
236 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
237 | { | |
238 | *(u16 *)data = alias; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static u16 get_alias(struct device *dev) | |
243 | { | |
244 | struct pci_dev *pdev = to_pci_dev(dev); | |
245 | u16 devid, ivrs_alias, pci_alias; | |
246 | ||
6c0b43df | 247 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 | 248 | devid = get_device_id(dev); |
5ebb1bc2 AN |
249 | |
250 | /* For ACPI HID devices, we simply return the devid as such */ | |
251 | if (!dev_is_pci(dev)) | |
252 | return devid; | |
253 | ||
e3156048 | 254 | ivrs_alias = amd_iommu_alias_table[devid]; |
5ebb1bc2 | 255 | |
e3156048 JR |
256 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); |
257 | ||
258 | if (ivrs_alias == pci_alias) | |
259 | return ivrs_alias; | |
260 | ||
261 | /* | |
262 | * DMA alias showdown | |
263 | * | |
264 | * The IVRS is fairly reliable in telling us about aliases, but it | |
265 | * can't know about every screwy device. If we don't have an IVRS | |
266 | * reported alias, use the PCI reported alias. In that case we may | |
267 | * still need to initialize the rlookup and dev_table entries if the | |
268 | * alias is to a non-existent device. | |
269 | */ | |
270 | if (ivrs_alias == devid) { | |
271 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
272 | amd_iommu_rlookup_table[pci_alias] = | |
273 | amd_iommu_rlookup_table[devid]; | |
274 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
275 | amd_iommu_dev_table[devid].data, | |
276 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
277 | } | |
278 | ||
279 | return pci_alias; | |
280 | } | |
281 | ||
101fa037 | 282 | pr_info("Using IVRS reported alias %02x:%02x.%d " |
e3156048 JR |
283 | "for device %s[%04x:%04x], kernel reported alias " |
284 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
285 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
286 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
287 | PCI_FUNC(pci_alias)); | |
288 | ||
289 | /* | |
290 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
291 | * bus, then the IVRS table may know about a quirk that we don't. | |
292 | */ | |
293 | if (pci_alias == devid && | |
294 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 295 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
101fa037 | 296 | pr_info("Added PCI DMA alias %02x.%d for %s\n", |
e3156048 JR |
297 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), |
298 | dev_name(dev)); | |
299 | } | |
300 | ||
301 | return ivrs_alias; | |
302 | } | |
303 | ||
3b03bb74 JR |
304 | static struct iommu_dev_data *find_dev_data(u16 devid) |
305 | { | |
306 | struct iommu_dev_data *dev_data; | |
df3f7a6e | 307 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3b03bb74 JR |
308 | |
309 | dev_data = search_dev_data(devid); | |
310 | ||
df3f7a6e | 311 | if (dev_data == NULL) { |
3b03bb74 | 312 | dev_data = alloc_dev_data(devid); |
39ffe395 SAS |
313 | if (!dev_data) |
314 | return NULL; | |
3b03bb74 | 315 | |
df3f7a6e BH |
316 | if (translation_pre_enabled(iommu)) |
317 | dev_data->defer_attach = true; | |
318 | } | |
319 | ||
3b03bb74 JR |
320 | return dev_data; |
321 | } | |
322 | ||
daae2d25 | 323 | struct iommu_dev_data *get_dev_data(struct device *dev) |
657cbb6b JR |
324 | { |
325 | return dev->archdata.iommu; | |
326 | } | |
daae2d25 | 327 | EXPORT_SYMBOL(get_dev_data); |
657cbb6b | 328 | |
b097d11a WZ |
329 | /* |
330 | * Find or create an IOMMU group for a acpihid device. | |
331 | */ | |
332 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 333 | { |
b097d11a | 334 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 335 | int devid; |
b097d11a WZ |
336 | |
337 | devid = get_acpihid_device_id(dev, &entry); | |
338 | if (devid < 0) | |
339 | return ERR_PTR(devid); | |
340 | ||
341 | list_for_each_entry(p, &acpihid_map, list) { | |
342 | if ((devid == p->devid) && p->group) | |
343 | entry->group = p->group; | |
344 | } | |
345 | ||
346 | if (!entry->group) | |
347 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
348 | else |
349 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
350 | |
351 | return entry->group; | |
657cbb6b JR |
352 | } |
353 | ||
5abcdba4 JR |
354 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
355 | { | |
356 | static const int caps[] = { | |
357 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
358 | PCI_EXT_CAP_ID_PRI, |
359 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
360 | }; |
361 | int i, pos; | |
362 | ||
cef74409 GK |
363 | if (pci_ats_disabled()) |
364 | return false; | |
365 | ||
5abcdba4 JR |
366 | for (i = 0; i < 3; ++i) { |
367 | pos = pci_find_ext_capability(pdev, caps[i]); | |
368 | if (pos == 0) | |
369 | return false; | |
370 | } | |
371 | ||
372 | return true; | |
373 | } | |
374 | ||
6a113ddc JR |
375 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
376 | { | |
377 | struct iommu_dev_data *dev_data; | |
378 | ||
379 | dev_data = get_dev_data(&pdev->dev); | |
380 | ||
381 | return dev_data->errata & (1 << erratum) ? true : false; | |
382 | } | |
383 | ||
98fc5a69 JR |
384 | /* |
385 | * This function checks if the driver got a valid device from the caller to | |
386 | * avoid dereferencing invalid pointers. | |
387 | */ | |
388 | static bool check_device(struct device *dev) | |
389 | { | |
7aba6cb9 | 390 | int devid; |
98fc5a69 JR |
391 | |
392 | if (!dev || !dev->dma_mask) | |
393 | return false; | |
394 | ||
98fc5a69 | 395 | devid = get_device_id(dev); |
9ee35e4c | 396 | if (devid < 0) |
7aba6cb9 | 397 | return false; |
98fc5a69 JR |
398 | |
399 | /* Out of our scope? */ | |
400 | if (devid > amd_iommu_last_bdf) | |
401 | return false; | |
402 | ||
403 | if (amd_iommu_rlookup_table[devid] == NULL) | |
404 | return false; | |
405 | ||
406 | return true; | |
407 | } | |
408 | ||
25b11ce2 | 409 | static void init_iommu_group(struct device *dev) |
2851db21 | 410 | { |
2851db21 | 411 | struct iommu_group *group; |
2851db21 | 412 | |
65d5352f | 413 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
414 | if (IS_ERR(group)) |
415 | return; | |
416 | ||
0bb6e243 | 417 | iommu_group_put(group); |
eb9c9527 AW |
418 | } |
419 | ||
420 | static int iommu_init_device(struct device *dev) | |
421 | { | |
eb9c9527 | 422 | struct iommu_dev_data *dev_data; |
39ab9555 | 423 | struct amd_iommu *iommu; |
7aba6cb9 | 424 | int devid; |
eb9c9527 AW |
425 | |
426 | if (dev->archdata.iommu) | |
427 | return 0; | |
428 | ||
7aba6cb9 | 429 | devid = get_device_id(dev); |
9ee35e4c | 430 | if (devid < 0) |
7aba6cb9 WZ |
431 | return devid; |
432 | ||
39ab9555 JR |
433 | iommu = amd_iommu_rlookup_table[devid]; |
434 | ||
7aba6cb9 | 435 | dev_data = find_dev_data(devid); |
eb9c9527 AW |
436 | if (!dev_data) |
437 | return -ENOMEM; | |
438 | ||
e3156048 JR |
439 | dev_data->alias = get_alias(dev); |
440 | ||
c12b08eb YZ |
441 | /* |
442 | * By default we use passthrough mode for IOMMUv2 capable device. | |
443 | * But if amd_iommu=force_isolation is set (e.g. to debug DMA to | |
444 | * invalid address), we ignore the capability for the device so | |
445 | * it'll be forced to go into translation mode. | |
446 | */ | |
447 | if ((iommu_pass_through || !amd_iommu_force_isolation) && | |
448 | dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { | |
5abcdba4 JR |
449 | struct amd_iommu *iommu; |
450 | ||
2bf9a0a1 | 451 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
452 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
453 | } | |
454 | ||
657cbb6b JR |
455 | dev->archdata.iommu = dev_data; |
456 | ||
e3d10af1 | 457 | iommu_device_link(&iommu->iommu, dev); |
066f2e98 | 458 | |
657cbb6b JR |
459 | return 0; |
460 | } | |
461 | ||
26018874 JR |
462 | static void iommu_ignore_device(struct device *dev) |
463 | { | |
7aba6cb9 WZ |
464 | u16 alias; |
465 | int devid; | |
26018874 JR |
466 | |
467 | devid = get_device_id(dev); | |
9ee35e4c | 468 | if (devid < 0) |
7aba6cb9 WZ |
469 | return; |
470 | ||
e3156048 | 471 | alias = get_alias(dev); |
26018874 JR |
472 | |
473 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
474 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
475 | ||
476 | amd_iommu_rlookup_table[devid] = NULL; | |
477 | amd_iommu_rlookup_table[alias] = NULL; | |
478 | } | |
479 | ||
657cbb6b JR |
480 | static void iommu_uninit_device(struct device *dev) |
481 | { | |
7aba6cb9 | 482 | struct iommu_dev_data *dev_data; |
39ab9555 JR |
483 | struct amd_iommu *iommu; |
484 | int devid; | |
c1931090 | 485 | |
7aba6cb9 | 486 | devid = get_device_id(dev); |
9ee35e4c | 487 | if (devid < 0) |
7aba6cb9 | 488 | return; |
c1931090 | 489 | |
39ab9555 JR |
490 | iommu = amd_iommu_rlookup_table[devid]; |
491 | ||
7aba6cb9 | 492 | dev_data = search_dev_data(devid); |
c1931090 AW |
493 | if (!dev_data) |
494 | return; | |
495 | ||
b6809ee5 JR |
496 | if (dev_data->domain) |
497 | detach_device(dev); | |
498 | ||
e3d10af1 | 499 | iommu_device_unlink(&iommu->iommu, dev); |
066f2e98 | 500 | |
9dcd6130 AW |
501 | iommu_group_remove_device(dev); |
502 | ||
aafd8ba0 | 503 | /* Remove dma-ops */ |
5657933d | 504 | dev->dma_ops = NULL; |
aafd8ba0 | 505 | |
8fa5f802 | 506 | /* |
c1931090 AW |
507 | * We keep dev_data around for unplugged devices and reuse it when the |
508 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 509 | */ |
657cbb6b | 510 | } |
b7cc9554 | 511 | |
a80dc3e0 JR |
512 | /**************************************************************************** |
513 | * | |
514 | * Interrupt handling functions | |
515 | * | |
516 | ****************************************************************************/ | |
517 | ||
e3e59876 JR |
518 | static void dump_dte_entry(u16 devid) |
519 | { | |
520 | int i; | |
521 | ||
ee6c2868 | 522 | for (i = 0; i < 4; ++i) |
101fa037 | 523 | pr_err("DTE[%d]: %016llx\n", i, |
e3e59876 JR |
524 | amd_iommu_dev_table[devid].data[i]); |
525 | } | |
526 | ||
945b4ac4 JR |
527 | static void dump_command(unsigned long phys_addr) |
528 | { | |
2543a786 | 529 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
530 | int i; |
531 | ||
532 | for (i = 0; i < 4; ++i) | |
101fa037 | 533 | pr_err("CMD[%d]: %08x\n", i, cmd->data[i]); |
945b4ac4 JR |
534 | } |
535 | ||
30bf2df6 JR |
536 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
537 | u64 address, int flags) | |
538 | { | |
539 | struct iommu_dev_data *dev_data = NULL; | |
540 | struct pci_dev *pdev; | |
541 | ||
d5bf0f4f SK |
542 | pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid), |
543 | devid & 0xff); | |
30bf2df6 JR |
544 | if (pdev) |
545 | dev_data = get_dev_data(&pdev->dev); | |
546 | ||
547 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
6f5086a6 | 548 | dev_err(&pdev->dev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
549 | domain_id, address, flags); |
550 | } else if (printk_ratelimit()) { | |
6f5086a6 | 551 | pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
30bf2df6 JR |
552 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
553 | domain_id, address, flags); | |
554 | } | |
555 | ||
556 | if (pdev) | |
557 | pci_dev_put(pdev); | |
558 | } | |
559 | ||
a345b23b | 560 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 561 | { |
90ca3859 | 562 | struct device *dev = iommu->iommu.dev; |
e7f63ffc | 563 | int type, devid, pasid, flags, tag; |
3d06fca8 JR |
564 | volatile u32 *event = __evt; |
565 | int count = 0; | |
566 | u64 address; | |
567 | ||
568 | retry: | |
569 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
570 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
d64c0486 | 571 | pasid = PPR_PASID(*(u64 *)&event[0]); |
3d06fca8 JR |
572 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; |
573 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
574 | ||
575 | if (type == 0) { | |
576 | /* Did we hit the erratum? */ | |
577 | if (++count == LOOP_TIMEOUT) { | |
101fa037 | 578 | pr_err("No event written to event log\n"); |
3d06fca8 JR |
579 | return; |
580 | } | |
581 | udelay(1); | |
582 | goto retry; | |
583 | } | |
90008ee4 | 584 | |
30bf2df6 | 585 | if (type == EVENT_TYPE_IO_FAULT) { |
d64c0486 | 586 | amd_iommu_report_page_fault(devid, pasid, address, flags); |
30bf2df6 | 587 | return; |
30bf2df6 | 588 | } |
90008ee4 JR |
589 | |
590 | switch (type) { | |
591 | case EVENT_TYPE_ILL_DEV: | |
6f5086a6 | 592 | dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 593 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 594 | pasid, address, flags); |
e3e59876 | 595 | dump_dte_entry(devid); |
90008ee4 | 596 | break; |
90008ee4 | 597 | case EVENT_TYPE_DEV_TAB_ERR: |
1a21ee1a | 598 | dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " |
6f5086a6 | 599 | "address=0x%llx flags=0x%04x]\n", |
90ca3859 GH |
600 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
601 | address, flags); | |
90008ee4 JR |
602 | break; |
603 | case EVENT_TYPE_PAGE_TAB_ERR: | |
6f5086a6 | 604 | dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 605 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 606 | pasid, address, flags); |
90008ee4 JR |
607 | break; |
608 | case EVENT_TYPE_ILL_CMD: | |
6f5086a6 | 609 | dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address); |
945b4ac4 | 610 | dump_command(address); |
90008ee4 JR |
611 | break; |
612 | case EVENT_TYPE_CMD_HARD_ERR: | |
6f5086a6 | 613 | dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n", |
d64c0486 | 614 | address, flags); |
90008ee4 JR |
615 | break; |
616 | case EVENT_TYPE_IOTLB_INV_TO: | |
6f5086a6 | 617 | dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n", |
90ca3859 GH |
618 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
619 | address); | |
90008ee4 JR |
620 | break; |
621 | case EVENT_TYPE_INV_DEV_REQ: | |
6f5086a6 | 622 | dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
90ca3859 | 623 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
d64c0486 | 624 | pasid, address, flags); |
90008ee4 | 625 | break; |
e7f63ffc GH |
626 | case EVENT_TYPE_INV_PPR_REQ: |
627 | pasid = ((event[0] >> 16) & 0xFFFF) | |
628 | | ((event[1] << 6) & 0xF0000); | |
629 | tag = event[1] & 0x03FF; | |
6f5086a6 | 630 | dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n", |
e7f63ffc GH |
631 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
632 | pasid, address, flags); | |
90008ee4 JR |
633 | break; |
634 | default: | |
1a21ee1a | 635 | dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n", |
90ca3859 | 636 | event[0], event[1], event[2], event[3]); |
90008ee4 | 637 | } |
3d06fca8 JR |
638 | |
639 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
640 | } |
641 | ||
642 | static void iommu_poll_events(struct amd_iommu *iommu) | |
643 | { | |
644 | u32 head, tail; | |
90008ee4 JR |
645 | |
646 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
647 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
648 | ||
649 | while (head != tail) { | |
a345b23b | 650 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 651 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
652 | } |
653 | ||
654 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
655 | } |
656 | ||
eee53537 | 657 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
658 | { |
659 | struct amd_iommu_fault fault; | |
72e1dcc4 | 660 | |
72e1dcc4 | 661 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
101fa037 | 662 | pr_err_ratelimited("Unknown PPR request received\n"); |
72e1dcc4 JR |
663 | return; |
664 | } | |
665 | ||
666 | fault.address = raw[1]; | |
667 | fault.pasid = PPR_PASID(raw[0]); | |
668 | fault.device_id = PPR_DEVID(raw[0]); | |
669 | fault.tag = PPR_TAG(raw[0]); | |
670 | fault.flags = PPR_FLAGS(raw[0]); | |
671 | ||
72e1dcc4 JR |
672 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
673 | } | |
674 | ||
675 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
676 | { | |
72e1dcc4 JR |
677 | u32 head, tail; |
678 | ||
679 | if (iommu->ppr_log == NULL) | |
680 | return; | |
681 | ||
72e1dcc4 JR |
682 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
683 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
684 | ||
685 | while (head != tail) { | |
eee53537 JR |
686 | volatile u64 *raw; |
687 | u64 entry[2]; | |
688 | int i; | |
689 | ||
690 | raw = (u64 *)(iommu->ppr_log + head); | |
691 | ||
692 | /* | |
693 | * Hardware bug: Interrupt may arrive before the entry is | |
694 | * written to memory. If this happens we need to wait for the | |
695 | * entry to arrive. | |
696 | */ | |
697 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
698 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
699 | break; | |
700 | udelay(1); | |
701 | } | |
72e1dcc4 | 702 | |
eee53537 JR |
703 | /* Avoid memcpy function-call overhead */ |
704 | entry[0] = raw[0]; | |
705 | entry[1] = raw[1]; | |
72e1dcc4 | 706 | |
eee53537 JR |
707 | /* |
708 | * To detect the hardware bug we need to clear the entry | |
709 | * back to zero. | |
710 | */ | |
711 | raw[0] = raw[1] = 0UL; | |
712 | ||
713 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
714 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
715 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 716 | |
eee53537 JR |
717 | /* Handle PPR entry */ |
718 | iommu_handle_ppr_entry(iommu, entry); | |
719 | ||
eee53537 JR |
720 | /* Refresh ring-buffer information */ |
721 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
722 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
723 | } | |
72e1dcc4 JR |
724 | } |
725 | ||
bd6fcefc SS |
726 | #ifdef CONFIG_IRQ_REMAP |
727 | static int (*iommu_ga_log_notifier)(u32); | |
728 | ||
729 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
730 | { | |
731 | iommu_ga_log_notifier = notifier; | |
732 | ||
733 | return 0; | |
734 | } | |
735 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
736 | ||
737 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
738 | { | |
739 | u32 head, tail, cnt = 0; | |
740 | ||
741 | if (iommu->ga_log == NULL) | |
742 | return; | |
743 | ||
744 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
745 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
746 | ||
747 | while (head != tail) { | |
748 | volatile u64 *raw; | |
749 | u64 log_entry; | |
750 | ||
751 | raw = (u64 *)(iommu->ga_log + head); | |
752 | cnt++; | |
753 | ||
754 | /* Avoid memcpy function-call overhead */ | |
755 | log_entry = *raw; | |
756 | ||
757 | /* Update head pointer of hardware ring-buffer */ | |
758 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
759 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
760 | ||
761 | /* Handle GA entry */ | |
762 | switch (GA_REQ_TYPE(log_entry)) { | |
763 | case GA_GUEST_NR: | |
764 | if (!iommu_ga_log_notifier) | |
765 | break; | |
766 | ||
101fa037 | 767 | pr_debug("%s: devid=%#x, ga_tag=%#x\n", |
bd6fcefc SS |
768 | __func__, GA_DEVID(log_entry), |
769 | GA_TAG(log_entry)); | |
770 | ||
771 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
101fa037 | 772 | pr_err("GA log notifier failed.\n"); |
bd6fcefc SS |
773 | break; |
774 | default: | |
775 | break; | |
776 | } | |
777 | } | |
778 | } | |
779 | #endif /* CONFIG_IRQ_REMAP */ | |
780 | ||
781 | #define AMD_IOMMU_INT_MASK \ | |
782 | (MMIO_STATUS_EVT_INT_MASK | \ | |
783 | MMIO_STATUS_PPR_INT_MASK | \ | |
784 | MMIO_STATUS_GALOG_INT_MASK) | |
785 | ||
72fe00f0 | 786 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 787 | { |
3f398bc7 SS |
788 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
789 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 790 | |
bd6fcefc SS |
791 | while (status & AMD_IOMMU_INT_MASK) { |
792 | /* Enable EVT and PPR and GA interrupts again */ | |
793 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 794 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 795 | |
3f398bc7 | 796 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
101fa037 | 797 | pr_devel("Processing IOMMU Event Log\n"); |
3f398bc7 SS |
798 | iommu_poll_events(iommu); |
799 | } | |
90008ee4 | 800 | |
3f398bc7 | 801 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
101fa037 | 802 | pr_devel("Processing IOMMU PPR Log\n"); |
3f398bc7 SS |
803 | iommu_poll_ppr_log(iommu); |
804 | } | |
90008ee4 | 805 | |
bd6fcefc SS |
806 | #ifdef CONFIG_IRQ_REMAP |
807 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
101fa037 | 808 | pr_devel("Processing IOMMU GA Log\n"); |
bd6fcefc SS |
809 | iommu_poll_ga_log(iommu); |
810 | } | |
811 | #endif | |
812 | ||
3f398bc7 SS |
813 | /* |
814 | * Hardware bug: ERBT1312 | |
815 | * When re-enabling interrupt (by writing 1 | |
816 | * to clear the bit), the hardware might also try to set | |
817 | * the interrupt bit in the event status register. | |
818 | * In this scenario, the bit will be set, and disable | |
819 | * subsequent interrupts. | |
820 | * | |
821 | * Workaround: The IOMMU driver should read back the | |
822 | * status register and check if the interrupt bits are cleared. | |
823 | * If not, driver will need to go through the interrupt handler | |
824 | * again and re-clear the bits | |
825 | */ | |
826 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
827 | } | |
90008ee4 | 828 | return IRQ_HANDLED; |
a80dc3e0 JR |
829 | } |
830 | ||
72fe00f0 JR |
831 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
832 | { | |
833 | return IRQ_WAKE_THREAD; | |
834 | } | |
835 | ||
431b2a20 JR |
836 | /**************************************************************************** |
837 | * | |
838 | * IOMMU command queuing functions | |
839 | * | |
840 | ****************************************************************************/ | |
841 | ||
ac0ea6e9 JR |
842 | static int wait_on_sem(volatile u64 *sem) |
843 | { | |
844 | int i = 0; | |
845 | ||
846 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
847 | udelay(1); | |
848 | i += 1; | |
849 | } | |
850 | ||
851 | if (i == LOOP_TIMEOUT) { | |
101fa037 | 852 | pr_alert("Completion-Wait loop timed out\n"); |
ac0ea6e9 JR |
853 | return -EIO; |
854 | } | |
855 | ||
856 | return 0; | |
857 | } | |
858 | ||
859 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 860 | struct iommu_cmd *cmd) |
a19ae1ec | 861 | { |
a19ae1ec JR |
862 | u8 *target; |
863 | ||
d334a563 TL |
864 | target = iommu->cmd_buf + iommu->cmd_buf_tail; |
865 | ||
866 | iommu->cmd_buf_tail += sizeof(*cmd); | |
867 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; | |
ac0ea6e9 JR |
868 | |
869 | /* Copy command to buffer */ | |
870 | memcpy(target, cmd, sizeof(*cmd)); | |
871 | ||
872 | /* Tell the IOMMU about it */ | |
d334a563 | 873 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 874 | } |
a19ae1ec | 875 | |
815b33fd | 876 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 877 | { |
2543a786 TL |
878 | u64 paddr = iommu_virt_to_phys((void *)address); |
879 | ||
815b33fd JR |
880 | WARN_ON(address & 0x7ULL); |
881 | ||
ded46737 | 882 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
883 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
884 | cmd->data[1] = upper_32_bits(paddr); | |
815b33fd | 885 | cmd->data[2] = 1; |
ded46737 JR |
886 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
887 | } | |
888 | ||
94fe79e2 JR |
889 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
890 | { | |
891 | memset(cmd, 0, sizeof(*cmd)); | |
892 | cmd->data[0] = devid; | |
893 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
894 | } | |
895 | ||
11b6402c JR |
896 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
897 | size_t size, u16 domid, int pde) | |
898 | { | |
899 | u64 pages; | |
ae0cbbb1 | 900 | bool s; |
11b6402c JR |
901 | |
902 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 903 | s = false; |
11b6402c JR |
904 | |
905 | if (pages > 1) { | |
906 | /* | |
907 | * If we have to flush more than one page, flush all | |
908 | * TLB entries for this domain | |
909 | */ | |
910 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 911 | s = true; |
11b6402c JR |
912 | } |
913 | ||
914 | address &= PAGE_MASK; | |
915 | ||
916 | memset(cmd, 0, sizeof(*cmd)); | |
917 | cmd->data[1] |= domid; | |
918 | cmd->data[2] = lower_32_bits(address); | |
919 | cmd->data[3] = upper_32_bits(address); | |
920 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
921 | if (s) /* size bit - we flush more than one 4kb page */ | |
922 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 923 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
925 | } | |
926 | ||
cb41ed85 JR |
927 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
928 | u64 address, size_t size) | |
929 | { | |
930 | u64 pages; | |
ae0cbbb1 | 931 | bool s; |
cb41ed85 JR |
932 | |
933 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 934 | s = false; |
cb41ed85 JR |
935 | |
936 | if (pages > 1) { | |
937 | /* | |
938 | * If we have to flush more than one page, flush all | |
939 | * TLB entries for this domain | |
940 | */ | |
941 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 942 | s = true; |
cb41ed85 JR |
943 | } |
944 | ||
945 | address &= PAGE_MASK; | |
946 | ||
947 | memset(cmd, 0, sizeof(*cmd)); | |
948 | cmd->data[0] = devid; | |
949 | cmd->data[0] |= (qdep & 0xff) << 24; | |
950 | cmd->data[1] = devid; | |
951 | cmd->data[2] = lower_32_bits(address); | |
952 | cmd->data[3] = upper_32_bits(address); | |
953 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
954 | if (s) | |
955 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
956 | } | |
957 | ||
22e266c7 JR |
958 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
959 | u64 address, bool size) | |
960 | { | |
961 | memset(cmd, 0, sizeof(*cmd)); | |
962 | ||
963 | address &= ~(0xfffULL); | |
964 | ||
a919a018 | 965 | cmd->data[0] = pasid; |
22e266c7 JR |
966 | cmd->data[1] = domid; |
967 | cmd->data[2] = lower_32_bits(address); | |
968 | cmd->data[3] = upper_32_bits(address); | |
969 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
970 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
971 | if (size) | |
972 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
973 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
974 | } | |
975 | ||
976 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
977 | int qdep, u64 address, bool size) | |
978 | { | |
979 | memset(cmd, 0, sizeof(*cmd)); | |
980 | ||
981 | address &= ~(0xfffULL); | |
982 | ||
983 | cmd->data[0] = devid; | |
e8d2d82d | 984 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
985 | cmd->data[0] |= (qdep & 0xff) << 24; |
986 | cmd->data[1] = devid; | |
e8d2d82d | 987 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
988 | cmd->data[2] = lower_32_bits(address); |
989 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
990 | cmd->data[3] = upper_32_bits(address); | |
991 | if (size) | |
992 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
993 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
994 | } | |
995 | ||
c99afa25 JR |
996 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
997 | int status, int tag, bool gn) | |
998 | { | |
999 | memset(cmd, 0, sizeof(*cmd)); | |
1000 | ||
1001 | cmd->data[0] = devid; | |
1002 | if (gn) { | |
a919a018 | 1003 | cmd->data[1] = pasid; |
c99afa25 JR |
1004 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
1005 | } | |
1006 | cmd->data[3] = tag & 0x1ff; | |
1007 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1008 | ||
1009 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1010 | } | |
1011 | ||
58fc7f14 JR |
1012 | static void build_inv_all(struct iommu_cmd *cmd) |
1013 | { | |
1014 | memset(cmd, 0, sizeof(*cmd)); | |
1015 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1016 | } |
1017 | ||
7ef2798d JR |
1018 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1019 | { | |
1020 | memset(cmd, 0, sizeof(*cmd)); | |
1021 | cmd->data[0] = devid; | |
1022 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1023 | } | |
1024 | ||
431b2a20 | 1025 | /* |
431b2a20 | 1026 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1027 | * hardware about the new command. |
431b2a20 | 1028 | */ |
4bf5beef JR |
1029 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1030 | struct iommu_cmd *cmd, | |
1031 | bool sync) | |
a19ae1ec | 1032 | { |
23e967e1 | 1033 | unsigned int count = 0; |
d334a563 | 1034 | u32 left, next_tail; |
a19ae1ec | 1035 | |
d334a563 | 1036 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 1037 | again: |
d334a563 | 1038 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 1039 | |
432abf68 | 1040 | if (left <= 0x20) { |
23e967e1 TL |
1041 | /* Skip udelay() the first time around */ |
1042 | if (count++) { | |
1043 | if (count == LOOP_TIMEOUT) { | |
101fa037 | 1044 | pr_err("Command buffer timeout\n"); |
23e967e1 TL |
1045 | return -EIO; |
1046 | } | |
da49f6df | 1047 | |
23e967e1 TL |
1048 | udelay(1); |
1049 | } | |
ac0ea6e9 | 1050 | |
23e967e1 TL |
1051 | /* Update head and recheck remaining space */ |
1052 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1053 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1054 | |
1055 | goto again; | |
8d201968 JR |
1056 | } |
1057 | ||
d334a563 | 1058 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1059 | |
23e967e1 | 1060 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1061 | iommu->need_sync = sync; |
ac0ea6e9 | 1062 | |
4bf5beef JR |
1063 | return 0; |
1064 | } | |
1065 | ||
1066 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1067 | struct iommu_cmd *cmd, | |
1068 | bool sync) | |
1069 | { | |
1070 | unsigned long flags; | |
1071 | int ret; | |
1072 | ||
27790398 | 1073 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef | 1074 | ret = __iommu_queue_command_sync(iommu, cmd, sync); |
27790398 | 1075 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1076 | |
4bf5beef | 1077 | return ret; |
8d201968 JR |
1078 | } |
1079 | ||
f1ca1512 JR |
1080 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1081 | { | |
1082 | return iommu_queue_command_sync(iommu, cmd, true); | |
1083 | } | |
1084 | ||
8d201968 JR |
1085 | /* |
1086 | * This function queues a completion wait command into the command | |
1087 | * buffer of an IOMMU | |
1088 | */ | |
a19ae1ec | 1089 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1090 | { |
1091 | struct iommu_cmd cmd; | |
4bf5beef | 1092 | unsigned long flags; |
ac0ea6e9 | 1093 | int ret; |
8d201968 | 1094 | |
09ee17eb | 1095 | if (!iommu->need_sync) |
815b33fd | 1096 | return 0; |
09ee17eb | 1097 | |
a19ae1ec | 1098 | |
4bf5beef JR |
1099 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1100 | ||
27790398 | 1101 | raw_spin_lock_irqsave(&iommu->lock, flags); |
4bf5beef JR |
1102 | |
1103 | iommu->cmd_sem = 0; | |
1104 | ||
1105 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1106 | if (ret) |
4bf5beef JR |
1107 | goto out_unlock; |
1108 | ||
1109 | ret = wait_on_sem(&iommu->cmd_sem); | |
1110 | ||
1111 | out_unlock: | |
27790398 | 1112 | raw_spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1113 | |
4bf5beef | 1114 | return ret; |
8d201968 JR |
1115 | } |
1116 | ||
d8c13085 | 1117 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1118 | { |
d8c13085 | 1119 | struct iommu_cmd cmd; |
a19ae1ec | 1120 | |
d8c13085 | 1121 | build_inv_dte(&cmd, devid); |
7e4f88da | 1122 | |
d8c13085 JR |
1123 | return iommu_queue_command(iommu, &cmd); |
1124 | } | |
09ee17eb | 1125 | |
0688a099 | 1126 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1127 | { |
1128 | u32 devid; | |
09ee17eb | 1129 | |
7d0c5cc5 JR |
1130 | for (devid = 0; devid <= 0xffff; ++devid) |
1131 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1132 | |
7d0c5cc5 JR |
1133 | iommu_completion_wait(iommu); |
1134 | } | |
84df8175 | 1135 | |
7d0c5cc5 JR |
1136 | /* |
1137 | * This function uses heavy locking and may disable irqs for some time. But | |
1138 | * this is no issue because it is only called during resume. | |
1139 | */ | |
0688a099 | 1140 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1141 | { |
1142 | u32 dom_id; | |
a19ae1ec | 1143 | |
7d0c5cc5 JR |
1144 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1145 | struct iommu_cmd cmd; | |
1146 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1147 | dom_id, 1); | |
1148 | iommu_queue_command(iommu, &cmd); | |
1149 | } | |
8eed9833 | 1150 | |
7d0c5cc5 | 1151 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1152 | } |
1153 | ||
0688a099 | 1154 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1155 | { |
58fc7f14 | 1156 | struct iommu_cmd cmd; |
0518a3a4 | 1157 | |
58fc7f14 | 1158 | build_inv_all(&cmd); |
0518a3a4 | 1159 | |
58fc7f14 JR |
1160 | iommu_queue_command(iommu, &cmd); |
1161 | iommu_completion_wait(iommu); | |
1162 | } | |
1163 | ||
7ef2798d JR |
1164 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1165 | { | |
1166 | struct iommu_cmd cmd; | |
1167 | ||
1168 | build_inv_irt(&cmd, devid); | |
1169 | ||
1170 | iommu_queue_command(iommu, &cmd); | |
1171 | } | |
1172 | ||
0688a099 | 1173 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1174 | { |
1175 | u32 devid; | |
1176 | ||
1177 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1178 | iommu_flush_irt(iommu, devid); | |
1179 | ||
1180 | iommu_completion_wait(iommu); | |
1181 | } | |
1182 | ||
7d0c5cc5 JR |
1183 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1184 | { | |
58fc7f14 | 1185 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1186 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1187 | } else { |
0688a099 JR |
1188 | amd_iommu_flush_dte_all(iommu); |
1189 | amd_iommu_flush_irt_all(iommu); | |
1190 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1191 | } |
1192 | } | |
1193 | ||
431b2a20 | 1194 | /* |
cb41ed85 | 1195 | * Command send function for flushing on-device TLB |
431b2a20 | 1196 | */ |
6c542047 JR |
1197 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1198 | u64 address, size_t size) | |
3fa43655 JR |
1199 | { |
1200 | struct amd_iommu *iommu; | |
b00d3bcf | 1201 | struct iommu_cmd cmd; |
cb41ed85 | 1202 | int qdep; |
3fa43655 | 1203 | |
ea61cddb JR |
1204 | qdep = dev_data->ats.qdep; |
1205 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1206 | |
ea61cddb | 1207 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1208 | |
1209 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1210 | } |
1211 | ||
431b2a20 | 1212 | /* |
431b2a20 | 1213 | * Command send function for invalidating a device table entry |
431b2a20 | 1214 | */ |
6c542047 | 1215 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1216 | { |
3fa43655 | 1217 | struct amd_iommu *iommu; |
e25bfb56 | 1218 | u16 alias; |
ee2fa743 | 1219 | int ret; |
a19ae1ec | 1220 | |
6c542047 | 1221 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1222 | alias = dev_data->alias; |
a19ae1ec | 1223 | |
f62dda66 | 1224 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1225 | if (!ret && alias != dev_data->devid) |
1226 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1227 | if (ret) |
1228 | return ret; | |
1229 | ||
ea61cddb | 1230 | if (dev_data->ats.enabled) |
6c542047 | 1231 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1232 | |
ee2fa743 | 1233 | return ret; |
a19ae1ec JR |
1234 | } |
1235 | ||
431b2a20 JR |
1236 | /* |
1237 | * TLB invalidation function which is called from the mapping functions. | |
1238 | * It invalidates a single PTE if the range to flush is within a single | |
1239 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1240 | */ | |
17b124bf JR |
1241 | static void __domain_flush_pages(struct protection_domain *domain, |
1242 | u64 address, size_t size, int pde) | |
a19ae1ec | 1243 | { |
cb41ed85 | 1244 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1245 | struct iommu_cmd cmd; |
1246 | int ret = 0, i; | |
a19ae1ec | 1247 | |
11b6402c | 1248 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1249 | |
6b9376e3 | 1250 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1251 | if (!domain->dev_iommu[i]) |
1252 | continue; | |
1253 | ||
1254 | /* | |
1255 | * Devices of this domain are behind this IOMMU | |
1256 | * We need a TLB flush | |
1257 | */ | |
11b6402c | 1258 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1259 | } |
1260 | ||
cb41ed85 | 1261 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1262 | |
ea61cddb | 1263 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1264 | continue; |
1265 | ||
6c542047 | 1266 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1267 | } |
1268 | ||
11b6402c | 1269 | WARN_ON(ret); |
6de8ad9b JR |
1270 | } |
1271 | ||
17b124bf JR |
1272 | static void domain_flush_pages(struct protection_domain *domain, |
1273 | u64 address, size_t size) | |
6de8ad9b | 1274 | { |
17b124bf | 1275 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1276 | } |
b6c02715 | 1277 | |
1c655773 | 1278 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1279 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1280 | { |
17b124bf | 1281 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1282 | } |
1283 | ||
42a49f96 | 1284 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1285 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1286 | { |
17b124bf | 1287 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1288 | } |
1289 | ||
17b124bf | 1290 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1291 | { |
17b124bf | 1292 | int i; |
18811f55 | 1293 | |
6b9376e3 | 1294 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1295 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1296 | continue; |
bfd1be18 | 1297 | |
17b124bf JR |
1298 | /* |
1299 | * Devices of this domain are behind this IOMMU | |
1300 | * We need to wait for completion of all commands. | |
1301 | */ | |
1302 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1303 | } |
e394d72a JR |
1304 | } |
1305 | ||
b00d3bcf | 1306 | |
09b42804 | 1307 | /* |
b00d3bcf | 1308 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1309 | */ |
17b124bf | 1310 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1311 | { |
b00d3bcf | 1312 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1313 | |
b00d3bcf | 1314 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1315 | device_flush_dte(dev_data); |
a345b23b JR |
1316 | } |
1317 | ||
431b2a20 JR |
1318 | /**************************************************************************** |
1319 | * | |
1320 | * The functions below are used the create the page table mappings for | |
1321 | * unity mapped regions. | |
1322 | * | |
1323 | ****************************************************************************/ | |
1324 | ||
ac3a7092 JR |
1325 | static void free_page_list(struct page *freelist) |
1326 | { | |
1327 | while (freelist != NULL) { | |
1328 | unsigned long p = (unsigned long)page_address(freelist); | |
1329 | freelist = freelist->freelist; | |
1330 | free_page(p); | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static struct page *free_pt_page(unsigned long pt, struct page *freelist) | |
1335 | { | |
1336 | struct page *p = virt_to_page((void *)pt); | |
1337 | ||
1338 | p->freelist = freelist; | |
1339 | ||
1340 | return p; | |
1341 | } | |
1342 | ||
1343 | #define DEFINE_FREE_PT_FN(LVL, FN) \ | |
1344 | static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \ | |
1345 | { \ | |
1346 | unsigned long p; \ | |
1347 | u64 *pt; \ | |
1348 | int i; \ | |
1349 | \ | |
1350 | pt = (u64 *)__pt; \ | |
1351 | \ | |
1352 | for (i = 0; i < 512; ++i) { \ | |
1353 | /* PTE present? */ \ | |
1354 | if (!IOMMU_PTE_PRESENT(pt[i])) \ | |
1355 | continue; \ | |
1356 | \ | |
1357 | /* Large PTE? */ \ | |
1358 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1359 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1360 | continue; \ | |
1361 | \ | |
1362 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ | |
1363 | freelist = FN(p, freelist); \ | |
1364 | } \ | |
1365 | \ | |
1366 | return free_pt_page((unsigned long)pt, freelist); \ | |
1367 | } | |
1368 | ||
1369 | DEFINE_FREE_PT_FN(l2, free_pt_page) | |
1370 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1371 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1372 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1373 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1374 | ||
409afa44 JR |
1375 | static struct page *free_sub_pt(unsigned long root, int mode, |
1376 | struct page *freelist) | |
ac3a7092 | 1377 | { |
409afa44 | 1378 | switch (mode) { |
ac3a7092 | 1379 | case PAGE_MODE_NONE: |
69be8852 | 1380 | case PAGE_MODE_7_LEVEL: |
ac3a7092 JR |
1381 | break; |
1382 | case PAGE_MODE_1_LEVEL: | |
1383 | freelist = free_pt_page(root, freelist); | |
1384 | break; | |
1385 | case PAGE_MODE_2_LEVEL: | |
1386 | freelist = free_pt_l2(root, freelist); | |
1387 | break; | |
1388 | case PAGE_MODE_3_LEVEL: | |
1389 | freelist = free_pt_l3(root, freelist); | |
1390 | break; | |
1391 | case PAGE_MODE_4_LEVEL: | |
1392 | freelist = free_pt_l4(root, freelist); | |
1393 | break; | |
1394 | case PAGE_MODE_5_LEVEL: | |
1395 | freelist = free_pt_l5(root, freelist); | |
1396 | break; | |
1397 | case PAGE_MODE_6_LEVEL: | |
1398 | freelist = free_pt_l6(root, freelist); | |
1399 | break; | |
1400 | default: | |
1401 | BUG(); | |
1402 | } | |
1403 | ||
409afa44 JR |
1404 | return freelist; |
1405 | } | |
1406 | ||
1407 | static void free_pagetable(struct protection_domain *domain) | |
1408 | { | |
1409 | unsigned long root = (unsigned long)domain->pt_root; | |
1410 | struct page *freelist = NULL; | |
1411 | ||
69be8852 JR |
1412 | BUG_ON(domain->mode < PAGE_MODE_NONE || |
1413 | domain->mode > PAGE_MODE_6_LEVEL); | |
1414 | ||
409afa44 JR |
1415 | free_sub_pt(root, domain->mode, freelist); |
1416 | ||
ac3a7092 JR |
1417 | free_page_list(freelist); |
1418 | } | |
1419 | ||
308973d3 JR |
1420 | /* |
1421 | * This function is used to add another level to an IO page table. Adding | |
1422 | * another level increases the size of the address space by 9 bits to a size up | |
1423 | * to 64 bits. | |
1424 | */ | |
1425 | static bool increase_address_space(struct protection_domain *domain, | |
1426 | gfp_t gfp) | |
1427 | { | |
1428 | u64 *pte; | |
1429 | ||
1430 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1431 | /* address space already 64 bit large */ | |
1432 | return false; | |
1433 | ||
1434 | pte = (void *)get_zeroed_page(gfp); | |
1435 | if (!pte) | |
1436 | return false; | |
1437 | ||
1438 | *pte = PM_LEVEL_PDE(domain->mode, | |
2543a786 | 1439 | iommu_virt_to_phys(domain->pt_root)); |
308973d3 JR |
1440 | domain->pt_root = pte; |
1441 | domain->mode += 1; | |
1442 | domain->updated = true; | |
1443 | ||
1444 | return true; | |
1445 | } | |
1446 | ||
1447 | static u64 *alloc_pte(struct protection_domain *domain, | |
1448 | unsigned long address, | |
cbb9d729 | 1449 | unsigned long page_size, |
308973d3 JR |
1450 | u64 **pte_page, |
1451 | gfp_t gfp) | |
1452 | { | |
cbb9d729 | 1453 | int level, end_lvl; |
308973d3 | 1454 | u64 *pte, *page; |
cbb9d729 JR |
1455 | |
1456 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1457 | |
1458 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1459 | increase_address_space(domain, gfp); | |
1460 | ||
cbb9d729 JR |
1461 | level = domain->mode - 1; |
1462 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1463 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1464 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1465 | |
1466 | while (level > end_lvl) { | |
7bfa5bd2 | 1467 | u64 __pte, __npte; |
6d568ef9 | 1468 | int pte_level; |
7bfa5bd2 | 1469 | |
6d568ef9 JR |
1470 | __pte = *pte; |
1471 | pte_level = PM_PTE_LEVEL(__pte); | |
7bfa5bd2 | 1472 | |
6d568ef9 JR |
1473 | if (!IOMMU_PTE_PRESENT(__pte) || |
1474 | pte_level == PAGE_MODE_7_LEVEL) { | |
308973d3 JR |
1475 | page = (u64 *)get_zeroed_page(gfp); |
1476 | if (!page) | |
1477 | return NULL; | |
7bfa5bd2 | 1478 | |
2543a786 | 1479 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
7bfa5bd2 | 1480 | |
134414ff | 1481 | /* pte could have been changed somewhere. */ |
9db034d5 | 1482 | if (cmpxchg64(pte, __pte, __npte) != __pte) |
7bfa5bd2 | 1483 | free_page((unsigned long)page); |
9db034d5 | 1484 | else if (pte_level == PAGE_MODE_7_LEVEL) |
6d568ef9 | 1485 | domain->updated = true; |
9db034d5 JR |
1486 | |
1487 | continue; | |
308973d3 JR |
1488 | } |
1489 | ||
cbb9d729 | 1490 | /* No level skipping support yet */ |
6d568ef9 | 1491 | if (pte_level != level) |
cbb9d729 JR |
1492 | return NULL; |
1493 | ||
308973d3 JR |
1494 | level -= 1; |
1495 | ||
9db034d5 | 1496 | pte = IOMMU_PTE_PAGE(__pte); |
308973d3 JR |
1497 | |
1498 | if (pte_page && level == end_lvl) | |
1499 | *pte_page = pte; | |
1500 | ||
1501 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1502 | } | |
1503 | ||
1504 | return pte; | |
1505 | } | |
1506 | ||
1507 | /* | |
1508 | * This function checks if there is a PTE for a given dma address. If | |
1509 | * there is one, it returns the pointer to it. | |
1510 | */ | |
3039ca1b JR |
1511 | static u64 *fetch_pte(struct protection_domain *domain, |
1512 | unsigned long address, | |
1513 | unsigned long *page_size) | |
308973d3 JR |
1514 | { |
1515 | int level; | |
1516 | u64 *pte; | |
1517 | ||
4674686d | 1518 | *page_size = 0; |
1519 | ||
24cd7723 JR |
1520 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1521 | return NULL; | |
1522 | ||
3039ca1b JR |
1523 | level = domain->mode - 1; |
1524 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1525 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1526 | |
24cd7723 JR |
1527 | while (level > 0) { |
1528 | ||
1529 | /* Not Present */ | |
308973d3 JR |
1530 | if (!IOMMU_PTE_PRESENT(*pte)) |
1531 | return NULL; | |
1532 | ||
24cd7723 | 1533 | /* Large PTE */ |
3039ca1b JR |
1534 | if (PM_PTE_LEVEL(*pte) == 7 || |
1535 | PM_PTE_LEVEL(*pte) == 0) | |
1536 | break; | |
24cd7723 JR |
1537 | |
1538 | /* No level skipping support yet */ | |
1539 | if (PM_PTE_LEVEL(*pte) != level) | |
1540 | return NULL; | |
1541 | ||
308973d3 JR |
1542 | level -= 1; |
1543 | ||
24cd7723 | 1544 | /* Walk to the next level */ |
3039ca1b JR |
1545 | pte = IOMMU_PTE_PAGE(*pte); |
1546 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1547 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1548 | } | |
1549 | ||
1550 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1551 | unsigned long pte_mask; | |
1552 | ||
1553 | /* | |
1554 | * If we have a series of large PTEs, make | |
1555 | * sure to return a pointer to the first one. | |
1556 | */ | |
1557 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1558 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1559 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1560 | } |
1561 | ||
1562 | return pte; | |
1563 | } | |
1564 | ||
6f820bb9 JR |
1565 | static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist) |
1566 | { | |
1567 | unsigned long pt; | |
1568 | int mode; | |
1569 | ||
1570 | while (cmpxchg64(pte, pteval, 0) != pteval) { | |
1571 | pr_warn("AMD-Vi: IOMMU pte changed since we read it\n"); | |
1572 | pteval = *pte; | |
1573 | } | |
1574 | ||
1575 | if (!IOMMU_PTE_PRESENT(pteval)) | |
1576 | return freelist; | |
1577 | ||
1578 | pt = (unsigned long)IOMMU_PTE_PAGE(pteval); | |
1579 | mode = IOMMU_PTE_MODE(pteval); | |
1580 | ||
1581 | return free_sub_pt(pt, mode, freelist); | |
1582 | } | |
1583 | ||
431b2a20 JR |
1584 | /* |
1585 | * Generic mapping functions. It maps a physical address into a DMA | |
1586 | * address space. It allocates the page table pages if necessary. | |
1587 | * In the future it can be extended to a generic mapping function | |
1588 | * supporting all features of AMD IOMMU page tables like level skipping | |
1589 | * and full 64 bit address spaces. | |
1590 | */ | |
38e817fe JR |
1591 | static int iommu_map_page(struct protection_domain *dom, |
1592 | unsigned long bus_addr, | |
1593 | unsigned long phys_addr, | |
b911b89b | 1594 | unsigned long page_size, |
abdc5eb3 | 1595 | int prot, |
b911b89b | 1596 | gfp_t gfp) |
bd0e5211 | 1597 | { |
6f820bb9 | 1598 | struct page *freelist = NULL; |
8bda3092 | 1599 | u64 __pte, *pte; |
cbb9d729 | 1600 | int i, count; |
abdc5eb3 | 1601 | |
d4b03664 JR |
1602 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1603 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1604 | ||
bad1cac2 | 1605 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1606 | return -EINVAL; |
1607 | ||
d4b03664 | 1608 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1609 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1610 | |
63eaa75e ML |
1611 | if (!pte) |
1612 | return -ENOMEM; | |
1613 | ||
cbb9d729 | 1614 | for (i = 0; i < count; ++i) |
6f820bb9 JR |
1615 | freelist = free_clear_pte(&pte[i], pte[i], freelist); |
1616 | ||
1617 | if (freelist != NULL) | |
1618 | dom->updated = true; | |
bd0e5211 | 1619 | |
d4b03664 | 1620 | if (count > 1) { |
2543a786 | 1621 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
07a80a6b | 1622 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
cbb9d729 | 1623 | } else |
4dfc2788 | 1624 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
bd0e5211 | 1625 | |
bd0e5211 JR |
1626 | if (prot & IOMMU_PROT_IR) |
1627 | __pte |= IOMMU_PTE_IR; | |
1628 | if (prot & IOMMU_PROT_IW) | |
1629 | __pte |= IOMMU_PTE_IW; | |
1630 | ||
cbb9d729 JR |
1631 | for (i = 0; i < count; ++i) |
1632 | pte[i] = __pte; | |
bd0e5211 | 1633 | |
04bfdd84 JR |
1634 | update_domain(dom); |
1635 | ||
6f820bb9 JR |
1636 | /* Everything flushed out, free pages now */ |
1637 | free_page_list(freelist); | |
1638 | ||
bd0e5211 JR |
1639 | return 0; |
1640 | } | |
1641 | ||
24cd7723 JR |
1642 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1643 | unsigned long bus_addr, | |
1644 | unsigned long page_size) | |
eb74ff6c | 1645 | { |
71b390e9 JR |
1646 | unsigned long long unmapped; |
1647 | unsigned long unmap_size; | |
24cd7723 JR |
1648 | u64 *pte; |
1649 | ||
1650 | BUG_ON(!is_power_of_2(page_size)); | |
1651 | ||
1652 | unmapped = 0; | |
eb74ff6c | 1653 | |
24cd7723 JR |
1654 | while (unmapped < page_size) { |
1655 | ||
71b390e9 JR |
1656 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1657 | ||
1658 | if (pte) { | |
1659 | int i, count; | |
1660 | ||
1661 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1662 | for (i = 0; i < count; i++) |
1663 | pte[i] = 0ULL; | |
1664 | } | |
1665 | ||
1666 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1667 | unmapped += unmap_size; | |
1668 | } | |
1669 | ||
60d0ca3c | 1670 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1671 | |
24cd7723 | 1672 | return unmapped; |
eb74ff6c | 1673 | } |
eb74ff6c | 1674 | |
431b2a20 JR |
1675 | /**************************************************************************** |
1676 | * | |
1677 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1678 | * interface functions. |
431b2a20 JR |
1679 | * |
1680 | ****************************************************************************/ | |
d3086444 | 1681 | |
9cabe89b | 1682 | |
256e4621 JR |
1683 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1684 | struct dma_ops_domain *dma_dom, | |
1685 | unsigned int pages, u64 dma_mask) | |
384de729 | 1686 | { |
256e4621 | 1687 | unsigned long pfn = 0; |
384de729 | 1688 | |
256e4621 | 1689 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1690 | |
256e4621 JR |
1691 | if (dma_mask > DMA_BIT_MASK(32)) |
1692 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
538d5b33 | 1693 | IOVA_PFN(DMA_BIT_MASK(32)), false); |
7b5e25b8 | 1694 | |
256e4621 | 1695 | if (!pfn) |
538d5b33 TN |
1696 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
1697 | IOVA_PFN(dma_mask), true); | |
5f6bed50 | 1698 | |
256e4621 | 1699 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1700 | } |
1701 | ||
256e4621 JR |
1702 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1703 | unsigned long address, | |
1704 | unsigned int pages) | |
d3086444 | 1705 | { |
256e4621 JR |
1706 | pages = __roundup_pow_of_two(pages); |
1707 | address >>= PAGE_SHIFT; | |
384de729 | 1708 | |
256e4621 | 1709 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1710 | } |
1711 | ||
431b2a20 JR |
1712 | /**************************************************************************** |
1713 | * | |
1714 | * The next functions belong to the domain allocation. A domain is | |
1715 | * allocated for every IOMMU as the default domain. If device isolation | |
1716 | * is enabled, every device get its own domain. The most important thing | |
1717 | * about domains is the page table mapping the DMA address space they | |
1718 | * contain. | |
1719 | * | |
1720 | ****************************************************************************/ | |
1721 | ||
aeb26f55 JR |
1722 | /* |
1723 | * This function adds a protection domain to the global protection domain list | |
1724 | */ | |
1725 | static void add_domain_to_list(struct protection_domain *domain) | |
1726 | { | |
1727 | unsigned long flags; | |
1728 | ||
1729 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1730 | list_add(&domain->list, &amd_iommu_pd_list); | |
1731 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1732 | } | |
1733 | ||
1734 | /* | |
1735 | * This function removes a protection domain to the global | |
1736 | * protection domain list | |
1737 | */ | |
1738 | static void del_domain_from_list(struct protection_domain *domain) | |
1739 | { | |
1740 | unsigned long flags; | |
1741 | ||
1742 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1743 | list_del(&domain->list); | |
1744 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1745 | } | |
1746 | ||
ec487d1a JR |
1747 | static u16 domain_id_alloc(void) |
1748 | { | |
ec487d1a JR |
1749 | int id; |
1750 | ||
2bc00180 | 1751 | spin_lock(&pd_bitmap_lock); |
ec487d1a JR |
1752 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); |
1753 | BUG_ON(id == 0); | |
1754 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1755 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1756 | else | |
1757 | id = 0; | |
2bc00180 | 1758 | spin_unlock(&pd_bitmap_lock); |
ec487d1a JR |
1759 | |
1760 | return id; | |
1761 | } | |
1762 | ||
a2acfb75 JR |
1763 | static void domain_id_free(int id) |
1764 | { | |
2bc00180 | 1765 | spin_lock(&pd_bitmap_lock); |
a2acfb75 JR |
1766 | if (id > 0 && id < MAX_DOMAIN_ID) |
1767 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
2bc00180 | 1768 | spin_unlock(&pd_bitmap_lock); |
a2acfb75 | 1769 | } |
a2acfb75 | 1770 | |
b16137b1 JR |
1771 | static void free_gcr3_tbl_level1(u64 *tbl) |
1772 | { | |
1773 | u64 *ptr; | |
1774 | int i; | |
1775 | ||
1776 | for (i = 0; i < 512; ++i) { | |
1777 | if (!(tbl[i] & GCR3_VALID)) | |
1778 | continue; | |
1779 | ||
2543a786 | 1780 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1781 | |
1782 | free_page((unsigned long)ptr); | |
1783 | } | |
1784 | } | |
1785 | ||
1786 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1787 | { | |
1788 | u64 *ptr; | |
1789 | int i; | |
1790 | ||
1791 | for (i = 0; i < 512; ++i) { | |
1792 | if (!(tbl[i] & GCR3_VALID)) | |
1793 | continue; | |
1794 | ||
2543a786 | 1795 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1796 | |
1797 | free_gcr3_tbl_level1(ptr); | |
1798 | } | |
1799 | } | |
1800 | ||
52815b75 JR |
1801 | static void free_gcr3_table(struct protection_domain *domain) |
1802 | { | |
b16137b1 JR |
1803 | if (domain->glx == 2) |
1804 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1805 | else if (domain->glx == 1) | |
1806 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1807 | else |
1808 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1809 | |
52815b75 JR |
1810 | free_page((unsigned long)domain->gcr3_tbl); |
1811 | } | |
1812 | ||
fca6af6a JR |
1813 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) |
1814 | { | |
fca6af6a JR |
1815 | domain_flush_tlb(&dom->domain); |
1816 | domain_flush_complete(&dom->domain); | |
fd62190a JR |
1817 | } |
1818 | ||
9003d618 | 1819 | static void iova_domain_flush_tlb(struct iova_domain *iovad) |
fd62190a | 1820 | { |
9003d618 | 1821 | struct dma_ops_domain *dom; |
fd62190a | 1822 | |
9003d618 | 1823 | dom = container_of(iovad, struct dma_ops_domain, iovad); |
fca6af6a JR |
1824 | |
1825 | dma_ops_domain_flush_tlb(dom); | |
fca6af6a JR |
1826 | } |
1827 | ||
431b2a20 JR |
1828 | /* |
1829 | * Free a domain, only used if something went wrong in the | |
1830 | * allocation path and we need to free an already allocated page table | |
1831 | */ | |
ec487d1a JR |
1832 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1833 | { | |
1834 | if (!dom) | |
1835 | return; | |
1836 | ||
aeb26f55 JR |
1837 | del_domain_from_list(&dom->domain); |
1838 | ||
2d4c515b | 1839 | put_iova_domain(&dom->iovad); |
ec487d1a | 1840 | |
2d4c515b | 1841 | free_pagetable(&dom->domain); |
ec487d1a | 1842 | |
c3db901c BH |
1843 | if (dom->domain.id) |
1844 | domain_id_free(dom->domain.id); | |
1845 | ||
ec487d1a JR |
1846 | kfree(dom); |
1847 | } | |
1848 | ||
431b2a20 JR |
1849 | /* |
1850 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1851 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1852 | * structures required for the dma_ops interface |
1853 | */ | |
87a64d52 | 1854 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1855 | { |
1856 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1857 | |
1858 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1859 | if (!dma_dom) | |
1860 | return NULL; | |
1861 | ||
7a5a566e | 1862 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1863 | goto free_dma_dom; |
7a5a566e | 1864 | |
ffec2197 | 1865 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1866 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1867 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1868 | if (!dma_dom->domain.pt_root) |
1869 | goto free_dma_dom; | |
ec487d1a | 1870 | |
aa3ac946 | 1871 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN); |
307d5851 | 1872 | |
9003d618 | 1873 | if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL)) |
d4241a27 JR |
1874 | goto free_dma_dom; |
1875 | ||
9003d618 JR |
1876 | /* Initialize reserved ranges */ |
1877 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
fca6af6a | 1878 | |
2d4c515b JR |
1879 | add_domain_to_list(&dma_dom->domain); |
1880 | ||
ec487d1a JR |
1881 | return dma_dom; |
1882 | ||
1883 | free_dma_dom: | |
1884 | dma_ops_domain_free(dma_dom); | |
1885 | ||
1886 | return NULL; | |
1887 | } | |
1888 | ||
5b28df6f JR |
1889 | /* |
1890 | * little helper function to check whether a given protection domain is a | |
1891 | * dma_ops domain | |
1892 | */ | |
1893 | static bool dma_ops_domain(struct protection_domain *domain) | |
1894 | { | |
1895 | return domain->flags & PD_DMA_OPS_MASK; | |
1896 | } | |
1897 | ||
ff18c4e5 GH |
1898 | static void set_dte_entry(u16 devid, struct protection_domain *domain, |
1899 | bool ats, bool ppr) | |
b20ac0d4 | 1900 | { |
132bd68f | 1901 | u64 pte_root = 0; |
ee6c2868 | 1902 | u64 flags = 0; |
863c74eb | 1903 | |
132bd68f | 1904 | if (domain->mode != PAGE_MODE_NONE) |
2543a786 | 1905 | pte_root = iommu_virt_to_phys(domain->pt_root); |
132bd68f | 1906 | |
38ddf41b JR |
1907 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1908 | << DEV_ENTRY_MODE_SHIFT; | |
07a80a6b | 1909 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
b20ac0d4 | 1910 | |
ee6c2868 JR |
1911 | flags = amd_iommu_dev_table[devid].data[1]; |
1912 | ||
fd7b5535 JR |
1913 | if (ats) |
1914 | flags |= DTE_FLAG_IOTLB; | |
1915 | ||
ff18c4e5 GH |
1916 | if (ppr) { |
1917 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1918 | ||
1919 | if (iommu_feature(iommu, FEATURE_EPHSUP)) | |
1920 | pte_root |= 1ULL << DEV_ENTRY_PPR; | |
1921 | } | |
1922 | ||
52815b75 | 1923 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1924 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1925 | u64 glx = domain->glx; |
1926 | u64 tmp; | |
1927 | ||
1928 | pte_root |= DTE_FLAG_GV; | |
1929 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1930 | ||
1931 | /* First mask out possible old values for GCR3 table */ | |
1932 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1933 | flags &= ~tmp; | |
1934 | ||
1935 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1936 | flags &= ~tmp; | |
1937 | ||
1938 | /* Encode GCR3 table into DTE */ | |
1939 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1940 | pte_root |= tmp; | |
1941 | ||
1942 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1943 | flags |= tmp; | |
1944 | ||
1945 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1946 | flags |= tmp; | |
1947 | } | |
1948 | ||
45a01c42 | 1949 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1950 | flags |= domain->id; |
1951 | ||
1952 | amd_iommu_dev_table[devid].data[1] = flags; | |
1953 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1954 | } |
1955 | ||
1956 | static void clear_dte_entry(u16 devid) | |
1957 | { | |
15898bbc | 1958 | /* remove entry from the device table seen by the hardware */ |
07a80a6b | 1959 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
cbf3ccd0 | 1960 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc JR |
1961 | |
1962 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1963 | } |
1964 | ||
ec9e79ef JR |
1965 | static void do_attach(struct iommu_dev_data *dev_data, |
1966 | struct protection_domain *domain) | |
7f760ddd | 1967 | { |
7f760ddd | 1968 | struct amd_iommu *iommu; |
e25bfb56 | 1969 | u16 alias; |
ec9e79ef | 1970 | bool ats; |
fd7b5535 | 1971 | |
ec9e79ef | 1972 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1973 | alias = dev_data->alias; |
ec9e79ef | 1974 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1975 | |
1976 | /* Update data structures */ | |
1977 | dev_data->domain = domain; | |
1978 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1979 | |
1980 | /* Do reference counting */ | |
1981 | domain->dev_iommu[iommu->index] += 1; | |
1982 | domain->dev_cnt += 1; | |
1983 | ||
e25bfb56 | 1984 | /* Update device table */ |
ff18c4e5 | 1985 | set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1986 | if (alias != dev_data->devid) |
ff18c4e5 | 1987 | set_dte_entry(alias, domain, ats, dev_data->iommu_v2); |
e25bfb56 | 1988 | |
6c542047 | 1989 | device_flush_dte(dev_data); |
7f760ddd JR |
1990 | } |
1991 | ||
ec9e79ef | 1992 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1993 | { |
9825bd94 | 1994 | struct protection_domain *domain = dev_data->domain; |
7f760ddd | 1995 | struct amd_iommu *iommu; |
e25bfb56 | 1996 | u16 alias; |
7f760ddd | 1997 | |
ec9e79ef | 1998 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1999 | alias = dev_data->alias; |
15898bbc | 2000 | |
7f760ddd JR |
2001 | /* Update data structures */ |
2002 | dev_data->domain = NULL; | |
2003 | list_del(&dev_data->list); | |
f62dda66 | 2004 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
2005 | if (alias != dev_data->devid) |
2006 | clear_dte_entry(alias); | |
15898bbc | 2007 | |
7f760ddd | 2008 | /* Flush the DTE entry */ |
6c542047 | 2009 | device_flush_dte(dev_data); |
9825bd94 SS |
2010 | |
2011 | /* Flush IOTLB */ | |
2012 | domain_flush_tlb_pde(domain); | |
2013 | ||
2014 | /* Wait for the flushes to finish */ | |
2015 | domain_flush_complete(domain); | |
2016 | ||
2017 | /* decrease reference counters - needs to happen after the flushes */ | |
2018 | domain->dev_iommu[iommu->index] -= 1; | |
2019 | domain->dev_cnt -= 1; | |
2b681faf JR |
2020 | } |
2021 | ||
2022 | /* | |
29a0c415 AMG |
2023 | * If a device is not yet associated with a domain, this function makes the |
2024 | * device visible in the domain | |
2b681faf | 2025 | */ |
ec9e79ef | 2026 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2027 | struct protection_domain *domain) |
2b681faf | 2028 | { |
84fe6c19 | 2029 | int ret; |
657cbb6b | 2030 | |
2b681faf JR |
2031 | /* lock domain */ |
2032 | spin_lock(&domain->lock); | |
2033 | ||
397111ab | 2034 | ret = -EBUSY; |
150952f9 | 2035 | if (dev_data->domain != NULL) |
397111ab | 2036 | goto out_unlock; |
15898bbc | 2037 | |
397111ab | 2038 | /* Attach alias group root */ |
150952f9 | 2039 | do_attach(dev_data, domain); |
24100055 | 2040 | |
84fe6c19 JL |
2041 | ret = 0; |
2042 | ||
2043 | out_unlock: | |
2044 | ||
eba6ac60 JR |
2045 | /* ready */ |
2046 | spin_unlock(&domain->lock); | |
15898bbc | 2047 | |
84fe6c19 | 2048 | return ret; |
0feae533 | 2049 | } |
b20ac0d4 | 2050 | |
52815b75 JR |
2051 | |
2052 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2053 | { | |
2054 | pci_disable_ats(pdev); | |
2055 | pci_disable_pri(pdev); | |
2056 | pci_disable_pasid(pdev); | |
2057 | } | |
2058 | ||
6a113ddc JR |
2059 | /* FIXME: Change generic reset-function to do the same */ |
2060 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2061 | { | |
2062 | u16 control; | |
2063 | int pos; | |
2064 | ||
46277b75 | 2065 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2066 | if (!pos) |
2067 | return -EINVAL; | |
2068 | ||
46277b75 JR |
2069 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2070 | control |= PCI_PRI_CTRL_RESET; | |
2071 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2072 | |
2073 | return 0; | |
2074 | } | |
2075 | ||
52815b75 JR |
2076 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2077 | { | |
6a113ddc JR |
2078 | bool reset_enable; |
2079 | int reqs, ret; | |
2080 | ||
2081 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2082 | reqs = 32; | |
2083 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2084 | reqs = 1; | |
2085 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2086 | |
2087 | /* Only allow access to user-accessible pages */ | |
2088 | ret = pci_enable_pasid(pdev, 0); | |
2089 | if (ret) | |
2090 | goto out_err; | |
2091 | ||
2092 | /* First reset the PRI state of the device */ | |
2093 | ret = pci_reset_pri(pdev); | |
2094 | if (ret) | |
2095 | goto out_err; | |
2096 | ||
6a113ddc JR |
2097 | /* Enable PRI */ |
2098 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2099 | if (ret) |
2100 | goto out_err; | |
2101 | ||
6a113ddc JR |
2102 | if (reset_enable) { |
2103 | ret = pri_reset_while_enabled(pdev); | |
2104 | if (ret) | |
2105 | goto out_err; | |
2106 | } | |
2107 | ||
52815b75 JR |
2108 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2109 | if (ret) | |
2110 | goto out_err; | |
2111 | ||
2112 | return 0; | |
2113 | ||
2114 | out_err: | |
2115 | pci_disable_pri(pdev); | |
2116 | pci_disable_pasid(pdev); | |
2117 | ||
2118 | return ret; | |
2119 | } | |
2120 | ||
c99afa25 | 2121 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2122 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2123 | |
98f1ad25 | 2124 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2125 | { |
a3b93121 | 2126 | u16 status; |
c99afa25 JR |
2127 | int pos; |
2128 | ||
46277b75 | 2129 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2130 | if (!pos) |
2131 | return false; | |
2132 | ||
a3b93121 | 2133 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2134 | |
a3b93121 | 2135 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2136 | } |
2137 | ||
407d733e | 2138 | /* |
29a0c415 AMG |
2139 | * If a device is not yet associated with a domain, this function makes the |
2140 | * device visible in the domain | |
407d733e | 2141 | */ |
15898bbc JR |
2142 | static int attach_device(struct device *dev, |
2143 | struct protection_domain *domain) | |
0feae533 | 2144 | { |
2bf9a0a1 | 2145 | struct pci_dev *pdev; |
ea61cddb | 2146 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2147 | unsigned long flags; |
15898bbc | 2148 | int ret; |
eba6ac60 | 2149 | |
ea61cddb JR |
2150 | dev_data = get_dev_data(dev); |
2151 | ||
2bf9a0a1 WZ |
2152 | if (!dev_is_pci(dev)) |
2153 | goto skip_ats_check; | |
2154 | ||
2155 | pdev = to_pci_dev(dev); | |
52815b75 | 2156 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2157 | if (!dev_data->passthrough) |
52815b75 JR |
2158 | return -EINVAL; |
2159 | ||
02ca2021 JR |
2160 | if (dev_data->iommu_v2) { |
2161 | if (pdev_iommuv2_enable(pdev) != 0) | |
2162 | return -EINVAL; | |
52815b75 | 2163 | |
02ca2021 JR |
2164 | dev_data->ats.enabled = true; |
2165 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2166 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2167 | } | |
52815b75 JR |
2168 | } else if (amd_iommu_iotlb_sup && |
2169 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2170 | dev_data->ats.enabled = true; |
2171 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2172 | } | |
fd7b5535 | 2173 | |
2bf9a0a1 | 2174 | skip_ats_check: |
2cd1083d | 2175 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2176 | ret = __attach_device(dev_data, domain); |
2cd1083d | 2177 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
b20ac0d4 | 2178 | |
0feae533 JR |
2179 | /* |
2180 | * We might boot into a crash-kernel here. The crashed kernel | |
2181 | * left the caches in the IOMMU dirty. So we have to flush | |
2182 | * here to evict all dirty stuff. | |
2183 | */ | |
17b124bf | 2184 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2185 | |
2186 | return ret; | |
b20ac0d4 JR |
2187 | } |
2188 | ||
355bf553 JR |
2189 | /* |
2190 | * Removes a device from a protection domain (unlocked) | |
2191 | */ | |
ec9e79ef | 2192 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2193 | { |
2ca76279 | 2194 | struct protection_domain *domain; |
c4596114 | 2195 | |
2ca76279 | 2196 | domain = dev_data->domain; |
71f77580 | 2197 | |
f1dd0a8b | 2198 | spin_lock(&domain->lock); |
24100055 | 2199 | |
150952f9 | 2200 | do_detach(dev_data); |
7f760ddd | 2201 | |
f1dd0a8b | 2202 | spin_unlock(&domain->lock); |
355bf553 JR |
2203 | } |
2204 | ||
2205 | /* | |
2206 | * Removes a device from a protection domain (with devtable_lock held) | |
2207 | */ | |
15898bbc | 2208 | static void detach_device(struct device *dev) |
355bf553 | 2209 | { |
52815b75 | 2210 | struct protection_domain *domain; |
ea61cddb | 2211 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2212 | unsigned long flags; |
2213 | ||
ec9e79ef | 2214 | dev_data = get_dev_data(dev); |
52815b75 | 2215 | domain = dev_data->domain; |
ec9e79ef | 2216 | |
ea3fd040 AMG |
2217 | /* |
2218 | * First check if the device is still attached. It might already | |
2219 | * be detached from its domain because the generic | |
2220 | * iommu_detach_group code detached it and we try again here in | |
2221 | * our alias handling. | |
2222 | */ | |
2223 | if (WARN_ON(!dev_data->domain)) | |
2224 | return; | |
2225 | ||
355bf553 | 2226 | /* lock device table */ |
2cd1083d | 2227 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2228 | __detach_device(dev_data); |
2cd1083d | 2229 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2230 | |
2bf9a0a1 WZ |
2231 | if (!dev_is_pci(dev)) |
2232 | return; | |
2233 | ||
02ca2021 | 2234 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2235 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2236 | else if (dev_data->ats.enabled) | |
ea61cddb | 2237 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2238 | |
2239 | dev_data->ats.enabled = false; | |
355bf553 | 2240 | } |
e275a2a0 | 2241 | |
aafd8ba0 | 2242 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2243 | { |
5abcdba4 | 2244 | struct iommu_dev_data *dev_data; |
07ee8694 | 2245 | struct iommu_domain *domain; |
e275a2a0 | 2246 | struct amd_iommu *iommu; |
7aba6cb9 | 2247 | int ret, devid; |
e275a2a0 | 2248 | |
aafd8ba0 | 2249 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2250 | return 0; |
e275a2a0 | 2251 | |
aafd8ba0 | 2252 | devid = get_device_id(dev); |
9ee35e4c | 2253 | if (devid < 0) |
7aba6cb9 WZ |
2254 | return devid; |
2255 | ||
aafd8ba0 | 2256 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2257 | |
aafd8ba0 | 2258 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2259 | if (ret) { |
2260 | if (ret != -ENOTSUPP) | |
2261 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2262 | dev_name(dev)); | |
657cbb6b | 2263 | |
aafd8ba0 | 2264 | iommu_ignore_device(dev); |
356da6d0 | 2265 | dev->dma_ops = NULL; |
aafd8ba0 JR |
2266 | goto out; |
2267 | } | |
2268 | init_iommu_group(dev); | |
2c9195e9 | 2269 | |
07ee8694 | 2270 | dev_data = get_dev_data(dev); |
2c9195e9 | 2271 | |
4d58b8a6 | 2272 | BUG_ON(!dev_data); |
657cbb6b | 2273 | |
1e6a7b04 | 2274 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2275 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2276 | |
07ee8694 JR |
2277 | /* Domains are initialized for this device - have a look what we ended up with */ |
2278 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2279 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2280 | dev_data->passthrough = true; |
32302324 | 2281 | else |
5657933d | 2282 | dev->dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2283 | |
aafd8ba0 | 2284 | out: |
e275a2a0 JR |
2285 | iommu_completion_wait(iommu); |
2286 | ||
e275a2a0 JR |
2287 | return 0; |
2288 | } | |
2289 | ||
aafd8ba0 | 2290 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2291 | { |
aafd8ba0 | 2292 | struct amd_iommu *iommu; |
7aba6cb9 | 2293 | int devid; |
aafd8ba0 JR |
2294 | |
2295 | if (!check_device(dev)) | |
2296 | return; | |
2297 | ||
2298 | devid = get_device_id(dev); | |
9ee35e4c | 2299 | if (devid < 0) |
7aba6cb9 WZ |
2300 | return; |
2301 | ||
aafd8ba0 JR |
2302 | iommu = amd_iommu_rlookup_table[devid]; |
2303 | ||
2304 | iommu_uninit_device(dev); | |
2305 | iommu_completion_wait(iommu); | |
8638c491 JR |
2306 | } |
2307 | ||
b097d11a WZ |
2308 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2309 | { | |
2310 | if (dev_is_pci(dev)) | |
2311 | return pci_device_group(dev); | |
2312 | ||
2313 | return acpihid_device_group(dev); | |
2314 | } | |
2315 | ||
431b2a20 JR |
2316 | /***************************************************************************** |
2317 | * | |
2318 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2319 | * | |
2320 | *****************************************************************************/ | |
2321 | ||
2322 | /* | |
2323 | * In the dma_ops path we only have the struct device. This function | |
2324 | * finds the corresponding IOMMU, the protection domain and the | |
2325 | * requestor id for a given device. | |
2326 | * If the device is not yet associated with a domain this is also done | |
2327 | * in this function. | |
2328 | */ | |
94f6d190 | 2329 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2330 | { |
94f6d190 | 2331 | struct protection_domain *domain; |
df3f7a6e | 2332 | struct iommu_domain *io_domain; |
b20ac0d4 | 2333 | |
f99c0f1c | 2334 | if (!check_device(dev)) |
94f6d190 | 2335 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2336 | |
d26592a9 | 2337 | domain = get_dev_data(dev)->domain; |
df3f7a6e BH |
2338 | if (domain == NULL && get_dev_data(dev)->defer_attach) { |
2339 | get_dev_data(dev)->defer_attach = false; | |
2340 | io_domain = iommu_get_domain_for_dev(dev); | |
2341 | domain = to_pdomain(io_domain); | |
2342 | attach_device(dev, domain); | |
2343 | } | |
ec62b1ab BH |
2344 | if (domain == NULL) |
2345 | return ERR_PTR(-EBUSY); | |
2346 | ||
0bb6e243 | 2347 | if (!dma_ops_domain(domain)) |
94f6d190 | 2348 | return ERR_PTR(-EBUSY); |
f91ba190 | 2349 | |
0bb6e243 | 2350 | return domain; |
b20ac0d4 JR |
2351 | } |
2352 | ||
04bfdd84 JR |
2353 | static void update_device_table(struct protection_domain *domain) |
2354 | { | |
492667da | 2355 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2356 | |
3254de6b | 2357 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ff18c4e5 GH |
2358 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled, |
2359 | dev_data->iommu_v2); | |
3254de6b JR |
2360 | |
2361 | if (dev_data->devid == dev_data->alias) | |
2362 | continue; | |
2363 | ||
2364 | /* There is an alias, update device table entry for it */ | |
ff18c4e5 GH |
2365 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled, |
2366 | dev_data->iommu_v2); | |
3254de6b | 2367 | } |
04bfdd84 JR |
2368 | } |
2369 | ||
2370 | static void update_domain(struct protection_domain *domain) | |
2371 | { | |
2372 | if (!domain->updated) | |
2373 | return; | |
2374 | ||
2375 | update_device_table(domain); | |
17b124bf JR |
2376 | |
2377 | domain_flush_devices(domain); | |
2378 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2379 | |
2380 | domain->updated = false; | |
2381 | } | |
2382 | ||
f37f7f33 JR |
2383 | static int dir2prot(enum dma_data_direction direction) |
2384 | { | |
2385 | if (direction == DMA_TO_DEVICE) | |
2386 | return IOMMU_PROT_IR; | |
2387 | else if (direction == DMA_FROM_DEVICE) | |
2388 | return IOMMU_PROT_IW; | |
2389 | else if (direction == DMA_BIDIRECTIONAL) | |
2390 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2391 | else | |
2392 | return 0; | |
2393 | } | |
daae2d25 | 2394 | |
431b2a20 JR |
2395 | /* |
2396 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2397 | * contiguous memory region into DMA address space. It is used by all |
2398 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2399 | * Must be called with the domain lock held. |
2400 | */ | |
cb76c322 | 2401 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2402 | struct dma_ops_domain *dma_dom, |
2403 | phys_addr_t paddr, | |
2404 | size_t size, | |
f37f7f33 | 2405 | enum dma_data_direction direction, |
832a90c3 | 2406 | u64 dma_mask) |
cb76c322 JR |
2407 | { |
2408 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2409 | dma_addr_t address, start, ret; |
cb76c322 | 2410 | unsigned int pages; |
518d9b45 | 2411 | int prot = 0; |
cb76c322 JR |
2412 | int i; |
2413 | ||
e3c449f5 | 2414 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2415 | paddr &= PAGE_MASK; |
2416 | ||
256e4621 | 2417 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
b3aa14f0 | 2418 | if (!address) |
266a3bd2 | 2419 | goto out; |
cb76c322 | 2420 | |
f37f7f33 | 2421 | prot = dir2prot(direction); |
518d9b45 | 2422 | |
cb76c322 JR |
2423 | start = address; |
2424 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2425 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2426 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2427 | if (ret) | |
53812c11 JR |
2428 | goto out_unmap; |
2429 | ||
cb76c322 JR |
2430 | paddr += PAGE_SIZE; |
2431 | start += PAGE_SIZE; | |
2432 | } | |
2433 | address += offset; | |
2434 | ||
ab7032bb | 2435 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2436 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2437 | domain_flush_complete(&dma_dom->domain); |
2438 | } | |
270cab24 | 2439 | |
cb76c322 JR |
2440 | out: |
2441 | return address; | |
53812c11 JR |
2442 | |
2443 | out_unmap: | |
2444 | ||
2445 | for (--i; i >= 0; --i) { | |
2446 | start -= PAGE_SIZE; | |
518d9b45 | 2447 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2448 | } |
2449 | ||
256e4621 JR |
2450 | domain_flush_tlb(&dma_dom->domain); |
2451 | domain_flush_complete(&dma_dom->domain); | |
2452 | ||
2453 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2454 | |
b3aa14f0 | 2455 | return DMA_MAPPING_ERROR; |
cb76c322 JR |
2456 | } |
2457 | ||
431b2a20 JR |
2458 | /* |
2459 | * Does the reverse of the __map_single function. Must be called with | |
2460 | * the domain lock held too | |
2461 | */ | |
cd8c82e8 | 2462 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2463 | dma_addr_t dma_addr, |
2464 | size_t size, | |
2465 | int dir) | |
2466 | { | |
2467 | dma_addr_t i, start; | |
2468 | unsigned int pages; | |
2469 | ||
e3c449f5 | 2470 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2471 | dma_addr &= PAGE_MASK; |
2472 | start = dma_addr; | |
2473 | ||
2474 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2475 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2476 | start += PAGE_SIZE; |
2477 | } | |
2478 | ||
b1516a14 | 2479 | if (amd_iommu_unmap_flush) { |
b1516a14 JR |
2480 | domain_flush_tlb(&dma_dom->domain); |
2481 | domain_flush_complete(&dma_dom->domain); | |
3c120143 | 2482 | dma_ops_free_iova(dma_dom, dma_addr, pages); |
b1516a14 | 2483 | } else { |
9003d618 JR |
2484 | pages = __roundup_pow_of_two(pages); |
2485 | queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0); | |
b1516a14 | 2486 | } |
cb76c322 JR |
2487 | } |
2488 | ||
431b2a20 JR |
2489 | /* |
2490 | * The exported map_single function for dma_ops. | |
2491 | */ | |
51491367 FT |
2492 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2493 | unsigned long offset, size_t size, | |
2494 | enum dma_data_direction dir, | |
00085f1e | 2495 | unsigned long attrs) |
4da70b9e | 2496 | { |
92d420ec | 2497 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2498 | struct protection_domain *domain; |
b3311b06 | 2499 | struct dma_ops_domain *dma_dom; |
832a90c3 | 2500 | u64 dma_mask; |
4da70b9e | 2501 | |
94f6d190 JR |
2502 | domain = get_domain(dev); |
2503 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2504 | return (dma_addr_t)paddr; |
94f6d190 | 2505 | else if (IS_ERR(domain)) |
b3aa14f0 | 2506 | return DMA_MAPPING_ERROR; |
4da70b9e | 2507 | |
f99c0f1c | 2508 | dma_mask = *dev->dma_mask; |
b3311b06 | 2509 | dma_dom = to_dma_ops_domain(domain); |
f99c0f1c | 2510 | |
b3311b06 | 2511 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2512 | } |
2513 | ||
431b2a20 JR |
2514 | /* |
2515 | * The exported unmap_single function for dma_ops. | |
2516 | */ | |
51491367 | 2517 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2518 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2519 | { |
4da70b9e | 2520 | struct protection_domain *domain; |
b3311b06 | 2521 | struct dma_ops_domain *dma_dom; |
4da70b9e | 2522 | |
94f6d190 JR |
2523 | domain = get_domain(dev); |
2524 | if (IS_ERR(domain)) | |
5b28df6f JR |
2525 | return; |
2526 | ||
b3311b06 JR |
2527 | dma_dom = to_dma_ops_domain(domain); |
2528 | ||
2529 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2530 | } |
2531 | ||
80187fd3 JR |
2532 | static int sg_num_pages(struct device *dev, |
2533 | struct scatterlist *sglist, | |
2534 | int nelems) | |
2535 | { | |
2536 | unsigned long mask, boundary_size; | |
2537 | struct scatterlist *s; | |
2538 | int i, npages = 0; | |
2539 | ||
2540 | mask = dma_get_seg_boundary(dev); | |
2541 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2542 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2543 | ||
2544 | for_each_sg(sglist, s, nelems, i) { | |
2545 | int p, n; | |
2546 | ||
2547 | s->dma_address = npages << PAGE_SHIFT; | |
2548 | p = npages % boundary_size; | |
2549 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2550 | if (p + n > boundary_size) | |
2551 | npages += boundary_size - p; | |
2552 | npages += n; | |
2553 | } | |
2554 | ||
2555 | return npages; | |
2556 | } | |
2557 | ||
431b2a20 JR |
2558 | /* |
2559 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2560 | * lists). | |
2561 | */ | |
65b050ad | 2562 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2563 | int nelems, enum dma_data_direction direction, |
00085f1e | 2564 | unsigned long attrs) |
65b050ad | 2565 | { |
80187fd3 | 2566 | int mapped_pages = 0, npages = 0, prot = 0, i; |
65b050ad | 2567 | struct protection_domain *domain; |
80187fd3 | 2568 | struct dma_ops_domain *dma_dom; |
65b050ad | 2569 | struct scatterlist *s; |
80187fd3 | 2570 | unsigned long address; |
832a90c3 | 2571 | u64 dma_mask; |
65b050ad | 2572 | |
94f6d190 | 2573 | domain = get_domain(dev); |
a0e191b2 | 2574 | if (IS_ERR(domain)) |
94f6d190 | 2575 | return 0; |
dbcc112e | 2576 | |
b3311b06 | 2577 | dma_dom = to_dma_ops_domain(domain); |
832a90c3 | 2578 | dma_mask = *dev->dma_mask; |
65b050ad | 2579 | |
80187fd3 JR |
2580 | npages = sg_num_pages(dev, sglist, nelems); |
2581 | ||
2582 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
b3aa14f0 | 2583 | if (address == DMA_MAPPING_ERROR) |
80187fd3 JR |
2584 | goto out_err; |
2585 | ||
2586 | prot = dir2prot(direction); | |
2587 | ||
2588 | /* Map all sg entries */ | |
65b050ad | 2589 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2590 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2591 | ||
2592 | for (j = 0; j < pages; ++j) { | |
2593 | unsigned long bus_addr, phys_addr; | |
2594 | int ret; | |
65b050ad | 2595 | |
80187fd3 JR |
2596 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2597 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
2598 | ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC); | |
2599 | if (ret) | |
2600 | goto out_unmap; | |
65b050ad | 2601 | |
80187fd3 JR |
2602 | mapped_pages += 1; |
2603 | } | |
65b050ad JR |
2604 | } |
2605 | ||
80187fd3 JR |
2606 | /* Everything is mapped - write the right values into s->dma_address */ |
2607 | for_each_sg(sglist, s, nelems, i) { | |
2608 | s->dma_address += address + s->offset; | |
2609 | s->dma_length = s->length; | |
2610 | } | |
2611 | ||
2612 | return nelems; | |
2613 | ||
2614 | out_unmap: | |
2615 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2616 | dev_name(dev), npages); | |
2617 | ||
2618 | for_each_sg(sglist, s, nelems, i) { | |
2619 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2620 | ||
2621 | for (j = 0; j < pages; ++j) { | |
2622 | unsigned long bus_addr; | |
92d420ec | 2623 | |
80187fd3 JR |
2624 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2625 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2626 | ||
f1724c08 | 2627 | if (--mapped_pages == 0) |
80187fd3 JR |
2628 | goto out_free_iova; |
2629 | } | |
65b050ad JR |
2630 | } |
2631 | ||
80187fd3 | 2632 | out_free_iova: |
51d8838d | 2633 | free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages); |
80187fd3 JR |
2634 | |
2635 | out_err: | |
92d420ec | 2636 | return 0; |
65b050ad JR |
2637 | } |
2638 | ||
431b2a20 JR |
2639 | /* |
2640 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2641 | * lists). | |
2642 | */ | |
65b050ad | 2643 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2644 | int nelems, enum dma_data_direction dir, |
00085f1e | 2645 | unsigned long attrs) |
65b050ad | 2646 | { |
65b050ad | 2647 | struct protection_domain *domain; |
b3311b06 | 2648 | struct dma_ops_domain *dma_dom; |
80187fd3 JR |
2649 | unsigned long startaddr; |
2650 | int npages = 2; | |
65b050ad | 2651 | |
94f6d190 JR |
2652 | domain = get_domain(dev); |
2653 | if (IS_ERR(domain)) | |
5b28df6f JR |
2654 | return; |
2655 | ||
80187fd3 | 2656 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
b3311b06 | 2657 | dma_dom = to_dma_ops_domain(domain); |
80187fd3 JR |
2658 | npages = sg_num_pages(dev, sglist, nelems); |
2659 | ||
b3311b06 | 2660 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2661 | } |
2662 | ||
431b2a20 JR |
2663 | /* |
2664 | * The exported alloc_coherent function for dma_ops. | |
2665 | */ | |
5d8b53cf | 2666 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2667 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2668 | unsigned long attrs) |
5d8b53cf | 2669 | { |
832a90c3 | 2670 | u64 dma_mask = dev->coherent_dma_mask; |
e16c4790 LT |
2671 | struct protection_domain *domain; |
2672 | struct dma_ops_domain *dma_dom; | |
2673 | struct page *page; | |
2674 | ||
2675 | domain = get_domain(dev); | |
2676 | if (PTR_ERR(domain) == -EINVAL) { | |
2677 | page = alloc_pages(flag, get_order(size)); | |
2678 | *dma_addr = page_to_phys(page); | |
2679 | return page_address(page); | |
2680 | } else if (IS_ERR(domain)) | |
2681 | return NULL; | |
5d8b53cf | 2682 | |
e16c4790 LT |
2683 | dma_dom = to_dma_ops_domain(domain); |
2684 | size = PAGE_ALIGN(size); | |
2685 | dma_mask = dev->coherent_dma_mask; | |
2686 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2687 | flag |= __GFP_ZERO; | |
2688 | ||
2689 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); | |
2690 | if (!page) { | |
2691 | if (!gfpflags_allow_blocking(flag)) | |
3b839a57 | 2692 | return NULL; |
5d8b53cf | 2693 | |
e16c4790 | 2694 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
d834c5ab | 2695 | get_order(size), flag & __GFP_NOWARN); |
e16c4790 LT |
2696 | if (!page) |
2697 | return NULL; | |
2698 | } | |
b468620f | 2699 | |
832a90c3 JR |
2700 | if (!dma_mask) |
2701 | dma_mask = *dev->dma_mask; | |
2702 | ||
e16c4790 LT |
2703 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
2704 | size, DMA_BIDIRECTIONAL, dma_mask); | |
2705 | ||
b3aa14f0 | 2706 | if (*dma_addr == DMA_MAPPING_ERROR) |
5b28df6f | 2707 | goto out_free; |
e16c4790 LT |
2708 | |
2709 | return page_address(page); | |
5b28df6f JR |
2710 | |
2711 | out_free: | |
e16c4790 LT |
2712 | |
2713 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
2714 | __free_pages(page, get_order(size)); | |
2715 | ||
5b28df6f | 2716 | return NULL; |
5d8b53cf JR |
2717 | } |
2718 | ||
431b2a20 JR |
2719 | /* |
2720 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2721 | */ |
5d8b53cf | 2722 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2723 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2724 | unsigned long attrs) |
5d8b53cf | 2725 | { |
e16c4790 LT |
2726 | struct protection_domain *domain; |
2727 | struct dma_ops_domain *dma_dom; | |
2728 | struct page *page; | |
5d8b53cf | 2729 | |
e16c4790 | 2730 | page = virt_to_page(virt_addr); |
3b839a57 JR |
2731 | size = PAGE_ALIGN(size); |
2732 | ||
e16c4790 LT |
2733 | domain = get_domain(dev); |
2734 | if (IS_ERR(domain)) | |
2735 | goto free_mem; | |
5b28df6f | 2736 | |
e16c4790 LT |
2737 | dma_dom = to_dma_ops_domain(domain); |
2738 | ||
2739 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2740 | |
e16c4790 LT |
2741 | free_mem: |
2742 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
2743 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2744 | } |
2745 | ||
b39ba6ad JR |
2746 | /* |
2747 | * This function is called by the DMA layer to find out if we can handle a | |
2748 | * particular device. It is part of the dma_ops. | |
2749 | */ | |
2750 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2751 | { | |
fec777c3 | 2752 | if (!dma_direct_supported(dev, mask)) |
5860acc1 | 2753 | return 0; |
420aef8a | 2754 | return check_device(dev); |
b39ba6ad JR |
2755 | } |
2756 | ||
5299709d | 2757 | static const struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2758 | .alloc = alloc_coherent, |
2759 | .free = free_coherent, | |
2760 | .map_page = map_page, | |
2761 | .unmap_page = unmap_page, | |
2762 | .map_sg = map_sg, | |
2763 | .unmap_sg = unmap_sg, | |
2764 | .dma_supported = amd_iommu_dma_supported, | |
6631ee9d JR |
2765 | }; |
2766 | ||
81cd07b9 JR |
2767 | static int init_reserved_iova_ranges(void) |
2768 | { | |
2769 | struct pci_dev *pdev = NULL; | |
2770 | struct iova *val; | |
2771 | ||
aa3ac946 | 2772 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN); |
81cd07b9 JR |
2773 | |
2774 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2775 | &reserved_rbtree_key); | |
2776 | ||
2777 | /* MSI memory range */ | |
2778 | val = reserve_iova(&reserved_iova_ranges, | |
2779 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2780 | if (!val) { | |
2781 | pr_err("Reserving MSI range failed\n"); | |
2782 | return -ENOMEM; | |
2783 | } | |
2784 | ||
2785 | /* HT memory range */ | |
2786 | val = reserve_iova(&reserved_iova_ranges, | |
2787 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2788 | if (!val) { | |
2789 | pr_err("Reserving HT range failed\n"); | |
2790 | return -ENOMEM; | |
2791 | } | |
2792 | ||
2793 | /* | |
2794 | * Memory used for PCI resources | |
2795 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2796 | */ | |
2797 | for_each_pci_dev(pdev) { | |
2798 | int i; | |
2799 | ||
2800 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2801 | struct resource *r = &pdev->resource[i]; | |
2802 | ||
2803 | if (!(r->flags & IORESOURCE_MEM)) | |
2804 | continue; | |
2805 | ||
2806 | val = reserve_iova(&reserved_iova_ranges, | |
2807 | IOVA_PFN(r->start), | |
2808 | IOVA_PFN(r->end)); | |
2809 | if (!val) { | |
2810 | pr_err("Reserve pci-resource range failed\n"); | |
2811 | return -ENOMEM; | |
2812 | } | |
2813 | } | |
2814 | } | |
2815 | ||
2816 | return 0; | |
2817 | } | |
2818 | ||
3a18404c | 2819 | int __init amd_iommu_init_api(void) |
27c2127a | 2820 | { |
460c26d0 | 2821 | int ret, err = 0; |
307d5851 JR |
2822 | |
2823 | ret = iova_cache_get(); | |
2824 | if (ret) | |
2825 | return ret; | |
9a4d3bf5 | 2826 | |
81cd07b9 JR |
2827 | ret = init_reserved_iova_ranges(); |
2828 | if (ret) | |
2829 | return ret; | |
2830 | ||
9a4d3bf5 WZ |
2831 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2832 | if (err) | |
2833 | return err; | |
2834 | #ifdef CONFIG_ARM_AMBA | |
2835 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2836 | if (err) | |
2837 | return err; | |
2838 | #endif | |
0076cd3d WZ |
2839 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2840 | if (err) | |
2841 | return err; | |
c5b5da9c | 2842 | |
460c26d0 | 2843 | return 0; |
f5325094 JR |
2844 | } |
2845 | ||
6631ee9d JR |
2846 | int __init amd_iommu_init_dma_ops(void) |
2847 | { | |
aba2d9a6 | 2848 | swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; |
6631ee9d | 2849 | iommu_detected = 1; |
6631ee9d | 2850 | |
62410eeb | 2851 | if (amd_iommu_unmap_flush) |
101fa037 | 2852 | pr_info("IO/TLB flush on unmap enabled\n"); |
62410eeb | 2853 | else |
101fa037 | 2854 | pr_info("Lazy IO/TLB flushing enabled\n"); |
62410eeb | 2855 | |
6631ee9d | 2856 | return 0; |
c5b5da9c | 2857 | |
6631ee9d | 2858 | } |
6d98cd80 JR |
2859 | |
2860 | /***************************************************************************** | |
2861 | * | |
2862 | * The following functions belong to the exported interface of AMD IOMMU | |
2863 | * | |
2864 | * This interface allows access to lower level functions of the IOMMU | |
2865 | * like protection domain handling and assignement of devices to domains | |
2866 | * which is not possible with the dma_ops interface. | |
2867 | * | |
2868 | *****************************************************************************/ | |
2869 | ||
6d98cd80 JR |
2870 | static void cleanup_domain(struct protection_domain *domain) |
2871 | { | |
9b29d3c6 | 2872 | struct iommu_dev_data *entry; |
6d98cd80 | 2873 | unsigned long flags; |
6d98cd80 | 2874 | |
2cd1083d | 2875 | spin_lock_irqsave(&amd_iommu_devtable_lock, flags); |
6d98cd80 | 2876 | |
9b29d3c6 JR |
2877 | while (!list_empty(&domain->dev_list)) { |
2878 | entry = list_first_entry(&domain->dev_list, | |
2879 | struct iommu_dev_data, list); | |
ea3fd040 | 2880 | BUG_ON(!entry->domain); |
9b29d3c6 | 2881 | __detach_device(entry); |
492667da | 2882 | } |
6d98cd80 | 2883 | |
2cd1083d | 2884 | spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
6d98cd80 JR |
2885 | } |
2886 | ||
2650815f JR |
2887 | static void protection_domain_free(struct protection_domain *domain) |
2888 | { | |
2889 | if (!domain) | |
2890 | return; | |
2891 | ||
aeb26f55 JR |
2892 | del_domain_from_list(domain); |
2893 | ||
2650815f JR |
2894 | if (domain->id) |
2895 | domain_id_free(domain->id); | |
2896 | ||
2897 | kfree(domain); | |
2898 | } | |
2899 | ||
7a5a566e JR |
2900 | static int protection_domain_init(struct protection_domain *domain) |
2901 | { | |
2902 | spin_lock_init(&domain->lock); | |
2903 | mutex_init(&domain->api_lock); | |
2904 | domain->id = domain_id_alloc(); | |
2905 | if (!domain->id) | |
2906 | return -ENOMEM; | |
2907 | INIT_LIST_HEAD(&domain->dev_list); | |
2908 | ||
2909 | return 0; | |
2910 | } | |
2911 | ||
2650815f | 2912 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2913 | { |
2914 | struct protection_domain *domain; | |
2915 | ||
2916 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2917 | if (!domain) | |
2650815f | 2918 | return NULL; |
c156e347 | 2919 | |
7a5a566e | 2920 | if (protection_domain_init(domain)) |
2650815f JR |
2921 | goto out_err; |
2922 | ||
aeb26f55 JR |
2923 | add_domain_to_list(domain); |
2924 | ||
2650815f JR |
2925 | return domain; |
2926 | ||
2927 | out_err: | |
2928 | kfree(domain); | |
2929 | ||
2930 | return NULL; | |
2931 | } | |
2932 | ||
3f4b87b9 | 2933 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2934 | { |
3f4b87b9 | 2935 | struct protection_domain *pdomain; |
0bb6e243 | 2936 | struct dma_ops_domain *dma_domain; |
2650815f | 2937 | |
0bb6e243 JR |
2938 | switch (type) { |
2939 | case IOMMU_DOMAIN_UNMANAGED: | |
2940 | pdomain = protection_domain_alloc(); | |
2941 | if (!pdomain) | |
2942 | return NULL; | |
c156e347 | 2943 | |
0bb6e243 JR |
2944 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2945 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2946 | if (!pdomain->pt_root) { | |
2947 | protection_domain_free(pdomain); | |
2948 | return NULL; | |
2949 | } | |
c156e347 | 2950 | |
0bb6e243 JR |
2951 | pdomain->domain.geometry.aperture_start = 0; |
2952 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2953 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2954 | |
0bb6e243 JR |
2955 | break; |
2956 | case IOMMU_DOMAIN_DMA: | |
2957 | dma_domain = dma_ops_domain_alloc(); | |
2958 | if (!dma_domain) { | |
101fa037 | 2959 | pr_err("Failed to allocate\n"); |
0bb6e243 JR |
2960 | return NULL; |
2961 | } | |
2962 | pdomain = &dma_domain->domain; | |
2963 | break; | |
07f643a3 JR |
2964 | case IOMMU_DOMAIN_IDENTITY: |
2965 | pdomain = protection_domain_alloc(); | |
2966 | if (!pdomain) | |
2967 | return NULL; | |
c156e347 | 2968 | |
07f643a3 JR |
2969 | pdomain->mode = PAGE_MODE_NONE; |
2970 | break; | |
0bb6e243 JR |
2971 | default: |
2972 | return NULL; | |
2973 | } | |
c156e347 | 2974 | |
3f4b87b9 | 2975 | return &pdomain->domain; |
c156e347 JR |
2976 | } |
2977 | ||
3f4b87b9 | 2978 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2979 | { |
3f4b87b9 | 2980 | struct protection_domain *domain; |
cda7005b | 2981 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2982 | |
3f4b87b9 JR |
2983 | domain = to_pdomain(dom); |
2984 | ||
98383fc3 JR |
2985 | if (domain->dev_cnt > 0) |
2986 | cleanup_domain(domain); | |
2987 | ||
2988 | BUG_ON(domain->dev_cnt != 0); | |
2989 | ||
cda7005b JR |
2990 | if (!dom) |
2991 | return; | |
98383fc3 | 2992 | |
cda7005b JR |
2993 | switch (dom->type) { |
2994 | case IOMMU_DOMAIN_DMA: | |
281e8ccb | 2995 | /* Now release the domain */ |
b3311b06 | 2996 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
2997 | dma_ops_domain_free(dma_dom); |
2998 | break; | |
2999 | default: | |
3000 | if (domain->mode != PAGE_MODE_NONE) | |
3001 | free_pagetable(domain); | |
52815b75 | 3002 | |
cda7005b JR |
3003 | if (domain->flags & PD_IOMMUV2_MASK) |
3004 | free_gcr3_table(domain); | |
3005 | ||
3006 | protection_domain_free(domain); | |
3007 | break; | |
3008 | } | |
98383fc3 JR |
3009 | } |
3010 | ||
684f2888 JR |
3011 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3012 | struct device *dev) | |
3013 | { | |
657cbb6b | 3014 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3015 | struct amd_iommu *iommu; |
7aba6cb9 | 3016 | int devid; |
684f2888 | 3017 | |
98fc5a69 | 3018 | if (!check_device(dev)) |
684f2888 JR |
3019 | return; |
3020 | ||
98fc5a69 | 3021 | devid = get_device_id(dev); |
9ee35e4c | 3022 | if (devid < 0) |
7aba6cb9 | 3023 | return; |
684f2888 | 3024 | |
657cbb6b | 3025 | if (dev_data->domain != NULL) |
15898bbc | 3026 | detach_device(dev); |
684f2888 JR |
3027 | |
3028 | iommu = amd_iommu_rlookup_table[devid]; | |
3029 | if (!iommu) | |
3030 | return; | |
3031 | ||
d98de49a SS |
3032 | #ifdef CONFIG_IRQ_REMAP |
3033 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
3034 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
3035 | dev_data->use_vapic = 0; | |
3036 | #endif | |
3037 | ||
684f2888 JR |
3038 | iommu_completion_wait(iommu); |
3039 | } | |
3040 | ||
01106066 JR |
3041 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3042 | struct device *dev) | |
3043 | { | |
3f4b87b9 | 3044 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3045 | struct iommu_dev_data *dev_data; |
01106066 | 3046 | struct amd_iommu *iommu; |
15898bbc | 3047 | int ret; |
01106066 | 3048 | |
98fc5a69 | 3049 | if (!check_device(dev)) |
01106066 JR |
3050 | return -EINVAL; |
3051 | ||
657cbb6b JR |
3052 | dev_data = dev->archdata.iommu; |
3053 | ||
f62dda66 | 3054 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3055 | if (!iommu) |
3056 | return -EINVAL; | |
3057 | ||
657cbb6b | 3058 | if (dev_data->domain) |
15898bbc | 3059 | detach_device(dev); |
01106066 | 3060 | |
15898bbc | 3061 | ret = attach_device(dev, domain); |
01106066 | 3062 | |
d98de49a SS |
3063 | #ifdef CONFIG_IRQ_REMAP |
3064 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3065 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3066 | dev_data->use_vapic = 1; | |
3067 | else | |
3068 | dev_data->use_vapic = 0; | |
3069 | } | |
3070 | #endif | |
3071 | ||
01106066 JR |
3072 | iommu_completion_wait(iommu); |
3073 | ||
15898bbc | 3074 | return ret; |
01106066 JR |
3075 | } |
3076 | ||
468e2366 | 3077 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3078 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3079 | { |
3f4b87b9 | 3080 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3081 | int prot = 0; |
3082 | int ret; | |
3083 | ||
132bd68f JR |
3084 | if (domain->mode == PAGE_MODE_NONE) |
3085 | return -EINVAL; | |
3086 | ||
c6229ca6 JR |
3087 | if (iommu_prot & IOMMU_READ) |
3088 | prot |= IOMMU_PROT_IR; | |
3089 | if (iommu_prot & IOMMU_WRITE) | |
3090 | prot |= IOMMU_PROT_IW; | |
3091 | ||
5d214fe6 | 3092 | mutex_lock(&domain->api_lock); |
b911b89b | 3093 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3094 | mutex_unlock(&domain->api_lock); |
3095 | ||
795e74f7 | 3096 | return ret; |
c6229ca6 JR |
3097 | } |
3098 | ||
5009065d OBC |
3099 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3100 | size_t page_size) | |
eb74ff6c | 3101 | { |
3f4b87b9 | 3102 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3103 | size_t unmap_size; |
eb74ff6c | 3104 | |
132bd68f | 3105 | if (domain->mode == PAGE_MODE_NONE) |
c5611a87 | 3106 | return 0; |
132bd68f | 3107 | |
5d214fe6 | 3108 | mutex_lock(&domain->api_lock); |
468e2366 | 3109 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3110 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3111 | |
5009065d | 3112 | return unmap_size; |
eb74ff6c JR |
3113 | } |
3114 | ||
645c4c8d | 3115 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3116 | dma_addr_t iova) |
645c4c8d | 3117 | { |
3f4b87b9 | 3118 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3119 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3120 | u64 *pte, __pte; |
645c4c8d | 3121 | |
132bd68f JR |
3122 | if (domain->mode == PAGE_MODE_NONE) |
3123 | return iova; | |
3124 | ||
3039ca1b | 3125 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3126 | |
a6d41a40 | 3127 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3128 | return 0; |
3129 | ||
b24b1b63 | 3130 | offset_mask = pte_pgsize - 1; |
b3e9b515 | 3131 | __pte = __sme_clr(*pte & PM_ADDR_MASK); |
645c4c8d | 3132 | |
b24b1b63 | 3133 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3134 | } |
3135 | ||
ab636481 | 3136 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3137 | { |
80a506b8 JR |
3138 | switch (cap) { |
3139 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3140 | return true; |
bdddadcb | 3141 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3142 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3143 | case IOMMU_CAP_NOEXEC: |
3144 | return false; | |
e84b7cc4 LB |
3145 | default: |
3146 | break; | |
80a506b8 JR |
3147 | } |
3148 | ||
ab636481 | 3149 | return false; |
dbb9fd86 SY |
3150 | } |
3151 | ||
e5b5234a EA |
3152 | static void amd_iommu_get_resv_regions(struct device *dev, |
3153 | struct list_head *head) | |
35cf248f | 3154 | { |
4397f32c | 3155 | struct iommu_resv_region *region; |
35cf248f | 3156 | struct unity_map_entry *entry; |
7aba6cb9 | 3157 | int devid; |
35cf248f JR |
3158 | |
3159 | devid = get_device_id(dev); | |
9ee35e4c | 3160 | if (devid < 0) |
7aba6cb9 | 3161 | return; |
35cf248f JR |
3162 | |
3163 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
4397f32c EA |
3164 | size_t length; |
3165 | int prot = 0; | |
35cf248f JR |
3166 | |
3167 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3168 | continue; | |
3169 | ||
4397f32c EA |
3170 | length = entry->address_end - entry->address_start; |
3171 | if (entry->prot & IOMMU_PROT_IR) | |
3172 | prot |= IOMMU_READ; | |
3173 | if (entry->prot & IOMMU_PROT_IW) | |
3174 | prot |= IOMMU_WRITE; | |
3175 | ||
3176 | region = iommu_alloc_resv_region(entry->address_start, | |
3177 | length, prot, | |
3178 | IOMMU_RESV_DIRECT); | |
35cf248f JR |
3179 | if (!region) { |
3180 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3181 | dev_name(dev)); | |
3182 | return; | |
3183 | } | |
35cf248f JR |
3184 | list_add_tail(®ion->list, head); |
3185 | } | |
4397f32c EA |
3186 | |
3187 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3188 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 3189 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
3190 | if (!region) |
3191 | return; | |
3192 | list_add_tail(®ion->list, head); | |
3193 | ||
3194 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3195 | HT_RANGE_END - HT_RANGE_START + 1, | |
3196 | 0, IOMMU_RESV_RESERVED); | |
3197 | if (!region) | |
3198 | return; | |
3199 | list_add_tail(®ion->list, head); | |
35cf248f JR |
3200 | } |
3201 | ||
e5b5234a | 3202 | static void amd_iommu_put_resv_regions(struct device *dev, |
35cf248f JR |
3203 | struct list_head *head) |
3204 | { | |
e5b5234a | 3205 | struct iommu_resv_region *entry, *next; |
35cf248f JR |
3206 | |
3207 | list_for_each_entry_safe(entry, next, head, list) | |
3208 | kfree(entry); | |
3209 | } | |
3210 | ||
e5b5234a | 3211 | static void amd_iommu_apply_resv_region(struct device *dev, |
8d54d6c8 | 3212 | struct iommu_domain *domain, |
e5b5234a | 3213 | struct iommu_resv_region *region) |
8d54d6c8 | 3214 | { |
b3311b06 | 3215 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3216 | unsigned long start, end; |
3217 | ||
3218 | start = IOVA_PFN(region->start); | |
b92b4fb5 | 3219 | end = IOVA_PFN(region->start + region->length - 1); |
8d54d6c8 JR |
3220 | |
3221 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3222 | } | |
3223 | ||
df3f7a6e BH |
3224 | static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
3225 | struct device *dev) | |
3226 | { | |
3227 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
3228 | return dev_data->defer_attach; | |
3229 | } | |
3230 | ||
eb5ecd1a SS |
3231 | static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain) |
3232 | { | |
3233 | struct protection_domain *dom = to_pdomain(domain); | |
3234 | ||
3235 | domain_flush_tlb_pde(dom); | |
3236 | domain_flush_complete(dom); | |
3237 | } | |
3238 | ||
3239 | static void amd_iommu_iotlb_range_add(struct iommu_domain *domain, | |
3240 | unsigned long iova, size_t size) | |
3241 | { | |
3242 | } | |
3243 | ||
b0119e87 | 3244 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3245 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3246 | .domain_alloc = amd_iommu_domain_alloc, |
3247 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3248 | .attach_dev = amd_iommu_attach_device, |
3249 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3250 | .map = amd_iommu_map, |
3251 | .unmap = amd_iommu_unmap, | |
26961efe | 3252 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3253 | .add_device = amd_iommu_add_device, |
3254 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3255 | .device_group = amd_iommu_device_group, |
e5b5234a EA |
3256 | .get_resv_regions = amd_iommu_get_resv_regions, |
3257 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3258 | .apply_resv_region = amd_iommu_apply_resv_region, | |
df3f7a6e | 3259 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 3260 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
eb5ecd1a SS |
3261 | .flush_iotlb_all = amd_iommu_flush_iotlb_all, |
3262 | .iotlb_range_add = amd_iommu_iotlb_range_add, | |
3263 | .iotlb_sync = amd_iommu_flush_iotlb_all, | |
26961efe JR |
3264 | }; |
3265 | ||
0feae533 JR |
3266 | /***************************************************************************** |
3267 | * | |
3268 | * The next functions do a basic initialization of IOMMU for pass through | |
3269 | * mode | |
3270 | * | |
3271 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3272 | * DMA-API translation. | |
3273 | * | |
3274 | *****************************************************************************/ | |
3275 | ||
72e1dcc4 JR |
3276 | /* IOMMUv2 specific functions */ |
3277 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3278 | { | |
3279 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3280 | } | |
3281 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3282 | ||
3283 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3284 | { | |
3285 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3286 | } | |
3287 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3288 | |
3289 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3290 | { | |
3f4b87b9 | 3291 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3292 | unsigned long flags; |
3293 | ||
3294 | spin_lock_irqsave(&domain->lock, flags); | |
3295 | ||
3296 | /* Update data structure */ | |
3297 | domain->mode = PAGE_MODE_NONE; | |
3298 | domain->updated = true; | |
3299 | ||
3300 | /* Make changes visible to IOMMUs */ | |
3301 | update_domain(domain); | |
3302 | ||
3303 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3304 | free_pagetable(domain); | |
3305 | ||
3306 | spin_unlock_irqrestore(&domain->lock, flags); | |
3307 | } | |
3308 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3309 | |
3310 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3311 | { | |
3f4b87b9 | 3312 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3313 | unsigned long flags; |
3314 | int levels, ret; | |
3315 | ||
3316 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3317 | return -EINVAL; | |
3318 | ||
3319 | /* Number of GCR3 table levels required */ | |
3320 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3321 | levels += 1; | |
3322 | ||
3323 | if (levels > amd_iommu_max_glx_val) | |
3324 | return -EINVAL; | |
3325 | ||
3326 | spin_lock_irqsave(&domain->lock, flags); | |
3327 | ||
3328 | /* | |
3329 | * Save us all sanity checks whether devices already in the | |
3330 | * domain support IOMMUv2. Just force that the domain has no | |
3331 | * devices attached when it is switched into IOMMUv2 mode. | |
3332 | */ | |
3333 | ret = -EBUSY; | |
3334 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3335 | goto out; | |
3336 | ||
3337 | ret = -ENOMEM; | |
3338 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3339 | if (domain->gcr3_tbl == NULL) | |
3340 | goto out; | |
3341 | ||
3342 | domain->glx = levels; | |
3343 | domain->flags |= PD_IOMMUV2_MASK; | |
3344 | domain->updated = true; | |
3345 | ||
3346 | update_domain(domain); | |
3347 | ||
3348 | ret = 0; | |
3349 | ||
3350 | out: | |
3351 | spin_unlock_irqrestore(&domain->lock, flags); | |
3352 | ||
3353 | return ret; | |
3354 | } | |
3355 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3356 | |
3357 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3358 | u64 address, bool size) | |
3359 | { | |
3360 | struct iommu_dev_data *dev_data; | |
3361 | struct iommu_cmd cmd; | |
3362 | int i, ret; | |
3363 | ||
3364 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3365 | return -EINVAL; | |
3366 | ||
3367 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3368 | ||
3369 | /* | |
3370 | * IOMMU TLB needs to be flushed before Device TLB to | |
3371 | * prevent device TLB refill from IOMMU TLB | |
3372 | */ | |
6b9376e3 | 3373 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
3374 | if (domain->dev_iommu[i] == 0) |
3375 | continue; | |
3376 | ||
3377 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3378 | if (ret != 0) | |
3379 | goto out; | |
3380 | } | |
3381 | ||
3382 | /* Wait until IOMMU TLB flushes are complete */ | |
3383 | domain_flush_complete(domain); | |
3384 | ||
3385 | /* Now flush device TLBs */ | |
3386 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3387 | struct amd_iommu *iommu; | |
3388 | int qdep; | |
3389 | ||
1c1cc454 JR |
3390 | /* |
3391 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3392 | * domain. | |
3393 | */ | |
3394 | if (!dev_data->ats.enabled) | |
3395 | continue; | |
22e266c7 JR |
3396 | |
3397 | qdep = dev_data->ats.qdep; | |
3398 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3399 | ||
3400 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3401 | qdep, address, size); | |
3402 | ||
3403 | ret = iommu_queue_command(iommu, &cmd); | |
3404 | if (ret != 0) | |
3405 | goto out; | |
3406 | } | |
3407 | ||
3408 | /* Wait until all device TLBs are flushed */ | |
3409 | domain_flush_complete(domain); | |
3410 | ||
3411 | ret = 0; | |
3412 | ||
3413 | out: | |
3414 | ||
3415 | return ret; | |
3416 | } | |
3417 | ||
3418 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3419 | u64 address) | |
3420 | { | |
3421 | return __flush_pasid(domain, pasid, address, false); | |
3422 | } | |
3423 | ||
3424 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3425 | u64 address) | |
3426 | { | |
3f4b87b9 | 3427 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3428 | unsigned long flags; |
3429 | int ret; | |
3430 | ||
3431 | spin_lock_irqsave(&domain->lock, flags); | |
3432 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3433 | spin_unlock_irqrestore(&domain->lock, flags); | |
3434 | ||
3435 | return ret; | |
3436 | } | |
3437 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3438 | ||
3439 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3440 | { | |
3441 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3442 | true); | |
3443 | } | |
3444 | ||
3445 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3446 | { | |
3f4b87b9 | 3447 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3448 | unsigned long flags; |
3449 | int ret; | |
3450 | ||
3451 | spin_lock_irqsave(&domain->lock, flags); | |
3452 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3453 | spin_unlock_irqrestore(&domain->lock, flags); | |
3454 | ||
3455 | return ret; | |
3456 | } | |
3457 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3458 | ||
b16137b1 JR |
3459 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3460 | { | |
3461 | int index; | |
3462 | u64 *pte; | |
3463 | ||
3464 | while (true) { | |
3465 | ||
3466 | index = (pasid >> (9 * level)) & 0x1ff; | |
3467 | pte = &root[index]; | |
3468 | ||
3469 | if (level == 0) | |
3470 | break; | |
3471 | ||
3472 | if (!(*pte & GCR3_VALID)) { | |
3473 | if (!alloc) | |
3474 | return NULL; | |
3475 | ||
3476 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3477 | if (root == NULL) | |
3478 | return NULL; | |
3479 | ||
2543a786 | 3480 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
3481 | } |
3482 | ||
2543a786 | 3483 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
3484 | |
3485 | level -= 1; | |
3486 | } | |
3487 | ||
3488 | return pte; | |
3489 | } | |
3490 | ||
3491 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3492 | unsigned long cr3) | |
3493 | { | |
3494 | u64 *pte; | |
3495 | ||
3496 | if (domain->mode != PAGE_MODE_NONE) | |
3497 | return -EINVAL; | |
3498 | ||
3499 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3500 | if (pte == NULL) | |
3501 | return -ENOMEM; | |
3502 | ||
3503 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3504 | ||
3505 | return __amd_iommu_flush_tlb(domain, pasid); | |
3506 | } | |
3507 | ||
3508 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3509 | { | |
3510 | u64 *pte; | |
3511 | ||
3512 | if (domain->mode != PAGE_MODE_NONE) | |
3513 | return -EINVAL; | |
3514 | ||
3515 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3516 | if (pte == NULL) | |
3517 | return 0; | |
3518 | ||
3519 | *pte = 0; | |
3520 | ||
3521 | return __amd_iommu_flush_tlb(domain, pasid); | |
3522 | } | |
3523 | ||
3524 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3525 | unsigned long cr3) | |
3526 | { | |
3f4b87b9 | 3527 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3528 | unsigned long flags; |
3529 | int ret; | |
3530 | ||
3531 | spin_lock_irqsave(&domain->lock, flags); | |
3532 | ret = __set_gcr3(domain, pasid, cr3); | |
3533 | spin_unlock_irqrestore(&domain->lock, flags); | |
3534 | ||
3535 | return ret; | |
3536 | } | |
3537 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3538 | ||
3539 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3540 | { | |
3f4b87b9 | 3541 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3542 | unsigned long flags; |
3543 | int ret; | |
3544 | ||
3545 | spin_lock_irqsave(&domain->lock, flags); | |
3546 | ret = __clear_gcr3(domain, pasid); | |
3547 | spin_unlock_irqrestore(&domain->lock, flags); | |
3548 | ||
3549 | return ret; | |
3550 | } | |
3551 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3552 | |
3553 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3554 | int status, int tag) | |
3555 | { | |
3556 | struct iommu_dev_data *dev_data; | |
3557 | struct amd_iommu *iommu; | |
3558 | struct iommu_cmd cmd; | |
3559 | ||
3560 | dev_data = get_dev_data(&pdev->dev); | |
3561 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3562 | ||
3563 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3564 | tag, dev_data->pri_tlp); | |
3565 | ||
3566 | return iommu_queue_command(iommu, &cmd); | |
3567 | } | |
3568 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3569 | |
3570 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3571 | { | |
3f4b87b9 | 3572 | struct protection_domain *pdomain; |
f3572db8 | 3573 | |
3f4b87b9 JR |
3574 | pdomain = get_domain(&pdev->dev); |
3575 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3576 | return NULL; |
3577 | ||
3578 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3579 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3580 | return NULL; |
3581 | ||
3f4b87b9 | 3582 | return &pdomain->domain; |
f3572db8 JR |
3583 | } |
3584 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3585 | |
3586 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3587 | { | |
3588 | struct iommu_dev_data *dev_data; | |
3589 | ||
3590 | if (!amd_iommu_v2_supported()) | |
3591 | return; | |
3592 | ||
3593 | dev_data = get_dev_data(&pdev->dev); | |
3594 | dev_data->errata |= (1 << erratum); | |
3595 | } | |
3596 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3597 | |
3598 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3599 | struct amd_iommu_device_info *info) | |
3600 | { | |
3601 | int max_pasids; | |
3602 | int pos; | |
3603 | ||
3604 | if (pdev == NULL || info == NULL) | |
3605 | return -EINVAL; | |
3606 | ||
3607 | if (!amd_iommu_v2_supported()) | |
3608 | return -EINVAL; | |
3609 | ||
3610 | memset(info, 0, sizeof(*info)); | |
3611 | ||
cef74409 GK |
3612 | if (!pci_ats_disabled()) { |
3613 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3614 | if (pos) | |
3615 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3616 | } | |
52efdb89 JR |
3617 | |
3618 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3619 | if (pos) | |
3620 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3621 | ||
3622 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3623 | if (pos) { | |
3624 | int features; | |
3625 | ||
3626 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3627 | max_pasids = min(max_pasids, (1 << 20)); | |
3628 | ||
3629 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3630 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3631 | ||
3632 | features = pci_pasid_features(pdev); | |
3633 | if (features & PCI_PASID_CAP_EXEC) | |
3634 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3635 | if (features & PCI_PASID_CAP_PRIV) | |
3636 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3637 | } | |
3638 | ||
3639 | return 0; | |
3640 | } | |
3641 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3642 | |
3643 | #ifdef CONFIG_IRQ_REMAP | |
3644 | ||
3645 | /***************************************************************************** | |
3646 | * | |
3647 | * Interrupt Remapping Implementation | |
3648 | * | |
3649 | *****************************************************************************/ | |
3650 | ||
7c71d306 | 3651 | static struct irq_chip amd_ir_chip; |
94c793ac | 3652 | static DEFINE_SPINLOCK(iommu_table_lock); |
7c71d306 | 3653 | |
2b324506 JR |
3654 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
3655 | { | |
3656 | u64 dte; | |
3657 | ||
3658 | dte = amd_iommu_dev_table[devid].data[2]; | |
3659 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
2543a786 | 3660 | dte |= iommu_virt_to_phys(table->table); |
2b324506 JR |
3661 | dte |= DTE_IRQ_REMAP_INTCTL; |
3662 | dte |= DTE_IRQ_TABLE_LEN; | |
3663 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3664 | ||
3665 | amd_iommu_dev_table[devid].data[2] = dte; | |
3666 | } | |
3667 | ||
df42a04b SW |
3668 | static struct irq_remap_table *get_irq_table(u16 devid) |
3669 | { | |
3670 | struct irq_remap_table *table; | |
3671 | ||
3672 | if (WARN_ONCE(!amd_iommu_rlookup_table[devid], | |
3673 | "%s: no iommu for devid %x\n", __func__, devid)) | |
3674 | return NULL; | |
3675 | ||
3676 | table = irq_lookup_table[devid]; | |
3677 | if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid)) | |
3678 | return NULL; | |
3679 | ||
3680 | return table; | |
3681 | } | |
3682 | ||
993ca6e0 SAS |
3683 | static struct irq_remap_table *__alloc_irq_table(void) |
3684 | { | |
3685 | struct irq_remap_table *table; | |
3686 | ||
3687 | table = kzalloc(sizeof(*table), GFP_KERNEL); | |
3688 | if (!table) | |
3689 | return NULL; | |
3690 | ||
3691 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL); | |
3692 | if (!table->table) { | |
3693 | kfree(table); | |
3694 | return NULL; | |
3695 | } | |
3696 | raw_spin_lock_init(&table->lock); | |
3697 | ||
3698 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) | |
3699 | memset(table->table, 0, | |
3700 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3701 | else | |
3702 | memset(table->table, 0, | |
3703 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
3704 | return table; | |
3705 | } | |
3706 | ||
2fcc1e8a SAS |
3707 | static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid, |
3708 | struct irq_remap_table *table) | |
3709 | { | |
3710 | irq_lookup_table[devid] = table; | |
3711 | set_dte_irq_entry(devid, table); | |
3712 | iommu_flush_dte(iommu, devid); | |
3713 | } | |
3714 | ||
fde65dd3 | 3715 | static struct irq_remap_table *alloc_irq_table(u16 devid) |
2b324506 JR |
3716 | { |
3717 | struct irq_remap_table *table = NULL; | |
993ca6e0 | 3718 | struct irq_remap_table *new_table = NULL; |
2b324506 JR |
3719 | struct amd_iommu *iommu; |
3720 | unsigned long flags; | |
3721 | u16 alias; | |
3722 | ||
ea6166f4 | 3723 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 JR |
3724 | |
3725 | iommu = amd_iommu_rlookup_table[devid]; | |
3726 | if (!iommu) | |
3727 | goto out_unlock; | |
3728 | ||
3729 | table = irq_lookup_table[devid]; | |
3730 | if (table) | |
09284b9c | 3731 | goto out_unlock; |
2b324506 JR |
3732 | |
3733 | alias = amd_iommu_alias_table[devid]; | |
3734 | table = irq_lookup_table[alias]; | |
3735 | if (table) { | |
2fcc1e8a | 3736 | set_remap_table_entry(iommu, devid, table); |
993ca6e0 | 3737 | goto out_wait; |
2b324506 | 3738 | } |
993ca6e0 | 3739 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 JR |
3740 | |
3741 | /* Nothing there yet, allocate new irq remapping table */ | |
993ca6e0 SAS |
3742 | new_table = __alloc_irq_table(); |
3743 | if (!new_table) | |
3744 | return NULL; | |
197887f0 | 3745 | |
993ca6e0 | 3746 | spin_lock_irqsave(&iommu_table_lock, flags); |
2b324506 | 3747 | |
993ca6e0 SAS |
3748 | table = irq_lookup_table[devid]; |
3749 | if (table) | |
09284b9c | 3750 | goto out_unlock; |
2b324506 | 3751 | |
993ca6e0 SAS |
3752 | table = irq_lookup_table[alias]; |
3753 | if (table) { | |
3754 | set_remap_table_entry(iommu, devid, table); | |
3755 | goto out_wait; | |
2b324506 JR |
3756 | } |
3757 | ||
993ca6e0 SAS |
3758 | table = new_table; |
3759 | new_table = NULL; | |
2b324506 | 3760 | |
2fcc1e8a SAS |
3761 | set_remap_table_entry(iommu, devid, table); |
3762 | if (devid != alias) | |
3763 | set_remap_table_entry(iommu, alias, table); | |
2b324506 | 3764 | |
993ca6e0 | 3765 | out_wait: |
2b324506 JR |
3766 | iommu_completion_wait(iommu); |
3767 | ||
3768 | out_unlock: | |
ea6166f4 | 3769 | spin_unlock_irqrestore(&iommu_table_lock, flags); |
2b324506 | 3770 | |
993ca6e0 SAS |
3771 | if (new_table) { |
3772 | kmem_cache_free(amd_iommu_irq_cache, new_table->table); | |
3773 | kfree(new_table); | |
3774 | } | |
2b324506 JR |
3775 | return table; |
3776 | } | |
3777 | ||
37946d95 | 3778 | static int alloc_irq_index(u16 devid, int count, bool align) |
2b324506 JR |
3779 | { |
3780 | struct irq_remap_table *table; | |
37946d95 | 3781 | int index, c, alignment = 1; |
2b324506 | 3782 | unsigned long flags; |
77bdab46 SS |
3783 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3784 | ||
3785 | if (!iommu) | |
3786 | return -ENODEV; | |
2b324506 | 3787 | |
fde65dd3 | 3788 | table = alloc_irq_table(devid); |
2b324506 JR |
3789 | if (!table) |
3790 | return -ENODEV; | |
3791 | ||
37946d95 JR |
3792 | if (align) |
3793 | alignment = roundup_pow_of_two(count); | |
3794 | ||
27790398 | 3795 | raw_spin_lock_irqsave(&table->lock, flags); |
2b324506 JR |
3796 | |
3797 | /* Scan table for free entries */ | |
37946d95 | 3798 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 3799 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 3800 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 3801 | c += 1; |
37946d95 JR |
3802 | } else { |
3803 | c = 0; | |
07d1c91b | 3804 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
3805 | continue; |
3806 | } | |
2b324506 JR |
3807 | |
3808 | if (c == count) { | |
2b324506 | 3809 | for (; c != 0; --c) |
77bdab46 | 3810 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3811 | |
3812 | index -= count - 1; | |
2b324506 JR |
3813 | goto out; |
3814 | } | |
07d1c91b AW |
3815 | |
3816 | index++; | |
2b324506 JR |
3817 | } |
3818 | ||
3819 | index = -ENOSPC; | |
3820 | ||
3821 | out: | |
27790398 | 3822 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3823 | |
3824 | return index; | |
3825 | } | |
3826 | ||
b9fc6b56 SS |
3827 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3828 | struct amd_ir_data *data) | |
2b324506 JR |
3829 | { |
3830 | struct irq_remap_table *table; | |
3831 | struct amd_iommu *iommu; | |
3832 | unsigned long flags; | |
880ac60e | 3833 | struct irte_ga *entry; |
2b324506 JR |
3834 | |
3835 | iommu = amd_iommu_rlookup_table[devid]; | |
3836 | if (iommu == NULL) | |
3837 | return -EINVAL; | |
3838 | ||
df42a04b | 3839 | table = get_irq_table(devid); |
2b324506 JR |
3840 | if (!table) |
3841 | return -ENOMEM; | |
3842 | ||
27790398 | 3843 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e SS |
3844 | |
3845 | entry = (struct irte_ga *)table->table; | |
3846 | entry = &entry[index]; | |
3847 | entry->lo.fields_remap.valid = 0; | |
3848 | entry->hi.val = irte->hi.val; | |
3849 | entry->lo.val = irte->lo.val; | |
3850 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3851 | if (data) |
3852 | data->ref = entry; | |
880ac60e | 3853 | |
27790398 | 3854 | raw_spin_unlock_irqrestore(&table->lock, flags); |
880ac60e SS |
3855 | |
3856 | iommu_flush_irt(iommu, devid); | |
3857 | iommu_completion_wait(iommu); | |
3858 | ||
3859 | return 0; | |
3860 | } | |
3861 | ||
3862 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3863 | { |
3864 | struct irq_remap_table *table; | |
3865 | struct amd_iommu *iommu; | |
3866 | unsigned long flags; | |
3867 | ||
3868 | iommu = amd_iommu_rlookup_table[devid]; | |
3869 | if (iommu == NULL) | |
3870 | return -EINVAL; | |
3871 | ||
df42a04b | 3872 | table = get_irq_table(devid); |
2b324506 JR |
3873 | if (!table) |
3874 | return -ENOMEM; | |
3875 | ||
27790398 | 3876 | raw_spin_lock_irqsave(&table->lock, flags); |
880ac60e | 3877 | table->table[index] = irte->val; |
27790398 | 3878 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3879 | |
3880 | iommu_flush_irt(iommu, devid); | |
3881 | iommu_completion_wait(iommu); | |
3882 | ||
3883 | return 0; | |
3884 | } | |
3885 | ||
3886 | static void free_irte(u16 devid, int index) | |
3887 | { | |
3888 | struct irq_remap_table *table; | |
3889 | struct amd_iommu *iommu; | |
3890 | unsigned long flags; | |
3891 | ||
3892 | iommu = amd_iommu_rlookup_table[devid]; | |
3893 | if (iommu == NULL) | |
3894 | return; | |
3895 | ||
df42a04b | 3896 | table = get_irq_table(devid); |
2b324506 JR |
3897 | if (!table) |
3898 | return; | |
3899 | ||
27790398 | 3900 | raw_spin_lock_irqsave(&table->lock, flags); |
77bdab46 | 3901 | iommu->irte_ops->clear_allocated(table, index); |
27790398 | 3902 | raw_spin_unlock_irqrestore(&table->lock, flags); |
2b324506 JR |
3903 | |
3904 | iommu_flush_irt(iommu, devid); | |
3905 | iommu_completion_wait(iommu); | |
3906 | } | |
3907 | ||
880ac60e SS |
3908 | static void irte_prepare(void *entry, |
3909 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3910 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3911 | { |
3912 | union irte *irte = (union irte *) entry; | |
3913 | ||
3914 | irte->val = 0; | |
3915 | irte->fields.vector = vector; | |
3916 | irte->fields.int_type = delivery_mode; | |
3917 | irte->fields.destination = dest_apicid; | |
3918 | irte->fields.dm = dest_mode; | |
3919 | irte->fields.valid = 1; | |
3920 | } | |
3921 | ||
3922 | static void irte_ga_prepare(void *entry, | |
3923 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3924 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3925 | { |
3926 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3927 | ||
3928 | irte->lo.val = 0; | |
3929 | irte->hi.val = 0; | |
880ac60e SS |
3930 | irte->lo.fields_remap.int_type = delivery_mode; |
3931 | irte->lo.fields_remap.dm = dest_mode; | |
3932 | irte->hi.fields.vector = vector; | |
90fcffd9 SS |
3933 | irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); |
3934 | irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); | |
880ac60e SS |
3935 | irte->lo.fields_remap.valid = 1; |
3936 | } | |
3937 | ||
3938 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3939 | { | |
3940 | union irte *irte = (union irte *) entry; | |
3941 | ||
3942 | irte->fields.valid = 1; | |
3943 | modify_irte(devid, index, irte); | |
3944 | } | |
3945 | ||
3946 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3947 | { | |
3948 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3949 | ||
3950 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3951 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3952 | } |
3953 | ||
3954 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3955 | { | |
3956 | union irte *irte = (union irte *) entry; | |
3957 | ||
3958 | irte->fields.valid = 0; | |
3959 | modify_irte(devid, index, irte); | |
3960 | } | |
3961 | ||
3962 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3963 | { | |
3964 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3965 | ||
3966 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3967 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3968 | } |
3969 | ||
3970 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3971 | u8 vector, u32 dest_apicid) | |
3972 | { | |
3973 | union irte *irte = (union irte *) entry; | |
3974 | ||
3975 | irte->fields.vector = vector; | |
3976 | irte->fields.destination = dest_apicid; | |
3977 | modify_irte(devid, index, irte); | |
3978 | } | |
3979 | ||
3980 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3981 | u8 vector, u32 dest_apicid) | |
3982 | { | |
3983 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3984 | ||
01ee04ba | 3985 | if (!irte->lo.fields_remap.guest_mode) { |
d98de49a | 3986 | irte->hi.fields.vector = vector; |
90fcffd9 SS |
3987 | irte->lo.fields_remap.destination = |
3988 | APICID_TO_IRTE_DEST_LO(dest_apicid); | |
3989 | irte->hi.fields.destination = | |
3990 | APICID_TO_IRTE_DEST_HI(dest_apicid); | |
d98de49a SS |
3991 | modify_irte_ga(devid, index, irte, NULL); |
3992 | } | |
880ac60e SS |
3993 | } |
3994 | ||
77bdab46 | 3995 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3996 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3997 | { | |
3998 | table->table[index] = IRTE_ALLOCATED; | |
3999 | } | |
4000 | ||
4001 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
4002 | { | |
4003 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4004 | struct irte_ga *irte = &ptr[index]; | |
4005 | ||
4006 | memset(&irte->lo.val, 0, sizeof(u64)); | |
4007 | memset(&irte->hi.val, 0, sizeof(u64)); | |
4008 | irte->hi.fields.vector = 0xff; | |
4009 | } | |
4010 | ||
4011 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
4012 | { | |
4013 | union irte *ptr = (union irte *)table->table; | |
4014 | union irte *irte = &ptr[index]; | |
4015 | ||
4016 | return irte->val != 0; | |
4017 | } | |
4018 | ||
4019 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
4020 | { | |
4021 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4022 | struct irte_ga *irte = &ptr[index]; | |
4023 | ||
4024 | return irte->hi.fields.vector != 0; | |
4025 | } | |
4026 | ||
4027 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
4028 | { | |
4029 | table->table[index] = 0; | |
4030 | } | |
4031 | ||
4032 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
4033 | { | |
4034 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
4035 | struct irte_ga *irte = &ptr[index]; | |
4036 | ||
4037 | memset(&irte->lo.val, 0, sizeof(u64)); | |
4038 | memset(&irte->hi.val, 0, sizeof(u64)); | |
4039 | } | |
4040 | ||
7c71d306 | 4041 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 4042 | { |
7c71d306 | 4043 | int devid = -1; |
5527de74 | 4044 | |
7c71d306 JL |
4045 | switch (info->type) { |
4046 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4047 | devid = get_ioapic_devid(info->ioapic_id); | |
4048 | break; | |
4049 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4050 | devid = get_hpet_devid(info->hpet_id); | |
4051 | break; | |
4052 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4053 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4054 | devid = get_device_id(&info->msi_dev->dev); | |
4055 | break; | |
4056 | default: | |
4057 | BUG_ON(1); | |
4058 | break; | |
4059 | } | |
5527de74 | 4060 | |
7c71d306 JL |
4061 | return devid; |
4062 | } | |
5527de74 | 4063 | |
7c71d306 JL |
4064 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4065 | { | |
4066 | struct amd_iommu *iommu; | |
4067 | int devid; | |
5527de74 | 4068 | |
7c71d306 JL |
4069 | if (!info) |
4070 | return NULL; | |
5527de74 | 4071 | |
7c71d306 JL |
4072 | devid = get_devid(info); |
4073 | if (devid >= 0) { | |
4074 | iommu = amd_iommu_rlookup_table[devid]; | |
4075 | if (iommu) | |
4076 | return iommu->ir_domain; | |
4077 | } | |
5527de74 | 4078 | |
7c71d306 | 4079 | return NULL; |
5527de74 JR |
4080 | } |
4081 | ||
7c71d306 | 4082 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4083 | { |
7c71d306 JL |
4084 | struct amd_iommu *iommu; |
4085 | int devid; | |
5527de74 | 4086 | |
7c71d306 JL |
4087 | if (!info) |
4088 | return NULL; | |
5527de74 | 4089 | |
7c71d306 JL |
4090 | switch (info->type) { |
4091 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4092 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4093 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 4094 | if (devid < 0) |
7aba6cb9 WZ |
4095 | return NULL; |
4096 | ||
1fb260bc DC |
4097 | iommu = amd_iommu_rlookup_table[devid]; |
4098 | if (iommu) | |
4099 | return iommu->msi_domain; | |
7c71d306 JL |
4100 | break; |
4101 | default: | |
4102 | break; | |
4103 | } | |
5527de74 | 4104 | |
7c71d306 JL |
4105 | return NULL; |
4106 | } | |
5527de74 | 4107 | |
6b474b82 | 4108 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4109 | .prepare = amd_iommu_prepare, |
4110 | .enable = amd_iommu_enable, | |
4111 | .disable = amd_iommu_disable, | |
4112 | .reenable = amd_iommu_reenable, | |
4113 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4114 | .get_ir_irq_domain = get_ir_irq_domain, |
4115 | .get_irq_domain = get_irq_domain, | |
4116 | }; | |
5527de74 | 4117 | |
7c71d306 JL |
4118 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4119 | struct irq_cfg *irq_cfg, | |
4120 | struct irq_alloc_info *info, | |
4121 | int devid, int index, int sub_handle) | |
4122 | { | |
4123 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4124 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4125 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4126 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4127 | ||
4128 | if (!iommu) | |
4129 | return; | |
5527de74 | 4130 | |
7c71d306 JL |
4131 | data->irq_2_irte.devid = devid; |
4132 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4133 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4134 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 4135 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
4136 | |
4137 | switch (info->type) { | |
4138 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4139 | /* Setup IOAPIC entry */ | |
4140 | entry = info->ioapic_entry; | |
4141 | info->ioapic_entry = NULL; | |
4142 | memset(entry, 0, sizeof(*entry)); | |
4143 | entry->vector = index; | |
4144 | entry->mask = 0; | |
4145 | entry->trigger = info->ioapic_trigger; | |
4146 | entry->polarity = info->ioapic_polarity; | |
4147 | /* Mask level triggered irqs. */ | |
4148 | if (info->ioapic_trigger) | |
4149 | entry->mask = 1; | |
4150 | break; | |
5527de74 | 4151 | |
7c71d306 JL |
4152 | case X86_IRQ_ALLOC_TYPE_HPET: |
4153 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4154 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4155 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4156 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4157 | msg->data = irte_info->index; | |
4158 | break; | |
5527de74 | 4159 | |
7c71d306 JL |
4160 | default: |
4161 | BUG_ON(1); | |
4162 | break; | |
4163 | } | |
5527de74 JR |
4164 | } |
4165 | ||
880ac60e SS |
4166 | struct amd_irte_ops irte_32_ops = { |
4167 | .prepare = irte_prepare, | |
4168 | .activate = irte_activate, | |
4169 | .deactivate = irte_deactivate, | |
4170 | .set_affinity = irte_set_affinity, | |
4171 | .set_allocated = irte_set_allocated, | |
4172 | .is_allocated = irte_is_allocated, | |
4173 | .clear_allocated = irte_clear_allocated, | |
4174 | }; | |
4175 | ||
4176 | struct amd_irte_ops irte_128_ops = { | |
4177 | .prepare = irte_ga_prepare, | |
4178 | .activate = irte_ga_activate, | |
4179 | .deactivate = irte_ga_deactivate, | |
4180 | .set_affinity = irte_ga_set_affinity, | |
4181 | .set_allocated = irte_ga_set_allocated, | |
4182 | .is_allocated = irte_ga_is_allocated, | |
4183 | .clear_allocated = irte_ga_clear_allocated, | |
4184 | }; | |
4185 | ||
7c71d306 JL |
4186 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4187 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4188 | { |
7c71d306 JL |
4189 | struct irq_alloc_info *info = arg; |
4190 | struct irq_data *irq_data; | |
77bdab46 | 4191 | struct amd_ir_data *data = NULL; |
5527de74 | 4192 | struct irq_cfg *cfg; |
7c71d306 | 4193 | int i, ret, devid; |
29d049be | 4194 | int index; |
5527de74 | 4195 | |
7c71d306 JL |
4196 | if (!info) |
4197 | return -EINVAL; | |
4198 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4199 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4200 | return -EINVAL; |
4201 | ||
7c71d306 JL |
4202 | /* |
4203 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4204 | * to support multiple MSI interrupts. | |
4205 | */ | |
4206 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4207 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4208 | |
7c71d306 JL |
4209 | devid = get_devid(info); |
4210 | if (devid < 0) | |
4211 | return -EINVAL; | |
5527de74 | 4212 | |
7c71d306 JL |
4213 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4214 | if (ret < 0) | |
4215 | return ret; | |
0b4d48cb | 4216 | |
7c71d306 | 4217 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
fde65dd3 SAS |
4218 | struct irq_remap_table *table; |
4219 | struct amd_iommu *iommu; | |
4220 | ||
4221 | table = alloc_irq_table(devid); | |
4222 | if (table) { | |
4223 | if (!table->min_index) { | |
4224 | /* | |
4225 | * Keep the first 32 indexes free for IOAPIC | |
4226 | * interrupts. | |
4227 | */ | |
4228 | table->min_index = 32; | |
4229 | iommu = amd_iommu_rlookup_table[devid]; | |
4230 | for (i = 0; i < 32; ++i) | |
4231 | iommu->irte_ops->set_allocated(table, i); | |
4232 | } | |
4233 | WARN_ON(table->min_index != 32); | |
7c71d306 | 4234 | index = info->ioapic_pin; |
fde65dd3 | 4235 | } else { |
29d049be | 4236 | index = -ENOMEM; |
fde65dd3 | 4237 | } |
7c71d306 | 4238 | } else { |
53b9ec3f JR |
4239 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
4240 | ||
4241 | index = alloc_irq_index(devid, nr_irqs, align); | |
7c71d306 JL |
4242 | } |
4243 | if (index < 0) { | |
4244 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 4245 | ret = index; |
7c71d306 JL |
4246 | goto out_free_parent; |
4247 | } | |
0b4d48cb | 4248 | |
7c71d306 JL |
4249 | for (i = 0; i < nr_irqs; i++) { |
4250 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4251 | cfg = irqd_cfg(irq_data); | |
4252 | if (!irq_data || !cfg) { | |
4253 | ret = -EINVAL; | |
4254 | goto out_free_data; | |
4255 | } | |
0b4d48cb | 4256 | |
a130e69f JR |
4257 | ret = -ENOMEM; |
4258 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4259 | if (!data) | |
4260 | goto out_free_data; | |
4261 | ||
77bdab46 SS |
4262 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4263 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4264 | else | |
4265 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4266 | GFP_KERNEL); | |
4267 | if (!data->entry) { | |
4268 | kfree(data); | |
4269 | goto out_free_data; | |
4270 | } | |
4271 | ||
7c71d306 JL |
4272 | irq_data->hwirq = (devid << 16) + i; |
4273 | irq_data->chip_data = data; | |
4274 | irq_data->chip = &amd_ir_chip; | |
4275 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4276 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4277 | } | |
a130e69f | 4278 | |
7c71d306 | 4279 | return 0; |
0b4d48cb | 4280 | |
7c71d306 JL |
4281 | out_free_data: |
4282 | for (i--; i >= 0; i--) { | |
4283 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4284 | if (irq_data) | |
4285 | kfree(irq_data->chip_data); | |
4286 | } | |
4287 | for (i = 0; i < nr_irqs; i++) | |
4288 | free_irte(devid, index + i); | |
4289 | out_free_parent: | |
4290 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4291 | return ret; | |
0b4d48cb JR |
4292 | } |
4293 | ||
7c71d306 JL |
4294 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4295 | unsigned int nr_irqs) | |
0b4d48cb | 4296 | { |
7c71d306 JL |
4297 | struct irq_2_irte *irte_info; |
4298 | struct irq_data *irq_data; | |
4299 | struct amd_ir_data *data; | |
4300 | int i; | |
0b4d48cb | 4301 | |
7c71d306 JL |
4302 | for (i = 0; i < nr_irqs; i++) { |
4303 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4304 | if (irq_data && irq_data->chip_data) { | |
4305 | data = irq_data->chip_data; | |
4306 | irte_info = &data->irq_2_irte; | |
4307 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4308 | kfree(data->entry); |
7c71d306 JL |
4309 | kfree(data); |
4310 | } | |
4311 | } | |
4312 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4313 | } | |
0b4d48cb | 4314 | |
5ba204a1 TG |
4315 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
4316 | struct amd_ir_data *ir_data, | |
4317 | struct irq_2_irte *irte_info, | |
4318 | struct irq_cfg *cfg); | |
4319 | ||
72491643 | 4320 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 4321 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
4322 | { |
4323 | struct amd_ir_data *data = irq_data->chip_data; | |
4324 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4325 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
5ba204a1 | 4326 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 4327 | |
5ba204a1 TG |
4328 | if (!iommu) |
4329 | return 0; | |
4330 | ||
4331 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4332 | irte_info->index); | |
4333 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 4334 | return 0; |
0b4d48cb JR |
4335 | } |
4336 | ||
7c71d306 JL |
4337 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4338 | struct irq_data *irq_data) | |
0b4d48cb | 4339 | { |
7c71d306 JL |
4340 | struct amd_ir_data *data = irq_data->chip_data; |
4341 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4342 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4343 | |
77bdab46 SS |
4344 | if (iommu) |
4345 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4346 | irte_info->index); | |
7c71d306 | 4347 | } |
0b4d48cb | 4348 | |
e2f9d45f | 4349 | static const struct irq_domain_ops amd_ir_domain_ops = { |
7c71d306 JL |
4350 | .alloc = irq_remapping_alloc, |
4351 | .free = irq_remapping_free, | |
4352 | .activate = irq_remapping_activate, | |
4353 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4354 | }; |
0b4d48cb | 4355 | |
b9fc6b56 SS |
4356 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4357 | { | |
4358 | struct amd_iommu *iommu; | |
4359 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4360 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4361 | struct amd_ir_data *ir_data = data->chip_data; | |
4362 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4363 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
d98de49a SS |
4364 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
4365 | ||
4366 | /* Note: | |
4367 | * This device has never been set up for guest mode. | |
4368 | * we should not modify the IRTE | |
4369 | */ | |
4370 | if (!dev_data || !dev_data->use_vapic) | |
4371 | return 0; | |
b9fc6b56 SS |
4372 | |
4373 | pi_data->ir_data = ir_data; | |
4374 | ||
4375 | /* Note: | |
4376 | * SVM tries to set up for VAPIC mode, but we are in | |
4377 | * legacy mode. So, we force legacy mode instead. | |
4378 | */ | |
4379 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
101fa037 | 4380 | pr_debug("%s: Fall back to using intr legacy remap\n", |
b9fc6b56 SS |
4381 | __func__); |
4382 | pi_data->is_guest_mode = false; | |
4383 | } | |
4384 | ||
4385 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4386 | if (iommu == NULL) | |
4387 | return -EINVAL; | |
4388 | ||
4389 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4390 | if (pi_data->is_guest_mode) { | |
4391 | /* Setting */ | |
4392 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4393 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
efe6f241 | 4394 | irte->lo.fields_vapic.ga_log_intr = 1; |
b9fc6b56 SS |
4395 | irte->lo.fields_vapic.guest_mode = 1; |
4396 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4397 | ||
4398 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4399 | } else { | |
4400 | /* Un-Setting */ | |
4401 | struct irq_cfg *cfg = irqd_cfg(data); | |
4402 | ||
4403 | irte->hi.val = 0; | |
4404 | irte->lo.val = 0; | |
4405 | irte->hi.fields.vector = cfg->vector; | |
4406 | irte->lo.fields_remap.guest_mode = 0; | |
90fcffd9 SS |
4407 | irte->lo.fields_remap.destination = |
4408 | APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); | |
4409 | irte->hi.fields.destination = | |
4410 | APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); | |
b9fc6b56 SS |
4411 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; |
4412 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4413 | ||
4414 | /* | |
4415 | * This communicates the ga_tag back to the caller | |
4416 | * so that it can do all the necessary clean up. | |
4417 | */ | |
4418 | ir_data->cached_ga_tag = 0; | |
4419 | } | |
4420 | ||
4421 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4422 | } | |
4423 | ||
5ba204a1 TG |
4424 | |
4425 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
4426 | struct amd_ir_data *ir_data, | |
4427 | struct irq_2_irte *irte_info, | |
4428 | struct irq_cfg *cfg) | |
4429 | { | |
4430 | ||
4431 | /* | |
4432 | * Atomically updates the IRTE with the new destination, vector | |
4433 | * and flushes the interrupt entry cache. | |
4434 | */ | |
4435 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
4436 | irte_info->index, cfg->vector, | |
4437 | cfg->dest_apicid); | |
4438 | } | |
4439 | ||
7c71d306 JL |
4440 | static int amd_ir_set_affinity(struct irq_data *data, |
4441 | const struct cpumask *mask, bool force) | |
4442 | { | |
4443 | struct amd_ir_data *ir_data = data->chip_data; | |
4444 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4445 | struct irq_cfg *cfg = irqd_cfg(data); | |
4446 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4447 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4448 | int ret; |
0b4d48cb | 4449 | |
77bdab46 SS |
4450 | if (!iommu) |
4451 | return -ENODEV; | |
4452 | ||
7c71d306 JL |
4453 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4454 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4455 | return ret; | |
0b4d48cb | 4456 | |
5ba204a1 | 4457 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
4458 | /* |
4459 | * After this point, all the interrupts will start arriving | |
4460 | * at the new destination. So, time to cleanup the previous | |
4461 | * vector allocation. | |
4462 | */ | |
c6c2002b | 4463 | send_cleanup_vector(cfg); |
7c71d306 JL |
4464 | |
4465 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4466 | } |
4467 | ||
7c71d306 | 4468 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4469 | { |
7c71d306 | 4470 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4471 | |
7c71d306 JL |
4472 | *msg = ir_data->msi_entry; |
4473 | } | |
d976195c | 4474 | |
7c71d306 | 4475 | static struct irq_chip amd_ir_chip = { |
290be194 | 4476 | .name = "AMD-IR", |
8a2b7d14 | 4477 | .irq_ack = apic_ack_irq, |
290be194 TG |
4478 | .irq_set_affinity = amd_ir_set_affinity, |
4479 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4480 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 4481 | }; |
d976195c | 4482 | |
7c71d306 JL |
4483 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4484 | { | |
3e49a818 TG |
4485 | struct fwnode_handle *fn; |
4486 | ||
4487 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4488 | if (!fn) | |
4489 | return -ENOMEM; | |
4490 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
4491 | irq_domain_free_fwnode(fn); | |
7c71d306 JL |
4492 | if (!iommu->ir_domain) |
4493 | return -ENOMEM; | |
d976195c | 4494 | |
7c71d306 | 4495 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
4496 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
4497 | "AMD-IR-MSI", | |
4498 | iommu->index); | |
d976195c JR |
4499 | return 0; |
4500 | } | |
8dbea3fd SS |
4501 | |
4502 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4503 | { | |
4504 | unsigned long flags; | |
4505 | struct amd_iommu *iommu; | |
4fde541c | 4506 | struct irq_remap_table *table; |
8dbea3fd SS |
4507 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; |
4508 | int devid = ir_data->irq_2_irte.devid; | |
4509 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4510 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4511 | ||
4512 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4513 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4514 | return 0; | |
4515 | ||
4516 | iommu = amd_iommu_rlookup_table[devid]; | |
4517 | if (!iommu) | |
4518 | return -ENODEV; | |
4519 | ||
4fde541c SAS |
4520 | table = get_irq_table(devid); |
4521 | if (!table) | |
8dbea3fd SS |
4522 | return -ENODEV; |
4523 | ||
4fde541c | 4524 | raw_spin_lock_irqsave(&table->lock, flags); |
8dbea3fd SS |
4525 | |
4526 | if (ref->lo.fields_vapic.guest_mode) { | |
90fcffd9 SS |
4527 | if (cpu >= 0) { |
4528 | ref->lo.fields_vapic.destination = | |
4529 | APICID_TO_IRTE_DEST_LO(cpu); | |
4530 | ref->hi.fields.destination = | |
4531 | APICID_TO_IRTE_DEST_HI(cpu); | |
4532 | } | |
8dbea3fd SS |
4533 | ref->lo.fields_vapic.is_run = is_run; |
4534 | barrier(); | |
4535 | } | |
4536 | ||
4fde541c | 4537 | raw_spin_unlock_irqrestore(&table->lock, flags); |
8dbea3fd SS |
4538 | |
4539 | iommu_flush_irt(iommu, devid); | |
4540 | iommu_completion_wait(iommu); | |
4541 | return 0; | |
4542 | } | |
4543 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4544 | #endif |