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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
cb41ed85 | 22 | #include <linux/pci-ats.h> |
a66022c4 | 23 | #include <linux/bitmap.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
7f26508b | 25 | #include <linux/debugfs.h> |
b6c02715 | 26 | #include <linux/scatterlist.h> |
51491367 | 27 | #include <linux/dma-mapping.h> |
b6c02715 | 28 | #include <linux/iommu-helper.h> |
c156e347 | 29 | #include <linux/iommu.h> |
815b33fd | 30 | #include <linux/delay.h> |
403f81d8 | 31 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
32 | #include <linux/notifier.h> |
33 | #include <linux/export.h> | |
2b324506 JR |
34 | #include <linux/irq.h> |
35 | #include <linux/msi.h> | |
3b839a57 | 36 | #include <linux/dma-contiguous.h> |
7c71d306 | 37 | #include <linux/irqdomain.h> |
2b324506 JR |
38 | #include <asm/irq_remapping.h> |
39 | #include <asm/io_apic.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/hw_irq.h> | |
17f5b569 | 42 | #include <asm/msidef.h> |
b6c02715 | 43 | #include <asm/proto.h> |
46a7fa27 | 44 | #include <asm/iommu.h> |
1d9b16d1 | 45 | #include <asm/gart.h> |
27c2127a | 46 | #include <asm/dma.h> |
403f81d8 JR |
47 | |
48 | #include "amd_iommu_proto.h" | |
49 | #include "amd_iommu_types.h" | |
6b474b82 | 50 | #include "irq_remapping.h" |
b6c02715 JR |
51 | |
52 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
53 | ||
815b33fd | 54 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 55 | |
aa3de9c0 OBC |
56 | /* |
57 | * This bitmap is used to advertise the page sizes our hardware support | |
58 | * to the IOMMU core, which will then use this information to split | |
59 | * physically contiguous memory regions it is mapping into page sizes | |
60 | * that we support. | |
61 | * | |
954e3dd8 | 62 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 63 | */ |
954e3dd8 | 64 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 65 | |
b6c02715 JR |
66 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
67 | ||
8fa5f802 JR |
68 | /* List of all available dev_data structures */ |
69 | static LIST_HEAD(dev_data_list); | |
70 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
71 | ||
6efed63b JR |
72 | LIST_HEAD(ioapic_map); |
73 | LIST_HEAD(hpet_map); | |
74 | ||
0feae533 JR |
75 | /* |
76 | * Domain for untranslated devices - only allocated | |
77 | * if iommu=pt passed on kernel cmd line. | |
78 | */ | |
b22f6434 | 79 | static const struct iommu_ops amd_iommu_ops; |
26961efe | 80 | |
72e1dcc4 | 81 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 82 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 83 | |
ac1534a5 JR |
84 | static struct dma_map_ops amd_iommu_dma_ops; |
85 | ||
50917e26 JR |
86 | /* |
87 | * This struct contains device specific data for the IOMMU | |
88 | */ | |
89 | struct iommu_dev_data { | |
90 | struct list_head list; /* For domain->dev_list */ | |
91 | struct list_head dev_data_list; /* For global dev_data_list */ | |
f251e187 | 92 | struct list_head alias_list; /* Link alias-groups together */ |
50917e26 JR |
93 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
94 | struct protection_domain *domain; /* Domain the device is bound to */ | |
50917e26 JR |
95 | u16 devid; /* PCI Device ID */ |
96 | bool iommu_v2; /* Device can make use of IOMMUv2 */ | |
1e6a7b04 | 97 | bool passthrough; /* Device is identity mapped */ |
50917e26 JR |
98 | struct { |
99 | bool enabled; | |
100 | int qdep; | |
101 | } ats; /* ATS state */ | |
102 | bool pri_tlp; /* PASID TLB required for | |
103 | PPR completions */ | |
104 | u32 errata; /* Bitmap for errata to apply */ | |
105 | }; | |
106 | ||
431b2a20 JR |
107 | /* |
108 | * general struct to manage commands send to an IOMMU | |
109 | */ | |
d6449536 | 110 | struct iommu_cmd { |
b6c02715 JR |
111 | u32 data[4]; |
112 | }; | |
113 | ||
05152a04 JR |
114 | struct kmem_cache *amd_iommu_irq_cache; |
115 | ||
04bfdd84 | 116 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 117 | static int protection_domain_init(struct protection_domain *domain); |
c1eee67b | 118 | |
15898bbc JR |
119 | /**************************************************************************** |
120 | * | |
121 | * Helper functions | |
122 | * | |
123 | ****************************************************************************/ | |
124 | ||
3f4b87b9 JR |
125 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
126 | { | |
127 | return container_of(dom, struct protection_domain, domain); | |
128 | } | |
129 | ||
f62dda66 | 130 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
131 | { |
132 | struct iommu_dev_data *dev_data; | |
133 | unsigned long flags; | |
134 | ||
135 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
136 | if (!dev_data) | |
137 | return NULL; | |
138 | ||
f251e187 JR |
139 | INIT_LIST_HEAD(&dev_data->alias_list); |
140 | ||
f62dda66 | 141 | dev_data->devid = devid; |
8fa5f802 JR |
142 | |
143 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
144 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
145 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
146 | ||
147 | return dev_data; | |
148 | } | |
149 | ||
150 | static void free_dev_data(struct iommu_dev_data *dev_data) | |
151 | { | |
152 | unsigned long flags; | |
153 | ||
154 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
155 | list_del(&dev_data->dev_data_list); | |
156 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
157 | ||
158 | kfree(dev_data); | |
159 | } | |
160 | ||
3b03bb74 JR |
161 | static struct iommu_dev_data *search_dev_data(u16 devid) |
162 | { | |
163 | struct iommu_dev_data *dev_data; | |
164 | unsigned long flags; | |
165 | ||
166 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
167 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
168 | if (dev_data->devid == devid) | |
169 | goto out_unlock; | |
170 | } | |
171 | ||
172 | dev_data = NULL; | |
173 | ||
174 | out_unlock: | |
175 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
176 | ||
177 | return dev_data; | |
178 | } | |
179 | ||
180 | static struct iommu_dev_data *find_dev_data(u16 devid) | |
181 | { | |
182 | struct iommu_dev_data *dev_data; | |
183 | ||
184 | dev_data = search_dev_data(devid); | |
185 | ||
186 | if (dev_data == NULL) | |
187 | dev_data = alloc_dev_data(devid); | |
188 | ||
189 | return dev_data; | |
190 | } | |
191 | ||
15898bbc JR |
192 | static inline u16 get_device_id(struct device *dev) |
193 | { | |
194 | struct pci_dev *pdev = to_pci_dev(dev); | |
195 | ||
6f2729ba | 196 | return PCI_DEVID(pdev->bus->number, pdev->devfn); |
15898bbc JR |
197 | } |
198 | ||
657cbb6b JR |
199 | static struct iommu_dev_data *get_dev_data(struct device *dev) |
200 | { | |
201 | return dev->archdata.iommu; | |
202 | } | |
203 | ||
5abcdba4 JR |
204 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
205 | { | |
206 | static const int caps[] = { | |
207 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
208 | PCI_EXT_CAP_ID_PRI, |
209 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
210 | }; |
211 | int i, pos; | |
212 | ||
213 | for (i = 0; i < 3; ++i) { | |
214 | pos = pci_find_ext_capability(pdev, caps[i]); | |
215 | if (pos == 0) | |
216 | return false; | |
217 | } | |
218 | ||
219 | return true; | |
220 | } | |
221 | ||
6a113ddc JR |
222 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
223 | { | |
224 | struct iommu_dev_data *dev_data; | |
225 | ||
226 | dev_data = get_dev_data(&pdev->dev); | |
227 | ||
228 | return dev_data->errata & (1 << erratum) ? true : false; | |
229 | } | |
230 | ||
71c70984 | 231 | /* |
0bb6e243 JR |
232 | * This function actually applies the mapping to the page table of the |
233 | * dma_ops domain. | |
71c70984 | 234 | */ |
0bb6e243 JR |
235 | static void alloc_unity_mapping(struct dma_ops_domain *dma_dom, |
236 | struct unity_map_entry *e) | |
71c70984 | 237 | { |
0bb6e243 | 238 | u64 addr; |
71c70984 | 239 | |
0bb6e243 JR |
240 | for (addr = e->address_start; addr < e->address_end; |
241 | addr += PAGE_SIZE) { | |
242 | if (addr < dma_dom->aperture_size) | |
243 | __set_bit(addr >> PAGE_SHIFT, | |
244 | dma_dom->aperture[0]->bitmap); | |
71c70984 | 245 | } |
0bb6e243 | 246 | } |
71c70984 | 247 | |
0bb6e243 JR |
248 | /* |
249 | * Inits the unity mappings required for a specific device | |
250 | */ | |
251 | static void init_unity_mappings_for_device(struct device *dev, | |
252 | struct dma_ops_domain *dma_dom) | |
253 | { | |
254 | struct unity_map_entry *e; | |
255 | u16 devid; | |
71c70984 | 256 | |
0bb6e243 | 257 | devid = get_device_id(dev); |
71c70984 | 258 | |
0bb6e243 JR |
259 | list_for_each_entry(e, &amd_iommu_unity_map, list) { |
260 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
261 | continue; | |
262 | alloc_unity_mapping(dma_dom, e); | |
263 | } | |
71c70984 JR |
264 | } |
265 | ||
98fc5a69 JR |
266 | /* |
267 | * This function checks if the driver got a valid device from the caller to | |
268 | * avoid dereferencing invalid pointers. | |
269 | */ | |
270 | static bool check_device(struct device *dev) | |
271 | { | |
272 | u16 devid; | |
273 | ||
274 | if (!dev || !dev->dma_mask) | |
275 | return false; | |
276 | ||
b82a2272 YW |
277 | /* No PCI device */ |
278 | if (!dev_is_pci(dev)) | |
98fc5a69 JR |
279 | return false; |
280 | ||
281 | devid = get_device_id(dev); | |
282 | ||
283 | /* Out of our scope? */ | |
284 | if (devid > amd_iommu_last_bdf) | |
285 | return false; | |
286 | ||
287 | if (amd_iommu_rlookup_table[devid] == NULL) | |
288 | return false; | |
289 | ||
290 | return true; | |
291 | } | |
292 | ||
25b11ce2 | 293 | static void init_iommu_group(struct device *dev) |
2851db21 | 294 | { |
0bb6e243 JR |
295 | struct dma_ops_domain *dma_domain; |
296 | struct iommu_domain *domain; | |
2851db21 | 297 | struct iommu_group *group; |
2851db21 | 298 | |
65d5352f | 299 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
300 | if (IS_ERR(group)) |
301 | return; | |
302 | ||
303 | domain = iommu_group_default_domain(group); | |
304 | if (!domain) | |
305 | goto out; | |
306 | ||
307 | dma_domain = to_pdomain(domain)->priv; | |
308 | ||
309 | init_unity_mappings_for_device(dev, dma_domain); | |
310 | out: | |
311 | iommu_group_put(group); | |
eb9c9527 AW |
312 | } |
313 | ||
c1931090 AW |
314 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
315 | { | |
316 | *(u16 *)data = alias; | |
317 | return 0; | |
318 | } | |
319 | ||
320 | static u16 get_alias(struct device *dev) | |
321 | { | |
322 | struct pci_dev *pdev = to_pci_dev(dev); | |
323 | u16 devid, ivrs_alias, pci_alias; | |
324 | ||
325 | devid = get_device_id(dev); | |
326 | ivrs_alias = amd_iommu_alias_table[devid]; | |
327 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); | |
328 | ||
329 | if (ivrs_alias == pci_alias) | |
330 | return ivrs_alias; | |
331 | ||
332 | /* | |
333 | * DMA alias showdown | |
334 | * | |
335 | * The IVRS is fairly reliable in telling us about aliases, but it | |
336 | * can't know about every screwy device. If we don't have an IVRS | |
337 | * reported alias, use the PCI reported alias. In that case we may | |
338 | * still need to initialize the rlookup and dev_table entries if the | |
339 | * alias is to a non-existent device. | |
340 | */ | |
341 | if (ivrs_alias == devid) { | |
342 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
343 | amd_iommu_rlookup_table[pci_alias] = | |
344 | amd_iommu_rlookup_table[devid]; | |
345 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
346 | amd_iommu_dev_table[devid].data, | |
347 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
348 | } | |
349 | ||
350 | return pci_alias; | |
351 | } | |
352 | ||
353 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
354 | "for device %s[%04x:%04x], kernel reported alias " | |
355 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
356 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
357 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
358 | PCI_FUNC(pci_alias)); | |
359 | ||
360 | /* | |
361 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
362 | * bus, then the IVRS table may know about a quirk that we don't. | |
363 | */ | |
364 | if (pci_alias == devid && | |
365 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
366 | pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN; | |
367 | pdev->dma_alias_devfn = ivrs_alias & 0xff; | |
368 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", | |
369 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
370 | dev_name(dev)); | |
371 | } | |
372 | ||
373 | return ivrs_alias; | |
374 | } | |
375 | ||
eb9c9527 AW |
376 | static int iommu_init_device(struct device *dev) |
377 | { | |
378 | struct pci_dev *pdev = to_pci_dev(dev); | |
379 | struct iommu_dev_data *dev_data; | |
380 | u16 alias; | |
eb9c9527 AW |
381 | |
382 | if (dev->archdata.iommu) | |
383 | return 0; | |
384 | ||
385 | dev_data = find_dev_data(get_device_id(dev)); | |
386 | if (!dev_data) | |
387 | return -ENOMEM; | |
388 | ||
c1931090 AW |
389 | alias = get_alias(dev); |
390 | ||
eb9c9527 AW |
391 | if (alias != dev_data->devid) { |
392 | struct iommu_dev_data *alias_data; | |
393 | ||
394 | alias_data = find_dev_data(alias); | |
395 | if (alias_data == NULL) { | |
396 | pr_err("AMD-Vi: Warning: Unhandled device %s\n", | |
397 | dev_name(dev)); | |
398 | free_dev_data(dev_data); | |
399 | return -ENOTSUPP; | |
400 | } | |
401 | dev_data->alias_data = alias_data; | |
eb9c9527 | 402 | |
f251e187 JR |
403 | /* Add device to the alias_list */ |
404 | list_add(&dev_data->alias_list, &alias_data->alias_list); | |
e644a013 | 405 | } |
9dcd6130 | 406 | |
5abcdba4 JR |
407 | if (pci_iommuv2_capable(pdev)) { |
408 | struct amd_iommu *iommu; | |
409 | ||
410 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
411 | dev_data->iommu_v2 = iommu->is_iommu_v2; | |
412 | } | |
413 | ||
657cbb6b JR |
414 | dev->archdata.iommu = dev_data; |
415 | ||
066f2e98 AW |
416 | iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
417 | dev); | |
418 | ||
657cbb6b JR |
419 | return 0; |
420 | } | |
421 | ||
26018874 JR |
422 | static void iommu_ignore_device(struct device *dev) |
423 | { | |
424 | u16 devid, alias; | |
425 | ||
426 | devid = get_device_id(dev); | |
427 | alias = amd_iommu_alias_table[devid]; | |
428 | ||
429 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
430 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
431 | ||
432 | amd_iommu_rlookup_table[devid] = NULL; | |
433 | amd_iommu_rlookup_table[alias] = NULL; | |
434 | } | |
435 | ||
657cbb6b JR |
436 | static void iommu_uninit_device(struct device *dev) |
437 | { | |
c1931090 AW |
438 | struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev)); |
439 | ||
440 | if (!dev_data) | |
441 | return; | |
442 | ||
066f2e98 AW |
443 | iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev, |
444 | dev); | |
445 | ||
9dcd6130 AW |
446 | iommu_group_remove_device(dev); |
447 | ||
c1931090 AW |
448 | /* Unlink from alias, it may change if another device is re-plugged */ |
449 | dev_data->alias_data = NULL; | |
450 | ||
aafd8ba0 JR |
451 | /* Remove dma-ops */ |
452 | dev->archdata.dma_ops = NULL; | |
453 | ||
8fa5f802 | 454 | /* |
c1931090 AW |
455 | * We keep dev_data around for unplugged devices and reuse it when the |
456 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 457 | */ |
657cbb6b | 458 | } |
b7cc9554 | 459 | |
7f26508b JR |
460 | #ifdef CONFIG_AMD_IOMMU_STATS |
461 | ||
462 | /* | |
463 | * Initialization code for statistics collection | |
464 | */ | |
465 | ||
da49f6df | 466 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 467 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 468 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 469 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 470 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 471 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 472 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 473 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 474 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 475 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 476 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 477 | DECLARE_STATS_COUNTER(total_map_requests); |
399be2f5 JR |
478 | DECLARE_STATS_COUNTER(complete_ppr); |
479 | DECLARE_STATS_COUNTER(invalidate_iotlb); | |
480 | DECLARE_STATS_COUNTER(invalidate_iotlb_all); | |
481 | DECLARE_STATS_COUNTER(pri_requests); | |
482 | ||
7f26508b | 483 | static struct dentry *stats_dir; |
7f26508b JR |
484 | static struct dentry *de_fflush; |
485 | ||
486 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
487 | { | |
488 | if (stats_dir == NULL) | |
489 | return; | |
490 | ||
491 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
492 | &cnt->value); | |
493 | } | |
494 | ||
495 | static void amd_iommu_stats_init(void) | |
496 | { | |
497 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
498 | if (stats_dir == NULL) | |
499 | return; | |
500 | ||
7f26508b | 501 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, |
3775d481 | 502 | &amd_iommu_unmap_flush); |
da49f6df JR |
503 | |
504 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 505 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 506 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 507 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 508 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 509 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 510 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 511 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 512 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 513 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 514 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 515 | amd_iommu_stats_add(&total_map_requests); |
399be2f5 JR |
516 | amd_iommu_stats_add(&complete_ppr); |
517 | amd_iommu_stats_add(&invalidate_iotlb); | |
518 | amd_iommu_stats_add(&invalidate_iotlb_all); | |
519 | amd_iommu_stats_add(&pri_requests); | |
7f26508b JR |
520 | } |
521 | ||
522 | #endif | |
523 | ||
a80dc3e0 JR |
524 | /**************************************************************************** |
525 | * | |
526 | * Interrupt handling functions | |
527 | * | |
528 | ****************************************************************************/ | |
529 | ||
e3e59876 JR |
530 | static void dump_dte_entry(u16 devid) |
531 | { | |
532 | int i; | |
533 | ||
ee6c2868 JR |
534 | for (i = 0; i < 4; ++i) |
535 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
536 | amd_iommu_dev_table[devid].data[i]); |
537 | } | |
538 | ||
945b4ac4 JR |
539 | static void dump_command(unsigned long phys_addr) |
540 | { | |
541 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
542 | int i; | |
543 | ||
544 | for (i = 0; i < 4; ++i) | |
545 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
546 | } | |
547 | ||
a345b23b | 548 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 549 | { |
3d06fca8 JR |
550 | int type, devid, domid, flags; |
551 | volatile u32 *event = __evt; | |
552 | int count = 0; | |
553 | u64 address; | |
554 | ||
555 | retry: | |
556 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
557 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
558 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
559 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
560 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
561 | ||
562 | if (type == 0) { | |
563 | /* Did we hit the erratum? */ | |
564 | if (++count == LOOP_TIMEOUT) { | |
565 | pr_err("AMD-Vi: No event written to event log\n"); | |
566 | return; | |
567 | } | |
568 | udelay(1); | |
569 | goto retry; | |
570 | } | |
90008ee4 | 571 | |
4c6f40d4 | 572 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
573 | |
574 | switch (type) { | |
575 | case EVENT_TYPE_ILL_DEV: | |
576 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
577 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 578 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 579 | address, flags); |
e3e59876 | 580 | dump_dte_entry(devid); |
90008ee4 JR |
581 | break; |
582 | case EVENT_TYPE_IO_FAULT: | |
583 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
584 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 585 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
586 | domid, address, flags); |
587 | break; | |
588 | case EVENT_TYPE_DEV_TAB_ERR: | |
589 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
590 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 591 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
592 | address, flags); |
593 | break; | |
594 | case EVENT_TYPE_PAGE_TAB_ERR: | |
595 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
596 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 597 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
598 | domid, address, flags); |
599 | break; | |
600 | case EVENT_TYPE_ILL_CMD: | |
601 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 602 | dump_command(address); |
90008ee4 JR |
603 | break; |
604 | case EVENT_TYPE_CMD_HARD_ERR: | |
605 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
606 | "flags=0x%04x]\n", address, flags); | |
607 | break; | |
608 | case EVENT_TYPE_IOTLB_INV_TO: | |
609 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
610 | "address=0x%016llx]\n", | |
c5081cd7 | 611 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
612 | address); |
613 | break; | |
614 | case EVENT_TYPE_INV_DEV_REQ: | |
615 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
616 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 617 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
618 | address, flags); |
619 | break; | |
620 | default: | |
621 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
622 | } | |
3d06fca8 JR |
623 | |
624 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
625 | } |
626 | ||
627 | static void iommu_poll_events(struct amd_iommu *iommu) | |
628 | { | |
629 | u32 head, tail; | |
90008ee4 JR |
630 | |
631 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
632 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
633 | ||
634 | while (head != tail) { | |
a345b23b | 635 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
636 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
637 | } | |
638 | ||
639 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
640 | } |
641 | ||
eee53537 | 642 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
643 | { |
644 | struct amd_iommu_fault fault; | |
72e1dcc4 | 645 | |
399be2f5 JR |
646 | INC_STATS_COUNTER(pri_requests); |
647 | ||
72e1dcc4 JR |
648 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
649 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
650 | return; | |
651 | } | |
652 | ||
653 | fault.address = raw[1]; | |
654 | fault.pasid = PPR_PASID(raw[0]); | |
655 | fault.device_id = PPR_DEVID(raw[0]); | |
656 | fault.tag = PPR_TAG(raw[0]); | |
657 | fault.flags = PPR_FLAGS(raw[0]); | |
658 | ||
72e1dcc4 JR |
659 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
660 | } | |
661 | ||
662 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
663 | { | |
72e1dcc4 JR |
664 | u32 head, tail; |
665 | ||
666 | if (iommu->ppr_log == NULL) | |
667 | return; | |
668 | ||
72e1dcc4 JR |
669 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
670 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
671 | ||
672 | while (head != tail) { | |
eee53537 JR |
673 | volatile u64 *raw; |
674 | u64 entry[2]; | |
675 | int i; | |
676 | ||
677 | raw = (u64 *)(iommu->ppr_log + head); | |
678 | ||
679 | /* | |
680 | * Hardware bug: Interrupt may arrive before the entry is | |
681 | * written to memory. If this happens we need to wait for the | |
682 | * entry to arrive. | |
683 | */ | |
684 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
685 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
686 | break; | |
687 | udelay(1); | |
688 | } | |
72e1dcc4 | 689 | |
eee53537 JR |
690 | /* Avoid memcpy function-call overhead */ |
691 | entry[0] = raw[0]; | |
692 | entry[1] = raw[1]; | |
72e1dcc4 | 693 | |
eee53537 JR |
694 | /* |
695 | * To detect the hardware bug we need to clear the entry | |
696 | * back to zero. | |
697 | */ | |
698 | raw[0] = raw[1] = 0UL; | |
699 | ||
700 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
701 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
702 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 703 | |
eee53537 JR |
704 | /* Handle PPR entry */ |
705 | iommu_handle_ppr_entry(iommu, entry); | |
706 | ||
eee53537 JR |
707 | /* Refresh ring-buffer information */ |
708 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
709 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
710 | } | |
72e1dcc4 JR |
711 | } |
712 | ||
72fe00f0 | 713 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 714 | { |
3f398bc7 SS |
715 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
716 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 717 | |
3f398bc7 SS |
718 | while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) { |
719 | /* Enable EVT and PPR interrupts again */ | |
720 | writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK), | |
721 | iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 722 | |
3f398bc7 SS |
723 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
724 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
725 | iommu_poll_events(iommu); | |
726 | } | |
90008ee4 | 727 | |
3f398bc7 SS |
728 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
729 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
730 | iommu_poll_ppr_log(iommu); | |
731 | } | |
90008ee4 | 732 | |
3f398bc7 SS |
733 | /* |
734 | * Hardware bug: ERBT1312 | |
735 | * When re-enabling interrupt (by writing 1 | |
736 | * to clear the bit), the hardware might also try to set | |
737 | * the interrupt bit in the event status register. | |
738 | * In this scenario, the bit will be set, and disable | |
739 | * subsequent interrupts. | |
740 | * | |
741 | * Workaround: The IOMMU driver should read back the | |
742 | * status register and check if the interrupt bits are cleared. | |
743 | * If not, driver will need to go through the interrupt handler | |
744 | * again and re-clear the bits | |
745 | */ | |
746 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
747 | } | |
90008ee4 | 748 | return IRQ_HANDLED; |
a80dc3e0 JR |
749 | } |
750 | ||
72fe00f0 JR |
751 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
752 | { | |
753 | return IRQ_WAKE_THREAD; | |
754 | } | |
755 | ||
431b2a20 JR |
756 | /**************************************************************************** |
757 | * | |
758 | * IOMMU command queuing functions | |
759 | * | |
760 | ****************************************************************************/ | |
761 | ||
ac0ea6e9 JR |
762 | static int wait_on_sem(volatile u64 *sem) |
763 | { | |
764 | int i = 0; | |
765 | ||
766 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
767 | udelay(1); | |
768 | i += 1; | |
769 | } | |
770 | ||
771 | if (i == LOOP_TIMEOUT) { | |
772 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
773 | return -EIO; | |
774 | } | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
780 | struct iommu_cmd *cmd, | |
781 | u32 tail) | |
a19ae1ec | 782 | { |
a19ae1ec JR |
783 | u8 *target; |
784 | ||
8a7c5ef3 | 785 | target = iommu->cmd_buf + tail; |
ac0ea6e9 JR |
786 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; |
787 | ||
788 | /* Copy command to buffer */ | |
789 | memcpy(target, cmd, sizeof(*cmd)); | |
790 | ||
791 | /* Tell the IOMMU about it */ | |
a19ae1ec | 792 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 793 | } |
a19ae1ec | 794 | |
815b33fd | 795 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 796 | { |
815b33fd JR |
797 | WARN_ON(address & 0x7ULL); |
798 | ||
ded46737 | 799 | memset(cmd, 0, sizeof(*cmd)); |
815b33fd JR |
800 | cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK; |
801 | cmd->data[1] = upper_32_bits(__pa(address)); | |
802 | cmd->data[2] = 1; | |
ded46737 JR |
803 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
804 | } | |
805 | ||
94fe79e2 JR |
806 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
807 | { | |
808 | memset(cmd, 0, sizeof(*cmd)); | |
809 | cmd->data[0] = devid; | |
810 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
811 | } | |
812 | ||
11b6402c JR |
813 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
814 | size_t size, u16 domid, int pde) | |
815 | { | |
816 | u64 pages; | |
ae0cbbb1 | 817 | bool s; |
11b6402c JR |
818 | |
819 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 820 | s = false; |
11b6402c JR |
821 | |
822 | if (pages > 1) { | |
823 | /* | |
824 | * If we have to flush more than one page, flush all | |
825 | * TLB entries for this domain | |
826 | */ | |
827 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 828 | s = true; |
11b6402c JR |
829 | } |
830 | ||
831 | address &= PAGE_MASK; | |
832 | ||
833 | memset(cmd, 0, sizeof(*cmd)); | |
834 | cmd->data[1] |= domid; | |
835 | cmd->data[2] = lower_32_bits(address); | |
836 | cmd->data[3] = upper_32_bits(address); | |
837 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
838 | if (s) /* size bit - we flush more than one 4kb page */ | |
839 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 840 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
841 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
842 | } | |
843 | ||
cb41ed85 JR |
844 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
845 | u64 address, size_t size) | |
846 | { | |
847 | u64 pages; | |
ae0cbbb1 | 848 | bool s; |
cb41ed85 JR |
849 | |
850 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 851 | s = false; |
cb41ed85 JR |
852 | |
853 | if (pages > 1) { | |
854 | /* | |
855 | * If we have to flush more than one page, flush all | |
856 | * TLB entries for this domain | |
857 | */ | |
858 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 859 | s = true; |
cb41ed85 JR |
860 | } |
861 | ||
862 | address &= PAGE_MASK; | |
863 | ||
864 | memset(cmd, 0, sizeof(*cmd)); | |
865 | cmd->data[0] = devid; | |
866 | cmd->data[0] |= (qdep & 0xff) << 24; | |
867 | cmd->data[1] = devid; | |
868 | cmd->data[2] = lower_32_bits(address); | |
869 | cmd->data[3] = upper_32_bits(address); | |
870 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
871 | if (s) | |
872 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
873 | } | |
874 | ||
22e266c7 JR |
875 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
876 | u64 address, bool size) | |
877 | { | |
878 | memset(cmd, 0, sizeof(*cmd)); | |
879 | ||
880 | address &= ~(0xfffULL); | |
881 | ||
a919a018 | 882 | cmd->data[0] = pasid; |
22e266c7 JR |
883 | cmd->data[1] = domid; |
884 | cmd->data[2] = lower_32_bits(address); | |
885 | cmd->data[3] = upper_32_bits(address); | |
886 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
887 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
888 | if (size) | |
889 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
890 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
891 | } | |
892 | ||
893 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
894 | int qdep, u64 address, bool size) | |
895 | { | |
896 | memset(cmd, 0, sizeof(*cmd)); | |
897 | ||
898 | address &= ~(0xfffULL); | |
899 | ||
900 | cmd->data[0] = devid; | |
e8d2d82d | 901 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
902 | cmd->data[0] |= (qdep & 0xff) << 24; |
903 | cmd->data[1] = devid; | |
e8d2d82d | 904 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
905 | cmd->data[2] = lower_32_bits(address); |
906 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
907 | cmd->data[3] = upper_32_bits(address); | |
908 | if (size) | |
909 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
910 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
911 | } | |
912 | ||
c99afa25 JR |
913 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
914 | int status, int tag, bool gn) | |
915 | { | |
916 | memset(cmd, 0, sizeof(*cmd)); | |
917 | ||
918 | cmd->data[0] = devid; | |
919 | if (gn) { | |
a919a018 | 920 | cmd->data[1] = pasid; |
c99afa25 JR |
921 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
922 | } | |
923 | cmd->data[3] = tag & 0x1ff; | |
924 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
925 | ||
926 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
927 | } | |
928 | ||
58fc7f14 JR |
929 | static void build_inv_all(struct iommu_cmd *cmd) |
930 | { | |
931 | memset(cmd, 0, sizeof(*cmd)); | |
932 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
933 | } |
934 | ||
7ef2798d JR |
935 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
936 | { | |
937 | memset(cmd, 0, sizeof(*cmd)); | |
938 | cmd->data[0] = devid; | |
939 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
940 | } | |
941 | ||
431b2a20 | 942 | /* |
431b2a20 | 943 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 944 | * hardware about the new command. |
431b2a20 | 945 | */ |
f1ca1512 JR |
946 | static int iommu_queue_command_sync(struct amd_iommu *iommu, |
947 | struct iommu_cmd *cmd, | |
948 | bool sync) | |
a19ae1ec | 949 | { |
ac0ea6e9 | 950 | u32 left, tail, head, next_tail; |
a19ae1ec | 951 | unsigned long flags; |
a19ae1ec | 952 | |
549c90dc | 953 | WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED); |
ac0ea6e9 JR |
954 | |
955 | again: | |
a19ae1ec | 956 | spin_lock_irqsave(&iommu->lock, flags); |
a19ae1ec | 957 | |
ac0ea6e9 JR |
958 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); |
959 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
960 | next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
961 | left = (head - next_tail) % iommu->cmd_buf_size; | |
a19ae1ec | 962 | |
ac0ea6e9 JR |
963 | if (left <= 2) { |
964 | struct iommu_cmd sync_cmd; | |
965 | volatile u64 sem = 0; | |
966 | int ret; | |
8d201968 | 967 | |
ac0ea6e9 JR |
968 | build_completion_wait(&sync_cmd, (u64)&sem); |
969 | copy_cmd_to_buffer(iommu, &sync_cmd, tail); | |
da49f6df | 970 | |
ac0ea6e9 JR |
971 | spin_unlock_irqrestore(&iommu->lock, flags); |
972 | ||
973 | if ((ret = wait_on_sem(&sem)) != 0) | |
974 | return ret; | |
975 | ||
976 | goto again; | |
8d201968 JR |
977 | } |
978 | ||
ac0ea6e9 JR |
979 | copy_cmd_to_buffer(iommu, cmd, tail); |
980 | ||
981 | /* We need to sync now to make sure all commands are processed */ | |
f1ca1512 | 982 | iommu->need_sync = sync; |
ac0ea6e9 | 983 | |
a19ae1ec | 984 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 985 | |
815b33fd | 986 | return 0; |
8d201968 JR |
987 | } |
988 | ||
f1ca1512 JR |
989 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
990 | { | |
991 | return iommu_queue_command_sync(iommu, cmd, true); | |
992 | } | |
993 | ||
8d201968 JR |
994 | /* |
995 | * This function queues a completion wait command into the command | |
996 | * buffer of an IOMMU | |
997 | */ | |
a19ae1ec | 998 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
999 | { |
1000 | struct iommu_cmd cmd; | |
815b33fd | 1001 | volatile u64 sem = 0; |
ac0ea6e9 | 1002 | int ret; |
8d201968 | 1003 | |
09ee17eb | 1004 | if (!iommu->need_sync) |
815b33fd | 1005 | return 0; |
09ee17eb | 1006 | |
815b33fd | 1007 | build_completion_wait(&cmd, (u64)&sem); |
a19ae1ec | 1008 | |
f1ca1512 | 1009 | ret = iommu_queue_command_sync(iommu, &cmd, false); |
a19ae1ec | 1010 | if (ret) |
815b33fd | 1011 | return ret; |
8d201968 | 1012 | |
ac0ea6e9 | 1013 | return wait_on_sem(&sem); |
8d201968 JR |
1014 | } |
1015 | ||
d8c13085 | 1016 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1017 | { |
d8c13085 | 1018 | struct iommu_cmd cmd; |
a19ae1ec | 1019 | |
d8c13085 | 1020 | build_inv_dte(&cmd, devid); |
7e4f88da | 1021 | |
d8c13085 JR |
1022 | return iommu_queue_command(iommu, &cmd); |
1023 | } | |
09ee17eb | 1024 | |
7d0c5cc5 JR |
1025 | static void iommu_flush_dte_all(struct amd_iommu *iommu) |
1026 | { | |
1027 | u32 devid; | |
09ee17eb | 1028 | |
7d0c5cc5 JR |
1029 | for (devid = 0; devid <= 0xffff; ++devid) |
1030 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1031 | |
7d0c5cc5 JR |
1032 | iommu_completion_wait(iommu); |
1033 | } | |
84df8175 | 1034 | |
7d0c5cc5 JR |
1035 | /* |
1036 | * This function uses heavy locking and may disable irqs for some time. But | |
1037 | * this is no issue because it is only called during resume. | |
1038 | */ | |
1039 | static void iommu_flush_tlb_all(struct amd_iommu *iommu) | |
1040 | { | |
1041 | u32 dom_id; | |
a19ae1ec | 1042 | |
7d0c5cc5 JR |
1043 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1044 | struct iommu_cmd cmd; | |
1045 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1046 | dom_id, 1); | |
1047 | iommu_queue_command(iommu, &cmd); | |
1048 | } | |
8eed9833 | 1049 | |
7d0c5cc5 | 1050 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1051 | } |
1052 | ||
58fc7f14 | 1053 | static void iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1054 | { |
58fc7f14 | 1055 | struct iommu_cmd cmd; |
0518a3a4 | 1056 | |
58fc7f14 | 1057 | build_inv_all(&cmd); |
0518a3a4 | 1058 | |
58fc7f14 JR |
1059 | iommu_queue_command(iommu, &cmd); |
1060 | iommu_completion_wait(iommu); | |
1061 | } | |
1062 | ||
7ef2798d JR |
1063 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1064 | { | |
1065 | struct iommu_cmd cmd; | |
1066 | ||
1067 | build_inv_irt(&cmd, devid); | |
1068 | ||
1069 | iommu_queue_command(iommu, &cmd); | |
1070 | } | |
1071 | ||
1072 | static void iommu_flush_irt_all(struct amd_iommu *iommu) | |
1073 | { | |
1074 | u32 devid; | |
1075 | ||
1076 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1077 | iommu_flush_irt(iommu, devid); | |
1078 | ||
1079 | iommu_completion_wait(iommu); | |
1080 | } | |
1081 | ||
7d0c5cc5 JR |
1082 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1083 | { | |
58fc7f14 JR |
1084 | if (iommu_feature(iommu, FEATURE_IA)) { |
1085 | iommu_flush_all(iommu); | |
1086 | } else { | |
1087 | iommu_flush_dte_all(iommu); | |
7ef2798d | 1088 | iommu_flush_irt_all(iommu); |
58fc7f14 | 1089 | iommu_flush_tlb_all(iommu); |
0518a3a4 JR |
1090 | } |
1091 | } | |
1092 | ||
431b2a20 | 1093 | /* |
cb41ed85 | 1094 | * Command send function for flushing on-device TLB |
431b2a20 | 1095 | */ |
6c542047 JR |
1096 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1097 | u64 address, size_t size) | |
3fa43655 JR |
1098 | { |
1099 | struct amd_iommu *iommu; | |
b00d3bcf | 1100 | struct iommu_cmd cmd; |
cb41ed85 | 1101 | int qdep; |
3fa43655 | 1102 | |
ea61cddb JR |
1103 | qdep = dev_data->ats.qdep; |
1104 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1105 | |
ea61cddb | 1106 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1107 | |
1108 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1109 | } |
1110 | ||
431b2a20 | 1111 | /* |
431b2a20 | 1112 | * Command send function for invalidating a device table entry |
431b2a20 | 1113 | */ |
6c542047 | 1114 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1115 | { |
3fa43655 | 1116 | struct amd_iommu *iommu; |
ee2fa743 | 1117 | int ret; |
a19ae1ec | 1118 | |
6c542047 | 1119 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
a19ae1ec | 1120 | |
f62dda66 | 1121 | ret = iommu_flush_dte(iommu, dev_data->devid); |
cb41ed85 JR |
1122 | if (ret) |
1123 | return ret; | |
1124 | ||
ea61cddb | 1125 | if (dev_data->ats.enabled) |
6c542047 | 1126 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1127 | |
ee2fa743 | 1128 | return ret; |
a19ae1ec JR |
1129 | } |
1130 | ||
431b2a20 JR |
1131 | /* |
1132 | * TLB invalidation function which is called from the mapping functions. | |
1133 | * It invalidates a single PTE if the range to flush is within a single | |
1134 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1135 | */ | |
17b124bf JR |
1136 | static void __domain_flush_pages(struct protection_domain *domain, |
1137 | u64 address, size_t size, int pde) | |
a19ae1ec | 1138 | { |
cb41ed85 | 1139 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1140 | struct iommu_cmd cmd; |
1141 | int ret = 0, i; | |
a19ae1ec | 1142 | |
11b6402c | 1143 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1144 | |
6de8ad9b JR |
1145 | for (i = 0; i < amd_iommus_present; ++i) { |
1146 | if (!domain->dev_iommu[i]) | |
1147 | continue; | |
1148 | ||
1149 | /* | |
1150 | * Devices of this domain are behind this IOMMU | |
1151 | * We need a TLB flush | |
1152 | */ | |
11b6402c | 1153 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1154 | } |
1155 | ||
cb41ed85 | 1156 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1157 | |
ea61cddb | 1158 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1159 | continue; |
1160 | ||
6c542047 | 1161 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1162 | } |
1163 | ||
11b6402c | 1164 | WARN_ON(ret); |
6de8ad9b JR |
1165 | } |
1166 | ||
17b124bf JR |
1167 | static void domain_flush_pages(struct protection_domain *domain, |
1168 | u64 address, size_t size) | |
6de8ad9b | 1169 | { |
17b124bf | 1170 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1171 | } |
b6c02715 | 1172 | |
1c655773 | 1173 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1174 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1175 | { |
17b124bf | 1176 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1177 | } |
1178 | ||
42a49f96 | 1179 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1180 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1181 | { |
17b124bf | 1182 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1183 | } |
1184 | ||
17b124bf | 1185 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1186 | { |
17b124bf | 1187 | int i; |
18811f55 | 1188 | |
17b124bf JR |
1189 | for (i = 0; i < amd_iommus_present; ++i) { |
1190 | if (!domain->dev_iommu[i]) | |
1191 | continue; | |
bfd1be18 | 1192 | |
17b124bf JR |
1193 | /* |
1194 | * Devices of this domain are behind this IOMMU | |
1195 | * We need to wait for completion of all commands. | |
1196 | */ | |
1197 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1198 | } |
e394d72a JR |
1199 | } |
1200 | ||
b00d3bcf | 1201 | |
09b42804 | 1202 | /* |
b00d3bcf | 1203 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1204 | */ |
17b124bf | 1205 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1206 | { |
b00d3bcf | 1207 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1208 | |
b00d3bcf | 1209 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1210 | device_flush_dte(dev_data); |
a345b23b JR |
1211 | } |
1212 | ||
431b2a20 JR |
1213 | /**************************************************************************** |
1214 | * | |
1215 | * The functions below are used the create the page table mappings for | |
1216 | * unity mapped regions. | |
1217 | * | |
1218 | ****************************************************************************/ | |
1219 | ||
308973d3 JR |
1220 | /* |
1221 | * This function is used to add another level to an IO page table. Adding | |
1222 | * another level increases the size of the address space by 9 bits to a size up | |
1223 | * to 64 bits. | |
1224 | */ | |
1225 | static bool increase_address_space(struct protection_domain *domain, | |
1226 | gfp_t gfp) | |
1227 | { | |
1228 | u64 *pte; | |
1229 | ||
1230 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1231 | /* address space already 64 bit large */ | |
1232 | return false; | |
1233 | ||
1234 | pte = (void *)get_zeroed_page(gfp); | |
1235 | if (!pte) | |
1236 | return false; | |
1237 | ||
1238 | *pte = PM_LEVEL_PDE(domain->mode, | |
1239 | virt_to_phys(domain->pt_root)); | |
1240 | domain->pt_root = pte; | |
1241 | domain->mode += 1; | |
1242 | domain->updated = true; | |
1243 | ||
1244 | return true; | |
1245 | } | |
1246 | ||
1247 | static u64 *alloc_pte(struct protection_domain *domain, | |
1248 | unsigned long address, | |
cbb9d729 | 1249 | unsigned long page_size, |
308973d3 JR |
1250 | u64 **pte_page, |
1251 | gfp_t gfp) | |
1252 | { | |
cbb9d729 | 1253 | int level, end_lvl; |
308973d3 | 1254 | u64 *pte, *page; |
cbb9d729 JR |
1255 | |
1256 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1257 | |
1258 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1259 | increase_address_space(domain, gfp); | |
1260 | ||
cbb9d729 JR |
1261 | level = domain->mode - 1; |
1262 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1263 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1264 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1265 | |
1266 | while (level > end_lvl) { | |
1267 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1268 | page = (u64 *)get_zeroed_page(gfp); | |
1269 | if (!page) | |
1270 | return NULL; | |
1271 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1272 | } | |
1273 | ||
cbb9d729 JR |
1274 | /* No level skipping support yet */ |
1275 | if (PM_PTE_LEVEL(*pte) != level) | |
1276 | return NULL; | |
1277 | ||
308973d3 JR |
1278 | level -= 1; |
1279 | ||
1280 | pte = IOMMU_PTE_PAGE(*pte); | |
1281 | ||
1282 | if (pte_page && level == end_lvl) | |
1283 | *pte_page = pte; | |
1284 | ||
1285 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1286 | } | |
1287 | ||
1288 | return pte; | |
1289 | } | |
1290 | ||
1291 | /* | |
1292 | * This function checks if there is a PTE for a given dma address. If | |
1293 | * there is one, it returns the pointer to it. | |
1294 | */ | |
3039ca1b JR |
1295 | static u64 *fetch_pte(struct protection_domain *domain, |
1296 | unsigned long address, | |
1297 | unsigned long *page_size) | |
308973d3 JR |
1298 | { |
1299 | int level; | |
1300 | u64 *pte; | |
1301 | ||
24cd7723 JR |
1302 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1303 | return NULL; | |
1304 | ||
3039ca1b JR |
1305 | level = domain->mode - 1; |
1306 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1307 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1308 | |
24cd7723 JR |
1309 | while (level > 0) { |
1310 | ||
1311 | /* Not Present */ | |
308973d3 JR |
1312 | if (!IOMMU_PTE_PRESENT(*pte)) |
1313 | return NULL; | |
1314 | ||
24cd7723 | 1315 | /* Large PTE */ |
3039ca1b JR |
1316 | if (PM_PTE_LEVEL(*pte) == 7 || |
1317 | PM_PTE_LEVEL(*pte) == 0) | |
1318 | break; | |
24cd7723 JR |
1319 | |
1320 | /* No level skipping support yet */ | |
1321 | if (PM_PTE_LEVEL(*pte) != level) | |
1322 | return NULL; | |
1323 | ||
308973d3 JR |
1324 | level -= 1; |
1325 | ||
24cd7723 | 1326 | /* Walk to the next level */ |
3039ca1b JR |
1327 | pte = IOMMU_PTE_PAGE(*pte); |
1328 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1329 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1330 | } | |
1331 | ||
1332 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1333 | unsigned long pte_mask; | |
1334 | ||
1335 | /* | |
1336 | * If we have a series of large PTEs, make | |
1337 | * sure to return a pointer to the first one. | |
1338 | */ | |
1339 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1340 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1341 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1342 | } |
1343 | ||
1344 | return pte; | |
1345 | } | |
1346 | ||
431b2a20 JR |
1347 | /* |
1348 | * Generic mapping functions. It maps a physical address into a DMA | |
1349 | * address space. It allocates the page table pages if necessary. | |
1350 | * In the future it can be extended to a generic mapping function | |
1351 | * supporting all features of AMD IOMMU page tables like level skipping | |
1352 | * and full 64 bit address spaces. | |
1353 | */ | |
38e817fe JR |
1354 | static int iommu_map_page(struct protection_domain *dom, |
1355 | unsigned long bus_addr, | |
1356 | unsigned long phys_addr, | |
abdc5eb3 | 1357 | int prot, |
cbb9d729 | 1358 | unsigned long page_size) |
bd0e5211 | 1359 | { |
8bda3092 | 1360 | u64 __pte, *pte; |
cbb9d729 | 1361 | int i, count; |
abdc5eb3 | 1362 | |
d4b03664 JR |
1363 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1364 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1365 | ||
bad1cac2 | 1366 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1367 | return -EINVAL; |
1368 | ||
d4b03664 JR |
1369 | count = PAGE_SIZE_PTE_COUNT(page_size); |
1370 | pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL); | |
cbb9d729 | 1371 | |
63eaa75e ML |
1372 | if (!pte) |
1373 | return -ENOMEM; | |
1374 | ||
cbb9d729 JR |
1375 | for (i = 0; i < count; ++i) |
1376 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1377 | return -EBUSY; | |
bd0e5211 | 1378 | |
d4b03664 | 1379 | if (count > 1) { |
cbb9d729 JR |
1380 | __pte = PAGE_SIZE_PTE(phys_addr, page_size); |
1381 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1382 | } else | |
1383 | __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
bd0e5211 | 1384 | |
bd0e5211 JR |
1385 | if (prot & IOMMU_PROT_IR) |
1386 | __pte |= IOMMU_PTE_IR; | |
1387 | if (prot & IOMMU_PROT_IW) | |
1388 | __pte |= IOMMU_PTE_IW; | |
1389 | ||
cbb9d729 JR |
1390 | for (i = 0; i < count; ++i) |
1391 | pte[i] = __pte; | |
bd0e5211 | 1392 | |
04bfdd84 JR |
1393 | update_domain(dom); |
1394 | ||
bd0e5211 JR |
1395 | return 0; |
1396 | } | |
1397 | ||
24cd7723 JR |
1398 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1399 | unsigned long bus_addr, | |
1400 | unsigned long page_size) | |
eb74ff6c | 1401 | { |
71b390e9 JR |
1402 | unsigned long long unmapped; |
1403 | unsigned long unmap_size; | |
24cd7723 JR |
1404 | u64 *pte; |
1405 | ||
1406 | BUG_ON(!is_power_of_2(page_size)); | |
1407 | ||
1408 | unmapped = 0; | |
eb74ff6c | 1409 | |
24cd7723 JR |
1410 | while (unmapped < page_size) { |
1411 | ||
71b390e9 JR |
1412 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1413 | ||
1414 | if (pte) { | |
1415 | int i, count; | |
1416 | ||
1417 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1418 | for (i = 0; i < count; i++) |
1419 | pte[i] = 0ULL; | |
1420 | } | |
1421 | ||
1422 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1423 | unmapped += unmap_size; | |
1424 | } | |
1425 | ||
60d0ca3c | 1426 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1427 | |
24cd7723 | 1428 | return unmapped; |
eb74ff6c | 1429 | } |
eb74ff6c | 1430 | |
431b2a20 JR |
1431 | /**************************************************************************** |
1432 | * | |
1433 | * The next functions belong to the address allocator for the dma_ops | |
1434 | * interface functions. They work like the allocators in the other IOMMU | |
1435 | * drivers. Its basically a bitmap which marks the allocated pages in | |
1436 | * the aperture. Maybe it could be enhanced in the future to a more | |
1437 | * efficient allocator. | |
1438 | * | |
1439 | ****************************************************************************/ | |
d3086444 | 1440 | |
431b2a20 | 1441 | /* |
384de729 | 1442 | * The address allocator core functions. |
431b2a20 JR |
1443 | * |
1444 | * called with domain->lock held | |
1445 | */ | |
384de729 | 1446 | |
171e7b37 JR |
1447 | /* |
1448 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1449 | * ranges. | |
1450 | */ | |
1451 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, | |
1452 | unsigned long start_page, | |
1453 | unsigned int pages) | |
1454 | { | |
1455 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; | |
1456 | ||
1457 | if (start_page + pages > last_page) | |
1458 | pages = last_page - start_page; | |
1459 | ||
1460 | for (i = start_page; i < start_page + pages; ++i) { | |
1461 | int index = i / APERTURE_RANGE_PAGES; | |
1462 | int page = i % APERTURE_RANGE_PAGES; | |
1463 | __set_bit(page, dom->aperture[index]->bitmap); | |
1464 | } | |
1465 | } | |
1466 | ||
9cabe89b JR |
1467 | /* |
1468 | * This function is used to add a new aperture range to an existing | |
1469 | * aperture in case of dma_ops domain allocation or address allocation | |
1470 | * failure. | |
1471 | */ | |
576175c2 | 1472 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
1473 | bool populate, gfp_t gfp) |
1474 | { | |
1475 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 1476 | struct amd_iommu *iommu; |
5d7c94c3 | 1477 | unsigned long i, old_size, pte_pgsize; |
9cabe89b | 1478 | |
f5e9705c JR |
1479 | #ifdef CONFIG_IOMMU_STRESS |
1480 | populate = false; | |
1481 | #endif | |
1482 | ||
9cabe89b JR |
1483 | if (index >= APERTURE_MAX_RANGES) |
1484 | return -ENOMEM; | |
1485 | ||
1486 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
1487 | if (!dma_dom->aperture[index]) | |
1488 | return -ENOMEM; | |
1489 | ||
1490 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
1491 | if (!dma_dom->aperture[index]->bitmap) | |
1492 | goto out_free; | |
1493 | ||
1494 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
1495 | ||
1496 | if (populate) { | |
1497 | unsigned long address = dma_dom->aperture_size; | |
1498 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
1499 | u64 *pte, *pte_page; | |
1500 | ||
1501 | for (i = 0; i < num_ptes; ++i) { | |
cbb9d729 | 1502 | pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE, |
9cabe89b JR |
1503 | &pte_page, gfp); |
1504 | if (!pte) | |
1505 | goto out_free; | |
1506 | ||
1507 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
1508 | ||
1509 | address += APERTURE_RANGE_SIZE / 64; | |
1510 | } | |
1511 | } | |
1512 | ||
17f5b569 | 1513 | old_size = dma_dom->aperture_size; |
9cabe89b JR |
1514 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; |
1515 | ||
17f5b569 JR |
1516 | /* Reserve address range used for MSI messages */ |
1517 | if (old_size < MSI_ADDR_BASE_LO && | |
1518 | dma_dom->aperture_size > MSI_ADDR_BASE_LO) { | |
1519 | unsigned long spage; | |
1520 | int pages; | |
1521 | ||
1522 | pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE); | |
1523 | spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT; | |
1524 | ||
1525 | dma_ops_reserve_addresses(dma_dom, spage, pages); | |
1526 | } | |
1527 | ||
b595076a | 1528 | /* Initialize the exclusion range if necessary */ |
576175c2 JR |
1529 | for_each_iommu(iommu) { |
1530 | if (iommu->exclusion_start && | |
1531 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
1532 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
1533 | unsigned long startpage; | |
1534 | int pages = iommu_num_pages(iommu->exclusion_start, | |
1535 | iommu->exclusion_length, | |
1536 | PAGE_SIZE); | |
1537 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
1538 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
1539 | } | |
00cd122a JR |
1540 | } |
1541 | ||
1542 | /* | |
1543 | * Check for areas already mapped as present in the new aperture | |
1544 | * range and mark those pages as reserved in the allocator. Such | |
1545 | * mappings may already exist as a result of requested unity | |
1546 | * mappings for devices. | |
1547 | */ | |
1548 | for (i = dma_dom->aperture[index]->offset; | |
1549 | i < dma_dom->aperture_size; | |
5d7c94c3 | 1550 | i += pte_pgsize) { |
3039ca1b | 1551 | u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize); |
00cd122a JR |
1552 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
1553 | continue; | |
1554 | ||
5d7c94c3 JR |
1555 | dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, |
1556 | pte_pgsize >> 12); | |
00cd122a JR |
1557 | } |
1558 | ||
04bfdd84 JR |
1559 | update_domain(&dma_dom->domain); |
1560 | ||
9cabe89b JR |
1561 | return 0; |
1562 | ||
1563 | out_free: | |
04bfdd84 JR |
1564 | update_domain(&dma_dom->domain); |
1565 | ||
9cabe89b JR |
1566 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
1567 | ||
1568 | kfree(dma_dom->aperture[index]); | |
1569 | dma_dom->aperture[index] = NULL; | |
1570 | ||
1571 | return -ENOMEM; | |
1572 | } | |
1573 | ||
384de729 JR |
1574 | static unsigned long dma_ops_area_alloc(struct device *dev, |
1575 | struct dma_ops_domain *dom, | |
1576 | unsigned int pages, | |
1577 | unsigned long align_mask, | |
1578 | u64 dma_mask, | |
1579 | unsigned long start) | |
1580 | { | |
803b8cb4 | 1581 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
1582 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
1583 | int i = start >> APERTURE_RANGE_SHIFT; | |
e6aabee0 | 1584 | unsigned long boundary_size, mask; |
384de729 JR |
1585 | unsigned long address = -1; |
1586 | unsigned long limit; | |
1587 | ||
803b8cb4 JR |
1588 | next_bit >>= PAGE_SHIFT; |
1589 | ||
e6aabee0 JR |
1590 | mask = dma_get_seg_boundary(dev); |
1591 | ||
1592 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
1593 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
384de729 JR |
1594 | |
1595 | for (;i < max_index; ++i) { | |
1596 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
1597 | ||
1598 | if (dom->aperture[i]->offset >= dma_mask) | |
1599 | break; | |
1600 | ||
1601 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
1602 | dma_mask >> PAGE_SHIFT); | |
1603 | ||
1604 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
1605 | limit, next_bit, pages, 0, | |
1606 | boundary_size, align_mask); | |
1607 | if (address != -1) { | |
1608 | address = dom->aperture[i]->offset + | |
1609 | (address << PAGE_SHIFT); | |
803b8cb4 | 1610 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
1611 | break; |
1612 | } | |
1613 | ||
1614 | next_bit = 0; | |
1615 | } | |
1616 | ||
1617 | return address; | |
1618 | } | |
1619 | ||
d3086444 JR |
1620 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
1621 | struct dma_ops_domain *dom, | |
6d4f343f | 1622 | unsigned int pages, |
832a90c3 JR |
1623 | unsigned long align_mask, |
1624 | u64 dma_mask) | |
d3086444 | 1625 | { |
d3086444 | 1626 | unsigned long address; |
d3086444 | 1627 | |
fe16f088 JR |
1628 | #ifdef CONFIG_IOMMU_STRESS |
1629 | dom->next_address = 0; | |
1630 | dom->need_flush = true; | |
1631 | #endif | |
d3086444 | 1632 | |
384de729 | 1633 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 1634 | dma_mask, dom->next_address); |
d3086444 | 1635 | |
1c655773 | 1636 | if (address == -1) { |
803b8cb4 | 1637 | dom->next_address = 0; |
384de729 JR |
1638 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
1639 | dma_mask, 0); | |
1c655773 JR |
1640 | dom->need_flush = true; |
1641 | } | |
d3086444 | 1642 | |
384de729 | 1643 | if (unlikely(address == -1)) |
8fd524b3 | 1644 | address = DMA_ERROR_CODE; |
d3086444 JR |
1645 | |
1646 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
1647 | ||
1648 | return address; | |
1649 | } | |
1650 | ||
431b2a20 JR |
1651 | /* |
1652 | * The address free function. | |
1653 | * | |
1654 | * called with domain->lock held | |
1655 | */ | |
d3086444 JR |
1656 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
1657 | unsigned long address, | |
1658 | unsigned int pages) | |
1659 | { | |
384de729 JR |
1660 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
1661 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 1662 | |
384de729 JR |
1663 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
1664 | ||
47bccd6b JR |
1665 | #ifdef CONFIG_IOMMU_STRESS |
1666 | if (i < 4) | |
1667 | return; | |
1668 | #endif | |
80be308d | 1669 | |
803b8cb4 | 1670 | if (address >= dom->next_address) |
80be308d | 1671 | dom->need_flush = true; |
384de729 JR |
1672 | |
1673 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 1674 | |
a66022c4 | 1675 | bitmap_clear(range->bitmap, address, pages); |
384de729 | 1676 | |
d3086444 JR |
1677 | } |
1678 | ||
431b2a20 JR |
1679 | /**************************************************************************** |
1680 | * | |
1681 | * The next functions belong to the domain allocation. A domain is | |
1682 | * allocated for every IOMMU as the default domain. If device isolation | |
1683 | * is enabled, every device get its own domain. The most important thing | |
1684 | * about domains is the page table mapping the DMA address space they | |
1685 | * contain. | |
1686 | * | |
1687 | ****************************************************************************/ | |
1688 | ||
aeb26f55 JR |
1689 | /* |
1690 | * This function adds a protection domain to the global protection domain list | |
1691 | */ | |
1692 | static void add_domain_to_list(struct protection_domain *domain) | |
1693 | { | |
1694 | unsigned long flags; | |
1695 | ||
1696 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1697 | list_add(&domain->list, &amd_iommu_pd_list); | |
1698 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1699 | } | |
1700 | ||
1701 | /* | |
1702 | * This function removes a protection domain to the global | |
1703 | * protection domain list | |
1704 | */ | |
1705 | static void del_domain_from_list(struct protection_domain *domain) | |
1706 | { | |
1707 | unsigned long flags; | |
1708 | ||
1709 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1710 | list_del(&domain->list); | |
1711 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1712 | } | |
1713 | ||
ec487d1a JR |
1714 | static u16 domain_id_alloc(void) |
1715 | { | |
1716 | unsigned long flags; | |
1717 | int id; | |
1718 | ||
1719 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1720 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1721 | BUG_ON(id == 0); | |
1722 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1723 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1724 | else | |
1725 | id = 0; | |
1726 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1727 | ||
1728 | return id; | |
1729 | } | |
1730 | ||
a2acfb75 JR |
1731 | static void domain_id_free(int id) |
1732 | { | |
1733 | unsigned long flags; | |
1734 | ||
1735 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1736 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1737 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1738 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1739 | } | |
a2acfb75 | 1740 | |
5c34c403 JR |
1741 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1742 | static void free_pt_##LVL (unsigned long __pt) \ | |
1743 | { \ | |
1744 | unsigned long p; \ | |
1745 | u64 *pt; \ | |
1746 | int i; \ | |
1747 | \ | |
1748 | pt = (u64 *)__pt; \ | |
1749 | \ | |
1750 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1751 | /* PTE present? */ \ |
5c34c403 JR |
1752 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1753 | continue; \ | |
1754 | \ | |
0b3fff54 JR |
1755 | /* Large PTE? */ \ |
1756 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1757 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1758 | continue; \ | |
1759 | \ | |
5c34c403 JR |
1760 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1761 | FN(p); \ | |
1762 | } \ | |
1763 | free_page((unsigned long)pt); \ | |
1764 | } | |
1765 | ||
1766 | DEFINE_FREE_PT_FN(l2, free_page) | |
1767 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1768 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1769 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1770 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1771 | ||
86db2e5d | 1772 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1773 | { |
5c34c403 | 1774 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1775 | |
5c34c403 JR |
1776 | switch (domain->mode) { |
1777 | case PAGE_MODE_NONE: | |
1778 | break; | |
1779 | case PAGE_MODE_1_LEVEL: | |
1780 | free_page(root); | |
1781 | break; | |
1782 | case PAGE_MODE_2_LEVEL: | |
1783 | free_pt_l2(root); | |
1784 | break; | |
1785 | case PAGE_MODE_3_LEVEL: | |
1786 | free_pt_l3(root); | |
1787 | break; | |
1788 | case PAGE_MODE_4_LEVEL: | |
1789 | free_pt_l4(root); | |
1790 | break; | |
1791 | case PAGE_MODE_5_LEVEL: | |
1792 | free_pt_l5(root); | |
1793 | break; | |
1794 | case PAGE_MODE_6_LEVEL: | |
1795 | free_pt_l6(root); | |
1796 | break; | |
1797 | default: | |
1798 | BUG(); | |
ec487d1a | 1799 | } |
ec487d1a JR |
1800 | } |
1801 | ||
b16137b1 JR |
1802 | static void free_gcr3_tbl_level1(u64 *tbl) |
1803 | { | |
1804 | u64 *ptr; | |
1805 | int i; | |
1806 | ||
1807 | for (i = 0; i < 512; ++i) { | |
1808 | if (!(tbl[i] & GCR3_VALID)) | |
1809 | continue; | |
1810 | ||
1811 | ptr = __va(tbl[i] & PAGE_MASK); | |
1812 | ||
1813 | free_page((unsigned long)ptr); | |
1814 | } | |
1815 | } | |
1816 | ||
1817 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1818 | { | |
1819 | u64 *ptr; | |
1820 | int i; | |
1821 | ||
1822 | for (i = 0; i < 512; ++i) { | |
1823 | if (!(tbl[i] & GCR3_VALID)) | |
1824 | continue; | |
1825 | ||
1826 | ptr = __va(tbl[i] & PAGE_MASK); | |
1827 | ||
1828 | free_gcr3_tbl_level1(ptr); | |
1829 | } | |
1830 | } | |
1831 | ||
52815b75 JR |
1832 | static void free_gcr3_table(struct protection_domain *domain) |
1833 | { | |
b16137b1 JR |
1834 | if (domain->glx == 2) |
1835 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1836 | else if (domain->glx == 1) | |
1837 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1838 | else |
1839 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1840 | |
52815b75 JR |
1841 | free_page((unsigned long)domain->gcr3_tbl); |
1842 | } | |
1843 | ||
431b2a20 JR |
1844 | /* |
1845 | * Free a domain, only used if something went wrong in the | |
1846 | * allocation path and we need to free an already allocated page table | |
1847 | */ | |
ec487d1a JR |
1848 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1849 | { | |
384de729 JR |
1850 | int i; |
1851 | ||
ec487d1a JR |
1852 | if (!dom) |
1853 | return; | |
1854 | ||
aeb26f55 JR |
1855 | del_domain_from_list(&dom->domain); |
1856 | ||
86db2e5d | 1857 | free_pagetable(&dom->domain); |
ec487d1a | 1858 | |
384de729 JR |
1859 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1860 | if (!dom->aperture[i]) | |
1861 | continue; | |
1862 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1863 | kfree(dom->aperture[i]); | |
1864 | } | |
ec487d1a JR |
1865 | |
1866 | kfree(dom); | |
1867 | } | |
1868 | ||
431b2a20 JR |
1869 | /* |
1870 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1871 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1872 | * structures required for the dma_ops interface |
1873 | */ | |
87a64d52 | 1874 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1875 | { |
1876 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1877 | |
1878 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1879 | if (!dma_dom) | |
1880 | return NULL; | |
1881 | ||
7a5a566e | 1882 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1883 | goto free_dma_dom; |
7a5a566e | 1884 | |
8f7a017c | 1885 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1886 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1887 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1888 | dma_dom->domain.priv = dma_dom; |
1889 | if (!dma_dom->domain.pt_root) | |
1890 | goto free_dma_dom; | |
ec487d1a | 1891 | |
1c655773 JR |
1892 | dma_dom->need_flush = false; |
1893 | ||
aeb26f55 JR |
1894 | add_domain_to_list(&dma_dom->domain); |
1895 | ||
576175c2 | 1896 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1897 | goto free_dma_dom; |
ec487d1a | 1898 | |
431b2a20 | 1899 | /* |
ec487d1a JR |
1900 | * mark the first page as allocated so we never return 0 as |
1901 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1902 | */ |
384de729 | 1903 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1904 | dma_dom->next_address = 0; |
ec487d1a | 1905 | |
ec487d1a JR |
1906 | |
1907 | return dma_dom; | |
1908 | ||
1909 | free_dma_dom: | |
1910 | dma_ops_domain_free(dma_dom); | |
1911 | ||
1912 | return NULL; | |
1913 | } | |
1914 | ||
5b28df6f JR |
1915 | /* |
1916 | * little helper function to check whether a given protection domain is a | |
1917 | * dma_ops domain | |
1918 | */ | |
1919 | static bool dma_ops_domain(struct protection_domain *domain) | |
1920 | { | |
1921 | return domain->flags & PD_DMA_OPS_MASK; | |
1922 | } | |
1923 | ||
fd7b5535 | 1924 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1925 | { |
132bd68f | 1926 | u64 pte_root = 0; |
ee6c2868 | 1927 | u64 flags = 0; |
863c74eb | 1928 | |
132bd68f JR |
1929 | if (domain->mode != PAGE_MODE_NONE) |
1930 | pte_root = virt_to_phys(domain->pt_root); | |
1931 | ||
38ddf41b JR |
1932 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1933 | << DEV_ENTRY_MODE_SHIFT; | |
1934 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1935 | |
ee6c2868 JR |
1936 | flags = amd_iommu_dev_table[devid].data[1]; |
1937 | ||
fd7b5535 JR |
1938 | if (ats) |
1939 | flags |= DTE_FLAG_IOTLB; | |
1940 | ||
52815b75 JR |
1941 | if (domain->flags & PD_IOMMUV2_MASK) { |
1942 | u64 gcr3 = __pa(domain->gcr3_tbl); | |
1943 | u64 glx = domain->glx; | |
1944 | u64 tmp; | |
1945 | ||
1946 | pte_root |= DTE_FLAG_GV; | |
1947 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1948 | ||
1949 | /* First mask out possible old values for GCR3 table */ | |
1950 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1951 | flags &= ~tmp; | |
1952 | ||
1953 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1954 | flags &= ~tmp; | |
1955 | ||
1956 | /* Encode GCR3 table into DTE */ | |
1957 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1958 | pte_root |= tmp; | |
1959 | ||
1960 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1961 | flags |= tmp; | |
1962 | ||
1963 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1964 | flags |= tmp; | |
1965 | } | |
1966 | ||
ee6c2868 JR |
1967 | flags &= ~(0xffffUL); |
1968 | flags |= domain->id; | |
1969 | ||
1970 | amd_iommu_dev_table[devid].data[1] = flags; | |
1971 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
15898bbc JR |
1972 | } |
1973 | ||
1974 | static void clear_dte_entry(u16 devid) | |
1975 | { | |
15898bbc JR |
1976 | /* remove entry from the device table seen by the hardware */ |
1977 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1978 | amd_iommu_dev_table[devid].data[1] = 0; | |
15898bbc JR |
1979 | |
1980 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1981 | } |
1982 | ||
ec9e79ef JR |
1983 | static void do_attach(struct iommu_dev_data *dev_data, |
1984 | struct protection_domain *domain) | |
7f760ddd | 1985 | { |
7f760ddd | 1986 | struct amd_iommu *iommu; |
ec9e79ef | 1987 | bool ats; |
fd7b5535 | 1988 | |
ec9e79ef JR |
1989 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
1990 | ats = dev_data->ats.enabled; | |
7f760ddd JR |
1991 | |
1992 | /* Update data structures */ | |
1993 | dev_data->domain = domain; | |
1994 | list_add(&dev_data->list, &domain->dev_list); | |
f62dda66 | 1995 | set_dte_entry(dev_data->devid, domain, ats); |
7f760ddd JR |
1996 | |
1997 | /* Do reference counting */ | |
1998 | domain->dev_iommu[iommu->index] += 1; | |
1999 | domain->dev_cnt += 1; | |
2000 | ||
2001 | /* Flush the DTE entry */ | |
6c542047 | 2002 | device_flush_dte(dev_data); |
7f760ddd JR |
2003 | } |
2004 | ||
ec9e79ef | 2005 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 2006 | { |
7f760ddd | 2007 | struct amd_iommu *iommu; |
7f760ddd | 2008 | |
ec9e79ef | 2009 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
15898bbc JR |
2010 | |
2011 | /* decrease reference counters */ | |
7f760ddd JR |
2012 | dev_data->domain->dev_iommu[iommu->index] -= 1; |
2013 | dev_data->domain->dev_cnt -= 1; | |
2014 | ||
2015 | /* Update data structures */ | |
2016 | dev_data->domain = NULL; | |
2017 | list_del(&dev_data->list); | |
f62dda66 | 2018 | clear_dte_entry(dev_data->devid); |
15898bbc | 2019 | |
7f760ddd | 2020 | /* Flush the DTE entry */ |
6c542047 | 2021 | device_flush_dte(dev_data); |
2b681faf JR |
2022 | } |
2023 | ||
2024 | /* | |
2025 | * If a device is not yet associated with a domain, this function does | |
2026 | * assigns it visible for the hardware | |
2027 | */ | |
ec9e79ef | 2028 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 2029 | struct protection_domain *domain) |
2b681faf | 2030 | { |
84fe6c19 | 2031 | int ret; |
657cbb6b | 2032 | |
2b681faf JR |
2033 | /* lock domain */ |
2034 | spin_lock(&domain->lock); | |
2035 | ||
397111ab | 2036 | ret = -EBUSY; |
150952f9 | 2037 | if (dev_data->domain != NULL) |
397111ab | 2038 | goto out_unlock; |
15898bbc | 2039 | |
397111ab | 2040 | /* Attach alias group root */ |
150952f9 | 2041 | do_attach(dev_data, domain); |
24100055 | 2042 | |
84fe6c19 JL |
2043 | ret = 0; |
2044 | ||
2045 | out_unlock: | |
2046 | ||
eba6ac60 JR |
2047 | /* ready */ |
2048 | spin_unlock(&domain->lock); | |
15898bbc | 2049 | |
84fe6c19 | 2050 | return ret; |
0feae533 | 2051 | } |
b20ac0d4 | 2052 | |
52815b75 JR |
2053 | |
2054 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2055 | { | |
2056 | pci_disable_ats(pdev); | |
2057 | pci_disable_pri(pdev); | |
2058 | pci_disable_pasid(pdev); | |
2059 | } | |
2060 | ||
6a113ddc JR |
2061 | /* FIXME: Change generic reset-function to do the same */ |
2062 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2063 | { | |
2064 | u16 control; | |
2065 | int pos; | |
2066 | ||
46277b75 | 2067 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2068 | if (!pos) |
2069 | return -EINVAL; | |
2070 | ||
46277b75 JR |
2071 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2072 | control |= PCI_PRI_CTRL_RESET; | |
2073 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2074 | |
2075 | return 0; | |
2076 | } | |
2077 | ||
52815b75 JR |
2078 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2079 | { | |
6a113ddc JR |
2080 | bool reset_enable; |
2081 | int reqs, ret; | |
2082 | ||
2083 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2084 | reqs = 32; | |
2085 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2086 | reqs = 1; | |
2087 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2088 | |
2089 | /* Only allow access to user-accessible pages */ | |
2090 | ret = pci_enable_pasid(pdev, 0); | |
2091 | if (ret) | |
2092 | goto out_err; | |
2093 | ||
2094 | /* First reset the PRI state of the device */ | |
2095 | ret = pci_reset_pri(pdev); | |
2096 | if (ret) | |
2097 | goto out_err; | |
2098 | ||
6a113ddc JR |
2099 | /* Enable PRI */ |
2100 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2101 | if (ret) |
2102 | goto out_err; | |
2103 | ||
6a113ddc JR |
2104 | if (reset_enable) { |
2105 | ret = pri_reset_while_enabled(pdev); | |
2106 | if (ret) | |
2107 | goto out_err; | |
2108 | } | |
2109 | ||
52815b75 JR |
2110 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2111 | if (ret) | |
2112 | goto out_err; | |
2113 | ||
2114 | return 0; | |
2115 | ||
2116 | out_err: | |
2117 | pci_disable_pri(pdev); | |
2118 | pci_disable_pasid(pdev); | |
2119 | ||
2120 | return ret; | |
2121 | } | |
2122 | ||
c99afa25 | 2123 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2124 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2125 | |
98f1ad25 | 2126 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2127 | { |
a3b93121 | 2128 | u16 status; |
c99afa25 JR |
2129 | int pos; |
2130 | ||
46277b75 | 2131 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2132 | if (!pos) |
2133 | return false; | |
2134 | ||
a3b93121 | 2135 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2136 | |
a3b93121 | 2137 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2138 | } |
2139 | ||
407d733e | 2140 | /* |
df805abb | 2141 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2142 | * assigns it visible for the hardware |
2143 | */ | |
15898bbc JR |
2144 | static int attach_device(struct device *dev, |
2145 | struct protection_domain *domain) | |
0feae533 | 2146 | { |
fd7b5535 | 2147 | struct pci_dev *pdev = to_pci_dev(dev); |
ea61cddb | 2148 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2149 | unsigned long flags; |
15898bbc | 2150 | int ret; |
eba6ac60 | 2151 | |
ea61cddb JR |
2152 | dev_data = get_dev_data(dev); |
2153 | ||
52815b75 | 2154 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2155 | if (!dev_data->passthrough) |
52815b75 JR |
2156 | return -EINVAL; |
2157 | ||
02ca2021 JR |
2158 | if (dev_data->iommu_v2) { |
2159 | if (pdev_iommuv2_enable(pdev) != 0) | |
2160 | return -EINVAL; | |
52815b75 | 2161 | |
02ca2021 JR |
2162 | dev_data->ats.enabled = true; |
2163 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2164 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2165 | } | |
52815b75 JR |
2166 | } else if (amd_iommu_iotlb_sup && |
2167 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2168 | dev_data->ats.enabled = true; |
2169 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2170 | } | |
fd7b5535 | 2171 | |
eba6ac60 | 2172 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2173 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2174 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2175 | ||
0feae533 JR |
2176 | /* |
2177 | * We might boot into a crash-kernel here. The crashed kernel | |
2178 | * left the caches in the IOMMU dirty. So we have to flush | |
2179 | * here to evict all dirty stuff. | |
2180 | */ | |
17b124bf | 2181 | domain_flush_tlb_pde(domain); |
15898bbc JR |
2182 | |
2183 | return ret; | |
b20ac0d4 JR |
2184 | } |
2185 | ||
355bf553 JR |
2186 | /* |
2187 | * Removes a device from a protection domain (unlocked) | |
2188 | */ | |
ec9e79ef | 2189 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2190 | { |
2ca76279 | 2191 | struct protection_domain *domain; |
c4596114 | 2192 | |
f34c73f5 JR |
2193 | if (WARN_ON(!dev_data->domain)) |
2194 | return; | |
355bf553 | 2195 | |
2ca76279 JR |
2196 | domain = dev_data->domain; |
2197 | ||
f1dd0a8b | 2198 | spin_lock(&domain->lock); |
24100055 | 2199 | |
150952f9 | 2200 | do_detach(dev_data); |
7f760ddd | 2201 | |
f1dd0a8b | 2202 | spin_unlock(&domain->lock); |
355bf553 JR |
2203 | } |
2204 | ||
2205 | /* | |
2206 | * Removes a device from a protection domain (with devtable_lock held) | |
2207 | */ | |
15898bbc | 2208 | static void detach_device(struct device *dev) |
355bf553 | 2209 | { |
52815b75 | 2210 | struct protection_domain *domain; |
ea61cddb | 2211 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2212 | unsigned long flags; |
2213 | ||
ec9e79ef | 2214 | dev_data = get_dev_data(dev); |
52815b75 | 2215 | domain = dev_data->domain; |
ec9e79ef | 2216 | |
355bf553 JR |
2217 | /* lock device table */ |
2218 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2219 | __detach_device(dev_data); |
355bf553 | 2220 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2221 | |
02ca2021 | 2222 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2223 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2224 | else if (dev_data->ats.enabled) | |
ea61cddb | 2225 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2226 | |
2227 | dev_data->ats.enabled = false; | |
355bf553 | 2228 | } |
e275a2a0 | 2229 | |
aafd8ba0 | 2230 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2231 | { |
5abcdba4 | 2232 | struct iommu_dev_data *dev_data; |
07ee8694 | 2233 | struct iommu_domain *domain; |
e275a2a0 | 2234 | struct amd_iommu *iommu; |
5abcdba4 | 2235 | u16 devid; |
aafd8ba0 | 2236 | int ret; |
e275a2a0 | 2237 | |
aafd8ba0 | 2238 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2239 | return 0; |
e275a2a0 | 2240 | |
aafd8ba0 JR |
2241 | devid = get_device_id(dev); |
2242 | iommu = amd_iommu_rlookup_table[devid]; | |
657cbb6b | 2243 | |
aafd8ba0 | 2244 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2245 | if (ret) { |
2246 | if (ret != -ENOTSUPP) | |
2247 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2248 | dev_name(dev)); | |
657cbb6b | 2249 | |
aafd8ba0 | 2250 | iommu_ignore_device(dev); |
343e9cac | 2251 | dev->archdata.dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2252 | goto out; |
2253 | } | |
2254 | init_iommu_group(dev); | |
2c9195e9 | 2255 | |
07ee8694 | 2256 | dev_data = get_dev_data(dev); |
2c9195e9 | 2257 | |
4d58b8a6 | 2258 | BUG_ON(!dev_data); |
657cbb6b | 2259 | |
1e6a7b04 | 2260 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2261 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2262 | |
07ee8694 JR |
2263 | /* Domains are initialized for this device - have a look what we ended up with */ |
2264 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2265 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2266 | dev_data->passthrough = true; |
32302324 | 2267 | else |
2c9195e9 | 2268 | dev->archdata.dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2269 | |
aafd8ba0 | 2270 | out: |
e275a2a0 JR |
2271 | iommu_completion_wait(iommu); |
2272 | ||
e275a2a0 JR |
2273 | return 0; |
2274 | } | |
2275 | ||
aafd8ba0 | 2276 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2277 | { |
aafd8ba0 JR |
2278 | struct amd_iommu *iommu; |
2279 | u16 devid; | |
2280 | ||
2281 | if (!check_device(dev)) | |
2282 | return; | |
2283 | ||
2284 | devid = get_device_id(dev); | |
2285 | iommu = amd_iommu_rlookup_table[devid]; | |
2286 | ||
2287 | iommu_uninit_device(dev); | |
2288 | iommu_completion_wait(iommu); | |
8638c491 JR |
2289 | } |
2290 | ||
431b2a20 JR |
2291 | /***************************************************************************** |
2292 | * | |
2293 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2294 | * | |
2295 | *****************************************************************************/ | |
2296 | ||
2297 | /* | |
2298 | * In the dma_ops path we only have the struct device. This function | |
2299 | * finds the corresponding IOMMU, the protection domain and the | |
2300 | * requestor id for a given device. | |
2301 | * If the device is not yet associated with a domain this is also done | |
2302 | * in this function. | |
2303 | */ | |
94f6d190 | 2304 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2305 | { |
94f6d190 | 2306 | struct protection_domain *domain; |
063071df | 2307 | struct iommu_domain *io_domain; |
b20ac0d4 | 2308 | |
f99c0f1c | 2309 | if (!check_device(dev)) |
94f6d190 | 2310 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2311 | |
063071df | 2312 | io_domain = iommu_get_domain_for_dev(dev); |
0bb6e243 JR |
2313 | if (!io_domain) |
2314 | return NULL; | |
b20ac0d4 | 2315 | |
0bb6e243 JR |
2316 | domain = to_pdomain(io_domain); |
2317 | if (!dma_ops_domain(domain)) | |
94f6d190 | 2318 | return ERR_PTR(-EBUSY); |
f91ba190 | 2319 | |
0bb6e243 | 2320 | return domain; |
b20ac0d4 JR |
2321 | } |
2322 | ||
04bfdd84 JR |
2323 | static void update_device_table(struct protection_domain *domain) |
2324 | { | |
492667da | 2325 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2326 | |
ea61cddb JR |
2327 | list_for_each_entry(dev_data, &domain->dev_list, list) |
2328 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); | |
04bfdd84 JR |
2329 | } |
2330 | ||
2331 | static void update_domain(struct protection_domain *domain) | |
2332 | { | |
2333 | if (!domain->updated) | |
2334 | return; | |
2335 | ||
2336 | update_device_table(domain); | |
17b124bf JR |
2337 | |
2338 | domain_flush_devices(domain); | |
2339 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2340 | |
2341 | domain->updated = false; | |
2342 | } | |
2343 | ||
8bda3092 JR |
2344 | /* |
2345 | * This function fetches the PTE for a given address in the aperture | |
2346 | */ | |
2347 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
2348 | unsigned long address) | |
2349 | { | |
384de729 | 2350 | struct aperture_range *aperture; |
8bda3092 JR |
2351 | u64 *pte, *pte_page; |
2352 | ||
384de729 JR |
2353 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2354 | if (!aperture) | |
2355 | return NULL; | |
2356 | ||
2357 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 2358 | if (!pte) { |
cbb9d729 | 2359 | pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page, |
abdc5eb3 | 2360 | GFP_ATOMIC); |
384de729 JR |
2361 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
2362 | } else | |
8c8c143c | 2363 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 2364 | |
04bfdd84 | 2365 | update_domain(&dom->domain); |
8bda3092 JR |
2366 | |
2367 | return pte; | |
2368 | } | |
2369 | ||
431b2a20 JR |
2370 | /* |
2371 | * This is the generic map function. It maps one 4kb page at paddr to | |
2372 | * the given address in the DMA address space for the domain. | |
2373 | */ | |
680525e0 | 2374 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
2375 | unsigned long address, |
2376 | phys_addr_t paddr, | |
2377 | int direction) | |
2378 | { | |
2379 | u64 *pte, __pte; | |
2380 | ||
2381 | WARN_ON(address > dom->aperture_size); | |
2382 | ||
2383 | paddr &= PAGE_MASK; | |
2384 | ||
8bda3092 | 2385 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 2386 | if (!pte) |
8fd524b3 | 2387 | return DMA_ERROR_CODE; |
cb76c322 JR |
2388 | |
2389 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
2390 | ||
2391 | if (direction == DMA_TO_DEVICE) | |
2392 | __pte |= IOMMU_PTE_IR; | |
2393 | else if (direction == DMA_FROM_DEVICE) | |
2394 | __pte |= IOMMU_PTE_IW; | |
2395 | else if (direction == DMA_BIDIRECTIONAL) | |
2396 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
2397 | ||
2398 | WARN_ON(*pte); | |
2399 | ||
2400 | *pte = __pte; | |
2401 | ||
2402 | return (dma_addr_t)address; | |
2403 | } | |
2404 | ||
431b2a20 JR |
2405 | /* |
2406 | * The generic unmapping function for on page in the DMA address space. | |
2407 | */ | |
680525e0 | 2408 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
2409 | unsigned long address) |
2410 | { | |
384de729 | 2411 | struct aperture_range *aperture; |
cb76c322 JR |
2412 | u64 *pte; |
2413 | ||
2414 | if (address >= dom->aperture_size) | |
2415 | return; | |
2416 | ||
384de729 JR |
2417 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
2418 | if (!aperture) | |
2419 | return; | |
2420 | ||
2421 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
2422 | if (!pte) | |
2423 | return; | |
cb76c322 | 2424 | |
8c8c143c | 2425 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
2426 | |
2427 | WARN_ON(!*pte); | |
2428 | ||
2429 | *pte = 0ULL; | |
2430 | } | |
2431 | ||
431b2a20 JR |
2432 | /* |
2433 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2434 | * contiguous memory region into DMA address space. It is used by all |
2435 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2436 | * Must be called with the domain lock held. |
2437 | */ | |
cb76c322 | 2438 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2439 | struct dma_ops_domain *dma_dom, |
2440 | phys_addr_t paddr, | |
2441 | size_t size, | |
6d4f343f | 2442 | int dir, |
832a90c3 JR |
2443 | bool align, |
2444 | u64 dma_mask) | |
cb76c322 JR |
2445 | { |
2446 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2447 | dma_addr_t address, start, ret; |
cb76c322 | 2448 | unsigned int pages; |
6d4f343f | 2449 | unsigned long align_mask = 0; |
cb76c322 JR |
2450 | int i; |
2451 | ||
e3c449f5 | 2452 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2453 | paddr &= PAGE_MASK; |
2454 | ||
8ecaf8f1 JR |
2455 | INC_STATS_COUNTER(total_map_requests); |
2456 | ||
c1858976 JR |
2457 | if (pages > 1) |
2458 | INC_STATS_COUNTER(cross_page); | |
2459 | ||
6d4f343f JR |
2460 | if (align) |
2461 | align_mask = (1UL << get_order(size)) - 1; | |
2462 | ||
11b83888 | 2463 | retry: |
832a90c3 JR |
2464 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
2465 | dma_mask); | |
8fd524b3 | 2466 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
2467 | /* |
2468 | * setting next_address here will let the address | |
2469 | * allocator only scan the new allocated range in the | |
2470 | * first run. This is a small optimization. | |
2471 | */ | |
2472 | dma_dom->next_address = dma_dom->aperture_size; | |
2473 | ||
576175c2 | 2474 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
2475 | goto out; |
2476 | ||
2477 | /* | |
af901ca1 | 2478 | * aperture was successfully enlarged by 128 MB, try |
11b83888 JR |
2479 | * allocation again |
2480 | */ | |
2481 | goto retry; | |
2482 | } | |
cb76c322 JR |
2483 | |
2484 | start = address; | |
2485 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2486 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 2487 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
2488 | goto out_unmap; |
2489 | ||
cb76c322 JR |
2490 | paddr += PAGE_SIZE; |
2491 | start += PAGE_SIZE; | |
2492 | } | |
2493 | address += offset; | |
2494 | ||
5774f7c5 JR |
2495 | ADD_STATS_COUNTER(alloced_io_mem, size); |
2496 | ||
afa9fdc2 | 2497 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
17b124bf | 2498 | domain_flush_tlb(&dma_dom->domain); |
1c655773 | 2499 | dma_dom->need_flush = false; |
318afd41 | 2500 | } else if (unlikely(amd_iommu_np_cache)) |
17b124bf | 2501 | domain_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 2502 | |
cb76c322 JR |
2503 | out: |
2504 | return address; | |
53812c11 JR |
2505 | |
2506 | out_unmap: | |
2507 | ||
2508 | for (--i; i >= 0; --i) { | |
2509 | start -= PAGE_SIZE; | |
680525e0 | 2510 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
2511 | } |
2512 | ||
2513 | dma_ops_free_addresses(dma_dom, address, pages); | |
2514 | ||
8fd524b3 | 2515 | return DMA_ERROR_CODE; |
cb76c322 JR |
2516 | } |
2517 | ||
431b2a20 JR |
2518 | /* |
2519 | * Does the reverse of the __map_single function. Must be called with | |
2520 | * the domain lock held too | |
2521 | */ | |
cd8c82e8 | 2522 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2523 | dma_addr_t dma_addr, |
2524 | size_t size, | |
2525 | int dir) | |
2526 | { | |
04e0463e | 2527 | dma_addr_t flush_addr; |
cb76c322 JR |
2528 | dma_addr_t i, start; |
2529 | unsigned int pages; | |
2530 | ||
8fd524b3 | 2531 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 2532 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
2533 | return; |
2534 | ||
04e0463e | 2535 | flush_addr = dma_addr; |
e3c449f5 | 2536 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2537 | dma_addr &= PAGE_MASK; |
2538 | start = dma_addr; | |
2539 | ||
2540 | for (i = 0; i < pages; ++i) { | |
680525e0 | 2541 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
2542 | start += PAGE_SIZE; |
2543 | } | |
2544 | ||
5774f7c5 JR |
2545 | SUB_STATS_COUNTER(alloced_io_mem, size); |
2546 | ||
cb76c322 | 2547 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 2548 | |
80be308d | 2549 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
17b124bf | 2550 | domain_flush_pages(&dma_dom->domain, flush_addr, size); |
80be308d JR |
2551 | dma_dom->need_flush = false; |
2552 | } | |
cb76c322 JR |
2553 | } |
2554 | ||
431b2a20 JR |
2555 | /* |
2556 | * The exported map_single function for dma_ops. | |
2557 | */ | |
51491367 FT |
2558 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2559 | unsigned long offset, size_t size, | |
2560 | enum dma_data_direction dir, | |
2561 | struct dma_attrs *attrs) | |
4da70b9e JR |
2562 | { |
2563 | unsigned long flags; | |
4da70b9e | 2564 | struct protection_domain *domain; |
4da70b9e | 2565 | dma_addr_t addr; |
832a90c3 | 2566 | u64 dma_mask; |
51491367 | 2567 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2568 | |
0f2a86f2 JR |
2569 | INC_STATS_COUNTER(cnt_map_single); |
2570 | ||
94f6d190 JR |
2571 | domain = get_domain(dev); |
2572 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2573 | return (dma_addr_t)paddr; |
94f6d190 JR |
2574 | else if (IS_ERR(domain)) |
2575 | return DMA_ERROR_CODE; | |
4da70b9e | 2576 | |
f99c0f1c JR |
2577 | dma_mask = *dev->dma_mask; |
2578 | ||
4da70b9e | 2579 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 2580 | |
cd8c82e8 | 2581 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 2582 | dma_mask); |
8fd524b3 | 2583 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
2584 | goto out; |
2585 | ||
17b124bf | 2586 | domain_flush_complete(domain); |
4da70b9e JR |
2587 | |
2588 | out: | |
2589 | spin_unlock_irqrestore(&domain->lock, flags); | |
2590 | ||
2591 | return addr; | |
2592 | } | |
2593 | ||
431b2a20 JR |
2594 | /* |
2595 | * The exported unmap_single function for dma_ops. | |
2596 | */ | |
51491367 FT |
2597 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
2598 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
2599 | { |
2600 | unsigned long flags; | |
4da70b9e | 2601 | struct protection_domain *domain; |
4da70b9e | 2602 | |
146a6917 JR |
2603 | INC_STATS_COUNTER(cnt_unmap_single); |
2604 | ||
94f6d190 JR |
2605 | domain = get_domain(dev); |
2606 | if (IS_ERR(domain)) | |
5b28df6f JR |
2607 | return; |
2608 | ||
4da70b9e JR |
2609 | spin_lock_irqsave(&domain->lock, flags); |
2610 | ||
cd8c82e8 | 2611 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 2612 | |
17b124bf | 2613 | domain_flush_complete(domain); |
4da70b9e JR |
2614 | |
2615 | spin_unlock_irqrestore(&domain->lock, flags); | |
2616 | } | |
2617 | ||
431b2a20 JR |
2618 | /* |
2619 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2620 | * lists). | |
2621 | */ | |
65b050ad | 2622 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2623 | int nelems, enum dma_data_direction dir, |
2624 | struct dma_attrs *attrs) | |
65b050ad JR |
2625 | { |
2626 | unsigned long flags; | |
65b050ad | 2627 | struct protection_domain *domain; |
65b050ad JR |
2628 | int i; |
2629 | struct scatterlist *s; | |
2630 | phys_addr_t paddr; | |
2631 | int mapped_elems = 0; | |
832a90c3 | 2632 | u64 dma_mask; |
65b050ad | 2633 | |
d03f067a JR |
2634 | INC_STATS_COUNTER(cnt_map_sg); |
2635 | ||
94f6d190 | 2636 | domain = get_domain(dev); |
a0e191b2 | 2637 | if (IS_ERR(domain)) |
94f6d190 | 2638 | return 0; |
dbcc112e | 2639 | |
832a90c3 | 2640 | dma_mask = *dev->dma_mask; |
65b050ad | 2641 | |
65b050ad JR |
2642 | spin_lock_irqsave(&domain->lock, flags); |
2643 | ||
2644 | for_each_sg(sglist, s, nelems, i) { | |
2645 | paddr = sg_phys(s); | |
2646 | ||
cd8c82e8 | 2647 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
2648 | paddr, s->length, dir, false, |
2649 | dma_mask); | |
65b050ad JR |
2650 | |
2651 | if (s->dma_address) { | |
2652 | s->dma_length = s->length; | |
2653 | mapped_elems++; | |
2654 | } else | |
2655 | goto unmap; | |
65b050ad JR |
2656 | } |
2657 | ||
17b124bf | 2658 | domain_flush_complete(domain); |
65b050ad JR |
2659 | |
2660 | out: | |
2661 | spin_unlock_irqrestore(&domain->lock, flags); | |
2662 | ||
2663 | return mapped_elems; | |
2664 | unmap: | |
2665 | for_each_sg(sglist, s, mapped_elems, i) { | |
2666 | if (s->dma_address) | |
cd8c82e8 | 2667 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
2668 | s->dma_length, dir); |
2669 | s->dma_address = s->dma_length = 0; | |
2670 | } | |
2671 | ||
2672 | mapped_elems = 0; | |
2673 | ||
2674 | goto out; | |
2675 | } | |
2676 | ||
431b2a20 JR |
2677 | /* |
2678 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2679 | * lists). | |
2680 | */ | |
65b050ad | 2681 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
2682 | int nelems, enum dma_data_direction dir, |
2683 | struct dma_attrs *attrs) | |
65b050ad JR |
2684 | { |
2685 | unsigned long flags; | |
65b050ad JR |
2686 | struct protection_domain *domain; |
2687 | struct scatterlist *s; | |
65b050ad JR |
2688 | int i; |
2689 | ||
55877a6b JR |
2690 | INC_STATS_COUNTER(cnt_unmap_sg); |
2691 | ||
94f6d190 JR |
2692 | domain = get_domain(dev); |
2693 | if (IS_ERR(domain)) | |
5b28df6f JR |
2694 | return; |
2695 | ||
65b050ad JR |
2696 | spin_lock_irqsave(&domain->lock, flags); |
2697 | ||
2698 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 2699 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 2700 | s->dma_length, dir); |
65b050ad JR |
2701 | s->dma_address = s->dma_length = 0; |
2702 | } | |
2703 | ||
17b124bf | 2704 | domain_flush_complete(domain); |
65b050ad JR |
2705 | |
2706 | spin_unlock_irqrestore(&domain->lock, flags); | |
2707 | } | |
2708 | ||
431b2a20 JR |
2709 | /* |
2710 | * The exported alloc_coherent function for dma_ops. | |
2711 | */ | |
5d8b53cf | 2712 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
2713 | dma_addr_t *dma_addr, gfp_t flag, |
2714 | struct dma_attrs *attrs) | |
5d8b53cf | 2715 | { |
832a90c3 | 2716 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 JR |
2717 | struct protection_domain *domain; |
2718 | unsigned long flags; | |
2719 | struct page *page; | |
5d8b53cf | 2720 | |
c8f0fb36 JR |
2721 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2722 | ||
94f6d190 JR |
2723 | domain = get_domain(dev); |
2724 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2725 | page = alloc_pages(flag, get_order(size)); |
2726 | *dma_addr = page_to_phys(page); | |
2727 | return page_address(page); | |
94f6d190 JR |
2728 | } else if (IS_ERR(domain)) |
2729 | return NULL; | |
5d8b53cf | 2730 | |
3b839a57 | 2731 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2732 | dma_mask = dev->coherent_dma_mask; |
2733 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2734 | flag |= __GFP_ZERO; |
5d8b53cf | 2735 | |
3b839a57 JR |
2736 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2737 | if (!page) { | |
2738 | if (!(flag & __GFP_WAIT)) | |
2739 | return NULL; | |
5d8b53cf | 2740 | |
3b839a57 JR |
2741 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
2742 | get_order(size)); | |
2743 | if (!page) | |
2744 | return NULL; | |
2745 | } | |
5d8b53cf | 2746 | |
832a90c3 JR |
2747 | if (!dma_mask) |
2748 | dma_mask = *dev->dma_mask; | |
2749 | ||
5d8b53cf JR |
2750 | spin_lock_irqsave(&domain->lock, flags); |
2751 | ||
3b839a57 | 2752 | *dma_addr = __map_single(dev, domain->priv, page_to_phys(page), |
832a90c3 | 2753 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2754 | |
8fd524b3 | 2755 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2756 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2757 | goto out_free; |
367d04c4 | 2758 | } |
5d8b53cf | 2759 | |
17b124bf | 2760 | domain_flush_complete(domain); |
5d8b53cf | 2761 | |
5d8b53cf JR |
2762 | spin_unlock_irqrestore(&domain->lock, flags); |
2763 | ||
3b839a57 | 2764 | return page_address(page); |
5b28df6f JR |
2765 | |
2766 | out_free: | |
2767 | ||
3b839a57 JR |
2768 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2769 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2770 | |
2771 | return NULL; | |
5d8b53cf JR |
2772 | } |
2773 | ||
431b2a20 JR |
2774 | /* |
2775 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2776 | */ |
5d8b53cf | 2777 | static void free_coherent(struct device *dev, size_t size, |
baa676fc AP |
2778 | void *virt_addr, dma_addr_t dma_addr, |
2779 | struct dma_attrs *attrs) | |
5d8b53cf | 2780 | { |
5d8b53cf | 2781 | struct protection_domain *domain; |
3b839a57 JR |
2782 | unsigned long flags; |
2783 | struct page *page; | |
5d8b53cf | 2784 | |
5d31ee7e JR |
2785 | INC_STATS_COUNTER(cnt_free_coherent); |
2786 | ||
3b839a57 JR |
2787 | page = virt_to_page(virt_addr); |
2788 | size = PAGE_ALIGN(size); | |
2789 | ||
94f6d190 JR |
2790 | domain = get_domain(dev); |
2791 | if (IS_ERR(domain)) | |
5b28df6f JR |
2792 | goto free_mem; |
2793 | ||
5d8b53cf JR |
2794 | spin_lock_irqsave(&domain->lock, flags); |
2795 | ||
cd8c82e8 | 2796 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2797 | |
17b124bf | 2798 | domain_flush_complete(domain); |
5d8b53cf JR |
2799 | |
2800 | spin_unlock_irqrestore(&domain->lock, flags); | |
2801 | ||
2802 | free_mem: | |
3b839a57 JR |
2803 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2804 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2805 | } |
2806 | ||
b39ba6ad JR |
2807 | /* |
2808 | * This function is called by the DMA layer to find out if we can handle a | |
2809 | * particular device. It is part of the dma_ops. | |
2810 | */ | |
2811 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2812 | { | |
420aef8a | 2813 | return check_device(dev); |
b39ba6ad JR |
2814 | } |
2815 | ||
160c1d8e | 2816 | static struct dma_map_ops amd_iommu_dma_ops = { |
baa676fc AP |
2817 | .alloc = alloc_coherent, |
2818 | .free = free_coherent, | |
51491367 FT |
2819 | .map_page = map_page, |
2820 | .unmap_page = unmap_page, | |
6631ee9d JR |
2821 | .map_sg = map_sg, |
2822 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2823 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2824 | }; |
2825 | ||
3a18404c | 2826 | int __init amd_iommu_init_api(void) |
27c2127a | 2827 | { |
3a18404c | 2828 | return bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
f5325094 JR |
2829 | } |
2830 | ||
6631ee9d JR |
2831 | int __init amd_iommu_init_dma_ops(void) |
2832 | { | |
32302324 | 2833 | swiotlb = iommu_pass_through ? 1 : 0; |
6631ee9d | 2834 | iommu_detected = 1; |
6631ee9d | 2835 | |
52717828 JR |
2836 | /* |
2837 | * In case we don't initialize SWIOTLB (actually the common case | |
2838 | * when AMD IOMMU is enabled), make sure there are global | |
2839 | * dma_ops set as a fall-back for devices not handled by this | |
2840 | * driver (for example non-PCI devices). | |
2841 | */ | |
2842 | if (!swiotlb) | |
2843 | dma_ops = &nommu_dma_ops; | |
2844 | ||
7f26508b JR |
2845 | amd_iommu_stats_init(); |
2846 | ||
62410eeb JR |
2847 | if (amd_iommu_unmap_flush) |
2848 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2849 | else | |
2850 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2851 | ||
6631ee9d | 2852 | return 0; |
6631ee9d | 2853 | } |
6d98cd80 JR |
2854 | |
2855 | /***************************************************************************** | |
2856 | * | |
2857 | * The following functions belong to the exported interface of AMD IOMMU | |
2858 | * | |
2859 | * This interface allows access to lower level functions of the IOMMU | |
2860 | * like protection domain handling and assignement of devices to domains | |
2861 | * which is not possible with the dma_ops interface. | |
2862 | * | |
2863 | *****************************************************************************/ | |
2864 | ||
6d98cd80 JR |
2865 | static void cleanup_domain(struct protection_domain *domain) |
2866 | { | |
9b29d3c6 | 2867 | struct iommu_dev_data *entry; |
6d98cd80 | 2868 | unsigned long flags; |
6d98cd80 JR |
2869 | |
2870 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2871 | ||
9b29d3c6 JR |
2872 | while (!list_empty(&domain->dev_list)) { |
2873 | entry = list_first_entry(&domain->dev_list, | |
2874 | struct iommu_dev_data, list); | |
2875 | __detach_device(entry); | |
492667da | 2876 | } |
6d98cd80 JR |
2877 | |
2878 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2879 | } | |
2880 | ||
2650815f JR |
2881 | static void protection_domain_free(struct protection_domain *domain) |
2882 | { | |
2883 | if (!domain) | |
2884 | return; | |
2885 | ||
aeb26f55 JR |
2886 | del_domain_from_list(domain); |
2887 | ||
2650815f JR |
2888 | if (domain->id) |
2889 | domain_id_free(domain->id); | |
2890 | ||
2891 | kfree(domain); | |
2892 | } | |
2893 | ||
7a5a566e JR |
2894 | static int protection_domain_init(struct protection_domain *domain) |
2895 | { | |
2896 | spin_lock_init(&domain->lock); | |
2897 | mutex_init(&domain->api_lock); | |
2898 | domain->id = domain_id_alloc(); | |
2899 | if (!domain->id) | |
2900 | return -ENOMEM; | |
2901 | INIT_LIST_HEAD(&domain->dev_list); | |
2902 | ||
2903 | return 0; | |
2904 | } | |
2905 | ||
2650815f | 2906 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2907 | { |
2908 | struct protection_domain *domain; | |
2909 | ||
2910 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2911 | if (!domain) | |
2650815f | 2912 | return NULL; |
c156e347 | 2913 | |
7a5a566e | 2914 | if (protection_domain_init(domain)) |
2650815f JR |
2915 | goto out_err; |
2916 | ||
aeb26f55 JR |
2917 | add_domain_to_list(domain); |
2918 | ||
2650815f JR |
2919 | return domain; |
2920 | ||
2921 | out_err: | |
2922 | kfree(domain); | |
2923 | ||
2924 | return NULL; | |
2925 | } | |
2926 | ||
3f4b87b9 | 2927 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2928 | { |
3f4b87b9 | 2929 | struct protection_domain *pdomain; |
0bb6e243 | 2930 | struct dma_ops_domain *dma_domain; |
2650815f | 2931 | |
0bb6e243 JR |
2932 | switch (type) { |
2933 | case IOMMU_DOMAIN_UNMANAGED: | |
2934 | pdomain = protection_domain_alloc(); | |
2935 | if (!pdomain) | |
2936 | return NULL; | |
c156e347 | 2937 | |
0bb6e243 JR |
2938 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2939 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2940 | if (!pdomain->pt_root) { | |
2941 | protection_domain_free(pdomain); | |
2942 | return NULL; | |
2943 | } | |
c156e347 | 2944 | |
0bb6e243 JR |
2945 | pdomain->domain.geometry.aperture_start = 0; |
2946 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2947 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2948 | |
0bb6e243 JR |
2949 | break; |
2950 | case IOMMU_DOMAIN_DMA: | |
2951 | dma_domain = dma_ops_domain_alloc(); | |
2952 | if (!dma_domain) { | |
2953 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2954 | return NULL; | |
2955 | } | |
2956 | pdomain = &dma_domain->domain; | |
2957 | break; | |
07f643a3 JR |
2958 | case IOMMU_DOMAIN_IDENTITY: |
2959 | pdomain = protection_domain_alloc(); | |
2960 | if (!pdomain) | |
2961 | return NULL; | |
c156e347 | 2962 | |
07f643a3 JR |
2963 | pdomain->mode = PAGE_MODE_NONE; |
2964 | break; | |
0bb6e243 JR |
2965 | default: |
2966 | return NULL; | |
2967 | } | |
c156e347 | 2968 | |
3f4b87b9 | 2969 | return &pdomain->domain; |
c156e347 JR |
2970 | } |
2971 | ||
3f4b87b9 | 2972 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2973 | { |
3f4b87b9 | 2974 | struct protection_domain *domain; |
98383fc3 | 2975 | |
3f4b87b9 | 2976 | if (!dom) |
98383fc3 JR |
2977 | return; |
2978 | ||
3f4b87b9 JR |
2979 | domain = to_pdomain(dom); |
2980 | ||
98383fc3 JR |
2981 | if (domain->dev_cnt > 0) |
2982 | cleanup_domain(domain); | |
2983 | ||
2984 | BUG_ON(domain->dev_cnt != 0); | |
2985 | ||
132bd68f JR |
2986 | if (domain->mode != PAGE_MODE_NONE) |
2987 | free_pagetable(domain); | |
98383fc3 | 2988 | |
52815b75 JR |
2989 | if (domain->flags & PD_IOMMUV2_MASK) |
2990 | free_gcr3_table(domain); | |
2991 | ||
8b408fe4 | 2992 | protection_domain_free(domain); |
98383fc3 JR |
2993 | } |
2994 | ||
684f2888 JR |
2995 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2996 | struct device *dev) | |
2997 | { | |
657cbb6b | 2998 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 2999 | struct amd_iommu *iommu; |
684f2888 JR |
3000 | u16 devid; |
3001 | ||
98fc5a69 | 3002 | if (!check_device(dev)) |
684f2888 JR |
3003 | return; |
3004 | ||
98fc5a69 | 3005 | devid = get_device_id(dev); |
684f2888 | 3006 | |
657cbb6b | 3007 | if (dev_data->domain != NULL) |
15898bbc | 3008 | detach_device(dev); |
684f2888 JR |
3009 | |
3010 | iommu = amd_iommu_rlookup_table[devid]; | |
3011 | if (!iommu) | |
3012 | return; | |
3013 | ||
684f2888 JR |
3014 | iommu_completion_wait(iommu); |
3015 | } | |
3016 | ||
01106066 JR |
3017 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3018 | struct device *dev) | |
3019 | { | |
3f4b87b9 | 3020 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3021 | struct iommu_dev_data *dev_data; |
01106066 | 3022 | struct amd_iommu *iommu; |
15898bbc | 3023 | int ret; |
01106066 | 3024 | |
98fc5a69 | 3025 | if (!check_device(dev)) |
01106066 JR |
3026 | return -EINVAL; |
3027 | ||
657cbb6b JR |
3028 | dev_data = dev->archdata.iommu; |
3029 | ||
f62dda66 | 3030 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3031 | if (!iommu) |
3032 | return -EINVAL; | |
3033 | ||
657cbb6b | 3034 | if (dev_data->domain) |
15898bbc | 3035 | detach_device(dev); |
01106066 | 3036 | |
15898bbc | 3037 | ret = attach_device(dev, domain); |
01106066 JR |
3038 | |
3039 | iommu_completion_wait(iommu); | |
3040 | ||
15898bbc | 3041 | return ret; |
01106066 JR |
3042 | } |
3043 | ||
468e2366 | 3044 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3045 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3046 | { |
3f4b87b9 | 3047 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3048 | int prot = 0; |
3049 | int ret; | |
3050 | ||
132bd68f JR |
3051 | if (domain->mode == PAGE_MODE_NONE) |
3052 | return -EINVAL; | |
3053 | ||
c6229ca6 JR |
3054 | if (iommu_prot & IOMMU_READ) |
3055 | prot |= IOMMU_PROT_IR; | |
3056 | if (iommu_prot & IOMMU_WRITE) | |
3057 | prot |= IOMMU_PROT_IW; | |
3058 | ||
5d214fe6 | 3059 | mutex_lock(&domain->api_lock); |
795e74f7 | 3060 | ret = iommu_map_page(domain, iova, paddr, prot, page_size); |
5d214fe6 JR |
3061 | mutex_unlock(&domain->api_lock); |
3062 | ||
795e74f7 | 3063 | return ret; |
c6229ca6 JR |
3064 | } |
3065 | ||
5009065d OBC |
3066 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3067 | size_t page_size) | |
eb74ff6c | 3068 | { |
3f4b87b9 | 3069 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3070 | size_t unmap_size; |
eb74ff6c | 3071 | |
132bd68f JR |
3072 | if (domain->mode == PAGE_MODE_NONE) |
3073 | return -EINVAL; | |
3074 | ||
5d214fe6 | 3075 | mutex_lock(&domain->api_lock); |
468e2366 | 3076 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3077 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3078 | |
17b124bf | 3079 | domain_flush_tlb_pde(domain); |
5d214fe6 | 3080 | |
5009065d | 3081 | return unmap_size; |
eb74ff6c JR |
3082 | } |
3083 | ||
645c4c8d | 3084 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3085 | dma_addr_t iova) |
645c4c8d | 3086 | { |
3f4b87b9 | 3087 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3088 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3089 | u64 *pte, __pte; |
645c4c8d | 3090 | |
132bd68f JR |
3091 | if (domain->mode == PAGE_MODE_NONE) |
3092 | return iova; | |
3093 | ||
3039ca1b | 3094 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3095 | |
a6d41a40 | 3096 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3097 | return 0; |
3098 | ||
b24b1b63 JR |
3099 | offset_mask = pte_pgsize - 1; |
3100 | __pte = *pte & PM_ADDR_MASK; | |
645c4c8d | 3101 | |
b24b1b63 | 3102 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3103 | } |
3104 | ||
ab636481 | 3105 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3106 | { |
80a506b8 JR |
3107 | switch (cap) { |
3108 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3109 | return true; |
bdddadcb | 3110 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3111 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3112 | case IOMMU_CAP_NOEXEC: |
3113 | return false; | |
80a506b8 JR |
3114 | } |
3115 | ||
ab636481 | 3116 | return false; |
dbb9fd86 SY |
3117 | } |
3118 | ||
35cf248f JR |
3119 | static void amd_iommu_get_dm_regions(struct device *dev, |
3120 | struct list_head *head) | |
3121 | { | |
3122 | struct unity_map_entry *entry; | |
3123 | u16 devid; | |
3124 | ||
3125 | devid = get_device_id(dev); | |
3126 | ||
3127 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
3128 | struct iommu_dm_region *region; | |
3129 | ||
3130 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3131 | continue; | |
3132 | ||
3133 | region = kzalloc(sizeof(*region), GFP_KERNEL); | |
3134 | if (!region) { | |
3135 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3136 | dev_name(dev)); | |
3137 | return; | |
3138 | } | |
3139 | ||
3140 | region->start = entry->address_start; | |
3141 | region->length = entry->address_end - entry->address_start; | |
3142 | if (entry->prot & IOMMU_PROT_IR) | |
3143 | region->prot |= IOMMU_READ; | |
3144 | if (entry->prot & IOMMU_PROT_IW) | |
3145 | region->prot |= IOMMU_WRITE; | |
3146 | ||
3147 | list_add_tail(®ion->list, head); | |
3148 | } | |
3149 | } | |
3150 | ||
3151 | static void amd_iommu_put_dm_regions(struct device *dev, | |
3152 | struct list_head *head) | |
3153 | { | |
3154 | struct iommu_dm_region *entry, *next; | |
3155 | ||
3156 | list_for_each_entry_safe(entry, next, head, list) | |
3157 | kfree(entry); | |
3158 | } | |
3159 | ||
b22f6434 | 3160 | static const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3161 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3162 | .domain_alloc = amd_iommu_domain_alloc, |
3163 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3164 | .attach_dev = amd_iommu_attach_device, |
3165 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3166 | .map = amd_iommu_map, |
3167 | .unmap = amd_iommu_unmap, | |
315786eb | 3168 | .map_sg = default_iommu_map_sg, |
26961efe | 3169 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3170 | .add_device = amd_iommu_add_device, |
3171 | .remove_device = amd_iommu_remove_device, | |
35cf248f JR |
3172 | .get_dm_regions = amd_iommu_get_dm_regions, |
3173 | .put_dm_regions = amd_iommu_put_dm_regions, | |
aa3de9c0 | 3174 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3175 | }; |
3176 | ||
0feae533 JR |
3177 | /***************************************************************************** |
3178 | * | |
3179 | * The next functions do a basic initialization of IOMMU for pass through | |
3180 | * mode | |
3181 | * | |
3182 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3183 | * DMA-API translation. | |
3184 | * | |
3185 | *****************************************************************************/ | |
3186 | ||
72e1dcc4 JR |
3187 | /* IOMMUv2 specific functions */ |
3188 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3189 | { | |
3190 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3191 | } | |
3192 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3193 | ||
3194 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3195 | { | |
3196 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3197 | } | |
3198 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3199 | |
3200 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3201 | { | |
3f4b87b9 | 3202 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3203 | unsigned long flags; |
3204 | ||
3205 | spin_lock_irqsave(&domain->lock, flags); | |
3206 | ||
3207 | /* Update data structure */ | |
3208 | domain->mode = PAGE_MODE_NONE; | |
3209 | domain->updated = true; | |
3210 | ||
3211 | /* Make changes visible to IOMMUs */ | |
3212 | update_domain(domain); | |
3213 | ||
3214 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3215 | free_pagetable(domain); | |
3216 | ||
3217 | spin_unlock_irqrestore(&domain->lock, flags); | |
3218 | } | |
3219 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3220 | |
3221 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3222 | { | |
3f4b87b9 | 3223 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3224 | unsigned long flags; |
3225 | int levels, ret; | |
3226 | ||
3227 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3228 | return -EINVAL; | |
3229 | ||
3230 | /* Number of GCR3 table levels required */ | |
3231 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3232 | levels += 1; | |
3233 | ||
3234 | if (levels > amd_iommu_max_glx_val) | |
3235 | return -EINVAL; | |
3236 | ||
3237 | spin_lock_irqsave(&domain->lock, flags); | |
3238 | ||
3239 | /* | |
3240 | * Save us all sanity checks whether devices already in the | |
3241 | * domain support IOMMUv2. Just force that the domain has no | |
3242 | * devices attached when it is switched into IOMMUv2 mode. | |
3243 | */ | |
3244 | ret = -EBUSY; | |
3245 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3246 | goto out; | |
3247 | ||
3248 | ret = -ENOMEM; | |
3249 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3250 | if (domain->gcr3_tbl == NULL) | |
3251 | goto out; | |
3252 | ||
3253 | domain->glx = levels; | |
3254 | domain->flags |= PD_IOMMUV2_MASK; | |
3255 | domain->updated = true; | |
3256 | ||
3257 | update_domain(domain); | |
3258 | ||
3259 | ret = 0; | |
3260 | ||
3261 | out: | |
3262 | spin_unlock_irqrestore(&domain->lock, flags); | |
3263 | ||
3264 | return ret; | |
3265 | } | |
3266 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3267 | |
3268 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3269 | u64 address, bool size) | |
3270 | { | |
3271 | struct iommu_dev_data *dev_data; | |
3272 | struct iommu_cmd cmd; | |
3273 | int i, ret; | |
3274 | ||
3275 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3276 | return -EINVAL; | |
3277 | ||
3278 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3279 | ||
3280 | /* | |
3281 | * IOMMU TLB needs to be flushed before Device TLB to | |
3282 | * prevent device TLB refill from IOMMU TLB | |
3283 | */ | |
3284 | for (i = 0; i < amd_iommus_present; ++i) { | |
3285 | if (domain->dev_iommu[i] == 0) | |
3286 | continue; | |
3287 | ||
3288 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3289 | if (ret != 0) | |
3290 | goto out; | |
3291 | } | |
3292 | ||
3293 | /* Wait until IOMMU TLB flushes are complete */ | |
3294 | domain_flush_complete(domain); | |
3295 | ||
3296 | /* Now flush device TLBs */ | |
3297 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3298 | struct amd_iommu *iommu; | |
3299 | int qdep; | |
3300 | ||
1c1cc454 JR |
3301 | /* |
3302 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3303 | * domain. | |
3304 | */ | |
3305 | if (!dev_data->ats.enabled) | |
3306 | continue; | |
22e266c7 JR |
3307 | |
3308 | qdep = dev_data->ats.qdep; | |
3309 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3310 | ||
3311 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3312 | qdep, address, size); | |
3313 | ||
3314 | ret = iommu_queue_command(iommu, &cmd); | |
3315 | if (ret != 0) | |
3316 | goto out; | |
3317 | } | |
3318 | ||
3319 | /* Wait until all device TLBs are flushed */ | |
3320 | domain_flush_complete(domain); | |
3321 | ||
3322 | ret = 0; | |
3323 | ||
3324 | out: | |
3325 | ||
3326 | return ret; | |
3327 | } | |
3328 | ||
3329 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3330 | u64 address) | |
3331 | { | |
399be2f5 JR |
3332 | INC_STATS_COUNTER(invalidate_iotlb); |
3333 | ||
22e266c7 JR |
3334 | return __flush_pasid(domain, pasid, address, false); |
3335 | } | |
3336 | ||
3337 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3338 | u64 address) | |
3339 | { | |
3f4b87b9 | 3340 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3341 | unsigned long flags; |
3342 | int ret; | |
3343 | ||
3344 | spin_lock_irqsave(&domain->lock, flags); | |
3345 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3346 | spin_unlock_irqrestore(&domain->lock, flags); | |
3347 | ||
3348 | return ret; | |
3349 | } | |
3350 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3351 | ||
3352 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3353 | { | |
399be2f5 JR |
3354 | INC_STATS_COUNTER(invalidate_iotlb_all); |
3355 | ||
22e266c7 JR |
3356 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
3357 | true); | |
3358 | } | |
3359 | ||
3360 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3361 | { | |
3f4b87b9 | 3362 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3363 | unsigned long flags; |
3364 | int ret; | |
3365 | ||
3366 | spin_lock_irqsave(&domain->lock, flags); | |
3367 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3368 | spin_unlock_irqrestore(&domain->lock, flags); | |
3369 | ||
3370 | return ret; | |
3371 | } | |
3372 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3373 | ||
b16137b1 JR |
3374 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3375 | { | |
3376 | int index; | |
3377 | u64 *pte; | |
3378 | ||
3379 | while (true) { | |
3380 | ||
3381 | index = (pasid >> (9 * level)) & 0x1ff; | |
3382 | pte = &root[index]; | |
3383 | ||
3384 | if (level == 0) | |
3385 | break; | |
3386 | ||
3387 | if (!(*pte & GCR3_VALID)) { | |
3388 | if (!alloc) | |
3389 | return NULL; | |
3390 | ||
3391 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3392 | if (root == NULL) | |
3393 | return NULL; | |
3394 | ||
3395 | *pte = __pa(root) | GCR3_VALID; | |
3396 | } | |
3397 | ||
3398 | root = __va(*pte & PAGE_MASK); | |
3399 | ||
3400 | level -= 1; | |
3401 | } | |
3402 | ||
3403 | return pte; | |
3404 | } | |
3405 | ||
3406 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3407 | unsigned long cr3) | |
3408 | { | |
3409 | u64 *pte; | |
3410 | ||
3411 | if (domain->mode != PAGE_MODE_NONE) | |
3412 | return -EINVAL; | |
3413 | ||
3414 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3415 | if (pte == NULL) | |
3416 | return -ENOMEM; | |
3417 | ||
3418 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3419 | ||
3420 | return __amd_iommu_flush_tlb(domain, pasid); | |
3421 | } | |
3422 | ||
3423 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3424 | { | |
3425 | u64 *pte; | |
3426 | ||
3427 | if (domain->mode != PAGE_MODE_NONE) | |
3428 | return -EINVAL; | |
3429 | ||
3430 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3431 | if (pte == NULL) | |
3432 | return 0; | |
3433 | ||
3434 | *pte = 0; | |
3435 | ||
3436 | return __amd_iommu_flush_tlb(domain, pasid); | |
3437 | } | |
3438 | ||
3439 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3440 | unsigned long cr3) | |
3441 | { | |
3f4b87b9 | 3442 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3443 | unsigned long flags; |
3444 | int ret; | |
3445 | ||
3446 | spin_lock_irqsave(&domain->lock, flags); | |
3447 | ret = __set_gcr3(domain, pasid, cr3); | |
3448 | spin_unlock_irqrestore(&domain->lock, flags); | |
3449 | ||
3450 | return ret; | |
3451 | } | |
3452 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3453 | ||
3454 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3455 | { | |
3f4b87b9 | 3456 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3457 | unsigned long flags; |
3458 | int ret; | |
3459 | ||
3460 | spin_lock_irqsave(&domain->lock, flags); | |
3461 | ret = __clear_gcr3(domain, pasid); | |
3462 | spin_unlock_irqrestore(&domain->lock, flags); | |
3463 | ||
3464 | return ret; | |
3465 | } | |
3466 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3467 | |
3468 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3469 | int status, int tag) | |
3470 | { | |
3471 | struct iommu_dev_data *dev_data; | |
3472 | struct amd_iommu *iommu; | |
3473 | struct iommu_cmd cmd; | |
3474 | ||
399be2f5 JR |
3475 | INC_STATS_COUNTER(complete_ppr); |
3476 | ||
c99afa25 JR |
3477 | dev_data = get_dev_data(&pdev->dev); |
3478 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3479 | ||
3480 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3481 | tag, dev_data->pri_tlp); | |
3482 | ||
3483 | return iommu_queue_command(iommu, &cmd); | |
3484 | } | |
3485 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3486 | |
3487 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3488 | { | |
3f4b87b9 | 3489 | struct protection_domain *pdomain; |
f3572db8 | 3490 | |
3f4b87b9 JR |
3491 | pdomain = get_domain(&pdev->dev); |
3492 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3493 | return NULL; |
3494 | ||
3495 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3496 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3497 | return NULL; |
3498 | ||
3f4b87b9 | 3499 | return &pdomain->domain; |
f3572db8 JR |
3500 | } |
3501 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3502 | |
3503 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3504 | { | |
3505 | struct iommu_dev_data *dev_data; | |
3506 | ||
3507 | if (!amd_iommu_v2_supported()) | |
3508 | return; | |
3509 | ||
3510 | dev_data = get_dev_data(&pdev->dev); | |
3511 | dev_data->errata |= (1 << erratum); | |
3512 | } | |
3513 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3514 | |
3515 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3516 | struct amd_iommu_device_info *info) | |
3517 | { | |
3518 | int max_pasids; | |
3519 | int pos; | |
3520 | ||
3521 | if (pdev == NULL || info == NULL) | |
3522 | return -EINVAL; | |
3523 | ||
3524 | if (!amd_iommu_v2_supported()) | |
3525 | return -EINVAL; | |
3526 | ||
3527 | memset(info, 0, sizeof(*info)); | |
3528 | ||
3529 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3530 | if (pos) | |
3531 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3532 | ||
3533 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3534 | if (pos) | |
3535 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3536 | ||
3537 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3538 | if (pos) { | |
3539 | int features; | |
3540 | ||
3541 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3542 | max_pasids = min(max_pasids, (1 << 20)); | |
3543 | ||
3544 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3545 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3546 | ||
3547 | features = pci_pasid_features(pdev); | |
3548 | if (features & PCI_PASID_CAP_EXEC) | |
3549 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3550 | if (features & PCI_PASID_CAP_PRIV) | |
3551 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3552 | } | |
3553 | ||
3554 | return 0; | |
3555 | } | |
3556 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3557 | |
3558 | #ifdef CONFIG_IRQ_REMAP | |
3559 | ||
3560 | /***************************************************************************** | |
3561 | * | |
3562 | * Interrupt Remapping Implementation | |
3563 | * | |
3564 | *****************************************************************************/ | |
3565 | ||
3566 | union irte { | |
3567 | u32 val; | |
3568 | struct { | |
3569 | u32 valid : 1, | |
3570 | no_fault : 1, | |
3571 | int_type : 3, | |
3572 | rq_eoi : 1, | |
3573 | dm : 1, | |
3574 | rsvd_1 : 1, | |
3575 | destination : 8, | |
3576 | vector : 8, | |
3577 | rsvd_2 : 8; | |
3578 | } fields; | |
3579 | }; | |
3580 | ||
9c724966 JL |
3581 | struct irq_2_irte { |
3582 | u16 devid; /* Device ID for IRTE table */ | |
3583 | u16 index; /* Index into IRTE table*/ | |
3584 | }; | |
3585 | ||
7c71d306 JL |
3586 | struct amd_ir_data { |
3587 | struct irq_2_irte irq_2_irte; | |
3588 | union irte irte_entry; | |
3589 | union { | |
3590 | struct msi_msg msi_entry; | |
3591 | }; | |
3592 | }; | |
3593 | ||
3594 | static struct irq_chip amd_ir_chip; | |
3595 | ||
2b324506 JR |
3596 | #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6) |
3597 | #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) | |
3598 | #define DTE_IRQ_TABLE_LEN (8ULL << 1) | |
3599 | #define DTE_IRQ_REMAP_ENABLE 1ULL | |
3600 | ||
3601 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) | |
3602 | { | |
3603 | u64 dte; | |
3604 | ||
3605 | dte = amd_iommu_dev_table[devid].data[2]; | |
3606 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
3607 | dte |= virt_to_phys(table->table); | |
3608 | dte |= DTE_IRQ_REMAP_INTCTL; | |
3609 | dte |= DTE_IRQ_TABLE_LEN; | |
3610 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3611 | ||
3612 | amd_iommu_dev_table[devid].data[2] = dte; | |
3613 | } | |
3614 | ||
3615 | #define IRTE_ALLOCATED (~1U) | |
3616 | ||
3617 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) | |
3618 | { | |
3619 | struct irq_remap_table *table = NULL; | |
3620 | struct amd_iommu *iommu; | |
3621 | unsigned long flags; | |
3622 | u16 alias; | |
3623 | ||
3624 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3625 | ||
3626 | iommu = amd_iommu_rlookup_table[devid]; | |
3627 | if (!iommu) | |
3628 | goto out_unlock; | |
3629 | ||
3630 | table = irq_lookup_table[devid]; | |
3631 | if (table) | |
3632 | goto out; | |
3633 | ||
3634 | alias = amd_iommu_alias_table[devid]; | |
3635 | table = irq_lookup_table[alias]; | |
3636 | if (table) { | |
3637 | irq_lookup_table[devid] = table; | |
3638 | set_dte_irq_entry(devid, table); | |
3639 | iommu_flush_dte(iommu, devid); | |
3640 | goto out; | |
3641 | } | |
3642 | ||
3643 | /* Nothing there yet, allocate new irq remapping table */ | |
3644 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3645 | if (!table) | |
3646 | goto out; | |
3647 | ||
197887f0 JR |
3648 | /* Initialize table spin-lock */ |
3649 | spin_lock_init(&table->lock); | |
3650 | ||
2b324506 JR |
3651 | if (ioapic) |
3652 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3653 | table->min_index = 32; | |
3654 | ||
3655 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3656 | if (!table->table) { | |
3657 | kfree(table); | |
821f0f68 | 3658 | table = NULL; |
2b324506 JR |
3659 | goto out; |
3660 | } | |
3661 | ||
3662 | memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3663 | ||
3664 | if (ioapic) { | |
3665 | int i; | |
3666 | ||
3667 | for (i = 0; i < 32; ++i) | |
3668 | table->table[i] = IRTE_ALLOCATED; | |
3669 | } | |
3670 | ||
3671 | irq_lookup_table[devid] = table; | |
3672 | set_dte_irq_entry(devid, table); | |
3673 | iommu_flush_dte(iommu, devid); | |
3674 | if (devid != alias) { | |
3675 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3676 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3677 | iommu_flush_dte(iommu, alias); |
3678 | } | |
3679 | ||
3680 | out: | |
3681 | iommu_completion_wait(iommu); | |
3682 | ||
3683 | out_unlock: | |
3684 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3685 | ||
3686 | return table; | |
3687 | } | |
3688 | ||
3c3d4f90 | 3689 | static int alloc_irq_index(u16 devid, int count) |
2b324506 JR |
3690 | { |
3691 | struct irq_remap_table *table; | |
3692 | unsigned long flags; | |
3693 | int index, c; | |
3694 | ||
3695 | table = get_irq_table(devid, false); | |
3696 | if (!table) | |
3697 | return -ENODEV; | |
3698 | ||
3699 | spin_lock_irqsave(&table->lock, flags); | |
3700 | ||
3701 | /* Scan table for free entries */ | |
3702 | for (c = 0, index = table->min_index; | |
3703 | index < MAX_IRQS_PER_TABLE; | |
3704 | ++index) { | |
3705 | if (table->table[index] == 0) | |
3706 | c += 1; | |
3707 | else | |
3708 | c = 0; | |
3709 | ||
3710 | if (c == count) { | |
2b324506 JR |
3711 | for (; c != 0; --c) |
3712 | table->table[index - c + 1] = IRTE_ALLOCATED; | |
3713 | ||
3714 | index -= count - 1; | |
2b324506 JR |
3715 | goto out; |
3716 | } | |
3717 | } | |
3718 | ||
3719 | index = -ENOSPC; | |
3720 | ||
3721 | out: | |
3722 | spin_unlock_irqrestore(&table->lock, flags); | |
3723 | ||
3724 | return index; | |
3725 | } | |
3726 | ||
2b324506 JR |
3727 | static int modify_irte(u16 devid, int index, union irte irte) |
3728 | { | |
3729 | struct irq_remap_table *table; | |
3730 | struct amd_iommu *iommu; | |
3731 | unsigned long flags; | |
3732 | ||
3733 | iommu = amd_iommu_rlookup_table[devid]; | |
3734 | if (iommu == NULL) | |
3735 | return -EINVAL; | |
3736 | ||
3737 | table = get_irq_table(devid, false); | |
3738 | if (!table) | |
3739 | return -ENOMEM; | |
3740 | ||
3741 | spin_lock_irqsave(&table->lock, flags); | |
3742 | table->table[index] = irte.val; | |
3743 | spin_unlock_irqrestore(&table->lock, flags); | |
3744 | ||
3745 | iommu_flush_irt(iommu, devid); | |
3746 | iommu_completion_wait(iommu); | |
3747 | ||
3748 | return 0; | |
3749 | } | |
3750 | ||
3751 | static void free_irte(u16 devid, int index) | |
3752 | { | |
3753 | struct irq_remap_table *table; | |
3754 | struct amd_iommu *iommu; | |
3755 | unsigned long flags; | |
3756 | ||
3757 | iommu = amd_iommu_rlookup_table[devid]; | |
3758 | if (iommu == NULL) | |
3759 | return; | |
3760 | ||
3761 | table = get_irq_table(devid, false); | |
3762 | if (!table) | |
3763 | return; | |
3764 | ||
3765 | spin_lock_irqsave(&table->lock, flags); | |
3766 | table->table[index] = 0; | |
3767 | spin_unlock_irqrestore(&table->lock, flags); | |
3768 | ||
3769 | iommu_flush_irt(iommu, devid); | |
3770 | iommu_completion_wait(iommu); | |
3771 | } | |
3772 | ||
7c71d306 | 3773 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3774 | { |
7c71d306 | 3775 | int devid = -1; |
5527de74 | 3776 | |
7c71d306 JL |
3777 | switch (info->type) { |
3778 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3779 | devid = get_ioapic_devid(info->ioapic_id); | |
3780 | break; | |
3781 | case X86_IRQ_ALLOC_TYPE_HPET: | |
3782 | devid = get_hpet_devid(info->hpet_id); | |
3783 | break; | |
3784 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3785 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3786 | devid = get_device_id(&info->msi_dev->dev); | |
3787 | break; | |
3788 | default: | |
3789 | BUG_ON(1); | |
3790 | break; | |
3791 | } | |
5527de74 | 3792 | |
7c71d306 JL |
3793 | return devid; |
3794 | } | |
5527de74 | 3795 | |
7c71d306 JL |
3796 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
3797 | { | |
3798 | struct amd_iommu *iommu; | |
3799 | int devid; | |
5527de74 | 3800 | |
7c71d306 JL |
3801 | if (!info) |
3802 | return NULL; | |
5527de74 | 3803 | |
7c71d306 JL |
3804 | devid = get_devid(info); |
3805 | if (devid >= 0) { | |
3806 | iommu = amd_iommu_rlookup_table[devid]; | |
3807 | if (iommu) | |
3808 | return iommu->ir_domain; | |
3809 | } | |
5527de74 | 3810 | |
7c71d306 | 3811 | return NULL; |
5527de74 JR |
3812 | } |
3813 | ||
7c71d306 | 3814 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 3815 | { |
7c71d306 JL |
3816 | struct amd_iommu *iommu; |
3817 | int devid; | |
5527de74 | 3818 | |
7c71d306 JL |
3819 | if (!info) |
3820 | return NULL; | |
5527de74 | 3821 | |
7c71d306 JL |
3822 | switch (info->type) { |
3823 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3824 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3825 | devid = get_device_id(&info->msi_dev->dev); | |
3826 | if (devid >= 0) { | |
3827 | iommu = amd_iommu_rlookup_table[devid]; | |
3828 | if (iommu) | |
3829 | return iommu->msi_domain; | |
3830 | } | |
3831 | break; | |
3832 | default: | |
3833 | break; | |
3834 | } | |
5527de74 | 3835 | |
7c71d306 JL |
3836 | return NULL; |
3837 | } | |
5527de74 | 3838 | |
6b474b82 | 3839 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
3840 | .prepare = amd_iommu_prepare, |
3841 | .enable = amd_iommu_enable, | |
3842 | .disable = amd_iommu_disable, | |
3843 | .reenable = amd_iommu_reenable, | |
3844 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
3845 | .get_ir_irq_domain = get_ir_irq_domain, |
3846 | .get_irq_domain = get_irq_domain, | |
3847 | }; | |
5527de74 | 3848 | |
7c71d306 JL |
3849 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
3850 | struct irq_cfg *irq_cfg, | |
3851 | struct irq_alloc_info *info, | |
3852 | int devid, int index, int sub_handle) | |
3853 | { | |
3854 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
3855 | struct msi_msg *msg = &data->msi_entry; | |
3856 | union irte *irte = &data->irte_entry; | |
3857 | struct IO_APIC_route_entry *entry; | |
5527de74 | 3858 | |
7c71d306 JL |
3859 | data->irq_2_irte.devid = devid; |
3860 | data->irq_2_irte.index = index + sub_handle; | |
5527de74 | 3861 | |
7c71d306 JL |
3862 | /* Setup IRTE for IOMMU */ |
3863 | irte->val = 0; | |
3864 | irte->fields.vector = irq_cfg->vector; | |
3865 | irte->fields.int_type = apic->irq_delivery_mode; | |
3866 | irte->fields.destination = irq_cfg->dest_apicid; | |
3867 | irte->fields.dm = apic->irq_dest_mode; | |
3868 | irte->fields.valid = 1; | |
3869 | ||
3870 | switch (info->type) { | |
3871 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
3872 | /* Setup IOAPIC entry */ | |
3873 | entry = info->ioapic_entry; | |
3874 | info->ioapic_entry = NULL; | |
3875 | memset(entry, 0, sizeof(*entry)); | |
3876 | entry->vector = index; | |
3877 | entry->mask = 0; | |
3878 | entry->trigger = info->ioapic_trigger; | |
3879 | entry->polarity = info->ioapic_polarity; | |
3880 | /* Mask level triggered irqs. */ | |
3881 | if (info->ioapic_trigger) | |
3882 | entry->mask = 1; | |
3883 | break; | |
5527de74 | 3884 | |
7c71d306 JL |
3885 | case X86_IRQ_ALLOC_TYPE_HPET: |
3886 | case X86_IRQ_ALLOC_TYPE_MSI: | |
3887 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
3888 | msg->address_hi = MSI_ADDR_BASE_HI; | |
3889 | msg->address_lo = MSI_ADDR_BASE_LO; | |
3890 | msg->data = irte_info->index; | |
3891 | break; | |
5527de74 | 3892 | |
7c71d306 JL |
3893 | default: |
3894 | BUG_ON(1); | |
3895 | break; | |
3896 | } | |
5527de74 JR |
3897 | } |
3898 | ||
7c71d306 JL |
3899 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
3900 | unsigned int nr_irqs, void *arg) | |
5527de74 | 3901 | { |
7c71d306 JL |
3902 | struct irq_alloc_info *info = arg; |
3903 | struct irq_data *irq_data; | |
3904 | struct amd_ir_data *data; | |
5527de74 | 3905 | struct irq_cfg *cfg; |
7c71d306 JL |
3906 | int i, ret, devid; |
3907 | int index = -1; | |
5527de74 | 3908 | |
7c71d306 JL |
3909 | if (!info) |
3910 | return -EINVAL; | |
3911 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
3912 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
3913 | return -EINVAL; |
3914 | ||
7c71d306 JL |
3915 | /* |
3916 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
3917 | * to support multiple MSI interrupts. | |
3918 | */ | |
3919 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
3920 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 3921 | |
7c71d306 JL |
3922 | devid = get_devid(info); |
3923 | if (devid < 0) | |
3924 | return -EINVAL; | |
5527de74 | 3925 | |
7c71d306 JL |
3926 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
3927 | if (ret < 0) | |
3928 | return ret; | |
0b4d48cb | 3929 | |
7c71d306 JL |
3930 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
3931 | if (get_irq_table(devid, true)) | |
3932 | index = info->ioapic_pin; | |
3933 | else | |
3934 | ret = -ENOMEM; | |
3935 | } else { | |
3c3d4f90 | 3936 | index = alloc_irq_index(devid, nr_irqs); |
7c71d306 JL |
3937 | } |
3938 | if (index < 0) { | |
3939 | pr_warn("Failed to allocate IRTE\n"); | |
7c71d306 JL |
3940 | goto out_free_parent; |
3941 | } | |
0b4d48cb | 3942 | |
7c71d306 JL |
3943 | for (i = 0; i < nr_irqs; i++) { |
3944 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3945 | cfg = irqd_cfg(irq_data); | |
3946 | if (!irq_data || !cfg) { | |
3947 | ret = -EINVAL; | |
3948 | goto out_free_data; | |
3949 | } | |
0b4d48cb | 3950 | |
a130e69f JR |
3951 | ret = -ENOMEM; |
3952 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
3953 | if (!data) | |
3954 | goto out_free_data; | |
3955 | ||
7c71d306 JL |
3956 | irq_data->hwirq = (devid << 16) + i; |
3957 | irq_data->chip_data = data; | |
3958 | irq_data->chip = &amd_ir_chip; | |
3959 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
3960 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
3961 | } | |
a130e69f | 3962 | |
7c71d306 | 3963 | return 0; |
0b4d48cb | 3964 | |
7c71d306 JL |
3965 | out_free_data: |
3966 | for (i--; i >= 0; i--) { | |
3967 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3968 | if (irq_data) | |
3969 | kfree(irq_data->chip_data); | |
3970 | } | |
3971 | for (i = 0; i < nr_irqs; i++) | |
3972 | free_irte(devid, index + i); | |
3973 | out_free_parent: | |
3974 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3975 | return ret; | |
0b4d48cb JR |
3976 | } |
3977 | ||
7c71d306 JL |
3978 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
3979 | unsigned int nr_irqs) | |
0b4d48cb | 3980 | { |
7c71d306 JL |
3981 | struct irq_2_irte *irte_info; |
3982 | struct irq_data *irq_data; | |
3983 | struct amd_ir_data *data; | |
3984 | int i; | |
0b4d48cb | 3985 | |
7c71d306 JL |
3986 | for (i = 0; i < nr_irqs; i++) { |
3987 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
3988 | if (irq_data && irq_data->chip_data) { | |
3989 | data = irq_data->chip_data; | |
3990 | irte_info = &data->irq_2_irte; | |
3991 | free_irte(irte_info->devid, irte_info->index); | |
3992 | kfree(data); | |
3993 | } | |
3994 | } | |
3995 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
3996 | } | |
0b4d48cb | 3997 | |
7c71d306 JL |
3998 | static void irq_remapping_activate(struct irq_domain *domain, |
3999 | struct irq_data *irq_data) | |
4000 | { | |
4001 | struct amd_ir_data *data = irq_data->chip_data; | |
4002 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
0b4d48cb | 4003 | |
7c71d306 | 4004 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); |
0b4d48cb JR |
4005 | } |
4006 | ||
7c71d306 JL |
4007 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4008 | struct irq_data *irq_data) | |
0b4d48cb | 4009 | { |
7c71d306 JL |
4010 | struct amd_ir_data *data = irq_data->chip_data; |
4011 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4012 | union irte entry; | |
0b4d48cb | 4013 | |
7c71d306 JL |
4014 | entry.val = 0; |
4015 | modify_irte(irte_info->devid, irte_info->index, data->irte_entry); | |
4016 | } | |
0b4d48cb | 4017 | |
7c71d306 JL |
4018 | static struct irq_domain_ops amd_ir_domain_ops = { |
4019 | .alloc = irq_remapping_alloc, | |
4020 | .free = irq_remapping_free, | |
4021 | .activate = irq_remapping_activate, | |
4022 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4023 | }; |
0b4d48cb | 4024 | |
7c71d306 JL |
4025 | static int amd_ir_set_affinity(struct irq_data *data, |
4026 | const struct cpumask *mask, bool force) | |
4027 | { | |
4028 | struct amd_ir_data *ir_data = data->chip_data; | |
4029 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4030 | struct irq_cfg *cfg = irqd_cfg(data); | |
4031 | struct irq_data *parent = data->parent_data; | |
4032 | int ret; | |
0b4d48cb | 4033 | |
7c71d306 JL |
4034 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4035 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4036 | return ret; | |
0b4d48cb | 4037 | |
7c71d306 JL |
4038 | /* |
4039 | * Atomically updates the IRTE with the new destination, vector | |
4040 | * and flushes the interrupt entry cache. | |
4041 | */ | |
4042 | ir_data->irte_entry.fields.vector = cfg->vector; | |
4043 | ir_data->irte_entry.fields.destination = cfg->dest_apicid; | |
4044 | modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry); | |
0b4d48cb | 4045 | |
7c71d306 JL |
4046 | /* |
4047 | * After this point, all the interrupts will start arriving | |
4048 | * at the new destination. So, time to cleanup the previous | |
4049 | * vector allocation. | |
4050 | */ | |
c6c2002b | 4051 | send_cleanup_vector(cfg); |
7c71d306 JL |
4052 | |
4053 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4054 | } |
4055 | ||
7c71d306 | 4056 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4057 | { |
7c71d306 | 4058 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4059 | |
7c71d306 JL |
4060 | *msg = ir_data->msi_entry; |
4061 | } | |
d976195c | 4062 | |
7c71d306 JL |
4063 | static struct irq_chip amd_ir_chip = { |
4064 | .irq_ack = ir_ack_apic_edge, | |
4065 | .irq_set_affinity = amd_ir_set_affinity, | |
4066 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
4067 | }; | |
d976195c | 4068 | |
7c71d306 JL |
4069 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4070 | { | |
4071 | iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu); | |
4072 | if (!iommu->ir_domain) | |
4073 | return -ENOMEM; | |
d976195c | 4074 | |
7c71d306 JL |
4075 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
4076 | iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
d976195c JR |
4077 | |
4078 | return 0; | |
4079 | } | |
2b324506 | 4080 | #endif |