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Commit | Line | Data |
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b6c02715 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
b6c02715 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
72e1dcc4 | 20 | #include <linux/ratelimit.h> |
b6c02715 | 21 | #include <linux/pci.h> |
2bf9a0a1 | 22 | #include <linux/acpi.h> |
9a4d3bf5 | 23 | #include <linux/amba/bus.h> |
0076cd3d | 24 | #include <linux/platform_device.h> |
cb41ed85 | 25 | #include <linux/pci-ats.h> |
a66022c4 | 26 | #include <linux/bitmap.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
7f26508b | 28 | #include <linux/debugfs.h> |
b6c02715 | 29 | #include <linux/scatterlist.h> |
51491367 | 30 | #include <linux/dma-mapping.h> |
b6c02715 | 31 | #include <linux/iommu-helper.h> |
c156e347 | 32 | #include <linux/iommu.h> |
815b33fd | 33 | #include <linux/delay.h> |
403f81d8 | 34 | #include <linux/amd-iommu.h> |
72e1dcc4 JR |
35 | #include <linux/notifier.h> |
36 | #include <linux/export.h> | |
2b324506 JR |
37 | #include <linux/irq.h> |
38 | #include <linux/msi.h> | |
3b839a57 | 39 | #include <linux/dma-contiguous.h> |
7c71d306 | 40 | #include <linux/irqdomain.h> |
5f6bed50 | 41 | #include <linux/percpu.h> |
307d5851 | 42 | #include <linux/iova.h> |
2b324506 JR |
43 | #include <asm/irq_remapping.h> |
44 | #include <asm/io_apic.h> | |
45 | #include <asm/apic.h> | |
46 | #include <asm/hw_irq.h> | |
17f5b569 | 47 | #include <asm/msidef.h> |
b6c02715 | 48 | #include <asm/proto.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
1d9b16d1 | 50 | #include <asm/gart.h> |
27c2127a | 51 | #include <asm/dma.h> |
403f81d8 JR |
52 | |
53 | #include "amd_iommu_proto.h" | |
54 | #include "amd_iommu_types.h" | |
6b474b82 | 55 | #include "irq_remapping.h" |
b6c02715 | 56 | |
a869572c CH |
57 | #define AMD_IOMMU_MAPPING_ERROR 0 |
58 | ||
b6c02715 JR |
59 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) |
60 | ||
815b33fd | 61 | #define LOOP_TIMEOUT 100000 |
136f78a1 | 62 | |
307d5851 JR |
63 | /* IO virtual address start page frame number */ |
64 | #define IOVA_START_PFN (1) | |
65 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) | |
307d5851 | 66 | |
81cd07b9 JR |
67 | /* Reserved IOVA ranges */ |
68 | #define MSI_RANGE_START (0xfee00000) | |
69 | #define MSI_RANGE_END (0xfeefffff) | |
70 | #define HT_RANGE_START (0xfd00000000ULL) | |
71 | #define HT_RANGE_END (0xffffffffffULL) | |
72 | ||
aa3de9c0 OBC |
73 | /* |
74 | * This bitmap is used to advertise the page sizes our hardware support | |
75 | * to the IOMMU core, which will then use this information to split | |
76 | * physically contiguous memory regions it is mapping into page sizes | |
77 | * that we support. | |
78 | * | |
954e3dd8 | 79 | * 512GB Pages are not supported due to a hardware bug |
aa3de9c0 | 80 | */ |
954e3dd8 | 81 | #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38)) |
aa3de9c0 | 82 | |
b6c02715 JR |
83 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
84 | ||
8fa5f802 JR |
85 | /* List of all available dev_data structures */ |
86 | static LIST_HEAD(dev_data_list); | |
87 | static DEFINE_SPINLOCK(dev_data_list_lock); | |
88 | ||
6efed63b JR |
89 | LIST_HEAD(ioapic_map); |
90 | LIST_HEAD(hpet_map); | |
2a0cb4e2 | 91 | LIST_HEAD(acpihid_map); |
6efed63b | 92 | |
0feae533 JR |
93 | /* |
94 | * Domain for untranslated devices - only allocated | |
95 | * if iommu=pt passed on kernel cmd line. | |
96 | */ | |
b0119e87 | 97 | const struct iommu_ops amd_iommu_ops; |
26961efe | 98 | |
72e1dcc4 | 99 | static ATOMIC_NOTIFIER_HEAD(ppr_notifier); |
52815b75 | 100 | int amd_iommu_max_glx_val = -1; |
72e1dcc4 | 101 | |
5299709d | 102 | static const struct dma_map_ops amd_iommu_dma_ops; |
ac1534a5 | 103 | |
431b2a20 JR |
104 | /* |
105 | * general struct to manage commands send to an IOMMU | |
106 | */ | |
d6449536 | 107 | struct iommu_cmd { |
b6c02715 JR |
108 | u32 data[4]; |
109 | }; | |
110 | ||
05152a04 JR |
111 | struct kmem_cache *amd_iommu_irq_cache; |
112 | ||
04bfdd84 | 113 | static void update_domain(struct protection_domain *domain); |
7a5a566e | 114 | static int protection_domain_init(struct protection_domain *domain); |
b6809ee5 | 115 | static void detach_device(struct device *dev); |
9003d618 | 116 | static void iova_domain_flush_tlb(struct iova_domain *iovad); |
d4241a27 | 117 | |
007b74ba JR |
118 | /* |
119 | * Data container for a dma_ops specific protection domain | |
120 | */ | |
121 | struct dma_ops_domain { | |
122 | /* generic protection domain information */ | |
123 | struct protection_domain domain; | |
124 | ||
307d5851 JR |
125 | /* IOVA RB-Tree */ |
126 | struct iova_domain iovad; | |
007b74ba JR |
127 | }; |
128 | ||
81cd07b9 JR |
129 | static struct iova_domain reserved_iova_ranges; |
130 | static struct lock_class_key reserved_rbtree_key; | |
131 | ||
15898bbc JR |
132 | /**************************************************************************** |
133 | * | |
134 | * Helper functions | |
135 | * | |
136 | ****************************************************************************/ | |
137 | ||
2bf9a0a1 WZ |
138 | static inline int match_hid_uid(struct device *dev, |
139 | struct acpihid_map_entry *entry) | |
3f4b87b9 | 140 | { |
fcc15f1f | 141 | struct acpi_device *adev = ACPI_COMPANION(dev); |
2bf9a0a1 WZ |
142 | const char *hid, *uid; |
143 | ||
fcc15f1f AM |
144 | if (!adev) |
145 | return -ENODEV; | |
146 | ||
147 | hid = acpi_device_hid(adev); | |
148 | uid = acpi_device_uid(adev); | |
2bf9a0a1 WZ |
149 | |
150 | if (!hid || !(*hid)) | |
151 | return -ENODEV; | |
152 | ||
153 | if (!uid || !(*uid)) | |
154 | return strcmp(hid, entry->hid); | |
155 | ||
156 | if (!(*entry->uid)) | |
157 | return strcmp(hid, entry->hid); | |
158 | ||
159 | return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid)); | |
3f4b87b9 JR |
160 | } |
161 | ||
2bf9a0a1 | 162 | static inline u16 get_pci_device_id(struct device *dev) |
e3156048 JR |
163 | { |
164 | struct pci_dev *pdev = to_pci_dev(dev); | |
165 | ||
166 | return PCI_DEVID(pdev->bus->number, pdev->devfn); | |
167 | } | |
168 | ||
2bf9a0a1 WZ |
169 | static inline int get_acpihid_device_id(struct device *dev, |
170 | struct acpihid_map_entry **entry) | |
171 | { | |
172 | struct acpihid_map_entry *p; | |
173 | ||
174 | list_for_each_entry(p, &acpihid_map, list) { | |
175 | if (!match_hid_uid(dev, p)) { | |
176 | if (entry) | |
177 | *entry = p; | |
178 | return p->devid; | |
179 | } | |
180 | } | |
181 | return -EINVAL; | |
182 | } | |
183 | ||
184 | static inline int get_device_id(struct device *dev) | |
185 | { | |
186 | int devid; | |
187 | ||
188 | if (dev_is_pci(dev)) | |
189 | devid = get_pci_device_id(dev); | |
190 | else | |
191 | devid = get_acpihid_device_id(dev, NULL); | |
192 | ||
193 | return devid; | |
194 | } | |
195 | ||
3f4b87b9 JR |
196 | static struct protection_domain *to_pdomain(struct iommu_domain *dom) |
197 | { | |
198 | return container_of(dom, struct protection_domain, domain); | |
199 | } | |
200 | ||
b3311b06 JR |
201 | static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain) |
202 | { | |
203 | BUG_ON(domain->flags != PD_DMA_OPS_MASK); | |
204 | return container_of(domain, struct dma_ops_domain, domain); | |
205 | } | |
206 | ||
f62dda66 | 207 | static struct iommu_dev_data *alloc_dev_data(u16 devid) |
8fa5f802 JR |
208 | { |
209 | struct iommu_dev_data *dev_data; | |
210 | unsigned long flags; | |
211 | ||
212 | dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL); | |
213 | if (!dev_data) | |
214 | return NULL; | |
215 | ||
f62dda66 | 216 | dev_data->devid = devid; |
8fa5f802 JR |
217 | |
218 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
219 | list_add_tail(&dev_data->dev_data_list, &dev_data_list); | |
220 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
221 | ||
30bf2df6 JR |
222 | ratelimit_default_init(&dev_data->rs); |
223 | ||
8fa5f802 JR |
224 | return dev_data; |
225 | } | |
226 | ||
3b03bb74 JR |
227 | static struct iommu_dev_data *search_dev_data(u16 devid) |
228 | { | |
229 | struct iommu_dev_data *dev_data; | |
230 | unsigned long flags; | |
231 | ||
232 | spin_lock_irqsave(&dev_data_list_lock, flags); | |
233 | list_for_each_entry(dev_data, &dev_data_list, dev_data_list) { | |
234 | if (dev_data->devid == devid) | |
235 | goto out_unlock; | |
236 | } | |
237 | ||
238 | dev_data = NULL; | |
239 | ||
240 | out_unlock: | |
241 | spin_unlock_irqrestore(&dev_data_list_lock, flags); | |
242 | ||
243 | return dev_data; | |
244 | } | |
245 | ||
e3156048 JR |
246 | static int __last_alias(struct pci_dev *pdev, u16 alias, void *data) |
247 | { | |
248 | *(u16 *)data = alias; | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static u16 get_alias(struct device *dev) | |
253 | { | |
254 | struct pci_dev *pdev = to_pci_dev(dev); | |
255 | u16 devid, ivrs_alias, pci_alias; | |
256 | ||
6c0b43df | 257 | /* The callers make sure that get_device_id() does not fail here */ |
e3156048 | 258 | devid = get_device_id(dev); |
eeb3805c AN |
259 | |
260 | /* For ACPI HID devices, we simply return the devid as such */ | |
261 | if (!dev_is_pci(dev)) | |
262 | return devid; | |
263 | ||
e3156048 | 264 | ivrs_alias = amd_iommu_alias_table[devid]; |
eeb3805c | 265 | |
e3156048 JR |
266 | pci_for_each_dma_alias(pdev, __last_alias, &pci_alias); |
267 | ||
268 | if (ivrs_alias == pci_alias) | |
269 | return ivrs_alias; | |
270 | ||
271 | /* | |
272 | * DMA alias showdown | |
273 | * | |
274 | * The IVRS is fairly reliable in telling us about aliases, but it | |
275 | * can't know about every screwy device. If we don't have an IVRS | |
276 | * reported alias, use the PCI reported alias. In that case we may | |
277 | * still need to initialize the rlookup and dev_table entries if the | |
278 | * alias is to a non-existent device. | |
279 | */ | |
280 | if (ivrs_alias == devid) { | |
281 | if (!amd_iommu_rlookup_table[pci_alias]) { | |
282 | amd_iommu_rlookup_table[pci_alias] = | |
283 | amd_iommu_rlookup_table[devid]; | |
284 | memcpy(amd_iommu_dev_table[pci_alias].data, | |
285 | amd_iommu_dev_table[devid].data, | |
286 | sizeof(amd_iommu_dev_table[pci_alias].data)); | |
287 | } | |
288 | ||
289 | return pci_alias; | |
290 | } | |
291 | ||
292 | pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d " | |
293 | "for device %s[%04x:%04x], kernel reported alias " | |
294 | "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias), | |
295 | PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device, | |
296 | PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias), | |
297 | PCI_FUNC(pci_alias)); | |
298 | ||
299 | /* | |
300 | * If we don't have a PCI DMA alias and the IVRS alias is on the same | |
301 | * bus, then the IVRS table may know about a quirk that we don't. | |
302 | */ | |
303 | if (pci_alias == devid && | |
304 | PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) { | |
7afd16f8 | 305 | pci_add_dma_alias(pdev, ivrs_alias & 0xff); |
e3156048 JR |
306 | pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n", |
307 | PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias), | |
308 | dev_name(dev)); | |
309 | } | |
310 | ||
311 | return ivrs_alias; | |
312 | } | |
313 | ||
3b03bb74 JR |
314 | static struct iommu_dev_data *find_dev_data(u16 devid) |
315 | { | |
316 | struct iommu_dev_data *dev_data; | |
df3f7a6e | 317 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3b03bb74 JR |
318 | |
319 | dev_data = search_dev_data(devid); | |
320 | ||
df3f7a6e | 321 | if (dev_data == NULL) { |
3b03bb74 | 322 | dev_data = alloc_dev_data(devid); |
a5761383 SAS |
323 | if (!dev_data) |
324 | return NULL; | |
3b03bb74 | 325 | |
df3f7a6e BH |
326 | if (translation_pre_enabled(iommu)) |
327 | dev_data->defer_attach = true; | |
328 | } | |
329 | ||
3b03bb74 JR |
330 | return dev_data; |
331 | } | |
332 | ||
daae2d25 | 333 | struct iommu_dev_data *get_dev_data(struct device *dev) |
657cbb6b JR |
334 | { |
335 | return dev->archdata.iommu; | |
336 | } | |
daae2d25 | 337 | EXPORT_SYMBOL(get_dev_data); |
657cbb6b | 338 | |
b097d11a WZ |
339 | /* |
340 | * Find or create an IOMMU group for a acpihid device. | |
341 | */ | |
342 | static struct iommu_group *acpihid_device_group(struct device *dev) | |
657cbb6b | 343 | { |
b097d11a | 344 | struct acpihid_map_entry *p, *entry = NULL; |
2d8e1f03 | 345 | int devid; |
b097d11a WZ |
346 | |
347 | devid = get_acpihid_device_id(dev, &entry); | |
348 | if (devid < 0) | |
349 | return ERR_PTR(devid); | |
350 | ||
351 | list_for_each_entry(p, &acpihid_map, list) { | |
352 | if ((devid == p->devid) && p->group) | |
353 | entry->group = p->group; | |
354 | } | |
355 | ||
356 | if (!entry->group) | |
357 | entry->group = generic_device_group(dev); | |
f2f101f6 RM |
358 | else |
359 | iommu_group_ref_get(entry->group); | |
b097d11a WZ |
360 | |
361 | return entry->group; | |
657cbb6b JR |
362 | } |
363 | ||
5abcdba4 JR |
364 | static bool pci_iommuv2_capable(struct pci_dev *pdev) |
365 | { | |
366 | static const int caps[] = { | |
367 | PCI_EXT_CAP_ID_ATS, | |
46277b75 JR |
368 | PCI_EXT_CAP_ID_PRI, |
369 | PCI_EXT_CAP_ID_PASID, | |
5abcdba4 JR |
370 | }; |
371 | int i, pos; | |
372 | ||
373 | for (i = 0; i < 3; ++i) { | |
374 | pos = pci_find_ext_capability(pdev, caps[i]); | |
375 | if (pos == 0) | |
376 | return false; | |
377 | } | |
378 | ||
379 | return true; | |
380 | } | |
381 | ||
6a113ddc JR |
382 | static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum) |
383 | { | |
384 | struct iommu_dev_data *dev_data; | |
385 | ||
386 | dev_data = get_dev_data(&pdev->dev); | |
387 | ||
388 | return dev_data->errata & (1 << erratum) ? true : false; | |
389 | } | |
390 | ||
98fc5a69 JR |
391 | /* |
392 | * This function checks if the driver got a valid device from the caller to | |
393 | * avoid dereferencing invalid pointers. | |
394 | */ | |
395 | static bool check_device(struct device *dev) | |
396 | { | |
7aba6cb9 | 397 | int devid; |
98fc5a69 JR |
398 | |
399 | if (!dev || !dev->dma_mask) | |
400 | return false; | |
401 | ||
98fc5a69 | 402 | devid = get_device_id(dev); |
9ee35e4c | 403 | if (devid < 0) |
7aba6cb9 | 404 | return false; |
98fc5a69 JR |
405 | |
406 | /* Out of our scope? */ | |
407 | if (devid > amd_iommu_last_bdf) | |
408 | return false; | |
409 | ||
410 | if (amd_iommu_rlookup_table[devid] == NULL) | |
411 | return false; | |
412 | ||
413 | return true; | |
414 | } | |
415 | ||
25b11ce2 | 416 | static void init_iommu_group(struct device *dev) |
2851db21 | 417 | { |
2851db21 | 418 | struct iommu_group *group; |
2851db21 | 419 | |
65d5352f | 420 | group = iommu_group_get_for_dev(dev); |
0bb6e243 JR |
421 | if (IS_ERR(group)) |
422 | return; | |
423 | ||
0bb6e243 | 424 | iommu_group_put(group); |
eb9c9527 AW |
425 | } |
426 | ||
427 | static int iommu_init_device(struct device *dev) | |
428 | { | |
eb9c9527 | 429 | struct iommu_dev_data *dev_data; |
39ab9555 | 430 | struct amd_iommu *iommu; |
7aba6cb9 | 431 | int devid; |
eb9c9527 AW |
432 | |
433 | if (dev->archdata.iommu) | |
434 | return 0; | |
435 | ||
7aba6cb9 | 436 | devid = get_device_id(dev); |
9ee35e4c | 437 | if (devid < 0) |
7aba6cb9 WZ |
438 | return devid; |
439 | ||
39ab9555 JR |
440 | iommu = amd_iommu_rlookup_table[devid]; |
441 | ||
7aba6cb9 | 442 | dev_data = find_dev_data(devid); |
eb9c9527 AW |
443 | if (!dev_data) |
444 | return -ENOMEM; | |
445 | ||
e3156048 JR |
446 | dev_data->alias = get_alias(dev); |
447 | ||
fb146410 YZ |
448 | /* |
449 | * By default we use passthrough mode for IOMMUv2 capable device. | |
450 | * But if amd_iommu=force_isolation is set (e.g. to debug DMA to | |
451 | * invalid address), we ignore the capability for the device so | |
452 | * it'll be forced to go into translation mode. | |
453 | */ | |
454 | if ((iommu_pass_through || !amd_iommu_force_isolation) && | |
455 | dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) { | |
5abcdba4 JR |
456 | struct amd_iommu *iommu; |
457 | ||
2bf9a0a1 | 458 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
5abcdba4 JR |
459 | dev_data->iommu_v2 = iommu->is_iommu_v2; |
460 | } | |
461 | ||
657cbb6b JR |
462 | dev->archdata.iommu = dev_data; |
463 | ||
e3d10af1 | 464 | iommu_device_link(&iommu->iommu, dev); |
066f2e98 | 465 | |
657cbb6b JR |
466 | return 0; |
467 | } | |
468 | ||
26018874 JR |
469 | static void iommu_ignore_device(struct device *dev) |
470 | { | |
7aba6cb9 WZ |
471 | u16 alias; |
472 | int devid; | |
26018874 JR |
473 | |
474 | devid = get_device_id(dev); | |
9ee35e4c | 475 | if (devid < 0) |
7aba6cb9 WZ |
476 | return; |
477 | ||
e3156048 | 478 | alias = get_alias(dev); |
26018874 JR |
479 | |
480 | memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry)); | |
481 | memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry)); | |
482 | ||
483 | amd_iommu_rlookup_table[devid] = NULL; | |
484 | amd_iommu_rlookup_table[alias] = NULL; | |
485 | } | |
486 | ||
657cbb6b JR |
487 | static void iommu_uninit_device(struct device *dev) |
488 | { | |
7aba6cb9 | 489 | struct iommu_dev_data *dev_data; |
39ab9555 JR |
490 | struct amd_iommu *iommu; |
491 | int devid; | |
c1931090 | 492 | |
7aba6cb9 | 493 | devid = get_device_id(dev); |
9ee35e4c | 494 | if (devid < 0) |
7aba6cb9 | 495 | return; |
c1931090 | 496 | |
39ab9555 JR |
497 | iommu = amd_iommu_rlookup_table[devid]; |
498 | ||
7aba6cb9 | 499 | dev_data = search_dev_data(devid); |
c1931090 AW |
500 | if (!dev_data) |
501 | return; | |
502 | ||
b6809ee5 JR |
503 | if (dev_data->domain) |
504 | detach_device(dev); | |
505 | ||
e3d10af1 | 506 | iommu_device_unlink(&iommu->iommu, dev); |
066f2e98 | 507 | |
9dcd6130 AW |
508 | iommu_group_remove_device(dev); |
509 | ||
aafd8ba0 | 510 | /* Remove dma-ops */ |
5657933d | 511 | dev->dma_ops = NULL; |
aafd8ba0 | 512 | |
8fa5f802 | 513 | /* |
c1931090 AW |
514 | * We keep dev_data around for unplugged devices and reuse it when the |
515 | * device is re-plugged - not doing so would introduce a ton of races. | |
8fa5f802 | 516 | */ |
657cbb6b | 517 | } |
b7cc9554 | 518 | |
a80dc3e0 JR |
519 | /**************************************************************************** |
520 | * | |
521 | * Interrupt handling functions | |
522 | * | |
523 | ****************************************************************************/ | |
524 | ||
e3e59876 JR |
525 | static void dump_dte_entry(u16 devid) |
526 | { | |
527 | int i; | |
528 | ||
ee6c2868 JR |
529 | for (i = 0; i < 4; ++i) |
530 | pr_err("AMD-Vi: DTE[%d]: %016llx\n", i, | |
e3e59876 JR |
531 | amd_iommu_dev_table[devid].data[i]); |
532 | } | |
533 | ||
945b4ac4 JR |
534 | static void dump_command(unsigned long phys_addr) |
535 | { | |
2543a786 | 536 | struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr); |
945b4ac4 JR |
537 | int i; |
538 | ||
539 | for (i = 0; i < 4; ++i) | |
540 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
541 | } | |
542 | ||
30bf2df6 JR |
543 | static void amd_iommu_report_page_fault(u16 devid, u16 domain_id, |
544 | u64 address, int flags) | |
545 | { | |
546 | struct iommu_dev_data *dev_data = NULL; | |
547 | struct pci_dev *pdev; | |
548 | ||
549 | pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff); | |
550 | if (pdev) | |
551 | dev_data = get_dev_data(&pdev->dev); | |
552 | ||
553 | if (dev_data && __ratelimit(&dev_data->rs)) { | |
554 | dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
555 | domain_id, address, flags); | |
556 | } else if (printk_ratelimit()) { | |
557 | pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
558 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
559 | domain_id, address, flags); | |
560 | } | |
561 | ||
562 | if (pdev) | |
563 | pci_dev_put(pdev); | |
564 | } | |
565 | ||
a345b23b | 566 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 | 567 | { |
3d06fca8 JR |
568 | int type, devid, domid, flags; |
569 | volatile u32 *event = __evt; | |
570 | int count = 0; | |
571 | u64 address; | |
572 | ||
573 | retry: | |
574 | type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
575 | devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
576 | domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
577 | flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
578 | address = (u64)(((u64)event[3]) << 32) | event[2]; | |
579 | ||
580 | if (type == 0) { | |
581 | /* Did we hit the erratum? */ | |
582 | if (++count == LOOP_TIMEOUT) { | |
583 | pr_err("AMD-Vi: No event written to event log\n"); | |
584 | return; | |
585 | } | |
586 | udelay(1); | |
587 | goto retry; | |
588 | } | |
90008ee4 | 589 | |
30bf2df6 JR |
590 | if (type == EVENT_TYPE_IO_FAULT) { |
591 | amd_iommu_report_page_fault(devid, domid, address, flags); | |
592 | return; | |
593 | } else { | |
594 | printk(KERN_ERR "AMD-Vi: Event logged ["); | |
595 | } | |
90008ee4 JR |
596 | |
597 | switch (type) { | |
598 | case EVENT_TYPE_ILL_DEV: | |
599 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
600 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 601 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 | 602 | address, flags); |
e3e59876 | 603 | dump_dte_entry(devid); |
90008ee4 | 604 | break; |
90008ee4 JR |
605 | case EVENT_TYPE_DEV_TAB_ERR: |
606 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
607 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 608 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
609 | address, flags); |
610 | break; | |
611 | case EVENT_TYPE_PAGE_TAB_ERR: | |
612 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
613 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 614 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
615 | domid, address, flags); |
616 | break; | |
617 | case EVENT_TYPE_ILL_CMD: | |
618 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
945b4ac4 | 619 | dump_command(address); |
90008ee4 JR |
620 | break; |
621 | case EVENT_TYPE_CMD_HARD_ERR: | |
622 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
623 | "flags=0x%04x]\n", address, flags); | |
624 | break; | |
625 | case EVENT_TYPE_IOTLB_INV_TO: | |
626 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
627 | "address=0x%016llx]\n", | |
c5081cd7 | 628 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
629 | address); |
630 | break; | |
631 | case EVENT_TYPE_INV_DEV_REQ: | |
632 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
633 | "address=0x%016llx flags=0x%04x]\n", | |
c5081cd7 | 634 | PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid), |
90008ee4 JR |
635 | address, flags); |
636 | break; | |
637 | default: | |
638 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
639 | } | |
3d06fca8 JR |
640 | |
641 | memset(__evt, 0, 4 * sizeof(u32)); | |
90008ee4 JR |
642 | } |
643 | ||
644 | static void iommu_poll_events(struct amd_iommu *iommu) | |
645 | { | |
646 | u32 head, tail; | |
90008ee4 JR |
647 | |
648 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
649 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
650 | ||
651 | while (head != tail) { | |
a345b23b | 652 | iommu_print_event(iommu, iommu->evt_buf + head); |
deba4bce | 653 | head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE; |
90008ee4 JR |
654 | } |
655 | ||
656 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
90008ee4 JR |
657 | } |
658 | ||
eee53537 | 659 | static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw) |
72e1dcc4 JR |
660 | { |
661 | struct amd_iommu_fault fault; | |
72e1dcc4 | 662 | |
72e1dcc4 JR |
663 | if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) { |
664 | pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n"); | |
665 | return; | |
666 | } | |
667 | ||
668 | fault.address = raw[1]; | |
669 | fault.pasid = PPR_PASID(raw[0]); | |
670 | fault.device_id = PPR_DEVID(raw[0]); | |
671 | fault.tag = PPR_TAG(raw[0]); | |
672 | fault.flags = PPR_FLAGS(raw[0]); | |
673 | ||
72e1dcc4 JR |
674 | atomic_notifier_call_chain(&ppr_notifier, 0, &fault); |
675 | } | |
676 | ||
677 | static void iommu_poll_ppr_log(struct amd_iommu *iommu) | |
678 | { | |
72e1dcc4 JR |
679 | u32 head, tail; |
680 | ||
681 | if (iommu->ppr_log == NULL) | |
682 | return; | |
683 | ||
72e1dcc4 JR |
684 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); |
685 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
686 | ||
687 | while (head != tail) { | |
eee53537 JR |
688 | volatile u64 *raw; |
689 | u64 entry[2]; | |
690 | int i; | |
691 | ||
692 | raw = (u64 *)(iommu->ppr_log + head); | |
693 | ||
694 | /* | |
695 | * Hardware bug: Interrupt may arrive before the entry is | |
696 | * written to memory. If this happens we need to wait for the | |
697 | * entry to arrive. | |
698 | */ | |
699 | for (i = 0; i < LOOP_TIMEOUT; ++i) { | |
700 | if (PPR_REQ_TYPE(raw[0]) != 0) | |
701 | break; | |
702 | udelay(1); | |
703 | } | |
72e1dcc4 | 704 | |
eee53537 JR |
705 | /* Avoid memcpy function-call overhead */ |
706 | entry[0] = raw[0]; | |
707 | entry[1] = raw[1]; | |
72e1dcc4 | 708 | |
eee53537 JR |
709 | /* |
710 | * To detect the hardware bug we need to clear the entry | |
711 | * back to zero. | |
712 | */ | |
713 | raw[0] = raw[1] = 0UL; | |
714 | ||
715 | /* Update head pointer of hardware ring-buffer */ | |
72e1dcc4 JR |
716 | head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE; |
717 | writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
eee53537 | 718 | |
eee53537 JR |
719 | /* Handle PPR entry */ |
720 | iommu_handle_ppr_entry(iommu, entry); | |
721 | ||
eee53537 JR |
722 | /* Refresh ring-buffer information */ |
723 | head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
72e1dcc4 JR |
724 | tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); |
725 | } | |
72e1dcc4 JR |
726 | } |
727 | ||
bd6fcefc SS |
728 | #ifdef CONFIG_IRQ_REMAP |
729 | static int (*iommu_ga_log_notifier)(u32); | |
730 | ||
731 | int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) | |
732 | { | |
733 | iommu_ga_log_notifier = notifier; | |
734 | ||
735 | return 0; | |
736 | } | |
737 | EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier); | |
738 | ||
739 | static void iommu_poll_ga_log(struct amd_iommu *iommu) | |
740 | { | |
741 | u32 head, tail, cnt = 0; | |
742 | ||
743 | if (iommu->ga_log == NULL) | |
744 | return; | |
745 | ||
746 | head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
747 | tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET); | |
748 | ||
749 | while (head != tail) { | |
750 | volatile u64 *raw; | |
751 | u64 log_entry; | |
752 | ||
753 | raw = (u64 *)(iommu->ga_log + head); | |
754 | cnt++; | |
755 | ||
756 | /* Avoid memcpy function-call overhead */ | |
757 | log_entry = *raw; | |
758 | ||
759 | /* Update head pointer of hardware ring-buffer */ | |
760 | head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE; | |
761 | writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); | |
762 | ||
763 | /* Handle GA entry */ | |
764 | switch (GA_REQ_TYPE(log_entry)) { | |
765 | case GA_GUEST_NR: | |
766 | if (!iommu_ga_log_notifier) | |
767 | break; | |
768 | ||
769 | pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n", | |
770 | __func__, GA_DEVID(log_entry), | |
771 | GA_TAG(log_entry)); | |
772 | ||
773 | if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0) | |
774 | pr_err("AMD-Vi: GA log notifier failed.\n"); | |
775 | break; | |
776 | default: | |
777 | break; | |
778 | } | |
779 | } | |
780 | } | |
781 | #endif /* CONFIG_IRQ_REMAP */ | |
782 | ||
783 | #define AMD_IOMMU_INT_MASK \ | |
784 | (MMIO_STATUS_EVT_INT_MASK | \ | |
785 | MMIO_STATUS_PPR_INT_MASK | \ | |
786 | MMIO_STATUS_GALOG_INT_MASK) | |
787 | ||
72fe00f0 | 788 | irqreturn_t amd_iommu_int_thread(int irq, void *data) |
a80dc3e0 | 789 | { |
3f398bc7 SS |
790 | struct amd_iommu *iommu = (struct amd_iommu *) data; |
791 | u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
90008ee4 | 792 | |
bd6fcefc SS |
793 | while (status & AMD_IOMMU_INT_MASK) { |
794 | /* Enable EVT and PPR and GA interrupts again */ | |
795 | writel(AMD_IOMMU_INT_MASK, | |
3f398bc7 | 796 | iommu->mmio_base + MMIO_STATUS_OFFSET); |
90008ee4 | 797 | |
3f398bc7 SS |
798 | if (status & MMIO_STATUS_EVT_INT_MASK) { |
799 | pr_devel("AMD-Vi: Processing IOMMU Event Log\n"); | |
800 | iommu_poll_events(iommu); | |
801 | } | |
90008ee4 | 802 | |
3f398bc7 SS |
803 | if (status & MMIO_STATUS_PPR_INT_MASK) { |
804 | pr_devel("AMD-Vi: Processing IOMMU PPR Log\n"); | |
805 | iommu_poll_ppr_log(iommu); | |
806 | } | |
90008ee4 | 807 | |
bd6fcefc SS |
808 | #ifdef CONFIG_IRQ_REMAP |
809 | if (status & MMIO_STATUS_GALOG_INT_MASK) { | |
810 | pr_devel("AMD-Vi: Processing IOMMU GA Log\n"); | |
811 | iommu_poll_ga_log(iommu); | |
812 | } | |
813 | #endif | |
814 | ||
3f398bc7 SS |
815 | /* |
816 | * Hardware bug: ERBT1312 | |
817 | * When re-enabling interrupt (by writing 1 | |
818 | * to clear the bit), the hardware might also try to set | |
819 | * the interrupt bit in the event status register. | |
820 | * In this scenario, the bit will be set, and disable | |
821 | * subsequent interrupts. | |
822 | * | |
823 | * Workaround: The IOMMU driver should read back the | |
824 | * status register and check if the interrupt bits are cleared. | |
825 | * If not, driver will need to go through the interrupt handler | |
826 | * again and re-clear the bits | |
827 | */ | |
828 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
829 | } | |
90008ee4 | 830 | return IRQ_HANDLED; |
a80dc3e0 JR |
831 | } |
832 | ||
72fe00f0 JR |
833 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
834 | { | |
835 | return IRQ_WAKE_THREAD; | |
836 | } | |
837 | ||
431b2a20 JR |
838 | /**************************************************************************** |
839 | * | |
840 | * IOMMU command queuing functions | |
841 | * | |
842 | ****************************************************************************/ | |
843 | ||
ac0ea6e9 JR |
844 | static int wait_on_sem(volatile u64 *sem) |
845 | { | |
846 | int i = 0; | |
847 | ||
848 | while (*sem == 0 && i < LOOP_TIMEOUT) { | |
849 | udelay(1); | |
850 | i += 1; | |
851 | } | |
852 | ||
853 | if (i == LOOP_TIMEOUT) { | |
854 | pr_alert("AMD-Vi: Completion-Wait loop timed out\n"); | |
855 | return -EIO; | |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static void copy_cmd_to_buffer(struct amd_iommu *iommu, | |
d334a563 | 862 | struct iommu_cmd *cmd) |
a19ae1ec | 863 | { |
a19ae1ec JR |
864 | u8 *target; |
865 | ||
d334a563 TL |
866 | target = iommu->cmd_buf + iommu->cmd_buf_tail; |
867 | ||
868 | iommu->cmd_buf_tail += sizeof(*cmd); | |
869 | iommu->cmd_buf_tail %= CMD_BUFFER_SIZE; | |
ac0ea6e9 JR |
870 | |
871 | /* Copy command to buffer */ | |
872 | memcpy(target, cmd, sizeof(*cmd)); | |
873 | ||
874 | /* Tell the IOMMU about it */ | |
d334a563 | 875 | writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); |
ac0ea6e9 | 876 | } |
a19ae1ec | 877 | |
815b33fd | 878 | static void build_completion_wait(struct iommu_cmd *cmd, u64 address) |
ded46737 | 879 | { |
2543a786 TL |
880 | u64 paddr = iommu_virt_to_phys((void *)address); |
881 | ||
815b33fd JR |
882 | WARN_ON(address & 0x7ULL); |
883 | ||
ded46737 | 884 | memset(cmd, 0, sizeof(*cmd)); |
2543a786 TL |
885 | cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; |
886 | cmd->data[1] = upper_32_bits(paddr); | |
815b33fd | 887 | cmd->data[2] = 1; |
ded46737 JR |
888 | CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); |
889 | } | |
890 | ||
94fe79e2 JR |
891 | static void build_inv_dte(struct iommu_cmd *cmd, u16 devid) |
892 | { | |
893 | memset(cmd, 0, sizeof(*cmd)); | |
894 | cmd->data[0] = devid; | |
895 | CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY); | |
896 | } | |
897 | ||
11b6402c JR |
898 | static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
899 | size_t size, u16 domid, int pde) | |
900 | { | |
901 | u64 pages; | |
ae0cbbb1 | 902 | bool s; |
11b6402c JR |
903 | |
904 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 905 | s = false; |
11b6402c JR |
906 | |
907 | if (pages > 1) { | |
908 | /* | |
909 | * If we have to flush more than one page, flush all | |
910 | * TLB entries for this domain | |
911 | */ | |
912 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 913 | s = true; |
11b6402c JR |
914 | } |
915 | ||
916 | address &= PAGE_MASK; | |
917 | ||
918 | memset(cmd, 0, sizeof(*cmd)); | |
919 | cmd->data[1] |= domid; | |
920 | cmd->data[2] = lower_32_bits(address); | |
921 | cmd->data[3] = upper_32_bits(address); | |
922 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
923 | if (s) /* size bit - we flush more than one 4kb page */ | |
924 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
df805abb | 925 | if (pde) /* PDE bit - we want to flush everything, not only the PTEs */ |
11b6402c JR |
926 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; |
927 | } | |
928 | ||
cb41ed85 JR |
929 | static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep, |
930 | u64 address, size_t size) | |
931 | { | |
932 | u64 pages; | |
ae0cbbb1 | 933 | bool s; |
cb41ed85 JR |
934 | |
935 | pages = iommu_num_pages(address, size, PAGE_SIZE); | |
ae0cbbb1 | 936 | s = false; |
cb41ed85 JR |
937 | |
938 | if (pages > 1) { | |
939 | /* | |
940 | * If we have to flush more than one page, flush all | |
941 | * TLB entries for this domain | |
942 | */ | |
943 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
ae0cbbb1 | 944 | s = true; |
cb41ed85 JR |
945 | } |
946 | ||
947 | address &= PAGE_MASK; | |
948 | ||
949 | memset(cmd, 0, sizeof(*cmd)); | |
950 | cmd->data[0] = devid; | |
951 | cmd->data[0] |= (qdep & 0xff) << 24; | |
952 | cmd->data[1] = devid; | |
953 | cmd->data[2] = lower_32_bits(address); | |
954 | cmd->data[3] = upper_32_bits(address); | |
955 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
956 | if (s) | |
957 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
958 | } | |
959 | ||
22e266c7 JR |
960 | static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid, |
961 | u64 address, bool size) | |
962 | { | |
963 | memset(cmd, 0, sizeof(*cmd)); | |
964 | ||
965 | address &= ~(0xfffULL); | |
966 | ||
a919a018 | 967 | cmd->data[0] = pasid; |
22e266c7 JR |
968 | cmd->data[1] = domid; |
969 | cmd->data[2] = lower_32_bits(address); | |
970 | cmd->data[3] = upper_32_bits(address); | |
971 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
972 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
973 | if (size) | |
974 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
975 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
976 | } | |
977 | ||
978 | static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid, | |
979 | int qdep, u64 address, bool size) | |
980 | { | |
981 | memset(cmd, 0, sizeof(*cmd)); | |
982 | ||
983 | address &= ~(0xfffULL); | |
984 | ||
985 | cmd->data[0] = devid; | |
e8d2d82d | 986 | cmd->data[0] |= ((pasid >> 8) & 0xff) << 16; |
22e266c7 JR |
987 | cmd->data[0] |= (qdep & 0xff) << 24; |
988 | cmd->data[1] = devid; | |
e8d2d82d | 989 | cmd->data[1] |= (pasid & 0xff) << 16; |
22e266c7 JR |
990 | cmd->data[2] = lower_32_bits(address); |
991 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK; | |
992 | cmd->data[3] = upper_32_bits(address); | |
993 | if (size) | |
994 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
995 | CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES); | |
996 | } | |
997 | ||
c99afa25 JR |
998 | static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid, |
999 | int status, int tag, bool gn) | |
1000 | { | |
1001 | memset(cmd, 0, sizeof(*cmd)); | |
1002 | ||
1003 | cmd->data[0] = devid; | |
1004 | if (gn) { | |
a919a018 | 1005 | cmd->data[1] = pasid; |
c99afa25 JR |
1006 | cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK; |
1007 | } | |
1008 | cmd->data[3] = tag & 0x1ff; | |
1009 | cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT; | |
1010 | ||
1011 | CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR); | |
1012 | } | |
1013 | ||
58fc7f14 JR |
1014 | static void build_inv_all(struct iommu_cmd *cmd) |
1015 | { | |
1016 | memset(cmd, 0, sizeof(*cmd)); | |
1017 | CMD_SET_TYPE(cmd, CMD_INV_ALL); | |
a19ae1ec JR |
1018 | } |
1019 | ||
7ef2798d JR |
1020 | static void build_inv_irt(struct iommu_cmd *cmd, u16 devid) |
1021 | { | |
1022 | memset(cmd, 0, sizeof(*cmd)); | |
1023 | cmd->data[0] = devid; | |
1024 | CMD_SET_TYPE(cmd, CMD_INV_IRT); | |
1025 | } | |
1026 | ||
431b2a20 | 1027 | /* |
431b2a20 | 1028 | * Writes the command to the IOMMUs command buffer and informs the |
ac0ea6e9 | 1029 | * hardware about the new command. |
431b2a20 | 1030 | */ |
4bf5beef JR |
1031 | static int __iommu_queue_command_sync(struct amd_iommu *iommu, |
1032 | struct iommu_cmd *cmd, | |
1033 | bool sync) | |
a19ae1ec | 1034 | { |
23e967e1 | 1035 | unsigned int count = 0; |
d334a563 | 1036 | u32 left, next_tail; |
a19ae1ec | 1037 | |
d334a563 | 1038 | next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE; |
ac0ea6e9 | 1039 | again: |
d334a563 | 1040 | left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE; |
a19ae1ec | 1041 | |
432abf68 | 1042 | if (left <= 0x20) { |
23e967e1 TL |
1043 | /* Skip udelay() the first time around */ |
1044 | if (count++) { | |
1045 | if (count == LOOP_TIMEOUT) { | |
1046 | pr_err("AMD-Vi: Command buffer timeout\n"); | |
1047 | return -EIO; | |
1048 | } | |
da49f6df | 1049 | |
23e967e1 TL |
1050 | udelay(1); |
1051 | } | |
ac0ea6e9 | 1052 | |
23e967e1 TL |
1053 | /* Update head and recheck remaining space */ |
1054 | iommu->cmd_buf_head = readl(iommu->mmio_base + | |
1055 | MMIO_CMD_HEAD_OFFSET); | |
ac0ea6e9 JR |
1056 | |
1057 | goto again; | |
8d201968 JR |
1058 | } |
1059 | ||
d334a563 | 1060 | copy_cmd_to_buffer(iommu, cmd); |
ac0ea6e9 | 1061 | |
23e967e1 | 1062 | /* Do we need to make sure all commands are processed? */ |
f1ca1512 | 1063 | iommu->need_sync = sync; |
ac0ea6e9 | 1064 | |
4bf5beef JR |
1065 | return 0; |
1066 | } | |
1067 | ||
1068 | static int iommu_queue_command_sync(struct amd_iommu *iommu, | |
1069 | struct iommu_cmd *cmd, | |
1070 | bool sync) | |
1071 | { | |
1072 | unsigned long flags; | |
1073 | int ret; | |
1074 | ||
1075 | spin_lock_irqsave(&iommu->lock, flags); | |
1076 | ret = __iommu_queue_command_sync(iommu, cmd, sync); | |
a19ae1ec | 1077 | spin_unlock_irqrestore(&iommu->lock, flags); |
8d201968 | 1078 | |
4bf5beef | 1079 | return ret; |
8d201968 JR |
1080 | } |
1081 | ||
f1ca1512 JR |
1082 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
1083 | { | |
1084 | return iommu_queue_command_sync(iommu, cmd, true); | |
1085 | } | |
1086 | ||
8d201968 JR |
1087 | /* |
1088 | * This function queues a completion wait command into the command | |
1089 | * buffer of an IOMMU | |
1090 | */ | |
a19ae1ec | 1091 | static int iommu_completion_wait(struct amd_iommu *iommu) |
8d201968 JR |
1092 | { |
1093 | struct iommu_cmd cmd; | |
4bf5beef | 1094 | unsigned long flags; |
ac0ea6e9 | 1095 | int ret; |
8d201968 | 1096 | |
09ee17eb | 1097 | if (!iommu->need_sync) |
815b33fd | 1098 | return 0; |
09ee17eb | 1099 | |
a19ae1ec | 1100 | |
4bf5beef JR |
1101 | build_completion_wait(&cmd, (u64)&iommu->cmd_sem); |
1102 | ||
1103 | spin_lock_irqsave(&iommu->lock, flags); | |
1104 | ||
1105 | iommu->cmd_sem = 0; | |
1106 | ||
1107 | ret = __iommu_queue_command_sync(iommu, &cmd, false); | |
a19ae1ec | 1108 | if (ret) |
4bf5beef JR |
1109 | goto out_unlock; |
1110 | ||
1111 | ret = wait_on_sem(&iommu->cmd_sem); | |
1112 | ||
1113 | out_unlock: | |
1114 | spin_unlock_irqrestore(&iommu->lock, flags); | |
8d201968 | 1115 | |
4bf5beef | 1116 | return ret; |
8d201968 JR |
1117 | } |
1118 | ||
d8c13085 | 1119 | static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) |
a19ae1ec | 1120 | { |
d8c13085 | 1121 | struct iommu_cmd cmd; |
a19ae1ec | 1122 | |
d8c13085 | 1123 | build_inv_dte(&cmd, devid); |
7e4f88da | 1124 | |
d8c13085 JR |
1125 | return iommu_queue_command(iommu, &cmd); |
1126 | } | |
09ee17eb | 1127 | |
0688a099 | 1128 | static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1129 | { |
1130 | u32 devid; | |
09ee17eb | 1131 | |
7d0c5cc5 JR |
1132 | for (devid = 0; devid <= 0xffff; ++devid) |
1133 | iommu_flush_dte(iommu, devid); | |
a19ae1ec | 1134 | |
7d0c5cc5 JR |
1135 | iommu_completion_wait(iommu); |
1136 | } | |
84df8175 | 1137 | |
7d0c5cc5 JR |
1138 | /* |
1139 | * This function uses heavy locking and may disable irqs for some time. But | |
1140 | * this is no issue because it is only called during resume. | |
1141 | */ | |
0688a099 | 1142 | static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu) |
7d0c5cc5 JR |
1143 | { |
1144 | u32 dom_id; | |
a19ae1ec | 1145 | |
7d0c5cc5 JR |
1146 | for (dom_id = 0; dom_id <= 0xffff; ++dom_id) { |
1147 | struct iommu_cmd cmd; | |
1148 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1149 | dom_id, 1); | |
1150 | iommu_queue_command(iommu, &cmd); | |
1151 | } | |
8eed9833 | 1152 | |
7d0c5cc5 | 1153 | iommu_completion_wait(iommu); |
a19ae1ec JR |
1154 | } |
1155 | ||
c284a37b SH |
1156 | static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) |
1157 | { | |
1158 | struct iommu_cmd cmd; | |
1159 | ||
1160 | build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
1161 | dom_id, 1); | |
1162 | iommu_queue_command(iommu, &cmd); | |
1163 | ||
1164 | iommu_completion_wait(iommu); | |
1165 | } | |
1166 | ||
0688a099 | 1167 | static void amd_iommu_flush_all(struct amd_iommu *iommu) |
0518a3a4 | 1168 | { |
58fc7f14 | 1169 | struct iommu_cmd cmd; |
0518a3a4 | 1170 | |
58fc7f14 | 1171 | build_inv_all(&cmd); |
0518a3a4 | 1172 | |
58fc7f14 JR |
1173 | iommu_queue_command(iommu, &cmd); |
1174 | iommu_completion_wait(iommu); | |
1175 | } | |
1176 | ||
7ef2798d JR |
1177 | static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) |
1178 | { | |
1179 | struct iommu_cmd cmd; | |
1180 | ||
1181 | build_inv_irt(&cmd, devid); | |
1182 | ||
1183 | iommu_queue_command(iommu, &cmd); | |
1184 | } | |
1185 | ||
0688a099 | 1186 | static void amd_iommu_flush_irt_all(struct amd_iommu *iommu) |
7ef2798d JR |
1187 | { |
1188 | u32 devid; | |
1189 | ||
1190 | for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++) | |
1191 | iommu_flush_irt(iommu, devid); | |
1192 | ||
1193 | iommu_completion_wait(iommu); | |
1194 | } | |
1195 | ||
7d0c5cc5 JR |
1196 | void iommu_flush_all_caches(struct amd_iommu *iommu) |
1197 | { | |
58fc7f14 | 1198 | if (iommu_feature(iommu, FEATURE_IA)) { |
0688a099 | 1199 | amd_iommu_flush_all(iommu); |
58fc7f14 | 1200 | } else { |
0688a099 JR |
1201 | amd_iommu_flush_dte_all(iommu); |
1202 | amd_iommu_flush_irt_all(iommu); | |
1203 | amd_iommu_flush_tlb_all(iommu); | |
0518a3a4 JR |
1204 | } |
1205 | } | |
1206 | ||
431b2a20 | 1207 | /* |
cb41ed85 | 1208 | * Command send function for flushing on-device TLB |
431b2a20 | 1209 | */ |
6c542047 JR |
1210 | static int device_flush_iotlb(struct iommu_dev_data *dev_data, |
1211 | u64 address, size_t size) | |
3fa43655 JR |
1212 | { |
1213 | struct amd_iommu *iommu; | |
b00d3bcf | 1214 | struct iommu_cmd cmd; |
cb41ed85 | 1215 | int qdep; |
3fa43655 | 1216 | |
ea61cddb JR |
1217 | qdep = dev_data->ats.qdep; |
1218 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3fa43655 | 1219 | |
ea61cddb | 1220 | build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size); |
b00d3bcf JR |
1221 | |
1222 | return iommu_queue_command(iommu, &cmd); | |
3fa43655 JR |
1223 | } |
1224 | ||
431b2a20 | 1225 | /* |
431b2a20 | 1226 | * Command send function for invalidating a device table entry |
431b2a20 | 1227 | */ |
6c542047 | 1228 | static int device_flush_dte(struct iommu_dev_data *dev_data) |
a19ae1ec | 1229 | { |
3fa43655 | 1230 | struct amd_iommu *iommu; |
e25bfb56 | 1231 | u16 alias; |
ee2fa743 | 1232 | int ret; |
a19ae1ec | 1233 | |
6c542047 | 1234 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1235 | alias = dev_data->alias; |
a19ae1ec | 1236 | |
f62dda66 | 1237 | ret = iommu_flush_dte(iommu, dev_data->devid); |
e25bfb56 JR |
1238 | if (!ret && alias != dev_data->devid) |
1239 | ret = iommu_flush_dte(iommu, alias); | |
cb41ed85 JR |
1240 | if (ret) |
1241 | return ret; | |
1242 | ||
ea61cddb | 1243 | if (dev_data->ats.enabled) |
6c542047 | 1244 | ret = device_flush_iotlb(dev_data, 0, ~0UL); |
ee2fa743 | 1245 | |
ee2fa743 | 1246 | return ret; |
a19ae1ec JR |
1247 | } |
1248 | ||
431b2a20 JR |
1249 | /* |
1250 | * TLB invalidation function which is called from the mapping functions. | |
1251 | * It invalidates a single PTE if the range to flush is within a single | |
1252 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
1253 | */ | |
17b124bf JR |
1254 | static void __domain_flush_pages(struct protection_domain *domain, |
1255 | u64 address, size_t size, int pde) | |
a19ae1ec | 1256 | { |
cb41ed85 | 1257 | struct iommu_dev_data *dev_data; |
11b6402c JR |
1258 | struct iommu_cmd cmd; |
1259 | int ret = 0, i; | |
a19ae1ec | 1260 | |
11b6402c | 1261 | build_inv_iommu_pages(&cmd, address, size, domain->id, pde); |
999ba417 | 1262 | |
6b9376e3 | 1263 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
6de8ad9b JR |
1264 | if (!domain->dev_iommu[i]) |
1265 | continue; | |
1266 | ||
1267 | /* | |
1268 | * Devices of this domain are behind this IOMMU | |
1269 | * We need a TLB flush | |
1270 | */ | |
11b6402c | 1271 | ret |= iommu_queue_command(amd_iommus[i], &cmd); |
6de8ad9b JR |
1272 | } |
1273 | ||
cb41ed85 | 1274 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
cb41ed85 | 1275 | |
ea61cddb | 1276 | if (!dev_data->ats.enabled) |
cb41ed85 JR |
1277 | continue; |
1278 | ||
6c542047 | 1279 | ret |= device_flush_iotlb(dev_data, address, size); |
cb41ed85 JR |
1280 | } |
1281 | ||
11b6402c | 1282 | WARN_ON(ret); |
6de8ad9b JR |
1283 | } |
1284 | ||
17b124bf JR |
1285 | static void domain_flush_pages(struct protection_domain *domain, |
1286 | u64 address, size_t size) | |
6de8ad9b | 1287 | { |
17b124bf | 1288 | __domain_flush_pages(domain, address, size, 0); |
a19ae1ec | 1289 | } |
b6c02715 | 1290 | |
1c655773 | 1291 | /* Flush the whole IO/TLB for a given protection domain */ |
17b124bf | 1292 | static void domain_flush_tlb(struct protection_domain *domain) |
1c655773 | 1293 | { |
17b124bf | 1294 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
1295 | } |
1296 | ||
42a49f96 | 1297 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
17b124bf | 1298 | static void domain_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 1299 | { |
17b124bf | 1300 | __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
1301 | } |
1302 | ||
17b124bf | 1303 | static void domain_flush_complete(struct protection_domain *domain) |
b00d3bcf | 1304 | { |
17b124bf | 1305 | int i; |
18811f55 | 1306 | |
6b9376e3 | 1307 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
f1eae7c5 | 1308 | if (domain && !domain->dev_iommu[i]) |
17b124bf | 1309 | continue; |
bfd1be18 | 1310 | |
17b124bf JR |
1311 | /* |
1312 | * Devices of this domain are behind this IOMMU | |
1313 | * We need to wait for completion of all commands. | |
1314 | */ | |
1315 | iommu_completion_wait(amd_iommus[i]); | |
bfd1be18 | 1316 | } |
e394d72a JR |
1317 | } |
1318 | ||
b00d3bcf | 1319 | |
09b42804 | 1320 | /* |
b00d3bcf | 1321 | * This function flushes the DTEs for all devices in domain |
09b42804 | 1322 | */ |
17b124bf | 1323 | static void domain_flush_devices(struct protection_domain *domain) |
e394d72a | 1324 | { |
b00d3bcf | 1325 | struct iommu_dev_data *dev_data; |
b26e81b8 | 1326 | |
b00d3bcf | 1327 | list_for_each_entry(dev_data, &domain->dev_list, list) |
6c542047 | 1328 | device_flush_dte(dev_data); |
a345b23b JR |
1329 | } |
1330 | ||
431b2a20 JR |
1331 | /**************************************************************************** |
1332 | * | |
1333 | * The functions below are used the create the page table mappings for | |
1334 | * unity mapped regions. | |
1335 | * | |
1336 | ****************************************************************************/ | |
1337 | ||
308973d3 JR |
1338 | /* |
1339 | * This function is used to add another level to an IO page table. Adding | |
1340 | * another level increases the size of the address space by 9 bits to a size up | |
1341 | * to 64 bits. | |
1342 | */ | |
71afff05 | 1343 | static void increase_address_space(struct protection_domain *domain, |
308973d3 JR |
1344 | gfp_t gfp) |
1345 | { | |
71afff05 | 1346 | unsigned long flags; |
308973d3 JR |
1347 | u64 *pte; |
1348 | ||
71afff05 JR |
1349 | spin_lock_irqsave(&domain->lock, flags); |
1350 | ||
1351 | if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL)) | |
308973d3 | 1352 | /* address space already 64 bit large */ |
71afff05 | 1353 | goto out; |
308973d3 JR |
1354 | |
1355 | pte = (void *)get_zeroed_page(gfp); | |
1356 | if (!pte) | |
71afff05 | 1357 | goto out; |
308973d3 JR |
1358 | |
1359 | *pte = PM_LEVEL_PDE(domain->mode, | |
2543a786 | 1360 | iommu_virt_to_phys(domain->pt_root)); |
308973d3 JR |
1361 | domain->pt_root = pte; |
1362 | domain->mode += 1; | |
1363 | domain->updated = true; | |
1364 | ||
71afff05 JR |
1365 | out: |
1366 | spin_unlock_irqrestore(&domain->lock, flags); | |
1367 | ||
1368 | return; | |
308973d3 JR |
1369 | } |
1370 | ||
1371 | static u64 *alloc_pte(struct protection_domain *domain, | |
1372 | unsigned long address, | |
cbb9d729 | 1373 | unsigned long page_size, |
308973d3 JR |
1374 | u64 **pte_page, |
1375 | gfp_t gfp) | |
1376 | { | |
cbb9d729 | 1377 | int level, end_lvl; |
308973d3 | 1378 | u64 *pte, *page; |
cbb9d729 JR |
1379 | |
1380 | BUG_ON(!is_power_of_2(page_size)); | |
308973d3 JR |
1381 | |
1382 | while (address > PM_LEVEL_SIZE(domain->mode)) | |
1383 | increase_address_space(domain, gfp); | |
1384 | ||
cbb9d729 JR |
1385 | level = domain->mode - 1; |
1386 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1387 | address = PAGE_SIZE_ALIGN(address, page_size); | |
1388 | end_lvl = PAGE_SIZE_LEVEL(page_size); | |
308973d3 JR |
1389 | |
1390 | while (level > end_lvl) { | |
7bfa5bd2 JR |
1391 | u64 __pte, __npte; |
1392 | ||
1393 | __pte = *pte; | |
1394 | ||
1395 | if (!IOMMU_PTE_PRESENT(__pte)) { | |
308973d3 JR |
1396 | page = (u64 *)get_zeroed_page(gfp); |
1397 | if (!page) | |
1398 | return NULL; | |
7bfa5bd2 | 1399 | |
2543a786 | 1400 | __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page)); |
7bfa5bd2 | 1401 | |
134414ff BH |
1402 | /* pte could have been changed somewhere. */ |
1403 | if (cmpxchg64(pte, __pte, __npte) != __pte) { | |
7bfa5bd2 JR |
1404 | free_page((unsigned long)page); |
1405 | continue; | |
1406 | } | |
308973d3 JR |
1407 | } |
1408 | ||
cbb9d729 JR |
1409 | /* No level skipping support yet */ |
1410 | if (PM_PTE_LEVEL(*pte) != level) | |
1411 | return NULL; | |
1412 | ||
308973d3 JR |
1413 | level -= 1; |
1414 | ||
1415 | pte = IOMMU_PTE_PAGE(*pte); | |
1416 | ||
1417 | if (pte_page && level == end_lvl) | |
1418 | *pte_page = pte; | |
1419 | ||
1420 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1421 | } | |
1422 | ||
1423 | return pte; | |
1424 | } | |
1425 | ||
1426 | /* | |
1427 | * This function checks if there is a PTE for a given dma address. If | |
1428 | * there is one, it returns the pointer to it. | |
1429 | */ | |
3039ca1b JR |
1430 | static u64 *fetch_pte(struct protection_domain *domain, |
1431 | unsigned long address, | |
1432 | unsigned long *page_size) | |
308973d3 JR |
1433 | { |
1434 | int level; | |
1435 | u64 *pte; | |
1436 | ||
24cd7723 JR |
1437 | if (address > PM_LEVEL_SIZE(domain->mode)) |
1438 | return NULL; | |
1439 | ||
3039ca1b JR |
1440 | level = domain->mode - 1; |
1441 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
1442 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
308973d3 | 1443 | |
24cd7723 JR |
1444 | while (level > 0) { |
1445 | ||
1446 | /* Not Present */ | |
308973d3 JR |
1447 | if (!IOMMU_PTE_PRESENT(*pte)) |
1448 | return NULL; | |
1449 | ||
24cd7723 | 1450 | /* Large PTE */ |
3039ca1b JR |
1451 | if (PM_PTE_LEVEL(*pte) == 7 || |
1452 | PM_PTE_LEVEL(*pte) == 0) | |
1453 | break; | |
24cd7723 JR |
1454 | |
1455 | /* No level skipping support yet */ | |
1456 | if (PM_PTE_LEVEL(*pte) != level) | |
1457 | return NULL; | |
1458 | ||
308973d3 JR |
1459 | level -= 1; |
1460 | ||
24cd7723 | 1461 | /* Walk to the next level */ |
3039ca1b JR |
1462 | pte = IOMMU_PTE_PAGE(*pte); |
1463 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
1464 | *page_size = PTE_LEVEL_PAGE_SIZE(level); | |
1465 | } | |
1466 | ||
1467 | if (PM_PTE_LEVEL(*pte) == 0x07) { | |
1468 | unsigned long pte_mask; | |
1469 | ||
1470 | /* | |
1471 | * If we have a series of large PTEs, make | |
1472 | * sure to return a pointer to the first one. | |
1473 | */ | |
1474 | *page_size = pte_mask = PTE_PAGE_SIZE(*pte); | |
1475 | pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1); | |
1476 | pte = (u64 *)(((unsigned long)pte) & pte_mask); | |
308973d3 JR |
1477 | } |
1478 | ||
1479 | return pte; | |
1480 | } | |
1481 | ||
431b2a20 JR |
1482 | /* |
1483 | * Generic mapping functions. It maps a physical address into a DMA | |
1484 | * address space. It allocates the page table pages if necessary. | |
1485 | * In the future it can be extended to a generic mapping function | |
1486 | * supporting all features of AMD IOMMU page tables like level skipping | |
1487 | * and full 64 bit address spaces. | |
1488 | */ | |
38e817fe JR |
1489 | static int iommu_map_page(struct protection_domain *dom, |
1490 | unsigned long bus_addr, | |
1491 | unsigned long phys_addr, | |
b911b89b | 1492 | unsigned long page_size, |
abdc5eb3 | 1493 | int prot, |
b911b89b | 1494 | gfp_t gfp) |
bd0e5211 | 1495 | { |
8bda3092 | 1496 | u64 __pte, *pte; |
cbb9d729 | 1497 | int i, count; |
abdc5eb3 | 1498 | |
d4b03664 JR |
1499 | BUG_ON(!IS_ALIGNED(bus_addr, page_size)); |
1500 | BUG_ON(!IS_ALIGNED(phys_addr, page_size)); | |
1501 | ||
bad1cac2 | 1502 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
1503 | return -EINVAL; |
1504 | ||
d4b03664 | 1505 | count = PAGE_SIZE_PTE_COUNT(page_size); |
b911b89b | 1506 | pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp); |
cbb9d729 | 1507 | |
63eaa75e ML |
1508 | if (!pte) |
1509 | return -ENOMEM; | |
1510 | ||
cbb9d729 JR |
1511 | for (i = 0; i < count; ++i) |
1512 | if (IOMMU_PTE_PRESENT(pte[i])) | |
1513 | return -EBUSY; | |
bd0e5211 | 1514 | |
d4b03664 | 1515 | if (count > 1) { |
2543a786 | 1516 | __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size); |
07a80a6b | 1517 | __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
cbb9d729 | 1518 | } else |
4dfc2788 | 1519 | __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC; |
bd0e5211 | 1520 | |
bd0e5211 JR |
1521 | if (prot & IOMMU_PROT_IR) |
1522 | __pte |= IOMMU_PTE_IR; | |
1523 | if (prot & IOMMU_PROT_IW) | |
1524 | __pte |= IOMMU_PTE_IW; | |
1525 | ||
cbb9d729 JR |
1526 | for (i = 0; i < count; ++i) |
1527 | pte[i] = __pte; | |
bd0e5211 | 1528 | |
04bfdd84 JR |
1529 | update_domain(dom); |
1530 | ||
bd0e5211 JR |
1531 | return 0; |
1532 | } | |
1533 | ||
24cd7723 JR |
1534 | static unsigned long iommu_unmap_page(struct protection_domain *dom, |
1535 | unsigned long bus_addr, | |
1536 | unsigned long page_size) | |
eb74ff6c | 1537 | { |
71b390e9 JR |
1538 | unsigned long long unmapped; |
1539 | unsigned long unmap_size; | |
24cd7723 JR |
1540 | u64 *pte; |
1541 | ||
1542 | BUG_ON(!is_power_of_2(page_size)); | |
1543 | ||
1544 | unmapped = 0; | |
eb74ff6c | 1545 | |
24cd7723 JR |
1546 | while (unmapped < page_size) { |
1547 | ||
71b390e9 JR |
1548 | pte = fetch_pte(dom, bus_addr, &unmap_size); |
1549 | ||
1550 | if (pte) { | |
1551 | int i, count; | |
1552 | ||
1553 | count = PAGE_SIZE_PTE_COUNT(unmap_size); | |
24cd7723 JR |
1554 | for (i = 0; i < count; i++) |
1555 | pte[i] = 0ULL; | |
1556 | } | |
1557 | ||
1558 | bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size; | |
1559 | unmapped += unmap_size; | |
1560 | } | |
1561 | ||
60d0ca3c | 1562 | BUG_ON(unmapped && !is_power_of_2(unmapped)); |
eb74ff6c | 1563 | |
24cd7723 | 1564 | return unmapped; |
eb74ff6c | 1565 | } |
eb74ff6c | 1566 | |
431b2a20 JR |
1567 | /**************************************************************************** |
1568 | * | |
1569 | * The next functions belong to the address allocator for the dma_ops | |
2d4c515b | 1570 | * interface functions. |
431b2a20 JR |
1571 | * |
1572 | ****************************************************************************/ | |
d3086444 | 1573 | |
9cabe89b | 1574 | |
256e4621 JR |
1575 | static unsigned long dma_ops_alloc_iova(struct device *dev, |
1576 | struct dma_ops_domain *dma_dom, | |
1577 | unsigned int pages, u64 dma_mask) | |
384de729 | 1578 | { |
256e4621 | 1579 | unsigned long pfn = 0; |
384de729 | 1580 | |
256e4621 | 1581 | pages = __roundup_pow_of_two(pages); |
ccb50e03 | 1582 | |
256e4621 JR |
1583 | if (dma_mask > DMA_BIT_MASK(32)) |
1584 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, | |
538d5b33 | 1585 | IOVA_PFN(DMA_BIT_MASK(32)), false); |
7b5e25b8 | 1586 | |
256e4621 | 1587 | if (!pfn) |
538d5b33 TN |
1588 | pfn = alloc_iova_fast(&dma_dom->iovad, pages, |
1589 | IOVA_PFN(dma_mask), true); | |
5f6bed50 | 1590 | |
256e4621 | 1591 | return (pfn << PAGE_SHIFT); |
384de729 JR |
1592 | } |
1593 | ||
256e4621 JR |
1594 | static void dma_ops_free_iova(struct dma_ops_domain *dma_dom, |
1595 | unsigned long address, | |
1596 | unsigned int pages) | |
d3086444 | 1597 | { |
256e4621 JR |
1598 | pages = __roundup_pow_of_two(pages); |
1599 | address >>= PAGE_SHIFT; | |
384de729 | 1600 | |
256e4621 | 1601 | free_iova_fast(&dma_dom->iovad, address, pages); |
d3086444 JR |
1602 | } |
1603 | ||
431b2a20 JR |
1604 | /**************************************************************************** |
1605 | * | |
1606 | * The next functions belong to the domain allocation. A domain is | |
1607 | * allocated for every IOMMU as the default domain. If device isolation | |
1608 | * is enabled, every device get its own domain. The most important thing | |
1609 | * about domains is the page table mapping the DMA address space they | |
1610 | * contain. | |
1611 | * | |
1612 | ****************************************************************************/ | |
1613 | ||
aeb26f55 JR |
1614 | /* |
1615 | * This function adds a protection domain to the global protection domain list | |
1616 | */ | |
1617 | static void add_domain_to_list(struct protection_domain *domain) | |
1618 | { | |
1619 | unsigned long flags; | |
1620 | ||
1621 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1622 | list_add(&domain->list, &amd_iommu_pd_list); | |
1623 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1624 | } | |
1625 | ||
1626 | /* | |
1627 | * This function removes a protection domain to the global | |
1628 | * protection domain list | |
1629 | */ | |
1630 | static void del_domain_from_list(struct protection_domain *domain) | |
1631 | { | |
1632 | unsigned long flags; | |
1633 | ||
1634 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1635 | list_del(&domain->list); | |
1636 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1637 | } | |
1638 | ||
ec487d1a JR |
1639 | static u16 domain_id_alloc(void) |
1640 | { | |
1641 | unsigned long flags; | |
1642 | int id; | |
1643 | ||
1644 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1645 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1646 | BUG_ON(id == 0); | |
1647 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1648 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1649 | else | |
1650 | id = 0; | |
1651 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1652 | ||
1653 | return id; | |
1654 | } | |
1655 | ||
a2acfb75 JR |
1656 | static void domain_id_free(int id) |
1657 | { | |
1658 | unsigned long flags; | |
1659 | ||
1660 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1661 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1662 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1663 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1664 | } | |
a2acfb75 | 1665 | |
5c34c403 JR |
1666 | #define DEFINE_FREE_PT_FN(LVL, FN) \ |
1667 | static void free_pt_##LVL (unsigned long __pt) \ | |
1668 | { \ | |
1669 | unsigned long p; \ | |
1670 | u64 *pt; \ | |
1671 | int i; \ | |
1672 | \ | |
1673 | pt = (u64 *)__pt; \ | |
1674 | \ | |
1675 | for (i = 0; i < 512; ++i) { \ | |
0b3fff54 | 1676 | /* PTE present? */ \ |
5c34c403 JR |
1677 | if (!IOMMU_PTE_PRESENT(pt[i])) \ |
1678 | continue; \ | |
1679 | \ | |
0b3fff54 JR |
1680 | /* Large PTE? */ \ |
1681 | if (PM_PTE_LEVEL(pt[i]) == 0 || \ | |
1682 | PM_PTE_LEVEL(pt[i]) == 7) \ | |
1683 | continue; \ | |
1684 | \ | |
5c34c403 JR |
1685 | p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \ |
1686 | FN(p); \ | |
1687 | } \ | |
1688 | free_page((unsigned long)pt); \ | |
1689 | } | |
1690 | ||
1691 | DEFINE_FREE_PT_FN(l2, free_page) | |
1692 | DEFINE_FREE_PT_FN(l3, free_pt_l2) | |
1693 | DEFINE_FREE_PT_FN(l4, free_pt_l3) | |
1694 | DEFINE_FREE_PT_FN(l5, free_pt_l4) | |
1695 | DEFINE_FREE_PT_FN(l6, free_pt_l5) | |
1696 | ||
86db2e5d | 1697 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a | 1698 | { |
5c34c403 | 1699 | unsigned long root = (unsigned long)domain->pt_root; |
ec487d1a | 1700 | |
5c34c403 JR |
1701 | switch (domain->mode) { |
1702 | case PAGE_MODE_NONE: | |
1703 | break; | |
1704 | case PAGE_MODE_1_LEVEL: | |
1705 | free_page(root); | |
1706 | break; | |
1707 | case PAGE_MODE_2_LEVEL: | |
1708 | free_pt_l2(root); | |
1709 | break; | |
1710 | case PAGE_MODE_3_LEVEL: | |
1711 | free_pt_l3(root); | |
1712 | break; | |
1713 | case PAGE_MODE_4_LEVEL: | |
1714 | free_pt_l4(root); | |
1715 | break; | |
1716 | case PAGE_MODE_5_LEVEL: | |
1717 | free_pt_l5(root); | |
1718 | break; | |
1719 | case PAGE_MODE_6_LEVEL: | |
1720 | free_pt_l6(root); | |
1721 | break; | |
1722 | default: | |
1723 | BUG(); | |
ec487d1a | 1724 | } |
ec487d1a JR |
1725 | } |
1726 | ||
b16137b1 JR |
1727 | static void free_gcr3_tbl_level1(u64 *tbl) |
1728 | { | |
1729 | u64 *ptr; | |
1730 | int i; | |
1731 | ||
1732 | for (i = 0; i < 512; ++i) { | |
1733 | if (!(tbl[i] & GCR3_VALID)) | |
1734 | continue; | |
1735 | ||
2543a786 | 1736 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1737 | |
1738 | free_page((unsigned long)ptr); | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | static void free_gcr3_tbl_level2(u64 *tbl) | |
1743 | { | |
1744 | u64 *ptr; | |
1745 | int i; | |
1746 | ||
1747 | for (i = 0; i < 512; ++i) { | |
1748 | if (!(tbl[i] & GCR3_VALID)) | |
1749 | continue; | |
1750 | ||
2543a786 | 1751 | ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK); |
b16137b1 JR |
1752 | |
1753 | free_gcr3_tbl_level1(ptr); | |
1754 | } | |
1755 | } | |
1756 | ||
52815b75 JR |
1757 | static void free_gcr3_table(struct protection_domain *domain) |
1758 | { | |
b16137b1 JR |
1759 | if (domain->glx == 2) |
1760 | free_gcr3_tbl_level2(domain->gcr3_tbl); | |
1761 | else if (domain->glx == 1) | |
1762 | free_gcr3_tbl_level1(domain->gcr3_tbl); | |
23d3a98c JR |
1763 | else |
1764 | BUG_ON(domain->glx != 0); | |
b16137b1 | 1765 | |
52815b75 JR |
1766 | free_page((unsigned long)domain->gcr3_tbl); |
1767 | } | |
1768 | ||
fca6af6a JR |
1769 | static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom) |
1770 | { | |
fca6af6a JR |
1771 | domain_flush_tlb(&dom->domain); |
1772 | domain_flush_complete(&dom->domain); | |
fd62190a JR |
1773 | } |
1774 | ||
9003d618 | 1775 | static void iova_domain_flush_tlb(struct iova_domain *iovad) |
fd62190a | 1776 | { |
9003d618 | 1777 | struct dma_ops_domain *dom; |
fd62190a | 1778 | |
9003d618 | 1779 | dom = container_of(iovad, struct dma_ops_domain, iovad); |
fca6af6a JR |
1780 | |
1781 | dma_ops_domain_flush_tlb(dom); | |
fca6af6a JR |
1782 | } |
1783 | ||
431b2a20 JR |
1784 | /* |
1785 | * Free a domain, only used if something went wrong in the | |
1786 | * allocation path and we need to free an already allocated page table | |
1787 | */ | |
ec487d1a JR |
1788 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1789 | { | |
1790 | if (!dom) | |
1791 | return; | |
1792 | ||
aeb26f55 JR |
1793 | del_domain_from_list(&dom->domain); |
1794 | ||
2d4c515b | 1795 | put_iova_domain(&dom->iovad); |
ec487d1a | 1796 | |
2d4c515b | 1797 | free_pagetable(&dom->domain); |
ec487d1a | 1798 | |
c3db901c BH |
1799 | if (dom->domain.id) |
1800 | domain_id_free(dom->domain.id); | |
1801 | ||
ec487d1a JR |
1802 | kfree(dom); |
1803 | } | |
1804 | ||
431b2a20 JR |
1805 | /* |
1806 | * Allocates a new protection domain usable for the dma_ops functions. | |
b595076a | 1807 | * It also initializes the page table and the address allocator data |
431b2a20 JR |
1808 | * structures required for the dma_ops interface |
1809 | */ | |
87a64d52 | 1810 | static struct dma_ops_domain *dma_ops_domain_alloc(void) |
ec487d1a JR |
1811 | { |
1812 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1813 | |
1814 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1815 | if (!dma_dom) | |
1816 | return NULL; | |
1817 | ||
7a5a566e | 1818 | if (protection_domain_init(&dma_dom->domain)) |
ec487d1a | 1819 | goto free_dma_dom; |
7a5a566e | 1820 | |
ffec2197 | 1821 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; |
ec487d1a | 1822 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1823 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1824 | if (!dma_dom->domain.pt_root) |
1825 | goto free_dma_dom; | |
ec487d1a | 1826 | |
aa3ac946 | 1827 | init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN); |
307d5851 | 1828 | |
9003d618 | 1829 | if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL)) |
d4241a27 JR |
1830 | goto free_dma_dom; |
1831 | ||
9003d618 JR |
1832 | /* Initialize reserved ranges */ |
1833 | copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad); | |
fca6af6a | 1834 | |
2d4c515b JR |
1835 | add_domain_to_list(&dma_dom->domain); |
1836 | ||
ec487d1a JR |
1837 | return dma_dom; |
1838 | ||
1839 | free_dma_dom: | |
1840 | dma_ops_domain_free(dma_dom); | |
1841 | ||
1842 | return NULL; | |
1843 | } | |
1844 | ||
5b28df6f JR |
1845 | /* |
1846 | * little helper function to check whether a given protection domain is a | |
1847 | * dma_ops domain | |
1848 | */ | |
1849 | static bool dma_ops_domain(struct protection_domain *domain) | |
1850 | { | |
1851 | return domain->flags & PD_DMA_OPS_MASK; | |
1852 | } | |
1853 | ||
fd7b5535 | 1854 | static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats) |
b20ac0d4 | 1855 | { |
132bd68f | 1856 | u64 pte_root = 0; |
ee6c2868 | 1857 | u64 flags = 0; |
c284a37b | 1858 | u32 old_domid; |
863c74eb | 1859 | |
132bd68f | 1860 | if (domain->mode != PAGE_MODE_NONE) |
2543a786 | 1861 | pte_root = iommu_virt_to_phys(domain->pt_root); |
132bd68f | 1862 | |
38ddf41b JR |
1863 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1864 | << DEV_ENTRY_MODE_SHIFT; | |
07a80a6b | 1865 | pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV; |
b20ac0d4 | 1866 | |
ee6c2868 JR |
1867 | flags = amd_iommu_dev_table[devid].data[1]; |
1868 | ||
fd7b5535 JR |
1869 | if (ats) |
1870 | flags |= DTE_FLAG_IOTLB; | |
1871 | ||
52815b75 | 1872 | if (domain->flags & PD_IOMMUV2_MASK) { |
2543a786 | 1873 | u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl); |
52815b75 JR |
1874 | u64 glx = domain->glx; |
1875 | u64 tmp; | |
1876 | ||
1877 | pte_root |= DTE_FLAG_GV; | |
1878 | pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT; | |
1879 | ||
1880 | /* First mask out possible old values for GCR3 table */ | |
1881 | tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B; | |
1882 | flags &= ~tmp; | |
1883 | ||
1884 | tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C; | |
1885 | flags &= ~tmp; | |
1886 | ||
1887 | /* Encode GCR3 table into DTE */ | |
1888 | tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A; | |
1889 | pte_root |= tmp; | |
1890 | ||
1891 | tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B; | |
1892 | flags |= tmp; | |
1893 | ||
1894 | tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C; | |
1895 | flags |= tmp; | |
1896 | } | |
1897 | ||
45a01c42 | 1898 | flags &= ~DEV_DOMID_MASK; |
ee6c2868 JR |
1899 | flags |= domain->id; |
1900 | ||
c284a37b | 1901 | old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK; |
ee6c2868 JR |
1902 | amd_iommu_dev_table[devid].data[1] = flags; |
1903 | amd_iommu_dev_table[devid].data[0] = pte_root; | |
c284a37b SH |
1904 | |
1905 | /* | |
1906 | * A kdump kernel might be replacing a domain ID that was copied from | |
1907 | * the previous kernel--if so, it needs to flush the translation cache | |
1908 | * entries for the old domain ID that is being overwritten | |
1909 | */ | |
1910 | if (old_domid) { | |
1911 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1912 | ||
1913 | amd_iommu_flush_tlb_domid(iommu, old_domid); | |
1914 | } | |
15898bbc JR |
1915 | } |
1916 | ||
1917 | static void clear_dte_entry(u16 devid) | |
1918 | { | |
15898bbc | 1919 | /* remove entry from the device table seen by the hardware */ |
07a80a6b | 1920 | amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV; |
cbf3ccd0 | 1921 | amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK; |
15898bbc JR |
1922 | |
1923 | amd_iommu_apply_erratum_63(devid); | |
7f760ddd JR |
1924 | } |
1925 | ||
ec9e79ef JR |
1926 | static void do_attach(struct iommu_dev_data *dev_data, |
1927 | struct protection_domain *domain) | |
7f760ddd | 1928 | { |
7f760ddd | 1929 | struct amd_iommu *iommu; |
e25bfb56 | 1930 | u16 alias; |
ec9e79ef | 1931 | bool ats; |
fd7b5535 | 1932 | |
ec9e79ef | 1933 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1934 | alias = dev_data->alias; |
ec9e79ef | 1935 | ats = dev_data->ats.enabled; |
7f760ddd JR |
1936 | |
1937 | /* Update data structures */ | |
1938 | dev_data->domain = domain; | |
1939 | list_add(&dev_data->list, &domain->dev_list); | |
7f760ddd JR |
1940 | |
1941 | /* Do reference counting */ | |
1942 | domain->dev_iommu[iommu->index] += 1; | |
1943 | domain->dev_cnt += 1; | |
1944 | ||
e25bfb56 JR |
1945 | /* Update device table */ |
1946 | set_dte_entry(dev_data->devid, domain, ats); | |
1947 | if (alias != dev_data->devid) | |
9b1a12d2 | 1948 | set_dte_entry(alias, domain, ats); |
e25bfb56 | 1949 | |
6c542047 | 1950 | device_flush_dte(dev_data); |
7f760ddd JR |
1951 | } |
1952 | ||
ec9e79ef | 1953 | static void do_detach(struct iommu_dev_data *dev_data) |
7f760ddd | 1954 | { |
b1211c55 | 1955 | struct protection_domain *domain = dev_data->domain; |
7f760ddd | 1956 | struct amd_iommu *iommu; |
e25bfb56 | 1957 | u16 alias; |
7f760ddd | 1958 | |
5adad991 JR |
1959 | /* |
1960 | * First check if the device is still attached. It might already | |
1961 | * be detached from its domain because the generic | |
1962 | * iommu_detach_group code detached it and we try again here in | |
1963 | * our alias handling. | |
1964 | */ | |
1965 | if (!dev_data->domain) | |
1966 | return; | |
1967 | ||
ec9e79ef | 1968 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
e3156048 | 1969 | alias = dev_data->alias; |
15898bbc | 1970 | |
7f760ddd JR |
1971 | /* Update data structures */ |
1972 | dev_data->domain = NULL; | |
1973 | list_del(&dev_data->list); | |
f62dda66 | 1974 | clear_dte_entry(dev_data->devid); |
e25bfb56 JR |
1975 | if (alias != dev_data->devid) |
1976 | clear_dte_entry(alias); | |
15898bbc | 1977 | |
7f760ddd | 1978 | /* Flush the DTE entry */ |
6c542047 | 1979 | device_flush_dte(dev_data); |
b1211c55 SS |
1980 | |
1981 | /* Flush IOTLB */ | |
1982 | domain_flush_tlb_pde(domain); | |
1983 | ||
1984 | /* Wait for the flushes to finish */ | |
1985 | domain_flush_complete(domain); | |
1986 | ||
1987 | /* decrease reference counters - needs to happen after the flushes */ | |
1988 | domain->dev_iommu[iommu->index] -= 1; | |
1989 | domain->dev_cnt -= 1; | |
2b681faf JR |
1990 | } |
1991 | ||
1992 | /* | |
1993 | * If a device is not yet associated with a domain, this function does | |
1994 | * assigns it visible for the hardware | |
1995 | */ | |
ec9e79ef | 1996 | static int __attach_device(struct iommu_dev_data *dev_data, |
15898bbc | 1997 | struct protection_domain *domain) |
2b681faf | 1998 | { |
84fe6c19 | 1999 | int ret; |
657cbb6b | 2000 | |
272e4f99 JR |
2001 | /* |
2002 | * Must be called with IRQs disabled. Warn here to detect early | |
2003 | * when its not. | |
2004 | */ | |
2005 | WARN_ON(!irqs_disabled()); | |
2006 | ||
2b681faf JR |
2007 | /* lock domain */ |
2008 | spin_lock(&domain->lock); | |
2009 | ||
397111ab | 2010 | ret = -EBUSY; |
150952f9 | 2011 | if (dev_data->domain != NULL) |
397111ab | 2012 | goto out_unlock; |
15898bbc | 2013 | |
397111ab | 2014 | /* Attach alias group root */ |
150952f9 | 2015 | do_attach(dev_data, domain); |
24100055 | 2016 | |
84fe6c19 JL |
2017 | ret = 0; |
2018 | ||
2019 | out_unlock: | |
2020 | ||
eba6ac60 JR |
2021 | /* ready */ |
2022 | spin_unlock(&domain->lock); | |
15898bbc | 2023 | |
84fe6c19 | 2024 | return ret; |
0feae533 | 2025 | } |
b20ac0d4 | 2026 | |
52815b75 JR |
2027 | |
2028 | static void pdev_iommuv2_disable(struct pci_dev *pdev) | |
2029 | { | |
2030 | pci_disable_ats(pdev); | |
2031 | pci_disable_pri(pdev); | |
2032 | pci_disable_pasid(pdev); | |
2033 | } | |
2034 | ||
6a113ddc JR |
2035 | /* FIXME: Change generic reset-function to do the same */ |
2036 | static int pri_reset_while_enabled(struct pci_dev *pdev) | |
2037 | { | |
2038 | u16 control; | |
2039 | int pos; | |
2040 | ||
46277b75 | 2041 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
6a113ddc JR |
2042 | if (!pos) |
2043 | return -EINVAL; | |
2044 | ||
46277b75 JR |
2045 | pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control); |
2046 | control |= PCI_PRI_CTRL_RESET; | |
2047 | pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control); | |
6a113ddc JR |
2048 | |
2049 | return 0; | |
2050 | } | |
2051 | ||
52815b75 JR |
2052 | static int pdev_iommuv2_enable(struct pci_dev *pdev) |
2053 | { | |
6a113ddc JR |
2054 | bool reset_enable; |
2055 | int reqs, ret; | |
2056 | ||
2057 | /* FIXME: Hardcode number of outstanding requests for now */ | |
2058 | reqs = 32; | |
2059 | if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE)) | |
2060 | reqs = 1; | |
2061 | reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET); | |
52815b75 JR |
2062 | |
2063 | /* Only allow access to user-accessible pages */ | |
2064 | ret = pci_enable_pasid(pdev, 0); | |
2065 | if (ret) | |
2066 | goto out_err; | |
2067 | ||
2068 | /* First reset the PRI state of the device */ | |
2069 | ret = pci_reset_pri(pdev); | |
2070 | if (ret) | |
2071 | goto out_err; | |
2072 | ||
6a113ddc JR |
2073 | /* Enable PRI */ |
2074 | ret = pci_enable_pri(pdev, reqs); | |
52815b75 JR |
2075 | if (ret) |
2076 | goto out_err; | |
2077 | ||
6a113ddc JR |
2078 | if (reset_enable) { |
2079 | ret = pri_reset_while_enabled(pdev); | |
2080 | if (ret) | |
2081 | goto out_err; | |
2082 | } | |
2083 | ||
52815b75 JR |
2084 | ret = pci_enable_ats(pdev, PAGE_SHIFT); |
2085 | if (ret) | |
2086 | goto out_err; | |
2087 | ||
2088 | return 0; | |
2089 | ||
2090 | out_err: | |
2091 | pci_disable_pri(pdev); | |
2092 | pci_disable_pasid(pdev); | |
2093 | ||
2094 | return ret; | |
2095 | } | |
2096 | ||
c99afa25 | 2097 | /* FIXME: Move this to PCI code */ |
a3b93121 | 2098 | #define PCI_PRI_TLP_OFF (1 << 15) |
c99afa25 | 2099 | |
98f1ad25 | 2100 | static bool pci_pri_tlp_required(struct pci_dev *pdev) |
c99afa25 | 2101 | { |
a3b93121 | 2102 | u16 status; |
c99afa25 JR |
2103 | int pos; |
2104 | ||
46277b75 | 2105 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); |
c99afa25 JR |
2106 | if (!pos) |
2107 | return false; | |
2108 | ||
a3b93121 | 2109 | pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); |
c99afa25 | 2110 | |
a3b93121 | 2111 | return (status & PCI_PRI_TLP_OFF) ? true : false; |
c99afa25 JR |
2112 | } |
2113 | ||
407d733e | 2114 | /* |
df805abb | 2115 | * If a device is not yet associated with a domain, this function |
407d733e JR |
2116 | * assigns it visible for the hardware |
2117 | */ | |
15898bbc JR |
2118 | static int attach_device(struct device *dev, |
2119 | struct protection_domain *domain) | |
0feae533 | 2120 | { |
2bf9a0a1 | 2121 | struct pci_dev *pdev; |
ea61cddb | 2122 | struct iommu_dev_data *dev_data; |
eba6ac60 | 2123 | unsigned long flags; |
15898bbc | 2124 | int ret; |
eba6ac60 | 2125 | |
ea61cddb JR |
2126 | dev_data = get_dev_data(dev); |
2127 | ||
2bf9a0a1 WZ |
2128 | if (!dev_is_pci(dev)) |
2129 | goto skip_ats_check; | |
2130 | ||
2131 | pdev = to_pci_dev(dev); | |
52815b75 | 2132 | if (domain->flags & PD_IOMMUV2_MASK) { |
02ca2021 | 2133 | if (!dev_data->passthrough) |
52815b75 JR |
2134 | return -EINVAL; |
2135 | ||
02ca2021 JR |
2136 | if (dev_data->iommu_v2) { |
2137 | if (pdev_iommuv2_enable(pdev) != 0) | |
2138 | return -EINVAL; | |
52815b75 | 2139 | |
02ca2021 JR |
2140 | dev_data->ats.enabled = true; |
2141 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2142 | dev_data->pri_tlp = pci_pri_tlp_required(pdev); | |
2143 | } | |
52815b75 JR |
2144 | } else if (amd_iommu_iotlb_sup && |
2145 | pci_enable_ats(pdev, PAGE_SHIFT) == 0) { | |
ea61cddb JR |
2146 | dev_data->ats.enabled = true; |
2147 | dev_data->ats.qdep = pci_ats_queue_depth(pdev); | |
2148 | } | |
fd7b5535 | 2149 | |
2bf9a0a1 | 2150 | skip_ats_check: |
eba6ac60 | 2151 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
ec9e79ef | 2152 | ret = __attach_device(dev_data, domain); |
b20ac0d4 JR |
2153 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
2154 | ||
0feae533 JR |
2155 | /* |
2156 | * We might boot into a crash-kernel here. The crashed kernel | |
2157 | * left the caches in the IOMMU dirty. So we have to flush | |
2158 | * here to evict all dirty stuff. | |
2159 | */ | |
17b124bf | 2160 | domain_flush_tlb_pde(domain); |
15898bbc | 2161 | |
2ef3db92 FS |
2162 | domain_flush_complete(domain); |
2163 | ||
15898bbc | 2164 | return ret; |
b20ac0d4 JR |
2165 | } |
2166 | ||
355bf553 JR |
2167 | /* |
2168 | * Removes a device from a protection domain (unlocked) | |
2169 | */ | |
ec9e79ef | 2170 | static void __detach_device(struct iommu_dev_data *dev_data) |
355bf553 | 2171 | { |
2ca76279 | 2172 | struct protection_domain *domain; |
c4596114 | 2173 | |
272e4f99 JR |
2174 | /* |
2175 | * Must be called with IRQs disabled. Warn here to detect early | |
2176 | * when its not. | |
2177 | */ | |
2178 | WARN_ON(!irqs_disabled()); | |
2ca76279 | 2179 | |
f34c73f5 JR |
2180 | if (WARN_ON(!dev_data->domain)) |
2181 | return; | |
24100055 | 2182 | |
2ca76279 | 2183 | domain = dev_data->domain; |
71f77580 | 2184 | |
f1dd0a8b | 2185 | spin_lock(&domain->lock); |
24100055 | 2186 | |
150952f9 | 2187 | do_detach(dev_data); |
7f760ddd | 2188 | |
f1dd0a8b | 2189 | spin_unlock(&domain->lock); |
355bf553 JR |
2190 | } |
2191 | ||
2192 | /* | |
2193 | * Removes a device from a protection domain (with devtable_lock held) | |
2194 | */ | |
15898bbc | 2195 | static void detach_device(struct device *dev) |
355bf553 | 2196 | { |
52815b75 | 2197 | struct protection_domain *domain; |
ea61cddb | 2198 | struct iommu_dev_data *dev_data; |
355bf553 JR |
2199 | unsigned long flags; |
2200 | ||
ec9e79ef | 2201 | dev_data = get_dev_data(dev); |
52815b75 | 2202 | domain = dev_data->domain; |
ec9e79ef | 2203 | |
355bf553 JR |
2204 | /* lock device table */ |
2205 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
ec9e79ef | 2206 | __detach_device(dev_data); |
355bf553 | 2207 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
fd7b5535 | 2208 | |
2bf9a0a1 WZ |
2209 | if (!dev_is_pci(dev)) |
2210 | return; | |
2211 | ||
02ca2021 | 2212 | if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2) |
52815b75 JR |
2213 | pdev_iommuv2_disable(to_pci_dev(dev)); |
2214 | else if (dev_data->ats.enabled) | |
ea61cddb | 2215 | pci_disable_ats(to_pci_dev(dev)); |
52815b75 JR |
2216 | |
2217 | dev_data->ats.enabled = false; | |
355bf553 | 2218 | } |
e275a2a0 | 2219 | |
aafd8ba0 | 2220 | static int amd_iommu_add_device(struct device *dev) |
e275a2a0 | 2221 | { |
5abcdba4 | 2222 | struct iommu_dev_data *dev_data; |
07ee8694 | 2223 | struct iommu_domain *domain; |
e275a2a0 | 2224 | struct amd_iommu *iommu; |
7aba6cb9 | 2225 | int ret, devid; |
e275a2a0 | 2226 | |
aafd8ba0 | 2227 | if (!check_device(dev) || get_dev_data(dev)) |
98fc5a69 | 2228 | return 0; |
e275a2a0 | 2229 | |
aafd8ba0 | 2230 | devid = get_device_id(dev); |
9ee35e4c | 2231 | if (devid < 0) |
7aba6cb9 WZ |
2232 | return devid; |
2233 | ||
aafd8ba0 | 2234 | iommu = amd_iommu_rlookup_table[devid]; |
657cbb6b | 2235 | |
aafd8ba0 | 2236 | ret = iommu_init_device(dev); |
4d58b8a6 JR |
2237 | if (ret) { |
2238 | if (ret != -ENOTSUPP) | |
2239 | pr_err("Failed to initialize device %s - trying to proceed anyway\n", | |
2240 | dev_name(dev)); | |
657cbb6b | 2241 | |
aafd8ba0 | 2242 | iommu_ignore_device(dev); |
5657933d | 2243 | dev->dma_ops = &nommu_dma_ops; |
aafd8ba0 JR |
2244 | goto out; |
2245 | } | |
2246 | init_iommu_group(dev); | |
2c9195e9 | 2247 | |
07ee8694 | 2248 | dev_data = get_dev_data(dev); |
2c9195e9 | 2249 | |
4d58b8a6 | 2250 | BUG_ON(!dev_data); |
657cbb6b | 2251 | |
1e6a7b04 | 2252 | if (iommu_pass_through || dev_data->iommu_v2) |
07ee8694 | 2253 | iommu_request_dm_for_dev(dev); |
ac1534a5 | 2254 | |
07ee8694 JR |
2255 | /* Domains are initialized for this device - have a look what we ended up with */ |
2256 | domain = iommu_get_domain_for_dev(dev); | |
32302324 | 2257 | if (domain->type == IOMMU_DOMAIN_IDENTITY) |
07ee8694 | 2258 | dev_data->passthrough = true; |
32302324 | 2259 | else |
5657933d | 2260 | dev->dma_ops = &amd_iommu_dma_ops; |
e275a2a0 | 2261 | |
aafd8ba0 | 2262 | out: |
e275a2a0 JR |
2263 | iommu_completion_wait(iommu); |
2264 | ||
e275a2a0 JR |
2265 | return 0; |
2266 | } | |
2267 | ||
aafd8ba0 | 2268 | static void amd_iommu_remove_device(struct device *dev) |
8638c491 | 2269 | { |
aafd8ba0 | 2270 | struct amd_iommu *iommu; |
7aba6cb9 | 2271 | int devid; |
aafd8ba0 JR |
2272 | |
2273 | if (!check_device(dev)) | |
2274 | return; | |
2275 | ||
2276 | devid = get_device_id(dev); | |
9ee35e4c | 2277 | if (devid < 0) |
7aba6cb9 WZ |
2278 | return; |
2279 | ||
aafd8ba0 JR |
2280 | iommu = amd_iommu_rlookup_table[devid]; |
2281 | ||
2282 | iommu_uninit_device(dev); | |
2283 | iommu_completion_wait(iommu); | |
8638c491 JR |
2284 | } |
2285 | ||
b097d11a WZ |
2286 | static struct iommu_group *amd_iommu_device_group(struct device *dev) |
2287 | { | |
2288 | if (dev_is_pci(dev)) | |
2289 | return pci_device_group(dev); | |
2290 | ||
2291 | return acpihid_device_group(dev); | |
2292 | } | |
2293 | ||
431b2a20 JR |
2294 | /***************************************************************************** |
2295 | * | |
2296 | * The next functions belong to the dma_ops mapping/unmapping code. | |
2297 | * | |
2298 | *****************************************************************************/ | |
2299 | ||
2300 | /* | |
2301 | * In the dma_ops path we only have the struct device. This function | |
2302 | * finds the corresponding IOMMU, the protection domain and the | |
2303 | * requestor id for a given device. | |
2304 | * If the device is not yet associated with a domain this is also done | |
2305 | * in this function. | |
2306 | */ | |
94f6d190 | 2307 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 2308 | { |
94f6d190 | 2309 | struct protection_domain *domain; |
df3f7a6e | 2310 | struct iommu_domain *io_domain; |
b20ac0d4 | 2311 | |
f99c0f1c | 2312 | if (!check_device(dev)) |
94f6d190 | 2313 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 2314 | |
d26592a9 | 2315 | domain = get_dev_data(dev)->domain; |
df3f7a6e BH |
2316 | if (domain == NULL && get_dev_data(dev)->defer_attach) { |
2317 | get_dev_data(dev)->defer_attach = false; | |
2318 | io_domain = iommu_get_domain_for_dev(dev); | |
2319 | domain = to_pdomain(io_domain); | |
2320 | attach_device(dev, domain); | |
2321 | } | |
ec62b1ab BH |
2322 | if (domain == NULL) |
2323 | return ERR_PTR(-EBUSY); | |
2324 | ||
0bb6e243 | 2325 | if (!dma_ops_domain(domain)) |
94f6d190 | 2326 | return ERR_PTR(-EBUSY); |
f91ba190 | 2327 | |
0bb6e243 | 2328 | return domain; |
b20ac0d4 JR |
2329 | } |
2330 | ||
04bfdd84 JR |
2331 | static void update_device_table(struct protection_domain *domain) |
2332 | { | |
492667da | 2333 | struct iommu_dev_data *dev_data; |
04bfdd84 | 2334 | |
3254de6b | 2335 | list_for_each_entry(dev_data, &domain->dev_list, list) { |
ea61cddb | 2336 | set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled); |
3254de6b JR |
2337 | |
2338 | if (dev_data->devid == dev_data->alias) | |
2339 | continue; | |
2340 | ||
2341 | /* There is an alias, update device table entry for it */ | |
2342 | set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled); | |
2343 | } | |
04bfdd84 JR |
2344 | } |
2345 | ||
2346 | static void update_domain(struct protection_domain *domain) | |
2347 | { | |
2348 | if (!domain->updated) | |
2349 | return; | |
2350 | ||
2351 | update_device_table(domain); | |
17b124bf JR |
2352 | |
2353 | domain_flush_devices(domain); | |
2354 | domain_flush_tlb_pde(domain); | |
04bfdd84 JR |
2355 | |
2356 | domain->updated = false; | |
2357 | } | |
2358 | ||
f37f7f33 JR |
2359 | static int dir2prot(enum dma_data_direction direction) |
2360 | { | |
2361 | if (direction == DMA_TO_DEVICE) | |
2362 | return IOMMU_PROT_IR; | |
2363 | else if (direction == DMA_FROM_DEVICE) | |
2364 | return IOMMU_PROT_IW; | |
2365 | else if (direction == DMA_BIDIRECTIONAL) | |
2366 | return IOMMU_PROT_IW | IOMMU_PROT_IR; | |
2367 | else | |
2368 | return 0; | |
2369 | } | |
daae2d25 | 2370 | |
431b2a20 JR |
2371 | /* |
2372 | * This function contains common code for mapping of a physically | |
24f81160 JR |
2373 | * contiguous memory region into DMA address space. It is used by all |
2374 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
2375 | * Must be called with the domain lock held. |
2376 | */ | |
cb76c322 | 2377 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
2378 | struct dma_ops_domain *dma_dom, |
2379 | phys_addr_t paddr, | |
2380 | size_t size, | |
f37f7f33 | 2381 | enum dma_data_direction direction, |
832a90c3 | 2382 | u64 dma_mask) |
cb76c322 JR |
2383 | { |
2384 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 2385 | dma_addr_t address, start, ret; |
cb76c322 | 2386 | unsigned int pages; |
518d9b45 | 2387 | int prot = 0; |
cb76c322 JR |
2388 | int i; |
2389 | ||
e3c449f5 | 2390 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
2391 | paddr &= PAGE_MASK; |
2392 | ||
256e4621 | 2393 | address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask); |
a869572c | 2394 | if (address == AMD_IOMMU_MAPPING_ERROR) |
266a3bd2 | 2395 | goto out; |
cb76c322 | 2396 | |
f37f7f33 | 2397 | prot = dir2prot(direction); |
518d9b45 | 2398 | |
cb76c322 JR |
2399 | start = address; |
2400 | for (i = 0; i < pages; ++i) { | |
518d9b45 JR |
2401 | ret = iommu_map_page(&dma_dom->domain, start, paddr, |
2402 | PAGE_SIZE, prot, GFP_ATOMIC); | |
2403 | if (ret) | |
53812c11 JR |
2404 | goto out_unmap; |
2405 | ||
cb76c322 JR |
2406 | paddr += PAGE_SIZE; |
2407 | start += PAGE_SIZE; | |
2408 | } | |
2409 | address += offset; | |
2410 | ||
ab7032bb | 2411 | if (unlikely(amd_iommu_np_cache)) { |
17b124bf | 2412 | domain_flush_pages(&dma_dom->domain, address, size); |
ab7032bb JR |
2413 | domain_flush_complete(&dma_dom->domain); |
2414 | } | |
270cab24 | 2415 | |
cb76c322 JR |
2416 | out: |
2417 | return address; | |
53812c11 JR |
2418 | |
2419 | out_unmap: | |
2420 | ||
2421 | for (--i; i >= 0; --i) { | |
2422 | start -= PAGE_SIZE; | |
518d9b45 | 2423 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
53812c11 JR |
2424 | } |
2425 | ||
256e4621 JR |
2426 | domain_flush_tlb(&dma_dom->domain); |
2427 | domain_flush_complete(&dma_dom->domain); | |
2428 | ||
2429 | dma_ops_free_iova(dma_dom, address, pages); | |
53812c11 | 2430 | |
a869572c | 2431 | return AMD_IOMMU_MAPPING_ERROR; |
cb76c322 JR |
2432 | } |
2433 | ||
431b2a20 JR |
2434 | /* |
2435 | * Does the reverse of the __map_single function. Must be called with | |
2436 | * the domain lock held too | |
2437 | */ | |
cd8c82e8 | 2438 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
2439 | dma_addr_t dma_addr, |
2440 | size_t size, | |
2441 | int dir) | |
2442 | { | |
2443 | dma_addr_t i, start; | |
2444 | unsigned int pages; | |
2445 | ||
e3c449f5 | 2446 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
2447 | dma_addr &= PAGE_MASK; |
2448 | start = dma_addr; | |
2449 | ||
2450 | for (i = 0; i < pages; ++i) { | |
518d9b45 | 2451 | iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE); |
cb76c322 JR |
2452 | start += PAGE_SIZE; |
2453 | } | |
2454 | ||
b1516a14 | 2455 | if (amd_iommu_unmap_flush) { |
b1516a14 JR |
2456 | domain_flush_tlb(&dma_dom->domain); |
2457 | domain_flush_complete(&dma_dom->domain); | |
b7a6615c | 2458 | dma_ops_free_iova(dma_dom, dma_addr, pages); |
b1516a14 | 2459 | } else { |
9003d618 JR |
2460 | pages = __roundup_pow_of_two(pages); |
2461 | queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0); | |
b1516a14 | 2462 | } |
cb76c322 JR |
2463 | } |
2464 | ||
431b2a20 JR |
2465 | /* |
2466 | * The exported map_single function for dma_ops. | |
2467 | */ | |
51491367 FT |
2468 | static dma_addr_t map_page(struct device *dev, struct page *page, |
2469 | unsigned long offset, size_t size, | |
2470 | enum dma_data_direction dir, | |
00085f1e | 2471 | unsigned long attrs) |
4da70b9e | 2472 | { |
92d420ec | 2473 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 2474 | struct protection_domain *domain; |
b3311b06 | 2475 | struct dma_ops_domain *dma_dom; |
832a90c3 | 2476 | u64 dma_mask; |
4da70b9e | 2477 | |
94f6d190 JR |
2478 | domain = get_domain(dev); |
2479 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 2480 | return (dma_addr_t)paddr; |
94f6d190 | 2481 | else if (IS_ERR(domain)) |
a869572c | 2482 | return AMD_IOMMU_MAPPING_ERROR; |
4da70b9e | 2483 | |
f99c0f1c | 2484 | dma_mask = *dev->dma_mask; |
b3311b06 | 2485 | dma_dom = to_dma_ops_domain(domain); |
f99c0f1c | 2486 | |
b3311b06 | 2487 | return __map_single(dev, dma_dom, paddr, size, dir, dma_mask); |
4da70b9e JR |
2488 | } |
2489 | ||
431b2a20 JR |
2490 | /* |
2491 | * The exported unmap_single function for dma_ops. | |
2492 | */ | |
51491367 | 2493 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
00085f1e | 2494 | enum dma_data_direction dir, unsigned long attrs) |
4da70b9e | 2495 | { |
4da70b9e | 2496 | struct protection_domain *domain; |
b3311b06 | 2497 | struct dma_ops_domain *dma_dom; |
4da70b9e | 2498 | |
94f6d190 JR |
2499 | domain = get_domain(dev); |
2500 | if (IS_ERR(domain)) | |
5b28df6f JR |
2501 | return; |
2502 | ||
b3311b06 JR |
2503 | dma_dom = to_dma_ops_domain(domain); |
2504 | ||
2505 | __unmap_single(dma_dom, dma_addr, size, dir); | |
4da70b9e JR |
2506 | } |
2507 | ||
80187fd3 JR |
2508 | static int sg_num_pages(struct device *dev, |
2509 | struct scatterlist *sglist, | |
2510 | int nelems) | |
2511 | { | |
2512 | unsigned long mask, boundary_size; | |
2513 | struct scatterlist *s; | |
2514 | int i, npages = 0; | |
2515 | ||
2516 | mask = dma_get_seg_boundary(dev); | |
2517 | boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT : | |
2518 | 1UL << (BITS_PER_LONG - PAGE_SHIFT); | |
2519 | ||
2520 | for_each_sg(sglist, s, nelems, i) { | |
2521 | int p, n; | |
2522 | ||
2523 | s->dma_address = npages << PAGE_SHIFT; | |
2524 | p = npages % boundary_size; | |
2525 | n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2526 | if (p + n > boundary_size) | |
2527 | npages += boundary_size - p; | |
2528 | npages += n; | |
2529 | } | |
2530 | ||
2531 | return npages; | |
2532 | } | |
2533 | ||
431b2a20 JR |
2534 | /* |
2535 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2536 | * lists). | |
2537 | */ | |
65b050ad | 2538 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
80187fd3 | 2539 | int nelems, enum dma_data_direction direction, |
00085f1e | 2540 | unsigned long attrs) |
65b050ad | 2541 | { |
80187fd3 | 2542 | int mapped_pages = 0, npages = 0, prot = 0, i; |
65b050ad | 2543 | struct protection_domain *domain; |
80187fd3 | 2544 | struct dma_ops_domain *dma_dom; |
65b050ad | 2545 | struct scatterlist *s; |
80187fd3 | 2546 | unsigned long address; |
832a90c3 | 2547 | u64 dma_mask; |
65b050ad | 2548 | |
94f6d190 | 2549 | domain = get_domain(dev); |
a0e191b2 | 2550 | if (IS_ERR(domain)) |
94f6d190 | 2551 | return 0; |
dbcc112e | 2552 | |
b3311b06 | 2553 | dma_dom = to_dma_ops_domain(domain); |
832a90c3 | 2554 | dma_mask = *dev->dma_mask; |
65b050ad | 2555 | |
80187fd3 JR |
2556 | npages = sg_num_pages(dev, sglist, nelems); |
2557 | ||
2558 | address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask); | |
a869572c | 2559 | if (address == AMD_IOMMU_MAPPING_ERROR) |
80187fd3 JR |
2560 | goto out_err; |
2561 | ||
2562 | prot = dir2prot(direction); | |
2563 | ||
2564 | /* Map all sg entries */ | |
65b050ad | 2565 | for_each_sg(sglist, s, nelems, i) { |
80187fd3 JR |
2566 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); |
2567 | ||
2568 | for (j = 0; j < pages; ++j) { | |
2569 | unsigned long bus_addr, phys_addr; | |
2570 | int ret; | |
65b050ad | 2571 | |
80187fd3 JR |
2572 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2573 | phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT); | |
5f4a1e68 QC |
2574 | ret = iommu_map_page(domain, bus_addr, phys_addr, |
2575 | PAGE_SIZE, prot, | |
2576 | GFP_ATOMIC | __GFP_NOWARN); | |
80187fd3 JR |
2577 | if (ret) |
2578 | goto out_unmap; | |
65b050ad | 2579 | |
80187fd3 JR |
2580 | mapped_pages += 1; |
2581 | } | |
65b050ad JR |
2582 | } |
2583 | ||
80187fd3 JR |
2584 | /* Everything is mapped - write the right values into s->dma_address */ |
2585 | for_each_sg(sglist, s, nelems, i) { | |
a2fd1b3d SG |
2586 | /* |
2587 | * Add in the remaining piece of the scatter-gather offset that | |
2588 | * was masked out when we were determining the physical address | |
2589 | * via (sg_phys(s) & PAGE_MASK) earlier. | |
2590 | */ | |
2591 | s->dma_address += address + (s->offset & ~PAGE_MASK); | |
80187fd3 JR |
2592 | s->dma_length = s->length; |
2593 | } | |
2594 | ||
2595 | return nelems; | |
2596 | ||
2597 | out_unmap: | |
2598 | pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n", | |
2599 | dev_name(dev), npages); | |
2600 | ||
2601 | for_each_sg(sglist, s, nelems, i) { | |
2602 | int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE); | |
2603 | ||
2604 | for (j = 0; j < pages; ++j) { | |
2605 | unsigned long bus_addr; | |
92d420ec | 2606 | |
80187fd3 JR |
2607 | bus_addr = address + s->dma_address + (j << PAGE_SHIFT); |
2608 | iommu_unmap_page(domain, bus_addr, PAGE_SIZE); | |
2609 | ||
90b29e60 | 2610 | if (--mapped_pages == 0) |
80187fd3 JR |
2611 | goto out_free_iova; |
2612 | } | |
65b050ad JR |
2613 | } |
2614 | ||
80187fd3 | 2615 | out_free_iova: |
7e50af0c | 2616 | free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages); |
80187fd3 JR |
2617 | |
2618 | out_err: | |
92d420ec | 2619 | return 0; |
65b050ad JR |
2620 | } |
2621 | ||
431b2a20 JR |
2622 | /* |
2623 | * The exported map_sg function for dma_ops (handles scatter-gather | |
2624 | * lists). | |
2625 | */ | |
65b050ad | 2626 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e | 2627 | int nelems, enum dma_data_direction dir, |
00085f1e | 2628 | unsigned long attrs) |
65b050ad | 2629 | { |
65b050ad | 2630 | struct protection_domain *domain; |
b3311b06 | 2631 | struct dma_ops_domain *dma_dom; |
80187fd3 JR |
2632 | unsigned long startaddr; |
2633 | int npages = 2; | |
65b050ad | 2634 | |
94f6d190 JR |
2635 | domain = get_domain(dev); |
2636 | if (IS_ERR(domain)) | |
5b28df6f JR |
2637 | return; |
2638 | ||
80187fd3 | 2639 | startaddr = sg_dma_address(sglist) & PAGE_MASK; |
b3311b06 | 2640 | dma_dom = to_dma_ops_domain(domain); |
80187fd3 JR |
2641 | npages = sg_num_pages(dev, sglist, nelems); |
2642 | ||
b3311b06 | 2643 | __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir); |
65b050ad JR |
2644 | } |
2645 | ||
431b2a20 JR |
2646 | /* |
2647 | * The exported alloc_coherent function for dma_ops. | |
2648 | */ | |
5d8b53cf | 2649 | static void *alloc_coherent(struct device *dev, size_t size, |
baa676fc | 2650 | dma_addr_t *dma_addr, gfp_t flag, |
00085f1e | 2651 | unsigned long attrs) |
5d8b53cf | 2652 | { |
832a90c3 | 2653 | u64 dma_mask = dev->coherent_dma_mask; |
3b839a57 | 2654 | struct protection_domain *domain; |
b3311b06 | 2655 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2656 | struct page *page; |
5d8b53cf | 2657 | |
94f6d190 JR |
2658 | domain = get_domain(dev); |
2659 | if (PTR_ERR(domain) == -EINVAL) { | |
3b839a57 JR |
2660 | page = alloc_pages(flag, get_order(size)); |
2661 | *dma_addr = page_to_phys(page); | |
2662 | return page_address(page); | |
94f6d190 JR |
2663 | } else if (IS_ERR(domain)) |
2664 | return NULL; | |
5d8b53cf | 2665 | |
b3311b06 | 2666 | dma_dom = to_dma_ops_domain(domain); |
3b839a57 | 2667 | size = PAGE_ALIGN(size); |
f99c0f1c JR |
2668 | dma_mask = dev->coherent_dma_mask; |
2669 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2d0ec7a1 | 2670 | flag |= __GFP_ZERO; |
5d8b53cf | 2671 | |
3b839a57 JR |
2672 | page = alloc_pages(flag | __GFP_NOWARN, get_order(size)); |
2673 | if (!page) { | |
d0164adc | 2674 | if (!gfpflags_allow_blocking(flag)) |
3b839a57 | 2675 | return NULL; |
5d8b53cf | 2676 | |
3b839a57 | 2677 | page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT, |
712c604d | 2678 | get_order(size), flag); |
3b839a57 JR |
2679 | if (!page) |
2680 | return NULL; | |
2681 | } | |
5d8b53cf | 2682 | |
832a90c3 JR |
2683 | if (!dma_mask) |
2684 | dma_mask = *dev->dma_mask; | |
2685 | ||
b3311b06 | 2686 | *dma_addr = __map_single(dev, dma_dom, page_to_phys(page), |
bda350db | 2687 | size, DMA_BIDIRECTIONAL, dma_mask); |
5d8b53cf | 2688 | |
a869572c | 2689 | if (*dma_addr == AMD_IOMMU_MAPPING_ERROR) |
5b28df6f | 2690 | goto out_free; |
5d8b53cf | 2691 | |
3b839a57 | 2692 | return page_address(page); |
5b28df6f JR |
2693 | |
2694 | out_free: | |
2695 | ||
3b839a57 JR |
2696 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2697 | __free_pages(page, get_order(size)); | |
5b28df6f JR |
2698 | |
2699 | return NULL; | |
5d8b53cf JR |
2700 | } |
2701 | ||
431b2a20 JR |
2702 | /* |
2703 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2704 | */ |
5d8b53cf | 2705 | static void free_coherent(struct device *dev, size_t size, |
baa676fc | 2706 | void *virt_addr, dma_addr_t dma_addr, |
00085f1e | 2707 | unsigned long attrs) |
5d8b53cf | 2708 | { |
5d8b53cf | 2709 | struct protection_domain *domain; |
b3311b06 | 2710 | struct dma_ops_domain *dma_dom; |
3b839a57 | 2711 | struct page *page; |
5d8b53cf | 2712 | |
3b839a57 JR |
2713 | page = virt_to_page(virt_addr); |
2714 | size = PAGE_ALIGN(size); | |
2715 | ||
94f6d190 JR |
2716 | domain = get_domain(dev); |
2717 | if (IS_ERR(domain)) | |
5b28df6f JR |
2718 | goto free_mem; |
2719 | ||
b3311b06 JR |
2720 | dma_dom = to_dma_ops_domain(domain); |
2721 | ||
2722 | __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 2723 | |
5d8b53cf | 2724 | free_mem: |
3b839a57 JR |
2725 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
2726 | __free_pages(page, get_order(size)); | |
5d8b53cf JR |
2727 | } |
2728 | ||
b39ba6ad JR |
2729 | /* |
2730 | * This function is called by the DMA layer to find out if we can handle a | |
2731 | * particular device. It is part of the dma_ops. | |
2732 | */ | |
2733 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2734 | { | |
5860acc1 CH |
2735 | if (!x86_dma_supported(dev, mask)) |
2736 | return 0; | |
420aef8a | 2737 | return check_device(dev); |
b39ba6ad JR |
2738 | } |
2739 | ||
a869572c CH |
2740 | static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr) |
2741 | { | |
2742 | return dma_addr == AMD_IOMMU_MAPPING_ERROR; | |
2743 | } | |
2744 | ||
5299709d | 2745 | static const struct dma_map_ops amd_iommu_dma_ops = { |
a639a8ee JR |
2746 | .alloc = alloc_coherent, |
2747 | .free = free_coherent, | |
2748 | .map_page = map_page, | |
2749 | .unmap_page = unmap_page, | |
2750 | .map_sg = map_sg, | |
2751 | .unmap_sg = unmap_sg, | |
2752 | .dma_supported = amd_iommu_dma_supported, | |
a869572c | 2753 | .mapping_error = amd_iommu_mapping_error, |
6631ee9d JR |
2754 | }; |
2755 | ||
81cd07b9 JR |
2756 | static int init_reserved_iova_ranges(void) |
2757 | { | |
2758 | struct pci_dev *pdev = NULL; | |
2759 | struct iova *val; | |
2760 | ||
aa3ac946 | 2761 | init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN); |
81cd07b9 JR |
2762 | |
2763 | lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock, | |
2764 | &reserved_rbtree_key); | |
2765 | ||
2766 | /* MSI memory range */ | |
2767 | val = reserve_iova(&reserved_iova_ranges, | |
2768 | IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END)); | |
2769 | if (!val) { | |
2770 | pr_err("Reserving MSI range failed\n"); | |
2771 | return -ENOMEM; | |
2772 | } | |
2773 | ||
2774 | /* HT memory range */ | |
2775 | val = reserve_iova(&reserved_iova_ranges, | |
2776 | IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END)); | |
2777 | if (!val) { | |
2778 | pr_err("Reserving HT range failed\n"); | |
2779 | return -ENOMEM; | |
2780 | } | |
2781 | ||
2782 | /* | |
2783 | * Memory used for PCI resources | |
2784 | * FIXME: Check whether we can reserve the PCI-hole completly | |
2785 | */ | |
2786 | for_each_pci_dev(pdev) { | |
2787 | int i; | |
2788 | ||
2789 | for (i = 0; i < PCI_NUM_RESOURCES; ++i) { | |
2790 | struct resource *r = &pdev->resource[i]; | |
2791 | ||
2792 | if (!(r->flags & IORESOURCE_MEM)) | |
2793 | continue; | |
2794 | ||
2795 | val = reserve_iova(&reserved_iova_ranges, | |
2796 | IOVA_PFN(r->start), | |
2797 | IOVA_PFN(r->end)); | |
2798 | if (!val) { | |
2799 | pr_err("Reserve pci-resource range failed\n"); | |
2800 | return -ENOMEM; | |
2801 | } | |
2802 | } | |
2803 | } | |
2804 | ||
2805 | return 0; | |
2806 | } | |
2807 | ||
3a18404c | 2808 | int __init amd_iommu_init_api(void) |
27c2127a | 2809 | { |
460c26d0 | 2810 | int ret, err = 0; |
307d5851 JR |
2811 | |
2812 | ret = iova_cache_get(); | |
2813 | if (ret) | |
2814 | return ret; | |
9a4d3bf5 | 2815 | |
81cd07b9 JR |
2816 | ret = init_reserved_iova_ranges(); |
2817 | if (ret) | |
2818 | return ret; | |
2819 | ||
9a4d3bf5 WZ |
2820 | err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops); |
2821 | if (err) | |
2822 | return err; | |
2823 | #ifdef CONFIG_ARM_AMBA | |
2824 | err = bus_set_iommu(&amba_bustype, &amd_iommu_ops); | |
2825 | if (err) | |
2826 | return err; | |
2827 | #endif | |
0076cd3d WZ |
2828 | err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops); |
2829 | if (err) | |
2830 | return err; | |
c5b5da9c | 2831 | |
460c26d0 | 2832 | return 0; |
f5325094 JR |
2833 | } |
2834 | ||
6631ee9d JR |
2835 | int __init amd_iommu_init_dma_ops(void) |
2836 | { | |
aba2d9a6 | 2837 | swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0; |
6631ee9d | 2838 | iommu_detected = 1; |
6631ee9d | 2839 | |
52717828 JR |
2840 | /* |
2841 | * In case we don't initialize SWIOTLB (actually the common case | |
aba2d9a6 TL |
2842 | * when AMD IOMMU is enabled and SME is not active), make sure there |
2843 | * are global dma_ops set as a fall-back for devices not handled by | |
2844 | * this driver (for example non-PCI devices). When SME is active, | |
2845 | * make sure that swiotlb variable remains set so the global dma_ops | |
2846 | * continue to be SWIOTLB. | |
52717828 JR |
2847 | */ |
2848 | if (!swiotlb) | |
2849 | dma_ops = &nommu_dma_ops; | |
2850 | ||
62410eeb JR |
2851 | if (amd_iommu_unmap_flush) |
2852 | pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n"); | |
2853 | else | |
2854 | pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n"); | |
2855 | ||
6631ee9d | 2856 | return 0; |
c5b5da9c | 2857 | |
6631ee9d | 2858 | } |
6d98cd80 JR |
2859 | |
2860 | /***************************************************************************** | |
2861 | * | |
2862 | * The following functions belong to the exported interface of AMD IOMMU | |
2863 | * | |
2864 | * This interface allows access to lower level functions of the IOMMU | |
2865 | * like protection domain handling and assignement of devices to domains | |
2866 | * which is not possible with the dma_ops interface. | |
2867 | * | |
2868 | *****************************************************************************/ | |
2869 | ||
6d98cd80 JR |
2870 | static void cleanup_domain(struct protection_domain *domain) |
2871 | { | |
9b29d3c6 | 2872 | struct iommu_dev_data *entry; |
6d98cd80 | 2873 | unsigned long flags; |
6d98cd80 JR |
2874 | |
2875 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2876 | ||
9b29d3c6 JR |
2877 | while (!list_empty(&domain->dev_list)) { |
2878 | entry = list_first_entry(&domain->dev_list, | |
2879 | struct iommu_dev_data, list); | |
2880 | __detach_device(entry); | |
492667da | 2881 | } |
6d98cd80 JR |
2882 | |
2883 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2884 | } | |
2885 | ||
2650815f JR |
2886 | static void protection_domain_free(struct protection_domain *domain) |
2887 | { | |
2888 | if (!domain) | |
2889 | return; | |
2890 | ||
aeb26f55 JR |
2891 | del_domain_from_list(domain); |
2892 | ||
2650815f JR |
2893 | if (domain->id) |
2894 | domain_id_free(domain->id); | |
2895 | ||
2896 | kfree(domain); | |
2897 | } | |
2898 | ||
7a5a566e JR |
2899 | static int protection_domain_init(struct protection_domain *domain) |
2900 | { | |
2901 | spin_lock_init(&domain->lock); | |
2902 | mutex_init(&domain->api_lock); | |
2903 | domain->id = domain_id_alloc(); | |
2904 | if (!domain->id) | |
2905 | return -ENOMEM; | |
2906 | INIT_LIST_HEAD(&domain->dev_list); | |
2907 | ||
2908 | return 0; | |
2909 | } | |
2910 | ||
2650815f | 2911 | static struct protection_domain *protection_domain_alloc(void) |
c156e347 JR |
2912 | { |
2913 | struct protection_domain *domain; | |
2914 | ||
2915 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2916 | if (!domain) | |
2650815f | 2917 | return NULL; |
c156e347 | 2918 | |
7a5a566e | 2919 | if (protection_domain_init(domain)) |
2650815f JR |
2920 | goto out_err; |
2921 | ||
aeb26f55 JR |
2922 | add_domain_to_list(domain); |
2923 | ||
2650815f JR |
2924 | return domain; |
2925 | ||
2926 | out_err: | |
2927 | kfree(domain); | |
2928 | ||
2929 | return NULL; | |
2930 | } | |
2931 | ||
3f4b87b9 | 2932 | static struct iommu_domain *amd_iommu_domain_alloc(unsigned type) |
2650815f | 2933 | { |
3f4b87b9 | 2934 | struct protection_domain *pdomain; |
0bb6e243 | 2935 | struct dma_ops_domain *dma_domain; |
2650815f | 2936 | |
0bb6e243 JR |
2937 | switch (type) { |
2938 | case IOMMU_DOMAIN_UNMANAGED: | |
2939 | pdomain = protection_domain_alloc(); | |
2940 | if (!pdomain) | |
2941 | return NULL; | |
c156e347 | 2942 | |
0bb6e243 JR |
2943 | pdomain->mode = PAGE_MODE_3_LEVEL; |
2944 | pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2945 | if (!pdomain->pt_root) { | |
2946 | protection_domain_free(pdomain); | |
2947 | return NULL; | |
2948 | } | |
c156e347 | 2949 | |
0bb6e243 JR |
2950 | pdomain->domain.geometry.aperture_start = 0; |
2951 | pdomain->domain.geometry.aperture_end = ~0ULL; | |
2952 | pdomain->domain.geometry.force_aperture = true; | |
0ff64f80 | 2953 | |
0bb6e243 JR |
2954 | break; |
2955 | case IOMMU_DOMAIN_DMA: | |
2956 | dma_domain = dma_ops_domain_alloc(); | |
2957 | if (!dma_domain) { | |
2958 | pr_err("AMD-Vi: Failed to allocate\n"); | |
2959 | return NULL; | |
2960 | } | |
2961 | pdomain = &dma_domain->domain; | |
2962 | break; | |
07f643a3 JR |
2963 | case IOMMU_DOMAIN_IDENTITY: |
2964 | pdomain = protection_domain_alloc(); | |
2965 | if (!pdomain) | |
2966 | return NULL; | |
c156e347 | 2967 | |
07f643a3 JR |
2968 | pdomain->mode = PAGE_MODE_NONE; |
2969 | break; | |
0bb6e243 JR |
2970 | default: |
2971 | return NULL; | |
2972 | } | |
c156e347 | 2973 | |
3f4b87b9 | 2974 | return &pdomain->domain; |
c156e347 JR |
2975 | } |
2976 | ||
3f4b87b9 | 2977 | static void amd_iommu_domain_free(struct iommu_domain *dom) |
98383fc3 | 2978 | { |
3f4b87b9 | 2979 | struct protection_domain *domain; |
cda7005b | 2980 | struct dma_ops_domain *dma_dom; |
98383fc3 | 2981 | |
3f4b87b9 JR |
2982 | domain = to_pdomain(dom); |
2983 | ||
98383fc3 JR |
2984 | if (domain->dev_cnt > 0) |
2985 | cleanup_domain(domain); | |
2986 | ||
2987 | BUG_ON(domain->dev_cnt != 0); | |
2988 | ||
cda7005b JR |
2989 | if (!dom) |
2990 | return; | |
98383fc3 | 2991 | |
cda7005b JR |
2992 | switch (dom->type) { |
2993 | case IOMMU_DOMAIN_DMA: | |
281e8ccb | 2994 | /* Now release the domain */ |
b3311b06 | 2995 | dma_dom = to_dma_ops_domain(domain); |
cda7005b JR |
2996 | dma_ops_domain_free(dma_dom); |
2997 | break; | |
2998 | default: | |
2999 | if (domain->mode != PAGE_MODE_NONE) | |
3000 | free_pagetable(domain); | |
52815b75 | 3001 | |
cda7005b JR |
3002 | if (domain->flags & PD_IOMMUV2_MASK) |
3003 | free_gcr3_table(domain); | |
3004 | ||
3005 | protection_domain_free(domain); | |
3006 | break; | |
3007 | } | |
98383fc3 JR |
3008 | } |
3009 | ||
684f2888 JR |
3010 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
3011 | struct device *dev) | |
3012 | { | |
657cbb6b | 3013 | struct iommu_dev_data *dev_data = dev->archdata.iommu; |
684f2888 | 3014 | struct amd_iommu *iommu; |
7aba6cb9 | 3015 | int devid; |
684f2888 | 3016 | |
98fc5a69 | 3017 | if (!check_device(dev)) |
684f2888 JR |
3018 | return; |
3019 | ||
98fc5a69 | 3020 | devid = get_device_id(dev); |
9ee35e4c | 3021 | if (devid < 0) |
7aba6cb9 | 3022 | return; |
684f2888 | 3023 | |
657cbb6b | 3024 | if (dev_data->domain != NULL) |
15898bbc | 3025 | detach_device(dev); |
684f2888 JR |
3026 | |
3027 | iommu = amd_iommu_rlookup_table[devid]; | |
3028 | if (!iommu) | |
3029 | return; | |
3030 | ||
d98de49a SS |
3031 | #ifdef CONFIG_IRQ_REMAP |
3032 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && | |
3033 | (dom->type == IOMMU_DOMAIN_UNMANAGED)) | |
3034 | dev_data->use_vapic = 0; | |
3035 | #endif | |
3036 | ||
684f2888 JR |
3037 | iommu_completion_wait(iommu); |
3038 | } | |
3039 | ||
01106066 JR |
3040 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
3041 | struct device *dev) | |
3042 | { | |
3f4b87b9 | 3043 | struct protection_domain *domain = to_pdomain(dom); |
657cbb6b | 3044 | struct iommu_dev_data *dev_data; |
01106066 | 3045 | struct amd_iommu *iommu; |
15898bbc | 3046 | int ret; |
01106066 | 3047 | |
98fc5a69 | 3048 | if (!check_device(dev)) |
01106066 JR |
3049 | return -EINVAL; |
3050 | ||
657cbb6b JR |
3051 | dev_data = dev->archdata.iommu; |
3052 | ||
f62dda66 | 3053 | iommu = amd_iommu_rlookup_table[dev_data->devid]; |
01106066 JR |
3054 | if (!iommu) |
3055 | return -EINVAL; | |
3056 | ||
657cbb6b | 3057 | if (dev_data->domain) |
15898bbc | 3058 | detach_device(dev); |
01106066 | 3059 | |
15898bbc | 3060 | ret = attach_device(dev, domain); |
01106066 | 3061 | |
d98de49a SS |
3062 | #ifdef CONFIG_IRQ_REMAP |
3063 | if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
3064 | if (dom->type == IOMMU_DOMAIN_UNMANAGED) | |
3065 | dev_data->use_vapic = 1; | |
3066 | else | |
3067 | dev_data->use_vapic = 0; | |
3068 | } | |
3069 | #endif | |
3070 | ||
01106066 JR |
3071 | iommu_completion_wait(iommu); |
3072 | ||
15898bbc | 3073 | return ret; |
01106066 JR |
3074 | } |
3075 | ||
468e2366 | 3076 | static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova, |
5009065d | 3077 | phys_addr_t paddr, size_t page_size, int iommu_prot) |
c6229ca6 | 3078 | { |
3f4b87b9 | 3079 | struct protection_domain *domain = to_pdomain(dom); |
c6229ca6 JR |
3080 | int prot = 0; |
3081 | int ret; | |
3082 | ||
132bd68f JR |
3083 | if (domain->mode == PAGE_MODE_NONE) |
3084 | return -EINVAL; | |
3085 | ||
c6229ca6 JR |
3086 | if (iommu_prot & IOMMU_READ) |
3087 | prot |= IOMMU_PROT_IR; | |
3088 | if (iommu_prot & IOMMU_WRITE) | |
3089 | prot |= IOMMU_PROT_IW; | |
3090 | ||
5d214fe6 | 3091 | mutex_lock(&domain->api_lock); |
b911b89b | 3092 | ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL); |
5d214fe6 JR |
3093 | mutex_unlock(&domain->api_lock); |
3094 | ||
795e74f7 | 3095 | return ret; |
c6229ca6 JR |
3096 | } |
3097 | ||
5009065d OBC |
3098 | static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, |
3099 | size_t page_size) | |
eb74ff6c | 3100 | { |
3f4b87b9 | 3101 | struct protection_domain *domain = to_pdomain(dom); |
5009065d | 3102 | size_t unmap_size; |
eb74ff6c | 3103 | |
132bd68f JR |
3104 | if (domain->mode == PAGE_MODE_NONE) |
3105 | return -EINVAL; | |
3106 | ||
5d214fe6 | 3107 | mutex_lock(&domain->api_lock); |
468e2366 | 3108 | unmap_size = iommu_unmap_page(domain, iova, page_size); |
795e74f7 | 3109 | mutex_unlock(&domain->api_lock); |
eb74ff6c | 3110 | |
17b124bf | 3111 | domain_flush_tlb_pde(domain); |
ce76353f | 3112 | domain_flush_complete(domain); |
5d214fe6 | 3113 | |
5009065d | 3114 | return unmap_size; |
eb74ff6c JR |
3115 | } |
3116 | ||
645c4c8d | 3117 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
bb5547ac | 3118 | dma_addr_t iova) |
645c4c8d | 3119 | { |
3f4b87b9 | 3120 | struct protection_domain *domain = to_pdomain(dom); |
3039ca1b | 3121 | unsigned long offset_mask, pte_pgsize; |
f03152bb | 3122 | u64 *pte, __pte; |
645c4c8d | 3123 | |
132bd68f JR |
3124 | if (domain->mode == PAGE_MODE_NONE) |
3125 | return iova; | |
3126 | ||
3039ca1b | 3127 | pte = fetch_pte(domain, iova, &pte_pgsize); |
645c4c8d | 3128 | |
a6d41a40 | 3129 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
3130 | return 0; |
3131 | ||
b24b1b63 | 3132 | offset_mask = pte_pgsize - 1; |
3011ca5d | 3133 | __pte = __sme_clr(*pte & PM_ADDR_MASK); |
645c4c8d | 3134 | |
b24b1b63 | 3135 | return (__pte & ~offset_mask) | (iova & offset_mask); |
645c4c8d JR |
3136 | } |
3137 | ||
ab636481 | 3138 | static bool amd_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 3139 | { |
80a506b8 JR |
3140 | switch (cap) { |
3141 | case IOMMU_CAP_CACHE_COHERENCY: | |
ab636481 | 3142 | return true; |
bdddadcb | 3143 | case IOMMU_CAP_INTR_REMAP: |
ab636481 | 3144 | return (irq_remapping_enabled == 1); |
cfdeec22 WD |
3145 | case IOMMU_CAP_NOEXEC: |
3146 | return false; | |
80a506b8 JR |
3147 | } |
3148 | ||
ab636481 | 3149 | return false; |
dbb9fd86 SY |
3150 | } |
3151 | ||
e5b5234a EA |
3152 | static void amd_iommu_get_resv_regions(struct device *dev, |
3153 | struct list_head *head) | |
35cf248f | 3154 | { |
4397f32c | 3155 | struct iommu_resv_region *region; |
35cf248f | 3156 | struct unity_map_entry *entry; |
7aba6cb9 | 3157 | int devid; |
35cf248f JR |
3158 | |
3159 | devid = get_device_id(dev); | |
9ee35e4c | 3160 | if (devid < 0) |
7aba6cb9 | 3161 | return; |
35cf248f JR |
3162 | |
3163 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
e6cc483d | 3164 | int type, prot = 0; |
4397f32c | 3165 | size_t length; |
35cf248f JR |
3166 | |
3167 | if (devid < entry->devid_start || devid > entry->devid_end) | |
3168 | continue; | |
3169 | ||
e6cc483d | 3170 | type = IOMMU_RESV_DIRECT; |
4397f32c EA |
3171 | length = entry->address_end - entry->address_start; |
3172 | if (entry->prot & IOMMU_PROT_IR) | |
3173 | prot |= IOMMU_READ; | |
3174 | if (entry->prot & IOMMU_PROT_IW) | |
3175 | prot |= IOMMU_WRITE; | |
e6cc483d JR |
3176 | if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE) |
3177 | /* Exclusion range */ | |
3178 | type = IOMMU_RESV_RESERVED; | |
4397f32c EA |
3179 | |
3180 | region = iommu_alloc_resv_region(entry->address_start, | |
e6cc483d | 3181 | length, prot, type); |
35cf248f JR |
3182 | if (!region) { |
3183 | pr_err("Out of memory allocating dm-regions for %s\n", | |
3184 | dev_name(dev)); | |
3185 | return; | |
3186 | } | |
35cf248f JR |
3187 | list_add_tail(®ion->list, head); |
3188 | } | |
4397f32c EA |
3189 | |
3190 | region = iommu_alloc_resv_region(MSI_RANGE_START, | |
3191 | MSI_RANGE_END - MSI_RANGE_START + 1, | |
9d3a4de4 | 3192 | 0, IOMMU_RESV_MSI); |
4397f32c EA |
3193 | if (!region) |
3194 | return; | |
3195 | list_add_tail(®ion->list, head); | |
3196 | ||
3197 | region = iommu_alloc_resv_region(HT_RANGE_START, | |
3198 | HT_RANGE_END - HT_RANGE_START + 1, | |
3199 | 0, IOMMU_RESV_RESERVED); | |
3200 | if (!region) | |
3201 | return; | |
3202 | list_add_tail(®ion->list, head); | |
35cf248f JR |
3203 | } |
3204 | ||
e5b5234a | 3205 | static void amd_iommu_put_resv_regions(struct device *dev, |
35cf248f JR |
3206 | struct list_head *head) |
3207 | { | |
e5b5234a | 3208 | struct iommu_resv_region *entry, *next; |
35cf248f JR |
3209 | |
3210 | list_for_each_entry_safe(entry, next, head, list) | |
3211 | kfree(entry); | |
3212 | } | |
3213 | ||
e5b5234a | 3214 | static void amd_iommu_apply_resv_region(struct device *dev, |
8d54d6c8 | 3215 | struct iommu_domain *domain, |
e5b5234a | 3216 | struct iommu_resv_region *region) |
8d54d6c8 | 3217 | { |
b3311b06 | 3218 | struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain)); |
8d54d6c8 JR |
3219 | unsigned long start, end; |
3220 | ||
3221 | start = IOVA_PFN(region->start); | |
b92b4fb5 | 3222 | end = IOVA_PFN(region->start + region->length - 1); |
8d54d6c8 JR |
3223 | |
3224 | WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); | |
3225 | } | |
3226 | ||
df3f7a6e BH |
3227 | static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain, |
3228 | struct device *dev) | |
3229 | { | |
3230 | struct iommu_dev_data *dev_data = dev->archdata.iommu; | |
3231 | return dev_data->defer_attach; | |
3232 | } | |
3233 | ||
b0119e87 | 3234 | const struct iommu_ops amd_iommu_ops = { |
ab636481 | 3235 | .capable = amd_iommu_capable, |
3f4b87b9 JR |
3236 | .domain_alloc = amd_iommu_domain_alloc, |
3237 | .domain_free = amd_iommu_domain_free, | |
26961efe JR |
3238 | .attach_dev = amd_iommu_attach_device, |
3239 | .detach_dev = amd_iommu_detach_device, | |
468e2366 JR |
3240 | .map = amd_iommu_map, |
3241 | .unmap = amd_iommu_unmap, | |
315786eb | 3242 | .map_sg = default_iommu_map_sg, |
26961efe | 3243 | .iova_to_phys = amd_iommu_iova_to_phys, |
aafd8ba0 JR |
3244 | .add_device = amd_iommu_add_device, |
3245 | .remove_device = amd_iommu_remove_device, | |
b097d11a | 3246 | .device_group = amd_iommu_device_group, |
e5b5234a EA |
3247 | .get_resv_regions = amd_iommu_get_resv_regions, |
3248 | .put_resv_regions = amd_iommu_put_resv_regions, | |
3249 | .apply_resv_region = amd_iommu_apply_resv_region, | |
df3f7a6e | 3250 | .is_attach_deferred = amd_iommu_is_attach_deferred, |
aa3de9c0 | 3251 | .pgsize_bitmap = AMD_IOMMU_PGSIZES, |
26961efe JR |
3252 | }; |
3253 | ||
0feae533 JR |
3254 | /***************************************************************************** |
3255 | * | |
3256 | * The next functions do a basic initialization of IOMMU for pass through | |
3257 | * mode | |
3258 | * | |
3259 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
3260 | * DMA-API translation. | |
3261 | * | |
3262 | *****************************************************************************/ | |
3263 | ||
72e1dcc4 JR |
3264 | /* IOMMUv2 specific functions */ |
3265 | int amd_iommu_register_ppr_notifier(struct notifier_block *nb) | |
3266 | { | |
3267 | return atomic_notifier_chain_register(&ppr_notifier, nb); | |
3268 | } | |
3269 | EXPORT_SYMBOL(amd_iommu_register_ppr_notifier); | |
3270 | ||
3271 | int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb) | |
3272 | { | |
3273 | return atomic_notifier_chain_unregister(&ppr_notifier, nb); | |
3274 | } | |
3275 | EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier); | |
132bd68f JR |
3276 | |
3277 | void amd_iommu_domain_direct_map(struct iommu_domain *dom) | |
3278 | { | |
3f4b87b9 | 3279 | struct protection_domain *domain = to_pdomain(dom); |
132bd68f JR |
3280 | unsigned long flags; |
3281 | ||
3282 | spin_lock_irqsave(&domain->lock, flags); | |
3283 | ||
3284 | /* Update data structure */ | |
3285 | domain->mode = PAGE_MODE_NONE; | |
3286 | domain->updated = true; | |
3287 | ||
3288 | /* Make changes visible to IOMMUs */ | |
3289 | update_domain(domain); | |
3290 | ||
3291 | /* Page-table is not visible to IOMMU anymore, so free it */ | |
3292 | free_pagetable(domain); | |
3293 | ||
3294 | spin_unlock_irqrestore(&domain->lock, flags); | |
3295 | } | |
3296 | EXPORT_SYMBOL(amd_iommu_domain_direct_map); | |
52815b75 JR |
3297 | |
3298 | int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids) | |
3299 | { | |
3f4b87b9 | 3300 | struct protection_domain *domain = to_pdomain(dom); |
52815b75 JR |
3301 | unsigned long flags; |
3302 | int levels, ret; | |
3303 | ||
3304 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
3305 | return -EINVAL; | |
3306 | ||
3307 | /* Number of GCR3 table levels required */ | |
3308 | for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9) | |
3309 | levels += 1; | |
3310 | ||
3311 | if (levels > amd_iommu_max_glx_val) | |
3312 | return -EINVAL; | |
3313 | ||
3314 | spin_lock_irqsave(&domain->lock, flags); | |
3315 | ||
3316 | /* | |
3317 | * Save us all sanity checks whether devices already in the | |
3318 | * domain support IOMMUv2. Just force that the domain has no | |
3319 | * devices attached when it is switched into IOMMUv2 mode. | |
3320 | */ | |
3321 | ret = -EBUSY; | |
3322 | if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK) | |
3323 | goto out; | |
3324 | ||
3325 | ret = -ENOMEM; | |
3326 | domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC); | |
3327 | if (domain->gcr3_tbl == NULL) | |
3328 | goto out; | |
3329 | ||
3330 | domain->glx = levels; | |
3331 | domain->flags |= PD_IOMMUV2_MASK; | |
3332 | domain->updated = true; | |
3333 | ||
3334 | update_domain(domain); | |
3335 | ||
3336 | ret = 0; | |
3337 | ||
3338 | out: | |
3339 | spin_unlock_irqrestore(&domain->lock, flags); | |
3340 | ||
3341 | return ret; | |
3342 | } | |
3343 | EXPORT_SYMBOL(amd_iommu_domain_enable_v2); | |
22e266c7 JR |
3344 | |
3345 | static int __flush_pasid(struct protection_domain *domain, int pasid, | |
3346 | u64 address, bool size) | |
3347 | { | |
3348 | struct iommu_dev_data *dev_data; | |
3349 | struct iommu_cmd cmd; | |
3350 | int i, ret; | |
3351 | ||
3352 | if (!(domain->flags & PD_IOMMUV2_MASK)) | |
3353 | return -EINVAL; | |
3354 | ||
3355 | build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size); | |
3356 | ||
3357 | /* | |
3358 | * IOMMU TLB needs to be flushed before Device TLB to | |
3359 | * prevent device TLB refill from IOMMU TLB | |
3360 | */ | |
6b9376e3 | 3361 | for (i = 0; i < amd_iommu_get_num_iommus(); ++i) { |
22e266c7 JR |
3362 | if (domain->dev_iommu[i] == 0) |
3363 | continue; | |
3364 | ||
3365 | ret = iommu_queue_command(amd_iommus[i], &cmd); | |
3366 | if (ret != 0) | |
3367 | goto out; | |
3368 | } | |
3369 | ||
3370 | /* Wait until IOMMU TLB flushes are complete */ | |
3371 | domain_flush_complete(domain); | |
3372 | ||
3373 | /* Now flush device TLBs */ | |
3374 | list_for_each_entry(dev_data, &domain->dev_list, list) { | |
3375 | struct amd_iommu *iommu; | |
3376 | int qdep; | |
3377 | ||
1c1cc454 JR |
3378 | /* |
3379 | There might be non-IOMMUv2 capable devices in an IOMMUv2 | |
3380 | * domain. | |
3381 | */ | |
3382 | if (!dev_data->ats.enabled) | |
3383 | continue; | |
22e266c7 JR |
3384 | |
3385 | qdep = dev_data->ats.qdep; | |
3386 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3387 | ||
3388 | build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid, | |
3389 | qdep, address, size); | |
3390 | ||
3391 | ret = iommu_queue_command(iommu, &cmd); | |
3392 | if (ret != 0) | |
3393 | goto out; | |
3394 | } | |
3395 | ||
3396 | /* Wait until all device TLBs are flushed */ | |
3397 | domain_flush_complete(domain); | |
3398 | ||
3399 | ret = 0; | |
3400 | ||
3401 | out: | |
3402 | ||
3403 | return ret; | |
3404 | } | |
3405 | ||
3406 | static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid, | |
3407 | u64 address) | |
3408 | { | |
3409 | return __flush_pasid(domain, pasid, address, false); | |
3410 | } | |
3411 | ||
3412 | int amd_iommu_flush_page(struct iommu_domain *dom, int pasid, | |
3413 | u64 address) | |
3414 | { | |
3f4b87b9 | 3415 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3416 | unsigned long flags; |
3417 | int ret; | |
3418 | ||
3419 | spin_lock_irqsave(&domain->lock, flags); | |
3420 | ret = __amd_iommu_flush_page(domain, pasid, address); | |
3421 | spin_unlock_irqrestore(&domain->lock, flags); | |
3422 | ||
3423 | return ret; | |
3424 | } | |
3425 | EXPORT_SYMBOL(amd_iommu_flush_page); | |
3426 | ||
3427 | static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid) | |
3428 | { | |
3429 | return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, | |
3430 | true); | |
3431 | } | |
3432 | ||
3433 | int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid) | |
3434 | { | |
3f4b87b9 | 3435 | struct protection_domain *domain = to_pdomain(dom); |
22e266c7 JR |
3436 | unsigned long flags; |
3437 | int ret; | |
3438 | ||
3439 | spin_lock_irqsave(&domain->lock, flags); | |
3440 | ret = __amd_iommu_flush_tlb(domain, pasid); | |
3441 | spin_unlock_irqrestore(&domain->lock, flags); | |
3442 | ||
3443 | return ret; | |
3444 | } | |
3445 | EXPORT_SYMBOL(amd_iommu_flush_tlb); | |
3446 | ||
b16137b1 JR |
3447 | static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc) |
3448 | { | |
3449 | int index; | |
3450 | u64 *pte; | |
3451 | ||
3452 | while (true) { | |
3453 | ||
3454 | index = (pasid >> (9 * level)) & 0x1ff; | |
3455 | pte = &root[index]; | |
3456 | ||
3457 | if (level == 0) | |
3458 | break; | |
3459 | ||
3460 | if (!(*pte & GCR3_VALID)) { | |
3461 | if (!alloc) | |
3462 | return NULL; | |
3463 | ||
3464 | root = (void *)get_zeroed_page(GFP_ATOMIC); | |
3465 | if (root == NULL) | |
3466 | return NULL; | |
3467 | ||
2543a786 | 3468 | *pte = iommu_virt_to_phys(root) | GCR3_VALID; |
b16137b1 JR |
3469 | } |
3470 | ||
2543a786 | 3471 | root = iommu_phys_to_virt(*pte & PAGE_MASK); |
b16137b1 JR |
3472 | |
3473 | level -= 1; | |
3474 | } | |
3475 | ||
3476 | return pte; | |
3477 | } | |
3478 | ||
3479 | static int __set_gcr3(struct protection_domain *domain, int pasid, | |
3480 | unsigned long cr3) | |
3481 | { | |
3482 | u64 *pte; | |
3483 | ||
3484 | if (domain->mode != PAGE_MODE_NONE) | |
3485 | return -EINVAL; | |
3486 | ||
3487 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true); | |
3488 | if (pte == NULL) | |
3489 | return -ENOMEM; | |
3490 | ||
3491 | *pte = (cr3 & PAGE_MASK) | GCR3_VALID; | |
3492 | ||
3493 | return __amd_iommu_flush_tlb(domain, pasid); | |
3494 | } | |
3495 | ||
3496 | static int __clear_gcr3(struct protection_domain *domain, int pasid) | |
3497 | { | |
3498 | u64 *pte; | |
3499 | ||
3500 | if (domain->mode != PAGE_MODE_NONE) | |
3501 | return -EINVAL; | |
3502 | ||
3503 | pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false); | |
3504 | if (pte == NULL) | |
3505 | return 0; | |
3506 | ||
3507 | *pte = 0; | |
3508 | ||
3509 | return __amd_iommu_flush_tlb(domain, pasid); | |
3510 | } | |
3511 | ||
3512 | int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid, | |
3513 | unsigned long cr3) | |
3514 | { | |
3f4b87b9 | 3515 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3516 | unsigned long flags; |
3517 | int ret; | |
3518 | ||
3519 | spin_lock_irqsave(&domain->lock, flags); | |
3520 | ret = __set_gcr3(domain, pasid, cr3); | |
3521 | spin_unlock_irqrestore(&domain->lock, flags); | |
3522 | ||
3523 | return ret; | |
3524 | } | |
3525 | EXPORT_SYMBOL(amd_iommu_domain_set_gcr3); | |
3526 | ||
3527 | int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid) | |
3528 | { | |
3f4b87b9 | 3529 | struct protection_domain *domain = to_pdomain(dom); |
b16137b1 JR |
3530 | unsigned long flags; |
3531 | int ret; | |
3532 | ||
3533 | spin_lock_irqsave(&domain->lock, flags); | |
3534 | ret = __clear_gcr3(domain, pasid); | |
3535 | spin_unlock_irqrestore(&domain->lock, flags); | |
3536 | ||
3537 | return ret; | |
3538 | } | |
3539 | EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3); | |
c99afa25 JR |
3540 | |
3541 | int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid, | |
3542 | int status, int tag) | |
3543 | { | |
3544 | struct iommu_dev_data *dev_data; | |
3545 | struct amd_iommu *iommu; | |
3546 | struct iommu_cmd cmd; | |
3547 | ||
3548 | dev_data = get_dev_data(&pdev->dev); | |
3549 | iommu = amd_iommu_rlookup_table[dev_data->devid]; | |
3550 | ||
3551 | build_complete_ppr(&cmd, dev_data->devid, pasid, status, | |
3552 | tag, dev_data->pri_tlp); | |
3553 | ||
3554 | return iommu_queue_command(iommu, &cmd); | |
3555 | } | |
3556 | EXPORT_SYMBOL(amd_iommu_complete_ppr); | |
f3572db8 JR |
3557 | |
3558 | struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev) | |
3559 | { | |
3f4b87b9 | 3560 | struct protection_domain *pdomain; |
f3572db8 | 3561 | |
3f4b87b9 JR |
3562 | pdomain = get_domain(&pdev->dev); |
3563 | if (IS_ERR(pdomain)) | |
f3572db8 JR |
3564 | return NULL; |
3565 | ||
3566 | /* Only return IOMMUv2 domains */ | |
3f4b87b9 | 3567 | if (!(pdomain->flags & PD_IOMMUV2_MASK)) |
f3572db8 JR |
3568 | return NULL; |
3569 | ||
3f4b87b9 | 3570 | return &pdomain->domain; |
f3572db8 JR |
3571 | } |
3572 | EXPORT_SYMBOL(amd_iommu_get_v2_domain); | |
6a113ddc JR |
3573 | |
3574 | void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum) | |
3575 | { | |
3576 | struct iommu_dev_data *dev_data; | |
3577 | ||
3578 | if (!amd_iommu_v2_supported()) | |
3579 | return; | |
3580 | ||
3581 | dev_data = get_dev_data(&pdev->dev); | |
3582 | dev_data->errata |= (1 << erratum); | |
3583 | } | |
3584 | EXPORT_SYMBOL(amd_iommu_enable_device_erratum); | |
52efdb89 JR |
3585 | |
3586 | int amd_iommu_device_info(struct pci_dev *pdev, | |
3587 | struct amd_iommu_device_info *info) | |
3588 | { | |
3589 | int max_pasids; | |
3590 | int pos; | |
3591 | ||
3592 | if (pdev == NULL || info == NULL) | |
3593 | return -EINVAL; | |
3594 | ||
3595 | if (!amd_iommu_v2_supported()) | |
3596 | return -EINVAL; | |
3597 | ||
3598 | memset(info, 0, sizeof(*info)); | |
3599 | ||
3600 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS); | |
3601 | if (pos) | |
3602 | info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP; | |
3603 | ||
3604 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); | |
3605 | if (pos) | |
3606 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP; | |
3607 | ||
3608 | pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID); | |
3609 | if (pos) { | |
3610 | int features; | |
3611 | ||
3612 | max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1)); | |
3613 | max_pasids = min(max_pasids, (1 << 20)); | |
3614 | ||
3615 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP; | |
3616 | info->max_pasids = min(pci_max_pasids(pdev), max_pasids); | |
3617 | ||
3618 | features = pci_pasid_features(pdev); | |
3619 | if (features & PCI_PASID_CAP_EXEC) | |
3620 | info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP; | |
3621 | if (features & PCI_PASID_CAP_PRIV) | |
3622 | info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP; | |
3623 | } | |
3624 | ||
3625 | return 0; | |
3626 | } | |
3627 | EXPORT_SYMBOL(amd_iommu_device_info); | |
2b324506 JR |
3628 | |
3629 | #ifdef CONFIG_IRQ_REMAP | |
3630 | ||
3631 | /***************************************************************************** | |
3632 | * | |
3633 | * Interrupt Remapping Implementation | |
3634 | * | |
3635 | *****************************************************************************/ | |
3636 | ||
7c71d306 JL |
3637 | static struct irq_chip amd_ir_chip; |
3638 | ||
2b324506 JR |
3639 | static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table) |
3640 | { | |
3641 | u64 dte; | |
3642 | ||
3643 | dte = amd_iommu_dev_table[devid].data[2]; | |
3644 | dte &= ~DTE_IRQ_PHYS_ADDR_MASK; | |
2543a786 | 3645 | dte |= iommu_virt_to_phys(table->table); |
2b324506 JR |
3646 | dte |= DTE_IRQ_REMAP_INTCTL; |
3647 | dte |= DTE_IRQ_TABLE_LEN; | |
3648 | dte |= DTE_IRQ_REMAP_ENABLE; | |
3649 | ||
3650 | amd_iommu_dev_table[devid].data[2] = dte; | |
3651 | } | |
3652 | ||
2b324506 JR |
3653 | static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic) |
3654 | { | |
3655 | struct irq_remap_table *table = NULL; | |
3656 | struct amd_iommu *iommu; | |
3657 | unsigned long flags; | |
3658 | u16 alias; | |
3659 | ||
3660 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
3661 | ||
3662 | iommu = amd_iommu_rlookup_table[devid]; | |
3663 | if (!iommu) | |
3664 | goto out_unlock; | |
3665 | ||
3666 | table = irq_lookup_table[devid]; | |
3667 | if (table) | |
09284b9c | 3668 | goto out_unlock; |
2b324506 JR |
3669 | |
3670 | alias = amd_iommu_alias_table[devid]; | |
3671 | table = irq_lookup_table[alias]; | |
3672 | if (table) { | |
3673 | irq_lookup_table[devid] = table; | |
3674 | set_dte_irq_entry(devid, table); | |
3675 | iommu_flush_dte(iommu, devid); | |
3676 | goto out; | |
3677 | } | |
3678 | ||
3679 | /* Nothing there yet, allocate new irq remapping table */ | |
3680 | table = kzalloc(sizeof(*table), GFP_ATOMIC); | |
3681 | if (!table) | |
09284b9c | 3682 | goto out_unlock; |
2b324506 | 3683 | |
197887f0 JR |
3684 | /* Initialize table spin-lock */ |
3685 | spin_lock_init(&table->lock); | |
3686 | ||
2b324506 JR |
3687 | if (ioapic) |
3688 | /* Keep the first 32 indexes free for IOAPIC interrupts */ | |
3689 | table->min_index = 32; | |
3690 | ||
3691 | table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC); | |
3692 | if (!table->table) { | |
3693 | kfree(table); | |
821f0f68 | 3694 | table = NULL; |
09284b9c | 3695 | goto out_unlock; |
2b324506 JR |
3696 | } |
3697 | ||
77bdab46 SS |
3698 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
3699 | memset(table->table, 0, | |
3700 | MAX_IRQS_PER_TABLE * sizeof(u32)); | |
3701 | else | |
3702 | memset(table->table, 0, | |
3703 | (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2))); | |
2b324506 JR |
3704 | |
3705 | if (ioapic) { | |
3706 | int i; | |
3707 | ||
3708 | for (i = 0; i < 32; ++i) | |
77bdab46 | 3709 | iommu->irte_ops->set_allocated(table, i); |
2b324506 JR |
3710 | } |
3711 | ||
3712 | irq_lookup_table[devid] = table; | |
3713 | set_dte_irq_entry(devid, table); | |
3714 | iommu_flush_dte(iommu, devid); | |
3715 | if (devid != alias) { | |
3716 | irq_lookup_table[alias] = table; | |
e028a9e6 | 3717 | set_dte_irq_entry(alias, table); |
2b324506 JR |
3718 | iommu_flush_dte(iommu, alias); |
3719 | } | |
3720 | ||
3721 | out: | |
3722 | iommu_completion_wait(iommu); | |
3723 | ||
3724 | out_unlock: | |
3725 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
3726 | ||
3727 | return table; | |
3728 | } | |
3729 | ||
37946d95 | 3730 | static int alloc_irq_index(u16 devid, int count, bool align) |
2b324506 JR |
3731 | { |
3732 | struct irq_remap_table *table; | |
37946d95 | 3733 | int index, c, alignment = 1; |
2b324506 | 3734 | unsigned long flags; |
77bdab46 SS |
3735 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
3736 | ||
3737 | if (!iommu) | |
3738 | return -ENODEV; | |
2b324506 JR |
3739 | |
3740 | table = get_irq_table(devid, false); | |
3741 | if (!table) | |
3742 | return -ENODEV; | |
3743 | ||
37946d95 JR |
3744 | if (align) |
3745 | alignment = roundup_pow_of_two(count); | |
3746 | ||
2b324506 JR |
3747 | spin_lock_irqsave(&table->lock, flags); |
3748 | ||
3749 | /* Scan table for free entries */ | |
37946d95 | 3750 | for (index = ALIGN(table->min_index, alignment), c = 0; |
07d1c91b | 3751 | index < MAX_IRQS_PER_TABLE;) { |
37946d95 | 3752 | if (!iommu->irte_ops->is_allocated(table, index)) { |
2b324506 | 3753 | c += 1; |
37946d95 JR |
3754 | } else { |
3755 | c = 0; | |
07d1c91b | 3756 | index = ALIGN(index + 1, alignment); |
37946d95 JR |
3757 | continue; |
3758 | } | |
2b324506 JR |
3759 | |
3760 | if (c == count) { | |
2b324506 | 3761 | for (; c != 0; --c) |
77bdab46 | 3762 | iommu->irte_ops->set_allocated(table, index - c + 1); |
2b324506 JR |
3763 | |
3764 | index -= count - 1; | |
2b324506 JR |
3765 | goto out; |
3766 | } | |
07d1c91b AW |
3767 | |
3768 | index++; | |
2b324506 JR |
3769 | } |
3770 | ||
3771 | index = -ENOSPC; | |
3772 | ||
3773 | out: | |
3774 | spin_unlock_irqrestore(&table->lock, flags); | |
3775 | ||
3776 | return index; | |
3777 | } | |
3778 | ||
b9fc6b56 SS |
3779 | static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte, |
3780 | struct amd_ir_data *data) | |
2b324506 JR |
3781 | { |
3782 | struct irq_remap_table *table; | |
3783 | struct amd_iommu *iommu; | |
3784 | unsigned long flags; | |
880ac60e | 3785 | struct irte_ga *entry; |
2b324506 JR |
3786 | |
3787 | iommu = amd_iommu_rlookup_table[devid]; | |
3788 | if (iommu == NULL) | |
3789 | return -EINVAL; | |
3790 | ||
3791 | table = get_irq_table(devid, false); | |
3792 | if (!table) | |
3793 | return -ENOMEM; | |
3794 | ||
3795 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e SS |
3796 | |
3797 | entry = (struct irte_ga *)table->table; | |
3798 | entry = &entry[index]; | |
3799 | entry->lo.fields_remap.valid = 0; | |
3800 | entry->hi.val = irte->hi.val; | |
3801 | entry->lo.val = irte->lo.val; | |
3802 | entry->lo.fields_remap.valid = 1; | |
b9fc6b56 SS |
3803 | if (data) |
3804 | data->ref = entry; | |
880ac60e SS |
3805 | |
3806 | spin_unlock_irqrestore(&table->lock, flags); | |
3807 | ||
3808 | iommu_flush_irt(iommu, devid); | |
3809 | iommu_completion_wait(iommu); | |
3810 | ||
3811 | return 0; | |
3812 | } | |
3813 | ||
3814 | static int modify_irte(u16 devid, int index, union irte *irte) | |
2b324506 JR |
3815 | { |
3816 | struct irq_remap_table *table; | |
3817 | struct amd_iommu *iommu; | |
3818 | unsigned long flags; | |
3819 | ||
3820 | iommu = amd_iommu_rlookup_table[devid]; | |
3821 | if (iommu == NULL) | |
3822 | return -EINVAL; | |
3823 | ||
3824 | table = get_irq_table(devid, false); | |
3825 | if (!table) | |
3826 | return -ENOMEM; | |
3827 | ||
3828 | spin_lock_irqsave(&table->lock, flags); | |
880ac60e | 3829 | table->table[index] = irte->val; |
2b324506 JR |
3830 | spin_unlock_irqrestore(&table->lock, flags); |
3831 | ||
3832 | iommu_flush_irt(iommu, devid); | |
3833 | iommu_completion_wait(iommu); | |
3834 | ||
3835 | return 0; | |
3836 | } | |
3837 | ||
3838 | static void free_irte(u16 devid, int index) | |
3839 | { | |
3840 | struct irq_remap_table *table; | |
3841 | struct amd_iommu *iommu; | |
3842 | unsigned long flags; | |
3843 | ||
3844 | iommu = amd_iommu_rlookup_table[devid]; | |
3845 | if (iommu == NULL) | |
3846 | return; | |
3847 | ||
3848 | table = get_irq_table(devid, false); | |
3849 | if (!table) | |
3850 | return; | |
3851 | ||
3852 | spin_lock_irqsave(&table->lock, flags); | |
77bdab46 | 3853 | iommu->irte_ops->clear_allocated(table, index); |
2b324506 JR |
3854 | spin_unlock_irqrestore(&table->lock, flags); |
3855 | ||
3856 | iommu_flush_irt(iommu, devid); | |
3857 | iommu_completion_wait(iommu); | |
3858 | } | |
3859 | ||
880ac60e SS |
3860 | static void irte_prepare(void *entry, |
3861 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3862 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3863 | { |
3864 | union irte *irte = (union irte *) entry; | |
3865 | ||
3866 | irte->val = 0; | |
3867 | irte->fields.vector = vector; | |
3868 | irte->fields.int_type = delivery_mode; | |
3869 | irte->fields.destination = dest_apicid; | |
3870 | irte->fields.dm = dest_mode; | |
3871 | irte->fields.valid = 1; | |
3872 | } | |
3873 | ||
3874 | static void irte_ga_prepare(void *entry, | |
3875 | u32 delivery_mode, u32 dest_mode, | |
d98de49a | 3876 | u8 vector, u32 dest_apicid, int devid) |
880ac60e SS |
3877 | { |
3878 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3879 | ||
3880 | irte->lo.val = 0; | |
3881 | irte->hi.val = 0; | |
880ac60e SS |
3882 | irte->lo.fields_remap.int_type = delivery_mode; |
3883 | irte->lo.fields_remap.dm = dest_mode; | |
3884 | irte->hi.fields.vector = vector; | |
e8dc5557 SS |
3885 | irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid); |
3886 | irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid); | |
880ac60e SS |
3887 | irte->lo.fields_remap.valid = 1; |
3888 | } | |
3889 | ||
3890 | static void irte_activate(void *entry, u16 devid, u16 index) | |
3891 | { | |
3892 | union irte *irte = (union irte *) entry; | |
3893 | ||
3894 | irte->fields.valid = 1; | |
3895 | modify_irte(devid, index, irte); | |
3896 | } | |
3897 | ||
3898 | static void irte_ga_activate(void *entry, u16 devid, u16 index) | |
3899 | { | |
3900 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3901 | ||
3902 | irte->lo.fields_remap.valid = 1; | |
b9fc6b56 | 3903 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3904 | } |
3905 | ||
3906 | static void irte_deactivate(void *entry, u16 devid, u16 index) | |
3907 | { | |
3908 | union irte *irte = (union irte *) entry; | |
3909 | ||
3910 | irte->fields.valid = 0; | |
3911 | modify_irte(devid, index, irte); | |
3912 | } | |
3913 | ||
3914 | static void irte_ga_deactivate(void *entry, u16 devid, u16 index) | |
3915 | { | |
3916 | struct irte_ga *irte = (struct irte_ga *) entry; | |
3917 | ||
3918 | irte->lo.fields_remap.valid = 0; | |
b9fc6b56 | 3919 | modify_irte_ga(devid, index, irte, NULL); |
880ac60e SS |
3920 | } |
3921 | ||
3922 | static void irte_set_affinity(void *entry, u16 devid, u16 index, | |
3923 | u8 vector, u32 dest_apicid) | |
3924 | { | |
3925 | union irte *irte = (union irte *) entry; | |
3926 | ||
3927 | irte->fields.vector = vector; | |
3928 | irte->fields.destination = dest_apicid; | |
3929 | modify_irte(devid, index, irte); | |
3930 | } | |
3931 | ||
3932 | static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, | |
3933 | u8 vector, u32 dest_apicid) | |
3934 | { | |
3935 | struct irte_ga *irte = (struct irte_ga *) entry; | |
d98de49a | 3936 | struct iommu_dev_data *dev_data = search_dev_data(devid); |
880ac60e | 3937 | |
84a21dbd SS |
3938 | if (!dev_data || !dev_data->use_vapic || |
3939 | !irte->lo.fields_remap.guest_mode) { | |
d98de49a | 3940 | irte->hi.fields.vector = vector; |
e8dc5557 SS |
3941 | irte->lo.fields_remap.destination = |
3942 | APICID_TO_IRTE_DEST_LO(dest_apicid); | |
3943 | irte->hi.fields.destination = | |
3944 | APICID_TO_IRTE_DEST_HI(dest_apicid); | |
d98de49a SS |
3945 | modify_irte_ga(devid, index, irte, NULL); |
3946 | } | |
880ac60e SS |
3947 | } |
3948 | ||
77bdab46 | 3949 | #define IRTE_ALLOCATED (~1U) |
880ac60e SS |
3950 | static void irte_set_allocated(struct irq_remap_table *table, int index) |
3951 | { | |
3952 | table->table[index] = IRTE_ALLOCATED; | |
3953 | } | |
3954 | ||
3955 | static void irte_ga_set_allocated(struct irq_remap_table *table, int index) | |
3956 | { | |
3957 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3958 | struct irte_ga *irte = &ptr[index]; | |
3959 | ||
3960 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3961 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3962 | irte->hi.fields.vector = 0xff; | |
3963 | } | |
3964 | ||
3965 | static bool irte_is_allocated(struct irq_remap_table *table, int index) | |
3966 | { | |
3967 | union irte *ptr = (union irte *)table->table; | |
3968 | union irte *irte = &ptr[index]; | |
3969 | ||
3970 | return irte->val != 0; | |
3971 | } | |
3972 | ||
3973 | static bool irte_ga_is_allocated(struct irq_remap_table *table, int index) | |
3974 | { | |
3975 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3976 | struct irte_ga *irte = &ptr[index]; | |
3977 | ||
3978 | return irte->hi.fields.vector != 0; | |
3979 | } | |
3980 | ||
3981 | static void irte_clear_allocated(struct irq_remap_table *table, int index) | |
3982 | { | |
3983 | table->table[index] = 0; | |
3984 | } | |
3985 | ||
3986 | static void irte_ga_clear_allocated(struct irq_remap_table *table, int index) | |
3987 | { | |
3988 | struct irte_ga *ptr = (struct irte_ga *)table->table; | |
3989 | struct irte_ga *irte = &ptr[index]; | |
3990 | ||
3991 | memset(&irte->lo.val, 0, sizeof(u64)); | |
3992 | memset(&irte->hi.val, 0, sizeof(u64)); | |
3993 | } | |
3994 | ||
7c71d306 | 3995 | static int get_devid(struct irq_alloc_info *info) |
5527de74 | 3996 | { |
7c71d306 | 3997 | int devid = -1; |
5527de74 | 3998 | |
7c71d306 JL |
3999 | switch (info->type) { |
4000 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4001 | devid = get_ioapic_devid(info->ioapic_id); | |
4002 | break; | |
4003 | case X86_IRQ_ALLOC_TYPE_HPET: | |
4004 | devid = get_hpet_devid(info->hpet_id); | |
4005 | break; | |
4006 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4007 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4008 | devid = get_device_id(&info->msi_dev->dev); | |
4009 | break; | |
4010 | default: | |
4011 | BUG_ON(1); | |
4012 | break; | |
4013 | } | |
5527de74 | 4014 | |
7c71d306 JL |
4015 | return devid; |
4016 | } | |
5527de74 | 4017 | |
7c71d306 JL |
4018 | static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info) |
4019 | { | |
4020 | struct amd_iommu *iommu; | |
4021 | int devid; | |
5527de74 | 4022 | |
7c71d306 JL |
4023 | if (!info) |
4024 | return NULL; | |
5527de74 | 4025 | |
7c71d306 JL |
4026 | devid = get_devid(info); |
4027 | if (devid >= 0) { | |
4028 | iommu = amd_iommu_rlookup_table[devid]; | |
4029 | if (iommu) | |
4030 | return iommu->ir_domain; | |
4031 | } | |
5527de74 | 4032 | |
7c71d306 | 4033 | return NULL; |
5527de74 JR |
4034 | } |
4035 | ||
7c71d306 | 4036 | static struct irq_domain *get_irq_domain(struct irq_alloc_info *info) |
5527de74 | 4037 | { |
7c71d306 JL |
4038 | struct amd_iommu *iommu; |
4039 | int devid; | |
5527de74 | 4040 | |
7c71d306 JL |
4041 | if (!info) |
4042 | return NULL; | |
5527de74 | 4043 | |
7c71d306 JL |
4044 | switch (info->type) { |
4045 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4046 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4047 | devid = get_device_id(&info->msi_dev->dev); | |
9ee35e4c | 4048 | if (devid < 0) |
7aba6cb9 WZ |
4049 | return NULL; |
4050 | ||
1fb260bc DC |
4051 | iommu = amd_iommu_rlookup_table[devid]; |
4052 | if (iommu) | |
4053 | return iommu->msi_domain; | |
7c71d306 JL |
4054 | break; |
4055 | default: | |
4056 | break; | |
4057 | } | |
5527de74 | 4058 | |
7c71d306 JL |
4059 | return NULL; |
4060 | } | |
5527de74 | 4061 | |
6b474b82 | 4062 | struct irq_remap_ops amd_iommu_irq_ops = { |
6b474b82 JR |
4063 | .prepare = amd_iommu_prepare, |
4064 | .enable = amd_iommu_enable, | |
4065 | .disable = amd_iommu_disable, | |
4066 | .reenable = amd_iommu_reenable, | |
4067 | .enable_faulting = amd_iommu_enable_faulting, | |
7c71d306 JL |
4068 | .get_ir_irq_domain = get_ir_irq_domain, |
4069 | .get_irq_domain = get_irq_domain, | |
4070 | }; | |
5527de74 | 4071 | |
7c71d306 JL |
4072 | static void irq_remapping_prepare_irte(struct amd_ir_data *data, |
4073 | struct irq_cfg *irq_cfg, | |
4074 | struct irq_alloc_info *info, | |
4075 | int devid, int index, int sub_handle) | |
4076 | { | |
4077 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
4078 | struct msi_msg *msg = &data->msi_entry; | |
7c71d306 | 4079 | struct IO_APIC_route_entry *entry; |
77bdab46 SS |
4080 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
4081 | ||
4082 | if (!iommu) | |
4083 | return; | |
5527de74 | 4084 | |
7c71d306 JL |
4085 | data->irq_2_irte.devid = devid; |
4086 | data->irq_2_irte.index = index + sub_handle; | |
77bdab46 SS |
4087 | iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode, |
4088 | apic->irq_dest_mode, irq_cfg->vector, | |
d98de49a | 4089 | irq_cfg->dest_apicid, devid); |
7c71d306 JL |
4090 | |
4091 | switch (info->type) { | |
4092 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
4093 | /* Setup IOAPIC entry */ | |
4094 | entry = info->ioapic_entry; | |
4095 | info->ioapic_entry = NULL; | |
4096 | memset(entry, 0, sizeof(*entry)); | |
4097 | entry->vector = index; | |
4098 | entry->mask = 0; | |
4099 | entry->trigger = info->ioapic_trigger; | |
4100 | entry->polarity = info->ioapic_polarity; | |
4101 | /* Mask level triggered irqs. */ | |
4102 | if (info->ioapic_trigger) | |
4103 | entry->mask = 1; | |
4104 | break; | |
5527de74 | 4105 | |
7c71d306 JL |
4106 | case X86_IRQ_ALLOC_TYPE_HPET: |
4107 | case X86_IRQ_ALLOC_TYPE_MSI: | |
4108 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
4109 | msg->address_hi = MSI_ADDR_BASE_HI; | |
4110 | msg->address_lo = MSI_ADDR_BASE_LO; | |
4111 | msg->data = irte_info->index; | |
4112 | break; | |
5527de74 | 4113 | |
7c71d306 JL |
4114 | default: |
4115 | BUG_ON(1); | |
4116 | break; | |
4117 | } | |
5527de74 JR |
4118 | } |
4119 | ||
880ac60e SS |
4120 | struct amd_irte_ops irte_32_ops = { |
4121 | .prepare = irte_prepare, | |
4122 | .activate = irte_activate, | |
4123 | .deactivate = irte_deactivate, | |
4124 | .set_affinity = irte_set_affinity, | |
4125 | .set_allocated = irte_set_allocated, | |
4126 | .is_allocated = irte_is_allocated, | |
4127 | .clear_allocated = irte_clear_allocated, | |
4128 | }; | |
4129 | ||
4130 | struct amd_irte_ops irte_128_ops = { | |
4131 | .prepare = irte_ga_prepare, | |
4132 | .activate = irte_ga_activate, | |
4133 | .deactivate = irte_ga_deactivate, | |
4134 | .set_affinity = irte_ga_set_affinity, | |
4135 | .set_allocated = irte_ga_set_allocated, | |
4136 | .is_allocated = irte_ga_is_allocated, | |
4137 | .clear_allocated = irte_ga_clear_allocated, | |
4138 | }; | |
4139 | ||
7c71d306 JL |
4140 | static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, |
4141 | unsigned int nr_irqs, void *arg) | |
5527de74 | 4142 | { |
7c71d306 JL |
4143 | struct irq_alloc_info *info = arg; |
4144 | struct irq_data *irq_data; | |
77bdab46 | 4145 | struct amd_ir_data *data = NULL; |
5527de74 | 4146 | struct irq_cfg *cfg; |
7c71d306 JL |
4147 | int i, ret, devid; |
4148 | int index = -1; | |
5527de74 | 4149 | |
7c71d306 JL |
4150 | if (!info) |
4151 | return -EINVAL; | |
4152 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
4153 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
5527de74 JR |
4154 | return -EINVAL; |
4155 | ||
7c71d306 JL |
4156 | /* |
4157 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
4158 | * to support multiple MSI interrupts. | |
4159 | */ | |
4160 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
4161 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
5527de74 | 4162 | |
7c71d306 JL |
4163 | devid = get_devid(info); |
4164 | if (devid < 0) | |
4165 | return -EINVAL; | |
5527de74 | 4166 | |
7c71d306 JL |
4167 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
4168 | if (ret < 0) | |
4169 | return ret; | |
0b4d48cb | 4170 | |
7c71d306 JL |
4171 | if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) { |
4172 | if (get_irq_table(devid, true)) | |
4173 | index = info->ioapic_pin; | |
4174 | else | |
4175 | ret = -ENOMEM; | |
4176 | } else { | |
53b9ec3f JR |
4177 | bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI); |
4178 | ||
4179 | index = alloc_irq_index(devid, nr_irqs, align); | |
7c71d306 JL |
4180 | } |
4181 | if (index < 0) { | |
4182 | pr_warn("Failed to allocate IRTE\n"); | |
517abe49 | 4183 | ret = index; |
7c71d306 JL |
4184 | goto out_free_parent; |
4185 | } | |
0b4d48cb | 4186 | |
7c71d306 JL |
4187 | for (i = 0; i < nr_irqs; i++) { |
4188 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4189 | cfg = irqd_cfg(irq_data); | |
4190 | if (!irq_data || !cfg) { | |
4191 | ret = -EINVAL; | |
4192 | goto out_free_data; | |
4193 | } | |
0b4d48cb | 4194 | |
a130e69f JR |
4195 | ret = -ENOMEM; |
4196 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
4197 | if (!data) | |
4198 | goto out_free_data; | |
4199 | ||
77bdab46 SS |
4200 | if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir)) |
4201 | data->entry = kzalloc(sizeof(union irte), GFP_KERNEL); | |
4202 | else | |
4203 | data->entry = kzalloc(sizeof(struct irte_ga), | |
4204 | GFP_KERNEL); | |
4205 | if (!data->entry) { | |
4206 | kfree(data); | |
4207 | goto out_free_data; | |
4208 | } | |
4209 | ||
7c71d306 JL |
4210 | irq_data->hwirq = (devid << 16) + i; |
4211 | irq_data->chip_data = data; | |
4212 | irq_data->chip = &amd_ir_chip; | |
4213 | irq_remapping_prepare_irte(data, cfg, info, devid, index, i); | |
4214 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
4215 | } | |
a130e69f | 4216 | |
7c71d306 | 4217 | return 0; |
0b4d48cb | 4218 | |
7c71d306 JL |
4219 | out_free_data: |
4220 | for (i--; i >= 0; i--) { | |
4221 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4222 | if (irq_data) | |
4223 | kfree(irq_data->chip_data); | |
4224 | } | |
4225 | for (i = 0; i < nr_irqs; i++) | |
4226 | free_irte(devid, index + i); | |
4227 | out_free_parent: | |
4228 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4229 | return ret; | |
0b4d48cb JR |
4230 | } |
4231 | ||
7c71d306 JL |
4232 | static void irq_remapping_free(struct irq_domain *domain, unsigned int virq, |
4233 | unsigned int nr_irqs) | |
0b4d48cb | 4234 | { |
7c71d306 JL |
4235 | struct irq_2_irte *irte_info; |
4236 | struct irq_data *irq_data; | |
4237 | struct amd_ir_data *data; | |
4238 | int i; | |
0b4d48cb | 4239 | |
7c71d306 JL |
4240 | for (i = 0; i < nr_irqs; i++) { |
4241 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
4242 | if (irq_data && irq_data->chip_data) { | |
4243 | data = irq_data->chip_data; | |
4244 | irte_info = &data->irq_2_irte; | |
4245 | free_irte(irte_info->devid, irte_info->index); | |
77bdab46 | 4246 | kfree(data->entry); |
7c71d306 JL |
4247 | kfree(data); |
4248 | } | |
4249 | } | |
4250 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
4251 | } | |
0b4d48cb | 4252 | |
5ba204a1 TG |
4253 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, |
4254 | struct amd_ir_data *ir_data, | |
4255 | struct irq_2_irte *irte_info, | |
4256 | struct irq_cfg *cfg); | |
4257 | ||
72491643 | 4258 | static int irq_remapping_activate(struct irq_domain *domain, |
702cb0a0 | 4259 | struct irq_data *irq_data, bool reserve) |
7c71d306 JL |
4260 | { |
4261 | struct amd_ir_data *data = irq_data->chip_data; | |
4262 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4263 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
5ba204a1 | 4264 | struct irq_cfg *cfg = irqd_cfg(irq_data); |
0b4d48cb | 4265 | |
5ba204a1 TG |
4266 | if (!iommu) |
4267 | return 0; | |
4268 | ||
4269 | iommu->irte_ops->activate(data->entry, irte_info->devid, | |
4270 | irte_info->index); | |
4271 | amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg); | |
72491643 | 4272 | return 0; |
0b4d48cb JR |
4273 | } |
4274 | ||
7c71d306 JL |
4275 | static void irq_remapping_deactivate(struct irq_domain *domain, |
4276 | struct irq_data *irq_data) | |
0b4d48cb | 4277 | { |
7c71d306 JL |
4278 | struct amd_ir_data *data = irq_data->chip_data; |
4279 | struct irq_2_irte *irte_info = &data->irq_2_irte; | |
77bdab46 | 4280 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
0b4d48cb | 4281 | |
77bdab46 SS |
4282 | if (iommu) |
4283 | iommu->irte_ops->deactivate(data->entry, irte_info->devid, | |
4284 | irte_info->index); | |
7c71d306 | 4285 | } |
0b4d48cb | 4286 | |
e2f9d45f | 4287 | static const struct irq_domain_ops amd_ir_domain_ops = { |
7c71d306 JL |
4288 | .alloc = irq_remapping_alloc, |
4289 | .free = irq_remapping_free, | |
4290 | .activate = irq_remapping_activate, | |
4291 | .deactivate = irq_remapping_deactivate, | |
6b474b82 | 4292 | }; |
0b4d48cb | 4293 | |
b9fc6b56 SS |
4294 | static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) |
4295 | { | |
4296 | struct amd_iommu *iommu; | |
4297 | struct amd_iommu_pi_data *pi_data = vcpu_info; | |
4298 | struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data; | |
4299 | struct amd_ir_data *ir_data = data->chip_data; | |
4300 | struct irte_ga *irte = (struct irte_ga *) ir_data->entry; | |
4301 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
d98de49a SS |
4302 | struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid); |
4303 | ||
4304 | /* Note: | |
4305 | * This device has never been set up for guest mode. | |
4306 | * we should not modify the IRTE | |
4307 | */ | |
4308 | if (!dev_data || !dev_data->use_vapic) | |
4309 | return 0; | |
b9fc6b56 SS |
4310 | |
4311 | pi_data->ir_data = ir_data; | |
4312 | ||
4313 | /* Note: | |
4314 | * SVM tries to set up for VAPIC mode, but we are in | |
4315 | * legacy mode. So, we force legacy mode instead. | |
4316 | */ | |
4317 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) { | |
4318 | pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n", | |
4319 | __func__); | |
4320 | pi_data->is_guest_mode = false; | |
4321 | } | |
4322 | ||
4323 | iommu = amd_iommu_rlookup_table[irte_info->devid]; | |
4324 | if (iommu == NULL) | |
4325 | return -EINVAL; | |
4326 | ||
4327 | pi_data->prev_ga_tag = ir_data->cached_ga_tag; | |
4328 | if (pi_data->is_guest_mode) { | |
4329 | /* Setting */ | |
4330 | irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); | |
4331 | irte->hi.fields.vector = vcpu_pi_info->vector; | |
efe6f241 | 4332 | irte->lo.fields_vapic.ga_log_intr = 1; |
b9fc6b56 SS |
4333 | irte->lo.fields_vapic.guest_mode = 1; |
4334 | irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; | |
4335 | ||
4336 | ir_data->cached_ga_tag = pi_data->ga_tag; | |
4337 | } else { | |
4338 | /* Un-Setting */ | |
4339 | struct irq_cfg *cfg = irqd_cfg(data); | |
4340 | ||
4341 | irte->hi.val = 0; | |
4342 | irte->lo.val = 0; | |
4343 | irte->hi.fields.vector = cfg->vector; | |
4344 | irte->lo.fields_remap.guest_mode = 0; | |
e8dc5557 SS |
4345 | irte->lo.fields_remap.destination = |
4346 | APICID_TO_IRTE_DEST_LO(cfg->dest_apicid); | |
4347 | irte->hi.fields.destination = | |
4348 | APICID_TO_IRTE_DEST_HI(cfg->dest_apicid); | |
b9fc6b56 SS |
4349 | irte->lo.fields_remap.int_type = apic->irq_delivery_mode; |
4350 | irte->lo.fields_remap.dm = apic->irq_dest_mode; | |
4351 | ||
4352 | /* | |
4353 | * This communicates the ga_tag back to the caller | |
4354 | * so that it can do all the necessary clean up. | |
4355 | */ | |
4356 | ir_data->cached_ga_tag = 0; | |
4357 | } | |
4358 | ||
4359 | return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data); | |
4360 | } | |
4361 | ||
5ba204a1 TG |
4362 | |
4363 | static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu, | |
4364 | struct amd_ir_data *ir_data, | |
4365 | struct irq_2_irte *irte_info, | |
4366 | struct irq_cfg *cfg) | |
4367 | { | |
4368 | ||
4369 | /* | |
4370 | * Atomically updates the IRTE with the new destination, vector | |
4371 | * and flushes the interrupt entry cache. | |
4372 | */ | |
4373 | iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid, | |
4374 | irte_info->index, cfg->vector, | |
4375 | cfg->dest_apicid); | |
4376 | } | |
4377 | ||
7c71d306 JL |
4378 | static int amd_ir_set_affinity(struct irq_data *data, |
4379 | const struct cpumask *mask, bool force) | |
4380 | { | |
4381 | struct amd_ir_data *ir_data = data->chip_data; | |
4382 | struct irq_2_irte *irte_info = &ir_data->irq_2_irte; | |
4383 | struct irq_cfg *cfg = irqd_cfg(data); | |
4384 | struct irq_data *parent = data->parent_data; | |
77bdab46 | 4385 | struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid]; |
7c71d306 | 4386 | int ret; |
0b4d48cb | 4387 | |
77bdab46 SS |
4388 | if (!iommu) |
4389 | return -ENODEV; | |
4390 | ||
7c71d306 JL |
4391 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
4392 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
4393 | return ret; | |
0b4d48cb | 4394 | |
5ba204a1 | 4395 | amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg); |
7c71d306 JL |
4396 | /* |
4397 | * After this point, all the interrupts will start arriving | |
4398 | * at the new destination. So, time to cleanup the previous | |
4399 | * vector allocation. | |
4400 | */ | |
c6c2002b | 4401 | send_cleanup_vector(cfg); |
7c71d306 JL |
4402 | |
4403 | return IRQ_SET_MASK_OK_DONE; | |
0b4d48cb JR |
4404 | } |
4405 | ||
7c71d306 | 4406 | static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg) |
d976195c | 4407 | { |
7c71d306 | 4408 | struct amd_ir_data *ir_data = irq_data->chip_data; |
d976195c | 4409 | |
7c71d306 JL |
4410 | *msg = ir_data->msi_entry; |
4411 | } | |
d976195c | 4412 | |
7c71d306 | 4413 | static struct irq_chip amd_ir_chip = { |
290be194 | 4414 | .name = "AMD-IR", |
7e297530 | 4415 | .irq_ack = apic_ack_irq, |
290be194 TG |
4416 | .irq_set_affinity = amd_ir_set_affinity, |
4417 | .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity, | |
4418 | .irq_compose_msi_msg = ir_compose_msi_msg, | |
7c71d306 | 4419 | }; |
d976195c | 4420 | |
7c71d306 JL |
4421 | int amd_iommu_create_irq_domain(struct amd_iommu *iommu) |
4422 | { | |
3e49a818 TG |
4423 | struct fwnode_handle *fn; |
4424 | ||
4425 | fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index); | |
4426 | if (!fn) | |
4427 | return -ENOMEM; | |
4428 | iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu); | |
4429 | irq_domain_free_fwnode(fn); | |
7c71d306 JL |
4430 | if (!iommu->ir_domain) |
4431 | return -ENOMEM; | |
d976195c | 4432 | |
7c71d306 | 4433 | iommu->ir_domain->parent = arch_get_ir_parent_domain(); |
3e49a818 TG |
4434 | iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain, |
4435 | "AMD-IR-MSI", | |
4436 | iommu->index); | |
d976195c JR |
4437 | return 0; |
4438 | } | |
8dbea3fd SS |
4439 | |
4440 | int amd_iommu_update_ga(int cpu, bool is_run, void *data) | |
4441 | { | |
4442 | unsigned long flags; | |
4443 | struct amd_iommu *iommu; | |
4444 | struct irq_remap_table *irt; | |
4445 | struct amd_ir_data *ir_data = (struct amd_ir_data *)data; | |
4446 | int devid = ir_data->irq_2_irte.devid; | |
4447 | struct irte_ga *entry = (struct irte_ga *) ir_data->entry; | |
4448 | struct irte_ga *ref = (struct irte_ga *) ir_data->ref; | |
4449 | ||
4450 | if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || | |
4451 | !ref || !entry || !entry->lo.fields_vapic.guest_mode) | |
4452 | return 0; | |
4453 | ||
4454 | iommu = amd_iommu_rlookup_table[devid]; | |
4455 | if (!iommu) | |
4456 | return -ENODEV; | |
4457 | ||
4458 | irt = get_irq_table(devid, false); | |
4459 | if (!irt) | |
4460 | return -ENODEV; | |
4461 | ||
4462 | spin_lock_irqsave(&irt->lock, flags); | |
4463 | ||
4464 | if (ref->lo.fields_vapic.guest_mode) { | |
e8dc5557 SS |
4465 | if (cpu >= 0) { |
4466 | ref->lo.fields_vapic.destination = | |
4467 | APICID_TO_IRTE_DEST_LO(cpu); | |
4468 | ref->hi.fields.destination = | |
4469 | APICID_TO_IRTE_DEST_HI(cpu); | |
4470 | } | |
8dbea3fd SS |
4471 | ref->lo.fields_vapic.is_run = is_run; |
4472 | barrier(); | |
4473 | } | |
4474 | ||
4475 | spin_unlock_irqrestore(&irt->lock, flags); | |
4476 | ||
4477 | iommu_flush_irt(iommu, devid); | |
4478 | iommu_completion_wait(iommu); | |
4479 | return 0; | |
4480 | } | |
4481 | EXPORT_SYMBOL(amd_iommu_update_ga); | |
2b324506 | 4482 | #endif |