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f6e2e6b6 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
f6e2e6b6
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
f6e2e6b6 22#include <linux/list.h>
5c87f62d 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
f3c6ea1b 25#include <linux/syscore_ops.h>
a80dc3e0
JR		 26#include <linux/interrupt.h>
27#include <linux/msi.h>
403f81d8 28#include <linux/amd-iommu.h>
400a28a0 29#include <linux/export.h>
066f2e98 30#include <linux/iommu.h>
ebcfa284 31#include <linux/kmemleak.h>
f6e2e6b6 32#include <asm/pci-direct.h>
46a7fa27 33#include <asm/iommu.h>
1d9b16d1 34#include <asm/gart.h>
ea1b0d39 35#include <asm/x86_init.h>
22e6daf4 36#include <asm/iommu_table.h>
eb1eb7ae 37#include <asm/io_apic.h>
6b474b82 38#include <asm/irq_remapping.h>
403f81d8
JR		 39
40#include "amd_iommu_proto.h"
41#include "amd_iommu_types.h"
05152a04 42#include "irq_remapping.h"
403f81d8 43
f6e2e6b6
JR		 44/*
45 * definitions for the ACPI scanning code
46 */
f6e2e6b6 47#define IVRS_HEADER_LENGTH 48
f6e2e6b6 48
8c7142f5 49#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
f6e2e6b6
JR		 50#define ACPI_IVMD_TYPE_ALL 0x20
51#define ACPI_IVMD_TYPE 0x21
52#define ACPI_IVMD_TYPE_RANGE 0x22
53
54#define IVHD_DEV_ALL 0x01
55#define IVHD_DEV_SELECT 0x02
56#define IVHD_DEV_SELECT_RANGE_START 0x03
57#define IVHD_DEV_RANGE_END 0x04
58#define IVHD_DEV_ALIAS 0x42
59#define IVHD_DEV_ALIAS_RANGE 0x43
60#define IVHD_DEV_EXT_SELECT 0x46
61#define IVHD_DEV_EXT_SELECT_RANGE 0x47
6efed63b 62#define IVHD_DEV_SPECIAL 0x48
8c7142f5 63#define IVHD_DEV_ACPI_HID 0xf0
6efed63b 64
2a0cb4e2
WZ		 65#define UID_NOT_PRESENT 0
66#define UID_IS_INTEGER 1
67#define UID_IS_CHARACTER 2
68
6efed63b
JR		 69#define IVHD_SPECIAL_IOAPIC 1
70#define IVHD_SPECIAL_HPET 2
f6e2e6b6 71
6da7342f
JR		 72#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
73#define IVHD_FLAG_PASSPW_EN_MASK 0x02
74#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
75#define IVHD_FLAG_ISOC_EN_MASK 0x08
f6e2e6b6
JR		 76
77#define IVMD_FLAG_EXCL_RANGE 0x08
78#define IVMD_FLAG_UNITY_MAP 0x01
79
80#define ACPI_DEVFLAG_INITPASS 0x01
81#define ACPI_DEVFLAG_EXTINT 0x02
82#define ACPI_DEVFLAG_NMI 0x04
83#define ACPI_DEVFLAG_SYSMGT1 0x10
84#define ACPI_DEVFLAG_SYSMGT2 0x20
85#define ACPI_DEVFLAG_LINT0 0x40
86#define ACPI_DEVFLAG_LINT1 0x80
87#define ACPI_DEVFLAG_ATSDIS 0x10000000
88
8bda0cfb 89#define LOOP_TIMEOUT 100000
b65233a9
JR		 90/*
91 * ACPI table definitions
92 *
93 * These data structures are laid over the table to parse the important values
94 * out of it.
95 */
96
b0119e87
JR		 97extern const struct iommu_ops amd_iommu_ops;
98
b65233a9
JR		 99/*
100 * structure describing one IOMMU in the ACPI table. Typically followed by one
101 * or more ivhd_entrys.
102 */
f6e2e6b6
JR		 103struct ivhd_header {
104 u8 type;
105 u8 flags;
106 u16 length;
107 u16 devid;
108 u16 cap_ptr;
109 u64 mmio_phys;
110 u16 pci_seg;
111 u16 info;
7d7d38af
SS		 112 u32 efr_attr;
113
114 /* Following only valid on IVHD type 11h and 40h */
115 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
116 u64 res;
f6e2e6b6
JR		 117} __attribute__((packed));
118
b65233a9
JR		 119/*
120 * A device entry describing which devices a specific IOMMU translates and
121 * which requestor ids they use.
122 */
f6e2e6b6
JR		 123struct ivhd_entry {
124 u8 type;
125 u16 devid;
126 u8 flags;
127 u32 ext;
2a0cb4e2
WZ		 128 u32 hidh;
129 u64 cid;
130 u8 uidf;
131 u8 uidl;
132 u8 uid;
f6e2e6b6
JR		 133} __attribute__((packed));
134
b65233a9
JR		 135/*
136 * An AMD IOMMU memory definition structure. It defines things like exclusion
137 * ranges for devices and regions that should be unity mapped.
138 */
f6e2e6b6
JR		 139struct ivmd_header {
140 u8 type;
141 u8 flags;
142 u16 length;
143 u16 devid;
144 u16 aux;
145 u64 resv;
146 u64 range_start;
147 u64 range_length;
148} __attribute__((packed));
149
fefda117 150bool amd_iommu_dump;
05152a04 151bool amd_iommu_irq_remap __read_mostly;
fefda117 152
d98de49a 153int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
3928aa3f 154
02f3b3f5 155static bool amd_iommu_detected;
a5235725 156static bool __initdata amd_iommu_disabled;
8c7142f5 157static int amd_iommu_target_ivhd_type;
c1cbebee 158
b65233a9
JR		 159u16 amd_iommu_last_bdf; /* largest PCI device id we have
160 to handle */
2e22847f 161LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
b65233a9 162 we find in ACPI */
621a5f7a 163bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
928abd25 164
2e22847f 165LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
b65233a9 166 system */
928abd25 167
bb52777e
JR		 168/* Array to assign indices to IOMMUs*/
169struct amd_iommu *amd_iommus[MAX_IOMMUS];
170int amd_iommus_present;
171
318afd41
JR		 172/* IOMMUs have a non-present cache? */
173bool amd_iommu_np_cache __read_mostly;
60f723b4 174bool amd_iommu_iotlb_sup __read_mostly = true;
318afd41 175
a919a018 176u32 amd_iommu_max_pasid __read_mostly = ~0;
62f71abb 177
400a28a0 178bool amd_iommu_v2_present __read_mostly;
4160cd9e 179static bool amd_iommu_pc_present __read_mostly;
400a28a0 180
5abcdba4
JR		 181bool amd_iommu_force_isolation __read_mostly;
182
aeb26f55
JR		 183/*
184 * List of protection domains - used during resume
185 */
186LIST_HEAD(amd_iommu_pd_list);
187spinlock_t amd_iommu_pd_lock;
188
b65233a9
JR		 189/*
190 * Pointer to the device table which is shared by all AMD IOMMUs
191 * it is indexed by the PCI device id or the HT unit id and contains
192 * information about the domain the device belongs to as well as the
193 * page table root pointer.
194 */
928abd25 195struct dev_table_entry *amd_iommu_dev_table;
b65233a9
JR		 196
197/*
198 * The alias table is a driver specific data structure which contains the
199 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
200 * More than one device can share the same requestor id.
201 */
928abd25 202u16 *amd_iommu_alias_table;
b65233a9
JR		 203
204/*
205 * The rlookup table is used to find the IOMMU which is responsible
206 * for a specific device. It is also indexed by the PCI device id.
207 */
928abd25 208struct amd_iommu **amd_iommu_rlookup_table;
b65233a9 209
b65233a9 210/*
0ea2c422
JR		 211 * This table is used to find the irq remapping table for a given device id
212 * quickly.
213 */
214struct irq_remap_table **irq_lookup_table;
215
b65233a9 216/*
df805abb 217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
b65233a9
JR		 218 * to know which ones are already in use.
219 */
928abd25
JR		 220unsigned long *amd_iommu_pd_alloc_bitmap;
221
b65233a9
JR		 222static u32 dev_table_size; /* size of the device table */
223static u32 alias_table_size; /* size of the alias table */
224static u32 rlookup_table_size; /* size if the rlookup table */
3e8064ba 225
2c0ae172
JR		 226enum iommu_init_state {
227 IOMMU_START_STATE,
228 IOMMU_IVRS_DETECTED,
229 IOMMU_ACPI_FINISHED,
230 IOMMU_ENABLED,
231 IOMMU_PCI_INIT,
232 IOMMU_INTERRUPTS_EN,
233 IOMMU_DMA_OPS,
234 IOMMU_INITIALIZED,
235 IOMMU_NOT_FOUND,
236 IOMMU_INIT_ERROR,
237};
238
235dacbc
JR		 239/* Early ioapic and hpet maps from kernel command line */
240#define EARLY_MAP_SIZE 4
241static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
242static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
2a0cb4e2
WZ		 243static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
244
235dacbc
JR		 245static int __initdata early_ioapic_map_size;
246static int __initdata early_hpet_map_size;
2a0cb4e2
WZ		 247static int __initdata early_acpihid_map_size;
248
dfbb6d47 249static bool __initdata cmdline_maps;
235dacbc 250
2c0ae172
JR		 251static enum iommu_init_state init_state = IOMMU_START_STATE;
252
ae295142 253static int amd_iommu_enable_interrupts(void);
2c0ae172 254static int __init iommu_go_to_state(enum iommu_init_state state);
aafd8ba0 255static void init_device_table_dma(void);
3d9761e7 256
38e45d02
SS		 257static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
258 u8 bank, u8 cntr, u8 fxn,
259 u64 *value, bool is_write);
260
208ec8c9
JR		 261static inline void update_last_devid(u16 devid)
262{
263 if (devid > amd_iommu_last_bdf)
264 amd_iommu_last_bdf = devid;
265}
266
c571484e
JR		 267static inline unsigned long tbl_size(int entry_size)
268{
269 unsigned shift = PAGE_SHIFT +
421f909c 270 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
c571484e
JR		 271
272 return 1UL << shift;
273}
274
5bcd757f
MG		 275/* Access to l1 and l2 indexed register spaces */
276
277static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
278{
279 u32 val;
280
281 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
282 pci_read_config_dword(iommu->dev, 0xfc, &val);
283 return val;
284}
285
286static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
287{
288 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
289 pci_write_config_dword(iommu->dev, 0xfc, val);
290 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
291}
292
293static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
294{
295 u32 val;
296
297 pci_write_config_dword(iommu->dev, 0xf0, address);
298 pci_read_config_dword(iommu->dev, 0xf4, &val);
299 return val;
300}
301
302static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
303{
304 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
305 pci_write_config_dword(iommu->dev, 0xf4, val);
306}
307
b65233a9
JR		 308/****************************************************************************
309 *
310 * AMD IOMMU MMIO register space handling functions
311 *
312 * These functions are used to program the IOMMU device registers in
313 * MMIO space required for that driver.
314 *
315 ****************************************************************************/
3e8064ba 316
b65233a9
JR		 317/*
318 * This function set the exclusion range in the IOMMU. DMA accesses to the
319 * exclusion range are passed through untranslated
320 */
05f92db9 321static void iommu_set_exclusion_range(struct amd_iommu *iommu)
b2026aa2
JR		 322{
323 u64 start = iommu->exclusion_start & PAGE_MASK;
324 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
325 u64 entry;
326
327 if (!iommu->exclusion_start)
328 return;
329
330 entry = start | MMIO_EXCL_ENABLE_MASK;
331 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
332 &entry, sizeof(entry));
333
334 entry = limit;
335 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
336 &entry, sizeof(entry));
337}
338
b65233a9 339/* Programs the physical address of the device table into the IOMMU hardware */
6b7f000e 340static void iommu_set_device_table(struct amd_iommu *iommu)
b2026aa2 341{
f609891f 342 u64 entry;
b2026aa2
JR		 343
344 BUG_ON(iommu->mmio_base == NULL);
345
346 entry = virt_to_phys(amd_iommu_dev_table);
347 entry |= (dev_table_size >> 12) - 1;
348 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
349 &entry, sizeof(entry));
350}
351
b65233a9 352/* Generic functions to enable/disable certain features of the IOMMU. */
05f92db9 353static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 354{
355 u32 ctrl;
356
357 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
358 ctrl |= (1 << bit);
359 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
360}
361
ca020711 362static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 363{
364 u32 ctrl;
365
199d0d50 366 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
b2026aa2
JR		 367 ctrl &= ~(1 << bit);
368 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
369}
370
1456e9d2
JR		 371static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
372{
373 u32 ctrl;
374
375 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
376 ctrl &= ~CTRL_INV_TO_MASK;
377 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
378 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
379}
380
b65233a9 381/* Function to enable the hardware */
05f92db9 382static void iommu_enable(struct amd_iommu *iommu)
b2026aa2 383{
b2026aa2 384 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
b2026aa2
JR		 385}
386
92ac4320 387static void iommu_disable(struct amd_iommu *iommu)
126c52be 388{
a8c485bb
CW		 389 /* Disable command buffer */
390 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
391
392 /* Disable event logging and event interrupts */
393 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
394 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
395
8bda0cfb
SS		 396 /* Disable IOMMU GA_LOG */
397 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
398 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
399
a8c485bb 400 /* Disable IOMMU hardware itself */
92ac4320 401 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
126c52be
JR		 402}
403
b65233a9
JR		 404/*
405 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
406 * the system has one.
407 */
30861ddc 408static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
6c56747b 409{
30861ddc
SK		 410 if (!request_mem_region(address, end, "amd_iommu")) {
411 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
412 address, end);
e82752d8 413 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
6c56747b 414 return NULL;
e82752d8 415 }
6c56747b 416
30861ddc 417 return (u8 __iomem *)ioremap_nocache(address, end);
6c56747b
JR		 418}
419
420static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
421{
422 if (iommu->mmio_base)
423 iounmap(iommu->mmio_base);
30861ddc 424 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
6c56747b
JR		 425}
426
ac7ccf67
SS		 427static inline u32 get_ivhd_header_size(struct ivhd_header *h)
428{
429 u32 size = 0;
430
431 switch (h->type) {
432 case 0x10:
433 size = 24;
434 break;
435 case 0x11:
436 case 0x40:
437 size = 40;
438 break;
439 }
440 return size;
441}
442
b65233a9
JR		 443/****************************************************************************
444 *
445 * The functions below belong to the first pass of AMD IOMMU ACPI table
446 * parsing. In this pass we try to find out the highest device id this
447 * code has to handle. Upon this information the size of the shared data
448 * structures is determined later.
449 *
450 ****************************************************************************/
451
b514e555
JR		 452/*
453 * This function calculates the length of a given IVHD entry
454 */
455static inline int ivhd_entry_length(u8 *ivhd)
456{
8c7142f5
SS		 457 u32 type = ((struct ivhd_entry *)ivhd)->type;
458
459 if (type < 0x80) {
460 return 0x04 << (*ivhd >> 6);
461 } else if (type == IVHD_DEV_ACPI_HID) {
462 /* For ACPI_HID, offset 21 is uid len */
463 return *((u8 *)ivhd + 21) + 22;
464 }
465 return 0;
b514e555
JR		 466}
467
b65233a9
JR		 468/*
469 * After reading the highest device id from the IOMMU PCI capability header
470 * this function looks if there is a higher device id defined in the ACPI table
471 */
3e8064ba
JR		 472static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
473{
474 u8 *p = (void *)h, *end = (void *)h;
475 struct ivhd_entry *dev;
476
ac7ccf67
SS		 477 u32 ivhd_size = get_ivhd_header_size(h);
478
479 if (!ivhd_size) {
480 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
481 return -EINVAL;
482 }
483
484 p += ivhd_size;
3e8064ba
JR		 485 end += h->length;
486
3e8064ba
JR		 487 while (p < end) {
488 dev = (struct ivhd_entry *)p;
489 switch (dev->type) {
d1259416
JR		 490 case IVHD_DEV_ALL:
491 /* Use maximum BDF value for DEV_ALL */
492 update_last_devid(0xffff);
493 break;
3e8064ba
JR		 494 case IVHD_DEV_SELECT:
495 case IVHD_DEV_RANGE_END:
496 case IVHD_DEV_ALIAS:
497 case IVHD_DEV_EXT_SELECT:
b65233a9 498 /* all the above subfield types refer to device ids */
208ec8c9 499 update_last_devid(dev->devid);
3e8064ba
JR		 500 break;
501 default:
502 break;
503 }
b514e555 504 p += ivhd_entry_length(p);
3e8064ba
JR		 505 }
506
507 WARN_ON(p != end);
508
509 return 0;
510}
511
8c7142f5
SS		 512static int __init check_ivrs_checksum(struct acpi_table_header *table)
513{
514 int i;
515 u8 checksum = 0, *p = (u8 *)table;
516
517 for (i = 0; i < table->length; ++i)
518 checksum += p[i];
519 if (checksum != 0) {
520 /* ACPI table corrupt */
521 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
522 return -ENODEV;
523 }
524
525 return 0;
526}
527
b65233a9
JR		 528/*
529 * Iterate over all IVHD entries in the ACPI table and find the highest device
530 * id which we need to handle. This is the first of three functions which parse
531 * the ACPI table. So we check the checksum here.
532 */
3e8064ba
JR		 533static int __init find_last_devid_acpi(struct acpi_table_header *table)
534{
8c7142f5 535 u8 *p = (u8 *)table, *end = (u8 *)table;
3e8064ba
JR		 536 struct ivhd_header *h;
537
3e8064ba
JR		 538 p += IVRS_HEADER_LENGTH;
539
540 end += table->length;
541 while (p < end) {
542 h = (struct ivhd_header *)p;
8c7142f5
SS		 543 if (h->type == amd_iommu_target_ivhd_type) {
544 int ret = find_last_devid_from_ivhd(h);
545
546 if (ret)
547 return ret;
3e8064ba
JR		 548 }
549 p += h->length;
550 }
551 WARN_ON(p != end);
552
553 return 0;
554}
555
b65233a9
JR		 556/****************************************************************************
557 *
df805abb 558 * The following functions belong to the code path which parses the ACPI table
b65233a9
JR		 559 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
560 * data structures, initialize the device/alias/rlookup table and also
561 * basically initialize the hardware.
562 *
563 ****************************************************************************/
564
565/*
566 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
567 * write commands to that buffer later and the IOMMU will execute them
568 * asynchronously
569 */
f2c2db53 570static int __init alloc_command_buffer(struct amd_iommu *iommu)
b36ca91e 571{
f2c2db53
JR		 572 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
573 get_order(CMD_BUFFER_SIZE));
b36ca91e 574
f2c2db53 575 return iommu->cmd_buf ? 0 : -ENOMEM;
58492e12
JR		 576}
577
93f1cc67
JR		 578/*
579 * This function resets the command buffer if the IOMMU stopped fetching
580 * commands from it.
581 */
582void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
583{
584 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
585
586 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
587 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
588
589 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
590}
591
58492e12
JR		 592/*
593 * This function writes the command buffer address to the hardware and
594 * enables it.
595 */
596static void iommu_enable_command_buffer(struct amd_iommu *iommu)
597{
598 u64 entry;
599
600 BUG_ON(iommu->cmd_buf == NULL);
601
602 entry = (u64)virt_to_phys(iommu->cmd_buf);
b36ca91e 603 entry |= MMIO_CMD_SIZE_512;
58492e12 604
b36ca91e 605 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
58492e12 606 &entry, sizeof(entry));
b36ca91e 607
93f1cc67 608 amd_iommu_reset_cmd_buffer(iommu);
b36ca91e
JR		 609}
610
611static void __init free_command_buffer(struct amd_iommu *iommu)
612{
deba4bce 613 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
b36ca91e
JR		 614}
615
335503e5 616/* allocates the memory where the IOMMU will log its events to */
f2c2db53 617static int __init alloc_event_buffer(struct amd_iommu *iommu)
335503e5 618{
f2c2db53
JR		 619 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
620 get_order(EVT_BUFFER_SIZE));
335503e5 621
f2c2db53 622 return iommu->evt_buf ? 0 : -ENOMEM;
58492e12
JR		 623}
624
625static void iommu_enable_event_buffer(struct amd_iommu *iommu)
626{
627 u64 entry;
628
629 BUG_ON(iommu->evt_buf == NULL);
630
335503e5 631 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
58492e12 632
335503e5
JR		 633 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
634 &entry, sizeof(entry));
635
09067207
JR		 636 /* set head and tail to zero manually */
637 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
638 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
639
58492e12 640 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
335503e5
JR		 641}
642
643static void __init free_event_buffer(struct amd_iommu *iommu)
644{
645 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
646}
647
1a29ac01 648/* allocates the memory where the IOMMU will log its events to */
f2c2db53 649static int __init alloc_ppr_log(struct amd_iommu *iommu)
1a29ac01 650{
f2c2db53
JR		 651 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
652 get_order(PPR_LOG_SIZE));
1a29ac01 653
f2c2db53 654 return iommu->ppr_log ? 0 : -ENOMEM;
1a29ac01
JR		 655}
656
657static void iommu_enable_ppr_log(struct amd_iommu *iommu)
658{
659 u64 entry;
660
661 if (iommu->ppr_log == NULL)
662 return;
663
664 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
665
666 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
667 &entry, sizeof(entry));
668
669 /* set head and tail to zero manually */
670 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
671 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
672
673 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
674 iommu_feature_enable(iommu, CONTROL_PPR_EN);
675}
676
677static void __init free_ppr_log(struct amd_iommu *iommu)
678{
679 if (iommu->ppr_log == NULL)
680 return;
681
682 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
683}
684
8bda0cfb
SS		 685static void free_ga_log(struct amd_iommu *iommu)
686{
687#ifdef CONFIG_IRQ_REMAP
688 if (iommu->ga_log)
689 free_pages((unsigned long)iommu->ga_log,
690 get_order(GA_LOG_SIZE));
691 if (iommu->ga_log_tail)
692 free_pages((unsigned long)iommu->ga_log_tail,
693 get_order(8));
694#endif
695}
696
697static int iommu_ga_log_enable(struct amd_iommu *iommu)
698{
699#ifdef CONFIG_IRQ_REMAP
700 u32 status, i;
701
702 if (!iommu->ga_log)
703 return -EINVAL;
704
705 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
706
707 /* Check if already running */
708 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
709 return 0;
710
711 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
712 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
713
714 for (i = 0; i < LOOP_TIMEOUT; ++i) {
715 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
716 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
717 break;
718 }
719
720 if (i >= LOOP_TIMEOUT)
721 return -EINVAL;
722#endif /* CONFIG_IRQ_REMAP */
723 return 0;
724}
725
726#ifdef CONFIG_IRQ_REMAP
727static int iommu_init_ga_log(struct amd_iommu *iommu)
728{
729 u64 entry;
730
731 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
732 return 0;
733
734 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
735 get_order(GA_LOG_SIZE));
736 if (!iommu->ga_log)
737 goto err_out;
738
739 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
740 get_order(8));
741 if (!iommu->ga_log_tail)
742 goto err_out;
743
744 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
745 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
746 &entry, sizeof(entry));
747 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
748 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
749 &entry, sizeof(entry));
750 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
751 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
752
753 return 0;
754err_out:
755 free_ga_log(iommu);
756 return -EINVAL;
757}
758#endif /* CONFIG_IRQ_REMAP */
759
760static int iommu_init_ga(struct amd_iommu *iommu)
761{
762 int ret = 0;
763
764#ifdef CONFIG_IRQ_REMAP
765 /* Note: We have already checked GASup from IVRS table.
766 * Now, we need to make sure that GAMSup is set.
767 */
768 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
769 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
770 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
771
772 ret = iommu_init_ga_log(iommu);
773#endif /* CONFIG_IRQ_REMAP */
774
775 return ret;
776}
777
cbc33a90
JR		 778static void iommu_enable_gt(struct amd_iommu *iommu)
779{
780 if (!iommu_feature(iommu, FEATURE_GT))
781 return;
782
783 iommu_feature_enable(iommu, CONTROL_GT_EN);
784}
785
b65233a9 786/* sets a specific bit in the device table entry. */
3566b778
JR		 787static void set_dev_entry_bit(u16 devid, u8 bit)
788{
ee6c2868
JR		 789 int i = (bit >> 6) & 0x03;
790 int _bit = bit & 0x3f;
3566b778 791
ee6c2868 792 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
3566b778
JR		 793}
794
c5cca146
JR		 795static int get_dev_entry_bit(u16 devid, u8 bit)
796{
ee6c2868
JR		 797 int i = (bit >> 6) & 0x03;
798 int _bit = bit & 0x3f;
c5cca146 799
ee6c2868 800 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
c5cca146
JR		 801}
802
803
804void amd_iommu_apply_erratum_63(u16 devid)
805{
806 int sysmgt;
807
808 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
809 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
810
811 if (sysmgt == 0x01)
812 set_dev_entry_bit(devid, DEV_ENTRY_IW);
813}
814
5ff4789d
JR		 815/* Writes the specific IOMMU for a device into the rlookup table */
816static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
817{
818 amd_iommu_rlookup_table[devid] = iommu;
819}
820
b65233a9
JR		 821/*
822 * This function takes the device specific flags read from the ACPI
823 * table and sets up the device table entry with that information
824 */
5ff4789d
JR		 825static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
826 u16 devid, u32 flags, u32 ext_flags)
3566b778
JR		 827{
828 if (flags & ACPI_DEVFLAG_INITPASS)
829 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
830 if (flags & ACPI_DEVFLAG_EXTINT)
831 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
832 if (flags & ACPI_DEVFLAG_NMI)
833 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
834 if (flags & ACPI_DEVFLAG_SYSMGT1)
835 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
836 if (flags & ACPI_DEVFLAG_SYSMGT2)
837 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
838 if (flags & ACPI_DEVFLAG_LINT0)
839 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
840 if (flags & ACPI_DEVFLAG_LINT1)
841 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
3566b778 842
c5cca146
JR		 843 amd_iommu_apply_erratum_63(devid);
844
5ff4789d 845 set_iommu_for_device(iommu, devid);
3566b778
JR		 846}
847
c50e3247 848static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
6efed63b
JR		 849{
850 struct devid_map *entry;
851 struct list_head *list;
852
31cff67f
JR		 853 if (type == IVHD_SPECIAL_IOAPIC)
854 list = &ioapic_map;
855 else if (type == IVHD_SPECIAL_HPET)
856 list = &hpet_map;
857 else
6efed63b
JR		 858 return -EINVAL;
859
31cff67f
JR		 860 list_for_each_entry(entry, list, list) {
861 if (!(entry->id == id && entry->cmd_line))
862 continue;
863
864 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
865 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
866
c50e3247
JR		 867 *devid = entry->devid;
868
31cff67f
JR		 869 return 0;
870 }
871
6efed63b
JR		 872 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
873 if (!entry)
874 return -ENOMEM;
875
31cff67f 876 entry->id = id;
c50e3247 877 entry->devid = *devid;
31cff67f 878 entry->cmd_line = cmd_line;
6efed63b
JR		 879
880 list_add_tail(&entry->list, list);
881
882 return 0;
883}
884
2a0cb4e2
WZ		 885static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
886 bool cmd_line)
887{
888 struct acpihid_map_entry *entry;
889 struct list_head *list = &acpihid_map;
890
891 list_for_each_entry(entry, list, list) {
892 if (strcmp(entry->hid, hid) ||
893 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
894 !entry->cmd_line)
895 continue;
896
897 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
898 hid, uid);
899 *devid = entry->devid;
900 return 0;
901 }
902
903 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
904 if (!entry)
905 return -ENOMEM;
906
907 memcpy(entry->uid, uid, strlen(uid));
908 memcpy(entry->hid, hid, strlen(hid));
909 entry->devid = *devid;
910 entry->cmd_line = cmd_line;
911 entry->root_devid = (entry->devid & (~0x7));
912
913 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
914 entry->cmd_line ? "cmd" : "ivrs",
915 entry->hid, entry->uid, entry->root_devid);
916
917 list_add_tail(&entry->list, list);
918 return 0;
919}
920
235dacbc
JR		 921static int __init add_early_maps(void)
922{
923 int i, ret;
924
925 for (i = 0; i < early_ioapic_map_size; ++i) {
926 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
927 early_ioapic_map[i].id,
c50e3247 928 &early_ioapic_map[i].devid,
235dacbc
JR		 929 early_ioapic_map[i].cmd_line);
930 if (ret)
931 return ret;
932 }
933
934 for (i = 0; i < early_hpet_map_size; ++i) {
935 ret = add_special_device(IVHD_SPECIAL_HPET,
936 early_hpet_map[i].id,
c50e3247 937 &early_hpet_map[i].devid,
235dacbc
JR		 938 early_hpet_map[i].cmd_line);
939 if (ret)
940 return ret;
941 }
942
2a0cb4e2
WZ		 943 for (i = 0; i < early_acpihid_map_size; ++i) {
944 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
945 early_acpihid_map[i].uid,
946 &early_acpihid_map[i].devid,
947 early_acpihid_map[i].cmd_line);
948 if (ret)
949 return ret;
950 }
951
235dacbc
JR		 952 return 0;
953}
954
b65233a9 955/*
df805abb 956 * Reads the device exclusion range from ACPI and initializes the IOMMU with
b65233a9
JR		 957 * it
958 */
3566b778
JR		 959static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
960{
961 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
962
963 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
964 return;
965
966 if (iommu) {
b65233a9
JR		 967 /*
968 * We only can configure exclusion ranges per IOMMU, not
969 * per device. But we can enable the exclusion range per
970 * device. This is done here
971 */
2c16c9fd 972 set_dev_entry_bit(devid, DEV_ENTRY_EX);
3566b778
JR		 973 iommu->exclusion_start = m->range_start;
974 iommu->exclusion_length = m->range_length;
975 }
976}
977
b65233a9
JR		 978/*
979 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
980 * initializes the hardware and our data structures with it.
981 */
6efed63b 982static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
5d0c8e49
JR		 983 struct ivhd_header *h)
984{
985 u8 *p = (u8 *)h;
986 u8 *end = p, flags = 0;
0de66d5b
JR		 987 u16 devid = 0, devid_start = 0, devid_to = 0;
988 u32 dev_i, ext_flags = 0;
58a3bee5 989 bool alias = false;
5d0c8e49 990 struct ivhd_entry *e;
ac7ccf67 991 u32 ivhd_size;
235dacbc
JR		 992 int ret;
993
994
995 ret = add_early_maps();
996 if (ret)
997 return ret;
5d0c8e49
JR		 998
999 /*
e9bf5197 1000 * First save the recommended feature enable bits from ACPI
5d0c8e49 1001 */
e9bf5197 1002 iommu->acpi_flags = h->flags;
5d0c8e49
JR		 1003
1004 /*
1005 * Done. Now parse the device entries
1006 */
ac7ccf67
SS		 1007 ivhd_size = get_ivhd_header_size(h);
1008 if (!ivhd_size) {
1009 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1010 return -EINVAL;
1011 }
1012
1013 p += ivhd_size;
1014
5d0c8e49
JR		 1015 end += h->length;
1016
42a698f4 1017
5d0c8e49
JR		 1018 while (p < end) {
1019 e = (struct ivhd_entry *)p;
1020 switch (e->type) {
1021 case IVHD_DEV_ALL:
42a698f4 1022
226e889b 1023 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
42a698f4 1024
226e889b
JR		 1025 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1026 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
5d0c8e49
JR		 1027 break;
1028 case IVHD_DEV_SELECT:
42a698f4
JR		 1029
1030 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1031 "flags: %02x\n",
c5081cd7 1032 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1033 PCI_SLOT(e->devid),
1034 PCI_FUNC(e->devid),
1035 e->flags);
1036
5d0c8e49 1037 devid = e->devid;
5ff4789d 1038 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
5d0c8e49
JR		 1039 break;
1040 case IVHD_DEV_SELECT_RANGE_START:
42a698f4
JR		 1041
1042 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1043 "devid: %02x:%02x.%x flags: %02x\n",
c5081cd7 1044 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1045 PCI_SLOT(e->devid),
1046 PCI_FUNC(e->devid),
1047 e->flags);
1048
5d0c8e49
JR		 1049 devid_start = e->devid;
1050 flags = e->flags;
1051 ext_flags = 0;
58a3bee5 1052 alias = false;
5d0c8e49
JR		 1053 break;
1054 case IVHD_DEV_ALIAS:
42a698f4
JR		 1055
1056 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1057 "flags: %02x devid_to: %02x:%02x.%x\n",
c5081cd7 1058 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1059 PCI_SLOT(e->devid),
1060 PCI_FUNC(e->devid),
1061 e->flags,
c5081cd7 1062 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1063 PCI_SLOT(e->ext >> 8),
1064 PCI_FUNC(e->ext >> 8));
1065
5d0c8e49
JR		 1066 devid = e->devid;
1067 devid_to = e->ext >> 8;
7a6a3a08 1068 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
7455aab1 1069 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
5d0c8e49
JR		 1070 amd_iommu_alias_table[devid] = devid_to;
1071 break;
1072 case IVHD_DEV_ALIAS_RANGE:
42a698f4
JR		 1073
1074 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1075 "devid: %02x:%02x.%x flags: %02x "
1076 "devid_to: %02x:%02x.%x\n",
c5081cd7 1077 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1078 PCI_SLOT(e->devid),
1079 PCI_FUNC(e->devid),
1080 e->flags,
c5081cd7 1081 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1082 PCI_SLOT(e->ext >> 8),
1083 PCI_FUNC(e->ext >> 8));
1084
5d0c8e49
JR		 1085 devid_start = e->devid;
1086 flags = e->flags;
1087 devid_to = e->ext >> 8;
1088 ext_flags = 0;
58a3bee5 1089 alias = true;
5d0c8e49
JR		 1090 break;
1091 case IVHD_DEV_EXT_SELECT:
42a698f4
JR		 1092
1093 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1094 "flags: %02x ext: %08x\n",
c5081cd7 1095 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1096 PCI_SLOT(e->devid),
1097 PCI_FUNC(e->devid),
1098 e->flags, e->ext);
1099
5d0c8e49 1100 devid = e->devid;
5ff4789d
JR		 1101 set_dev_entry_from_acpi(iommu, devid, e->flags,
1102 e->ext);
5d0c8e49
JR		 1103 break;
1104 case IVHD_DEV_EXT_SELECT_RANGE:
42a698f4
JR		 1105
1106 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1107 "%02x:%02x.%x flags: %02x ext: %08x\n",
c5081cd7 1108 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1109 PCI_SLOT(e->devid),
1110 PCI_FUNC(e->devid),
1111 e->flags, e->ext);
1112
5d0c8e49
JR		 1113 devid_start = e->devid;
1114 flags = e->flags;
1115 ext_flags = e->ext;
58a3bee5 1116 alias = false;
5d0c8e49
JR		 1117 break;
1118 case IVHD_DEV_RANGE_END:
42a698f4
JR		 1119
1120 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
c5081cd7 1121 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1122 PCI_SLOT(e->devid),
1123 PCI_FUNC(e->devid));
1124
5d0c8e49
JR		 1125 devid = e->devid;
1126 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
7a6a3a08 1127 if (alias) {
5d0c8e49 1128 amd_iommu_alias_table[dev_i] = devid_to;
7a6a3a08
JR		 1129 set_dev_entry_from_acpi(iommu,
1130 devid_to, flags, ext_flags);
1131 }
1132 set_dev_entry_from_acpi(iommu, dev_i,
1133 flags, ext_flags);
5d0c8e49
JR		 1134 }
1135 break;
6efed63b
JR		 1136 case IVHD_DEV_SPECIAL: {
1137 u8 handle, type;
1138 const char *var;
1139 u16 devid;
1140 int ret;
1141
1142 handle = e->ext & 0xff;
1143 devid = (e->ext >> 8) & 0xffff;
1144 type = (e->ext >> 24) & 0xff;
1145
1146 if (type == IVHD_SPECIAL_IOAPIC)
1147 var = "IOAPIC";
1148 else if (type == IVHD_SPECIAL_HPET)
1149 var = "HPET";
1150 else
1151 var = "UNKNOWN";
1152
1153 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1154 var, (int)handle,
c5081cd7 1155 PCI_BUS_NUM(devid),
6efed63b
JR		 1156 PCI_SLOT(devid),
1157 PCI_FUNC(devid));
1158
c50e3247 1159 ret = add_special_device(type, handle, &devid, false);
6efed63b
JR		 1160 if (ret)
1161 return ret;
c50e3247
JR		 1162
1163 /*
1164 * add_special_device might update the devid in case a
1165 * command-line override is present. So call
1166 * set_dev_entry_from_acpi after add_special_device.
1167 */
1168 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1169
6efed63b
JR		 1170 break;
1171 }
2a0cb4e2
WZ		 1172 case IVHD_DEV_ACPI_HID: {
1173 u16 devid;
1174 u8 hid[ACPIHID_HID_LEN] = {0};
1175 u8 uid[ACPIHID_UID_LEN] = {0};
1176 int ret;
1177
1178 if (h->type != 0x40) {
1179 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1180 e->type);
1181 break;
1182 }
1183
1184 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1185 hid[ACPIHID_HID_LEN - 1] = '\0';
1186
1187 if (!(*hid)) {
1188 pr_err(FW_BUG "Invalid HID.\n");
1189 break;
1190 }
1191
1192 switch (e->uidf) {
1193 case UID_NOT_PRESENT:
1194
1195 if (e->uidl != 0)
1196 pr_warn(FW_BUG "Invalid UID length.\n");
1197
1198 break;
1199 case UID_IS_INTEGER:
1200
1201 sprintf(uid, "%d", e->uid);
1202
1203 break;
1204 case UID_IS_CHARACTER:
1205
1206 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1207 uid[ACPIHID_UID_LEN - 1] = '\0';
1208
1209 break;
1210 default:
1211 break;
1212 }
1213
6082ee72 1214 devid = e->devid;
2a0cb4e2
WZ		 1215 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1216 hid, uid,
1217 PCI_BUS_NUM(devid),
1218 PCI_SLOT(devid),
1219 PCI_FUNC(devid));
1220
2a0cb4e2
WZ		 1221 flags = e->flags;
1222
1223 ret = add_acpi_hid_device(hid, uid, &devid, false);
1224 if (ret)
1225 return ret;
1226
1227 /*
1228 * add_special_device might update the devid in case a
1229 * command-line override is present. So call
1230 * set_dev_entry_from_acpi after add_special_device.
1231 */
1232 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1233
1234 break;
1235 }
5d0c8e49
JR		 1236 default:
1237 break;
1238 }
1239
b514e555 1240 p += ivhd_entry_length(p);
5d0c8e49 1241 }
6efed63b
JR		 1242
1243 return 0;
5d0c8e49
JR		 1244}
1245
e47d402d
JR		 1246static void __init free_iommu_one(struct amd_iommu *iommu)
1247{
1248 free_command_buffer(iommu);
335503e5 1249 free_event_buffer(iommu);
1a29ac01 1250 free_ppr_log(iommu);
8bda0cfb 1251 free_ga_log(iommu);
e47d402d
JR		 1252 iommu_unmap_mmio_space(iommu);
1253}
1254
1255static void __init free_iommu_all(void)
1256{
1257 struct amd_iommu *iommu, *next;
1258
3bd22172 1259 for_each_iommu_safe(iommu, next) {
e47d402d
JR		 1260 list_del(&iommu->list);
1261 free_iommu_one(iommu);
1262 kfree(iommu);
1263 }
1264}
1265
318fe782
SS		 1266/*
1267 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1268 * Workaround:
1269 * BIOS should disable L2B micellaneous clock gating by setting
1270 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1271 */
e2f1a3bd 1272static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
318fe782
SS		 1273{
1274 u32 value;
1275
1276 if ((boot_cpu_data.x86 != 0x15) ||
1277 (boot_cpu_data.x86_model < 0x10) ||
1278 (boot_cpu_data.x86_model > 0x1f))
1279 return;
1280
1281 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1282 pci_read_config_dword(iommu->dev, 0xf4, &value);
1283
1284 if (value & BIT(2))
1285 return;
1286
1287 /* Select NB indirect register 0x90 and enable writing */
1288 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1289
1290 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1291 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1292 dev_name(&iommu->dev->dev));
1293
1294 /* Clear the enable writing bit */
1295 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1296}
1297
358875fd
JC		 1298/*
1299 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1300 * Workaround:
1301 * BIOS should enable ATS write permission check by setting
1302 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1303 */
1304static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1305{
1306 u32 value;
1307
1308 if ((boot_cpu_data.x86 != 0x15) ||
1309 (boot_cpu_data.x86_model < 0x30) ||
1310 (boot_cpu_data.x86_model > 0x3f))
1311 return;
1312
1313 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1314 value = iommu_read_l2(iommu, 0x47);
1315
1316 if (value & BIT(0))
1317 return;
1318
1319 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1320 iommu_write_l2(iommu, 0x47, value | BIT(0));
1321
1322 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1323 dev_name(&iommu->dev->dev));
1324}
1325
b65233a9
JR		 1326/*
1327 * This function clues the initialization function for one IOMMU
1328 * together and also allocates the command buffer and programs the
1329 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1330 */
e47d402d
JR		 1331static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1332{
6efed63b
JR		 1333 int ret;
1334
e47d402d 1335 spin_lock_init(&iommu->lock);
bb52777e
JR		 1336
1337 /* Add IOMMU to internal data structures */
e47d402d 1338 list_add_tail(&iommu->list, &amd_iommu_list);
bb52777e
JR		 1339 iommu->index = amd_iommus_present++;
1340
1341 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1342 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1343 return -ENOSYS;
1344 }
1345
1346 /* Index is fine - add IOMMU to the array */
1347 amd_iommus[iommu->index] = iommu;
e47d402d
JR		 1348
1349 /*
1350 * Copy data from ACPI table entry to the iommu struct
1351 */
23c742db 1352 iommu->devid = h->devid;
e47d402d 1353 iommu->cap_ptr = h->cap_ptr;
ee893c24 1354 iommu->pci_seg = h->pci_seg;
e47d402d 1355 iommu->mmio_phys = h->mmio_phys;
30861ddc 1356
7d7d38af
SS		 1357 switch (h->type) {
1358 case 0x10:
1359 /* Check if IVHD EFR contains proper max banks/counters */
1360 if ((h->efr_attr != 0) &&
1361 ((h->efr_attr & (0xF << 13)) != 0) &&
1362 ((h->efr_attr & (0x3F << 17)) != 0))
1363 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1364 else
1365 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1366 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1367 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1368 break;
1369 case 0x11:
1370 case 0x40:
1371 if (h->efr_reg & (1 << 9))
1372 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1373 else
1374 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1375 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1376 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1377 break;
1378 default:
1379 return -EINVAL;
30861ddc
SK		 1380 }
1381
1382 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1383 iommu->mmio_phys_end);
e47d402d
JR		 1384 if (!iommu->mmio_base)
1385 return -ENOMEM;
1386
f2c2db53 1387 if (alloc_command_buffer(iommu))
e47d402d
JR		 1388 return -ENOMEM;
1389
f2c2db53 1390 if (alloc_event_buffer(iommu))
335503e5
JR		 1391 return -ENOMEM;
1392
a80dc3e0
JR		 1393 iommu->int_enabled = false;
1394
6efed63b
JR		 1395 ret = init_iommu_from_acpi(iommu, h);
1396 if (ret)
1397 return ret;
f6fec00a 1398
7c71d306
JL		 1399 ret = amd_iommu_create_irq_domain(iommu);
1400 if (ret)
1401 return ret;
1402
f6fec00a
JR		 1403 /*
1404 * Make sure IOMMU is not considered to translate itself. The IVRS
1405 * table tells us so, but this is a lie!
1406 */
1407 amd_iommu_rlookup_table[iommu->devid] = NULL;
1408
23c742db 1409 return 0;
e47d402d
JR		 1410}
1411
8c7142f5
SS		 1412/**
1413 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1414 * @ivrs Pointer to the IVRS header
1415 *
1416 * This function search through all IVDB of the maximum supported IVHD
1417 */
1418static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1419{
1420 u8 *base = (u8 *)ivrs;
1421 struct ivhd_header *ivhd = (struct ivhd_header *)
1422 (base + IVRS_HEADER_LENGTH);
1423 u8 last_type = ivhd->type;
1424 u16 devid = ivhd->devid;
1425
1426 while (((u8 *)ivhd - base < ivrs->length) &&
1427 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1428 u8 *p = (u8 *) ivhd;
1429
1430 if (ivhd->devid == devid)
1431 last_type = ivhd->type;
1432 ivhd = (struct ivhd_header *)(p + ivhd->length);
1433 }
1434
1435 return last_type;
1436}
1437
b65233a9
JR		 1438/*
1439 * Iterates over all IOMMU entries in the ACPI table, allocates the
1440 * IOMMU structure and initializes it with init_iommu_one()
1441 */
e47d402d
JR		 1442static int __init init_iommu_all(struct acpi_table_header *table)
1443{
1444 u8 *p = (u8 *)table, *end = (u8 *)table;
1445 struct ivhd_header *h;
1446 struct amd_iommu *iommu;
1447 int ret;
1448
e47d402d
JR		 1449 end += table->length;
1450 p += IVRS_HEADER_LENGTH;
1451
1452 while (p < end) {
1453 h = (struct ivhd_header *)p;
8c7142f5 1454 if (*p == amd_iommu_target_ivhd_type) {
9c72041f 1455
ae908c22 1456 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
9c72041f 1457 "seg: %d flags: %01x info %04x\n",
c5081cd7 1458 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
9c72041f
JR		 1459 PCI_FUNC(h->devid), h->cap_ptr,
1460 h->pci_seg, h->flags, h->info);
1461 DUMP_printk(" mmio-addr: %016llx\n",
1462 h->mmio_phys);
1463
e47d402d 1464 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
02f3b3f5
JR		 1465 if (iommu == NULL)
1466 return -ENOMEM;
3551a708 1467
e47d402d 1468 ret = init_iommu_one(iommu, h);
02f3b3f5
JR		 1469 if (ret)
1470 return ret;
e47d402d
JR		 1471 }
1472 p += h->length;
1473
1474 }
1475 WARN_ON(p != end);
1476
1477 return 0;
1478}
1479
30861ddc
SK		 1480
1481static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1482{
1483 u64 val = 0xabcd, val2 = 0;
1484
1485 if (!iommu_feature(iommu, FEATURE_PC))
1486 return;
1487
1488 amd_iommu_pc_present = true;
1489
1490 /* Check if the performance counters can be written to */
38e45d02
SS		 1491 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1492 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
30861ddc
SK		 1493 (val != val2)) {
1494 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1495 amd_iommu_pc_present = false;
1496 return;
1497 }
1498
1499 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1500
1501 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1502 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1503 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1504}
1505
066f2e98
AW		 1506static ssize_t amd_iommu_show_cap(struct device *dev,
1507 struct device_attribute *attr,
1508 char *buf)
1509{
1510 struct amd_iommu *iommu = dev_get_drvdata(dev);
1511 return sprintf(buf, "%x\n", iommu->cap);
1512}
1513static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1514
1515static ssize_t amd_iommu_show_features(struct device *dev,
1516 struct device_attribute *attr,
1517 char *buf)
1518{
1519 struct amd_iommu *iommu = dev_get_drvdata(dev);
1520 return sprintf(buf, "%llx\n", iommu->features);
1521}
1522static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1523
1524static struct attribute *amd_iommu_attrs[] = {
1525 &dev_attr_cap.attr,
1526 &dev_attr_features.attr,
1527 NULL,
1528};
1529
1530static struct attribute_group amd_iommu_group = {
1531 .name = "amd-iommu",
1532 .attrs = amd_iommu_attrs,
1533};
1534
1535static const struct attribute_group *amd_iommu_groups[] = {
1536 &amd_iommu_group,
1537 NULL,
1538};
30861ddc 1539
23c742db
JR		 1540static int iommu_init_pci(struct amd_iommu *iommu)
1541{
1542 int cap_ptr = iommu->cap_ptr;
1543 u32 range, misc, low, high;
8bda0cfb 1544 int ret;
23c742db 1545
c5081cd7 1546 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
23c742db
JR		 1547 iommu->devid & 0xff);
1548 if (!iommu->dev)
1549 return -ENODEV;
1550
cbbc00be
JL		 1551 /* Prevent binding other PCI device drivers to IOMMU devices */
1552 iommu->dev->match_driver = false;
1553
23c742db
JR		 1554 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1555 &iommu->cap);
1556 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1557 &range);
1558 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1559 &misc);
1560
23c742db
JR		 1561 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1562 amd_iommu_iotlb_sup = false;
1563
1564 /* read extended feature bits */
1565 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1566 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1567
1568 iommu->features = ((u64)high << 32) | low;
1569
1570 if (iommu_feature(iommu, FEATURE_GT)) {
1571 int glxval;
a919a018
SS		 1572 u32 max_pasid;
1573 u64 pasmax;
23c742db 1574
a919a018
SS		 1575 pasmax = iommu->features & FEATURE_PASID_MASK;
1576 pasmax >>= FEATURE_PASID_SHIFT;
1577 max_pasid = (1 << (pasmax + 1)) - 1;
23c742db 1578
a919a018
SS		 1579 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1580
1581 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
23c742db
JR		 1582
1583 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1584 glxval >>= FEATURE_GLXVAL_SHIFT;
1585
1586 if (amd_iommu_max_glx_val == -1)
1587 amd_iommu_max_glx_val = glxval;
1588 else
1589 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1590 }
1591
1592 if (iommu_feature(iommu, FEATURE_GT) &&
1593 iommu_feature(iommu, FEATURE_PPR)) {
1594 iommu->is_iommu_v2 = true;
1595 amd_iommu_v2_present = true;
1596 }
1597
f2c2db53
JR		 1598 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1599 return -ENOMEM;
23c742db 1600
8bda0cfb
SS		 1601 ret = iommu_init_ga(iommu);
1602 if (ret)
1603 return ret;
3928aa3f 1604
23c742db
JR		 1605 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1606 amd_iommu_np_cache = true;
1607
30861ddc
SK		 1608 init_iommu_perf_ctr(iommu);
1609
23c742db
JR		 1610 if (is_rd890_iommu(iommu->dev)) {
1611 int i, j;
1612
1613 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1614 PCI_DEVFN(0, 0));
1615
1616 /*
1617 * Some rd890 systems may not be fully reconfigured by the
1618 * BIOS, so it's necessary for us to store this information so
1619 * it can be reprogrammed on resume
1620 */
1621 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1622 &iommu->stored_addr_lo);
1623 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1624 &iommu->stored_addr_hi);
1625
1626 /* Low bit locks writes to configuration space */
1627 iommu->stored_addr_lo &= ~1;
1628
1629 for (i = 0; i < 6; i++)
1630 for (j = 0; j < 0x12; j++)
1631 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1632
1633 for (i = 0; i < 0x83; i++)
1634 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1635 }
1636
318fe782 1637 amd_iommu_erratum_746_workaround(iommu);
358875fd 1638 amd_iommu_ats_write_check_workaround(iommu);
318fe782 1639
39ab9555
JR		 1640 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1641 amd_iommu_groups, "ivhd%d", iommu->index);
b0119e87
JR		 1642 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1643 iommu_device_register(&iommu->iommu);
066f2e98 1644
23c742db
JR		 1645 return pci_enable_device(iommu->dev);
1646}
1647
4d121c32
JR		 1648static void print_iommu_info(void)
1649{
1650 static const char * const feat_str[] = {
1651 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1652 "IA", "GA", "HE", "PC"
1653 };
1654 struct amd_iommu *iommu;
1655
1656 for_each_iommu(iommu) {
1657 int i;
1658
1659 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1660 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1661
1662 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
3928aa3f
SS		 1663 pr_info("AMD-Vi: Extended features (%#llx):\n",
1664 iommu->features);
2bd5ed00 1665 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
4d121c32
JR		 1666 if (iommu_feature(iommu, (1ULL << i)))
1667 pr_cont(" %s", feat_str[i]);
1668 }
3928aa3f
SS		 1669
1670 if (iommu->features & FEATURE_GAM_VAPIC)
1671 pr_cont(" GA_vAPIC");
1672
30861ddc 1673 pr_cont("\n");
500c25ed 1674 }
4d121c32 1675 }
3928aa3f 1676 if (irq_remapping_enabled) {
ebe60bbf 1677 pr_info("AMD-Vi: Interrupt remapping enabled\n");
3928aa3f
SS		 1678 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1679 pr_info("AMD-Vi: virtual APIC enabled\n");
1680 }
4d121c32
JR		 1681}
1682
2c0ae172 1683static int __init amd_iommu_init_pci(void)
23c742db
JR		 1684{
1685 struct amd_iommu *iommu;
1686 int ret = 0;
1687
1688 for_each_iommu(iommu) {
1689 ret = iommu_init_pci(iommu);
1690 if (ret)
1691 break;
1692 }
1693
522e5cb7
JR		 1694 /*
1695 * Order is important here to make sure any unity map requirements are
1696 * fulfilled. The unity mappings are created and written to the device
1697 * table during the amd_iommu_init_api() call.
1698 *
1699 * After that we call init_device_table_dma() to make sure any
1700 * uninitialized DTE will block DMA, and in the end we flush the caches
1701 * of all IOMMUs to make sure the changes to the device table are
1702 * active.
1703 */
1704 ret = amd_iommu_init_api();
1705
aafd8ba0
JR		 1706 init_device_table_dma();
1707
1708 for_each_iommu(iommu)
1709 iommu_flush_all_caches(iommu);
1710
3a18404c
JR		 1711 if (!ret)
1712 print_iommu_info();
4d121c32 1713
23c742db
JR		 1714 return ret;
1715}
1716
a80dc3e0
JR		 1717/****************************************************************************
1718 *
1719 * The following functions initialize the MSI interrupts for all IOMMUs
df805abb 1720 * in the system. It's a bit challenging because there could be multiple
a80dc3e0
JR		 1721 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1722 * pci_dev.
1723 *
1724 ****************************************************************************/
1725
9f800de3 1726static int iommu_setup_msi(struct amd_iommu *iommu)
a80dc3e0
JR		 1727{
1728 int r;
a80dc3e0 1729
9ddd592a
JR		 1730 r = pci_enable_msi(iommu->dev);
1731 if (r)
1732 return r;
a80dc3e0 1733
72fe00f0
JR		 1734 r = request_threaded_irq(iommu->dev->irq,
1735 amd_iommu_int_handler,
1736 amd_iommu_int_thread,
1737 0, "AMD-Vi",
3f398bc7 1738 iommu);
a80dc3e0
JR		 1739
1740 if (r) {
1741 pci_disable_msi(iommu->dev);
9ddd592a 1742 return r;
a80dc3e0
JR		 1743 }
1744
fab6afa3 1745 iommu->int_enabled = true;
1a29ac01 1746
a80dc3e0
JR		 1747 return 0;
1748}
1749
05f92db9 1750static int iommu_init_msi(struct amd_iommu *iommu)
a80dc3e0 1751{
9ddd592a
JR		 1752 int ret;
1753
a80dc3e0 1754 if (iommu->int_enabled)
9ddd592a 1755 goto enable_faults;
a80dc3e0 1756
82fcfc67 1757 if (iommu->dev->msi_cap)
9ddd592a
JR		 1758 ret = iommu_setup_msi(iommu);
1759 else
1760 ret = -ENODEV;
1761
1762 if (ret)
1763 return ret;
a80dc3e0 1764
9ddd592a
JR		 1765enable_faults:
1766 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
a80dc3e0 1767
9ddd592a
JR		 1768 if (iommu->ppr_log != NULL)
1769 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1770
8bda0cfb
SS		 1771 iommu_ga_log_enable(iommu);
1772
9ddd592a 1773 return 0;
a80dc3e0
JR		 1774}
1775
b65233a9
JR		 1776/****************************************************************************
1777 *
1778 * The next functions belong to the third pass of parsing the ACPI
1779 * table. In this last pass the memory mapping requirements are
df805abb 1780 * gathered (like exclusion and unity mapping ranges).
b65233a9
JR		 1781 *
1782 ****************************************************************************/
1783
be2a022c
JR		 1784static void __init free_unity_maps(void)
1785{
1786 struct unity_map_entry *entry, *next;
1787
1788 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1789 list_del(&entry->list);
1790 kfree(entry);
1791 }
1792}
1793
b65233a9 1794/* called when we find an exclusion range definition in ACPI */
be2a022c
JR		 1795static int __init init_exclusion_range(struct ivmd_header *m)
1796{
1797 int i;
1798
1799 switch (m->type) {
1800 case ACPI_IVMD_TYPE:
1801 set_device_exclusion_range(m->devid, m);
1802 break;
1803 case ACPI_IVMD_TYPE_ALL:
3a61ec38 1804 for (i = 0; i <= amd_iommu_last_bdf; ++i)
be2a022c
JR		 1805 set_device_exclusion_range(i, m);
1806 break;
1807 case ACPI_IVMD_TYPE_RANGE:
1808 for (i = m->devid; i <= m->aux; ++i)
1809 set_device_exclusion_range(i, m);
1810 break;
1811 default:
1812 break;
1813 }
1814
1815 return 0;
1816}
1817
b65233a9 1818/* called for unity map ACPI definition */
be2a022c
JR		 1819static int __init init_unity_map_range(struct ivmd_header *m)
1820{
98f1ad25 1821 struct unity_map_entry *e = NULL;
02acc43a 1822 char *s;
be2a022c
JR		 1823
1824 e = kzalloc(sizeof(*e), GFP_KERNEL);
1825 if (e == NULL)
1826 return -ENOMEM;
1827
1828 switch (m->type) {
1829 default:
0bc252f4
JR		 1830 kfree(e);
1831 return 0;
be2a022c 1832 case ACPI_IVMD_TYPE:
02acc43a 1833 s = "IVMD_TYPEi\t\t\t";
be2a022c
JR		 1834 e->devid_start = e->devid_end = m->devid;
1835 break;
1836 case ACPI_IVMD_TYPE_ALL:
02acc43a 1837 s = "IVMD_TYPE_ALL\t\t";
be2a022c
JR		 1838 e->devid_start = 0;
1839 e->devid_end = amd_iommu_last_bdf;
1840 break;
1841 case ACPI_IVMD_TYPE_RANGE:
02acc43a 1842 s = "IVMD_TYPE_RANGE\t\t";
be2a022c
JR		 1843 e->devid_start = m->devid;
1844 e->devid_end = m->aux;
1845 break;
1846 }
1847 e->address_start = PAGE_ALIGN(m->range_start);
1848 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1849 e->prot = m->flags >> 1;
1850
02acc43a
JR		 1851 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1852 " range_start: %016llx range_end: %016llx flags: %x\n", s,
c5081cd7
SK		 1853 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1854 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
02acc43a
JR		 1855 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1856 e->address_start, e->address_end, m->flags);
1857
be2a022c
JR		 1858 list_add_tail(&e->list, &amd_iommu_unity_map);
1859
1860 return 0;
1861}
1862
b65233a9 1863/* iterates over all memory definitions we find in the ACPI table */
be2a022c
JR		 1864static int __init init_memory_definitions(struct acpi_table_header *table)
1865{
1866 u8 *p = (u8 *)table, *end = (u8 *)table;
1867 struct ivmd_header *m;
1868
be2a022c
JR		 1869 end += table->length;
1870 p += IVRS_HEADER_LENGTH;
1871
1872 while (p < end) {
1873 m = (struct ivmd_header *)p;
1874 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1875 init_exclusion_range(m);
1876 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1877 init_unity_map_range(m);
1878
1879 p += m->length;
1880 }
1881
1882 return 0;
1883}
1884
9f5f5fb3
JR		 1885/*
1886 * Init the device table to not allow DMA access for devices and
1887 * suppress all page faults
1888 */
33f28c59 1889static void init_device_table_dma(void)
9f5f5fb3 1890{
0de66d5b 1891 u32 devid;
9f5f5fb3
JR		 1892
1893 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1894 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1895 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
9f5f5fb3
JR		 1896 }
1897}
1898
d04e0ba3
JR		 1899static void __init uninit_device_table_dma(void)
1900{
1901 u32 devid;
1902
1903 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1904 amd_iommu_dev_table[devid].data[0] = 0ULL;
1905 amd_iommu_dev_table[devid].data[1] = 0ULL;
1906 }
1907}
1908
33f28c59
JR		 1909static void init_device_table(void)
1910{
1911 u32 devid;
1912
1913 if (!amd_iommu_irq_remap)
1914 return;
1915
1916 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1917 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1918}
1919
e9bf5197
JR		 1920static void iommu_init_flags(struct amd_iommu *iommu)
1921{
1922 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1923 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1924 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1925
1926 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1927 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1928 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1929
1930 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1931 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1932 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1933
1934 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1935 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1936 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1937
1938 /*
1939 * make IOMMU memory accesses cache coherent
1940 */
1941 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1456e9d2
JR		 1942
1943 /* Set IOTLB invalidation timeout to 1s */
1944 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
e9bf5197
JR		 1945}
1946
5bcd757f 1947static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
4c894f47 1948{
5bcd757f
MG		 1949 int i, j;
1950 u32 ioc_feature_control;
c1bf94ec 1951 struct pci_dev *pdev = iommu->root_pdev;
5bcd757f
MG		 1952
1953 /* RD890 BIOSes may not have completely reconfigured the iommu */
c1bf94ec 1954 if (!is_rd890_iommu(iommu->dev) || !pdev)
5bcd757f
MG		 1955 return;
1956
1957 /*
1958 * First, we need to ensure that the iommu is enabled. This is
1959 * controlled by a register in the northbridge
1960 */
5bcd757f
MG		 1961
1962 /* Select Northbridge indirect register 0x75 and enable writing */
1963 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1964 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1965
1966 /* Enable the iommu */
1967 if (!(ioc_feature_control & 0x1))
1968 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1969
5bcd757f
MG		 1970 /* Restore the iommu BAR */
1971 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1972 iommu->stored_addr_lo);
1973 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1974 iommu->stored_addr_hi);
1975
1976 /* Restore the l1 indirect regs for each of the 6 l1s */
1977 for (i = 0; i < 6; i++)
1978 for (j = 0; j < 0x12; j++)
1979 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1980
1981 /* Restore the l2 indirect regs */
1982 for (i = 0; i < 0x83; i++)
1983 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1984
1985 /* Lock PCI setup registers */
1986 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1987 iommu->stored_addr_lo | 1);
4c894f47
JR		 1988}
1989
3928aa3f
SS		 1990static void iommu_enable_ga(struct amd_iommu *iommu)
1991{
1992#ifdef CONFIG_IRQ_REMAP
1993 switch (amd_iommu_guest_ir) {
1994 case AMD_IOMMU_GUEST_IR_VAPIC:
1995 iommu_feature_enable(iommu, CONTROL_GAM_EN);
1996 /* Fall through */
1997 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
1998 iommu_feature_enable(iommu, CONTROL_GA_EN);
77bdab46 1999 iommu->irte_ops = &irte_128_ops;
3928aa3f
SS		 2000 break;
2001 default:
77bdab46 2002 iommu->irte_ops = &irte_32_ops;
3928aa3f
SS		 2003 break;
2004 }
2005#endif
2006}
2007
b65233a9
JR		 2008/*
2009 * This function finally enables all IOMMUs found in the system after
2010 * they have been initialized
2011 */
11ee5ac4 2012static void early_enable_iommus(void)
8736197b
JR		 2013{
2014 struct amd_iommu *iommu;
2015
3bd22172 2016 for_each_iommu(iommu) {
a8c485bb 2017 iommu_disable(iommu);
e9bf5197 2018 iommu_init_flags(iommu);
58492e12
JR		 2019 iommu_set_device_table(iommu);
2020 iommu_enable_command_buffer(iommu);
2021 iommu_enable_event_buffer(iommu);
8736197b 2022 iommu_set_exclusion_range(iommu);
3928aa3f 2023 iommu_enable_ga(iommu);
8736197b 2024 iommu_enable(iommu);
7d0c5cc5 2025 iommu_flush_all_caches(iommu);
8736197b 2026 }
d98de49a
SS		 2027
2028#ifdef CONFIG_IRQ_REMAP
2029 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2030 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2031#endif
8736197b
JR		 2032}
2033
11ee5ac4
JR		 2034static void enable_iommus_v2(void)
2035{
2036 struct amd_iommu *iommu;
2037
2038 for_each_iommu(iommu) {
2039 iommu_enable_ppr_log(iommu);
2040 iommu_enable_gt(iommu);
2041 }
2042}
2043
2044static void enable_iommus(void)
2045{
2046 early_enable_iommus();
2047
2048 enable_iommus_v2();
2049}
2050
92ac4320
JR		 2051static void disable_iommus(void)
2052{
2053 struct amd_iommu *iommu;
2054
2055 for_each_iommu(iommu)
2056 iommu_disable(iommu);
d98de49a
SS		 2057
2058#ifdef CONFIG_IRQ_REMAP
2059 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2060 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2061#endif
92ac4320
JR		 2062}
2063
7441e9cb
JR		 2064/*
2065 * Suspend/Resume support
2066 * disable suspend until real resume implemented
2067 */
2068
f3c6ea1b 2069static void amd_iommu_resume(void)
7441e9cb 2070{
5bcd757f
MG		 2071 struct amd_iommu *iommu;
2072
2073 for_each_iommu(iommu)
2074 iommu_apply_resume_quirks(iommu);
2075
736501ee
JR		 2076 /* re-load the hardware */
2077 enable_iommus();
3d9761e7
JR		 2078
2079 amd_iommu_enable_interrupts();
7441e9cb
JR		 2080}
2081
f3c6ea1b 2082static int amd_iommu_suspend(void)
7441e9cb 2083{
736501ee
JR		 2084 /* disable IOMMUs to go out of the way for BIOS */
2085 disable_iommus();
2086
2087 return 0;
7441e9cb
JR		 2088}
2089
f3c6ea1b 2090static struct syscore_ops amd_iommu_syscore_ops = {
7441e9cb
JR		 2091 .suspend = amd_iommu_suspend,
2092 .resume = amd_iommu_resume,
2093};
2094
8704a1ba
JR		 2095static void __init free_on_init_error(void)
2096{
ebcfa284 2097 kmemleak_free(irq_lookup_table);
0ea2c422
JR		 2098 free_pages((unsigned long)irq_lookup_table,
2099 get_order(rlookup_table_size));
8704a1ba 2100
a591989a
JL		 2101 kmem_cache_destroy(amd_iommu_irq_cache);
2102 amd_iommu_irq_cache = NULL;
8704a1ba
JR		 2103
2104 free_pages((unsigned long)amd_iommu_rlookup_table,
2105 get_order(rlookup_table_size));
2106
2107 free_pages((unsigned long)amd_iommu_alias_table,
2108 get_order(alias_table_size));
2109
2110 free_pages((unsigned long)amd_iommu_dev_table,
2111 get_order(dev_table_size));
2112
2113 free_iommu_all();
2114
8704a1ba
JR		 2115#ifdef CONFIG_GART_IOMMU
2116 /*
2117 * We failed to initialize the AMD IOMMU - try fallback to GART
2118 * if possible.
2119 */
2120 gart_iommu_init();
2121
2122#endif
2123}
2124
c2ff5cf5
JR		 2125/* SB IOAPIC is always on this device in AMD systems */
2126#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2127
eb1eb7ae
JR		 2128static bool __init check_ioapic_information(void)
2129{
dfbb6d47 2130 const char *fw_bug = FW_BUG;
c2ff5cf5 2131 bool ret, has_sb_ioapic;
eb1eb7ae
JR		 2132 int idx;
2133
c2ff5cf5
JR		 2134 has_sb_ioapic = false;
2135 ret = false;
eb1eb7ae 2136
dfbb6d47
JR		 2137 /*
2138 * If we have map overrides on the kernel command line the
2139 * messages in this function might not describe firmware bugs
2140 * anymore - so be careful
2141 */
2142 if (cmdline_maps)
2143 fw_bug = "";
2144
c2ff5cf5
JR		 2145 for (idx = 0; idx < nr_ioapics; idx++) {
2146 int devid, id = mpc_ioapic_id(idx);
2147
2148 devid = get_ioapic_devid(id);
2149 if (devid < 0) {
dfbb6d47
JR		 2150 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2151 fw_bug, id);
c2ff5cf5
JR		 2152 ret = false;
2153 } else if (devid == IOAPIC_SB_DEVID) {
2154 has_sb_ioapic = true;
2155 ret = true;
eb1eb7ae
JR		 2156 }
2157 }
2158
c2ff5cf5
JR		 2159 if (!has_sb_ioapic) {
2160 /*
2161 * We expect the SB IOAPIC to be listed in the IVRS
2162 * table. The system timer is connected to the SB IOAPIC
2163 * and if we don't have it in the list the system will
2164 * panic at boot time. This situation usually happens
2165 * when the BIOS is buggy and provides us the wrong
2166 * device id for the IOAPIC in the system.
2167 */
dfbb6d47 2168 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
c2ff5cf5
JR		 2169 }
2170
2171 if (!ret)
dfbb6d47 2172 pr_err("AMD-Vi: Disabling interrupt remapping\n");
c2ff5cf5
JR		 2173
2174 return ret;
eb1eb7ae
JR		 2175}
2176
d04e0ba3
JR		 2177static void __init free_dma_resources(void)
2178{
d04e0ba3
JR		 2179 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2180 get_order(MAX_DOMAIN_ID/8));
2181
2182 free_unity_maps();
2183}
2184
b65233a9 2185/*
8704a1ba
JR		 2186 * This is the hardware init function for AMD IOMMU in the system.
2187 * This function is called either from amd_iommu_init or from the interrupt
2188 * remapping setup code.
b65233a9
JR		 2189 *
2190 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
8c7142f5 2191 * four times:
b65233a9 2192 *
8c7142f5
SS		 2193 * 1 pass) Discover the most comprehensive IVHD type to use.
2194 *
2195 * 2 pass) Find the highest PCI device id the driver has to handle.
b65233a9
JR		 2196 * Upon this information the size of the data structures is
2197 * determined that needs to be allocated.
2198 *
8c7142f5 2199 * 3 pass) Initialize the data structures just allocated with the
b65233a9
JR		 2200 * information in the ACPI table about available AMD IOMMUs
2201 * in the system. It also maps the PCI devices in the
2202 * system to specific IOMMUs
2203 *
8c7142f5 2204 * 4 pass) After the basic data structures are allocated and
b65233a9
JR		 2205 * initialized we update them with information about memory
2206 * remapping requirements parsed out of the ACPI table in
2207 * this last pass.
2208 *
8704a1ba
JR		 2209 * After everything is set up the IOMMUs are enabled and the necessary
2210 * hotplug and suspend notifiers are registered.
b65233a9 2211 */
643511b3 2212static int __init early_amd_iommu_init(void)
fe74c9cf 2213{
02f3b3f5 2214 struct acpi_table_header *ivrs_base;
02f3b3f5 2215 acpi_status status;
3928aa3f 2216 int i, remap_cache_sz, ret = 0;
fe74c9cf 2217
643511b3 2218 if (!amd_iommu_detected)
8704a1ba
JR		 2219 return -ENODEV;
2220
6b11d1d6 2221 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2222 if (status == AE_NOT_FOUND)
2223 return -ENODEV;
2224 else if (ACPI_FAILURE(status)) {
2225 const char *err = acpi_format_exception(status);
2226 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2227 return -EINVAL;
2228 }
2229
8c7142f5
SS		 2230 /*
2231 * Validate checksum here so we don't need to do it when
2232 * we actually parse the table
2233 */
2234 ret = check_ivrs_checksum(ivrs_base);
2235 if (ret)
99e8ccd3 2236 goto out;
8c7142f5
SS		 2237
2238 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2239 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2240
fe74c9cf
JR		 2241 /*
2242 * First parse ACPI tables to find the largest Bus/Dev/Func
2243 * we need to handle. Upon this information the shared data
2244 * structures for the IOMMUs in the system will be allocated
2245 */
2c0ae172
JR		 2246 ret = find_last_devid_acpi(ivrs_base);
2247 if (ret)
3551a708
JR		 2248 goto out;
2249
c571484e
JR		 2250 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2251 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2252 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
fe74c9cf 2253
fe74c9cf 2254 /* Device table - directly used by all IOMMUs */
8704a1ba 2255 ret = -ENOMEM;
5dc8bff0 2256 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2257 get_order(dev_table_size));
2258 if (amd_iommu_dev_table == NULL)
2259 goto out;
2260
2261 /*
2262 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2263 * IOMMU see for that device
2264 */
2265 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2266 get_order(alias_table_size));
2267 if (amd_iommu_alias_table == NULL)
2c0ae172 2268 goto out;
fe74c9cf
JR		 2269
2270 /* IOMMU rlookup table - find the IOMMU for a specific device */
83fd5cc6
JR		 2271 amd_iommu_rlookup_table = (void *)__get_free_pages(
2272 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2273 get_order(rlookup_table_size));
2274 if (amd_iommu_rlookup_table == NULL)
2c0ae172 2275 goto out;
fe74c9cf 2276
5dc8bff0
JR		 2277 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2278 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2279 get_order(MAX_DOMAIN_ID/8));
2280 if (amd_iommu_pd_alloc_bitmap == NULL)
2c0ae172 2281 goto out;
fe74c9cf
JR		 2282
2283 /*
5dc8bff0 2284 * let all alias entries point to itself
fe74c9cf 2285 */
3a61ec38 2286 for (i = 0; i <= amd_iommu_last_bdf; ++i)
fe74c9cf
JR		 2287 amd_iommu_alias_table[i] = i;
2288
fe74c9cf
JR		 2289 /*
2290 * never allocate domain 0 because its used as the non-allocated and
2291 * error value placeholder
2292 */
5c87f62d 2293 __set_bit(0, amd_iommu_pd_alloc_bitmap);
fe74c9cf 2294
aeb26f55
JR		 2295 spin_lock_init(&amd_iommu_pd_lock);
2296
fe74c9cf
JR		 2297 /*
2298 * now the data structures are allocated and basically initialized
2299 * start the real acpi table scan
2300 */
02f3b3f5
JR		 2301 ret = init_iommu_all(ivrs_base);
2302 if (ret)
2c0ae172 2303 goto out;
fe74c9cf 2304
eb1eb7ae
JR		 2305 if (amd_iommu_irq_remap)
2306 amd_iommu_irq_remap = check_ioapic_information();
2307
05152a04
JR		 2308 if (amd_iommu_irq_remap) {
2309 /*
2310 * Interrupt remapping enabled, create kmem_cache for the
2311 * remapping tables.
2312 */
83ed9c13 2313 ret = -ENOMEM;
3928aa3f
SS		 2314 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2315 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2316 else
2317 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
05152a04 2318 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
3928aa3f
SS		 2319 remap_cache_sz,
2320 IRQ_TABLE_ALIGNMENT,
2321 0, NULL);
05152a04
JR		 2322 if (!amd_iommu_irq_cache)
2323 goto out;
0ea2c422
JR		 2324
2325 irq_lookup_table = (void *)__get_free_pages(
2326 GFP_KERNEL | __GFP_ZERO,
2327 get_order(rlookup_table_size));
ebcfa284
LS		 2328 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2329 1, GFP_KERNEL);
0ea2c422
JR		 2330 if (!irq_lookup_table)
2331 goto out;
05152a04
JR		 2332 }
2333
02f3b3f5
JR		 2334 ret = init_memory_definitions(ivrs_base);
2335 if (ret)
2c0ae172 2336 goto out;
3551a708 2337
eb1eb7ae
JR		 2338 /* init the device table */
2339 init_device_table();
2340
8704a1ba 2341out:
02f3b3f5 2342 /* Don't leak any ACPI memory */
6b11d1d6 2343 acpi_put_table(ivrs_base);
02f3b3f5
JR		 2344 ivrs_base = NULL;
2345
643511b3
JR		 2346 return ret;
2347}
2348
ae295142 2349static int amd_iommu_enable_interrupts(void)
3d9761e7
JR		 2350{
2351 struct amd_iommu *iommu;
2352 int ret = 0;
2353
2354 for_each_iommu(iommu) {
2355 ret = iommu_init_msi(iommu);
2356 if (ret)
2357 goto out;
2358 }
2359
2360out:
2361 return ret;
2362}
2363
02f3b3f5
JR		 2364static bool detect_ivrs(void)
2365{
2366 struct acpi_table_header *ivrs_base;
02f3b3f5
JR		 2367 acpi_status status;
2368
6b11d1d6 2369 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2370 if (status == AE_NOT_FOUND)
2371 return false;
2372 else if (ACPI_FAILURE(status)) {
2373 const char *err = acpi_format_exception(status);
2374 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2375 return false;
2376 }
2377
6b11d1d6 2378 acpi_put_table(ivrs_base);
02f3b3f5 2379
1adb7d31
JR		 2380 /* Make sure ACS will be enabled during PCI probe */
2381 pci_request_acs();
2382
02f3b3f5
JR		 2383 return true;
2384}
2385
2c0ae172 2386/****************************************************************************
8704a1ba 2387 *
2c0ae172
JR		 2388 * AMD IOMMU Initialization State Machine
2389 *
2390 ****************************************************************************/
2391
2392static int __init state_next(void)
8704a1ba
JR		 2393{
2394 int ret = 0;
2395
2c0ae172
JR		 2396 switch (init_state) {
2397 case IOMMU_START_STATE:
2398 if (!detect_ivrs()) {
2399 init_state = IOMMU_NOT_FOUND;
2400 ret = -ENODEV;
2401 } else {
2402 init_state = IOMMU_IVRS_DETECTED;
2403 }
2404 break;
2405 case IOMMU_IVRS_DETECTED:
2406 ret = early_amd_iommu_init();
2407 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2408 break;
2409 case IOMMU_ACPI_FINISHED:
2410 early_enable_iommus();
2411 register_syscore_ops(&amd_iommu_syscore_ops);
2412 x86_platform.iommu_shutdown = disable_iommus;
2413 init_state = IOMMU_ENABLED;
2414 break;
2415 case IOMMU_ENABLED:
2416 ret = amd_iommu_init_pci();
2417 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2418 enable_iommus_v2();
2419 break;
2420 case IOMMU_PCI_INIT:
2421 ret = amd_iommu_enable_interrupts();
2422 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2423 break;
2424 case IOMMU_INTERRUPTS_EN:
1e6a7b04 2425 ret = amd_iommu_init_dma_ops();
2c0ae172
JR		 2426 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2427 break;
2428 case IOMMU_DMA_OPS:
2429 init_state = IOMMU_INITIALIZED;
2430 break;
2431 case IOMMU_INITIALIZED:
2432 /* Nothing to do */
2433 break;
2434 case IOMMU_NOT_FOUND:
2435 case IOMMU_INIT_ERROR:
2436 /* Error states => do nothing */
2437 ret = -EINVAL;
2438 break;
2439 default:
2440 /* Unknown state */
2441 BUG();
2442 }
3d9761e7 2443
2c0ae172
JR		 2444 return ret;
2445}
7441e9cb 2446
2c0ae172
JR		 2447static int __init iommu_go_to_state(enum iommu_init_state state)
2448{
2449 int ret = 0;
f5325094 2450
2c0ae172
JR		 2451 while (init_state != state) {
2452 ret = state_next();
2453 if (init_state == IOMMU_NOT_FOUND ||
2454 init_state == IOMMU_INIT_ERROR)
2455 break;
2456 }
f2f12b6f 2457
fe74c9cf 2458 return ret;
2c0ae172 2459}
fe74c9cf 2460
6b474b82
JR		 2461#ifdef CONFIG_IRQ_REMAP
2462int __init amd_iommu_prepare(void)
2463{
3f4cb7c0
TG		 2464 int ret;
2465
7fa1c842 2466 amd_iommu_irq_remap = true;
84d07793 2467
3f4cb7c0
TG		 2468 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2469 if (ret)
2470 return ret;
2471 return amd_iommu_irq_remap ? 0 : -ENODEV;
6b474b82 2472}
d7f07769 2473
6b474b82
JR		 2474int __init amd_iommu_enable(void)
2475{
2476 int ret;
2477
2478 ret = iommu_go_to_state(IOMMU_ENABLED);
2479 if (ret)
2480 return ret;
d7f07769 2481
6b474b82 2482 irq_remapping_enabled = 1;
d7f07769 2483
6b474b82
JR		 2484 return 0;
2485}
2486
2487void amd_iommu_disable(void)
2488{
2489 amd_iommu_suspend();
2490}
2491
2492int amd_iommu_reenable(int mode)
2493{
2494 amd_iommu_resume();
2495
2496 return 0;
2497}
d7f07769 2498
6b474b82
JR		 2499int __init amd_iommu_enable_faulting(void)
2500{
2501 /* We enable MSI later when PCI is initialized */
2502 return 0;
2503}
2504#endif
d7f07769 2505
2c0ae172
JR		 2506/*
2507 * This is the core init function for AMD IOMMU hardware in the system.
2508 * This function is called from the generic x86 DMA layer initialization
2509 * code.
2510 */
2511static int __init amd_iommu_init(void)
2512{
2513 int ret;
2514
2515 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2516 if (ret) {
d04e0ba3
JR		 2517 free_dma_resources();
2518 if (!irq_remapping_enabled) {
2519 disable_iommus();
2520 free_on_init_error();
2521 } else {
2522 struct amd_iommu *iommu;
2523
2524 uninit_device_table_dma();
2525 for_each_iommu(iommu)
2526 iommu_flush_all_caches(iommu);
2527 }
2c0ae172
JR		 2528 }
2529
2530 return ret;
fe74c9cf
JR		 2531}
2532
b65233a9
JR		 2533/****************************************************************************
2534 *
2535 * Early detect code. This code runs at IOMMU detection time in the DMA
2536 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2537 * IOMMUs
2538 *
2539 ****************************************************************************/
480125ba 2540int __init amd_iommu_detect(void)
ae7877de 2541{
2c0ae172 2542 int ret;
02f3b3f5 2543
75f1cdf1 2544 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
480125ba 2545 return -ENODEV;
ae7877de 2546
a5235725 2547 if (amd_iommu_disabled)
480125ba 2548 return -ENODEV;
a5235725 2549
2c0ae172
JR		 2550 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2551 if (ret)
2552 return ret;
11bd04f6 2553
02f3b3f5
JR		 2554 amd_iommu_detected = true;
2555 iommu_detected = 1;
2556 x86_init.iommu.iommu_init = amd_iommu_init;
2557
4781bc42 2558 return 1;
ae7877de
JR		 2559}
2560
b65233a9
JR		 2561/****************************************************************************
2562 *
2563 * Parsing functions for the AMD IOMMU specific kernel command line
2564 * options.
2565 *
2566 ****************************************************************************/
2567
fefda117
JR		 2568static int __init parse_amd_iommu_dump(char *str)
2569{
2570 amd_iommu_dump = true;
2571
2572 return 1;
2573}
2574
3928aa3f
SS		 2575static int __init parse_amd_iommu_intr(char *str)
2576{
2577 for (; *str; ++str) {
2578 if (strncmp(str, "legacy", 6) == 0) {
2579 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2580 break;
2581 }
2582 if (strncmp(str, "vapic", 5) == 0) {
2583 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2584 break;
2585 }
2586 }
2587 return 1;
2588}
2589
918ad6c5
JR		 2590static int __init parse_amd_iommu_options(char *str)
2591{
2592 for (; *str; ++str) {
695b5676 2593 if (strncmp(str, "fullflush", 9) == 0)
afa9fdc2 2594 amd_iommu_unmap_flush = true;
a5235725
JR		 2595 if (strncmp(str, "off", 3) == 0)
2596 amd_iommu_disabled = true;
5abcdba4
JR		 2597 if (strncmp(str, "force_isolation", 15) == 0)
2598 amd_iommu_force_isolation = true;
918ad6c5
JR		 2599 }
2600
2601 return 1;
2602}
2603
440e8998
JR		 2604static int __init parse_ivrs_ioapic(char *str)
2605{
2606 unsigned int bus, dev, fn;
2607 int ret, id, i;
2608 u16 devid;
2609
2610 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2611
2612 if (ret != 4) {
2613 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2614 return 1;
2615 }
2616
2617 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2618 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2619 str);
2620 return 1;
2621 }
2622
2623 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2624
dfbb6d47 2625 cmdline_maps = true;
440e8998
JR		 2626 i = early_ioapic_map_size++;
2627 early_ioapic_map[i].id = id;
2628 early_ioapic_map[i].devid = devid;
2629 early_ioapic_map[i].cmd_line = true;
2630
2631 return 1;
2632}
2633
2634static int __init parse_ivrs_hpet(char *str)
2635{
2636 unsigned int bus, dev, fn;
2637 int ret, id, i;
2638 u16 devid;
2639
2640 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2641
2642 if (ret != 4) {
2643 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2644 return 1;
2645 }
2646
2647 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2648 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2649 str);
2650 return 1;
2651 }
2652
2653 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2654
dfbb6d47 2655 cmdline_maps = true;
440e8998
JR		 2656 i = early_hpet_map_size++;
2657 early_hpet_map[i].id = id;
2658 early_hpet_map[i].devid = devid;
2659 early_hpet_map[i].cmd_line = true;
2660
2661 return 1;
2662}
2663
ca3bf5d4
SS		 2664static int __init parse_ivrs_acpihid(char *str)
2665{
2666 u32 bus, dev, fn;
2667 char *hid, *uid, *p;
2668 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2669 int ret, i;
2670
2671 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2672 if (ret != 4) {
2673 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2674 return 1;
2675 }
2676
2677 p = acpiid;
2678 hid = strsep(&p, ":");
2679 uid = p;
2680
2681 if (!hid || !(*hid) || !uid) {
2682 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2683 return 1;
2684 }
2685
2686 i = early_acpihid_map_size++;
2687 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2688 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2689 early_acpihid_map[i].devid =
2690 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2691 early_acpihid_map[i].cmd_line = true;
2692
2693 return 1;
2694}
2695
440e8998
JR		 2696__setup("amd_iommu_dump", parse_amd_iommu_dump);
2697__setup("amd_iommu=", parse_amd_iommu_options);
3928aa3f 2698__setup("amd_iommu_intr=", parse_amd_iommu_intr);
440e8998
JR		 2699__setup("ivrs_ioapic", parse_ivrs_ioapic);
2700__setup("ivrs_hpet", parse_ivrs_hpet);
ca3bf5d4 2701__setup("ivrs_acpihid", parse_ivrs_acpihid);
22e6daf4
KRW		 2702
2703IOMMU_INIT_FINISH(amd_iommu_detect,
2704 gart_iommu_hole_init,
98f1ad25
JR		 2705 NULL,
2706 NULL);
400a28a0
JR		 2707
2708bool amd_iommu_v2_supported(void)
2709{
2710 return amd_iommu_v2_present;
2711}
2712EXPORT_SYMBOL(amd_iommu_v2_supported);
30861ddc
SK		 2713
2714/****************************************************************************
2715 *
2716 * IOMMU EFR Performance Counter support functionality. This code allows
2717 * access to the IOMMU PC functionality.
2718 *
2719 ****************************************************************************/
2720
2721u8 amd_iommu_pc_get_max_banks(u16 devid)
2722{
2723 struct amd_iommu *iommu;
2724 u8 ret = 0;
2725
2726 /* locate the iommu governing the devid */
2727 iommu = amd_iommu_rlookup_table[devid];
2728 if (iommu)
2729 ret = iommu->max_banks;
2730
2731 return ret;
2732}
2733EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2734
2735bool amd_iommu_pc_supported(void)
2736{
2737 return amd_iommu_pc_present;
2738}
2739EXPORT_SYMBOL(amd_iommu_pc_supported);
2740
2741u8 amd_iommu_pc_get_max_counters(u16 devid)
2742{
2743 struct amd_iommu *iommu;
2744 u8 ret = 0;
2745
2746 /* locate the iommu governing the devid */
2747 iommu = amd_iommu_rlookup_table[devid];
2748 if (iommu)
2749 ret = iommu->max_counters;
2750
2751 return ret;
2752}
2753EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2754
38e45d02
SS		 2755static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2756 u8 bank, u8 cntr, u8 fxn,
30861ddc
SK		 2757 u64 *value, bool is_write)
2758{
30861ddc
SK		 2759 u32 offset;
2760 u32 max_offset_lim;
2761
30861ddc 2762 /* Check for valid iommu and pc register indexing */
38e45d02 2763 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
30861ddc
SK		 2764 return -ENODEV;
2765
2766 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2767
2768 /* Limit the offset to the hw defined mmio region aperture */
2769 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2770 (iommu->max_counters << 8) | 0x28);
2771 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2772 (offset > max_offset_lim))
2773 return -EINVAL;
2774
2775 if (is_write) {
2776 writel((u32)*value, iommu->mmio_base + offset);
2777 writel((*value >> 32), iommu->mmio_base + offset + 4);
2778 } else {
2779 *value = readl(iommu->mmio_base + offset + 4);
2780 *value <<= 32;
2781 *value = readl(iommu->mmio_base + offset);
2782 }
2783
2784 return 0;
2785}
2786EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
38e45d02
SS		 2787
2788int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2789 u64 *value, bool is_write)
2790{
2791 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2792
2793 /* Make sure the IOMMU PC resource is available */
2794 if (!amd_iommu_pc_present || iommu == NULL)
2795 return -ENODEV;
2796
2797 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
2798 value, is_write);
2799}
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