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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
f6e2e6b6 | 28 | #include <asm/pci-direct.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
ea1b0d39 | 31 | #include <asm/x86_init.h> |
22e6daf4 | 32 | #include <asm/iommu_table.h> |
403f81d8 JR |
33 | |
34 | #include "amd_iommu_proto.h" | |
35 | #include "amd_iommu_types.h" | |
36 | ||
f6e2e6b6 JR |
37 | /* |
38 | * definitions for the ACPI scanning code | |
39 | */ | |
f6e2e6b6 | 40 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
41 | |
42 | #define ACPI_IVHD_TYPE 0x10 | |
43 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
44 | #define ACPI_IVMD_TYPE 0x21 | |
45 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
46 | ||
47 | #define IVHD_DEV_ALL 0x01 | |
48 | #define IVHD_DEV_SELECT 0x02 | |
49 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
50 | #define IVHD_DEV_RANGE_END 0x04 | |
51 | #define IVHD_DEV_ALIAS 0x42 | |
52 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
53 | #define IVHD_DEV_EXT_SELECT 0x46 | |
54 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
55 | ||
6da7342f JR |
56 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
57 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
58 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
59 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
60 | |
61 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
62 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
63 | ||
64 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
65 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
66 | #define ACPI_DEVFLAG_NMI 0x04 | |
67 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
68 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
69 | #define ACPI_DEVFLAG_LINT0 0x40 | |
70 | #define ACPI_DEVFLAG_LINT1 0x80 | |
71 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
72 | ||
b65233a9 JR |
73 | /* |
74 | * ACPI table definitions | |
75 | * | |
76 | * These data structures are laid over the table to parse the important values | |
77 | * out of it. | |
78 | */ | |
79 | ||
80 | /* | |
81 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
82 | * or more ivhd_entrys. | |
83 | */ | |
f6e2e6b6 JR |
84 | struct ivhd_header { |
85 | u8 type; | |
86 | u8 flags; | |
87 | u16 length; | |
88 | u16 devid; | |
89 | u16 cap_ptr; | |
90 | u64 mmio_phys; | |
91 | u16 pci_seg; | |
92 | u16 info; | |
93 | u32 reserved; | |
94 | } __attribute__((packed)); | |
95 | ||
b65233a9 JR |
96 | /* |
97 | * A device entry describing which devices a specific IOMMU translates and | |
98 | * which requestor ids they use. | |
99 | */ | |
f6e2e6b6 JR |
100 | struct ivhd_entry { |
101 | u8 type; | |
102 | u16 devid; | |
103 | u8 flags; | |
104 | u32 ext; | |
105 | } __attribute__((packed)); | |
106 | ||
b65233a9 JR |
107 | /* |
108 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
109 | * ranges for devices and regions that should be unity mapped. | |
110 | */ | |
f6e2e6b6 JR |
111 | struct ivmd_header { |
112 | u8 type; | |
113 | u8 flags; | |
114 | u16 length; | |
115 | u16 devid; | |
116 | u16 aux; | |
117 | u64 resv; | |
118 | u64 range_start; | |
119 | u64 range_length; | |
120 | } __attribute__((packed)); | |
121 | ||
fefda117 JR |
122 | bool amd_iommu_dump; |
123 | ||
c1cbebee | 124 | static int __initdata amd_iommu_detected; |
a5235725 | 125 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 126 | |
b65233a9 JR |
127 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
128 | to handle */ | |
2e22847f | 129 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 130 | we find in ACPI */ |
afa9fdc2 | 131 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 132 | |
2e22847f | 133 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 134 | system */ |
928abd25 | 135 | |
bb52777e JR |
136 | /* Array to assign indices to IOMMUs*/ |
137 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
138 | int amd_iommus_present; | |
139 | ||
318afd41 JR |
140 | /* IOMMUs have a non-present cache? */ |
141 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 142 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 143 | |
62f71abb JR |
144 | u32 amd_iommu_max_pasids __read_mostly = ~0; |
145 | ||
0f764806 | 146 | /* |
3551a708 | 147 | * The ACPI table parsing functions set this variable on an error |
0f764806 | 148 | */ |
3551a708 | 149 | static int __initdata amd_iommu_init_err; |
0f764806 | 150 | |
aeb26f55 JR |
151 | /* |
152 | * List of protection domains - used during resume | |
153 | */ | |
154 | LIST_HEAD(amd_iommu_pd_list); | |
155 | spinlock_t amd_iommu_pd_lock; | |
156 | ||
b65233a9 JR |
157 | /* |
158 | * Pointer to the device table which is shared by all AMD IOMMUs | |
159 | * it is indexed by the PCI device id or the HT unit id and contains | |
160 | * information about the domain the device belongs to as well as the | |
161 | * page table root pointer. | |
162 | */ | |
928abd25 | 163 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
164 | |
165 | /* | |
166 | * The alias table is a driver specific data structure which contains the | |
167 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
168 | * More than one device can share the same requestor id. | |
169 | */ | |
928abd25 | 170 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
171 | |
172 | /* | |
173 | * The rlookup table is used to find the IOMMU which is responsible | |
174 | * for a specific device. It is also indexed by the PCI device id. | |
175 | */ | |
928abd25 | 176 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 177 | |
b65233a9 JR |
178 | /* |
179 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
180 | * to know which ones are already in use. | |
181 | */ | |
928abd25 JR |
182 | unsigned long *amd_iommu_pd_alloc_bitmap; |
183 | ||
b65233a9 JR |
184 | static u32 dev_table_size; /* size of the device table */ |
185 | static u32 alias_table_size; /* size of the alias table */ | |
186 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 187 | |
7d0c5cc5 JR |
188 | /* |
189 | * This function flushes all internal caches of | |
190 | * the IOMMU used by this driver. | |
191 | */ | |
192 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
193 | ||
208ec8c9 JR |
194 | static inline void update_last_devid(u16 devid) |
195 | { | |
196 | if (devid > amd_iommu_last_bdf) | |
197 | amd_iommu_last_bdf = devid; | |
198 | } | |
199 | ||
c571484e JR |
200 | static inline unsigned long tbl_size(int entry_size) |
201 | { | |
202 | unsigned shift = PAGE_SHIFT + | |
421f909c | 203 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
204 | |
205 | return 1UL << shift; | |
206 | } | |
207 | ||
5bcd757f MG |
208 | /* Access to l1 and l2 indexed register spaces */ |
209 | ||
210 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
211 | { | |
212 | u32 val; | |
213 | ||
214 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
215 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
216 | return val; | |
217 | } | |
218 | ||
219 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
220 | { | |
221 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
222 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
223 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
224 | } | |
225 | ||
226 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
227 | { | |
228 | u32 val; | |
229 | ||
230 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
231 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
232 | return val; | |
233 | } | |
234 | ||
235 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
236 | { | |
237 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
238 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
239 | } | |
240 | ||
b65233a9 JR |
241 | /**************************************************************************** |
242 | * | |
243 | * AMD IOMMU MMIO register space handling functions | |
244 | * | |
245 | * These functions are used to program the IOMMU device registers in | |
246 | * MMIO space required for that driver. | |
247 | * | |
248 | ****************************************************************************/ | |
3e8064ba | 249 | |
b65233a9 JR |
250 | /* |
251 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
252 | * exclusion range are passed through untranslated | |
253 | */ | |
05f92db9 | 254 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
255 | { |
256 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
257 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
258 | u64 entry; | |
259 | ||
260 | if (!iommu->exclusion_start) | |
261 | return; | |
262 | ||
263 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
264 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
265 | &entry, sizeof(entry)); | |
266 | ||
267 | entry = limit; | |
268 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
269 | &entry, sizeof(entry)); | |
270 | } | |
271 | ||
b65233a9 | 272 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
273 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
274 | { | |
f609891f | 275 | u64 entry; |
b2026aa2 JR |
276 | |
277 | BUG_ON(iommu->mmio_base == NULL); | |
278 | ||
279 | entry = virt_to_phys(amd_iommu_dev_table); | |
280 | entry |= (dev_table_size >> 12) - 1; | |
281 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
282 | &entry, sizeof(entry)); | |
283 | } | |
284 | ||
b65233a9 | 285 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 286 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
287 | { |
288 | u32 ctrl; | |
289 | ||
290 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
291 | ctrl |= (1 << bit); | |
292 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
293 | } | |
294 | ||
ca020711 | 295 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
296 | { |
297 | u32 ctrl; | |
298 | ||
199d0d50 | 299 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
300 | ctrl &= ~(1 << bit); |
301 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
302 | } | |
303 | ||
b65233a9 | 304 | /* Function to enable the hardware */ |
05f92db9 | 305 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 306 | { |
d99ddec3 JR |
307 | static const char * const feat_str[] = { |
308 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
309 | "IA", "GA", "HE", "PC", NULL | |
310 | }; | |
311 | int i; | |
312 | ||
313 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx", | |
a4e267c8 | 314 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 | 315 | |
d99ddec3 JR |
316 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { |
317 | printk(KERN_CONT " extended features: "); | |
318 | for (i = 0; feat_str[i]; ++i) | |
319 | if (iommu_feature(iommu, (1ULL << i))) | |
320 | printk(KERN_CONT " %s", feat_str[i]); | |
321 | } | |
322 | printk(KERN_CONT "\n"); | |
323 | ||
b2026aa2 | 324 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
325 | } |
326 | ||
92ac4320 | 327 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 328 | { |
a8c485bb CW |
329 | /* Disable command buffer */ |
330 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
331 | ||
332 | /* Disable event logging and event interrupts */ | |
333 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
334 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
335 | ||
336 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 337 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
338 | } |
339 | ||
b65233a9 JR |
340 | /* |
341 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
342 | * the system has one. | |
343 | */ | |
6c56747b JR |
344 | static u8 * __init iommu_map_mmio_space(u64 address) |
345 | { | |
346 | u8 *ret; | |
347 | ||
e82752d8 JR |
348 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
349 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
350 | address); | |
351 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 352 | return NULL; |
e82752d8 | 353 | } |
6c56747b JR |
354 | |
355 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
356 | if (ret != NULL) | |
357 | return ret; | |
358 | ||
359 | release_mem_region(address, MMIO_REGION_LENGTH); | |
360 | ||
361 | return NULL; | |
362 | } | |
363 | ||
364 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
365 | { | |
366 | if (iommu->mmio_base) | |
367 | iounmap(iommu->mmio_base); | |
368 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
369 | } | |
370 | ||
b65233a9 JR |
371 | /**************************************************************************** |
372 | * | |
373 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
374 | * parsing. In this pass we try to find out the highest device id this | |
375 | * code has to handle. Upon this information the size of the shared data | |
376 | * structures is determined later. | |
377 | * | |
378 | ****************************************************************************/ | |
379 | ||
b514e555 JR |
380 | /* |
381 | * This function calculates the length of a given IVHD entry | |
382 | */ | |
383 | static inline int ivhd_entry_length(u8 *ivhd) | |
384 | { | |
385 | return 0x04 << (*ivhd >> 6); | |
386 | } | |
387 | ||
b65233a9 JR |
388 | /* |
389 | * This function reads the last device id the IOMMU has to handle from the PCI | |
390 | * capability header for this IOMMU | |
391 | */ | |
3e8064ba JR |
392 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
393 | { | |
394 | u32 cap; | |
395 | ||
396 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 397 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
398 | |
399 | return 0; | |
400 | } | |
401 | ||
b65233a9 JR |
402 | /* |
403 | * After reading the highest device id from the IOMMU PCI capability header | |
404 | * this function looks if there is a higher device id defined in the ACPI table | |
405 | */ | |
3e8064ba JR |
406 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
407 | { | |
408 | u8 *p = (void *)h, *end = (void *)h; | |
409 | struct ivhd_entry *dev; | |
410 | ||
411 | p += sizeof(*h); | |
412 | end += h->length; | |
413 | ||
414 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
415 | PCI_SLOT(h->devid), | |
416 | PCI_FUNC(h->devid), | |
417 | h->cap_ptr); | |
418 | ||
419 | while (p < end) { | |
420 | dev = (struct ivhd_entry *)p; | |
421 | switch (dev->type) { | |
422 | case IVHD_DEV_SELECT: | |
423 | case IVHD_DEV_RANGE_END: | |
424 | case IVHD_DEV_ALIAS: | |
425 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 426 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 427 | update_last_devid(dev->devid); |
3e8064ba JR |
428 | break; |
429 | default: | |
430 | break; | |
431 | } | |
b514e555 | 432 | p += ivhd_entry_length(p); |
3e8064ba JR |
433 | } |
434 | ||
435 | WARN_ON(p != end); | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
b65233a9 JR |
440 | /* |
441 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
442 | * id which we need to handle. This is the first of three functions which parse | |
443 | * the ACPI table. So we check the checksum here. | |
444 | */ | |
3e8064ba JR |
445 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
446 | { | |
447 | int i; | |
448 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
449 | struct ivhd_header *h; | |
450 | ||
451 | /* | |
452 | * Validate checksum here so we don't need to do it when | |
453 | * we actually parse the table | |
454 | */ | |
455 | for (i = 0; i < table->length; ++i) | |
456 | checksum += p[i]; | |
3551a708 | 457 | if (checksum != 0) { |
3e8064ba | 458 | /* ACPI table corrupt */ |
3551a708 JR |
459 | amd_iommu_init_err = -ENODEV; |
460 | return 0; | |
461 | } | |
3e8064ba JR |
462 | |
463 | p += IVRS_HEADER_LENGTH; | |
464 | ||
465 | end += table->length; | |
466 | while (p < end) { | |
467 | h = (struct ivhd_header *)p; | |
468 | switch (h->type) { | |
469 | case ACPI_IVHD_TYPE: | |
470 | find_last_devid_from_ivhd(h); | |
471 | break; | |
472 | default: | |
473 | break; | |
474 | } | |
475 | p += h->length; | |
476 | } | |
477 | WARN_ON(p != end); | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
b65233a9 JR |
482 | /**************************************************************************** |
483 | * | |
484 | * The following functions belong the the code path which parses the ACPI table | |
485 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
486 | * data structures, initialize the device/alias/rlookup table and also | |
487 | * basically initialize the hardware. | |
488 | * | |
489 | ****************************************************************************/ | |
490 | ||
491 | /* | |
492 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
493 | * write commands to that buffer later and the IOMMU will execute them | |
494 | * asynchronously | |
495 | */ | |
b36ca91e JR |
496 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
497 | { | |
d0312b21 | 498 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 499 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
500 | |
501 | if (cmd_buf == NULL) | |
502 | return NULL; | |
503 | ||
549c90dc | 504 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 505 | |
58492e12 JR |
506 | return cmd_buf; |
507 | } | |
508 | ||
93f1cc67 JR |
509 | /* |
510 | * This function resets the command buffer if the IOMMU stopped fetching | |
511 | * commands from it. | |
512 | */ | |
513 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
514 | { | |
515 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
516 | ||
517 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
518 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
519 | ||
520 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
521 | } | |
522 | ||
58492e12 JR |
523 | /* |
524 | * This function writes the command buffer address to the hardware and | |
525 | * enables it. | |
526 | */ | |
527 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
528 | { | |
529 | u64 entry; | |
530 | ||
531 | BUG_ON(iommu->cmd_buf == NULL); | |
532 | ||
533 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 534 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 535 | |
b36ca91e | 536 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 537 | &entry, sizeof(entry)); |
b36ca91e | 538 | |
93f1cc67 | 539 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 540 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
541 | } |
542 | ||
543 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
544 | { | |
23c1713f | 545 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 546 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
547 | } |
548 | ||
335503e5 JR |
549 | /* allocates the memory where the IOMMU will log its events to */ |
550 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
551 | { | |
335503e5 JR |
552 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
553 | get_order(EVT_BUFFER_SIZE)); | |
554 | ||
555 | if (iommu->evt_buf == NULL) | |
556 | return NULL; | |
557 | ||
1bc6f838 JR |
558 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
559 | ||
58492e12 JR |
560 | return iommu->evt_buf; |
561 | } | |
562 | ||
563 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
564 | { | |
565 | u64 entry; | |
566 | ||
567 | BUG_ON(iommu->evt_buf == NULL); | |
568 | ||
335503e5 | 569 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 570 | |
335503e5 JR |
571 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
572 | &entry, sizeof(entry)); | |
573 | ||
09067207 JR |
574 | /* set head and tail to zero manually */ |
575 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
576 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
577 | ||
58492e12 | 578 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
579 | } |
580 | ||
581 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
582 | { | |
583 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
584 | } | |
585 | ||
1a29ac01 JR |
586 | /* allocates the memory where the IOMMU will log its events to */ |
587 | static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) | |
588 | { | |
589 | iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
590 | get_order(PPR_LOG_SIZE)); | |
591 | ||
592 | if (iommu->ppr_log == NULL) | |
593 | return NULL; | |
594 | ||
595 | return iommu->ppr_log; | |
596 | } | |
597 | ||
598 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
599 | { | |
600 | u64 entry; | |
601 | ||
602 | if (iommu->ppr_log == NULL) | |
603 | return; | |
604 | ||
605 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
606 | ||
607 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
608 | &entry, sizeof(entry)); | |
609 | ||
610 | /* set head and tail to zero manually */ | |
611 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
612 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
613 | ||
614 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
615 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
616 | } | |
617 | ||
618 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
619 | { | |
620 | if (iommu->ppr_log == NULL) | |
621 | return; | |
622 | ||
623 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
624 | } | |
625 | ||
b65233a9 | 626 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
627 | static void set_dev_entry_bit(u16 devid, u8 bit) |
628 | { | |
ee6c2868 JR |
629 | int i = (bit >> 6) & 0x03; |
630 | int _bit = bit & 0x3f; | |
3566b778 | 631 | |
ee6c2868 | 632 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
633 | } |
634 | ||
c5cca146 JR |
635 | static int get_dev_entry_bit(u16 devid, u8 bit) |
636 | { | |
ee6c2868 JR |
637 | int i = (bit >> 6) & 0x03; |
638 | int _bit = bit & 0x3f; | |
c5cca146 | 639 | |
ee6c2868 | 640 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
641 | } |
642 | ||
643 | ||
644 | void amd_iommu_apply_erratum_63(u16 devid) | |
645 | { | |
646 | int sysmgt; | |
647 | ||
648 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
649 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
650 | ||
651 | if (sysmgt == 0x01) | |
652 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
653 | } | |
654 | ||
5ff4789d JR |
655 | /* Writes the specific IOMMU for a device into the rlookup table */ |
656 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
657 | { | |
658 | amd_iommu_rlookup_table[devid] = iommu; | |
659 | } | |
660 | ||
b65233a9 JR |
661 | /* |
662 | * This function takes the device specific flags read from the ACPI | |
663 | * table and sets up the device table entry with that information | |
664 | */ | |
5ff4789d JR |
665 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
666 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
667 | { |
668 | if (flags & ACPI_DEVFLAG_INITPASS) | |
669 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
670 | if (flags & ACPI_DEVFLAG_EXTINT) | |
671 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
672 | if (flags & ACPI_DEVFLAG_NMI) | |
673 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
674 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
675 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
676 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
677 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
678 | if (flags & ACPI_DEVFLAG_LINT0) | |
679 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
680 | if (flags & ACPI_DEVFLAG_LINT1) | |
681 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 682 | |
c5cca146 JR |
683 | amd_iommu_apply_erratum_63(devid); |
684 | ||
5ff4789d | 685 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
686 | } |
687 | ||
b65233a9 JR |
688 | /* |
689 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
690 | * it | |
691 | */ | |
3566b778 JR |
692 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
693 | { | |
694 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
695 | ||
696 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
697 | return; | |
698 | ||
699 | if (iommu) { | |
b65233a9 JR |
700 | /* |
701 | * We only can configure exclusion ranges per IOMMU, not | |
702 | * per device. But we can enable the exclusion range per | |
703 | * device. This is done here | |
704 | */ | |
3566b778 JR |
705 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
706 | iommu->exclusion_start = m->range_start; | |
707 | iommu->exclusion_length = m->range_length; | |
708 | } | |
709 | } | |
710 | ||
b65233a9 JR |
711 | /* |
712 | * This function reads some important data from the IOMMU PCI space and | |
713 | * initializes the driver data structure with it. It reads the hardware | |
714 | * capabilities and the first/last device entries | |
715 | */ | |
5d0c8e49 JR |
716 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
717 | { | |
5d0c8e49 | 718 | int cap_ptr = iommu->cap_ptr; |
d99ddec3 | 719 | u32 range, misc, low, high; |
5bcd757f | 720 | int i, j; |
5d0c8e49 | 721 | |
3eaf28a1 JR |
722 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
723 | &iommu->cap); | |
724 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
725 | &range); | |
a80dc3e0 JR |
726 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
727 | &misc); | |
5d0c8e49 | 728 | |
d591b0a3 JR |
729 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
730 | MMIO_GET_FD(range)); | |
731 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
732 | MMIO_GET_LD(range)); | |
a80dc3e0 | 733 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
4c894f47 | 734 | |
60f723b4 JR |
735 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) |
736 | amd_iommu_iotlb_sup = false; | |
737 | ||
d99ddec3 JR |
738 | /* read extended feature bits */ |
739 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
740 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
741 | ||
742 | iommu->features = ((u64)high << 32) | low; | |
743 | ||
62f71abb JR |
744 | if (iommu_feature(iommu, FEATURE_GT)) { |
745 | u32 pasids; | |
746 | u64 shift; | |
747 | ||
748 | shift = iommu->features & FEATURE_PASID_MASK; | |
749 | shift >>= FEATURE_PASID_SHIFT; | |
750 | pasids = (1 << shift); | |
751 | ||
752 | amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids); | |
753 | } | |
754 | ||
5bcd757f MG |
755 | if (!is_rd890_iommu(iommu->dev)) |
756 | return; | |
757 | ||
758 | /* | |
759 | * Some rd890 systems may not be fully reconfigured by the BIOS, so | |
760 | * it's necessary for us to store this information so it can be | |
761 | * reprogrammed on resume | |
762 | */ | |
763 | ||
764 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
765 | &iommu->stored_addr_lo); | |
766 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
767 | &iommu->stored_addr_hi); | |
768 | ||
769 | /* Low bit locks writes to configuration space */ | |
770 | iommu->stored_addr_lo &= ~1; | |
771 | ||
772 | for (i = 0; i < 6; i++) | |
773 | for (j = 0; j < 0x12; j++) | |
774 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
775 | ||
776 | for (i = 0; i < 0x83; i++) | |
777 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
5d0c8e49 JR |
778 | } |
779 | ||
b65233a9 JR |
780 | /* |
781 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
782 | * initializes the hardware and our data structures with it. | |
783 | */ | |
5d0c8e49 JR |
784 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
785 | struct ivhd_header *h) | |
786 | { | |
787 | u8 *p = (u8 *)h; | |
788 | u8 *end = p, flags = 0; | |
0de66d5b JR |
789 | u16 devid = 0, devid_start = 0, devid_to = 0; |
790 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 791 | bool alias = false; |
5d0c8e49 JR |
792 | struct ivhd_entry *e; |
793 | ||
794 | /* | |
e9bf5197 | 795 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 796 | */ |
e9bf5197 | 797 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
798 | |
799 | /* | |
800 | * Done. Now parse the device entries | |
801 | */ | |
802 | p += sizeof(struct ivhd_header); | |
803 | end += h->length; | |
804 | ||
42a698f4 | 805 | |
5d0c8e49 JR |
806 | while (p < end) { |
807 | e = (struct ivhd_entry *)p; | |
808 | switch (e->type) { | |
809 | case IVHD_DEV_ALL: | |
42a698f4 JR |
810 | |
811 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
812 | " last device %02x:%02x.%x flags: %02x\n", | |
813 | PCI_BUS(iommu->first_device), | |
814 | PCI_SLOT(iommu->first_device), | |
815 | PCI_FUNC(iommu->first_device), | |
816 | PCI_BUS(iommu->last_device), | |
817 | PCI_SLOT(iommu->last_device), | |
818 | PCI_FUNC(iommu->last_device), | |
819 | e->flags); | |
820 | ||
5d0c8e49 JR |
821 | for (dev_i = iommu->first_device; |
822 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
823 | set_dev_entry_from_acpi(iommu, dev_i, |
824 | e->flags, 0); | |
5d0c8e49 JR |
825 | break; |
826 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
827 | |
828 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
829 | "flags: %02x\n", | |
830 | PCI_BUS(e->devid), | |
831 | PCI_SLOT(e->devid), | |
832 | PCI_FUNC(e->devid), | |
833 | e->flags); | |
834 | ||
5d0c8e49 | 835 | devid = e->devid; |
5ff4789d | 836 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
837 | break; |
838 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
839 | |
840 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
841 | "devid: %02x:%02x.%x flags: %02x\n", | |
842 | PCI_BUS(e->devid), | |
843 | PCI_SLOT(e->devid), | |
844 | PCI_FUNC(e->devid), | |
845 | e->flags); | |
846 | ||
5d0c8e49 JR |
847 | devid_start = e->devid; |
848 | flags = e->flags; | |
849 | ext_flags = 0; | |
58a3bee5 | 850 | alias = false; |
5d0c8e49 JR |
851 | break; |
852 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
853 | |
854 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
855 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
856 | PCI_BUS(e->devid), | |
857 | PCI_SLOT(e->devid), | |
858 | PCI_FUNC(e->devid), | |
859 | e->flags, | |
860 | PCI_BUS(e->ext >> 8), | |
861 | PCI_SLOT(e->ext >> 8), | |
862 | PCI_FUNC(e->ext >> 8)); | |
863 | ||
5d0c8e49 JR |
864 | devid = e->devid; |
865 | devid_to = e->ext >> 8; | |
7a6a3a08 | 866 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 867 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
868 | amd_iommu_alias_table[devid] = devid_to; |
869 | break; | |
870 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
871 | |
872 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
873 | "devid: %02x:%02x.%x flags: %02x " | |
874 | "devid_to: %02x:%02x.%x\n", | |
875 | PCI_BUS(e->devid), | |
876 | PCI_SLOT(e->devid), | |
877 | PCI_FUNC(e->devid), | |
878 | e->flags, | |
879 | PCI_BUS(e->ext >> 8), | |
880 | PCI_SLOT(e->ext >> 8), | |
881 | PCI_FUNC(e->ext >> 8)); | |
882 | ||
5d0c8e49 JR |
883 | devid_start = e->devid; |
884 | flags = e->flags; | |
885 | devid_to = e->ext >> 8; | |
886 | ext_flags = 0; | |
58a3bee5 | 887 | alias = true; |
5d0c8e49 JR |
888 | break; |
889 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
890 | |
891 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
892 | "flags: %02x ext: %08x\n", | |
893 | PCI_BUS(e->devid), | |
894 | PCI_SLOT(e->devid), | |
895 | PCI_FUNC(e->devid), | |
896 | e->flags, e->ext); | |
897 | ||
5d0c8e49 | 898 | devid = e->devid; |
5ff4789d JR |
899 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
900 | e->ext); | |
5d0c8e49 JR |
901 | break; |
902 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
903 | |
904 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
905 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
906 | PCI_BUS(e->devid), | |
907 | PCI_SLOT(e->devid), | |
908 | PCI_FUNC(e->devid), | |
909 | e->flags, e->ext); | |
910 | ||
5d0c8e49 JR |
911 | devid_start = e->devid; |
912 | flags = e->flags; | |
913 | ext_flags = e->ext; | |
58a3bee5 | 914 | alias = false; |
5d0c8e49 JR |
915 | break; |
916 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
917 | |
918 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
919 | PCI_BUS(e->devid), | |
920 | PCI_SLOT(e->devid), | |
921 | PCI_FUNC(e->devid)); | |
922 | ||
5d0c8e49 JR |
923 | devid = e->devid; |
924 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 925 | if (alias) { |
5d0c8e49 | 926 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
927 | set_dev_entry_from_acpi(iommu, |
928 | devid_to, flags, ext_flags); | |
929 | } | |
930 | set_dev_entry_from_acpi(iommu, dev_i, | |
931 | flags, ext_flags); | |
5d0c8e49 JR |
932 | } |
933 | break; | |
934 | default: | |
935 | break; | |
936 | } | |
937 | ||
b514e555 | 938 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
939 | } |
940 | } | |
941 | ||
b65233a9 | 942 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
943 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
944 | { | |
0de66d5b | 945 | u32 i; |
5d0c8e49 JR |
946 | |
947 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
948 | set_iommu_for_device(iommu, i); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
e47d402d JR |
953 | static void __init free_iommu_one(struct amd_iommu *iommu) |
954 | { | |
955 | free_command_buffer(iommu); | |
335503e5 | 956 | free_event_buffer(iommu); |
1a29ac01 | 957 | free_ppr_log(iommu); |
e47d402d JR |
958 | iommu_unmap_mmio_space(iommu); |
959 | } | |
960 | ||
961 | static void __init free_iommu_all(void) | |
962 | { | |
963 | struct amd_iommu *iommu, *next; | |
964 | ||
3bd22172 | 965 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
966 | list_del(&iommu->list); |
967 | free_iommu_one(iommu); | |
968 | kfree(iommu); | |
969 | } | |
970 | } | |
971 | ||
b65233a9 JR |
972 | /* |
973 | * This function clues the initialization function for one IOMMU | |
974 | * together and also allocates the command buffer and programs the | |
975 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
976 | */ | |
e47d402d JR |
977 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
978 | { | |
979 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
980 | |
981 | /* Add IOMMU to internal data structures */ | |
e47d402d | 982 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
983 | iommu->index = amd_iommus_present++; |
984 | ||
985 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
986 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
987 | return -ENOSYS; | |
988 | } | |
989 | ||
990 | /* Index is fine - add IOMMU to the array */ | |
991 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
992 | |
993 | /* | |
994 | * Copy data from ACPI table entry to the iommu struct | |
995 | */ | |
3eaf28a1 JR |
996 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
997 | if (!iommu->dev) | |
998 | return 1; | |
999 | ||
e47d402d | 1000 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1001 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
1002 | iommu->mmio_phys = h->mmio_phys; |
1003 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
1004 | if (!iommu->mmio_base) | |
1005 | return -ENOMEM; | |
1006 | ||
e47d402d JR |
1007 | iommu->cmd_buf = alloc_command_buffer(iommu); |
1008 | if (!iommu->cmd_buf) | |
1009 | return -ENOMEM; | |
1010 | ||
335503e5 JR |
1011 | iommu->evt_buf = alloc_event_buffer(iommu); |
1012 | if (!iommu->evt_buf) | |
1013 | return -ENOMEM; | |
1014 | ||
a80dc3e0 JR |
1015 | iommu->int_enabled = false; |
1016 | ||
e47d402d JR |
1017 | init_iommu_from_pci(iommu); |
1018 | init_iommu_from_acpi(iommu, h); | |
1019 | init_iommu_devices(iommu); | |
1020 | ||
1a29ac01 JR |
1021 | if (iommu_feature(iommu, FEATURE_PPR)) { |
1022 | iommu->ppr_log = alloc_ppr_log(iommu); | |
1023 | if (!iommu->ppr_log) | |
1024 | return -ENOMEM; | |
1025 | } | |
1026 | ||
318afd41 JR |
1027 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
1028 | amd_iommu_np_cache = true; | |
1029 | ||
8a66712b | 1030 | return pci_enable_device(iommu->dev); |
e47d402d JR |
1031 | } |
1032 | ||
b65233a9 JR |
1033 | /* |
1034 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1035 | * IOMMU structure and initializes it with init_iommu_one() | |
1036 | */ | |
e47d402d JR |
1037 | static int __init init_iommu_all(struct acpi_table_header *table) |
1038 | { | |
1039 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1040 | struct ivhd_header *h; | |
1041 | struct amd_iommu *iommu; | |
1042 | int ret; | |
1043 | ||
e47d402d JR |
1044 | end += table->length; |
1045 | p += IVRS_HEADER_LENGTH; | |
1046 | ||
1047 | while (p < end) { | |
1048 | h = (struct ivhd_header *)p; | |
1049 | switch (*p) { | |
1050 | case ACPI_IVHD_TYPE: | |
9c72041f | 1051 | |
ae908c22 | 1052 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
1053 | "seg: %d flags: %01x info %04x\n", |
1054 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
1055 | PCI_FUNC(h->devid), h->cap_ptr, | |
1056 | h->pci_seg, h->flags, h->info); | |
1057 | DUMP_printk(" mmio-addr: %016llx\n", | |
1058 | h->mmio_phys); | |
1059 | ||
e47d402d | 1060 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
3551a708 JR |
1061 | if (iommu == NULL) { |
1062 | amd_iommu_init_err = -ENOMEM; | |
1063 | return 0; | |
1064 | } | |
1065 | ||
e47d402d | 1066 | ret = init_iommu_one(iommu, h); |
3551a708 JR |
1067 | if (ret) { |
1068 | amd_iommu_init_err = ret; | |
1069 | return 0; | |
1070 | } | |
e47d402d JR |
1071 | break; |
1072 | default: | |
1073 | break; | |
1074 | } | |
1075 | p += h->length; | |
1076 | ||
1077 | } | |
1078 | WARN_ON(p != end); | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
a80dc3e0 JR |
1083 | /**************************************************************************** |
1084 | * | |
1085 | * The following functions initialize the MSI interrupts for all IOMMUs | |
1086 | * in the system. Its a bit challenging because there could be multiple | |
1087 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
1088 | * pci_dev. | |
1089 | * | |
1090 | ****************************************************************************/ | |
1091 | ||
9f800de3 | 1092 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1093 | { |
1094 | int r; | |
a80dc3e0 JR |
1095 | |
1096 | if (pci_enable_msi(iommu->dev)) | |
1097 | return 1; | |
1098 | ||
72fe00f0 JR |
1099 | r = request_threaded_irq(iommu->dev->irq, |
1100 | amd_iommu_int_handler, | |
1101 | amd_iommu_int_thread, | |
1102 | 0, "AMD-Vi", | |
1103 | iommu->dev); | |
a80dc3e0 JR |
1104 | |
1105 | if (r) { | |
1106 | pci_disable_msi(iommu->dev); | |
1107 | return 1; | |
1108 | } | |
1109 | ||
fab6afa3 | 1110 | iommu->int_enabled = true; |
58492e12 JR |
1111 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
1112 | ||
1a29ac01 JR |
1113 | if (iommu->ppr_log != NULL) |
1114 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1115 | ||
a80dc3e0 JR |
1116 | return 0; |
1117 | } | |
1118 | ||
05f92db9 | 1119 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1120 | { |
1121 | if (iommu->int_enabled) | |
1122 | return 0; | |
1123 | ||
d91cecdd | 1124 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
1125 | return iommu_setup_msi(iommu); |
1126 | ||
1127 | return 1; | |
1128 | } | |
1129 | ||
b65233a9 JR |
1130 | /**************************************************************************** |
1131 | * | |
1132 | * The next functions belong to the third pass of parsing the ACPI | |
1133 | * table. In this last pass the memory mapping requirements are | |
1134 | * gathered (like exclusion and unity mapping reanges). | |
1135 | * | |
1136 | ****************************************************************************/ | |
1137 | ||
be2a022c JR |
1138 | static void __init free_unity_maps(void) |
1139 | { | |
1140 | struct unity_map_entry *entry, *next; | |
1141 | ||
1142 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1143 | list_del(&entry->list); | |
1144 | kfree(entry); | |
1145 | } | |
1146 | } | |
1147 | ||
b65233a9 | 1148 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1149 | static int __init init_exclusion_range(struct ivmd_header *m) |
1150 | { | |
1151 | int i; | |
1152 | ||
1153 | switch (m->type) { | |
1154 | case ACPI_IVMD_TYPE: | |
1155 | set_device_exclusion_range(m->devid, m); | |
1156 | break; | |
1157 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1158 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1159 | set_device_exclusion_range(i, m); |
1160 | break; | |
1161 | case ACPI_IVMD_TYPE_RANGE: | |
1162 | for (i = m->devid; i <= m->aux; ++i) | |
1163 | set_device_exclusion_range(i, m); | |
1164 | break; | |
1165 | default: | |
1166 | break; | |
1167 | } | |
1168 | ||
1169 | return 0; | |
1170 | } | |
1171 | ||
b65233a9 | 1172 | /* called for unity map ACPI definition */ |
be2a022c JR |
1173 | static int __init init_unity_map_range(struct ivmd_header *m) |
1174 | { | |
1175 | struct unity_map_entry *e = 0; | |
02acc43a | 1176 | char *s; |
be2a022c JR |
1177 | |
1178 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1179 | if (e == NULL) | |
1180 | return -ENOMEM; | |
1181 | ||
1182 | switch (m->type) { | |
1183 | default: | |
0bc252f4 JR |
1184 | kfree(e); |
1185 | return 0; | |
be2a022c | 1186 | case ACPI_IVMD_TYPE: |
02acc43a | 1187 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1188 | e->devid_start = e->devid_end = m->devid; |
1189 | break; | |
1190 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1191 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1192 | e->devid_start = 0; |
1193 | e->devid_end = amd_iommu_last_bdf; | |
1194 | break; | |
1195 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1196 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1197 | e->devid_start = m->devid; |
1198 | e->devid_end = m->aux; | |
1199 | break; | |
1200 | } | |
1201 | e->address_start = PAGE_ALIGN(m->range_start); | |
1202 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1203 | e->prot = m->flags >> 1; | |
1204 | ||
02acc43a JR |
1205 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1206 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1207 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1208 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1209 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1210 | e->address_start, e->address_end, m->flags); | |
1211 | ||
be2a022c JR |
1212 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
b65233a9 | 1217 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1218 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1219 | { | |
1220 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1221 | struct ivmd_header *m; | |
1222 | ||
be2a022c JR |
1223 | end += table->length; |
1224 | p += IVRS_HEADER_LENGTH; | |
1225 | ||
1226 | while (p < end) { | |
1227 | m = (struct ivmd_header *)p; | |
1228 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1229 | init_exclusion_range(m); | |
1230 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1231 | init_unity_map_range(m); | |
1232 | ||
1233 | p += m->length; | |
1234 | } | |
1235 | ||
1236 | return 0; | |
1237 | } | |
1238 | ||
9f5f5fb3 JR |
1239 | /* |
1240 | * Init the device table to not allow DMA access for devices and | |
1241 | * suppress all page faults | |
1242 | */ | |
1243 | static void init_device_table(void) | |
1244 | { | |
0de66d5b | 1245 | u32 devid; |
9f5f5fb3 JR |
1246 | |
1247 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1248 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1249 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1250 | } |
1251 | } | |
1252 | ||
e9bf5197 JR |
1253 | static void iommu_init_flags(struct amd_iommu *iommu) |
1254 | { | |
1255 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1256 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1257 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1258 | ||
1259 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1260 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1261 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1262 | ||
1263 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1264 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1265 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1266 | ||
1267 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1268 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1269 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1270 | ||
1271 | /* | |
1272 | * make IOMMU memory accesses cache coherent | |
1273 | */ | |
1274 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1275 | } | |
1276 | ||
5bcd757f | 1277 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1278 | { |
5bcd757f MG |
1279 | int i, j; |
1280 | u32 ioc_feature_control; | |
1281 | struct pci_dev *pdev = NULL; | |
1282 | ||
1283 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
1284 | if (!is_rd890_iommu(iommu->dev)) | |
1285 | return; | |
1286 | ||
1287 | /* | |
1288 | * First, we need to ensure that the iommu is enabled. This is | |
1289 | * controlled by a register in the northbridge | |
1290 | */ | |
1291 | pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0)); | |
1292 | ||
1293 | if (!pdev) | |
1294 | return; | |
1295 | ||
1296 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1297 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1298 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1299 | ||
1300 | /* Enable the iommu */ | |
1301 | if (!(ioc_feature_control & 0x1)) | |
1302 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1303 | ||
1304 | pci_dev_put(pdev); | |
1305 | ||
1306 | /* Restore the iommu BAR */ | |
1307 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1308 | iommu->stored_addr_lo); | |
1309 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1310 | iommu->stored_addr_hi); | |
1311 | ||
1312 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1313 | for (i = 0; i < 6; i++) | |
1314 | for (j = 0; j < 0x12; j++) | |
1315 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1316 | ||
1317 | /* Restore the l2 indirect regs */ | |
1318 | for (i = 0; i < 0x83; i++) | |
1319 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1320 | ||
1321 | /* Lock PCI setup registers */ | |
1322 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1323 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1324 | } |
1325 | ||
b65233a9 JR |
1326 | /* |
1327 | * This function finally enables all IOMMUs found in the system after | |
1328 | * they have been initialized | |
1329 | */ | |
05f92db9 | 1330 | static void enable_iommus(void) |
8736197b JR |
1331 | { |
1332 | struct amd_iommu *iommu; | |
1333 | ||
3bd22172 | 1334 | for_each_iommu(iommu) { |
a8c485bb | 1335 | iommu_disable(iommu); |
e9bf5197 | 1336 | iommu_init_flags(iommu); |
58492e12 JR |
1337 | iommu_set_device_table(iommu); |
1338 | iommu_enable_command_buffer(iommu); | |
1339 | iommu_enable_event_buffer(iommu); | |
1a29ac01 | 1340 | iommu_enable_ppr_log(iommu); |
8736197b | 1341 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1342 | iommu_init_msi(iommu); |
8736197b | 1343 | iommu_enable(iommu); |
7d0c5cc5 | 1344 | iommu_flush_all_caches(iommu); |
8736197b JR |
1345 | } |
1346 | } | |
1347 | ||
92ac4320 JR |
1348 | static void disable_iommus(void) |
1349 | { | |
1350 | struct amd_iommu *iommu; | |
1351 | ||
1352 | for_each_iommu(iommu) | |
1353 | iommu_disable(iommu); | |
1354 | } | |
1355 | ||
7441e9cb JR |
1356 | /* |
1357 | * Suspend/Resume support | |
1358 | * disable suspend until real resume implemented | |
1359 | */ | |
1360 | ||
f3c6ea1b | 1361 | static void amd_iommu_resume(void) |
7441e9cb | 1362 | { |
5bcd757f MG |
1363 | struct amd_iommu *iommu; |
1364 | ||
1365 | for_each_iommu(iommu) | |
1366 | iommu_apply_resume_quirks(iommu); | |
1367 | ||
736501ee JR |
1368 | /* re-load the hardware */ |
1369 | enable_iommus(); | |
1370 | ||
1371 | /* | |
1372 | * we have to flush after the IOMMUs are enabled because a | |
1373 | * disabled IOMMU will never execute the commands we send | |
1374 | */ | |
7d0c5cc5 JR |
1375 | for_each_iommu(iommu) |
1376 | iommu_flush_all_caches(iommu); | |
7441e9cb JR |
1377 | } |
1378 | ||
f3c6ea1b | 1379 | static int amd_iommu_suspend(void) |
7441e9cb | 1380 | { |
736501ee JR |
1381 | /* disable IOMMUs to go out of the way for BIOS */ |
1382 | disable_iommus(); | |
1383 | ||
1384 | return 0; | |
7441e9cb JR |
1385 | } |
1386 | ||
f3c6ea1b | 1387 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1388 | .suspend = amd_iommu_suspend, |
1389 | .resume = amd_iommu_resume, | |
1390 | }; | |
1391 | ||
b65233a9 JR |
1392 | /* |
1393 | * This is the core init function for AMD IOMMU hardware in the system. | |
1394 | * This function is called from the generic x86 DMA layer initialization | |
1395 | * code. | |
1396 | * | |
1397 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1398 | * three times: | |
1399 | * | |
1400 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1401 | * Upon this information the size of the data structures is | |
1402 | * determined that needs to be allocated. | |
1403 | * | |
1404 | * 2 pass) Initialize the data structures just allocated with the | |
1405 | * information in the ACPI table about available AMD IOMMUs | |
1406 | * in the system. It also maps the PCI devices in the | |
1407 | * system to specific IOMMUs | |
1408 | * | |
1409 | * 3 pass) After the basic data structures are allocated and | |
1410 | * initialized we update them with information about memory | |
1411 | * remapping requirements parsed out of the ACPI table in | |
1412 | * this last pass. | |
1413 | * | |
1414 | * After that the hardware is initialized and ready to go. In the last | |
1415 | * step we do some Linux specific things like registering the driver in | |
1416 | * the dma_ops interface and initializing the suspend/resume support | |
1417 | * functions. Finally it prints some information about AMD IOMMUs and | |
1418 | * the driver state and enables the hardware. | |
1419 | */ | |
ea1b0d39 | 1420 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1421 | { |
1422 | int i, ret = 0; | |
1423 | ||
fe74c9cf JR |
1424 | /* |
1425 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1426 | * we need to handle. Upon this information the shared data | |
1427 | * structures for the IOMMUs in the system will be allocated | |
1428 | */ | |
1429 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1430 | return -ENODEV; | |
1431 | ||
3551a708 JR |
1432 | ret = amd_iommu_init_err; |
1433 | if (ret) | |
1434 | goto out; | |
1435 | ||
c571484e JR |
1436 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1437 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1438 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1439 | |
1440 | ret = -ENOMEM; | |
1441 | ||
1442 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1443 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1444 | get_order(dev_table_size)); |
1445 | if (amd_iommu_dev_table == NULL) | |
1446 | goto out; | |
1447 | ||
1448 | /* | |
1449 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1450 | * IOMMU see for that device | |
1451 | */ | |
1452 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1453 | get_order(alias_table_size)); | |
1454 | if (amd_iommu_alias_table == NULL) | |
1455 | goto free; | |
1456 | ||
1457 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1458 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1459 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1460 | get_order(rlookup_table_size)); |
1461 | if (amd_iommu_rlookup_table == NULL) | |
1462 | goto free; | |
1463 | ||
5dc8bff0 JR |
1464 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1465 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1466 | get_order(MAX_DOMAIN_ID/8)); |
1467 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1468 | goto free; | |
1469 | ||
9f5f5fb3 JR |
1470 | /* init the device table */ |
1471 | init_device_table(); | |
1472 | ||
fe74c9cf | 1473 | /* |
5dc8bff0 | 1474 | * let all alias entries point to itself |
fe74c9cf | 1475 | */ |
3a61ec38 | 1476 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1477 | amd_iommu_alias_table[i] = i; |
1478 | ||
fe74c9cf JR |
1479 | /* |
1480 | * never allocate domain 0 because its used as the non-allocated and | |
1481 | * error value placeholder | |
1482 | */ | |
1483 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1484 | ||
aeb26f55 JR |
1485 | spin_lock_init(&amd_iommu_pd_lock); |
1486 | ||
fe74c9cf JR |
1487 | /* |
1488 | * now the data structures are allocated and basically initialized | |
1489 | * start the real acpi table scan | |
1490 | */ | |
1491 | ret = -ENODEV; | |
1492 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1493 | goto free; | |
1494 | ||
3551a708 JR |
1495 | if (amd_iommu_init_err) { |
1496 | ret = amd_iommu_init_err; | |
0f764806 | 1497 | goto free; |
3551a708 | 1498 | } |
0f764806 | 1499 | |
fe74c9cf JR |
1500 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) |
1501 | goto free; | |
1502 | ||
3551a708 JR |
1503 | if (amd_iommu_init_err) { |
1504 | ret = amd_iommu_init_err; | |
1505 | goto free; | |
1506 | } | |
1507 | ||
b7cc9554 JR |
1508 | ret = amd_iommu_init_devices(); |
1509 | if (ret) | |
1510 | goto free; | |
1511 | ||
75f66533 CW |
1512 | enable_iommus(); |
1513 | ||
4751a951 JR |
1514 | if (iommu_pass_through) |
1515 | ret = amd_iommu_init_passthrough(); | |
1516 | else | |
1517 | ret = amd_iommu_init_dma_ops(); | |
f5325094 | 1518 | |
7441e9cb | 1519 | if (ret) |
e82752d8 | 1520 | goto free_disable; |
7441e9cb | 1521 | |
f5325094 JR |
1522 | amd_iommu_init_api(); |
1523 | ||
8638c491 JR |
1524 | amd_iommu_init_notifier(); |
1525 | ||
f3c6ea1b RW |
1526 | register_syscore_ops(&amd_iommu_syscore_ops); |
1527 | ||
4751a951 JR |
1528 | if (iommu_pass_through) |
1529 | goto out; | |
1530 | ||
afa9fdc2 | 1531 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1532 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1533 | else |
4c6f40d4 | 1534 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1535 | |
338bac52 | 1536 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1537 | out: |
1538 | return ret; | |
1539 | ||
e82752d8 | 1540 | free_disable: |
75f66533 | 1541 | disable_iommus(); |
b7cc9554 | 1542 | |
e82752d8 | 1543 | free: |
b7cc9554 JR |
1544 | amd_iommu_uninit_devices(); |
1545 | ||
d58befd3 JR |
1546 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1547 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1548 | |
9a836de0 JR |
1549 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1550 | get_order(rlookup_table_size)); | |
fe74c9cf | 1551 | |
9a836de0 JR |
1552 | free_pages((unsigned long)amd_iommu_alias_table, |
1553 | get_order(alias_table_size)); | |
fe74c9cf | 1554 | |
9a836de0 JR |
1555 | free_pages((unsigned long)amd_iommu_dev_table, |
1556 | get_order(dev_table_size)); | |
fe74c9cf JR |
1557 | |
1558 | free_iommu_all(); | |
1559 | ||
1560 | free_unity_maps(); | |
1561 | ||
d7f07769 JR |
1562 | #ifdef CONFIG_GART_IOMMU |
1563 | /* | |
1564 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1565 | * if possible. | |
1566 | */ | |
1567 | gart_iommu_init(); | |
1568 | ||
1569 | #endif | |
1570 | ||
fe74c9cf JR |
1571 | goto out; |
1572 | } | |
1573 | ||
b65233a9 JR |
1574 | /**************************************************************************** |
1575 | * | |
1576 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1577 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1578 | * IOMMUs | |
1579 | * | |
1580 | ****************************************************************************/ | |
ae7877de JR |
1581 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1582 | { | |
1583 | return 0; | |
1584 | } | |
1585 | ||
480125ba | 1586 | int __init amd_iommu_detect(void) |
ae7877de | 1587 | { |
75f1cdf1 | 1588 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 1589 | return -ENODEV; |
ae7877de | 1590 | |
a5235725 | 1591 | if (amd_iommu_disabled) |
480125ba | 1592 | return -ENODEV; |
a5235725 | 1593 | |
ae7877de JR |
1594 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1595 | iommu_detected = 1; | |
c1cbebee | 1596 | amd_iommu_detected = 1; |
ea1b0d39 | 1597 | x86_init.iommu.iommu_init = amd_iommu_init; |
11bd04f6 | 1598 | |
5d990b62 CW |
1599 | /* Make sure ACS will be enabled */ |
1600 | pci_request_acs(); | |
480125ba | 1601 | return 1; |
ae7877de | 1602 | } |
480125ba | 1603 | return -ENODEV; |
ae7877de JR |
1604 | } |
1605 | ||
b65233a9 JR |
1606 | /**************************************************************************** |
1607 | * | |
1608 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1609 | * options. | |
1610 | * | |
1611 | ****************************************************************************/ | |
1612 | ||
fefda117 JR |
1613 | static int __init parse_amd_iommu_dump(char *str) |
1614 | { | |
1615 | amd_iommu_dump = true; | |
1616 | ||
1617 | return 1; | |
1618 | } | |
1619 | ||
918ad6c5 JR |
1620 | static int __init parse_amd_iommu_options(char *str) |
1621 | { | |
1622 | for (; *str; ++str) { | |
695b5676 | 1623 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1624 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1625 | if (strncmp(str, "off", 3) == 0) |
1626 | amd_iommu_disabled = true; | |
918ad6c5 JR |
1627 | } |
1628 | ||
1629 | return 1; | |
1630 | } | |
1631 | ||
fefda117 | 1632 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1633 | __setup("amd_iommu=", parse_amd_iommu_options); |
22e6daf4 KRW |
1634 | |
1635 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
1636 | gart_iommu_hole_init, | |
1637 | 0, | |
1638 | 0); |