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f6e2e6b6 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
f6e2e6b6 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/acpi.h> | |
f6e2e6b6 | 22 | #include <linux/list.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f3c6ea1b | 24 | #include <linux/syscore_ops.h> |
a80dc3e0 JR |
25 | #include <linux/interrupt.h> |
26 | #include <linux/msi.h> | |
403f81d8 | 27 | #include <linux/amd-iommu.h> |
400a28a0 | 28 | #include <linux/export.h> |
f6e2e6b6 | 29 | #include <asm/pci-direct.h> |
46a7fa27 | 30 | #include <asm/iommu.h> |
1d9b16d1 | 31 | #include <asm/gart.h> |
ea1b0d39 | 32 | #include <asm/x86_init.h> |
22e6daf4 | 33 | #include <asm/iommu_table.h> |
403f81d8 JR |
34 | |
35 | #include "amd_iommu_proto.h" | |
36 | #include "amd_iommu_types.h" | |
37 | ||
f6e2e6b6 JR |
38 | /* |
39 | * definitions for the ACPI scanning code | |
40 | */ | |
f6e2e6b6 | 41 | #define IVRS_HEADER_LENGTH 48 |
f6e2e6b6 JR |
42 | |
43 | #define ACPI_IVHD_TYPE 0x10 | |
44 | #define ACPI_IVMD_TYPE_ALL 0x20 | |
45 | #define ACPI_IVMD_TYPE 0x21 | |
46 | #define ACPI_IVMD_TYPE_RANGE 0x22 | |
47 | ||
48 | #define IVHD_DEV_ALL 0x01 | |
49 | #define IVHD_DEV_SELECT 0x02 | |
50 | #define IVHD_DEV_SELECT_RANGE_START 0x03 | |
51 | #define IVHD_DEV_RANGE_END 0x04 | |
52 | #define IVHD_DEV_ALIAS 0x42 | |
53 | #define IVHD_DEV_ALIAS_RANGE 0x43 | |
54 | #define IVHD_DEV_EXT_SELECT 0x46 | |
55 | #define IVHD_DEV_EXT_SELECT_RANGE 0x47 | |
56 | ||
6da7342f JR |
57 | #define IVHD_FLAG_HT_TUN_EN_MASK 0x01 |
58 | #define IVHD_FLAG_PASSPW_EN_MASK 0x02 | |
59 | #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 | |
60 | #define IVHD_FLAG_ISOC_EN_MASK 0x08 | |
f6e2e6b6 JR |
61 | |
62 | #define IVMD_FLAG_EXCL_RANGE 0x08 | |
63 | #define IVMD_FLAG_UNITY_MAP 0x01 | |
64 | ||
65 | #define ACPI_DEVFLAG_INITPASS 0x01 | |
66 | #define ACPI_DEVFLAG_EXTINT 0x02 | |
67 | #define ACPI_DEVFLAG_NMI 0x04 | |
68 | #define ACPI_DEVFLAG_SYSMGT1 0x10 | |
69 | #define ACPI_DEVFLAG_SYSMGT2 0x20 | |
70 | #define ACPI_DEVFLAG_LINT0 0x40 | |
71 | #define ACPI_DEVFLAG_LINT1 0x80 | |
72 | #define ACPI_DEVFLAG_ATSDIS 0x10000000 | |
73 | ||
b65233a9 JR |
74 | /* |
75 | * ACPI table definitions | |
76 | * | |
77 | * These data structures are laid over the table to parse the important values | |
78 | * out of it. | |
79 | */ | |
80 | ||
81 | /* | |
82 | * structure describing one IOMMU in the ACPI table. Typically followed by one | |
83 | * or more ivhd_entrys. | |
84 | */ | |
f6e2e6b6 JR |
85 | struct ivhd_header { |
86 | u8 type; | |
87 | u8 flags; | |
88 | u16 length; | |
89 | u16 devid; | |
90 | u16 cap_ptr; | |
91 | u64 mmio_phys; | |
92 | u16 pci_seg; | |
93 | u16 info; | |
94 | u32 reserved; | |
95 | } __attribute__((packed)); | |
96 | ||
b65233a9 JR |
97 | /* |
98 | * A device entry describing which devices a specific IOMMU translates and | |
99 | * which requestor ids they use. | |
100 | */ | |
f6e2e6b6 JR |
101 | struct ivhd_entry { |
102 | u8 type; | |
103 | u16 devid; | |
104 | u8 flags; | |
105 | u32 ext; | |
106 | } __attribute__((packed)); | |
107 | ||
b65233a9 JR |
108 | /* |
109 | * An AMD IOMMU memory definition structure. It defines things like exclusion | |
110 | * ranges for devices and regions that should be unity mapped. | |
111 | */ | |
f6e2e6b6 JR |
112 | struct ivmd_header { |
113 | u8 type; | |
114 | u8 flags; | |
115 | u16 length; | |
116 | u16 devid; | |
117 | u16 aux; | |
118 | u64 resv; | |
119 | u64 range_start; | |
120 | u64 range_length; | |
121 | } __attribute__((packed)); | |
122 | ||
fefda117 JR |
123 | bool amd_iommu_dump; |
124 | ||
c1cbebee | 125 | static int __initdata amd_iommu_detected; |
a5235725 | 126 | static bool __initdata amd_iommu_disabled; |
c1cbebee | 127 | |
b65233a9 JR |
128 | u16 amd_iommu_last_bdf; /* largest PCI device id we have |
129 | to handle */ | |
2e22847f | 130 | LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings |
b65233a9 | 131 | we find in ACPI */ |
afa9fdc2 | 132 | bool amd_iommu_unmap_flush; /* if true, flush on every unmap */ |
928abd25 | 133 | |
2e22847f | 134 | LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the |
b65233a9 | 135 | system */ |
928abd25 | 136 | |
bb52777e JR |
137 | /* Array to assign indices to IOMMUs*/ |
138 | struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
139 | int amd_iommus_present; | |
140 | ||
318afd41 JR |
141 | /* IOMMUs have a non-present cache? */ |
142 | bool amd_iommu_np_cache __read_mostly; | |
60f723b4 | 143 | bool amd_iommu_iotlb_sup __read_mostly = true; |
318afd41 | 144 | |
62f71abb JR |
145 | u32 amd_iommu_max_pasids __read_mostly = ~0; |
146 | ||
400a28a0 JR |
147 | bool amd_iommu_v2_present __read_mostly; |
148 | ||
0f764806 | 149 | /* |
3551a708 | 150 | * The ACPI table parsing functions set this variable on an error |
0f764806 | 151 | */ |
3551a708 | 152 | static int __initdata amd_iommu_init_err; |
0f764806 | 153 | |
aeb26f55 JR |
154 | /* |
155 | * List of protection domains - used during resume | |
156 | */ | |
157 | LIST_HEAD(amd_iommu_pd_list); | |
158 | spinlock_t amd_iommu_pd_lock; | |
159 | ||
b65233a9 JR |
160 | /* |
161 | * Pointer to the device table which is shared by all AMD IOMMUs | |
162 | * it is indexed by the PCI device id or the HT unit id and contains | |
163 | * information about the domain the device belongs to as well as the | |
164 | * page table root pointer. | |
165 | */ | |
928abd25 | 166 | struct dev_table_entry *amd_iommu_dev_table; |
b65233a9 JR |
167 | |
168 | /* | |
169 | * The alias table is a driver specific data structure which contains the | |
170 | * mappings of the PCI device ids to the actual requestor ids on the IOMMU. | |
171 | * More than one device can share the same requestor id. | |
172 | */ | |
928abd25 | 173 | u16 *amd_iommu_alias_table; |
b65233a9 JR |
174 | |
175 | /* | |
176 | * The rlookup table is used to find the IOMMU which is responsible | |
177 | * for a specific device. It is also indexed by the PCI device id. | |
178 | */ | |
928abd25 | 179 | struct amd_iommu **amd_iommu_rlookup_table; |
b65233a9 | 180 | |
b65233a9 JR |
181 | /* |
182 | * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap | |
183 | * to know which ones are already in use. | |
184 | */ | |
928abd25 JR |
185 | unsigned long *amd_iommu_pd_alloc_bitmap; |
186 | ||
b65233a9 JR |
187 | static u32 dev_table_size; /* size of the device table */ |
188 | static u32 alias_table_size; /* size of the alias table */ | |
189 | static u32 rlookup_table_size; /* size if the rlookup table */ | |
3e8064ba | 190 | |
7d0c5cc5 JR |
191 | /* |
192 | * This function flushes all internal caches of | |
193 | * the IOMMU used by this driver. | |
194 | */ | |
195 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
196 | ||
208ec8c9 JR |
197 | static inline void update_last_devid(u16 devid) |
198 | { | |
199 | if (devid > amd_iommu_last_bdf) | |
200 | amd_iommu_last_bdf = devid; | |
201 | } | |
202 | ||
c571484e JR |
203 | static inline unsigned long tbl_size(int entry_size) |
204 | { | |
205 | unsigned shift = PAGE_SHIFT + | |
421f909c | 206 | get_order(((int)amd_iommu_last_bdf + 1) * entry_size); |
c571484e JR |
207 | |
208 | return 1UL << shift; | |
209 | } | |
210 | ||
5bcd757f MG |
211 | /* Access to l1 and l2 indexed register spaces */ |
212 | ||
213 | static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) | |
214 | { | |
215 | u32 val; | |
216 | ||
217 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
218 | pci_read_config_dword(iommu->dev, 0xfc, &val); | |
219 | return val; | |
220 | } | |
221 | ||
222 | static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) | |
223 | { | |
224 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); | |
225 | pci_write_config_dword(iommu->dev, 0xfc, val); | |
226 | pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); | |
227 | } | |
228 | ||
229 | static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) | |
230 | { | |
231 | u32 val; | |
232 | ||
233 | pci_write_config_dword(iommu->dev, 0xf0, address); | |
234 | pci_read_config_dword(iommu->dev, 0xf4, &val); | |
235 | return val; | |
236 | } | |
237 | ||
238 | static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) | |
239 | { | |
240 | pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); | |
241 | pci_write_config_dword(iommu->dev, 0xf4, val); | |
242 | } | |
243 | ||
b65233a9 JR |
244 | /**************************************************************************** |
245 | * | |
246 | * AMD IOMMU MMIO register space handling functions | |
247 | * | |
248 | * These functions are used to program the IOMMU device registers in | |
249 | * MMIO space required for that driver. | |
250 | * | |
251 | ****************************************************************************/ | |
3e8064ba | 252 | |
b65233a9 JR |
253 | /* |
254 | * This function set the exclusion range in the IOMMU. DMA accesses to the | |
255 | * exclusion range are passed through untranslated | |
256 | */ | |
05f92db9 | 257 | static void iommu_set_exclusion_range(struct amd_iommu *iommu) |
b2026aa2 JR |
258 | { |
259 | u64 start = iommu->exclusion_start & PAGE_MASK; | |
260 | u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; | |
261 | u64 entry; | |
262 | ||
263 | if (!iommu->exclusion_start) | |
264 | return; | |
265 | ||
266 | entry = start | MMIO_EXCL_ENABLE_MASK; | |
267 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, | |
268 | &entry, sizeof(entry)); | |
269 | ||
270 | entry = limit; | |
271 | memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, | |
272 | &entry, sizeof(entry)); | |
273 | } | |
274 | ||
b65233a9 | 275 | /* Programs the physical address of the device table into the IOMMU hardware */ |
b2026aa2 JR |
276 | static void __init iommu_set_device_table(struct amd_iommu *iommu) |
277 | { | |
f609891f | 278 | u64 entry; |
b2026aa2 JR |
279 | |
280 | BUG_ON(iommu->mmio_base == NULL); | |
281 | ||
282 | entry = virt_to_phys(amd_iommu_dev_table); | |
283 | entry |= (dev_table_size >> 12) - 1; | |
284 | memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, | |
285 | &entry, sizeof(entry)); | |
286 | } | |
287 | ||
b65233a9 | 288 | /* Generic functions to enable/disable certain features of the IOMMU. */ |
05f92db9 | 289 | static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
290 | { |
291 | u32 ctrl; | |
292 | ||
293 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
294 | ctrl |= (1 << bit); | |
295 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
296 | } | |
297 | ||
ca020711 | 298 | static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) |
b2026aa2 JR |
299 | { |
300 | u32 ctrl; | |
301 | ||
199d0d50 | 302 | ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET); |
b2026aa2 JR |
303 | ctrl &= ~(1 << bit); |
304 | writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); | |
305 | } | |
306 | ||
b65233a9 | 307 | /* Function to enable the hardware */ |
05f92db9 | 308 | static void iommu_enable(struct amd_iommu *iommu) |
b2026aa2 | 309 | { |
d99ddec3 JR |
310 | static const char * const feat_str[] = { |
311 | "PreF", "PPR", "X2APIC", "NX", "GT", "[5]", | |
312 | "IA", "GA", "HE", "PC", NULL | |
313 | }; | |
314 | int i; | |
315 | ||
316 | printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx", | |
a4e267c8 | 317 | dev_name(&iommu->dev->dev), iommu->cap_ptr); |
b2026aa2 | 318 | |
d99ddec3 JR |
319 | if (iommu->cap & (1 << IOMMU_CAP_EFR)) { |
320 | printk(KERN_CONT " extended features: "); | |
321 | for (i = 0; feat_str[i]; ++i) | |
322 | if (iommu_feature(iommu, (1ULL << i))) | |
323 | printk(KERN_CONT " %s", feat_str[i]); | |
324 | } | |
325 | printk(KERN_CONT "\n"); | |
326 | ||
b2026aa2 | 327 | iommu_feature_enable(iommu, CONTROL_IOMMU_EN); |
b2026aa2 JR |
328 | } |
329 | ||
92ac4320 | 330 | static void iommu_disable(struct amd_iommu *iommu) |
126c52be | 331 | { |
a8c485bb CW |
332 | /* Disable command buffer */ |
333 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
334 | ||
335 | /* Disable event logging and event interrupts */ | |
336 | iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); | |
337 | iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); | |
338 | ||
339 | /* Disable IOMMU hardware itself */ | |
92ac4320 | 340 | iommu_feature_disable(iommu, CONTROL_IOMMU_EN); |
126c52be JR |
341 | } |
342 | ||
b65233a9 JR |
343 | /* |
344 | * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in | |
345 | * the system has one. | |
346 | */ | |
6c56747b JR |
347 | static u8 * __init iommu_map_mmio_space(u64 address) |
348 | { | |
349 | u8 *ret; | |
350 | ||
e82752d8 JR |
351 | if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) { |
352 | pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n", | |
353 | address); | |
354 | pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n"); | |
6c56747b | 355 | return NULL; |
e82752d8 | 356 | } |
6c56747b JR |
357 | |
358 | ret = ioremap_nocache(address, MMIO_REGION_LENGTH); | |
359 | if (ret != NULL) | |
360 | return ret; | |
361 | ||
362 | release_mem_region(address, MMIO_REGION_LENGTH); | |
363 | ||
364 | return NULL; | |
365 | } | |
366 | ||
367 | static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) | |
368 | { | |
369 | if (iommu->mmio_base) | |
370 | iounmap(iommu->mmio_base); | |
371 | release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH); | |
372 | } | |
373 | ||
b65233a9 JR |
374 | /**************************************************************************** |
375 | * | |
376 | * The functions below belong to the first pass of AMD IOMMU ACPI table | |
377 | * parsing. In this pass we try to find out the highest device id this | |
378 | * code has to handle. Upon this information the size of the shared data | |
379 | * structures is determined later. | |
380 | * | |
381 | ****************************************************************************/ | |
382 | ||
b514e555 JR |
383 | /* |
384 | * This function calculates the length of a given IVHD entry | |
385 | */ | |
386 | static inline int ivhd_entry_length(u8 *ivhd) | |
387 | { | |
388 | return 0x04 << (*ivhd >> 6); | |
389 | } | |
390 | ||
b65233a9 JR |
391 | /* |
392 | * This function reads the last device id the IOMMU has to handle from the PCI | |
393 | * capability header for this IOMMU | |
394 | */ | |
3e8064ba JR |
395 | static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr) |
396 | { | |
397 | u32 cap; | |
398 | ||
399 | cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET); | |
d591b0a3 | 400 | update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap))); |
3e8064ba JR |
401 | |
402 | return 0; | |
403 | } | |
404 | ||
b65233a9 JR |
405 | /* |
406 | * After reading the highest device id from the IOMMU PCI capability header | |
407 | * this function looks if there is a higher device id defined in the ACPI table | |
408 | */ | |
3e8064ba JR |
409 | static int __init find_last_devid_from_ivhd(struct ivhd_header *h) |
410 | { | |
411 | u8 *p = (void *)h, *end = (void *)h; | |
412 | struct ivhd_entry *dev; | |
413 | ||
414 | p += sizeof(*h); | |
415 | end += h->length; | |
416 | ||
417 | find_last_devid_on_pci(PCI_BUS(h->devid), | |
418 | PCI_SLOT(h->devid), | |
419 | PCI_FUNC(h->devid), | |
420 | h->cap_ptr); | |
421 | ||
422 | while (p < end) { | |
423 | dev = (struct ivhd_entry *)p; | |
424 | switch (dev->type) { | |
425 | case IVHD_DEV_SELECT: | |
426 | case IVHD_DEV_RANGE_END: | |
427 | case IVHD_DEV_ALIAS: | |
428 | case IVHD_DEV_EXT_SELECT: | |
b65233a9 | 429 | /* all the above subfield types refer to device ids */ |
208ec8c9 | 430 | update_last_devid(dev->devid); |
3e8064ba JR |
431 | break; |
432 | default: | |
433 | break; | |
434 | } | |
b514e555 | 435 | p += ivhd_entry_length(p); |
3e8064ba JR |
436 | } |
437 | ||
438 | WARN_ON(p != end); | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
b65233a9 JR |
443 | /* |
444 | * Iterate over all IVHD entries in the ACPI table and find the highest device | |
445 | * id which we need to handle. This is the first of three functions which parse | |
446 | * the ACPI table. So we check the checksum here. | |
447 | */ | |
3e8064ba JR |
448 | static int __init find_last_devid_acpi(struct acpi_table_header *table) |
449 | { | |
450 | int i; | |
451 | u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table; | |
452 | struct ivhd_header *h; | |
453 | ||
454 | /* | |
455 | * Validate checksum here so we don't need to do it when | |
456 | * we actually parse the table | |
457 | */ | |
458 | for (i = 0; i < table->length; ++i) | |
459 | checksum += p[i]; | |
3551a708 | 460 | if (checksum != 0) { |
3e8064ba | 461 | /* ACPI table corrupt */ |
3551a708 JR |
462 | amd_iommu_init_err = -ENODEV; |
463 | return 0; | |
464 | } | |
3e8064ba JR |
465 | |
466 | p += IVRS_HEADER_LENGTH; | |
467 | ||
468 | end += table->length; | |
469 | while (p < end) { | |
470 | h = (struct ivhd_header *)p; | |
471 | switch (h->type) { | |
472 | case ACPI_IVHD_TYPE: | |
473 | find_last_devid_from_ivhd(h); | |
474 | break; | |
475 | default: | |
476 | break; | |
477 | } | |
478 | p += h->length; | |
479 | } | |
480 | WARN_ON(p != end); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
b65233a9 JR |
485 | /**************************************************************************** |
486 | * | |
487 | * The following functions belong the the code path which parses the ACPI table | |
488 | * the second time. In this ACPI parsing iteration we allocate IOMMU specific | |
489 | * data structures, initialize the device/alias/rlookup table and also | |
490 | * basically initialize the hardware. | |
491 | * | |
492 | ****************************************************************************/ | |
493 | ||
494 | /* | |
495 | * Allocates the command buffer. This buffer is per AMD IOMMU. We can | |
496 | * write commands to that buffer later and the IOMMU will execute them | |
497 | * asynchronously | |
498 | */ | |
b36ca91e JR |
499 | static u8 * __init alloc_command_buffer(struct amd_iommu *iommu) |
500 | { | |
d0312b21 | 501 | u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
b36ca91e | 502 | get_order(CMD_BUFFER_SIZE)); |
b36ca91e JR |
503 | |
504 | if (cmd_buf == NULL) | |
505 | return NULL; | |
506 | ||
549c90dc | 507 | iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED; |
b36ca91e | 508 | |
58492e12 JR |
509 | return cmd_buf; |
510 | } | |
511 | ||
93f1cc67 JR |
512 | /* |
513 | * This function resets the command buffer if the IOMMU stopped fetching | |
514 | * commands from it. | |
515 | */ | |
516 | void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) | |
517 | { | |
518 | iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); | |
519 | ||
520 | writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
521 | writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
522 | ||
523 | iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); | |
524 | } | |
525 | ||
58492e12 JR |
526 | /* |
527 | * This function writes the command buffer address to the hardware and | |
528 | * enables it. | |
529 | */ | |
530 | static void iommu_enable_command_buffer(struct amd_iommu *iommu) | |
531 | { | |
532 | u64 entry; | |
533 | ||
534 | BUG_ON(iommu->cmd_buf == NULL); | |
535 | ||
536 | entry = (u64)virt_to_phys(iommu->cmd_buf); | |
b36ca91e | 537 | entry |= MMIO_CMD_SIZE_512; |
58492e12 | 538 | |
b36ca91e | 539 | memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, |
58492e12 | 540 | &entry, sizeof(entry)); |
b36ca91e | 541 | |
93f1cc67 | 542 | amd_iommu_reset_cmd_buffer(iommu); |
549c90dc | 543 | iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED); |
b36ca91e JR |
544 | } |
545 | ||
546 | static void __init free_command_buffer(struct amd_iommu *iommu) | |
547 | { | |
23c1713f | 548 | free_pages((unsigned long)iommu->cmd_buf, |
549c90dc | 549 | get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED))); |
b36ca91e JR |
550 | } |
551 | ||
335503e5 JR |
552 | /* allocates the memory where the IOMMU will log its events to */ |
553 | static u8 * __init alloc_event_buffer(struct amd_iommu *iommu) | |
554 | { | |
335503e5 JR |
555 | iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
556 | get_order(EVT_BUFFER_SIZE)); | |
557 | ||
558 | if (iommu->evt_buf == NULL) | |
559 | return NULL; | |
560 | ||
1bc6f838 JR |
561 | iommu->evt_buf_size = EVT_BUFFER_SIZE; |
562 | ||
58492e12 JR |
563 | return iommu->evt_buf; |
564 | } | |
565 | ||
566 | static void iommu_enable_event_buffer(struct amd_iommu *iommu) | |
567 | { | |
568 | u64 entry; | |
569 | ||
570 | BUG_ON(iommu->evt_buf == NULL); | |
571 | ||
335503e5 | 572 | entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; |
58492e12 | 573 | |
335503e5 JR |
574 | memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, |
575 | &entry, sizeof(entry)); | |
576 | ||
09067207 JR |
577 | /* set head and tail to zero manually */ |
578 | writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
579 | writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
580 | ||
58492e12 | 581 | iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); |
335503e5 JR |
582 | } |
583 | ||
584 | static void __init free_event_buffer(struct amd_iommu *iommu) | |
585 | { | |
586 | free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); | |
587 | } | |
588 | ||
1a29ac01 JR |
589 | /* allocates the memory where the IOMMU will log its events to */ |
590 | static u8 * __init alloc_ppr_log(struct amd_iommu *iommu) | |
591 | { | |
592 | iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
593 | get_order(PPR_LOG_SIZE)); | |
594 | ||
595 | if (iommu->ppr_log == NULL) | |
596 | return NULL; | |
597 | ||
598 | return iommu->ppr_log; | |
599 | } | |
600 | ||
601 | static void iommu_enable_ppr_log(struct amd_iommu *iommu) | |
602 | { | |
603 | u64 entry; | |
604 | ||
605 | if (iommu->ppr_log == NULL) | |
606 | return; | |
607 | ||
608 | entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; | |
609 | ||
610 | memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, | |
611 | &entry, sizeof(entry)); | |
612 | ||
613 | /* set head and tail to zero manually */ | |
614 | writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); | |
615 | writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); | |
616 | ||
617 | iommu_feature_enable(iommu, CONTROL_PPFLOG_EN); | |
618 | iommu_feature_enable(iommu, CONTROL_PPR_EN); | |
619 | } | |
620 | ||
621 | static void __init free_ppr_log(struct amd_iommu *iommu) | |
622 | { | |
623 | if (iommu->ppr_log == NULL) | |
624 | return; | |
625 | ||
626 | free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); | |
627 | } | |
628 | ||
cbc33a90 JR |
629 | static void iommu_enable_gt(struct amd_iommu *iommu) |
630 | { | |
631 | if (!iommu_feature(iommu, FEATURE_GT)) | |
632 | return; | |
633 | ||
634 | iommu_feature_enable(iommu, CONTROL_GT_EN); | |
635 | } | |
636 | ||
b65233a9 | 637 | /* sets a specific bit in the device table entry. */ |
3566b778 JR |
638 | static void set_dev_entry_bit(u16 devid, u8 bit) |
639 | { | |
ee6c2868 JR |
640 | int i = (bit >> 6) & 0x03; |
641 | int _bit = bit & 0x3f; | |
3566b778 | 642 | |
ee6c2868 | 643 | amd_iommu_dev_table[devid].data[i] |= (1UL << _bit); |
3566b778 JR |
644 | } |
645 | ||
c5cca146 JR |
646 | static int get_dev_entry_bit(u16 devid, u8 bit) |
647 | { | |
ee6c2868 JR |
648 | int i = (bit >> 6) & 0x03; |
649 | int _bit = bit & 0x3f; | |
c5cca146 | 650 | |
ee6c2868 | 651 | return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit; |
c5cca146 JR |
652 | } |
653 | ||
654 | ||
655 | void amd_iommu_apply_erratum_63(u16 devid) | |
656 | { | |
657 | int sysmgt; | |
658 | ||
659 | sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) | | |
660 | (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1); | |
661 | ||
662 | if (sysmgt == 0x01) | |
663 | set_dev_entry_bit(devid, DEV_ENTRY_IW); | |
664 | } | |
665 | ||
5ff4789d JR |
666 | /* Writes the specific IOMMU for a device into the rlookup table */ |
667 | static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) | |
668 | { | |
669 | amd_iommu_rlookup_table[devid] = iommu; | |
670 | } | |
671 | ||
b65233a9 JR |
672 | /* |
673 | * This function takes the device specific flags read from the ACPI | |
674 | * table and sets up the device table entry with that information | |
675 | */ | |
5ff4789d JR |
676 | static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, |
677 | u16 devid, u32 flags, u32 ext_flags) | |
3566b778 JR |
678 | { |
679 | if (flags & ACPI_DEVFLAG_INITPASS) | |
680 | set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS); | |
681 | if (flags & ACPI_DEVFLAG_EXTINT) | |
682 | set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS); | |
683 | if (flags & ACPI_DEVFLAG_NMI) | |
684 | set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS); | |
685 | if (flags & ACPI_DEVFLAG_SYSMGT1) | |
686 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1); | |
687 | if (flags & ACPI_DEVFLAG_SYSMGT2) | |
688 | set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2); | |
689 | if (flags & ACPI_DEVFLAG_LINT0) | |
690 | set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS); | |
691 | if (flags & ACPI_DEVFLAG_LINT1) | |
692 | set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS); | |
3566b778 | 693 | |
c5cca146 JR |
694 | amd_iommu_apply_erratum_63(devid); |
695 | ||
5ff4789d | 696 | set_iommu_for_device(iommu, devid); |
3566b778 JR |
697 | } |
698 | ||
b65233a9 JR |
699 | /* |
700 | * Reads the device exclusion range from ACPI and initialize IOMMU with | |
701 | * it | |
702 | */ | |
3566b778 JR |
703 | static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m) |
704 | { | |
705 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
706 | ||
707 | if (!(m->flags & IVMD_FLAG_EXCL_RANGE)) | |
708 | return; | |
709 | ||
710 | if (iommu) { | |
b65233a9 JR |
711 | /* |
712 | * We only can configure exclusion ranges per IOMMU, not | |
713 | * per device. But we can enable the exclusion range per | |
714 | * device. This is done here | |
715 | */ | |
3566b778 JR |
716 | set_dev_entry_bit(m->devid, DEV_ENTRY_EX); |
717 | iommu->exclusion_start = m->range_start; | |
718 | iommu->exclusion_length = m->range_length; | |
719 | } | |
720 | } | |
721 | ||
b65233a9 JR |
722 | /* |
723 | * This function reads some important data from the IOMMU PCI space and | |
724 | * initializes the driver data structure with it. It reads the hardware | |
725 | * capabilities and the first/last device entries | |
726 | */ | |
5d0c8e49 JR |
727 | static void __init init_iommu_from_pci(struct amd_iommu *iommu) |
728 | { | |
5d0c8e49 | 729 | int cap_ptr = iommu->cap_ptr; |
d99ddec3 | 730 | u32 range, misc, low, high; |
5bcd757f | 731 | int i, j; |
5d0c8e49 | 732 | |
3eaf28a1 JR |
733 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, |
734 | &iommu->cap); | |
735 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET, | |
736 | &range); | |
a80dc3e0 JR |
737 | pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET, |
738 | &misc); | |
5d0c8e49 | 739 | |
d591b0a3 JR |
740 | iommu->first_device = calc_devid(MMIO_GET_BUS(range), |
741 | MMIO_GET_FD(range)); | |
742 | iommu->last_device = calc_devid(MMIO_GET_BUS(range), | |
743 | MMIO_GET_LD(range)); | |
a80dc3e0 | 744 | iommu->evt_msi_num = MMIO_MSI_NUM(misc); |
4c894f47 | 745 | |
60f723b4 JR |
746 | if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) |
747 | amd_iommu_iotlb_sup = false; | |
748 | ||
d99ddec3 JR |
749 | /* read extended feature bits */ |
750 | low = readl(iommu->mmio_base + MMIO_EXT_FEATURES); | |
751 | high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4); | |
752 | ||
753 | iommu->features = ((u64)high << 32) | low; | |
754 | ||
62f71abb JR |
755 | if (iommu_feature(iommu, FEATURE_GT)) { |
756 | u32 pasids; | |
757 | u64 shift; | |
758 | ||
759 | shift = iommu->features & FEATURE_PASID_MASK; | |
760 | shift >>= FEATURE_PASID_SHIFT; | |
761 | pasids = (1 << shift); | |
762 | ||
763 | amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids); | |
764 | } | |
765 | ||
400a28a0 JR |
766 | if (iommu_feature(iommu, FEATURE_GT) && |
767 | iommu_feature(iommu, FEATURE_PPR)) { | |
768 | iommu->is_iommu_v2 = true; | |
769 | amd_iommu_v2_present = true; | |
770 | } | |
771 | ||
5bcd757f MG |
772 | if (!is_rd890_iommu(iommu->dev)) |
773 | return; | |
774 | ||
775 | /* | |
776 | * Some rd890 systems may not be fully reconfigured by the BIOS, so | |
777 | * it's necessary for us to store this information so it can be | |
778 | * reprogrammed on resume | |
779 | */ | |
780 | ||
781 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
782 | &iommu->stored_addr_lo); | |
783 | pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
784 | &iommu->stored_addr_hi); | |
785 | ||
786 | /* Low bit locks writes to configuration space */ | |
787 | iommu->stored_addr_lo &= ~1; | |
788 | ||
789 | for (i = 0; i < 6; i++) | |
790 | for (j = 0; j < 0x12; j++) | |
791 | iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); | |
792 | ||
793 | for (i = 0; i < 0x83; i++) | |
794 | iommu->stored_l2[i] = iommu_read_l2(iommu, i); | |
5d0c8e49 JR |
795 | } |
796 | ||
b65233a9 JR |
797 | /* |
798 | * Takes a pointer to an AMD IOMMU entry in the ACPI table and | |
799 | * initializes the hardware and our data structures with it. | |
800 | */ | |
5d0c8e49 JR |
801 | static void __init init_iommu_from_acpi(struct amd_iommu *iommu, |
802 | struct ivhd_header *h) | |
803 | { | |
804 | u8 *p = (u8 *)h; | |
805 | u8 *end = p, flags = 0; | |
0de66d5b JR |
806 | u16 devid = 0, devid_start = 0, devid_to = 0; |
807 | u32 dev_i, ext_flags = 0; | |
58a3bee5 | 808 | bool alias = false; |
5d0c8e49 JR |
809 | struct ivhd_entry *e; |
810 | ||
811 | /* | |
e9bf5197 | 812 | * First save the recommended feature enable bits from ACPI |
5d0c8e49 | 813 | */ |
e9bf5197 | 814 | iommu->acpi_flags = h->flags; |
5d0c8e49 JR |
815 | |
816 | /* | |
817 | * Done. Now parse the device entries | |
818 | */ | |
819 | p += sizeof(struct ivhd_header); | |
820 | end += h->length; | |
821 | ||
42a698f4 | 822 | |
5d0c8e49 JR |
823 | while (p < end) { |
824 | e = (struct ivhd_entry *)p; | |
825 | switch (e->type) { | |
826 | case IVHD_DEV_ALL: | |
42a698f4 JR |
827 | |
828 | DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x" | |
829 | " last device %02x:%02x.%x flags: %02x\n", | |
830 | PCI_BUS(iommu->first_device), | |
831 | PCI_SLOT(iommu->first_device), | |
832 | PCI_FUNC(iommu->first_device), | |
833 | PCI_BUS(iommu->last_device), | |
834 | PCI_SLOT(iommu->last_device), | |
835 | PCI_FUNC(iommu->last_device), | |
836 | e->flags); | |
837 | ||
5d0c8e49 JR |
838 | for (dev_i = iommu->first_device; |
839 | dev_i <= iommu->last_device; ++dev_i) | |
5ff4789d JR |
840 | set_dev_entry_from_acpi(iommu, dev_i, |
841 | e->flags, 0); | |
5d0c8e49 JR |
842 | break; |
843 | case IVHD_DEV_SELECT: | |
42a698f4 JR |
844 | |
845 | DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x " | |
846 | "flags: %02x\n", | |
847 | PCI_BUS(e->devid), | |
848 | PCI_SLOT(e->devid), | |
849 | PCI_FUNC(e->devid), | |
850 | e->flags); | |
851 | ||
5d0c8e49 | 852 | devid = e->devid; |
5ff4789d | 853 | set_dev_entry_from_acpi(iommu, devid, e->flags, 0); |
5d0c8e49 JR |
854 | break; |
855 | case IVHD_DEV_SELECT_RANGE_START: | |
42a698f4 JR |
856 | |
857 | DUMP_printk(" DEV_SELECT_RANGE_START\t " | |
858 | "devid: %02x:%02x.%x flags: %02x\n", | |
859 | PCI_BUS(e->devid), | |
860 | PCI_SLOT(e->devid), | |
861 | PCI_FUNC(e->devid), | |
862 | e->flags); | |
863 | ||
5d0c8e49 JR |
864 | devid_start = e->devid; |
865 | flags = e->flags; | |
866 | ext_flags = 0; | |
58a3bee5 | 867 | alias = false; |
5d0c8e49 JR |
868 | break; |
869 | case IVHD_DEV_ALIAS: | |
42a698f4 JR |
870 | |
871 | DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x " | |
872 | "flags: %02x devid_to: %02x:%02x.%x\n", | |
873 | PCI_BUS(e->devid), | |
874 | PCI_SLOT(e->devid), | |
875 | PCI_FUNC(e->devid), | |
876 | e->flags, | |
877 | PCI_BUS(e->ext >> 8), | |
878 | PCI_SLOT(e->ext >> 8), | |
879 | PCI_FUNC(e->ext >> 8)); | |
880 | ||
5d0c8e49 JR |
881 | devid = e->devid; |
882 | devid_to = e->ext >> 8; | |
7a6a3a08 | 883 | set_dev_entry_from_acpi(iommu, devid , e->flags, 0); |
7455aab1 | 884 | set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); |
5d0c8e49 JR |
885 | amd_iommu_alias_table[devid] = devid_to; |
886 | break; | |
887 | case IVHD_DEV_ALIAS_RANGE: | |
42a698f4 JR |
888 | |
889 | DUMP_printk(" DEV_ALIAS_RANGE\t\t " | |
890 | "devid: %02x:%02x.%x flags: %02x " | |
891 | "devid_to: %02x:%02x.%x\n", | |
892 | PCI_BUS(e->devid), | |
893 | PCI_SLOT(e->devid), | |
894 | PCI_FUNC(e->devid), | |
895 | e->flags, | |
896 | PCI_BUS(e->ext >> 8), | |
897 | PCI_SLOT(e->ext >> 8), | |
898 | PCI_FUNC(e->ext >> 8)); | |
899 | ||
5d0c8e49 JR |
900 | devid_start = e->devid; |
901 | flags = e->flags; | |
902 | devid_to = e->ext >> 8; | |
903 | ext_flags = 0; | |
58a3bee5 | 904 | alias = true; |
5d0c8e49 JR |
905 | break; |
906 | case IVHD_DEV_EXT_SELECT: | |
42a698f4 JR |
907 | |
908 | DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x " | |
909 | "flags: %02x ext: %08x\n", | |
910 | PCI_BUS(e->devid), | |
911 | PCI_SLOT(e->devid), | |
912 | PCI_FUNC(e->devid), | |
913 | e->flags, e->ext); | |
914 | ||
5d0c8e49 | 915 | devid = e->devid; |
5ff4789d JR |
916 | set_dev_entry_from_acpi(iommu, devid, e->flags, |
917 | e->ext); | |
5d0c8e49 JR |
918 | break; |
919 | case IVHD_DEV_EXT_SELECT_RANGE: | |
42a698f4 JR |
920 | |
921 | DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: " | |
922 | "%02x:%02x.%x flags: %02x ext: %08x\n", | |
923 | PCI_BUS(e->devid), | |
924 | PCI_SLOT(e->devid), | |
925 | PCI_FUNC(e->devid), | |
926 | e->flags, e->ext); | |
927 | ||
5d0c8e49 JR |
928 | devid_start = e->devid; |
929 | flags = e->flags; | |
930 | ext_flags = e->ext; | |
58a3bee5 | 931 | alias = false; |
5d0c8e49 JR |
932 | break; |
933 | case IVHD_DEV_RANGE_END: | |
42a698f4 JR |
934 | |
935 | DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n", | |
936 | PCI_BUS(e->devid), | |
937 | PCI_SLOT(e->devid), | |
938 | PCI_FUNC(e->devid)); | |
939 | ||
5d0c8e49 JR |
940 | devid = e->devid; |
941 | for (dev_i = devid_start; dev_i <= devid; ++dev_i) { | |
7a6a3a08 | 942 | if (alias) { |
5d0c8e49 | 943 | amd_iommu_alias_table[dev_i] = devid_to; |
7a6a3a08 JR |
944 | set_dev_entry_from_acpi(iommu, |
945 | devid_to, flags, ext_flags); | |
946 | } | |
947 | set_dev_entry_from_acpi(iommu, dev_i, | |
948 | flags, ext_flags); | |
5d0c8e49 JR |
949 | } |
950 | break; | |
951 | default: | |
952 | break; | |
953 | } | |
954 | ||
b514e555 | 955 | p += ivhd_entry_length(p); |
5d0c8e49 JR |
956 | } |
957 | } | |
958 | ||
b65233a9 | 959 | /* Initializes the device->iommu mapping for the driver */ |
5d0c8e49 JR |
960 | static int __init init_iommu_devices(struct amd_iommu *iommu) |
961 | { | |
0de66d5b | 962 | u32 i; |
5d0c8e49 JR |
963 | |
964 | for (i = iommu->first_device; i <= iommu->last_device; ++i) | |
965 | set_iommu_for_device(iommu, i); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
e47d402d JR |
970 | static void __init free_iommu_one(struct amd_iommu *iommu) |
971 | { | |
972 | free_command_buffer(iommu); | |
335503e5 | 973 | free_event_buffer(iommu); |
1a29ac01 | 974 | free_ppr_log(iommu); |
e47d402d JR |
975 | iommu_unmap_mmio_space(iommu); |
976 | } | |
977 | ||
978 | static void __init free_iommu_all(void) | |
979 | { | |
980 | struct amd_iommu *iommu, *next; | |
981 | ||
3bd22172 | 982 | for_each_iommu_safe(iommu, next) { |
e47d402d JR |
983 | list_del(&iommu->list); |
984 | free_iommu_one(iommu); | |
985 | kfree(iommu); | |
986 | } | |
987 | } | |
988 | ||
b65233a9 JR |
989 | /* |
990 | * This function clues the initialization function for one IOMMU | |
991 | * together and also allocates the command buffer and programs the | |
992 | * hardware. It does NOT enable the IOMMU. This is done afterwards. | |
993 | */ | |
e47d402d JR |
994 | static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) |
995 | { | |
996 | spin_lock_init(&iommu->lock); | |
bb52777e JR |
997 | |
998 | /* Add IOMMU to internal data structures */ | |
e47d402d | 999 | list_add_tail(&iommu->list, &amd_iommu_list); |
bb52777e JR |
1000 | iommu->index = amd_iommus_present++; |
1001 | ||
1002 | if (unlikely(iommu->index >= MAX_IOMMUS)) { | |
1003 | WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n"); | |
1004 | return -ENOSYS; | |
1005 | } | |
1006 | ||
1007 | /* Index is fine - add IOMMU to the array */ | |
1008 | amd_iommus[iommu->index] = iommu; | |
e47d402d JR |
1009 | |
1010 | /* | |
1011 | * Copy data from ACPI table entry to the iommu struct | |
1012 | */ | |
3eaf28a1 JR |
1013 | iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff); |
1014 | if (!iommu->dev) | |
1015 | return 1; | |
1016 | ||
e47d402d | 1017 | iommu->cap_ptr = h->cap_ptr; |
ee893c24 | 1018 | iommu->pci_seg = h->pci_seg; |
e47d402d JR |
1019 | iommu->mmio_phys = h->mmio_phys; |
1020 | iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys); | |
1021 | if (!iommu->mmio_base) | |
1022 | return -ENOMEM; | |
1023 | ||
e47d402d JR |
1024 | iommu->cmd_buf = alloc_command_buffer(iommu); |
1025 | if (!iommu->cmd_buf) | |
1026 | return -ENOMEM; | |
1027 | ||
335503e5 JR |
1028 | iommu->evt_buf = alloc_event_buffer(iommu); |
1029 | if (!iommu->evt_buf) | |
1030 | return -ENOMEM; | |
1031 | ||
a80dc3e0 JR |
1032 | iommu->int_enabled = false; |
1033 | ||
e47d402d JR |
1034 | init_iommu_from_pci(iommu); |
1035 | init_iommu_from_acpi(iommu, h); | |
1036 | init_iommu_devices(iommu); | |
1037 | ||
1a29ac01 JR |
1038 | if (iommu_feature(iommu, FEATURE_PPR)) { |
1039 | iommu->ppr_log = alloc_ppr_log(iommu); | |
1040 | if (!iommu->ppr_log) | |
1041 | return -ENOMEM; | |
1042 | } | |
1043 | ||
318afd41 JR |
1044 | if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) |
1045 | amd_iommu_np_cache = true; | |
1046 | ||
8a66712b | 1047 | return pci_enable_device(iommu->dev); |
e47d402d JR |
1048 | } |
1049 | ||
b65233a9 JR |
1050 | /* |
1051 | * Iterates over all IOMMU entries in the ACPI table, allocates the | |
1052 | * IOMMU structure and initializes it with init_iommu_one() | |
1053 | */ | |
e47d402d JR |
1054 | static int __init init_iommu_all(struct acpi_table_header *table) |
1055 | { | |
1056 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1057 | struct ivhd_header *h; | |
1058 | struct amd_iommu *iommu; | |
1059 | int ret; | |
1060 | ||
e47d402d JR |
1061 | end += table->length; |
1062 | p += IVRS_HEADER_LENGTH; | |
1063 | ||
1064 | while (p < end) { | |
1065 | h = (struct ivhd_header *)p; | |
1066 | switch (*p) { | |
1067 | case ACPI_IVHD_TYPE: | |
9c72041f | 1068 | |
ae908c22 | 1069 | DUMP_printk("device: %02x:%02x.%01x cap: %04x " |
9c72041f JR |
1070 | "seg: %d flags: %01x info %04x\n", |
1071 | PCI_BUS(h->devid), PCI_SLOT(h->devid), | |
1072 | PCI_FUNC(h->devid), h->cap_ptr, | |
1073 | h->pci_seg, h->flags, h->info); | |
1074 | DUMP_printk(" mmio-addr: %016llx\n", | |
1075 | h->mmio_phys); | |
1076 | ||
e47d402d | 1077 | iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); |
3551a708 JR |
1078 | if (iommu == NULL) { |
1079 | amd_iommu_init_err = -ENOMEM; | |
1080 | return 0; | |
1081 | } | |
1082 | ||
e47d402d | 1083 | ret = init_iommu_one(iommu, h); |
3551a708 JR |
1084 | if (ret) { |
1085 | amd_iommu_init_err = ret; | |
1086 | return 0; | |
1087 | } | |
e47d402d JR |
1088 | break; |
1089 | default: | |
1090 | break; | |
1091 | } | |
1092 | p += h->length; | |
1093 | ||
1094 | } | |
1095 | WARN_ON(p != end); | |
1096 | ||
1097 | return 0; | |
1098 | } | |
1099 | ||
a80dc3e0 JR |
1100 | /**************************************************************************** |
1101 | * | |
1102 | * The following functions initialize the MSI interrupts for all IOMMUs | |
1103 | * in the system. Its a bit challenging because there could be multiple | |
1104 | * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per | |
1105 | * pci_dev. | |
1106 | * | |
1107 | ****************************************************************************/ | |
1108 | ||
9f800de3 | 1109 | static int iommu_setup_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1110 | { |
1111 | int r; | |
a80dc3e0 JR |
1112 | |
1113 | if (pci_enable_msi(iommu->dev)) | |
1114 | return 1; | |
1115 | ||
72fe00f0 JR |
1116 | r = request_threaded_irq(iommu->dev->irq, |
1117 | amd_iommu_int_handler, | |
1118 | amd_iommu_int_thread, | |
1119 | 0, "AMD-Vi", | |
1120 | iommu->dev); | |
a80dc3e0 JR |
1121 | |
1122 | if (r) { | |
1123 | pci_disable_msi(iommu->dev); | |
1124 | return 1; | |
1125 | } | |
1126 | ||
fab6afa3 | 1127 | iommu->int_enabled = true; |
58492e12 JR |
1128 | iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); |
1129 | ||
1a29ac01 JR |
1130 | if (iommu->ppr_log != NULL) |
1131 | iommu_feature_enable(iommu, CONTROL_PPFINT_EN); | |
1132 | ||
a80dc3e0 JR |
1133 | return 0; |
1134 | } | |
1135 | ||
05f92db9 | 1136 | static int iommu_init_msi(struct amd_iommu *iommu) |
a80dc3e0 JR |
1137 | { |
1138 | if (iommu->int_enabled) | |
1139 | return 0; | |
1140 | ||
d91cecdd | 1141 | if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI)) |
a80dc3e0 JR |
1142 | return iommu_setup_msi(iommu); |
1143 | ||
1144 | return 1; | |
1145 | } | |
1146 | ||
b65233a9 JR |
1147 | /**************************************************************************** |
1148 | * | |
1149 | * The next functions belong to the third pass of parsing the ACPI | |
1150 | * table. In this last pass the memory mapping requirements are | |
1151 | * gathered (like exclusion and unity mapping reanges). | |
1152 | * | |
1153 | ****************************************************************************/ | |
1154 | ||
be2a022c JR |
1155 | static void __init free_unity_maps(void) |
1156 | { | |
1157 | struct unity_map_entry *entry, *next; | |
1158 | ||
1159 | list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) { | |
1160 | list_del(&entry->list); | |
1161 | kfree(entry); | |
1162 | } | |
1163 | } | |
1164 | ||
b65233a9 | 1165 | /* called when we find an exclusion range definition in ACPI */ |
be2a022c JR |
1166 | static int __init init_exclusion_range(struct ivmd_header *m) |
1167 | { | |
1168 | int i; | |
1169 | ||
1170 | switch (m->type) { | |
1171 | case ACPI_IVMD_TYPE: | |
1172 | set_device_exclusion_range(m->devid, m); | |
1173 | break; | |
1174 | case ACPI_IVMD_TYPE_ALL: | |
3a61ec38 | 1175 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
be2a022c JR |
1176 | set_device_exclusion_range(i, m); |
1177 | break; | |
1178 | case ACPI_IVMD_TYPE_RANGE: | |
1179 | for (i = m->devid; i <= m->aux; ++i) | |
1180 | set_device_exclusion_range(i, m); | |
1181 | break; | |
1182 | default: | |
1183 | break; | |
1184 | } | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
b65233a9 | 1189 | /* called for unity map ACPI definition */ |
be2a022c JR |
1190 | static int __init init_unity_map_range(struct ivmd_header *m) |
1191 | { | |
1192 | struct unity_map_entry *e = 0; | |
02acc43a | 1193 | char *s; |
be2a022c JR |
1194 | |
1195 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
1196 | if (e == NULL) | |
1197 | return -ENOMEM; | |
1198 | ||
1199 | switch (m->type) { | |
1200 | default: | |
0bc252f4 JR |
1201 | kfree(e); |
1202 | return 0; | |
be2a022c | 1203 | case ACPI_IVMD_TYPE: |
02acc43a | 1204 | s = "IVMD_TYPEi\t\t\t"; |
be2a022c JR |
1205 | e->devid_start = e->devid_end = m->devid; |
1206 | break; | |
1207 | case ACPI_IVMD_TYPE_ALL: | |
02acc43a | 1208 | s = "IVMD_TYPE_ALL\t\t"; |
be2a022c JR |
1209 | e->devid_start = 0; |
1210 | e->devid_end = amd_iommu_last_bdf; | |
1211 | break; | |
1212 | case ACPI_IVMD_TYPE_RANGE: | |
02acc43a | 1213 | s = "IVMD_TYPE_RANGE\t\t"; |
be2a022c JR |
1214 | e->devid_start = m->devid; |
1215 | e->devid_end = m->aux; | |
1216 | break; | |
1217 | } | |
1218 | e->address_start = PAGE_ALIGN(m->range_start); | |
1219 | e->address_end = e->address_start + PAGE_ALIGN(m->range_length); | |
1220 | e->prot = m->flags >> 1; | |
1221 | ||
02acc43a JR |
1222 | DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x" |
1223 | " range_start: %016llx range_end: %016llx flags: %x\n", s, | |
1224 | PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start), | |
1225 | PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end), | |
1226 | PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), | |
1227 | e->address_start, e->address_end, m->flags); | |
1228 | ||
be2a022c JR |
1229 | list_add_tail(&e->list, &amd_iommu_unity_map); |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
b65233a9 | 1234 | /* iterates over all memory definitions we find in the ACPI table */ |
be2a022c JR |
1235 | static int __init init_memory_definitions(struct acpi_table_header *table) |
1236 | { | |
1237 | u8 *p = (u8 *)table, *end = (u8 *)table; | |
1238 | struct ivmd_header *m; | |
1239 | ||
be2a022c JR |
1240 | end += table->length; |
1241 | p += IVRS_HEADER_LENGTH; | |
1242 | ||
1243 | while (p < end) { | |
1244 | m = (struct ivmd_header *)p; | |
1245 | if (m->flags & IVMD_FLAG_EXCL_RANGE) | |
1246 | init_exclusion_range(m); | |
1247 | else if (m->flags & IVMD_FLAG_UNITY_MAP) | |
1248 | init_unity_map_range(m); | |
1249 | ||
1250 | p += m->length; | |
1251 | } | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
9f5f5fb3 JR |
1256 | /* |
1257 | * Init the device table to not allow DMA access for devices and | |
1258 | * suppress all page faults | |
1259 | */ | |
1260 | static void init_device_table(void) | |
1261 | { | |
0de66d5b | 1262 | u32 devid; |
9f5f5fb3 JR |
1263 | |
1264 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) { | |
1265 | set_dev_entry_bit(devid, DEV_ENTRY_VALID); | |
1266 | set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION); | |
9f5f5fb3 JR |
1267 | } |
1268 | } | |
1269 | ||
e9bf5197 JR |
1270 | static void iommu_init_flags(struct amd_iommu *iommu) |
1271 | { | |
1272 | iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? | |
1273 | iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : | |
1274 | iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); | |
1275 | ||
1276 | iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? | |
1277 | iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : | |
1278 | iommu_feature_disable(iommu, CONTROL_PASSPW_EN); | |
1279 | ||
1280 | iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? | |
1281 | iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : | |
1282 | iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); | |
1283 | ||
1284 | iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? | |
1285 | iommu_feature_enable(iommu, CONTROL_ISOC_EN) : | |
1286 | iommu_feature_disable(iommu, CONTROL_ISOC_EN); | |
1287 | ||
1288 | /* | |
1289 | * make IOMMU memory accesses cache coherent | |
1290 | */ | |
1291 | iommu_feature_enable(iommu, CONTROL_COHERENT_EN); | |
1292 | } | |
1293 | ||
5bcd757f | 1294 | static void iommu_apply_resume_quirks(struct amd_iommu *iommu) |
4c894f47 | 1295 | { |
5bcd757f MG |
1296 | int i, j; |
1297 | u32 ioc_feature_control; | |
1298 | struct pci_dev *pdev = NULL; | |
1299 | ||
1300 | /* RD890 BIOSes may not have completely reconfigured the iommu */ | |
1301 | if (!is_rd890_iommu(iommu->dev)) | |
1302 | return; | |
1303 | ||
1304 | /* | |
1305 | * First, we need to ensure that the iommu is enabled. This is | |
1306 | * controlled by a register in the northbridge | |
1307 | */ | |
1308 | pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0)); | |
1309 | ||
1310 | if (!pdev) | |
1311 | return; | |
1312 | ||
1313 | /* Select Northbridge indirect register 0x75 and enable writing */ | |
1314 | pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7)); | |
1315 | pci_read_config_dword(pdev, 0x64, &ioc_feature_control); | |
1316 | ||
1317 | /* Enable the iommu */ | |
1318 | if (!(ioc_feature_control & 0x1)) | |
1319 | pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1); | |
1320 | ||
1321 | pci_dev_put(pdev); | |
1322 | ||
1323 | /* Restore the iommu BAR */ | |
1324 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1325 | iommu->stored_addr_lo); | |
1326 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, | |
1327 | iommu->stored_addr_hi); | |
1328 | ||
1329 | /* Restore the l1 indirect regs for each of the 6 l1s */ | |
1330 | for (i = 0; i < 6; i++) | |
1331 | for (j = 0; j < 0x12; j++) | |
1332 | iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); | |
1333 | ||
1334 | /* Restore the l2 indirect regs */ | |
1335 | for (i = 0; i < 0x83; i++) | |
1336 | iommu_write_l2(iommu, i, iommu->stored_l2[i]); | |
1337 | ||
1338 | /* Lock PCI setup registers */ | |
1339 | pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, | |
1340 | iommu->stored_addr_lo | 1); | |
4c894f47 JR |
1341 | } |
1342 | ||
b65233a9 JR |
1343 | /* |
1344 | * This function finally enables all IOMMUs found in the system after | |
1345 | * they have been initialized | |
1346 | */ | |
05f92db9 | 1347 | static void enable_iommus(void) |
8736197b JR |
1348 | { |
1349 | struct amd_iommu *iommu; | |
1350 | ||
3bd22172 | 1351 | for_each_iommu(iommu) { |
a8c485bb | 1352 | iommu_disable(iommu); |
e9bf5197 | 1353 | iommu_init_flags(iommu); |
58492e12 JR |
1354 | iommu_set_device_table(iommu); |
1355 | iommu_enable_command_buffer(iommu); | |
1356 | iommu_enable_event_buffer(iommu); | |
1a29ac01 | 1357 | iommu_enable_ppr_log(iommu); |
cbc33a90 | 1358 | iommu_enable_gt(iommu); |
8736197b | 1359 | iommu_set_exclusion_range(iommu); |
a80dc3e0 | 1360 | iommu_init_msi(iommu); |
8736197b | 1361 | iommu_enable(iommu); |
7d0c5cc5 | 1362 | iommu_flush_all_caches(iommu); |
8736197b JR |
1363 | } |
1364 | } | |
1365 | ||
92ac4320 JR |
1366 | static void disable_iommus(void) |
1367 | { | |
1368 | struct amd_iommu *iommu; | |
1369 | ||
1370 | for_each_iommu(iommu) | |
1371 | iommu_disable(iommu); | |
1372 | } | |
1373 | ||
7441e9cb JR |
1374 | /* |
1375 | * Suspend/Resume support | |
1376 | * disable suspend until real resume implemented | |
1377 | */ | |
1378 | ||
f3c6ea1b | 1379 | static void amd_iommu_resume(void) |
7441e9cb | 1380 | { |
5bcd757f MG |
1381 | struct amd_iommu *iommu; |
1382 | ||
1383 | for_each_iommu(iommu) | |
1384 | iommu_apply_resume_quirks(iommu); | |
1385 | ||
736501ee JR |
1386 | /* re-load the hardware */ |
1387 | enable_iommus(); | |
1388 | ||
1389 | /* | |
1390 | * we have to flush after the IOMMUs are enabled because a | |
1391 | * disabled IOMMU will never execute the commands we send | |
1392 | */ | |
7d0c5cc5 JR |
1393 | for_each_iommu(iommu) |
1394 | iommu_flush_all_caches(iommu); | |
7441e9cb JR |
1395 | } |
1396 | ||
f3c6ea1b | 1397 | static int amd_iommu_suspend(void) |
7441e9cb | 1398 | { |
736501ee JR |
1399 | /* disable IOMMUs to go out of the way for BIOS */ |
1400 | disable_iommus(); | |
1401 | ||
1402 | return 0; | |
7441e9cb JR |
1403 | } |
1404 | ||
f3c6ea1b | 1405 | static struct syscore_ops amd_iommu_syscore_ops = { |
7441e9cb JR |
1406 | .suspend = amd_iommu_suspend, |
1407 | .resume = amd_iommu_resume, | |
1408 | }; | |
1409 | ||
b65233a9 JR |
1410 | /* |
1411 | * This is the core init function for AMD IOMMU hardware in the system. | |
1412 | * This function is called from the generic x86 DMA layer initialization | |
1413 | * code. | |
1414 | * | |
1415 | * This function basically parses the ACPI table for AMD IOMMU (IVRS) | |
1416 | * three times: | |
1417 | * | |
1418 | * 1 pass) Find the highest PCI device id the driver has to handle. | |
1419 | * Upon this information the size of the data structures is | |
1420 | * determined that needs to be allocated. | |
1421 | * | |
1422 | * 2 pass) Initialize the data structures just allocated with the | |
1423 | * information in the ACPI table about available AMD IOMMUs | |
1424 | * in the system. It also maps the PCI devices in the | |
1425 | * system to specific IOMMUs | |
1426 | * | |
1427 | * 3 pass) After the basic data structures are allocated and | |
1428 | * initialized we update them with information about memory | |
1429 | * remapping requirements parsed out of the ACPI table in | |
1430 | * this last pass. | |
1431 | * | |
1432 | * After that the hardware is initialized and ready to go. In the last | |
1433 | * step we do some Linux specific things like registering the driver in | |
1434 | * the dma_ops interface and initializing the suspend/resume support | |
1435 | * functions. Finally it prints some information about AMD IOMMUs and | |
1436 | * the driver state and enables the hardware. | |
1437 | */ | |
ea1b0d39 | 1438 | static int __init amd_iommu_init(void) |
fe74c9cf JR |
1439 | { |
1440 | int i, ret = 0; | |
1441 | ||
fe74c9cf JR |
1442 | /* |
1443 | * First parse ACPI tables to find the largest Bus/Dev/Func | |
1444 | * we need to handle. Upon this information the shared data | |
1445 | * structures for the IOMMUs in the system will be allocated | |
1446 | */ | |
1447 | if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0) | |
1448 | return -ENODEV; | |
1449 | ||
3551a708 JR |
1450 | ret = amd_iommu_init_err; |
1451 | if (ret) | |
1452 | goto out; | |
1453 | ||
c571484e JR |
1454 | dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE); |
1455 | alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE); | |
1456 | rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE); | |
fe74c9cf JR |
1457 | |
1458 | ret = -ENOMEM; | |
1459 | ||
1460 | /* Device table - directly used by all IOMMUs */ | |
5dc8bff0 | 1461 | amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, |
fe74c9cf JR |
1462 | get_order(dev_table_size)); |
1463 | if (amd_iommu_dev_table == NULL) | |
1464 | goto out; | |
1465 | ||
1466 | /* | |
1467 | * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the | |
1468 | * IOMMU see for that device | |
1469 | */ | |
1470 | amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL, | |
1471 | get_order(alias_table_size)); | |
1472 | if (amd_iommu_alias_table == NULL) | |
1473 | goto free; | |
1474 | ||
1475 | /* IOMMU rlookup table - find the IOMMU for a specific device */ | |
83fd5cc6 JR |
1476 | amd_iommu_rlookup_table = (void *)__get_free_pages( |
1477 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1478 | get_order(rlookup_table_size)); |
1479 | if (amd_iommu_rlookup_table == NULL) | |
1480 | goto free; | |
1481 | ||
5dc8bff0 JR |
1482 | amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages( |
1483 | GFP_KERNEL | __GFP_ZERO, | |
fe74c9cf JR |
1484 | get_order(MAX_DOMAIN_ID/8)); |
1485 | if (amd_iommu_pd_alloc_bitmap == NULL) | |
1486 | goto free; | |
1487 | ||
9f5f5fb3 JR |
1488 | /* init the device table */ |
1489 | init_device_table(); | |
1490 | ||
fe74c9cf | 1491 | /* |
5dc8bff0 | 1492 | * let all alias entries point to itself |
fe74c9cf | 1493 | */ |
3a61ec38 | 1494 | for (i = 0; i <= amd_iommu_last_bdf; ++i) |
fe74c9cf JR |
1495 | amd_iommu_alias_table[i] = i; |
1496 | ||
fe74c9cf JR |
1497 | /* |
1498 | * never allocate domain 0 because its used as the non-allocated and | |
1499 | * error value placeholder | |
1500 | */ | |
1501 | amd_iommu_pd_alloc_bitmap[0] = 1; | |
1502 | ||
aeb26f55 JR |
1503 | spin_lock_init(&amd_iommu_pd_lock); |
1504 | ||
fe74c9cf JR |
1505 | /* |
1506 | * now the data structures are allocated and basically initialized | |
1507 | * start the real acpi table scan | |
1508 | */ | |
1509 | ret = -ENODEV; | |
1510 | if (acpi_table_parse("IVRS", init_iommu_all) != 0) | |
1511 | goto free; | |
1512 | ||
3551a708 JR |
1513 | if (amd_iommu_init_err) { |
1514 | ret = amd_iommu_init_err; | |
0f764806 | 1515 | goto free; |
3551a708 | 1516 | } |
0f764806 | 1517 | |
fe74c9cf JR |
1518 | if (acpi_table_parse("IVRS", init_memory_definitions) != 0) |
1519 | goto free; | |
1520 | ||
3551a708 JR |
1521 | if (amd_iommu_init_err) { |
1522 | ret = amd_iommu_init_err; | |
1523 | goto free; | |
1524 | } | |
1525 | ||
b7cc9554 JR |
1526 | ret = amd_iommu_init_devices(); |
1527 | if (ret) | |
1528 | goto free; | |
1529 | ||
75f66533 CW |
1530 | enable_iommus(); |
1531 | ||
4751a951 JR |
1532 | if (iommu_pass_through) |
1533 | ret = amd_iommu_init_passthrough(); | |
1534 | else | |
1535 | ret = amd_iommu_init_dma_ops(); | |
f5325094 | 1536 | |
7441e9cb | 1537 | if (ret) |
e82752d8 | 1538 | goto free_disable; |
7441e9cb | 1539 | |
f5325094 JR |
1540 | amd_iommu_init_api(); |
1541 | ||
8638c491 JR |
1542 | amd_iommu_init_notifier(); |
1543 | ||
f3c6ea1b RW |
1544 | register_syscore_ops(&amd_iommu_syscore_ops); |
1545 | ||
4751a951 JR |
1546 | if (iommu_pass_through) |
1547 | goto out; | |
1548 | ||
afa9fdc2 | 1549 | if (amd_iommu_unmap_flush) |
4c6f40d4 | 1550 | printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n"); |
1c655773 | 1551 | else |
4c6f40d4 | 1552 | printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n"); |
1c655773 | 1553 | |
338bac52 | 1554 | x86_platform.iommu_shutdown = disable_iommus; |
fe74c9cf JR |
1555 | out: |
1556 | return ret; | |
1557 | ||
e82752d8 | 1558 | free_disable: |
75f66533 | 1559 | disable_iommus(); |
b7cc9554 | 1560 | |
e82752d8 | 1561 | free: |
b7cc9554 JR |
1562 | amd_iommu_uninit_devices(); |
1563 | ||
d58befd3 JR |
1564 | free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, |
1565 | get_order(MAX_DOMAIN_ID/8)); | |
fe74c9cf | 1566 | |
9a836de0 JR |
1567 | free_pages((unsigned long)amd_iommu_rlookup_table, |
1568 | get_order(rlookup_table_size)); | |
fe74c9cf | 1569 | |
9a836de0 JR |
1570 | free_pages((unsigned long)amd_iommu_alias_table, |
1571 | get_order(alias_table_size)); | |
fe74c9cf | 1572 | |
9a836de0 JR |
1573 | free_pages((unsigned long)amd_iommu_dev_table, |
1574 | get_order(dev_table_size)); | |
fe74c9cf JR |
1575 | |
1576 | free_iommu_all(); | |
1577 | ||
1578 | free_unity_maps(); | |
1579 | ||
d7f07769 JR |
1580 | #ifdef CONFIG_GART_IOMMU |
1581 | /* | |
1582 | * We failed to initialize the AMD IOMMU - try fallback to GART | |
1583 | * if possible. | |
1584 | */ | |
1585 | gart_iommu_init(); | |
1586 | ||
1587 | #endif | |
1588 | ||
fe74c9cf JR |
1589 | goto out; |
1590 | } | |
1591 | ||
b65233a9 JR |
1592 | /**************************************************************************** |
1593 | * | |
1594 | * Early detect code. This code runs at IOMMU detection time in the DMA | |
1595 | * layer. It just looks if there is an IVRS ACPI table to detect AMD | |
1596 | * IOMMUs | |
1597 | * | |
1598 | ****************************************************************************/ | |
ae7877de JR |
1599 | static int __init early_amd_iommu_detect(struct acpi_table_header *table) |
1600 | { | |
1601 | return 0; | |
1602 | } | |
1603 | ||
480125ba | 1604 | int __init amd_iommu_detect(void) |
ae7877de | 1605 | { |
75f1cdf1 | 1606 | if (no_iommu || (iommu_detected && !gart_iommu_aperture)) |
480125ba | 1607 | return -ENODEV; |
ae7877de | 1608 | |
a5235725 | 1609 | if (amd_iommu_disabled) |
480125ba | 1610 | return -ENODEV; |
a5235725 | 1611 | |
ae7877de JR |
1612 | if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) { |
1613 | iommu_detected = 1; | |
c1cbebee | 1614 | amd_iommu_detected = 1; |
ea1b0d39 | 1615 | x86_init.iommu.iommu_init = amd_iommu_init; |
11bd04f6 | 1616 | |
5d990b62 CW |
1617 | /* Make sure ACS will be enabled */ |
1618 | pci_request_acs(); | |
480125ba | 1619 | return 1; |
ae7877de | 1620 | } |
480125ba | 1621 | return -ENODEV; |
ae7877de JR |
1622 | } |
1623 | ||
b65233a9 JR |
1624 | /**************************************************************************** |
1625 | * | |
1626 | * Parsing functions for the AMD IOMMU specific kernel command line | |
1627 | * options. | |
1628 | * | |
1629 | ****************************************************************************/ | |
1630 | ||
fefda117 JR |
1631 | static int __init parse_amd_iommu_dump(char *str) |
1632 | { | |
1633 | amd_iommu_dump = true; | |
1634 | ||
1635 | return 1; | |
1636 | } | |
1637 | ||
918ad6c5 JR |
1638 | static int __init parse_amd_iommu_options(char *str) |
1639 | { | |
1640 | for (; *str; ++str) { | |
695b5676 | 1641 | if (strncmp(str, "fullflush", 9) == 0) |
afa9fdc2 | 1642 | amd_iommu_unmap_flush = true; |
a5235725 JR |
1643 | if (strncmp(str, "off", 3) == 0) |
1644 | amd_iommu_disabled = true; | |
918ad6c5 JR |
1645 | } |
1646 | ||
1647 | return 1; | |
1648 | } | |
1649 | ||
fefda117 | 1650 | __setup("amd_iommu_dump", parse_amd_iommu_dump); |
918ad6c5 | 1651 | __setup("amd_iommu=", parse_amd_iommu_options); |
22e6daf4 KRW |
1652 | |
1653 | IOMMU_INIT_FINISH(amd_iommu_detect, | |
1654 | gart_iommu_hole_init, | |
1655 | 0, | |
1656 | 0); | |
400a28a0 JR |
1657 | |
1658 | bool amd_iommu_v2_supported(void) | |
1659 | { | |
1660 | return amd_iommu_v2_present; | |
1661 | } | |
1662 | EXPORT_SYMBOL(amd_iommu_v2_supported); |