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iommu/amd: Rename free_on_init_error()
[mirror_ubuntu-hirsute-kernel.git] / drivers / iommu / amd_iommu_init.c
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f6e2e6b6 1/*
5d0d7156 2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
63ce3ae8 3 * Author: Joerg Roedel <jroedel@suse.de>
f6e2e6b6
JR		 4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/pci.h>
21#include <linux/acpi.h>
f6e2e6b6 22#include <linux/list.h>
5c87f62d 23#include <linux/bitmap.h>
5a0e3ad6 24#include <linux/slab.h>
f3c6ea1b 25#include <linux/syscore_ops.h>
a80dc3e0
JR		 26#include <linux/interrupt.h>
27#include <linux/msi.h>
403f81d8 28#include <linux/amd-iommu.h>
400a28a0 29#include <linux/export.h>
066f2e98 30#include <linux/iommu.h>
ebcfa284 31#include <linux/kmemleak.h>
54bd6357 32#include <linux/crash_dump.h>
f6e2e6b6 33#include <asm/pci-direct.h>
46a7fa27 34#include <asm/iommu.h>
1d9b16d1 35#include <asm/gart.h>
ea1b0d39 36#include <asm/x86_init.h>
22e6daf4 37#include <asm/iommu_table.h>
eb1eb7ae 38#include <asm/io_apic.h>
6b474b82 39#include <asm/irq_remapping.h>
403f81d8
JR		 40
41#include "amd_iommu_proto.h"
42#include "amd_iommu_types.h"
05152a04 43#include "irq_remapping.h"
403f81d8 44
f6e2e6b6
JR		 45/*
46 * definitions for the ACPI scanning code
47 */
f6e2e6b6 48#define IVRS_HEADER_LENGTH 48
f6e2e6b6 49
8c7142f5 50#define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
f6e2e6b6
JR		 51#define ACPI_IVMD_TYPE_ALL 0x20
52#define ACPI_IVMD_TYPE 0x21
53#define ACPI_IVMD_TYPE_RANGE 0x22
54
55#define IVHD_DEV_ALL 0x01
56#define IVHD_DEV_SELECT 0x02
57#define IVHD_DEV_SELECT_RANGE_START 0x03
58#define IVHD_DEV_RANGE_END 0x04
59#define IVHD_DEV_ALIAS 0x42
60#define IVHD_DEV_ALIAS_RANGE 0x43
61#define IVHD_DEV_EXT_SELECT 0x46
62#define IVHD_DEV_EXT_SELECT_RANGE 0x47
6efed63b 63#define IVHD_DEV_SPECIAL 0x48
8c7142f5 64#define IVHD_DEV_ACPI_HID 0xf0
6efed63b 65
2a0cb4e2
WZ		 66#define UID_NOT_PRESENT 0
67#define UID_IS_INTEGER 1
68#define UID_IS_CHARACTER 2
69
6efed63b
JR		 70#define IVHD_SPECIAL_IOAPIC 1
71#define IVHD_SPECIAL_HPET 2
f6e2e6b6 72
6da7342f
JR		 73#define IVHD_FLAG_HT_TUN_EN_MASK 0x01
74#define IVHD_FLAG_PASSPW_EN_MASK 0x02
75#define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
76#define IVHD_FLAG_ISOC_EN_MASK 0x08
f6e2e6b6
JR		 77
78#define IVMD_FLAG_EXCL_RANGE 0x08
79#define IVMD_FLAG_UNITY_MAP 0x01
80
81#define ACPI_DEVFLAG_INITPASS 0x01
82#define ACPI_DEVFLAG_EXTINT 0x02
83#define ACPI_DEVFLAG_NMI 0x04
84#define ACPI_DEVFLAG_SYSMGT1 0x10
85#define ACPI_DEVFLAG_SYSMGT2 0x20
86#define ACPI_DEVFLAG_LINT0 0x40
87#define ACPI_DEVFLAG_LINT1 0x80
88#define ACPI_DEVFLAG_ATSDIS 0x10000000
89
8bda0cfb 90#define LOOP_TIMEOUT 100000
b65233a9
JR		 91/*
92 * ACPI table definitions
93 *
94 * These data structures are laid over the table to parse the important values
95 * out of it.
96 */
97
b0119e87
JR		 98extern const struct iommu_ops amd_iommu_ops;
99
b65233a9
JR		 100/*
101 * structure describing one IOMMU in the ACPI table. Typically followed by one
102 * or more ivhd_entrys.
103 */
f6e2e6b6
JR		 104struct ivhd_header {
105 u8 type;
106 u8 flags;
107 u16 length;
108 u16 devid;
109 u16 cap_ptr;
110 u64 mmio_phys;
111 u16 pci_seg;
112 u16 info;
7d7d38af
SS		 113 u32 efr_attr;
114
115 /* Following only valid on IVHD type 11h and 40h */
116 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
117 u64 res;
f6e2e6b6
JR		 118} __attribute__((packed));
119
b65233a9
JR		 120/*
121 * A device entry describing which devices a specific IOMMU translates and
122 * which requestor ids they use.
123 */
f6e2e6b6
JR		 124struct ivhd_entry {
125 u8 type;
126 u16 devid;
127 u8 flags;
128 u32 ext;
2a0cb4e2
WZ		 129 u32 hidh;
130 u64 cid;
131 u8 uidf;
132 u8 uidl;
133 u8 uid;
f6e2e6b6
JR		 134} __attribute__((packed));
135
b65233a9
JR		 136/*
137 * An AMD IOMMU memory definition structure. It defines things like exclusion
138 * ranges for devices and regions that should be unity mapped.
139 */
f6e2e6b6
JR		 140struct ivmd_header {
141 u8 type;
142 u8 flags;
143 u16 length;
144 u16 devid;
145 u16 aux;
146 u64 resv;
147 u64 range_start;
148 u64 range_length;
149} __attribute__((packed));
150
fefda117 151bool amd_iommu_dump;
05152a04 152bool amd_iommu_irq_remap __read_mostly;
fefda117 153
d98de49a 154int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
3928aa3f 155
02f3b3f5 156static bool amd_iommu_detected;
a5235725 157static bool __initdata amd_iommu_disabled;
8c7142f5 158static int amd_iommu_target_ivhd_type;
c1cbebee 159
b65233a9
JR		 160u16 amd_iommu_last_bdf; /* largest PCI device id we have
161 to handle */
2e22847f 162LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
b65233a9 163 we find in ACPI */
621a5f7a 164bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
928abd25 165
2e22847f 166LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
b65233a9 167 system */
928abd25 168
bb52777e
JR		 169/* Array to assign indices to IOMMUs*/
170struct amd_iommu *amd_iommus[MAX_IOMMUS];
6b9376e3
SS		 171
172/* Number of IOMMUs present in the system */
173static int amd_iommus_present;
bb52777e 174
318afd41
JR		 175/* IOMMUs have a non-present cache? */
176bool amd_iommu_np_cache __read_mostly;
60f723b4 177bool amd_iommu_iotlb_sup __read_mostly = true;
318afd41 178
a919a018 179u32 amd_iommu_max_pasid __read_mostly = ~0;
62f71abb 180
400a28a0 181bool amd_iommu_v2_present __read_mostly;
4160cd9e 182static bool amd_iommu_pc_present __read_mostly;
400a28a0 183
5abcdba4
JR		 184bool amd_iommu_force_isolation __read_mostly;
185
aeb26f55
JR		 186/*
187 * List of protection domains - used during resume
188 */
189LIST_HEAD(amd_iommu_pd_list);
190spinlock_t amd_iommu_pd_lock;
191
b65233a9
JR		 192/*
193 * Pointer to the device table which is shared by all AMD IOMMUs
194 * it is indexed by the PCI device id or the HT unit id and contains
195 * information about the domain the device belongs to as well as the
196 * page table root pointer.
197 */
928abd25 198struct dev_table_entry *amd_iommu_dev_table;
b65233a9
JR		 199
200/*
201 * The alias table is a driver specific data structure which contains the
202 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
203 * More than one device can share the same requestor id.
204 */
928abd25 205u16 *amd_iommu_alias_table;
b65233a9
JR		 206
207/*
208 * The rlookup table is used to find the IOMMU which is responsible
209 * for a specific device. It is also indexed by the PCI device id.
210 */
928abd25 211struct amd_iommu **amd_iommu_rlookup_table;
b65233a9 212
b65233a9 213/*
0ea2c422
JR		 214 * This table is used to find the irq remapping table for a given device id
215 * quickly.
216 */
217struct irq_remap_table **irq_lookup_table;
218
b65233a9 219/*
df805abb 220 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
b65233a9
JR		 221 * to know which ones are already in use.
222 */
928abd25
JR		 223unsigned long *amd_iommu_pd_alloc_bitmap;
224
b65233a9
JR		 225static u32 dev_table_size; /* size of the device table */
226static u32 alias_table_size; /* size of the alias table */
227static u32 rlookup_table_size; /* size if the rlookup table */
3e8064ba 228
2c0ae172
JR		 229enum iommu_init_state {
230 IOMMU_START_STATE,
231 IOMMU_IVRS_DETECTED,
232 IOMMU_ACPI_FINISHED,
233 IOMMU_ENABLED,
234 IOMMU_PCI_INIT,
235 IOMMU_INTERRUPTS_EN,
236 IOMMU_DMA_OPS,
237 IOMMU_INITIALIZED,
238 IOMMU_NOT_FOUND,
239 IOMMU_INIT_ERROR,
240};
241
235dacbc
JR		 242/* Early ioapic and hpet maps from kernel command line */
243#define EARLY_MAP_SIZE 4
244static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
245static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
2a0cb4e2
WZ		 246static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
247
235dacbc
JR		 248static int __initdata early_ioapic_map_size;
249static int __initdata early_hpet_map_size;
2a0cb4e2
WZ		 250static int __initdata early_acpihid_map_size;
251
dfbb6d47 252static bool __initdata cmdline_maps;
235dacbc 253
2c0ae172
JR		 254static enum iommu_init_state init_state = IOMMU_START_STATE;
255
ae295142 256static int amd_iommu_enable_interrupts(void);
2c0ae172 257static int __init iommu_go_to_state(enum iommu_init_state state);
aafd8ba0 258static void init_device_table_dma(void);
3d9761e7 259
208ec8c9
JR		 260static inline void update_last_devid(u16 devid)
261{
262 if (devid > amd_iommu_last_bdf)
263 amd_iommu_last_bdf = devid;
264}
265
c571484e
JR		 266static inline unsigned long tbl_size(int entry_size)
267{
268 unsigned shift = PAGE_SHIFT +
421f909c 269 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
c571484e
JR		 270
271 return 1UL << shift;
272}
273
6b9376e3
SS		 274int amd_iommu_get_num_iommus(void)
275{
276 return amd_iommus_present;
277}
278
5bcd757f
MG		 279/* Access to l1 and l2 indexed register spaces */
280
281static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
282{
283 u32 val;
284
285 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
286 pci_read_config_dword(iommu->dev, 0xfc, &val);
287 return val;
288}
289
290static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
291{
292 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
293 pci_write_config_dword(iommu->dev, 0xfc, val);
294 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
295}
296
297static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
298{
299 u32 val;
300
301 pci_write_config_dword(iommu->dev, 0xf0, address);
302 pci_read_config_dword(iommu->dev, 0xf4, &val);
303 return val;
304}
305
306static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
307{
308 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
309 pci_write_config_dword(iommu->dev, 0xf4, val);
310}
311
b65233a9
JR		 312/****************************************************************************
313 *
314 * AMD IOMMU MMIO register space handling functions
315 *
316 * These functions are used to program the IOMMU device registers in
317 * MMIO space required for that driver.
318 *
319 ****************************************************************************/
3e8064ba 320
b65233a9
JR		 321/*
322 * This function set the exclusion range in the IOMMU. DMA accesses to the
323 * exclusion range are passed through untranslated
324 */
05f92db9 325static void iommu_set_exclusion_range(struct amd_iommu *iommu)
b2026aa2
JR		 326{
327 u64 start = iommu->exclusion_start & PAGE_MASK;
328 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
329 u64 entry;
330
331 if (!iommu->exclusion_start)
332 return;
333
334 entry = start | MMIO_EXCL_ENABLE_MASK;
335 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
336 &entry, sizeof(entry));
337
338 entry = limit;
339 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
340 &entry, sizeof(entry));
341}
342
b65233a9 343/* Programs the physical address of the device table into the IOMMU hardware */
6b7f000e 344static void iommu_set_device_table(struct amd_iommu *iommu)
b2026aa2 345{
f609891f 346 u64 entry;
b2026aa2
JR		 347
348 BUG_ON(iommu->mmio_base == NULL);
349
350 entry = virt_to_phys(amd_iommu_dev_table);
351 entry |= (dev_table_size >> 12) - 1;
352 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
353 &entry, sizeof(entry));
354}
355
b65233a9 356/* Generic functions to enable/disable certain features of the IOMMU. */
05f92db9 357static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 358{
359 u32 ctrl;
360
361 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
362 ctrl |= (1 << bit);
363 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
364}
365
ca020711 366static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
b2026aa2
JR		 367{
368 u32 ctrl;
369
199d0d50 370 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
b2026aa2
JR		 371 ctrl &= ~(1 << bit);
372 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
373}
374
1456e9d2
JR		 375static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
376{
377 u32 ctrl;
378
379 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
380 ctrl &= ~CTRL_INV_TO_MASK;
381 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
382 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
383}
384
b65233a9 385/* Function to enable the hardware */
05f92db9 386static void iommu_enable(struct amd_iommu *iommu)
b2026aa2 387{
b2026aa2 388 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
b2026aa2
JR		 389}
390
92ac4320 391static void iommu_disable(struct amd_iommu *iommu)
126c52be 392{
a8c485bb
CW		 393 /* Disable command buffer */
394 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
395
396 /* Disable event logging and event interrupts */
397 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
398 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
399
8bda0cfb
SS		 400 /* Disable IOMMU GA_LOG */
401 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
402 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
403
a8c485bb 404 /* Disable IOMMU hardware itself */
92ac4320 405 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
126c52be
JR		 406}
407
b65233a9
JR		 408/*
409 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
410 * the system has one.
411 */
30861ddc 412static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
6c56747b 413{
30861ddc
SK		 414 if (!request_mem_region(address, end, "amd_iommu")) {
415 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
416 address, end);
e82752d8 417 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
6c56747b 418 return NULL;
e82752d8 419 }
6c56747b 420
30861ddc 421 return (u8 __iomem *)ioremap_nocache(address, end);
6c56747b
JR		 422}
423
424static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
425{
426 if (iommu->mmio_base)
427 iounmap(iommu->mmio_base);
30861ddc 428 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
6c56747b
JR		 429}
430
ac7ccf67
SS		 431static inline u32 get_ivhd_header_size(struct ivhd_header *h)
432{
433 u32 size = 0;
434
435 switch (h->type) {
436 case 0x10:
437 size = 24;
438 break;
439 case 0x11:
440 case 0x40:
441 size = 40;
442 break;
443 }
444 return size;
445}
446
b65233a9
JR		 447/****************************************************************************
448 *
449 * The functions below belong to the first pass of AMD IOMMU ACPI table
450 * parsing. In this pass we try to find out the highest device id this
451 * code has to handle. Upon this information the size of the shared data
452 * structures is determined later.
453 *
454 ****************************************************************************/
455
b514e555
JR		 456/*
457 * This function calculates the length of a given IVHD entry
458 */
459static inline int ivhd_entry_length(u8 *ivhd)
460{
8c7142f5
SS		 461 u32 type = ((struct ivhd_entry *)ivhd)->type;
462
463 if (type < 0x80) {
464 return 0x04 << (*ivhd >> 6);
465 } else if (type == IVHD_DEV_ACPI_HID) {
466 /* For ACPI_HID, offset 21 is uid len */
467 return *((u8 *)ivhd + 21) + 22;
468 }
469 return 0;
b514e555
JR		 470}
471
b65233a9
JR		 472/*
473 * After reading the highest device id from the IOMMU PCI capability header
474 * this function looks if there is a higher device id defined in the ACPI table
475 */
3e8064ba
JR		 476static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
477{
478 u8 *p = (void *)h, *end = (void *)h;
479 struct ivhd_entry *dev;
480
ac7ccf67
SS		 481 u32 ivhd_size = get_ivhd_header_size(h);
482
483 if (!ivhd_size) {
484 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
485 return -EINVAL;
486 }
487
488 p += ivhd_size;
3e8064ba
JR		 489 end += h->length;
490
3e8064ba
JR		 491 while (p < end) {
492 dev = (struct ivhd_entry *)p;
493 switch (dev->type) {
d1259416
JR		 494 case IVHD_DEV_ALL:
495 /* Use maximum BDF value for DEV_ALL */
496 update_last_devid(0xffff);
497 break;
3e8064ba
JR		 498 case IVHD_DEV_SELECT:
499 case IVHD_DEV_RANGE_END:
500 case IVHD_DEV_ALIAS:
501 case IVHD_DEV_EXT_SELECT:
b65233a9 502 /* all the above subfield types refer to device ids */
208ec8c9 503 update_last_devid(dev->devid);
3e8064ba
JR		 504 break;
505 default:
506 break;
507 }
b514e555 508 p += ivhd_entry_length(p);
3e8064ba
JR		 509 }
510
511 WARN_ON(p != end);
512
513 return 0;
514}
515
8c7142f5
SS		 516static int __init check_ivrs_checksum(struct acpi_table_header *table)
517{
518 int i;
519 u8 checksum = 0, *p = (u8 *)table;
520
521 for (i = 0; i < table->length; ++i)
522 checksum += p[i];
523 if (checksum != 0) {
524 /* ACPI table corrupt */
525 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
526 return -ENODEV;
527 }
528
529 return 0;
530}
531
b65233a9
JR		 532/*
533 * Iterate over all IVHD entries in the ACPI table and find the highest device
534 * id which we need to handle. This is the first of three functions which parse
535 * the ACPI table. So we check the checksum here.
536 */
3e8064ba
JR		 537static int __init find_last_devid_acpi(struct acpi_table_header *table)
538{
8c7142f5 539 u8 *p = (u8 *)table, *end = (u8 *)table;
3e8064ba
JR		 540 struct ivhd_header *h;
541
3e8064ba
JR		 542 p += IVRS_HEADER_LENGTH;
543
544 end += table->length;
545 while (p < end) {
546 h = (struct ivhd_header *)p;
8c7142f5
SS		 547 if (h->type == amd_iommu_target_ivhd_type) {
548 int ret = find_last_devid_from_ivhd(h);
549
550 if (ret)
551 return ret;
3e8064ba
JR		 552 }
553 p += h->length;
554 }
555 WARN_ON(p != end);
556
557 return 0;
558}
559
b65233a9
JR		 560/****************************************************************************
561 *
df805abb 562 * The following functions belong to the code path which parses the ACPI table
b65233a9
JR		 563 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
564 * data structures, initialize the device/alias/rlookup table and also
565 * basically initialize the hardware.
566 *
567 ****************************************************************************/
568
569/*
570 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
571 * write commands to that buffer later and the IOMMU will execute them
572 * asynchronously
573 */
f2c2db53 574static int __init alloc_command_buffer(struct amd_iommu *iommu)
b36ca91e 575{
f2c2db53
JR		 576 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
577 get_order(CMD_BUFFER_SIZE));
b36ca91e 578
f2c2db53 579 return iommu->cmd_buf ? 0 : -ENOMEM;
58492e12
JR		 580}
581
93f1cc67
JR		 582/*
583 * This function resets the command buffer if the IOMMU stopped fetching
584 * commands from it.
585 */
586void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
587{
588 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
589
590 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
591 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
d334a563
TL		 592 iommu->cmd_buf_head = 0;
593 iommu->cmd_buf_tail = 0;
93f1cc67
JR		 594
595 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
596}
597
58492e12
JR		 598/*
599 * This function writes the command buffer address to the hardware and
600 * enables it.
601 */
602static void iommu_enable_command_buffer(struct amd_iommu *iommu)
603{
604 u64 entry;
605
606 BUG_ON(iommu->cmd_buf == NULL);
607
608 entry = (u64)virt_to_phys(iommu->cmd_buf);
b36ca91e 609 entry |= MMIO_CMD_SIZE_512;
58492e12 610
b36ca91e 611 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
58492e12 612 &entry, sizeof(entry));
b36ca91e 613
93f1cc67 614 amd_iommu_reset_cmd_buffer(iommu);
b36ca91e
JR		 615}
616
617static void __init free_command_buffer(struct amd_iommu *iommu)
618{
deba4bce 619 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
b36ca91e
JR		 620}
621
335503e5 622/* allocates the memory where the IOMMU will log its events to */
f2c2db53 623static int __init alloc_event_buffer(struct amd_iommu *iommu)
335503e5 624{
f2c2db53
JR		 625 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
626 get_order(EVT_BUFFER_SIZE));
335503e5 627
f2c2db53 628 return iommu->evt_buf ? 0 : -ENOMEM;
58492e12
JR		 629}
630
631static void iommu_enable_event_buffer(struct amd_iommu *iommu)
632{
633 u64 entry;
634
635 BUG_ON(iommu->evt_buf == NULL);
636
335503e5 637 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
58492e12 638
335503e5
JR		 639 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
640 &entry, sizeof(entry));
641
09067207
JR		 642 /* set head and tail to zero manually */
643 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
644 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
645
58492e12 646 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
335503e5
JR		 647}
648
649static void __init free_event_buffer(struct amd_iommu *iommu)
650{
651 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
652}
653
1a29ac01 654/* allocates the memory where the IOMMU will log its events to */
f2c2db53 655static int __init alloc_ppr_log(struct amd_iommu *iommu)
1a29ac01 656{
f2c2db53
JR		 657 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
658 get_order(PPR_LOG_SIZE));
1a29ac01 659
f2c2db53 660 return iommu->ppr_log ? 0 : -ENOMEM;
1a29ac01
JR		 661}
662
663static void iommu_enable_ppr_log(struct amd_iommu *iommu)
664{
665 u64 entry;
666
667 if (iommu->ppr_log == NULL)
668 return;
669
670 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
671
672 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
673 &entry, sizeof(entry));
674
675 /* set head and tail to zero manually */
676 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
677 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
678
679 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
680 iommu_feature_enable(iommu, CONTROL_PPR_EN);
681}
682
683static void __init free_ppr_log(struct amd_iommu *iommu)
684{
685 if (iommu->ppr_log == NULL)
686 return;
687
688 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
689}
690
8bda0cfb
SS		 691static void free_ga_log(struct amd_iommu *iommu)
692{
693#ifdef CONFIG_IRQ_REMAP
694 if (iommu->ga_log)
695 free_pages((unsigned long)iommu->ga_log,
696 get_order(GA_LOG_SIZE));
697 if (iommu->ga_log_tail)
698 free_pages((unsigned long)iommu->ga_log_tail,
699 get_order(8));
700#endif
701}
702
703static int iommu_ga_log_enable(struct amd_iommu *iommu)
704{
705#ifdef CONFIG_IRQ_REMAP
706 u32 status, i;
707
708 if (!iommu->ga_log)
709 return -EINVAL;
710
711 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
712
713 /* Check if already running */
714 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
715 return 0;
716
717 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
718 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
719
720 for (i = 0; i < LOOP_TIMEOUT; ++i) {
721 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
722 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
723 break;
724 }
725
726 if (i >= LOOP_TIMEOUT)
727 return -EINVAL;
728#endif /* CONFIG_IRQ_REMAP */
729 return 0;
730}
731
732#ifdef CONFIG_IRQ_REMAP
733static int iommu_init_ga_log(struct amd_iommu *iommu)
734{
735 u64 entry;
736
737 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
738 return 0;
739
740 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
741 get_order(GA_LOG_SIZE));
742 if (!iommu->ga_log)
743 goto err_out;
744
745 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
746 get_order(8));
747 if (!iommu->ga_log_tail)
748 goto err_out;
749
750 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
751 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
752 &entry, sizeof(entry));
753 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
754 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
755 &entry, sizeof(entry));
756 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
757 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
758
759 return 0;
760err_out:
761 free_ga_log(iommu);
762 return -EINVAL;
763}
764#endif /* CONFIG_IRQ_REMAP */
765
766static int iommu_init_ga(struct amd_iommu *iommu)
767{
768 int ret = 0;
769
770#ifdef CONFIG_IRQ_REMAP
771 /* Note: We have already checked GASup from IVRS table.
772 * Now, we need to make sure that GAMSup is set.
773 */
774 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
775 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
776 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
777
778 ret = iommu_init_ga_log(iommu);
779#endif /* CONFIG_IRQ_REMAP */
780
781 return ret;
782}
783
cbc33a90
JR		 784static void iommu_enable_gt(struct amd_iommu *iommu)
785{
786 if (!iommu_feature(iommu, FEATURE_GT))
787 return;
788
789 iommu_feature_enable(iommu, CONTROL_GT_EN);
790}
791
b65233a9 792/* sets a specific bit in the device table entry. */
3566b778
JR		 793static void set_dev_entry_bit(u16 devid, u8 bit)
794{
ee6c2868
JR		 795 int i = (bit >> 6) & 0x03;
796 int _bit = bit & 0x3f;
3566b778 797
ee6c2868 798 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
3566b778
JR		 799}
800
c5cca146
JR		 801static int get_dev_entry_bit(u16 devid, u8 bit)
802{
ee6c2868
JR		 803 int i = (bit >> 6) & 0x03;
804 int _bit = bit & 0x3f;
c5cca146 805
ee6c2868 806 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
c5cca146
JR		 807}
808
809
810void amd_iommu_apply_erratum_63(u16 devid)
811{
812 int sysmgt;
813
814 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
815 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
816
817 if (sysmgt == 0x01)
818 set_dev_entry_bit(devid, DEV_ENTRY_IW);
819}
820
5ff4789d
JR		 821/* Writes the specific IOMMU for a device into the rlookup table */
822static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
823{
824 amd_iommu_rlookup_table[devid] = iommu;
825}
826
b65233a9
JR		 827/*
828 * This function takes the device specific flags read from the ACPI
829 * table and sets up the device table entry with that information
830 */
5ff4789d
JR		 831static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
832 u16 devid, u32 flags, u32 ext_flags)
3566b778
JR		 833{
834 if (flags & ACPI_DEVFLAG_INITPASS)
835 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
836 if (flags & ACPI_DEVFLAG_EXTINT)
837 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
838 if (flags & ACPI_DEVFLAG_NMI)
839 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
840 if (flags & ACPI_DEVFLAG_SYSMGT1)
841 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
842 if (flags & ACPI_DEVFLAG_SYSMGT2)
843 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
844 if (flags & ACPI_DEVFLAG_LINT0)
845 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
846 if (flags & ACPI_DEVFLAG_LINT1)
847 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
3566b778 848
c5cca146
JR		 849 amd_iommu_apply_erratum_63(devid);
850
5ff4789d 851 set_iommu_for_device(iommu, devid);
3566b778
JR		 852}
853
c50e3247 854static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
6efed63b
JR		 855{
856 struct devid_map *entry;
857 struct list_head *list;
858
31cff67f
JR		 859 if (type == IVHD_SPECIAL_IOAPIC)
860 list = &ioapic_map;
861 else if (type == IVHD_SPECIAL_HPET)
862 list = &hpet_map;
863 else
6efed63b
JR		 864 return -EINVAL;
865
31cff67f
JR		 866 list_for_each_entry(entry, list, list) {
867 if (!(entry->id == id && entry->cmd_line))
868 continue;
869
870 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
871 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
872
c50e3247
JR		 873 *devid = entry->devid;
874
31cff67f
JR		 875 return 0;
876 }
877
6efed63b
JR		 878 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
879 if (!entry)
880 return -ENOMEM;
881
31cff67f 882 entry->id = id;
c50e3247 883 entry->devid = *devid;
31cff67f 884 entry->cmd_line = cmd_line;
6efed63b
JR		 885
886 list_add_tail(&entry->list, list);
887
888 return 0;
889}
890
2a0cb4e2
WZ		 891static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
892 bool cmd_line)
893{
894 struct acpihid_map_entry *entry;
895 struct list_head *list = &acpihid_map;
896
897 list_for_each_entry(entry, list, list) {
898 if (strcmp(entry->hid, hid) ||
899 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
900 !entry->cmd_line)
901 continue;
902
903 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
904 hid, uid);
905 *devid = entry->devid;
906 return 0;
907 }
908
909 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
910 if (!entry)
911 return -ENOMEM;
912
913 memcpy(entry->uid, uid, strlen(uid));
914 memcpy(entry->hid, hid, strlen(hid));
915 entry->devid = *devid;
916 entry->cmd_line = cmd_line;
917 entry->root_devid = (entry->devid & (~0x7));
918
919 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
920 entry->cmd_line ? "cmd" : "ivrs",
921 entry->hid, entry->uid, entry->root_devid);
922
923 list_add_tail(&entry->list, list);
924 return 0;
925}
926
235dacbc
JR		 927static int __init add_early_maps(void)
928{
929 int i, ret;
930
931 for (i = 0; i < early_ioapic_map_size; ++i) {
932 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
933 early_ioapic_map[i].id,
c50e3247 934 &early_ioapic_map[i].devid,
235dacbc
JR		 935 early_ioapic_map[i].cmd_line);
936 if (ret)
937 return ret;
938 }
939
940 for (i = 0; i < early_hpet_map_size; ++i) {
941 ret = add_special_device(IVHD_SPECIAL_HPET,
942 early_hpet_map[i].id,
c50e3247 943 &early_hpet_map[i].devid,
235dacbc
JR		 944 early_hpet_map[i].cmd_line);
945 if (ret)
946 return ret;
947 }
948
2a0cb4e2
WZ		 949 for (i = 0; i < early_acpihid_map_size; ++i) {
950 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
951 early_acpihid_map[i].uid,
952 &early_acpihid_map[i].devid,
953 early_acpihid_map[i].cmd_line);
954 if (ret)
955 return ret;
956 }
957
235dacbc
JR		 958 return 0;
959}
960
b65233a9 961/*
df805abb 962 * Reads the device exclusion range from ACPI and initializes the IOMMU with
b65233a9
JR		 963 * it
964 */
3566b778
JR		 965static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
966{
967 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
968
969 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
970 return;
971
972 if (iommu) {
b65233a9
JR		 973 /*
974 * We only can configure exclusion ranges per IOMMU, not
975 * per device. But we can enable the exclusion range per
976 * device. This is done here
977 */
2c16c9fd 978 set_dev_entry_bit(devid, DEV_ENTRY_EX);
3566b778
JR		 979 iommu->exclusion_start = m->range_start;
980 iommu->exclusion_length = m->range_length;
981 }
982}
983
b65233a9
JR		 984/*
985 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
986 * initializes the hardware and our data structures with it.
987 */
6efed63b 988static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
5d0c8e49
JR		 989 struct ivhd_header *h)
990{
991 u8 *p = (u8 *)h;
992 u8 *end = p, flags = 0;
0de66d5b
JR		 993 u16 devid = 0, devid_start = 0, devid_to = 0;
994 u32 dev_i, ext_flags = 0;
58a3bee5 995 bool alias = false;
5d0c8e49 996 struct ivhd_entry *e;
ac7ccf67 997 u32 ivhd_size;
235dacbc
JR		 998 int ret;
999
1000
1001 ret = add_early_maps();
1002 if (ret)
1003 return ret;
5d0c8e49
JR		 1004
1005 /*
e9bf5197 1006 * First save the recommended feature enable bits from ACPI
5d0c8e49 1007 */
e9bf5197 1008 iommu->acpi_flags = h->flags;
5d0c8e49
JR		 1009
1010 /*
1011 * Done. Now parse the device entries
1012 */
ac7ccf67
SS		 1013 ivhd_size = get_ivhd_header_size(h);
1014 if (!ivhd_size) {
1015 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1016 return -EINVAL;
1017 }
1018
1019 p += ivhd_size;
1020
5d0c8e49
JR		 1021 end += h->length;
1022
42a698f4 1023
5d0c8e49
JR		 1024 while (p < end) {
1025 e = (struct ivhd_entry *)p;
1026 switch (e->type) {
1027 case IVHD_DEV_ALL:
42a698f4 1028
226e889b 1029 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
42a698f4 1030
226e889b
JR		 1031 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1032 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
5d0c8e49
JR		 1033 break;
1034 case IVHD_DEV_SELECT:
42a698f4
JR		 1035
1036 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1037 "flags: %02x\n",
c5081cd7 1038 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1039 PCI_SLOT(e->devid),
1040 PCI_FUNC(e->devid),
1041 e->flags);
1042
5d0c8e49 1043 devid = e->devid;
5ff4789d 1044 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
5d0c8e49
JR		 1045 break;
1046 case IVHD_DEV_SELECT_RANGE_START:
42a698f4
JR		 1047
1048 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1049 "devid: %02x:%02x.%x flags: %02x\n",
c5081cd7 1050 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1051 PCI_SLOT(e->devid),
1052 PCI_FUNC(e->devid),
1053 e->flags);
1054
5d0c8e49
JR		 1055 devid_start = e->devid;
1056 flags = e->flags;
1057 ext_flags = 0;
58a3bee5 1058 alias = false;
5d0c8e49
JR		 1059 break;
1060 case IVHD_DEV_ALIAS:
42a698f4
JR		 1061
1062 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1063 "flags: %02x devid_to: %02x:%02x.%x\n",
c5081cd7 1064 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1065 PCI_SLOT(e->devid),
1066 PCI_FUNC(e->devid),
1067 e->flags,
c5081cd7 1068 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1069 PCI_SLOT(e->ext >> 8),
1070 PCI_FUNC(e->ext >> 8));
1071
5d0c8e49
JR		 1072 devid = e->devid;
1073 devid_to = e->ext >> 8;
7a6a3a08 1074 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
7455aab1 1075 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
5d0c8e49
JR		 1076 amd_iommu_alias_table[devid] = devid_to;
1077 break;
1078 case IVHD_DEV_ALIAS_RANGE:
42a698f4
JR		 1079
1080 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1081 "devid: %02x:%02x.%x flags: %02x "
1082 "devid_to: %02x:%02x.%x\n",
c5081cd7 1083 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1084 PCI_SLOT(e->devid),
1085 PCI_FUNC(e->devid),
1086 e->flags,
c5081cd7 1087 PCI_BUS_NUM(e->ext >> 8),
42a698f4
JR		 1088 PCI_SLOT(e->ext >> 8),
1089 PCI_FUNC(e->ext >> 8));
1090
5d0c8e49
JR		 1091 devid_start = e->devid;
1092 flags = e->flags;
1093 devid_to = e->ext >> 8;
1094 ext_flags = 0;
58a3bee5 1095 alias = true;
5d0c8e49
JR		 1096 break;
1097 case IVHD_DEV_EXT_SELECT:
42a698f4
JR		 1098
1099 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1100 "flags: %02x ext: %08x\n",
c5081cd7 1101 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1102 PCI_SLOT(e->devid),
1103 PCI_FUNC(e->devid),
1104 e->flags, e->ext);
1105
5d0c8e49 1106 devid = e->devid;
5ff4789d
JR		 1107 set_dev_entry_from_acpi(iommu, devid, e->flags,
1108 e->ext);
5d0c8e49
JR		 1109 break;
1110 case IVHD_DEV_EXT_SELECT_RANGE:
42a698f4
JR		 1111
1112 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1113 "%02x:%02x.%x flags: %02x ext: %08x\n",
c5081cd7 1114 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1115 PCI_SLOT(e->devid),
1116 PCI_FUNC(e->devid),
1117 e->flags, e->ext);
1118
5d0c8e49
JR		 1119 devid_start = e->devid;
1120 flags = e->flags;
1121 ext_flags = e->ext;
58a3bee5 1122 alias = false;
5d0c8e49
JR		 1123 break;
1124 case IVHD_DEV_RANGE_END:
42a698f4
JR		 1125
1126 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
c5081cd7 1127 PCI_BUS_NUM(e->devid),
42a698f4
JR		 1128 PCI_SLOT(e->devid),
1129 PCI_FUNC(e->devid));
1130
5d0c8e49
JR		 1131 devid = e->devid;
1132 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
7a6a3a08 1133 if (alias) {
5d0c8e49 1134 amd_iommu_alias_table[dev_i] = devid_to;
7a6a3a08
JR		 1135 set_dev_entry_from_acpi(iommu,
1136 devid_to, flags, ext_flags);
1137 }
1138 set_dev_entry_from_acpi(iommu, dev_i,
1139 flags, ext_flags);
5d0c8e49
JR		 1140 }
1141 break;
6efed63b
JR		 1142 case IVHD_DEV_SPECIAL: {
1143 u8 handle, type;
1144 const char *var;
1145 u16 devid;
1146 int ret;
1147
1148 handle = e->ext & 0xff;
1149 devid = (e->ext >> 8) & 0xffff;
1150 type = (e->ext >> 24) & 0xff;
1151
1152 if (type == IVHD_SPECIAL_IOAPIC)
1153 var = "IOAPIC";
1154 else if (type == IVHD_SPECIAL_HPET)
1155 var = "HPET";
1156 else
1157 var = "UNKNOWN";
1158
1159 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1160 var, (int)handle,
c5081cd7 1161 PCI_BUS_NUM(devid),
6efed63b
JR		 1162 PCI_SLOT(devid),
1163 PCI_FUNC(devid));
1164
c50e3247 1165 ret = add_special_device(type, handle, &devid, false);
6efed63b
JR		 1166 if (ret)
1167 return ret;
c50e3247
JR		 1168
1169 /*
1170 * add_special_device might update the devid in case a
1171 * command-line override is present. So call
1172 * set_dev_entry_from_acpi after add_special_device.
1173 */
1174 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1175
6efed63b
JR		 1176 break;
1177 }
2a0cb4e2
WZ		 1178 case IVHD_DEV_ACPI_HID: {
1179 u16 devid;
1180 u8 hid[ACPIHID_HID_LEN] = {0};
1181 u8 uid[ACPIHID_UID_LEN] = {0};
1182 int ret;
1183
1184 if (h->type != 0x40) {
1185 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1186 e->type);
1187 break;
1188 }
1189
1190 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1191 hid[ACPIHID_HID_LEN - 1] = '\0';
1192
1193 if (!(*hid)) {
1194 pr_err(FW_BUG "Invalid HID.\n");
1195 break;
1196 }
1197
1198 switch (e->uidf) {
1199 case UID_NOT_PRESENT:
1200
1201 if (e->uidl != 0)
1202 pr_warn(FW_BUG "Invalid UID length.\n");
1203
1204 break;
1205 case UID_IS_INTEGER:
1206
1207 sprintf(uid, "%d", e->uid);
1208
1209 break;
1210 case UID_IS_CHARACTER:
1211
1212 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1213 uid[ACPIHID_UID_LEN - 1] = '\0';
1214
1215 break;
1216 default:
1217 break;
1218 }
1219
6082ee72 1220 devid = e->devid;
2a0cb4e2
WZ		 1221 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1222 hid, uid,
1223 PCI_BUS_NUM(devid),
1224 PCI_SLOT(devid),
1225 PCI_FUNC(devid));
1226
2a0cb4e2
WZ		 1227 flags = e->flags;
1228
1229 ret = add_acpi_hid_device(hid, uid, &devid, false);
1230 if (ret)
1231 return ret;
1232
1233 /*
1234 * add_special_device might update the devid in case a
1235 * command-line override is present. So call
1236 * set_dev_entry_from_acpi after add_special_device.
1237 */
1238 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1239
1240 break;
1241 }
5d0c8e49
JR		 1242 default:
1243 break;
1244 }
1245
b514e555 1246 p += ivhd_entry_length(p);
5d0c8e49 1247 }
6efed63b
JR		 1248
1249 return 0;
5d0c8e49
JR		 1250}
1251
e47d402d
JR		 1252static void __init free_iommu_one(struct amd_iommu *iommu)
1253{
1254 free_command_buffer(iommu);
335503e5 1255 free_event_buffer(iommu);
1a29ac01 1256 free_ppr_log(iommu);
8bda0cfb 1257 free_ga_log(iommu);
e47d402d
JR		 1258 iommu_unmap_mmio_space(iommu);
1259}
1260
1261static void __init free_iommu_all(void)
1262{
1263 struct amd_iommu *iommu, *next;
1264
3bd22172 1265 for_each_iommu_safe(iommu, next) {
e47d402d
JR		 1266 list_del(&iommu->list);
1267 free_iommu_one(iommu);
1268 kfree(iommu);
1269 }
1270}
1271
318fe782
SS		 1272/*
1273 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1274 * Workaround:
1275 * BIOS should disable L2B micellaneous clock gating by setting
1276 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1277 */
e2f1a3bd 1278static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
318fe782
SS		 1279{
1280 u32 value;
1281
1282 if ((boot_cpu_data.x86 != 0x15) ||
1283 (boot_cpu_data.x86_model < 0x10) ||
1284 (boot_cpu_data.x86_model > 0x1f))
1285 return;
1286
1287 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1288 pci_read_config_dword(iommu->dev, 0xf4, &value);
1289
1290 if (value & BIT(2))
1291 return;
1292
1293 /* Select NB indirect register 0x90 and enable writing */
1294 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1295
1296 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1297 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1298 dev_name(&iommu->dev->dev));
1299
1300 /* Clear the enable writing bit */
1301 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1302}
1303
358875fd
JC		 1304/*
1305 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1306 * Workaround:
1307 * BIOS should enable ATS write permission check by setting
1308 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1309 */
1310static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1311{
1312 u32 value;
1313
1314 if ((boot_cpu_data.x86 != 0x15) ||
1315 (boot_cpu_data.x86_model < 0x30) ||
1316 (boot_cpu_data.x86_model > 0x3f))
1317 return;
1318
1319 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1320 value = iommu_read_l2(iommu, 0x47);
1321
1322 if (value & BIT(0))
1323 return;
1324
1325 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1326 iommu_write_l2(iommu, 0x47, value | BIT(0));
1327
1328 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1329 dev_name(&iommu->dev->dev));
1330}
1331
b65233a9
JR		 1332/*
1333 * This function clues the initialization function for one IOMMU
1334 * together and also allocates the command buffer and programs the
1335 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1336 */
e47d402d
JR		 1337static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1338{
6efed63b
JR		 1339 int ret;
1340
e47d402d 1341 spin_lock_init(&iommu->lock);
bb52777e
JR		 1342
1343 /* Add IOMMU to internal data structures */
e47d402d 1344 list_add_tail(&iommu->list, &amd_iommu_list);
6b9376e3 1345 iommu->index = amd_iommus_present++;
bb52777e
JR		 1346
1347 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1348 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1349 return -ENOSYS;
1350 }
1351
1352 /* Index is fine - add IOMMU to the array */
1353 amd_iommus[iommu->index] = iommu;
e47d402d
JR		 1354
1355 /*
1356 * Copy data from ACPI table entry to the iommu struct
1357 */
23c742db 1358 iommu->devid = h->devid;
e47d402d 1359 iommu->cap_ptr = h->cap_ptr;
ee893c24 1360 iommu->pci_seg = h->pci_seg;
e47d402d 1361 iommu->mmio_phys = h->mmio_phys;
30861ddc 1362
7d7d38af
SS		 1363 switch (h->type) {
1364 case 0x10:
1365 /* Check if IVHD EFR contains proper max banks/counters */
1366 if ((h->efr_attr != 0) &&
1367 ((h->efr_attr & (0xF << 13)) != 0) &&
1368 ((h->efr_attr & (0x3F << 17)) != 0))
1369 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1370 else
1371 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1372 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1373 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1374 break;
1375 case 0x11:
1376 case 0x40:
1377 if (h->efr_reg & (1 << 9))
1378 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1379 else
1380 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
3928aa3f
SS		 1381 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1382 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
7d7d38af
SS		 1383 break;
1384 default:
1385 return -EINVAL;
30861ddc
SK		 1386 }
1387
1388 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1389 iommu->mmio_phys_end);
e47d402d
JR		 1390 if (!iommu->mmio_base)
1391 return -ENOMEM;
1392
f2c2db53 1393 if (alloc_command_buffer(iommu))
e47d402d
JR		 1394 return -ENOMEM;
1395
f2c2db53 1396 if (alloc_event_buffer(iommu))
335503e5
JR		 1397 return -ENOMEM;
1398
a80dc3e0
JR		 1399 iommu->int_enabled = false;
1400
6efed63b
JR		 1401 ret = init_iommu_from_acpi(iommu, h);
1402 if (ret)
1403 return ret;
f6fec00a 1404
7c71d306
JL		 1405 ret = amd_iommu_create_irq_domain(iommu);
1406 if (ret)
1407 return ret;
1408
f6fec00a
JR		 1409 /*
1410 * Make sure IOMMU is not considered to translate itself. The IVRS
1411 * table tells us so, but this is a lie!
1412 */
1413 amd_iommu_rlookup_table[iommu->devid] = NULL;
1414
23c742db 1415 return 0;
e47d402d
JR		 1416}
1417
8c7142f5
SS		 1418/**
1419 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1420 * @ivrs Pointer to the IVRS header
1421 *
1422 * This function search through all IVDB of the maximum supported IVHD
1423 */
1424static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1425{
1426 u8 *base = (u8 *)ivrs;
1427 struct ivhd_header *ivhd = (struct ivhd_header *)
1428 (base + IVRS_HEADER_LENGTH);
1429 u8 last_type = ivhd->type;
1430 u16 devid = ivhd->devid;
1431
1432 while (((u8 *)ivhd - base < ivrs->length) &&
1433 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1434 u8 *p = (u8 *) ivhd;
1435
1436 if (ivhd->devid == devid)
1437 last_type = ivhd->type;
1438 ivhd = (struct ivhd_header *)(p + ivhd->length);
1439 }
1440
1441 return last_type;
1442}
1443
b65233a9
JR		 1444/*
1445 * Iterates over all IOMMU entries in the ACPI table, allocates the
1446 * IOMMU structure and initializes it with init_iommu_one()
1447 */
e47d402d
JR		 1448static int __init init_iommu_all(struct acpi_table_header *table)
1449{
1450 u8 *p = (u8 *)table, *end = (u8 *)table;
1451 struct ivhd_header *h;
1452 struct amd_iommu *iommu;
1453 int ret;
1454
e47d402d
JR		 1455 end += table->length;
1456 p += IVRS_HEADER_LENGTH;
1457
1458 while (p < end) {
1459 h = (struct ivhd_header *)p;
8c7142f5 1460 if (*p == amd_iommu_target_ivhd_type) {
9c72041f 1461
ae908c22 1462 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
9c72041f 1463 "seg: %d flags: %01x info %04x\n",
c5081cd7 1464 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
9c72041f
JR		 1465 PCI_FUNC(h->devid), h->cap_ptr,
1466 h->pci_seg, h->flags, h->info);
1467 DUMP_printk(" mmio-addr: %016llx\n",
1468 h->mmio_phys);
1469
e47d402d 1470 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
02f3b3f5
JR		 1471 if (iommu == NULL)
1472 return -ENOMEM;
3551a708 1473
e47d402d 1474 ret = init_iommu_one(iommu, h);
02f3b3f5
JR		 1475 if (ret)
1476 return ret;
e47d402d
JR		 1477 }
1478 p += h->length;
1479
1480 }
1481 WARN_ON(p != end);
1482
1483 return 0;
1484}
1485
1650dfd1
SS		 1486static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1487 u8 fxn, u64 *value, bool is_write);
30861ddc
SK		 1488
1489static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1490{
1491 u64 val = 0xabcd, val2 = 0;
1492
1493 if (!iommu_feature(iommu, FEATURE_PC))
1494 return;
1495
1496 amd_iommu_pc_present = true;
1497
1498 /* Check if the performance counters can be written to */
1650dfd1
SS		 1499 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1500 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
30861ddc
SK		 1501 (val != val2)) {
1502 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1503 amd_iommu_pc_present = false;
1504 return;
1505 }
1506
1507 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1508
1509 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1510 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1511 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1512}
1513
066f2e98
AW		 1514static ssize_t amd_iommu_show_cap(struct device *dev,
1515 struct device_attribute *attr,
1516 char *buf)
1517{
b7a42b9d 1518 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
066f2e98
AW		 1519 return sprintf(buf, "%x\n", iommu->cap);
1520}
1521static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1522
1523static ssize_t amd_iommu_show_features(struct device *dev,
1524 struct device_attribute *attr,
1525 char *buf)
1526{
b7a42b9d 1527 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
066f2e98
AW		 1528 return sprintf(buf, "%llx\n", iommu->features);
1529}
1530static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1531
1532static struct attribute *amd_iommu_attrs[] = {
1533 &dev_attr_cap.attr,
1534 &dev_attr_features.attr,
1535 NULL,
1536};
1537
1538static struct attribute_group amd_iommu_group = {
1539 .name = "amd-iommu",
1540 .attrs = amd_iommu_attrs,
1541};
1542
1543static const struct attribute_group *amd_iommu_groups[] = {
1544 &amd_iommu_group,
1545 NULL,
1546};
30861ddc 1547
23c742db
JR		 1548static int iommu_init_pci(struct amd_iommu *iommu)
1549{
1550 int cap_ptr = iommu->cap_ptr;
1551 u32 range, misc, low, high;
8bda0cfb 1552 int ret;
23c742db 1553
c5081cd7 1554 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
23c742db
JR		 1555 iommu->devid & 0xff);
1556 if (!iommu->dev)
1557 return -ENODEV;
1558
cbbc00be
JL		 1559 /* Prevent binding other PCI device drivers to IOMMU devices */
1560 iommu->dev->match_driver = false;
1561
23c742db
JR		 1562 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1563 &iommu->cap);
1564 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1565 &range);
1566 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1567 &misc);
1568
23c742db
JR		 1569 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1570 amd_iommu_iotlb_sup = false;
1571
1572 /* read extended feature bits */
1573 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1574 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1575
1576 iommu->features = ((u64)high << 32) | low;
1577
1578 if (iommu_feature(iommu, FEATURE_GT)) {
1579 int glxval;
a919a018
SS		 1580 u32 max_pasid;
1581 u64 pasmax;
23c742db 1582
a919a018
SS		 1583 pasmax = iommu->features & FEATURE_PASID_MASK;
1584 pasmax >>= FEATURE_PASID_SHIFT;
1585 max_pasid = (1 << (pasmax + 1)) - 1;
23c742db 1586
a919a018
SS		 1587 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1588
1589 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
23c742db
JR		 1590
1591 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1592 glxval >>= FEATURE_GLXVAL_SHIFT;
1593
1594 if (amd_iommu_max_glx_val == -1)
1595 amd_iommu_max_glx_val = glxval;
1596 else
1597 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1598 }
1599
1600 if (iommu_feature(iommu, FEATURE_GT) &&
1601 iommu_feature(iommu, FEATURE_PPR)) {
1602 iommu->is_iommu_v2 = true;
1603 amd_iommu_v2_present = true;
1604 }
1605
f2c2db53
JR		 1606 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1607 return -ENOMEM;
23c742db 1608
8bda0cfb
SS		 1609 ret = iommu_init_ga(iommu);
1610 if (ret)
1611 return ret;
3928aa3f 1612
23c742db
JR		 1613 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1614 amd_iommu_np_cache = true;
1615
30861ddc
SK		 1616 init_iommu_perf_ctr(iommu);
1617
23c742db
JR		 1618 if (is_rd890_iommu(iommu->dev)) {
1619 int i, j;
1620
1621 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1622 PCI_DEVFN(0, 0));
1623
1624 /*
1625 * Some rd890 systems may not be fully reconfigured by the
1626 * BIOS, so it's necessary for us to store this information so
1627 * it can be reprogrammed on resume
1628 */
1629 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1630 &iommu->stored_addr_lo);
1631 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1632 &iommu->stored_addr_hi);
1633
1634 /* Low bit locks writes to configuration space */
1635 iommu->stored_addr_lo &= ~1;
1636
1637 for (i = 0; i < 6; i++)
1638 for (j = 0; j < 0x12; j++)
1639 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1640
1641 for (i = 0; i < 0x83; i++)
1642 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1643 }
1644
318fe782 1645 amd_iommu_erratum_746_workaround(iommu);
358875fd 1646 amd_iommu_ats_write_check_workaround(iommu);
318fe782 1647
39ab9555
JR		 1648 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1649 amd_iommu_groups, "ivhd%d", iommu->index);
b0119e87
JR		 1650 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1651 iommu_device_register(&iommu->iommu);
066f2e98 1652
23c742db
JR		 1653 return pci_enable_device(iommu->dev);
1654}
1655
4d121c32
JR		 1656static void print_iommu_info(void)
1657{
1658 static const char * const feat_str[] = {
1659 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1660 "IA", "GA", "HE", "PC"
1661 };
1662 struct amd_iommu *iommu;
1663
1664 for_each_iommu(iommu) {
1665 int i;
1666
1667 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1668 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1669
1670 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
3928aa3f
SS		 1671 pr_info("AMD-Vi: Extended features (%#llx):\n",
1672 iommu->features);
2bd5ed00 1673 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
4d121c32
JR		 1674 if (iommu_feature(iommu, (1ULL << i)))
1675 pr_cont(" %s", feat_str[i]);
1676 }
3928aa3f
SS		 1677
1678 if (iommu->features & FEATURE_GAM_VAPIC)
1679 pr_cont(" GA_vAPIC");
1680
30861ddc 1681 pr_cont("\n");
500c25ed 1682 }
4d121c32 1683 }
3928aa3f 1684 if (irq_remapping_enabled) {
ebe60bbf 1685 pr_info("AMD-Vi: Interrupt remapping enabled\n");
3928aa3f
SS		 1686 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1687 pr_info("AMD-Vi: virtual APIC enabled\n");
1688 }
4d121c32
JR		 1689}
1690
2c0ae172 1691static int __init amd_iommu_init_pci(void)
23c742db
JR		 1692{
1693 struct amd_iommu *iommu;
1694 int ret = 0;
1695
1696 for_each_iommu(iommu) {
1697 ret = iommu_init_pci(iommu);
1698 if (ret)
1699 break;
1700 }
1701
522e5cb7
JR		 1702 /*
1703 * Order is important here to make sure any unity map requirements are
1704 * fulfilled. The unity mappings are created and written to the device
1705 * table during the amd_iommu_init_api() call.
1706 *
1707 * After that we call init_device_table_dma() to make sure any
1708 * uninitialized DTE will block DMA, and in the end we flush the caches
1709 * of all IOMMUs to make sure the changes to the device table are
1710 * active.
1711 */
1712 ret = amd_iommu_init_api();
1713
aafd8ba0
JR		 1714 init_device_table_dma();
1715
1716 for_each_iommu(iommu)
1717 iommu_flush_all_caches(iommu);
1718
3a18404c
JR		 1719 if (!ret)
1720 print_iommu_info();
4d121c32 1721
23c742db
JR		 1722 return ret;
1723}
1724
a80dc3e0
JR		 1725/****************************************************************************
1726 *
1727 * The following functions initialize the MSI interrupts for all IOMMUs
df805abb 1728 * in the system. It's a bit challenging because there could be multiple
a80dc3e0
JR		 1729 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1730 * pci_dev.
1731 *
1732 ****************************************************************************/
1733
9f800de3 1734static int iommu_setup_msi(struct amd_iommu *iommu)
a80dc3e0
JR		 1735{
1736 int r;
a80dc3e0 1737
9ddd592a
JR		 1738 r = pci_enable_msi(iommu->dev);
1739 if (r)
1740 return r;
a80dc3e0 1741
72fe00f0
JR		 1742 r = request_threaded_irq(iommu->dev->irq,
1743 amd_iommu_int_handler,
1744 amd_iommu_int_thread,
1745 0, "AMD-Vi",
3f398bc7 1746 iommu);
a80dc3e0
JR		 1747
1748 if (r) {
1749 pci_disable_msi(iommu->dev);
9ddd592a 1750 return r;
a80dc3e0
JR		 1751 }
1752
fab6afa3 1753 iommu->int_enabled = true;
1a29ac01 1754
a80dc3e0
JR		 1755 return 0;
1756}
1757
05f92db9 1758static int iommu_init_msi(struct amd_iommu *iommu)
a80dc3e0 1759{
9ddd592a
JR		 1760 int ret;
1761
a80dc3e0 1762 if (iommu->int_enabled)
9ddd592a 1763 goto enable_faults;
a80dc3e0 1764
82fcfc67 1765 if (iommu->dev->msi_cap)
9ddd592a
JR		 1766 ret = iommu_setup_msi(iommu);
1767 else
1768 ret = -ENODEV;
1769
1770 if (ret)
1771 return ret;
a80dc3e0 1772
9ddd592a
JR		 1773enable_faults:
1774 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
a80dc3e0 1775
9ddd592a
JR		 1776 if (iommu->ppr_log != NULL)
1777 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1778
8bda0cfb
SS		 1779 iommu_ga_log_enable(iommu);
1780
9ddd592a 1781 return 0;
a80dc3e0
JR		 1782}
1783
b65233a9
JR		 1784/****************************************************************************
1785 *
1786 * The next functions belong to the third pass of parsing the ACPI
1787 * table. In this last pass the memory mapping requirements are
df805abb 1788 * gathered (like exclusion and unity mapping ranges).
b65233a9
JR		 1789 *
1790 ****************************************************************************/
1791
be2a022c
JR		 1792static void __init free_unity_maps(void)
1793{
1794 struct unity_map_entry *entry, *next;
1795
1796 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1797 list_del(&entry->list);
1798 kfree(entry);
1799 }
1800}
1801
b65233a9 1802/* called when we find an exclusion range definition in ACPI */
be2a022c
JR		 1803static int __init init_exclusion_range(struct ivmd_header *m)
1804{
1805 int i;
1806
1807 switch (m->type) {
1808 case ACPI_IVMD_TYPE:
1809 set_device_exclusion_range(m->devid, m);
1810 break;
1811 case ACPI_IVMD_TYPE_ALL:
3a61ec38 1812 for (i = 0; i <= amd_iommu_last_bdf; ++i)
be2a022c
JR		 1813 set_device_exclusion_range(i, m);
1814 break;
1815 case ACPI_IVMD_TYPE_RANGE:
1816 for (i = m->devid; i <= m->aux; ++i)
1817 set_device_exclusion_range(i, m);
1818 break;
1819 default:
1820 break;
1821 }
1822
1823 return 0;
1824}
1825
b65233a9 1826/* called for unity map ACPI definition */
be2a022c
JR		 1827static int __init init_unity_map_range(struct ivmd_header *m)
1828{
98f1ad25 1829 struct unity_map_entry *e = NULL;
02acc43a 1830 char *s;
be2a022c
JR		 1831
1832 e = kzalloc(sizeof(*e), GFP_KERNEL);
1833 if (e == NULL)
1834 return -ENOMEM;
1835
1836 switch (m->type) {
1837 default:
0bc252f4
JR		 1838 kfree(e);
1839 return 0;
be2a022c 1840 case ACPI_IVMD_TYPE:
02acc43a 1841 s = "IVMD_TYPEi\t\t\t";
be2a022c
JR		 1842 e->devid_start = e->devid_end = m->devid;
1843 break;
1844 case ACPI_IVMD_TYPE_ALL:
02acc43a 1845 s = "IVMD_TYPE_ALL\t\t";
be2a022c
JR		 1846 e->devid_start = 0;
1847 e->devid_end = amd_iommu_last_bdf;
1848 break;
1849 case ACPI_IVMD_TYPE_RANGE:
02acc43a 1850 s = "IVMD_TYPE_RANGE\t\t";
be2a022c
JR		 1851 e->devid_start = m->devid;
1852 e->devid_end = m->aux;
1853 break;
1854 }
1855 e->address_start = PAGE_ALIGN(m->range_start);
1856 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1857 e->prot = m->flags >> 1;
1858
02acc43a
JR		 1859 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1860 " range_start: %016llx range_end: %016llx flags: %x\n", s,
c5081cd7
SK		 1861 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1862 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
02acc43a
JR		 1863 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1864 e->address_start, e->address_end, m->flags);
1865
be2a022c
JR		 1866 list_add_tail(&e->list, &amd_iommu_unity_map);
1867
1868 return 0;
1869}
1870
b65233a9 1871/* iterates over all memory definitions we find in the ACPI table */
be2a022c
JR		 1872static int __init init_memory_definitions(struct acpi_table_header *table)
1873{
1874 u8 *p = (u8 *)table, *end = (u8 *)table;
1875 struct ivmd_header *m;
1876
be2a022c
JR		 1877 end += table->length;
1878 p += IVRS_HEADER_LENGTH;
1879
1880 while (p < end) {
1881 m = (struct ivmd_header *)p;
1882 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1883 init_exclusion_range(m);
1884 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1885 init_unity_map_range(m);
1886
1887 p += m->length;
1888 }
1889
1890 return 0;
1891}
1892
9f5f5fb3
JR		 1893/*
1894 * Init the device table to not allow DMA access for devices and
1895 * suppress all page faults
1896 */
33f28c59 1897static void init_device_table_dma(void)
9f5f5fb3 1898{
0de66d5b 1899 u32 devid;
9f5f5fb3
JR		 1900
1901 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1902 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1903 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
54bd6357
JR		 1904 /*
1905 * In kdump kernels in-flight DMA from the old kernel might
1906 * cause IO_PAGE_FAULTs. There are no reports that a kdump
1907 * actually failed because of that, so just disable fault
1908 * reporting in the hardware to get rid of the messages
1909 */
1910 if (is_kdump_kernel())
1911 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
9f5f5fb3
JR		 1912 }
1913}
1914
d04e0ba3
JR		 1915static void __init uninit_device_table_dma(void)
1916{
1917 u32 devid;
1918
1919 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1920 amd_iommu_dev_table[devid].data[0] = 0ULL;
1921 amd_iommu_dev_table[devid].data[1] = 0ULL;
1922 }
1923}
1924
33f28c59
JR		 1925static void init_device_table(void)
1926{
1927 u32 devid;
1928
1929 if (!amd_iommu_irq_remap)
1930 return;
1931
1932 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1933 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1934}
1935
e9bf5197
JR		 1936static void iommu_init_flags(struct amd_iommu *iommu)
1937{
1938 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1939 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1940 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1941
1942 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1943 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1944 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1945
1946 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1947 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1948 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1949
1950 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1951 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1952 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1953
1954 /*
1955 * make IOMMU memory accesses cache coherent
1956 */
1957 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1456e9d2
JR		 1958
1959 /* Set IOTLB invalidation timeout to 1s */
1960 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
e9bf5197
JR		 1961}
1962
5bcd757f 1963static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
4c894f47 1964{
5bcd757f
MG		 1965 int i, j;
1966 u32 ioc_feature_control;
c1bf94ec 1967 struct pci_dev *pdev = iommu->root_pdev;
5bcd757f
MG		 1968
1969 /* RD890 BIOSes may not have completely reconfigured the iommu */
c1bf94ec 1970 if (!is_rd890_iommu(iommu->dev) || !pdev)
5bcd757f
MG		 1971 return;
1972
1973 /*
1974 * First, we need to ensure that the iommu is enabled. This is
1975 * controlled by a register in the northbridge
1976 */
5bcd757f
MG		 1977
1978 /* Select Northbridge indirect register 0x75 and enable writing */
1979 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1980 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1981
1982 /* Enable the iommu */
1983 if (!(ioc_feature_control & 0x1))
1984 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1985
5bcd757f
MG		 1986 /* Restore the iommu BAR */
1987 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1988 iommu->stored_addr_lo);
1989 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1990 iommu->stored_addr_hi);
1991
1992 /* Restore the l1 indirect regs for each of the 6 l1s */
1993 for (i = 0; i < 6; i++)
1994 for (j = 0; j < 0x12; j++)
1995 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1996
1997 /* Restore the l2 indirect regs */
1998 for (i = 0; i < 0x83; i++)
1999 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2000
2001 /* Lock PCI setup registers */
2002 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2003 iommu->stored_addr_lo | 1);
4c894f47
JR		 2004}
2005
3928aa3f
SS		 2006static void iommu_enable_ga(struct amd_iommu *iommu)
2007{
2008#ifdef CONFIG_IRQ_REMAP
2009 switch (amd_iommu_guest_ir) {
2010 case AMD_IOMMU_GUEST_IR_VAPIC:
2011 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2012 /* Fall through */
2013 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2014 iommu_feature_enable(iommu, CONTROL_GA_EN);
77bdab46 2015 iommu->irte_ops = &irte_128_ops;
3928aa3f
SS		 2016 break;
2017 default:
77bdab46 2018 iommu->irte_ops = &irte_32_ops;
3928aa3f
SS		 2019 break;
2020 }
2021#endif
2022}
2023
b65233a9
JR		 2024/*
2025 * This function finally enables all IOMMUs found in the system after
2026 * they have been initialized
2027 */
11ee5ac4 2028static void early_enable_iommus(void)
8736197b
JR		 2029{
2030 struct amd_iommu *iommu;
2031
3bd22172 2032 for_each_iommu(iommu) {
a8c485bb 2033 iommu_disable(iommu);
e9bf5197 2034 iommu_init_flags(iommu);
58492e12
JR		 2035 iommu_set_device_table(iommu);
2036 iommu_enable_command_buffer(iommu);
2037 iommu_enable_event_buffer(iommu);
8736197b 2038 iommu_set_exclusion_range(iommu);
3928aa3f 2039 iommu_enable_ga(iommu);
8736197b 2040 iommu_enable(iommu);
7d0c5cc5 2041 iommu_flush_all_caches(iommu);
8736197b 2042 }
d98de49a
SS		 2043
2044#ifdef CONFIG_IRQ_REMAP
2045 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2046 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2047#endif
8736197b
JR		 2048}
2049
11ee5ac4
JR		 2050static void enable_iommus_v2(void)
2051{
2052 struct amd_iommu *iommu;
2053
2054 for_each_iommu(iommu) {
2055 iommu_enable_ppr_log(iommu);
2056 iommu_enable_gt(iommu);
2057 }
2058}
2059
2060static void enable_iommus(void)
2061{
2062 early_enable_iommus();
2063
2064 enable_iommus_v2();
2065}
2066
92ac4320
JR		 2067static void disable_iommus(void)
2068{
2069 struct amd_iommu *iommu;
2070
2071 for_each_iommu(iommu)
2072 iommu_disable(iommu);
d98de49a
SS		 2073
2074#ifdef CONFIG_IRQ_REMAP
2075 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2076 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2077#endif
92ac4320
JR		 2078}
2079
7441e9cb
JR		 2080/*
2081 * Suspend/Resume support
2082 * disable suspend until real resume implemented
2083 */
2084
f3c6ea1b 2085static void amd_iommu_resume(void)
7441e9cb 2086{
5bcd757f
MG		 2087 struct amd_iommu *iommu;
2088
2089 for_each_iommu(iommu)
2090 iommu_apply_resume_quirks(iommu);
2091
736501ee
JR		 2092 /* re-load the hardware */
2093 enable_iommus();
3d9761e7
JR		 2094
2095 amd_iommu_enable_interrupts();
7441e9cb
JR		 2096}
2097
f3c6ea1b 2098static int amd_iommu_suspend(void)
7441e9cb 2099{
736501ee
JR		 2100 /* disable IOMMUs to go out of the way for BIOS */
2101 disable_iommus();
2102
2103 return 0;
7441e9cb
JR		 2104}
2105
f3c6ea1b 2106static struct syscore_ops amd_iommu_syscore_ops = {
7441e9cb
JR		 2107 .suspend = amd_iommu_suspend,
2108 .resume = amd_iommu_resume,
2109};
2110
90b3eb03 2111static void __init free_iommu_resources(void)
8704a1ba 2112{
ebcfa284 2113 kmemleak_free(irq_lookup_table);
0ea2c422
JR		 2114 free_pages((unsigned long)irq_lookup_table,
2115 get_order(rlookup_table_size));
8704a1ba 2116
a591989a
JL		 2117 kmem_cache_destroy(amd_iommu_irq_cache);
2118 amd_iommu_irq_cache = NULL;
8704a1ba
JR		 2119
2120 free_pages((unsigned long)amd_iommu_rlookup_table,
2121 get_order(rlookup_table_size));
2122
2123 free_pages((unsigned long)amd_iommu_alias_table,
2124 get_order(alias_table_size));
2125
2126 free_pages((unsigned long)amd_iommu_dev_table,
2127 get_order(dev_table_size));
2128
2129 free_iommu_all();
2130
8704a1ba
JR		 2131#ifdef CONFIG_GART_IOMMU
2132 /*
2133 * We failed to initialize the AMD IOMMU - try fallback to GART
2134 * if possible.
2135 */
2136 gart_iommu_init();
2137
2138#endif
2139}
2140
c2ff5cf5
JR		 2141/* SB IOAPIC is always on this device in AMD systems */
2142#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2143
eb1eb7ae
JR		 2144static bool __init check_ioapic_information(void)
2145{
dfbb6d47 2146 const char *fw_bug = FW_BUG;
c2ff5cf5 2147 bool ret, has_sb_ioapic;
eb1eb7ae
JR		 2148 int idx;
2149
c2ff5cf5
JR		 2150 has_sb_ioapic = false;
2151 ret = false;
eb1eb7ae 2152
dfbb6d47
JR		 2153 /*
2154 * If we have map overrides on the kernel command line the
2155 * messages in this function might not describe firmware bugs
2156 * anymore - so be careful
2157 */
2158 if (cmdline_maps)
2159 fw_bug = "";
2160
c2ff5cf5
JR		 2161 for (idx = 0; idx < nr_ioapics; idx++) {
2162 int devid, id = mpc_ioapic_id(idx);
2163
2164 devid = get_ioapic_devid(id);
2165 if (devid < 0) {
dfbb6d47
JR		 2166 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2167 fw_bug, id);
c2ff5cf5
JR		 2168 ret = false;
2169 } else if (devid == IOAPIC_SB_DEVID) {
2170 has_sb_ioapic = true;
2171 ret = true;
eb1eb7ae
JR		 2172 }
2173 }
2174
c2ff5cf5
JR		 2175 if (!has_sb_ioapic) {
2176 /*
2177 * We expect the SB IOAPIC to be listed in the IVRS
2178 * table. The system timer is connected to the SB IOAPIC
2179 * and if we don't have it in the list the system will
2180 * panic at boot time. This situation usually happens
2181 * when the BIOS is buggy and provides us the wrong
2182 * device id for the IOAPIC in the system.
2183 */
dfbb6d47 2184 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
c2ff5cf5
JR		 2185 }
2186
2187 if (!ret)
dfbb6d47 2188 pr_err("AMD-Vi: Disabling interrupt remapping\n");
c2ff5cf5
JR		 2189
2190 return ret;
eb1eb7ae
JR		 2191}
2192
d04e0ba3
JR		 2193static void __init free_dma_resources(void)
2194{
d04e0ba3
JR		 2195 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2196 get_order(MAX_DOMAIN_ID/8));
2197
2198 free_unity_maps();
2199}
2200
b65233a9 2201/*
8704a1ba
JR		 2202 * This is the hardware init function for AMD IOMMU in the system.
2203 * This function is called either from amd_iommu_init or from the interrupt
2204 * remapping setup code.
b65233a9
JR		 2205 *
2206 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
8c7142f5 2207 * four times:
b65233a9 2208 *
8c7142f5
SS		 2209 * 1 pass) Discover the most comprehensive IVHD type to use.
2210 *
2211 * 2 pass) Find the highest PCI device id the driver has to handle.
b65233a9
JR		 2212 * Upon this information the size of the data structures is
2213 * determined that needs to be allocated.
2214 *
8c7142f5 2215 * 3 pass) Initialize the data structures just allocated with the
b65233a9
JR		 2216 * information in the ACPI table about available AMD IOMMUs
2217 * in the system. It also maps the PCI devices in the
2218 * system to specific IOMMUs
2219 *
8c7142f5 2220 * 4 pass) After the basic data structures are allocated and
b65233a9
JR		 2221 * initialized we update them with information about memory
2222 * remapping requirements parsed out of the ACPI table in
2223 * this last pass.
2224 *
8704a1ba
JR		 2225 * After everything is set up the IOMMUs are enabled and the necessary
2226 * hotplug and suspend notifiers are registered.
b65233a9 2227 */
643511b3 2228static int __init early_amd_iommu_init(void)
fe74c9cf 2229{
02f3b3f5 2230 struct acpi_table_header *ivrs_base;
02f3b3f5 2231 acpi_status status;
3928aa3f 2232 int i, remap_cache_sz, ret = 0;
fe74c9cf 2233
643511b3 2234 if (!amd_iommu_detected)
8704a1ba
JR		 2235 return -ENODEV;
2236
6b11d1d6 2237 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2238 if (status == AE_NOT_FOUND)
2239 return -ENODEV;
2240 else if (ACPI_FAILURE(status)) {
2241 const char *err = acpi_format_exception(status);
2242 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2243 return -EINVAL;
2244 }
2245
8c7142f5
SS		 2246 /*
2247 * Validate checksum here so we don't need to do it when
2248 * we actually parse the table
2249 */
2250 ret = check_ivrs_checksum(ivrs_base);
2251 if (ret)
99e8ccd3 2252 goto out;
8c7142f5
SS		 2253
2254 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2255 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2256
fe74c9cf
JR		 2257 /*
2258 * First parse ACPI tables to find the largest Bus/Dev/Func
2259 * we need to handle. Upon this information the shared data
2260 * structures for the IOMMUs in the system will be allocated
2261 */
2c0ae172
JR		 2262 ret = find_last_devid_acpi(ivrs_base);
2263 if (ret)
3551a708
JR		 2264 goto out;
2265
c571484e
JR		 2266 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2267 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2268 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
fe74c9cf 2269
fe74c9cf 2270 /* Device table - directly used by all IOMMUs */
8704a1ba 2271 ret = -ENOMEM;
5dc8bff0 2272 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2273 get_order(dev_table_size));
2274 if (amd_iommu_dev_table == NULL)
2275 goto out;
2276
2277 /*
2278 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2279 * IOMMU see for that device
2280 */
2281 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2282 get_order(alias_table_size));
2283 if (amd_iommu_alias_table == NULL)
2c0ae172 2284 goto out;
fe74c9cf
JR		 2285
2286 /* IOMMU rlookup table - find the IOMMU for a specific device */
83fd5cc6
JR		 2287 amd_iommu_rlookup_table = (void *)__get_free_pages(
2288 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2289 get_order(rlookup_table_size));
2290 if (amd_iommu_rlookup_table == NULL)
2c0ae172 2291 goto out;
fe74c9cf 2292
5dc8bff0
JR		 2293 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2294 GFP_KERNEL | __GFP_ZERO,
fe74c9cf
JR		 2295 get_order(MAX_DOMAIN_ID/8));
2296 if (amd_iommu_pd_alloc_bitmap == NULL)
2c0ae172 2297 goto out;
fe74c9cf
JR		 2298
2299 /*
5dc8bff0 2300 * let all alias entries point to itself
fe74c9cf 2301 */
3a61ec38 2302 for (i = 0; i <= amd_iommu_last_bdf; ++i)
fe74c9cf
JR		 2303 amd_iommu_alias_table[i] = i;
2304
fe74c9cf
JR		 2305 /*
2306 * never allocate domain 0 because its used as the non-allocated and
2307 * error value placeholder
2308 */
5c87f62d 2309 __set_bit(0, amd_iommu_pd_alloc_bitmap);
fe74c9cf 2310
aeb26f55
JR		 2311 spin_lock_init(&amd_iommu_pd_lock);
2312
fe74c9cf
JR		 2313 /*
2314 * now the data structures are allocated and basically initialized
2315 * start the real acpi table scan
2316 */
02f3b3f5
JR		 2317 ret = init_iommu_all(ivrs_base);
2318 if (ret)
2c0ae172 2319 goto out;
fe74c9cf 2320
11123741
JR		 2321 /* Disable any previously enabled IOMMUs */
2322 disable_iommus();
2323
eb1eb7ae
JR		 2324 if (amd_iommu_irq_remap)
2325 amd_iommu_irq_remap = check_ioapic_information();
2326
05152a04
JR		 2327 if (amd_iommu_irq_remap) {
2328 /*
2329 * Interrupt remapping enabled, create kmem_cache for the
2330 * remapping tables.
2331 */
83ed9c13 2332 ret = -ENOMEM;
3928aa3f
SS		 2333 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2334 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2335 else
2336 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
05152a04 2337 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
3928aa3f
SS		 2338 remap_cache_sz,
2339 IRQ_TABLE_ALIGNMENT,
2340 0, NULL);
05152a04
JR		 2341 if (!amd_iommu_irq_cache)
2342 goto out;
0ea2c422
JR		 2343
2344 irq_lookup_table = (void *)__get_free_pages(
2345 GFP_KERNEL | __GFP_ZERO,
2346 get_order(rlookup_table_size));
ebcfa284
LS		 2347 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2348 1, GFP_KERNEL);
0ea2c422
JR		 2349 if (!irq_lookup_table)
2350 goto out;
05152a04
JR		 2351 }
2352
02f3b3f5
JR		 2353 ret = init_memory_definitions(ivrs_base);
2354 if (ret)
2c0ae172 2355 goto out;
3551a708 2356
eb1eb7ae
JR		 2357 /* init the device table */
2358 init_device_table();
2359
8704a1ba 2360out:
02f3b3f5 2361 /* Don't leak any ACPI memory */
6b11d1d6 2362 acpi_put_table(ivrs_base);
02f3b3f5
JR		 2363 ivrs_base = NULL;
2364
643511b3
JR		 2365 return ret;
2366}
2367
ae295142 2368static int amd_iommu_enable_interrupts(void)
3d9761e7
JR		 2369{
2370 struct amd_iommu *iommu;
2371 int ret = 0;
2372
2373 for_each_iommu(iommu) {
2374 ret = iommu_init_msi(iommu);
2375 if (ret)
2376 goto out;
2377 }
2378
2379out:
2380 return ret;
2381}
2382
02f3b3f5
JR		 2383static bool detect_ivrs(void)
2384{
2385 struct acpi_table_header *ivrs_base;
02f3b3f5
JR		 2386 acpi_status status;
2387
6b11d1d6 2388 status = acpi_get_table("IVRS", 0, &ivrs_base);
02f3b3f5
JR		 2389 if (status == AE_NOT_FOUND)
2390 return false;
2391 else if (ACPI_FAILURE(status)) {
2392 const char *err = acpi_format_exception(status);
2393 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2394 return false;
2395 }
2396
6b11d1d6 2397 acpi_put_table(ivrs_base);
02f3b3f5 2398
1adb7d31
JR		 2399 /* Make sure ACS will be enabled during PCI probe */
2400 pci_request_acs();
2401
02f3b3f5
JR		 2402 return true;
2403}
2404
2c0ae172 2405/****************************************************************************
8704a1ba 2406 *
2c0ae172
JR		 2407 * AMD IOMMU Initialization State Machine
2408 *
2409 ****************************************************************************/
2410
2411static int __init state_next(void)
8704a1ba
JR		 2412{
2413 int ret = 0;
2414
2c0ae172
JR		 2415 switch (init_state) {
2416 case IOMMU_START_STATE:
2417 if (!detect_ivrs()) {
2418 init_state = IOMMU_NOT_FOUND;
2419 ret = -ENODEV;
2420 } else {
2421 init_state = IOMMU_IVRS_DETECTED;
2422 }
2423 break;
2424 case IOMMU_IVRS_DETECTED:
2425 ret = early_amd_iommu_init();
2426 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2427 break;
2428 case IOMMU_ACPI_FINISHED:
2429 early_enable_iommus();
2430 register_syscore_ops(&amd_iommu_syscore_ops);
2431 x86_platform.iommu_shutdown = disable_iommus;
2432 init_state = IOMMU_ENABLED;
2433 break;
2434 case IOMMU_ENABLED:
2435 ret = amd_iommu_init_pci();
2436 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2437 enable_iommus_v2();
2438 break;
2439 case IOMMU_PCI_INIT:
2440 ret = amd_iommu_enable_interrupts();
2441 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2442 break;
2443 case IOMMU_INTERRUPTS_EN:
1e6a7b04 2444 ret = amd_iommu_init_dma_ops();
2c0ae172
JR		 2445 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2446 break;
2447 case IOMMU_DMA_OPS:
2448 init_state = IOMMU_INITIALIZED;
2449 break;
2450 case IOMMU_INITIALIZED:
2451 /* Nothing to do */
2452 break;
2453 case IOMMU_NOT_FOUND:
2454 case IOMMU_INIT_ERROR:
2455 /* Error states => do nothing */
2456 ret = -EINVAL;
2457 break;
2458 default:
2459 /* Unknown state */
2460 BUG();
2461 }
3d9761e7 2462
2c0ae172
JR		 2463 return ret;
2464}
7441e9cb 2465
2c0ae172
JR		 2466static int __init iommu_go_to_state(enum iommu_init_state state)
2467{
2468 int ret = 0;
f5325094 2469
2c0ae172
JR		 2470 while (init_state != state) {
2471 ret = state_next();
2472 if (init_state == IOMMU_NOT_FOUND ||
2473 init_state == IOMMU_INIT_ERROR)
2474 break;
2475 }
f2f12b6f 2476
fe74c9cf 2477 return ret;
2c0ae172 2478}
fe74c9cf 2479
6b474b82
JR		 2480#ifdef CONFIG_IRQ_REMAP
2481int __init amd_iommu_prepare(void)
2482{
3f4cb7c0
TG		 2483 int ret;
2484
7fa1c842 2485 amd_iommu_irq_remap = true;
84d07793 2486
3f4cb7c0
TG		 2487 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2488 if (ret)
2489 return ret;
2490 return amd_iommu_irq_remap ? 0 : -ENODEV;
6b474b82 2491}
d7f07769 2492
6b474b82
JR		 2493int __init amd_iommu_enable(void)
2494{
2495 int ret;
2496
2497 ret = iommu_go_to_state(IOMMU_ENABLED);
2498 if (ret)
2499 return ret;
d7f07769 2500
6b474b82 2501 irq_remapping_enabled = 1;
d7f07769 2502
6b474b82
JR		 2503 return 0;
2504}
2505
2506void amd_iommu_disable(void)
2507{
2508 amd_iommu_suspend();
2509}
2510
2511int amd_iommu_reenable(int mode)
2512{
2513 amd_iommu_resume();
2514
2515 return 0;
2516}
d7f07769 2517
6b474b82
JR		 2518int __init amd_iommu_enable_faulting(void)
2519{
2520 /* We enable MSI later when PCI is initialized */
2521 return 0;
2522}
2523#endif
d7f07769 2524
2c0ae172
JR		 2525/*
2526 * This is the core init function for AMD IOMMU hardware in the system.
2527 * This function is called from the generic x86 DMA layer initialization
2528 * code.
2529 */
2530static int __init amd_iommu_init(void)
2531{
2532 int ret;
2533
2534 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2535 if (ret) {
d04e0ba3
JR		 2536 free_dma_resources();
2537 if (!irq_remapping_enabled) {
2538 disable_iommus();
90b3eb03 2539 free_iommu_resources();
d04e0ba3
JR		 2540 } else {
2541 struct amd_iommu *iommu;
2542
2543 uninit_device_table_dma();
2544 for_each_iommu(iommu)
2545 iommu_flush_all_caches(iommu);
2546 }
2c0ae172
JR		 2547 }
2548
2549 return ret;
fe74c9cf
JR		 2550}
2551
b65233a9
JR		 2552/****************************************************************************
2553 *
2554 * Early detect code. This code runs at IOMMU detection time in the DMA
2555 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2556 * IOMMUs
2557 *
2558 ****************************************************************************/
480125ba 2559int __init amd_iommu_detect(void)
ae7877de 2560{
2c0ae172 2561 int ret;
02f3b3f5 2562
75f1cdf1 2563 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
480125ba 2564 return -ENODEV;
ae7877de 2565
a5235725 2566 if (amd_iommu_disabled)
480125ba 2567 return -ENODEV;
a5235725 2568
2c0ae172
JR		 2569 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2570 if (ret)
2571 return ret;
11bd04f6 2572
02f3b3f5
JR		 2573 amd_iommu_detected = true;
2574 iommu_detected = 1;
2575 x86_init.iommu.iommu_init = amd_iommu_init;
2576
4781bc42 2577 return 1;
ae7877de
JR		 2578}
2579
b65233a9
JR		 2580/****************************************************************************
2581 *
2582 * Parsing functions for the AMD IOMMU specific kernel command line
2583 * options.
2584 *
2585 ****************************************************************************/
2586
fefda117
JR		 2587static int __init parse_amd_iommu_dump(char *str)
2588{
2589 amd_iommu_dump = true;
2590
2591 return 1;
2592}
2593
3928aa3f
SS		 2594static int __init parse_amd_iommu_intr(char *str)
2595{
2596 for (; *str; ++str) {
2597 if (strncmp(str, "legacy", 6) == 0) {
2598 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2599 break;
2600 }
2601 if (strncmp(str, "vapic", 5) == 0) {
2602 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2603 break;
2604 }
2605 }
2606 return 1;
2607}
2608
918ad6c5
JR		 2609static int __init parse_amd_iommu_options(char *str)
2610{
2611 for (; *str; ++str) {
695b5676 2612 if (strncmp(str, "fullflush", 9) == 0)
afa9fdc2 2613 amd_iommu_unmap_flush = true;
a5235725
JR		 2614 if (strncmp(str, "off", 3) == 0)
2615 amd_iommu_disabled = true;
5abcdba4
JR		 2616 if (strncmp(str, "force_isolation", 15) == 0)
2617 amd_iommu_force_isolation = true;
918ad6c5
JR		 2618 }
2619
2620 return 1;
2621}
2622
440e8998
JR		 2623static int __init parse_ivrs_ioapic(char *str)
2624{
2625 unsigned int bus, dev, fn;
2626 int ret, id, i;
2627 u16 devid;
2628
2629 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2630
2631 if (ret != 4) {
2632 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2633 return 1;
2634 }
2635
2636 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2637 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2638 str);
2639 return 1;
2640 }
2641
2642 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2643
dfbb6d47 2644 cmdline_maps = true;
440e8998
JR		 2645 i = early_ioapic_map_size++;
2646 early_ioapic_map[i].id = id;
2647 early_ioapic_map[i].devid = devid;
2648 early_ioapic_map[i].cmd_line = true;
2649
2650 return 1;
2651}
2652
2653static int __init parse_ivrs_hpet(char *str)
2654{
2655 unsigned int bus, dev, fn;
2656 int ret, id, i;
2657 u16 devid;
2658
2659 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2660
2661 if (ret != 4) {
2662 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2663 return 1;
2664 }
2665
2666 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2667 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2668 str);
2669 return 1;
2670 }
2671
2672 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2673
dfbb6d47 2674 cmdline_maps = true;
440e8998
JR		 2675 i = early_hpet_map_size++;
2676 early_hpet_map[i].id = id;
2677 early_hpet_map[i].devid = devid;
2678 early_hpet_map[i].cmd_line = true;
2679
2680 return 1;
2681}
2682
ca3bf5d4
SS		 2683static int __init parse_ivrs_acpihid(char *str)
2684{
2685 u32 bus, dev, fn;
2686 char *hid, *uid, *p;
2687 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2688 int ret, i;
2689
2690 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2691 if (ret != 4) {
2692 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2693 return 1;
2694 }
2695
2696 p = acpiid;
2697 hid = strsep(&p, ":");
2698 uid = p;
2699
2700 if (!hid || !(*hid) || !uid) {
2701 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2702 return 1;
2703 }
2704
2705 i = early_acpihid_map_size++;
2706 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2707 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2708 early_acpihid_map[i].devid =
2709 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2710 early_acpihid_map[i].cmd_line = true;
2711
2712 return 1;
2713}
2714
440e8998
JR		 2715__setup("amd_iommu_dump", parse_amd_iommu_dump);
2716__setup("amd_iommu=", parse_amd_iommu_options);
3928aa3f 2717__setup("amd_iommu_intr=", parse_amd_iommu_intr);
440e8998
JR		 2718__setup("ivrs_ioapic", parse_ivrs_ioapic);
2719__setup("ivrs_hpet", parse_ivrs_hpet);
ca3bf5d4 2720__setup("ivrs_acpihid", parse_ivrs_acpihid);
22e6daf4
KRW		 2721
2722IOMMU_INIT_FINISH(amd_iommu_detect,
2723 gart_iommu_hole_init,
98f1ad25
JR		 2724 NULL,
2725 NULL);
400a28a0
JR		 2726
2727bool amd_iommu_v2_supported(void)
2728{
2729 return amd_iommu_v2_present;
2730}
2731EXPORT_SYMBOL(amd_iommu_v2_supported);
30861ddc 2732
f5863a00
SS		 2733struct amd_iommu *get_amd_iommu(unsigned int idx)
2734{
2735 unsigned int i = 0;
2736 struct amd_iommu *iommu;
2737
2738 for_each_iommu(iommu)
2739 if (i++ == idx)
2740 return iommu;
2741 return NULL;
2742}
2743EXPORT_SYMBOL(get_amd_iommu);
2744
30861ddc
SK		 2745/****************************************************************************
2746 *
2747 * IOMMU EFR Performance Counter support functionality. This code allows
2748 * access to the IOMMU PC functionality.
2749 *
2750 ****************************************************************************/
2751
f5863a00 2752u8 amd_iommu_pc_get_max_banks(unsigned int idx)
30861ddc 2753{
f5863a00 2754 struct amd_iommu *iommu = get_amd_iommu(idx);
30861ddc 2755
30861ddc 2756 if (iommu)
f5863a00 2757 return iommu->max_banks;
30861ddc 2758
f5863a00 2759 return 0;
30861ddc
SK		 2760}
2761EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2762
2763bool amd_iommu_pc_supported(void)
2764{
2765 return amd_iommu_pc_present;
2766}
2767EXPORT_SYMBOL(amd_iommu_pc_supported);
2768
f5863a00 2769u8 amd_iommu_pc_get_max_counters(unsigned int idx)
30861ddc 2770{
f5863a00 2771 struct amd_iommu *iommu = get_amd_iommu(idx);
30861ddc 2772
30861ddc 2773 if (iommu)
f5863a00 2774 return iommu->max_counters;
30861ddc 2775
f5863a00 2776 return 0;
30861ddc
SK		 2777}
2778EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2779
1650dfd1
SS		 2780static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2781 u8 fxn, u64 *value, bool is_write)
30861ddc 2782{
30861ddc
SK		 2783 u32 offset;
2784 u32 max_offset_lim;
2785
1650dfd1
SS		 2786 /* Make sure the IOMMU PC resource is available */
2787 if (!amd_iommu_pc_present)
2788 return -ENODEV;
2789
30861ddc 2790 /* Check for valid iommu and pc register indexing */
1650dfd1 2791 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
30861ddc
SK		 2792 return -ENODEV;
2793
0a6d80c7 2794 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
30861ddc
SK		 2795
2796 /* Limit the offset to the hw defined mmio region aperture */
0a6d80c7 2797 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
30861ddc
SK		 2798 (iommu->max_counters << 8) | 0x28);
2799 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2800 (offset > max_offset_lim))
2801 return -EINVAL;
2802
2803 if (is_write) {
0a6d80c7
SS		 2804 u64 val = *value & GENMASK_ULL(47, 0);
2805
2806 writel((u32)val, iommu->mmio_base + offset);
2807 writel((val >> 32), iommu->mmio_base + offset + 4);
30861ddc
SK		 2808 } else {
2809 *value = readl(iommu->mmio_base + offset + 4);
2810 *value <<= 32;
0a6d80c7
SS		 2811 *value |= readl(iommu->mmio_base + offset);
2812 *value &= GENMASK_ULL(47, 0);
30861ddc
SK		 2813 }
2814
2815 return 0;
2816}
38e45d02 2817
1650dfd1 2818int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
38e45d02 2819{
1650dfd1
SS		 2820 if (!iommu)
2821 return -EINVAL;
38e45d02 2822
1650dfd1
SS		 2823 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
2824}
2825EXPORT_SYMBOL(amd_iommu_pc_get_reg);
2826
2827int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2828{
2829 if (!iommu)
2830 return -EINVAL;
38e45d02 2831
1650dfd1 2832 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
38e45d02 2833}
1650dfd1 2834EXPORT_SYMBOL(amd_iommu_pc_set_reg);
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