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8d283c35 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
8d283c35 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1965aae3 PA |
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
22 | |
23 | #include <linux/types.h> | |
5d214fe6 | 24 | #include <linux/mutex.h> |
8d283c35 JR |
25 | #include <linux/list.h> |
26 | #include <linux/spinlock.h> | |
c5081cd7 | 27 | #include <linux/pci.h> |
4b180d97 | 28 | #include <linux/irqreturn.h> |
8d283c35 | 29 | |
bb52777e JR |
30 | /* |
31 | * Maximum number of IOMMUs supported | |
32 | */ | |
33 | #define MAX_IOMMUS 32 | |
34 | ||
8d283c35 JR |
35 | /* |
36 | * some size calculation constants | |
37 | */ | |
83f5aac1 | 38 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
39 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
40 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
41 | ||
8d283c35 JR |
42 | /* Capability offsets used by the driver */ |
43 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
44 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 45 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
46 | |
47 | /* Masks, shifts and macros to parse the device range capability */ | |
48 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
49 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
50 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
51 | #define MMIO_RANGE_LD_SHIFT 24 | |
52 | #define MMIO_RANGE_FD_SHIFT 16 | |
53 | #define MMIO_RANGE_BUS_SHIFT 8 | |
54 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
55 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
56 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 57 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
58 | |
59 | /* Flag masks for the AMD IOMMU exclusion range */ | |
60 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
61 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
62 | ||
63 | /* Used offsets into the MMIO space */ | |
64 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
65 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
66 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
67 | #define MMIO_CONTROL_OFFSET 0x0018 | |
68 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
69 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
d99ddec3 | 70 | #define MMIO_EXT_FEATURES 0x0030 |
1a29ac01 | 71 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
8d283c35 JR |
72 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
73 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
74 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
75 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
76 | #define MMIO_STATUS_OFFSET 0x2020 | |
1a29ac01 JR |
77 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
78 | #define MMIO_PPR_TAIL_OFFSET 0x2038 | |
30861ddc SK |
79 | #define MMIO_CNTR_CONF_OFFSET 0x4000 |
80 | #define MMIO_CNTR_REG_OFFSET 0x40000 | |
81 | #define MMIO_REG_END_OFFSET 0x80000 | |
82 | ||
8d283c35 | 83 | |
d99ddec3 JR |
84 | |
85 | /* Extended Feature Bits */ | |
86 | #define FEATURE_PREFETCH (1ULL<<0) | |
87 | #define FEATURE_PPR (1ULL<<1) | |
88 | #define FEATURE_X2APIC (1ULL<<2) | |
89 | #define FEATURE_NX (1ULL<<3) | |
90 | #define FEATURE_GT (1ULL<<4) | |
91 | #define FEATURE_IA (1ULL<<6) | |
92 | #define FEATURE_GA (1ULL<<7) | |
93 | #define FEATURE_HE (1ULL<<8) | |
94 | #define FEATURE_PC (1ULL<<9) | |
95 | ||
62f71abb JR |
96 | #define FEATURE_PASID_SHIFT 32 |
97 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) | |
98 | ||
52815b75 JR |
99 | #define FEATURE_GLXVAL_SHIFT 14 |
100 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) | |
101 | ||
a919a018 SS |
102 | /* Note: |
103 | * The current driver only support 16-bit PASID. | |
104 | * Currently, hardware only implement upto 16-bit PASID | |
105 | * even though the spec says it could have upto 20 bits. | |
106 | */ | |
107 | #define PASID_MASK 0x0000ffff | |
52815b75 | 108 | |
519c31ba | 109 | /* MMIO status bits */ |
925fe08b | 110 | #define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
72e1dcc4 JR |
111 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
112 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) | |
519c31ba | 113 | |
90008ee4 JR |
114 | /* event logging constants */ |
115 | #define EVENT_ENTRY_SIZE 0x10 | |
116 | #define EVENT_TYPE_SHIFT 28 | |
117 | #define EVENT_TYPE_MASK 0xf | |
118 | #define EVENT_TYPE_ILL_DEV 0x1 | |
119 | #define EVENT_TYPE_IO_FAULT 0x2 | |
120 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
121 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
122 | #define EVENT_TYPE_ILL_CMD 0x5 | |
123 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
124 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
125 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
126 | #define EVENT_DEVID_MASK 0xffff | |
127 | #define EVENT_DEVID_SHIFT 0 | |
128 | #define EVENT_DOMID_MASK 0xffff | |
129 | #define EVENT_DOMID_SHIFT 0 | |
130 | #define EVENT_FLAGS_MASK 0xfff | |
131 | #define EVENT_FLAGS_SHIFT 0x10 | |
132 | ||
8d283c35 JR |
133 | /* feature control bits */ |
134 | #define CONTROL_IOMMU_EN 0x00ULL | |
135 | #define CONTROL_HT_TUN_EN 0x01ULL | |
136 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
137 | #define CONTROL_EVT_INT_EN 0x03ULL | |
138 | #define CONTROL_COMWAIT_EN 0x04ULL | |
1456e9d2 | 139 | #define CONTROL_INV_TIMEOUT 0x05ULL |
8d283c35 JR |
140 | #define CONTROL_PASSPW_EN 0x08ULL |
141 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
142 | #define CONTROL_COHERENT_EN 0x0aULL | |
143 | #define CONTROL_ISOC_EN 0x0bULL | |
144 | #define CONTROL_CMDBUF_EN 0x0cULL | |
145 | #define CONTROL_PPFLOG_EN 0x0dULL | |
146 | #define CONTROL_PPFINT_EN 0x0eULL | |
1a29ac01 | 147 | #define CONTROL_PPR_EN 0x0fULL |
cbc33a90 | 148 | #define CONTROL_GT_EN 0x10ULL |
8d283c35 | 149 | |
1456e9d2 JR |
150 | #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
151 | #define CTRL_INV_TO_NONE 0 | |
152 | #define CTRL_INV_TO_1MS 1 | |
153 | #define CTRL_INV_TO_10MS 2 | |
154 | #define CTRL_INV_TO_100MS 3 | |
155 | #define CTRL_INV_TO_1S 4 | |
156 | #define CTRL_INV_TO_10S 5 | |
157 | #define CTRL_INV_TO_100S 6 | |
158 | ||
8d283c35 JR |
159 | /* command specific defines */ |
160 | #define CMD_COMPL_WAIT 0x01 | |
161 | #define CMD_INV_DEV_ENTRY 0x02 | |
cb41ed85 JR |
162 | #define CMD_INV_IOMMU_PAGES 0x03 |
163 | #define CMD_INV_IOTLB_PAGES 0x04 | |
7ef2798d | 164 | #define CMD_INV_IRT 0x05 |
c99afa25 | 165 | #define CMD_COMPLETE_PPR 0x07 |
58fc7f14 | 166 | #define CMD_INV_ALL 0x08 |
8d283c35 JR |
167 | |
168 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 169 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
170 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
171 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
22e266c7 | 172 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
8d283c35 | 173 | |
c99afa25 JR |
174 | #define PPR_STATUS_MASK 0xf |
175 | #define PPR_STATUS_SHIFT 12 | |
176 | ||
999ba417 JR |
177 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
178 | ||
8d283c35 JR |
179 | /* macros and definitions for device table entries */ |
180 | #define DEV_ENTRY_VALID 0x00 | |
181 | #define DEV_ENTRY_TRANSLATION 0x01 | |
182 | #define DEV_ENTRY_IR 0x3d | |
183 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 184 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
185 | #define DEV_ENTRY_EX 0x67 |
186 | #define DEV_ENTRY_SYSMGT1 0x68 | |
187 | #define DEV_ENTRY_SYSMGT2 0x69 | |
0ea2c422 | 188 | #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
8d283c35 JR |
189 | #define DEV_ENTRY_INIT_PASS 0xb8 |
190 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
191 | #define DEV_ENTRY_NMI_PASS 0xba | |
192 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
193 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
194 | #define DEV_ENTRY_MODE_MASK 0x07 |
195 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 | 196 | |
7ef2798d JR |
197 | #define MAX_DEV_TABLE_ENTRIES 0xffff |
198 | ||
8d283c35 JR |
199 | /* constants to configure the command buffer */ |
200 | #define CMD_BUFFER_SIZE 8192 | |
549c90dc | 201 | #define CMD_BUFFER_UNINITIALIZED 1 |
8d283c35 JR |
202 | #define CMD_BUFFER_ENTRIES 512 |
203 | #define MMIO_CMD_SIZE_SHIFT 56 | |
204 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
205 | ||
335503e5 JR |
206 | /* constants for event buffer handling */ |
207 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
208 | #define EVT_LEN_MASK (0x9ULL << 56) | |
209 | ||
1a29ac01 JR |
210 | /* Constants for PPR Log handling */ |
211 | #define PPR_LOG_ENTRIES 512 | |
212 | #define PPR_LOG_SIZE_SHIFT 56 | |
213 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) | |
214 | #define PPR_ENTRY_SIZE 16 | |
215 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) | |
216 | ||
72e1dcc4 JR |
217 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
218 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) | |
219 | #define PPR_DEVID(x) ((x) & 0xffffULL) | |
220 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) | |
221 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) | |
222 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) | |
223 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) | |
224 | ||
225 | #define PPR_REQ_FAULT 0x01 | |
226 | ||
0feae533 | 227 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
228 | #define PAGE_MODE_1_LEVEL 0x01 |
229 | #define PAGE_MODE_2_LEVEL 0x02 | |
230 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
231 | #define PAGE_MODE_4_LEVEL 0x04 |
232 | #define PAGE_MODE_5_LEVEL 0x05 | |
233 | #define PAGE_MODE_6_LEVEL 0x06 | |
8d283c35 | 234 | |
9355a081 JR |
235 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
236 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
237 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
238 | (0xffffffffffffffffULL)) | |
239 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
240 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
241 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
242 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) | |
a6b256b4 | 243 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 244 | |
abdc5eb3 JR |
245 | #define PM_MAP_4k 0 |
246 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
247 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
248 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
249 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 | 250 | |
cbb9d729 JR |
251 | /* |
252 | * Returns the page table level to use for a given page size | |
253 | * Pagesize is expected to be a power-of-two | |
254 | */ | |
255 | #define PAGE_SIZE_LEVEL(pagesize) \ | |
256 | ((__ffs(pagesize) - 12) / 9) | |
257 | /* | |
258 | * Returns the number of ptes to use for a given page size | |
259 | * Pagesize is expected to be a power-of-two | |
260 | */ | |
261 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | |
262 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | |
263 | ||
264 | /* | |
265 | * Aligns a given io-virtual address to a given page size | |
266 | * Pagesize is expected to be a power-of-two | |
267 | */ | |
268 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | |
269 | ((address) & ~((pagesize) - 1)) | |
270 | /* | |
df805abb | 271 | * Creates an IOMMU PTE for an address and a given pagesize |
cbb9d729 JR |
272 | * The PTE has no permission bits set |
273 | * Pagesize is expected to be a power-of-two larger than 4096 | |
274 | */ | |
275 | #define PAGE_SIZE_PTE(address, pagesize) \ | |
276 | (((address) | ((pagesize) - 1)) & \ | |
277 | (~(pagesize >> 1)) & PM_ADDR_MASK) | |
278 | ||
24cd7723 JR |
279 | /* |
280 | * Takes a PTE value with mode=0x07 and returns the page size it maps | |
281 | */ | |
282 | #define PTE_PAGE_SIZE(pte) \ | |
283 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | |
284 | ||
3039ca1b JR |
285 | /* |
286 | * Takes a page-table level and returns the default page-size for this level | |
287 | */ | |
288 | #define PTE_LEVEL_PAGE_SIZE(level) \ | |
289 | (1ULL << (12 + (9 * (level)))) | |
290 | ||
8d283c35 | 291 | #define IOMMU_PTE_P (1ULL << 0) |
38ddf41b | 292 | #define IOMMU_PTE_TV (1ULL << 1) |
8d283c35 JR |
293 | #define IOMMU_PTE_U (1ULL << 59) |
294 | #define IOMMU_PTE_FC (1ULL << 60) | |
295 | #define IOMMU_PTE_IR (1ULL << 61) | |
296 | #define IOMMU_PTE_IW (1ULL << 62) | |
297 | ||
ca9cab3a JR |
298 | #define DTE_FLAG_IOTLB (1ULL << 32) |
299 | #define DTE_FLAG_GV (1ULL << 55) | |
cbf3ccd0 | 300 | #define DTE_FLAG_MASK (0x3ffULL << 32) |
52815b75 JR |
301 | #define DTE_GLX_SHIFT (56) |
302 | #define DTE_GLX_MASK (3) | |
303 | ||
304 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) | |
305 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) | |
306 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) | |
307 | ||
308 | #define DTE_GCR3_INDEX_A 0 | |
309 | #define DTE_GCR3_INDEX_B 1 | |
310 | #define DTE_GCR3_INDEX_C 1 | |
311 | ||
312 | #define DTE_GCR3_SHIFT_A 58 | |
313 | #define DTE_GCR3_SHIFT_B 16 | |
314 | #define DTE_GCR3_SHIFT_C 43 | |
315 | ||
b16137b1 | 316 | #define GCR3_VALID 0x01ULL |
fd7b5535 | 317 | |
8d283c35 JR |
318 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
319 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) | |
320 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) | |
321 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) | |
322 | ||
323 | #define IOMMU_PROT_MASK 0x03 | |
324 | #define IOMMU_PROT_IR 0x01 | |
325 | #define IOMMU_PROT_IW 0x02 | |
326 | ||
327 | /* IOMMU capabilities */ | |
328 | #define IOMMU_CAP_IOTLB 24 | |
329 | #define IOMMU_CAP_NPCACHE 26 | |
d99ddec3 | 330 | #define IOMMU_CAP_EFR 27 |
8d283c35 JR |
331 | |
332 | #define MAX_DOMAIN_ID 65536 | |
333 | ||
9fdb19d6 JR |
334 | /* Protection domain flags */ |
335 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
336 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
337 | domain for an IOMMU */ | |
0feae533 JR |
338 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
339 | translation */ | |
52815b75 | 340 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
0feae533 | 341 | |
fefda117 JR |
342 | extern bool amd_iommu_dump; |
343 | #define DUMP_printk(format, arg...) \ | |
344 | do { \ | |
345 | if (amd_iommu_dump) \ | |
4c6f40d4 | 346 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 347 | } while(0); |
9fdb19d6 | 348 | |
318afd41 JR |
349 | /* global flag if IOMMUs cache non-present entries */ |
350 | extern bool amd_iommu_np_cache; | |
60f723b4 JR |
351 | /* Only true if all IOMMUs support device IOTLBs */ |
352 | extern bool amd_iommu_iotlb_sup; | |
318afd41 | 353 | |
05152a04 JR |
354 | #define MAX_IRQS_PER_TABLE 256 |
355 | #define IRQ_TABLE_ALIGNMENT 128 | |
356 | ||
0ea2c422 JR |
357 | struct irq_remap_table { |
358 | spinlock_t lock; | |
359 | unsigned min_index; | |
360 | u32 *table; | |
361 | }; | |
362 | ||
363 | extern struct irq_remap_table **irq_lookup_table; | |
364 | ||
05152a04 JR |
365 | /* Interrupt remapping feature used? */ |
366 | extern bool amd_iommu_irq_remap; | |
367 | ||
368 | /* kmem_cache to get tables with 128 byte alignement */ | |
369 | extern struct kmem_cache *amd_iommu_irq_cache; | |
370 | ||
3bd22172 JR |
371 | /* |
372 | * Make iterating over all IOMMUs easier | |
373 | */ | |
374 | #define for_each_iommu(iommu) \ | |
375 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
376 | #define for_each_iommu_safe(iommu, next) \ | |
377 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
378 | ||
384de729 JR |
379 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
380 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
381 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
382 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
383 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
384 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 385 | |
72e1dcc4 JR |
386 | |
387 | /* | |
388 | * This struct is used to pass information about | |
389 | * incoming PPR faults around. | |
390 | */ | |
391 | struct amd_iommu_fault { | |
392 | u64 address; /* IO virtual address of the fault*/ | |
393 | u32 pasid; /* Address space identifier */ | |
394 | u16 device_id; /* Originating PCI device id */ | |
395 | u16 tag; /* PPR tag */ | |
396 | u16 flags; /* Fault flags */ | |
397 | ||
398 | }; | |
399 | ||
72e1dcc4 | 400 | |
f3572db8 | 401 | struct iommu_domain; |
7c71d306 | 402 | struct irq_domain; |
f3572db8 | 403 | |
5694703f JR |
404 | /* |
405 | * This structure contains generic data for IOMMU protection domains | |
406 | * independent of their use. | |
407 | */ | |
8d283c35 | 408 | struct protection_domain { |
aeb26f55 | 409 | struct list_head list; /* for list of all protection domains */ |
7c392cbe | 410 | struct list_head dev_list; /* List of all devices in this domain */ |
3f4b87b9 JR |
411 | struct iommu_domain domain; /* generic domain handle used by |
412 | iommu core code */ | |
9fdb19d6 | 413 | spinlock_t lock; /* mostly used to lock the page table*/ |
5d214fe6 | 414 | struct mutex api_lock; /* protect page tables in the iommu-api path */ |
9fdb19d6 JR |
415 | u16 id; /* the domain id written to the device table */ |
416 | int mode; /* paging mode (0-6 levels) */ | |
417 | u64 *pt_root; /* page table root pointer */ | |
52815b75 JR |
418 | int glx; /* Number of levels for GCR3 table */ |
419 | u64 *gcr3_tbl; /* Guest CR3 table */ | |
9fdb19d6 | 420 | unsigned long flags; /* flags to find out type of domain */ |
04bfdd84 | 421 | bool updated; /* complete domain flush required */ |
863c74eb | 422 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 423 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
3f4b87b9 | 424 | void *priv; /* private data */ |
8d283c35 JR |
425 | }; |
426 | ||
5694703f JR |
427 | /* |
428 | * Structure where we save information about one hardware AMD IOMMU in the | |
429 | * system. | |
430 | */ | |
8d283c35 JR |
431 | struct amd_iommu { |
432 | struct list_head list; | |
5694703f | 433 | |
bb52777e JR |
434 | /* Index within the IOMMU array */ |
435 | int index; | |
436 | ||
5694703f | 437 | /* locks the accesses to the hardware */ |
8d283c35 JR |
438 | spinlock_t lock; |
439 | ||
3eaf28a1 JR |
440 | /* Pointer to PCI device of this IOMMU */ |
441 | struct pci_dev *dev; | |
442 | ||
c1bf94ec JR |
443 | /* Cache pdev to root device for resume quirks */ |
444 | struct pci_dev *root_pdev; | |
445 | ||
5694703f | 446 | /* physical address of MMIO space */ |
8d283c35 | 447 | u64 mmio_phys; |
30861ddc SK |
448 | |
449 | /* physical end address of MMIO space */ | |
450 | u64 mmio_phys_end; | |
451 | ||
5694703f | 452 | /* virtual address of MMIO space */ |
98f1ad25 | 453 | u8 __iomem *mmio_base; |
5694703f JR |
454 | |
455 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 456 | u32 cap; |
5694703f | 457 | |
e9bf5197 JR |
458 | /* flags read from acpi table */ |
459 | u8 acpi_flags; | |
460 | ||
d99ddec3 JR |
461 | /* Extended features */ |
462 | u64 features; | |
463 | ||
400a28a0 JR |
464 | /* IOMMUv2 */ |
465 | bool is_iommu_v2; | |
466 | ||
23c742db JR |
467 | /* PCI device id of the IOMMU device */ |
468 | u16 devid; | |
469 | ||
eac9fbc6 RK |
470 | /* |
471 | * Capability pointer. There could be more than one IOMMU per PCI | |
472 | * device function if there are more than one AMD IOMMU capability | |
473 | * pointers. | |
474 | */ | |
475 | u16 cap_ptr; | |
476 | ||
ee893c24 JR |
477 | /* pci domain of this IOMMU */ |
478 | u16 pci_seg; | |
479 | ||
5694703f | 480 | /* start of exclusion range of that IOMMU */ |
8d283c35 | 481 | u64 exclusion_start; |
5694703f | 482 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
483 | u64 exclusion_length; |
484 | ||
5694703f | 485 | /* command buffer virtual address */ |
8d283c35 | 486 | u8 *cmd_buf; |
8d283c35 | 487 | |
eac9fbc6 RK |
488 | /* event buffer virtual address */ |
489 | u8 *evt_buf; | |
335503e5 | 490 | |
1a29ac01 JR |
491 | /* Base of the PPR log, if present */ |
492 | u8 *ppr_log; | |
493 | ||
a80dc3e0 JR |
494 | /* true if interrupts for this IOMMU are already enabled */ |
495 | bool int_enabled; | |
496 | ||
eac9fbc6 | 497 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 498 | bool need_sync; |
eac9fbc6 | 499 | |
066f2e98 AW |
500 | /* IOMMU sysfs device */ |
501 | struct device *iommu_dev; | |
502 | ||
4c894f47 | 503 | /* |
5bcd757f MG |
504 | * We can't rely on the BIOS to restore all values on reinit, so we |
505 | * need to stash them | |
4c894f47 | 506 | */ |
5bcd757f MG |
507 | |
508 | /* The iommu BAR */ | |
509 | u32 stored_addr_lo; | |
510 | u32 stored_addr_hi; | |
511 | ||
512 | /* | |
513 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | |
514 | * registers | |
515 | */ | |
516 | u32 stored_l1[6][0x12]; | |
517 | ||
518 | /* The l2 indirect registers */ | |
519 | u32 stored_l2[0x83]; | |
30861ddc SK |
520 | |
521 | /* The maximum PC banks and counters/bank (PCSup=1) */ | |
522 | u8 max_banks; | |
523 | u8 max_counters; | |
7c71d306 JL |
524 | #ifdef CONFIG_IRQ_REMAP |
525 | struct irq_domain *ir_domain; | |
526 | struct irq_domain *msi_domain; | |
527 | #endif | |
8d283c35 JR |
528 | }; |
529 | ||
2a0cb4e2 WZ |
530 | #define ACPIHID_UID_LEN 256 |
531 | #define ACPIHID_HID_LEN 9 | |
532 | ||
533 | struct acpihid_map_entry { | |
534 | struct list_head list; | |
535 | u8 uid[ACPIHID_UID_LEN]; | |
536 | u8 hid[ACPIHID_HID_LEN]; | |
537 | u16 devid; | |
538 | u16 root_devid; | |
539 | bool cmd_line; | |
540 | struct iommu_group *group; | |
541 | }; | |
542 | ||
6efed63b JR |
543 | struct devid_map { |
544 | struct list_head list; | |
545 | u8 id; | |
546 | u16 devid; | |
31cff67f | 547 | bool cmd_line; |
6efed63b JR |
548 | }; |
549 | ||
550 | /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ | |
551 | extern struct list_head ioapic_map; | |
552 | extern struct list_head hpet_map; | |
2a0cb4e2 | 553 | extern struct list_head acpihid_map; |
6efed63b | 554 | |
5694703f JR |
555 | /* |
556 | * List with all IOMMUs in the system. This list is not locked because it is | |
557 | * only written and read at driver initialization or suspend time | |
558 | */ | |
8d283c35 JR |
559 | extern struct list_head amd_iommu_list; |
560 | ||
bb52777e JR |
561 | /* |
562 | * Array with pointers to each IOMMU struct | |
563 | * The indices are referenced in the protection domains | |
564 | */ | |
565 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
566 | ||
567 | /* Number of IOMMUs present in the system */ | |
568 | extern int amd_iommus_present; | |
569 | ||
aeb26f55 JR |
570 | /* |
571 | * Declarations for the global list of all protection domains | |
572 | */ | |
573 | extern spinlock_t amd_iommu_pd_lock; | |
574 | extern struct list_head amd_iommu_pd_list; | |
575 | ||
5694703f JR |
576 | /* |
577 | * Structure defining one entry in the device table | |
578 | */ | |
8d283c35 | 579 | struct dev_table_entry { |
ee6c2868 | 580 | u64 data[4]; |
8d283c35 JR |
581 | }; |
582 | ||
5694703f JR |
583 | /* |
584 | * One entry for unity mappings parsed out of the ACPI table. | |
585 | */ | |
8d283c35 JR |
586 | struct unity_map_entry { |
587 | struct list_head list; | |
5694703f JR |
588 | |
589 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 590 | u16 devid_start; |
5694703f | 591 | /* end device id this entry is used for (including) */ |
8d283c35 | 592 | u16 devid_end; |
5694703f JR |
593 | |
594 | /* start address to unity map (including) */ | |
8d283c35 | 595 | u64 address_start; |
5694703f | 596 | /* end address to unity map (including) */ |
8d283c35 | 597 | u64 address_end; |
5694703f JR |
598 | |
599 | /* required protection */ | |
8d283c35 JR |
600 | int prot; |
601 | }; | |
602 | ||
5694703f JR |
603 | /* |
604 | * List of all unity mappings. It is not locked because as runtime it is only | |
605 | * read. It is created at ACPI table parsing time. | |
606 | */ | |
8d283c35 JR |
607 | extern struct list_head amd_iommu_unity_map; |
608 | ||
5694703f JR |
609 | /* |
610 | * Data structures for device handling | |
611 | */ | |
612 | ||
613 | /* | |
614 | * Device table used by hardware. Read and write accesses by software are | |
615 | * locked with the amd_iommu_pd_table lock. | |
616 | */ | |
8d283c35 | 617 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
618 | |
619 | /* | |
620 | * Alias table to find requestor ids to device ids. Not locked because only | |
621 | * read on runtime. | |
622 | */ | |
8d283c35 | 623 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
624 | |
625 | /* | |
626 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
627 | */ | |
8d283c35 JR |
628 | extern struct amd_iommu **amd_iommu_rlookup_table; |
629 | ||
5694703f | 630 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
631 | extern unsigned amd_iommu_aperture_order; |
632 | ||
5694703f | 633 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
634 | extern u16 amd_iommu_last_bdf; |
635 | ||
5694703f | 636 | /* allocation bitmap for domain ids */ |
8d283c35 JR |
637 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
638 | ||
afa9fdc2 FT |
639 | /* |
640 | * If true, the addresses will be flushed on unmap time, not when | |
641 | * they are reused | |
642 | */ | |
621a5f7a | 643 | extern bool amd_iommu_unmap_flush; |
afa9fdc2 | 644 | |
a919a018 SS |
645 | /* Smallest max PASID supported by any IOMMU in the system */ |
646 | extern u32 amd_iommu_max_pasid; | |
62f71abb | 647 | |
400a28a0 JR |
648 | extern bool amd_iommu_v2_present; |
649 | ||
5abcdba4 JR |
650 | extern bool amd_iommu_force_isolation; |
651 | ||
52815b75 JR |
652 | /* Max levels of glxval supported */ |
653 | extern int amd_iommu_max_glx_val; | |
654 | ||
98f1ad25 JR |
655 | /* |
656 | * This function flushes all internal caches of | |
657 | * the IOMMU used by this driver. | |
658 | */ | |
659 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
660 | ||
6efed63b JR |
661 | static inline int get_ioapic_devid(int id) |
662 | { | |
663 | struct devid_map *entry; | |
664 | ||
665 | list_for_each_entry(entry, &ioapic_map, list) { | |
666 | if (entry->id == id) | |
667 | return entry->devid; | |
668 | } | |
669 | ||
670 | return -EINVAL; | |
671 | } | |
672 | ||
673 | static inline int get_hpet_devid(int id) | |
674 | { | |
675 | struct devid_map *entry; | |
676 | ||
677 | list_for_each_entry(entry, &hpet_map, list) { | |
678 | if (entry->id == id) | |
679 | return entry->devid; | |
680 | } | |
681 | ||
682 | return -EINVAL; | |
683 | } | |
684 | ||
1965aae3 | 685 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |