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8d283c35 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
63ce3ae8 | 3 | * Author: Joerg Roedel <jroedel@suse.de> |
8d283c35 JR |
4 | * Leo Duran <leo.duran@amd.com> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1965aae3 PA |
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
22 | |
23 | #include <linux/types.h> | |
5d214fe6 | 24 | #include <linux/mutex.h> |
a38180bd | 25 | #include <linux/msi.h> |
8d283c35 JR |
26 | #include <linux/list.h> |
27 | #include <linux/spinlock.h> | |
c5081cd7 | 28 | #include <linux/pci.h> |
4b180d97 | 29 | #include <linux/irqreturn.h> |
8d283c35 | 30 | |
bb52777e JR |
31 | /* |
32 | * Maximum number of IOMMUs supported | |
33 | */ | |
34 | #define MAX_IOMMUS 32 | |
35 | ||
8d283c35 JR |
36 | /* |
37 | * some size calculation constants | |
38 | */ | |
83f5aac1 | 39 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
40 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
41 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
42 | ||
8d283c35 JR |
43 | /* Capability offsets used by the driver */ |
44 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
45 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 46 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
47 | |
48 | /* Masks, shifts and macros to parse the device range capability */ | |
49 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
50 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
51 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
52 | #define MMIO_RANGE_LD_SHIFT 24 | |
53 | #define MMIO_RANGE_FD_SHIFT 16 | |
54 | #define MMIO_RANGE_BUS_SHIFT 8 | |
55 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
56 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
57 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 58 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
59 | |
60 | /* Flag masks for the AMD IOMMU exclusion range */ | |
61 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
62 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
63 | ||
64 | /* Used offsets into the MMIO space */ | |
65 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
66 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
67 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
68 | #define MMIO_CONTROL_OFFSET 0x0018 | |
69 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
70 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
d99ddec3 | 71 | #define MMIO_EXT_FEATURES 0x0030 |
1a29ac01 | 72 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
8d283c35 JR |
73 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
74 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
75 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
76 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
77 | #define MMIO_STATUS_OFFSET 0x2020 | |
1a29ac01 JR |
78 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
79 | #define MMIO_PPR_TAIL_OFFSET 0x2038 | |
30861ddc SK |
80 | #define MMIO_CNTR_CONF_OFFSET 0x4000 |
81 | #define MMIO_CNTR_REG_OFFSET 0x40000 | |
82 | #define MMIO_REG_END_OFFSET 0x80000 | |
83 | ||
8d283c35 | 84 | |
d99ddec3 JR |
85 | |
86 | /* Extended Feature Bits */ | |
87 | #define FEATURE_PREFETCH (1ULL<<0) | |
88 | #define FEATURE_PPR (1ULL<<1) | |
89 | #define FEATURE_X2APIC (1ULL<<2) | |
90 | #define FEATURE_NX (1ULL<<3) | |
91 | #define FEATURE_GT (1ULL<<4) | |
92 | #define FEATURE_IA (1ULL<<6) | |
93 | #define FEATURE_GA (1ULL<<7) | |
94 | #define FEATURE_HE (1ULL<<8) | |
95 | #define FEATURE_PC (1ULL<<9) | |
3928aa3f | 96 | #define FEATURE_GAM_VAPIC (1ULL<<21) |
d99ddec3 | 97 | |
62f71abb JR |
98 | #define FEATURE_PASID_SHIFT 32 |
99 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) | |
100 | ||
52815b75 JR |
101 | #define FEATURE_GLXVAL_SHIFT 14 |
102 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) | |
103 | ||
a919a018 SS |
104 | /* Note: |
105 | * The current driver only support 16-bit PASID. | |
106 | * Currently, hardware only implement upto 16-bit PASID | |
107 | * even though the spec says it could have upto 20 bits. | |
108 | */ | |
109 | #define PASID_MASK 0x0000ffff | |
52815b75 | 110 | |
519c31ba | 111 | /* MMIO status bits */ |
925fe08b | 112 | #define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
72e1dcc4 JR |
113 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
114 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) | |
519c31ba | 115 | |
90008ee4 JR |
116 | /* event logging constants */ |
117 | #define EVENT_ENTRY_SIZE 0x10 | |
118 | #define EVENT_TYPE_SHIFT 28 | |
119 | #define EVENT_TYPE_MASK 0xf | |
120 | #define EVENT_TYPE_ILL_DEV 0x1 | |
121 | #define EVENT_TYPE_IO_FAULT 0x2 | |
122 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
123 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
124 | #define EVENT_TYPE_ILL_CMD 0x5 | |
125 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
126 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
127 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
128 | #define EVENT_DEVID_MASK 0xffff | |
129 | #define EVENT_DEVID_SHIFT 0 | |
130 | #define EVENT_DOMID_MASK 0xffff | |
131 | #define EVENT_DOMID_SHIFT 0 | |
132 | #define EVENT_FLAGS_MASK 0xfff | |
133 | #define EVENT_FLAGS_SHIFT 0x10 | |
134 | ||
8d283c35 JR |
135 | /* feature control bits */ |
136 | #define CONTROL_IOMMU_EN 0x00ULL | |
137 | #define CONTROL_HT_TUN_EN 0x01ULL | |
138 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
139 | #define CONTROL_EVT_INT_EN 0x03ULL | |
140 | #define CONTROL_COMWAIT_EN 0x04ULL | |
1456e9d2 | 141 | #define CONTROL_INV_TIMEOUT 0x05ULL |
8d283c35 JR |
142 | #define CONTROL_PASSPW_EN 0x08ULL |
143 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
144 | #define CONTROL_COHERENT_EN 0x0aULL | |
145 | #define CONTROL_ISOC_EN 0x0bULL | |
146 | #define CONTROL_CMDBUF_EN 0x0cULL | |
147 | #define CONTROL_PPFLOG_EN 0x0dULL | |
148 | #define CONTROL_PPFINT_EN 0x0eULL | |
1a29ac01 | 149 | #define CONTROL_PPR_EN 0x0fULL |
cbc33a90 | 150 | #define CONTROL_GT_EN 0x10ULL |
3928aa3f SS |
151 | #define CONTROL_GA_EN 0x11ULL |
152 | #define CONTROL_GAM_EN 0x19ULL | |
8d283c35 | 153 | |
1456e9d2 JR |
154 | #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
155 | #define CTRL_INV_TO_NONE 0 | |
156 | #define CTRL_INV_TO_1MS 1 | |
157 | #define CTRL_INV_TO_10MS 2 | |
158 | #define CTRL_INV_TO_100MS 3 | |
159 | #define CTRL_INV_TO_1S 4 | |
160 | #define CTRL_INV_TO_10S 5 | |
161 | #define CTRL_INV_TO_100S 6 | |
162 | ||
8d283c35 JR |
163 | /* command specific defines */ |
164 | #define CMD_COMPL_WAIT 0x01 | |
165 | #define CMD_INV_DEV_ENTRY 0x02 | |
cb41ed85 JR |
166 | #define CMD_INV_IOMMU_PAGES 0x03 |
167 | #define CMD_INV_IOTLB_PAGES 0x04 | |
7ef2798d | 168 | #define CMD_INV_IRT 0x05 |
c99afa25 | 169 | #define CMD_COMPLETE_PPR 0x07 |
58fc7f14 | 170 | #define CMD_INV_ALL 0x08 |
8d283c35 JR |
171 | |
172 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 173 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
174 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
175 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
22e266c7 | 176 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
8d283c35 | 177 | |
c99afa25 JR |
178 | #define PPR_STATUS_MASK 0xf |
179 | #define PPR_STATUS_SHIFT 12 | |
180 | ||
999ba417 JR |
181 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
182 | ||
8d283c35 JR |
183 | /* macros and definitions for device table entries */ |
184 | #define DEV_ENTRY_VALID 0x00 | |
185 | #define DEV_ENTRY_TRANSLATION 0x01 | |
186 | #define DEV_ENTRY_IR 0x3d | |
187 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 188 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
189 | #define DEV_ENTRY_EX 0x67 |
190 | #define DEV_ENTRY_SYSMGT1 0x68 | |
191 | #define DEV_ENTRY_SYSMGT2 0x69 | |
0ea2c422 | 192 | #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
8d283c35 JR |
193 | #define DEV_ENTRY_INIT_PASS 0xb8 |
194 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
195 | #define DEV_ENTRY_NMI_PASS 0xba | |
196 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
197 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
198 | #define DEV_ENTRY_MODE_MASK 0x07 |
199 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 | 200 | |
7ef2798d JR |
201 | #define MAX_DEV_TABLE_ENTRIES 0xffff |
202 | ||
8d283c35 JR |
203 | /* constants to configure the command buffer */ |
204 | #define CMD_BUFFER_SIZE 8192 | |
549c90dc | 205 | #define CMD_BUFFER_UNINITIALIZED 1 |
8d283c35 JR |
206 | #define CMD_BUFFER_ENTRIES 512 |
207 | #define MMIO_CMD_SIZE_SHIFT 56 | |
208 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
209 | ||
335503e5 JR |
210 | /* constants for event buffer handling */ |
211 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
212 | #define EVT_LEN_MASK (0x9ULL << 56) | |
213 | ||
1a29ac01 JR |
214 | /* Constants for PPR Log handling */ |
215 | #define PPR_LOG_ENTRIES 512 | |
216 | #define PPR_LOG_SIZE_SHIFT 56 | |
217 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) | |
218 | #define PPR_ENTRY_SIZE 16 | |
219 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) | |
220 | ||
72e1dcc4 JR |
221 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
222 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) | |
223 | #define PPR_DEVID(x) ((x) & 0xffffULL) | |
224 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) | |
225 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) | |
226 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) | |
227 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) | |
228 | ||
229 | #define PPR_REQ_FAULT 0x01 | |
230 | ||
0feae533 | 231 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
232 | #define PAGE_MODE_1_LEVEL 0x01 |
233 | #define PAGE_MODE_2_LEVEL 0x02 | |
234 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
235 | #define PAGE_MODE_4_LEVEL 0x04 |
236 | #define PAGE_MODE_5_LEVEL 0x05 | |
237 | #define PAGE_MODE_6_LEVEL 0x06 | |
8d283c35 | 238 | |
9355a081 JR |
239 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
240 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
241 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
242 | (0xffffffffffffffffULL)) | |
243 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
244 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
245 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
246 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) | |
a6b256b4 | 247 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 248 | |
abdc5eb3 JR |
249 | #define PM_MAP_4k 0 |
250 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
251 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
252 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
253 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 | 254 | |
cbb9d729 JR |
255 | /* |
256 | * Returns the page table level to use for a given page size | |
257 | * Pagesize is expected to be a power-of-two | |
258 | */ | |
259 | #define PAGE_SIZE_LEVEL(pagesize) \ | |
260 | ((__ffs(pagesize) - 12) / 9) | |
261 | /* | |
262 | * Returns the number of ptes to use for a given page size | |
263 | * Pagesize is expected to be a power-of-two | |
264 | */ | |
265 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | |
266 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | |
267 | ||
268 | /* | |
269 | * Aligns a given io-virtual address to a given page size | |
270 | * Pagesize is expected to be a power-of-two | |
271 | */ | |
272 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | |
273 | ((address) & ~((pagesize) - 1)) | |
274 | /* | |
df805abb | 275 | * Creates an IOMMU PTE for an address and a given pagesize |
cbb9d729 JR |
276 | * The PTE has no permission bits set |
277 | * Pagesize is expected to be a power-of-two larger than 4096 | |
278 | */ | |
279 | #define PAGE_SIZE_PTE(address, pagesize) \ | |
280 | (((address) | ((pagesize) - 1)) & \ | |
281 | (~(pagesize >> 1)) & PM_ADDR_MASK) | |
282 | ||
24cd7723 JR |
283 | /* |
284 | * Takes a PTE value with mode=0x07 and returns the page size it maps | |
285 | */ | |
286 | #define PTE_PAGE_SIZE(pte) \ | |
287 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | |
288 | ||
3039ca1b JR |
289 | /* |
290 | * Takes a page-table level and returns the default page-size for this level | |
291 | */ | |
292 | #define PTE_LEVEL_PAGE_SIZE(level) \ | |
293 | (1ULL << (12 + (9 * (level)))) | |
294 | ||
8d283c35 | 295 | #define IOMMU_PTE_P (1ULL << 0) |
38ddf41b | 296 | #define IOMMU_PTE_TV (1ULL << 1) |
8d283c35 JR |
297 | #define IOMMU_PTE_U (1ULL << 59) |
298 | #define IOMMU_PTE_FC (1ULL << 60) | |
299 | #define IOMMU_PTE_IR (1ULL << 61) | |
300 | #define IOMMU_PTE_IW (1ULL << 62) | |
301 | ||
ca9cab3a JR |
302 | #define DTE_FLAG_IOTLB (1ULL << 32) |
303 | #define DTE_FLAG_GV (1ULL << 55) | |
cbf3ccd0 | 304 | #define DTE_FLAG_MASK (0x3ffULL << 32) |
52815b75 JR |
305 | #define DTE_GLX_SHIFT (56) |
306 | #define DTE_GLX_MASK (3) | |
307 | ||
308 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) | |
309 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) | |
310 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) | |
311 | ||
312 | #define DTE_GCR3_INDEX_A 0 | |
313 | #define DTE_GCR3_INDEX_B 1 | |
314 | #define DTE_GCR3_INDEX_C 1 | |
315 | ||
316 | #define DTE_GCR3_SHIFT_A 58 | |
317 | #define DTE_GCR3_SHIFT_B 16 | |
318 | #define DTE_GCR3_SHIFT_C 43 | |
319 | ||
b16137b1 | 320 | #define GCR3_VALID 0x01ULL |
fd7b5535 | 321 | |
8d283c35 JR |
322 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
323 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) | |
324 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) | |
325 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) | |
326 | ||
327 | #define IOMMU_PROT_MASK 0x03 | |
328 | #define IOMMU_PROT_IR 0x01 | |
329 | #define IOMMU_PROT_IW 0x02 | |
330 | ||
331 | /* IOMMU capabilities */ | |
332 | #define IOMMU_CAP_IOTLB 24 | |
333 | #define IOMMU_CAP_NPCACHE 26 | |
d99ddec3 | 334 | #define IOMMU_CAP_EFR 27 |
8d283c35 | 335 | |
3928aa3f SS |
336 | /* IOMMU Feature Reporting Field (for IVHD type 10h */ |
337 | #define IOMMU_FEAT_GASUP_SHIFT 6 | |
338 | ||
339 | /* IOMMU Extended Feature Register (EFR) */ | |
340 | #define IOMMU_EFR_GASUP_SHIFT 7 | |
341 | ||
8d283c35 JR |
342 | #define MAX_DOMAIN_ID 65536 |
343 | ||
9fdb19d6 JR |
344 | /* Protection domain flags */ |
345 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
346 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
347 | domain for an IOMMU */ | |
0feae533 JR |
348 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
349 | translation */ | |
52815b75 | 350 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
0feae533 | 351 | |
fefda117 JR |
352 | extern bool amd_iommu_dump; |
353 | #define DUMP_printk(format, arg...) \ | |
354 | do { \ | |
355 | if (amd_iommu_dump) \ | |
4c6f40d4 | 356 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 357 | } while(0); |
9fdb19d6 | 358 | |
318afd41 JR |
359 | /* global flag if IOMMUs cache non-present entries */ |
360 | extern bool amd_iommu_np_cache; | |
60f723b4 JR |
361 | /* Only true if all IOMMUs support device IOTLBs */ |
362 | extern bool amd_iommu_iotlb_sup; | |
318afd41 | 363 | |
05152a04 JR |
364 | #define MAX_IRQS_PER_TABLE 256 |
365 | #define IRQ_TABLE_ALIGNMENT 128 | |
366 | ||
0ea2c422 JR |
367 | struct irq_remap_table { |
368 | spinlock_t lock; | |
369 | unsigned min_index; | |
370 | u32 *table; | |
371 | }; | |
372 | ||
373 | extern struct irq_remap_table **irq_lookup_table; | |
374 | ||
05152a04 JR |
375 | /* Interrupt remapping feature used? */ |
376 | extern bool amd_iommu_irq_remap; | |
377 | ||
378 | /* kmem_cache to get tables with 128 byte alignement */ | |
379 | extern struct kmem_cache *amd_iommu_irq_cache; | |
380 | ||
3bd22172 JR |
381 | /* |
382 | * Make iterating over all IOMMUs easier | |
383 | */ | |
384 | #define for_each_iommu(iommu) \ | |
385 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
386 | #define for_each_iommu_safe(iommu, next) \ | |
387 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
388 | ||
384de729 JR |
389 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
390 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
391 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
392 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
393 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
394 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 395 | |
72e1dcc4 JR |
396 | |
397 | /* | |
398 | * This struct is used to pass information about | |
399 | * incoming PPR faults around. | |
400 | */ | |
401 | struct amd_iommu_fault { | |
402 | u64 address; /* IO virtual address of the fault*/ | |
403 | u32 pasid; /* Address space identifier */ | |
404 | u16 device_id; /* Originating PCI device id */ | |
405 | u16 tag; /* PPR tag */ | |
406 | u16 flags; /* Fault flags */ | |
407 | ||
408 | }; | |
409 | ||
72e1dcc4 | 410 | |
f3572db8 | 411 | struct iommu_domain; |
7c71d306 | 412 | struct irq_domain; |
f3572db8 | 413 | |
5694703f JR |
414 | /* |
415 | * This structure contains generic data for IOMMU protection domains | |
416 | * independent of their use. | |
417 | */ | |
8d283c35 | 418 | struct protection_domain { |
aeb26f55 | 419 | struct list_head list; /* for list of all protection domains */ |
7c392cbe | 420 | struct list_head dev_list; /* List of all devices in this domain */ |
3f4b87b9 JR |
421 | struct iommu_domain domain; /* generic domain handle used by |
422 | iommu core code */ | |
9fdb19d6 | 423 | spinlock_t lock; /* mostly used to lock the page table*/ |
5d214fe6 | 424 | struct mutex api_lock; /* protect page tables in the iommu-api path */ |
9fdb19d6 JR |
425 | u16 id; /* the domain id written to the device table */ |
426 | int mode; /* paging mode (0-6 levels) */ | |
427 | u64 *pt_root; /* page table root pointer */ | |
52815b75 JR |
428 | int glx; /* Number of levels for GCR3 table */ |
429 | u64 *gcr3_tbl; /* Guest CR3 table */ | |
9fdb19d6 | 430 | unsigned long flags; /* flags to find out type of domain */ |
04bfdd84 | 431 | bool updated; /* complete domain flush required */ |
863c74eb | 432 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 433 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
8d283c35 JR |
434 | }; |
435 | ||
5694703f JR |
436 | /* |
437 | * Structure where we save information about one hardware AMD IOMMU in the | |
438 | * system. | |
439 | */ | |
8d283c35 JR |
440 | struct amd_iommu { |
441 | struct list_head list; | |
5694703f | 442 | |
bb52777e JR |
443 | /* Index within the IOMMU array */ |
444 | int index; | |
445 | ||
5694703f | 446 | /* locks the accesses to the hardware */ |
8d283c35 JR |
447 | spinlock_t lock; |
448 | ||
3eaf28a1 JR |
449 | /* Pointer to PCI device of this IOMMU */ |
450 | struct pci_dev *dev; | |
451 | ||
c1bf94ec JR |
452 | /* Cache pdev to root device for resume quirks */ |
453 | struct pci_dev *root_pdev; | |
454 | ||
5694703f | 455 | /* physical address of MMIO space */ |
8d283c35 | 456 | u64 mmio_phys; |
30861ddc SK |
457 | |
458 | /* physical end address of MMIO space */ | |
459 | u64 mmio_phys_end; | |
460 | ||
5694703f | 461 | /* virtual address of MMIO space */ |
98f1ad25 | 462 | u8 __iomem *mmio_base; |
5694703f JR |
463 | |
464 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 465 | u32 cap; |
5694703f | 466 | |
e9bf5197 JR |
467 | /* flags read from acpi table */ |
468 | u8 acpi_flags; | |
469 | ||
d99ddec3 JR |
470 | /* Extended features */ |
471 | u64 features; | |
472 | ||
400a28a0 JR |
473 | /* IOMMUv2 */ |
474 | bool is_iommu_v2; | |
475 | ||
23c742db JR |
476 | /* PCI device id of the IOMMU device */ |
477 | u16 devid; | |
478 | ||
eac9fbc6 RK |
479 | /* |
480 | * Capability pointer. There could be more than one IOMMU per PCI | |
481 | * device function if there are more than one AMD IOMMU capability | |
482 | * pointers. | |
483 | */ | |
484 | u16 cap_ptr; | |
485 | ||
ee893c24 JR |
486 | /* pci domain of this IOMMU */ |
487 | u16 pci_seg; | |
488 | ||
5694703f | 489 | /* start of exclusion range of that IOMMU */ |
8d283c35 | 490 | u64 exclusion_start; |
5694703f | 491 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
492 | u64 exclusion_length; |
493 | ||
5694703f | 494 | /* command buffer virtual address */ |
8d283c35 | 495 | u8 *cmd_buf; |
8d283c35 | 496 | |
eac9fbc6 RK |
497 | /* event buffer virtual address */ |
498 | u8 *evt_buf; | |
335503e5 | 499 | |
1a29ac01 JR |
500 | /* Base of the PPR log, if present */ |
501 | u8 *ppr_log; | |
502 | ||
a80dc3e0 JR |
503 | /* true if interrupts for this IOMMU are already enabled */ |
504 | bool int_enabled; | |
505 | ||
eac9fbc6 | 506 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 507 | bool need_sync; |
eac9fbc6 | 508 | |
066f2e98 AW |
509 | /* IOMMU sysfs device */ |
510 | struct device *iommu_dev; | |
511 | ||
4c894f47 | 512 | /* |
5bcd757f MG |
513 | * We can't rely on the BIOS to restore all values on reinit, so we |
514 | * need to stash them | |
4c894f47 | 515 | */ |
5bcd757f MG |
516 | |
517 | /* The iommu BAR */ | |
518 | u32 stored_addr_lo; | |
519 | u32 stored_addr_hi; | |
520 | ||
521 | /* | |
522 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | |
523 | * registers | |
524 | */ | |
525 | u32 stored_l1[6][0x12]; | |
526 | ||
527 | /* The l2 indirect registers */ | |
528 | u32 stored_l2[0x83]; | |
30861ddc SK |
529 | |
530 | /* The maximum PC banks and counters/bank (PCSup=1) */ | |
531 | u8 max_banks; | |
532 | u8 max_counters; | |
7c71d306 JL |
533 | #ifdef CONFIG_IRQ_REMAP |
534 | struct irq_domain *ir_domain; | |
535 | struct irq_domain *msi_domain; | |
536 | #endif | |
8d283c35 JR |
537 | }; |
538 | ||
2a0cb4e2 WZ |
539 | #define ACPIHID_UID_LEN 256 |
540 | #define ACPIHID_HID_LEN 9 | |
541 | ||
542 | struct acpihid_map_entry { | |
543 | struct list_head list; | |
544 | u8 uid[ACPIHID_UID_LEN]; | |
545 | u8 hid[ACPIHID_HID_LEN]; | |
546 | u16 devid; | |
547 | u16 root_devid; | |
548 | bool cmd_line; | |
549 | struct iommu_group *group; | |
550 | }; | |
551 | ||
6efed63b JR |
552 | struct devid_map { |
553 | struct list_head list; | |
554 | u8 id; | |
555 | u16 devid; | |
31cff67f | 556 | bool cmd_line; |
6efed63b JR |
557 | }; |
558 | ||
559 | /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ | |
560 | extern struct list_head ioapic_map; | |
561 | extern struct list_head hpet_map; | |
2a0cb4e2 | 562 | extern struct list_head acpihid_map; |
6efed63b | 563 | |
5694703f JR |
564 | /* |
565 | * List with all IOMMUs in the system. This list is not locked because it is | |
566 | * only written and read at driver initialization or suspend time | |
567 | */ | |
8d283c35 JR |
568 | extern struct list_head amd_iommu_list; |
569 | ||
bb52777e JR |
570 | /* |
571 | * Array with pointers to each IOMMU struct | |
572 | * The indices are referenced in the protection domains | |
573 | */ | |
574 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
575 | ||
576 | /* Number of IOMMUs present in the system */ | |
577 | extern int amd_iommus_present; | |
578 | ||
aeb26f55 JR |
579 | /* |
580 | * Declarations for the global list of all protection domains | |
581 | */ | |
582 | extern spinlock_t amd_iommu_pd_lock; | |
583 | extern struct list_head amd_iommu_pd_list; | |
584 | ||
5694703f JR |
585 | /* |
586 | * Structure defining one entry in the device table | |
587 | */ | |
8d283c35 | 588 | struct dev_table_entry { |
ee6c2868 | 589 | u64 data[4]; |
8d283c35 JR |
590 | }; |
591 | ||
5694703f JR |
592 | /* |
593 | * One entry for unity mappings parsed out of the ACPI table. | |
594 | */ | |
8d283c35 JR |
595 | struct unity_map_entry { |
596 | struct list_head list; | |
5694703f JR |
597 | |
598 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 599 | u16 devid_start; |
5694703f | 600 | /* end device id this entry is used for (including) */ |
8d283c35 | 601 | u16 devid_end; |
5694703f JR |
602 | |
603 | /* start address to unity map (including) */ | |
8d283c35 | 604 | u64 address_start; |
5694703f | 605 | /* end address to unity map (including) */ |
8d283c35 | 606 | u64 address_end; |
5694703f JR |
607 | |
608 | /* required protection */ | |
8d283c35 JR |
609 | int prot; |
610 | }; | |
611 | ||
5694703f JR |
612 | /* |
613 | * List of all unity mappings. It is not locked because as runtime it is only | |
614 | * read. It is created at ACPI table parsing time. | |
615 | */ | |
8d283c35 JR |
616 | extern struct list_head amd_iommu_unity_map; |
617 | ||
5694703f JR |
618 | /* |
619 | * Data structures for device handling | |
620 | */ | |
621 | ||
622 | /* | |
623 | * Device table used by hardware. Read and write accesses by software are | |
624 | * locked with the amd_iommu_pd_table lock. | |
625 | */ | |
8d283c35 | 626 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
627 | |
628 | /* | |
629 | * Alias table to find requestor ids to device ids. Not locked because only | |
630 | * read on runtime. | |
631 | */ | |
8d283c35 | 632 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
633 | |
634 | /* | |
635 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
636 | */ | |
8d283c35 JR |
637 | extern struct amd_iommu **amd_iommu_rlookup_table; |
638 | ||
5694703f | 639 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
640 | extern unsigned amd_iommu_aperture_order; |
641 | ||
5694703f | 642 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
643 | extern u16 amd_iommu_last_bdf; |
644 | ||
5694703f | 645 | /* allocation bitmap for domain ids */ |
8d283c35 JR |
646 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
647 | ||
afa9fdc2 FT |
648 | /* |
649 | * If true, the addresses will be flushed on unmap time, not when | |
650 | * they are reused | |
651 | */ | |
621a5f7a | 652 | extern bool amd_iommu_unmap_flush; |
afa9fdc2 | 653 | |
a919a018 SS |
654 | /* Smallest max PASID supported by any IOMMU in the system */ |
655 | extern u32 amd_iommu_max_pasid; | |
62f71abb | 656 | |
400a28a0 JR |
657 | extern bool amd_iommu_v2_present; |
658 | ||
5abcdba4 JR |
659 | extern bool amd_iommu_force_isolation; |
660 | ||
52815b75 JR |
661 | /* Max levels of glxval supported */ |
662 | extern int amd_iommu_max_glx_val; | |
663 | ||
98f1ad25 JR |
664 | /* |
665 | * This function flushes all internal caches of | |
666 | * the IOMMU used by this driver. | |
667 | */ | |
668 | extern void iommu_flush_all_caches(struct amd_iommu *iommu); | |
669 | ||
6efed63b JR |
670 | static inline int get_ioapic_devid(int id) |
671 | { | |
672 | struct devid_map *entry; | |
673 | ||
674 | list_for_each_entry(entry, &ioapic_map, list) { | |
675 | if (entry->id == id) | |
676 | return entry->devid; | |
677 | } | |
678 | ||
679 | return -EINVAL; | |
680 | } | |
681 | ||
682 | static inline int get_hpet_devid(int id) | |
683 | { | |
684 | struct devid_map *entry; | |
685 | ||
686 | list_for_each_entry(entry, &hpet_map, list) { | |
687 | if (entry->id == id) | |
688 | return entry->devid; | |
689 | } | |
690 | ||
691 | return -EINVAL; | |
692 | } | |
693 | ||
3928aa3f SS |
694 | enum amd_iommu_intr_mode_type { |
695 | AMD_IOMMU_GUEST_IR_LEGACY, | |
696 | ||
697 | /* This mode is not visible to users. It is used when | |
698 | * we cannot fully enable vAPIC and fallback to only support | |
699 | * legacy interrupt remapping via 128-bit IRTE. | |
700 | */ | |
701 | AMD_IOMMU_GUEST_IR_LEGACY_GA, | |
702 | AMD_IOMMU_GUEST_IR_VAPIC, | |
703 | }; | |
704 | ||
705 | #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ | |
706 | x == AMD_IOMMU_GUEST_IR_LEGACY_GA) | |
707 | ||
708 | #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) | |
a38180bd SS |
709 | |
710 | union irte { | |
711 | u32 val; | |
712 | struct { | |
713 | u32 valid : 1, | |
714 | no_fault : 1, | |
715 | int_type : 3, | |
716 | rq_eoi : 1, | |
717 | dm : 1, | |
718 | rsvd_1 : 1, | |
719 | destination : 8, | |
720 | vector : 8, | |
721 | rsvd_2 : 8; | |
722 | } fields; | |
723 | }; | |
724 | ||
725 | union irte_ga_lo { | |
726 | u64 val; | |
727 | ||
728 | /* For int remapping */ | |
729 | struct { | |
730 | u64 valid : 1, | |
731 | no_fault : 1, | |
732 | /* ------ */ | |
733 | int_type : 3, | |
734 | rq_eoi : 1, | |
735 | dm : 1, | |
736 | /* ------ */ | |
737 | guest_mode : 1, | |
738 | destination : 8, | |
739 | rsvd : 48; | |
740 | } fields_remap; | |
741 | ||
742 | /* For guest vAPIC */ | |
743 | struct { | |
744 | u64 valid : 1, | |
745 | no_fault : 1, | |
746 | /* ------ */ | |
747 | ga_log_intr : 1, | |
748 | rsvd1 : 3, | |
749 | is_run : 1, | |
750 | /* ------ */ | |
751 | guest_mode : 1, | |
752 | destination : 8, | |
753 | rsvd2 : 16, | |
754 | ga_tag : 32; | |
755 | } fields_vapic; | |
756 | }; | |
757 | ||
758 | union irte_ga_hi { | |
759 | u64 val; | |
760 | struct { | |
761 | u64 vector : 8, | |
762 | rsvd_1 : 4, | |
763 | ga_root_ptr : 40, | |
764 | rsvd_2 : 12; | |
765 | } fields; | |
766 | }; | |
767 | ||
768 | struct irte_ga { | |
769 | union irte_ga_lo lo; | |
770 | union irte_ga_hi hi; | |
771 | }; | |
772 | ||
773 | struct irq_2_irte { | |
774 | u16 devid; /* Device ID for IRTE table */ | |
775 | u16 index; /* Index into IRTE table*/ | |
776 | }; | |
777 | ||
778 | struct amd_ir_data { | |
779 | struct irq_2_irte irq_2_irte; | |
780 | union irte irte_entry; | |
781 | struct msi_msg msi_entry; | |
782 | }; | |
783 | ||
1965aae3 | 784 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |