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8d283c35 | 1 | /* |
5d0d7156 | 2 | * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. |
8d283c35 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
1965aae3 PA |
20 | #ifndef _ASM_X86_AMD_IOMMU_TYPES_H |
21 | #define _ASM_X86_AMD_IOMMU_TYPES_H | |
8d283c35 JR |
22 | |
23 | #include <linux/types.h> | |
5d214fe6 | 24 | #include <linux/mutex.h> |
8d283c35 JR |
25 | #include <linux/list.h> |
26 | #include <linux/spinlock.h> | |
27 | ||
bb52777e JR |
28 | /* |
29 | * Maximum number of IOMMUs supported | |
30 | */ | |
31 | #define MAX_IOMMUS 32 | |
32 | ||
8d283c35 JR |
33 | /* |
34 | * some size calculation constants | |
35 | */ | |
83f5aac1 | 36 | #define DEV_TABLE_ENTRY_SIZE 32 |
8d283c35 JR |
37 | #define ALIAS_TABLE_ENTRY_SIZE 2 |
38 | #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) | |
39 | ||
8d283c35 JR |
40 | /* Length of the MMIO region for the AMD IOMMU */ |
41 | #define MMIO_REGION_LENGTH 0x4000 | |
42 | ||
43 | /* Capability offsets used by the driver */ | |
44 | #define MMIO_CAP_HDR_OFFSET 0x00 | |
45 | #define MMIO_RANGE_OFFSET 0x0c | |
a80dc3e0 | 46 | #define MMIO_MISC_OFFSET 0x10 |
8d283c35 JR |
47 | |
48 | /* Masks, shifts and macros to parse the device range capability */ | |
49 | #define MMIO_RANGE_LD_MASK 0xff000000 | |
50 | #define MMIO_RANGE_FD_MASK 0x00ff0000 | |
51 | #define MMIO_RANGE_BUS_MASK 0x0000ff00 | |
52 | #define MMIO_RANGE_LD_SHIFT 24 | |
53 | #define MMIO_RANGE_FD_SHIFT 16 | |
54 | #define MMIO_RANGE_BUS_SHIFT 8 | |
55 | #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) | |
56 | #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) | |
57 | #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) | |
a80dc3e0 | 58 | #define MMIO_MSI_NUM(x) ((x) & 0x1f) |
8d283c35 JR |
59 | |
60 | /* Flag masks for the AMD IOMMU exclusion range */ | |
61 | #define MMIO_EXCL_ENABLE_MASK 0x01ULL | |
62 | #define MMIO_EXCL_ALLOW_MASK 0x02ULL | |
63 | ||
64 | /* Used offsets into the MMIO space */ | |
65 | #define MMIO_DEV_TABLE_OFFSET 0x0000 | |
66 | #define MMIO_CMD_BUF_OFFSET 0x0008 | |
67 | #define MMIO_EVT_BUF_OFFSET 0x0010 | |
68 | #define MMIO_CONTROL_OFFSET 0x0018 | |
69 | #define MMIO_EXCL_BASE_OFFSET 0x0020 | |
70 | #define MMIO_EXCL_LIMIT_OFFSET 0x0028 | |
d99ddec3 | 71 | #define MMIO_EXT_FEATURES 0x0030 |
1a29ac01 | 72 | #define MMIO_PPR_LOG_OFFSET 0x0038 |
8d283c35 JR |
73 | #define MMIO_CMD_HEAD_OFFSET 0x2000 |
74 | #define MMIO_CMD_TAIL_OFFSET 0x2008 | |
75 | #define MMIO_EVT_HEAD_OFFSET 0x2010 | |
76 | #define MMIO_EVT_TAIL_OFFSET 0x2018 | |
77 | #define MMIO_STATUS_OFFSET 0x2020 | |
1a29ac01 JR |
78 | #define MMIO_PPR_HEAD_OFFSET 0x2030 |
79 | #define MMIO_PPR_TAIL_OFFSET 0x2038 | |
8d283c35 | 80 | |
d99ddec3 JR |
81 | |
82 | /* Extended Feature Bits */ | |
83 | #define FEATURE_PREFETCH (1ULL<<0) | |
84 | #define FEATURE_PPR (1ULL<<1) | |
85 | #define FEATURE_X2APIC (1ULL<<2) | |
86 | #define FEATURE_NX (1ULL<<3) | |
87 | #define FEATURE_GT (1ULL<<4) | |
88 | #define FEATURE_IA (1ULL<<6) | |
89 | #define FEATURE_GA (1ULL<<7) | |
90 | #define FEATURE_HE (1ULL<<8) | |
91 | #define FEATURE_PC (1ULL<<9) | |
92 | ||
62f71abb JR |
93 | #define FEATURE_PASID_SHIFT 32 |
94 | #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) | |
95 | ||
52815b75 JR |
96 | #define FEATURE_GLXVAL_SHIFT 14 |
97 | #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) | |
98 | ||
99 | #define PASID_MASK 0x000fffff | |
100 | ||
519c31ba | 101 | /* MMIO status bits */ |
72e1dcc4 JR |
102 | #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
103 | #define MMIO_STATUS_PPR_INT_MASK (1 << 6) | |
519c31ba | 104 | |
90008ee4 JR |
105 | /* event logging constants */ |
106 | #define EVENT_ENTRY_SIZE 0x10 | |
107 | #define EVENT_TYPE_SHIFT 28 | |
108 | #define EVENT_TYPE_MASK 0xf | |
109 | #define EVENT_TYPE_ILL_DEV 0x1 | |
110 | #define EVENT_TYPE_IO_FAULT 0x2 | |
111 | #define EVENT_TYPE_DEV_TAB_ERR 0x3 | |
112 | #define EVENT_TYPE_PAGE_TAB_ERR 0x4 | |
113 | #define EVENT_TYPE_ILL_CMD 0x5 | |
114 | #define EVENT_TYPE_CMD_HARD_ERR 0x6 | |
115 | #define EVENT_TYPE_IOTLB_INV_TO 0x7 | |
116 | #define EVENT_TYPE_INV_DEV_REQ 0x8 | |
117 | #define EVENT_DEVID_MASK 0xffff | |
118 | #define EVENT_DEVID_SHIFT 0 | |
119 | #define EVENT_DOMID_MASK 0xffff | |
120 | #define EVENT_DOMID_SHIFT 0 | |
121 | #define EVENT_FLAGS_MASK 0xfff | |
122 | #define EVENT_FLAGS_SHIFT 0x10 | |
123 | ||
8d283c35 JR |
124 | /* feature control bits */ |
125 | #define CONTROL_IOMMU_EN 0x00ULL | |
126 | #define CONTROL_HT_TUN_EN 0x01ULL | |
127 | #define CONTROL_EVT_LOG_EN 0x02ULL | |
128 | #define CONTROL_EVT_INT_EN 0x03ULL | |
129 | #define CONTROL_COMWAIT_EN 0x04ULL | |
130 | #define CONTROL_PASSPW_EN 0x08ULL | |
131 | #define CONTROL_RESPASSPW_EN 0x09ULL | |
132 | #define CONTROL_COHERENT_EN 0x0aULL | |
133 | #define CONTROL_ISOC_EN 0x0bULL | |
134 | #define CONTROL_CMDBUF_EN 0x0cULL | |
135 | #define CONTROL_PPFLOG_EN 0x0dULL | |
136 | #define CONTROL_PPFINT_EN 0x0eULL | |
1a29ac01 | 137 | #define CONTROL_PPR_EN 0x0fULL |
cbc33a90 | 138 | #define CONTROL_GT_EN 0x10ULL |
8d283c35 JR |
139 | |
140 | /* command specific defines */ | |
141 | #define CMD_COMPL_WAIT 0x01 | |
142 | #define CMD_INV_DEV_ENTRY 0x02 | |
cb41ed85 JR |
143 | #define CMD_INV_IOMMU_PAGES 0x03 |
144 | #define CMD_INV_IOTLB_PAGES 0x04 | |
c99afa25 | 145 | #define CMD_COMPLETE_PPR 0x07 |
58fc7f14 | 146 | #define CMD_INV_ALL 0x08 |
8d283c35 JR |
147 | |
148 | #define CMD_COMPL_WAIT_STORE_MASK 0x01 | |
519c31ba | 149 | #define CMD_COMPL_WAIT_INT_MASK 0x02 |
8d283c35 JR |
150 | #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
151 | #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 | |
22e266c7 | 152 | #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
8d283c35 | 153 | |
c99afa25 JR |
154 | #define PPR_STATUS_MASK 0xf |
155 | #define PPR_STATUS_SHIFT 12 | |
156 | ||
999ba417 JR |
157 | #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
158 | ||
8d283c35 JR |
159 | /* macros and definitions for device table entries */ |
160 | #define DEV_ENTRY_VALID 0x00 | |
161 | #define DEV_ENTRY_TRANSLATION 0x01 | |
162 | #define DEV_ENTRY_IR 0x3d | |
163 | #define DEV_ENTRY_IW 0x3e | |
9f5f5fb3 | 164 | #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
8d283c35 JR |
165 | #define DEV_ENTRY_EX 0x67 |
166 | #define DEV_ENTRY_SYSMGT1 0x68 | |
167 | #define DEV_ENTRY_SYSMGT2 0x69 | |
168 | #define DEV_ENTRY_INIT_PASS 0xb8 | |
169 | #define DEV_ENTRY_EINT_PASS 0xb9 | |
170 | #define DEV_ENTRY_NMI_PASS 0xba | |
171 | #define DEV_ENTRY_LINT0_PASS 0xbe | |
172 | #define DEV_ENTRY_LINT1_PASS 0xbf | |
38ddf41b JR |
173 | #define DEV_ENTRY_MODE_MASK 0x07 |
174 | #define DEV_ENTRY_MODE_SHIFT 0x09 | |
8d283c35 JR |
175 | |
176 | /* constants to configure the command buffer */ | |
177 | #define CMD_BUFFER_SIZE 8192 | |
549c90dc | 178 | #define CMD_BUFFER_UNINITIALIZED 1 |
8d283c35 JR |
179 | #define CMD_BUFFER_ENTRIES 512 |
180 | #define MMIO_CMD_SIZE_SHIFT 56 | |
181 | #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) | |
182 | ||
335503e5 JR |
183 | /* constants for event buffer handling */ |
184 | #define EVT_BUFFER_SIZE 8192 /* 512 entries */ | |
185 | #define EVT_LEN_MASK (0x9ULL << 56) | |
186 | ||
1a29ac01 JR |
187 | /* Constants for PPR Log handling */ |
188 | #define PPR_LOG_ENTRIES 512 | |
189 | #define PPR_LOG_SIZE_SHIFT 56 | |
190 | #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) | |
191 | #define PPR_ENTRY_SIZE 16 | |
192 | #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) | |
193 | ||
72e1dcc4 JR |
194 | #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
195 | #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) | |
196 | #define PPR_DEVID(x) ((x) & 0xffffULL) | |
197 | #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) | |
198 | #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) | |
199 | #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) | |
200 | #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) | |
201 | ||
202 | #define PPR_REQ_FAULT 0x01 | |
203 | ||
0feae533 | 204 | #define PAGE_MODE_NONE 0x00 |
8d283c35 JR |
205 | #define PAGE_MODE_1_LEVEL 0x01 |
206 | #define PAGE_MODE_2_LEVEL 0x02 | |
207 | #define PAGE_MODE_3_LEVEL 0x03 | |
9355a081 JR |
208 | #define PAGE_MODE_4_LEVEL 0x04 |
209 | #define PAGE_MODE_5_LEVEL 0x05 | |
210 | #define PAGE_MODE_6_LEVEL 0x06 | |
8d283c35 | 211 | |
9355a081 JR |
212 | #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
213 | #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ | |
214 | ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ | |
215 | (0xffffffffffffffffULL)) | |
216 | #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) | |
50020fb6 JR |
217 | #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
218 | #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ | |
219 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW) | |
a6b256b4 | 220 | #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
50020fb6 | 221 | |
abdc5eb3 JR |
222 | #define PM_MAP_4k 0 |
223 | #define PM_ADDR_MASK 0x000ffffffffff000ULL | |
224 | #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ | |
225 | (~((1ULL << (12 + ((lvl) * 9))) - 1))) | |
226 | #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) | |
8d283c35 | 227 | |
cbb9d729 JR |
228 | /* |
229 | * Returns the page table level to use for a given page size | |
230 | * Pagesize is expected to be a power-of-two | |
231 | */ | |
232 | #define PAGE_SIZE_LEVEL(pagesize) \ | |
233 | ((__ffs(pagesize) - 12) / 9) | |
234 | /* | |
235 | * Returns the number of ptes to use for a given page size | |
236 | * Pagesize is expected to be a power-of-two | |
237 | */ | |
238 | #define PAGE_SIZE_PTE_COUNT(pagesize) \ | |
239 | (1ULL << ((__ffs(pagesize) - 12) % 9)) | |
240 | ||
241 | /* | |
242 | * Aligns a given io-virtual address to a given page size | |
243 | * Pagesize is expected to be a power-of-two | |
244 | */ | |
245 | #define PAGE_SIZE_ALIGN(address, pagesize) \ | |
246 | ((address) & ~((pagesize) - 1)) | |
247 | /* | |
248 | * Creates an IOMMU PTE for an address an a given pagesize | |
249 | * The PTE has no permission bits set | |
250 | * Pagesize is expected to be a power-of-two larger than 4096 | |
251 | */ | |
252 | #define PAGE_SIZE_PTE(address, pagesize) \ | |
253 | (((address) | ((pagesize) - 1)) & \ | |
254 | (~(pagesize >> 1)) & PM_ADDR_MASK) | |
255 | ||
24cd7723 JR |
256 | /* |
257 | * Takes a PTE value with mode=0x07 and returns the page size it maps | |
258 | */ | |
259 | #define PTE_PAGE_SIZE(pte) \ | |
260 | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) | |
261 | ||
8d283c35 | 262 | #define IOMMU_PTE_P (1ULL << 0) |
38ddf41b | 263 | #define IOMMU_PTE_TV (1ULL << 1) |
8d283c35 JR |
264 | #define IOMMU_PTE_U (1ULL << 59) |
265 | #define IOMMU_PTE_FC (1ULL << 60) | |
266 | #define IOMMU_PTE_IR (1ULL << 61) | |
267 | #define IOMMU_PTE_IW (1ULL << 62) | |
268 | ||
ee6c2868 | 269 | #define DTE_FLAG_IOTLB (0x01UL << 32) |
52815b75 JR |
270 | #define DTE_FLAG_GV (0x01ULL << 55) |
271 | #define DTE_GLX_SHIFT (56) | |
272 | #define DTE_GLX_MASK (3) | |
273 | ||
274 | #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) | |
275 | #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) | |
276 | #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) | |
277 | ||
278 | #define DTE_GCR3_INDEX_A 0 | |
279 | #define DTE_GCR3_INDEX_B 1 | |
280 | #define DTE_GCR3_INDEX_C 1 | |
281 | ||
282 | #define DTE_GCR3_SHIFT_A 58 | |
283 | #define DTE_GCR3_SHIFT_B 16 | |
284 | #define DTE_GCR3_SHIFT_C 43 | |
285 | ||
b16137b1 | 286 | #define GCR3_VALID 0x01ULL |
fd7b5535 | 287 | |
8d283c35 JR |
288 | #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
289 | #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) | |
290 | #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) | |
291 | #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) | |
292 | ||
293 | #define IOMMU_PROT_MASK 0x03 | |
294 | #define IOMMU_PROT_IR 0x01 | |
295 | #define IOMMU_PROT_IW 0x02 | |
296 | ||
297 | /* IOMMU capabilities */ | |
298 | #define IOMMU_CAP_IOTLB 24 | |
299 | #define IOMMU_CAP_NPCACHE 26 | |
d99ddec3 | 300 | #define IOMMU_CAP_EFR 27 |
8d283c35 JR |
301 | |
302 | #define MAX_DOMAIN_ID 65536 | |
303 | ||
90008ee4 JR |
304 | /* FIXME: move this macro to <linux/pci.h> */ |
305 | #define PCI_BUS(x) (((x) >> 8) & 0xff) | |
306 | ||
9fdb19d6 JR |
307 | /* Protection domain flags */ |
308 | #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ | |
e2dc14a2 JR |
309 | #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops |
310 | domain for an IOMMU */ | |
0feae533 JR |
311 | #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page |
312 | translation */ | |
52815b75 | 313 | #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
0feae533 | 314 | |
fefda117 JR |
315 | extern bool amd_iommu_dump; |
316 | #define DUMP_printk(format, arg...) \ | |
317 | do { \ | |
318 | if (amd_iommu_dump) \ | |
4c6f40d4 | 319 | printk(KERN_INFO "AMD-Vi: " format, ## arg); \ |
fefda117 | 320 | } while(0); |
9fdb19d6 | 321 | |
318afd41 JR |
322 | /* global flag if IOMMUs cache non-present entries */ |
323 | extern bool amd_iommu_np_cache; | |
60f723b4 JR |
324 | /* Only true if all IOMMUs support device IOTLBs */ |
325 | extern bool amd_iommu_iotlb_sup; | |
318afd41 | 326 | |
3bd22172 JR |
327 | /* |
328 | * Make iterating over all IOMMUs easier | |
329 | */ | |
330 | #define for_each_iommu(iommu) \ | |
331 | list_for_each_entry((iommu), &amd_iommu_list, list) | |
332 | #define for_each_iommu_safe(iommu, next) \ | |
333 | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) | |
334 | ||
384de729 JR |
335 | #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
336 | #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) | |
337 | #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) | |
338 | #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ | |
339 | #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) | |
340 | #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) | |
9fdb19d6 | 341 | |
72e1dcc4 JR |
342 | |
343 | /* | |
344 | * This struct is used to pass information about | |
345 | * incoming PPR faults around. | |
346 | */ | |
347 | struct amd_iommu_fault { | |
348 | u64 address; /* IO virtual address of the fault*/ | |
349 | u32 pasid; /* Address space identifier */ | |
350 | u16 device_id; /* Originating PCI device id */ | |
351 | u16 tag; /* PPR tag */ | |
352 | u16 flags; /* Fault flags */ | |
353 | ||
354 | }; | |
355 | ||
356 | #define PPR_FAULT_EXEC (1 << 1) | |
357 | #define PPR_FAULT_READ (1 << 2) | |
358 | #define PPR_FAULT_WRITE (1 << 5) | |
359 | #define PPR_FAULT_USER (1 << 6) | |
360 | #define PPR_FAULT_RSVD (1 << 7) | |
361 | #define PPR_FAULT_GN (1 << 8) | |
362 | ||
5694703f JR |
363 | /* |
364 | * This structure contains generic data for IOMMU protection domains | |
365 | * independent of their use. | |
366 | */ | |
8d283c35 | 367 | struct protection_domain { |
aeb26f55 | 368 | struct list_head list; /* for list of all protection domains */ |
7c392cbe | 369 | struct list_head dev_list; /* List of all devices in this domain */ |
9fdb19d6 | 370 | spinlock_t lock; /* mostly used to lock the page table*/ |
5d214fe6 | 371 | struct mutex api_lock; /* protect page tables in the iommu-api path */ |
9fdb19d6 JR |
372 | u16 id; /* the domain id written to the device table */ |
373 | int mode; /* paging mode (0-6 levels) */ | |
374 | u64 *pt_root; /* page table root pointer */ | |
52815b75 JR |
375 | int glx; /* Number of levels for GCR3 table */ |
376 | u64 *gcr3_tbl; /* Guest CR3 table */ | |
9fdb19d6 | 377 | unsigned long flags; /* flags to find out type of domain */ |
04bfdd84 | 378 | bool updated; /* complete domain flush required */ |
863c74eb | 379 | unsigned dev_cnt; /* devices assigned to this domain */ |
c4596114 | 380 | unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ |
9fdb19d6 | 381 | void *priv; /* private data */ |
c4596114 | 382 | |
8d283c35 JR |
383 | }; |
384 | ||
657cbb6b JR |
385 | /* |
386 | * This struct contains device specific data for the IOMMU | |
387 | */ | |
388 | struct iommu_dev_data { | |
7c392cbe | 389 | struct list_head list; /* For domain->dev_list */ |
8fa5f802 | 390 | struct list_head dev_data_list; /* For global dev_data_list */ |
71f77580 | 391 | struct iommu_dev_data *alias_data;/* The alias dev_data */ |
657cbb6b | 392 | struct protection_domain *domain; /* Domain the device is bound to */ |
24100055 | 393 | atomic_t bind; /* Domain attach reverent count */ |
f62dda66 | 394 | u16 devid; /* PCI Device ID */ |
5abcdba4 JR |
395 | bool iommu_v2; /* Device can make use of IOMMUv2 */ |
396 | bool passthrough; /* Default for device is pt_domain */ | |
ea61cddb JR |
397 | struct { |
398 | bool enabled; | |
399 | int qdep; | |
400 | } ats; /* ATS state */ | |
c99afa25 JR |
401 | bool pri_tlp; /* PASID TLB required for |
402 | PPR completions */ | |
657cbb6b JR |
403 | }; |
404 | ||
c3239567 JR |
405 | /* |
406 | * For dynamic growth the aperture size is split into ranges of 128MB of | |
407 | * DMA address space each. This struct represents one such range. | |
408 | */ | |
409 | struct aperture_range { | |
410 | ||
411 | /* address allocation bitmap */ | |
412 | unsigned long *bitmap; | |
413 | ||
414 | /* | |
415 | * Array of PTE pages for the aperture. In this array we save all the | |
416 | * leaf pages of the domain page table used for the aperture. This way | |
417 | * we don't need to walk the page table to find a specific PTE. We can | |
418 | * just calculate its address in constant time. | |
419 | */ | |
420 | u64 *pte_pages[64]; | |
384de729 JR |
421 | |
422 | unsigned long offset; | |
c3239567 JR |
423 | }; |
424 | ||
5694703f JR |
425 | /* |
426 | * Data container for a dma_ops specific protection domain | |
427 | */ | |
8d283c35 JR |
428 | struct dma_ops_domain { |
429 | struct list_head list; | |
5694703f JR |
430 | |
431 | /* generic protection domain information */ | |
8d283c35 | 432 | struct protection_domain domain; |
5694703f JR |
433 | |
434 | /* size of the aperture for the mappings */ | |
8d283c35 | 435 | unsigned long aperture_size; |
5694703f JR |
436 | |
437 | /* address we start to search for free addresses */ | |
803b8cb4 | 438 | unsigned long next_address; |
5694703f | 439 | |
c3239567 | 440 | /* address space relevant data */ |
384de729 | 441 | struct aperture_range *aperture[APERTURE_MAX_RANGES]; |
1c655773 JR |
442 | |
443 | /* This will be set to true when TLB needs to be flushed */ | |
444 | bool need_flush; | |
bd60b735 JR |
445 | |
446 | /* | |
447 | * if this is a preallocated domain, keep the device for which it was | |
448 | * preallocated in this variable | |
449 | */ | |
450 | u16 target_dev; | |
8d283c35 JR |
451 | }; |
452 | ||
5694703f JR |
453 | /* |
454 | * Structure where we save information about one hardware AMD IOMMU in the | |
455 | * system. | |
456 | */ | |
8d283c35 JR |
457 | struct amd_iommu { |
458 | struct list_head list; | |
5694703f | 459 | |
bb52777e JR |
460 | /* Index within the IOMMU array */ |
461 | int index; | |
462 | ||
5694703f | 463 | /* locks the accesses to the hardware */ |
8d283c35 JR |
464 | spinlock_t lock; |
465 | ||
3eaf28a1 JR |
466 | /* Pointer to PCI device of this IOMMU */ |
467 | struct pci_dev *dev; | |
468 | ||
5694703f | 469 | /* physical address of MMIO space */ |
8d283c35 | 470 | u64 mmio_phys; |
5694703f | 471 | /* virtual address of MMIO space */ |
8d283c35 | 472 | u8 *mmio_base; |
5694703f JR |
473 | |
474 | /* capabilities of that IOMMU read from ACPI */ | |
8d283c35 | 475 | u32 cap; |
5694703f | 476 | |
e9bf5197 JR |
477 | /* flags read from acpi table */ |
478 | u8 acpi_flags; | |
479 | ||
d99ddec3 JR |
480 | /* Extended features */ |
481 | u64 features; | |
482 | ||
400a28a0 JR |
483 | /* IOMMUv2 */ |
484 | bool is_iommu_v2; | |
485 | ||
eac9fbc6 RK |
486 | /* |
487 | * Capability pointer. There could be more than one IOMMU per PCI | |
488 | * device function if there are more than one AMD IOMMU capability | |
489 | * pointers. | |
490 | */ | |
491 | u16 cap_ptr; | |
492 | ||
ee893c24 JR |
493 | /* pci domain of this IOMMU */ |
494 | u16 pci_seg; | |
495 | ||
5694703f | 496 | /* first device this IOMMU handles. read from PCI */ |
8d283c35 | 497 | u16 first_device; |
5694703f | 498 | /* last device this IOMMU handles. read from PCI */ |
8d283c35 | 499 | u16 last_device; |
5694703f JR |
500 | |
501 | /* start of exclusion range of that IOMMU */ | |
8d283c35 | 502 | u64 exclusion_start; |
5694703f | 503 | /* length of exclusion range of that IOMMU */ |
8d283c35 JR |
504 | u64 exclusion_length; |
505 | ||
5694703f | 506 | /* command buffer virtual address */ |
8d283c35 | 507 | u8 *cmd_buf; |
5694703f | 508 | /* size of command buffer */ |
8d283c35 JR |
509 | u32 cmd_buf_size; |
510 | ||
335503e5 JR |
511 | /* size of event buffer */ |
512 | u32 evt_buf_size; | |
eac9fbc6 RK |
513 | /* event buffer virtual address */ |
514 | u8 *evt_buf; | |
a80dc3e0 JR |
515 | /* MSI number for event interrupt */ |
516 | u16 evt_msi_num; | |
335503e5 | 517 | |
1a29ac01 JR |
518 | /* Base of the PPR log, if present */ |
519 | u8 *ppr_log; | |
520 | ||
a80dc3e0 JR |
521 | /* true if interrupts for this IOMMU are already enabled */ |
522 | bool int_enabled; | |
523 | ||
eac9fbc6 | 524 | /* if one, we need to send a completion wait command */ |
0cfd7aa9 | 525 | bool need_sync; |
eac9fbc6 | 526 | |
5694703f | 527 | /* default dma_ops domain for that IOMMU */ |
8d283c35 | 528 | struct dma_ops_domain *default_dom; |
4c894f47 JR |
529 | |
530 | /* | |
5bcd757f MG |
531 | * We can't rely on the BIOS to restore all values on reinit, so we |
532 | * need to stash them | |
4c894f47 | 533 | */ |
5bcd757f MG |
534 | |
535 | /* The iommu BAR */ | |
536 | u32 stored_addr_lo; | |
537 | u32 stored_addr_hi; | |
538 | ||
539 | /* | |
540 | * Each iommu has 6 l1s, each of which is documented as having 0x12 | |
541 | * registers | |
542 | */ | |
543 | u32 stored_l1[6][0x12]; | |
544 | ||
545 | /* The l2 indirect registers */ | |
546 | u32 stored_l2[0x83]; | |
8d283c35 JR |
547 | }; |
548 | ||
5694703f JR |
549 | /* |
550 | * List with all IOMMUs in the system. This list is not locked because it is | |
551 | * only written and read at driver initialization or suspend time | |
552 | */ | |
8d283c35 JR |
553 | extern struct list_head amd_iommu_list; |
554 | ||
bb52777e JR |
555 | /* |
556 | * Array with pointers to each IOMMU struct | |
557 | * The indices are referenced in the protection domains | |
558 | */ | |
559 | extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; | |
560 | ||
561 | /* Number of IOMMUs present in the system */ | |
562 | extern int amd_iommus_present; | |
563 | ||
aeb26f55 JR |
564 | /* |
565 | * Declarations for the global list of all protection domains | |
566 | */ | |
567 | extern spinlock_t amd_iommu_pd_lock; | |
568 | extern struct list_head amd_iommu_pd_list; | |
569 | ||
5694703f JR |
570 | /* |
571 | * Structure defining one entry in the device table | |
572 | */ | |
8d283c35 | 573 | struct dev_table_entry { |
ee6c2868 | 574 | u64 data[4]; |
8d283c35 JR |
575 | }; |
576 | ||
5694703f JR |
577 | /* |
578 | * One entry for unity mappings parsed out of the ACPI table. | |
579 | */ | |
8d283c35 JR |
580 | struct unity_map_entry { |
581 | struct list_head list; | |
5694703f JR |
582 | |
583 | /* starting device id this entry is used for (including) */ | |
8d283c35 | 584 | u16 devid_start; |
5694703f | 585 | /* end device id this entry is used for (including) */ |
8d283c35 | 586 | u16 devid_end; |
5694703f JR |
587 | |
588 | /* start address to unity map (including) */ | |
8d283c35 | 589 | u64 address_start; |
5694703f | 590 | /* end address to unity map (including) */ |
8d283c35 | 591 | u64 address_end; |
5694703f JR |
592 | |
593 | /* required protection */ | |
8d283c35 JR |
594 | int prot; |
595 | }; | |
596 | ||
5694703f JR |
597 | /* |
598 | * List of all unity mappings. It is not locked because as runtime it is only | |
599 | * read. It is created at ACPI table parsing time. | |
600 | */ | |
8d283c35 JR |
601 | extern struct list_head amd_iommu_unity_map; |
602 | ||
5694703f JR |
603 | /* |
604 | * Data structures for device handling | |
605 | */ | |
606 | ||
607 | /* | |
608 | * Device table used by hardware. Read and write accesses by software are | |
609 | * locked with the amd_iommu_pd_table lock. | |
610 | */ | |
8d283c35 | 611 | extern struct dev_table_entry *amd_iommu_dev_table; |
5694703f JR |
612 | |
613 | /* | |
614 | * Alias table to find requestor ids to device ids. Not locked because only | |
615 | * read on runtime. | |
616 | */ | |
8d283c35 | 617 | extern u16 *amd_iommu_alias_table; |
5694703f JR |
618 | |
619 | /* | |
620 | * Reverse lookup table to find the IOMMU which translates a specific device. | |
621 | */ | |
8d283c35 JR |
622 | extern struct amd_iommu **amd_iommu_rlookup_table; |
623 | ||
5694703f | 624 | /* size of the dma_ops aperture as power of 2 */ |
8d283c35 JR |
625 | extern unsigned amd_iommu_aperture_order; |
626 | ||
5694703f | 627 | /* largest PCI device id we expect translation requests for */ |
8d283c35 JR |
628 | extern u16 amd_iommu_last_bdf; |
629 | ||
5694703f | 630 | /* allocation bitmap for domain ids */ |
8d283c35 JR |
631 | extern unsigned long *amd_iommu_pd_alloc_bitmap; |
632 | ||
afa9fdc2 FT |
633 | /* |
634 | * If true, the addresses will be flushed on unmap time, not when | |
635 | * they are reused | |
636 | */ | |
637 | extern bool amd_iommu_unmap_flush; | |
638 | ||
62f71abb JR |
639 | /* Smallest number of PASIDs supported by any IOMMU in the system */ |
640 | extern u32 amd_iommu_max_pasids; | |
641 | ||
400a28a0 JR |
642 | extern bool amd_iommu_v2_present; |
643 | ||
5abcdba4 JR |
644 | extern bool amd_iommu_force_isolation; |
645 | ||
52815b75 JR |
646 | /* Max levels of glxval supported */ |
647 | extern int amd_iommu_max_glx_val; | |
648 | ||
d591b0a3 JR |
649 | /* takes bus and device/function and returns the device id |
650 | * FIXME: should that be in generic PCI code? */ | |
651 | static inline u16 calc_devid(u8 bus, u8 devfn) | |
652 | { | |
653 | return (((u16)bus) << 8) | devfn; | |
654 | } | |
655 | ||
a9dddbe0 JR |
656 | #ifdef CONFIG_AMD_IOMMU_STATS |
657 | ||
658 | struct __iommu_counter { | |
659 | char *name; | |
660 | struct dentry *dent; | |
661 | u64 value; | |
662 | }; | |
663 | ||
664 | #define DECLARE_STATS_COUNTER(nm) \ | |
665 | static struct __iommu_counter nm = { \ | |
666 | .name = #nm, \ | |
667 | } | |
668 | ||
669 | #define INC_STATS_COUNTER(name) name.value += 1 | |
670 | #define ADD_STATS_COUNTER(name, x) name.value += (x) | |
671 | #define SUB_STATS_COUNTER(name, x) name.value -= (x) | |
672 | ||
673 | #else /* CONFIG_AMD_IOMMU_STATS */ | |
674 | ||
675 | #define DECLARE_STATS_COUNTER(name) | |
676 | #define INC_STATS_COUNTER(name) | |
677 | #define ADD_STATS_COUNTER(name, x) | |
678 | #define SUB_STATS_COUNTER(name, x) | |
679 | ||
680 | #endif /* CONFIG_AMD_IOMMU_STATS */ | |
681 | ||
1965aae3 | 682 | #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ |