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e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
48 | struct task_struct *task; /* Task bound to this PASID */ | |
49 | struct mm_struct *mm; /* mm_struct for the faults */ | |
8736b2c3 | 50 | struct mmu_notifier mn; /* mmu_otifier handle */ |
ed96f228 JR |
51 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
52 | struct device_state *device_state; /* Link to our device_state */ | |
53 | int pasid; /* PASID index */ | |
028eeacc JR |
54 | spinlock_t lock; /* Protect pri_queues */ |
55 | wait_queue_head_t wq; /* To wait for count == 0 */ | |
ed96f228 JR |
56 | }; |
57 | ||
58 | struct device_state { | |
59 | atomic_t count; | |
60 | struct pci_dev *pdev; | |
61 | struct pasid_state **states; | |
62 | struct iommu_domain *domain; | |
63 | int pasid_levels; | |
64 | int max_pasids; | |
65 | spinlock_t lock; | |
028eeacc JR |
66 | wait_queue_head_t wq; |
67 | }; | |
68 | ||
69 | struct fault { | |
70 | struct work_struct work; | |
71 | struct device_state *dev_state; | |
72 | struct pasid_state *state; | |
73 | struct mm_struct *mm; | |
74 | u64 address; | |
75 | u16 devid; | |
76 | u16 pasid; | |
77 | u16 tag; | |
78 | u16 finish; | |
79 | u16 flags; | |
ed96f228 JR |
80 | }; |
81 | ||
82 | struct device_state **state_table; | |
83 | static spinlock_t state_lock; | |
84 | ||
85 | /* List and lock for all pasid_states */ | |
86 | static LIST_HEAD(pasid_state_list); | |
2d5503b6 JR |
87 | static DEFINE_SPINLOCK(ps_lock); |
88 | ||
028eeacc JR |
89 | static struct workqueue_struct *iommu_wq; |
90 | ||
8736b2c3 JR |
91 | /* |
92 | * Empty page table - Used between | |
93 | * mmu_notifier_invalidate_range_start and | |
94 | * mmu_notifier_invalidate_range_end | |
95 | */ | |
96 | static u64 *empty_page_table; | |
97 | ||
2d5503b6 JR |
98 | static void free_pasid_states(struct device_state *dev_state); |
99 | static void unbind_pasid(struct device_state *dev_state, int pasid); | |
8736b2c3 | 100 | static int task_exit(struct notifier_block *nb, unsigned long e, void *data); |
ed96f228 JR |
101 | |
102 | static u16 device_id(struct pci_dev *pdev) | |
103 | { | |
104 | u16 devid; | |
105 | ||
106 | devid = pdev->bus->number; | |
107 | devid = (devid << 8) | pdev->devfn; | |
108 | ||
109 | return devid; | |
110 | } | |
111 | ||
112 | static struct device_state *get_device_state(u16 devid) | |
113 | { | |
114 | struct device_state *dev_state; | |
115 | unsigned long flags; | |
116 | ||
117 | spin_lock_irqsave(&state_lock, flags); | |
118 | dev_state = state_table[devid]; | |
119 | if (dev_state != NULL) | |
120 | atomic_inc(&dev_state->count); | |
121 | spin_unlock_irqrestore(&state_lock, flags); | |
122 | ||
123 | return dev_state; | |
124 | } | |
125 | ||
126 | static void free_device_state(struct device_state *dev_state) | |
127 | { | |
2d5503b6 JR |
128 | /* |
129 | * First detach device from domain - No more PRI requests will arrive | |
130 | * from that device after it is unbound from the IOMMUv2 domain. | |
131 | */ | |
ed96f228 | 132 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
133 | |
134 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 135 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
136 | |
137 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
138 | kfree(dev_state); |
139 | } | |
140 | ||
141 | static void put_device_state(struct device_state *dev_state) | |
142 | { | |
143 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 144 | wake_up(&dev_state->wq); |
ed96f228 JR |
145 | } |
146 | ||
028eeacc JR |
147 | static void put_device_state_wait(struct device_state *dev_state) |
148 | { | |
149 | DEFINE_WAIT(wait); | |
150 | ||
151 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
152 | if (!atomic_dec_and_test(&dev_state->count)) | |
153 | schedule(); | |
154 | finish_wait(&dev_state->wq, &wait); | |
155 | ||
156 | free_device_state(dev_state); | |
157 | } | |
8736b2c3 JR |
158 | |
159 | static struct notifier_block profile_nb = { | |
160 | .notifier_call = task_exit, | |
161 | }; | |
162 | ||
2d5503b6 JR |
163 | static void link_pasid_state(struct pasid_state *pasid_state) |
164 | { | |
165 | spin_lock(&ps_lock); | |
166 | list_add_tail(&pasid_state->list, &pasid_state_list); | |
167 | spin_unlock(&ps_lock); | |
168 | } | |
169 | ||
170 | static void __unlink_pasid_state(struct pasid_state *pasid_state) | |
171 | { | |
172 | list_del(&pasid_state->list); | |
173 | } | |
174 | ||
175 | static void unlink_pasid_state(struct pasid_state *pasid_state) | |
176 | { | |
177 | spin_lock(&ps_lock); | |
178 | __unlink_pasid_state(pasid_state); | |
179 | spin_unlock(&ps_lock); | |
180 | } | |
181 | ||
182 | /* Must be called under dev_state->lock */ | |
183 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
184 | int pasid, bool alloc) | |
185 | { | |
186 | struct pasid_state **root, **ptr; | |
187 | int level, index; | |
188 | ||
189 | level = dev_state->pasid_levels; | |
190 | root = dev_state->states; | |
191 | ||
192 | while (true) { | |
193 | ||
194 | index = (pasid >> (9 * level)) & 0x1ff; | |
195 | ptr = &root[index]; | |
196 | ||
197 | if (level == 0) | |
198 | break; | |
199 | ||
200 | if (*ptr == NULL) { | |
201 | if (!alloc) | |
202 | return NULL; | |
203 | ||
204 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
205 | if (*ptr == NULL) | |
206 | return NULL; | |
207 | } | |
208 | ||
209 | root = (struct pasid_state **)*ptr; | |
210 | level -= 1; | |
211 | } | |
212 | ||
213 | return ptr; | |
214 | } | |
215 | ||
216 | static int set_pasid_state(struct device_state *dev_state, | |
217 | struct pasid_state *pasid_state, | |
218 | int pasid) | |
219 | { | |
220 | struct pasid_state **ptr; | |
221 | unsigned long flags; | |
222 | int ret; | |
223 | ||
224 | spin_lock_irqsave(&dev_state->lock, flags); | |
225 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
226 | ||
227 | ret = -ENOMEM; | |
228 | if (ptr == NULL) | |
229 | goto out_unlock; | |
230 | ||
231 | ret = -ENOMEM; | |
232 | if (*ptr != NULL) | |
233 | goto out_unlock; | |
234 | ||
235 | *ptr = pasid_state; | |
236 | ||
237 | ret = 0; | |
238 | ||
239 | out_unlock: | |
240 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
241 | ||
242 | return ret; | |
243 | } | |
244 | ||
245 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
246 | { | |
247 | struct pasid_state **ptr; | |
248 | unsigned long flags; | |
249 | ||
250 | spin_lock_irqsave(&dev_state->lock, flags); | |
251 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
252 | ||
253 | if (ptr == NULL) | |
254 | goto out_unlock; | |
255 | ||
256 | *ptr = NULL; | |
257 | ||
258 | out_unlock: | |
259 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
260 | } | |
261 | ||
262 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
263 | int pasid) | |
264 | { | |
265 | struct pasid_state **ptr, *ret = NULL; | |
266 | unsigned long flags; | |
267 | ||
268 | spin_lock_irqsave(&dev_state->lock, flags); | |
269 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
270 | ||
271 | if (ptr == NULL) | |
272 | goto out_unlock; | |
273 | ||
274 | ret = *ptr; | |
275 | if (ret) | |
276 | atomic_inc(&ret->count); | |
277 | ||
278 | out_unlock: | |
279 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
280 | ||
281 | return ret; | |
282 | } | |
283 | ||
284 | static void free_pasid_state(struct pasid_state *pasid_state) | |
285 | { | |
286 | kfree(pasid_state); | |
287 | } | |
288 | ||
289 | static void put_pasid_state(struct pasid_state *pasid_state) | |
290 | { | |
291 | if (atomic_dec_and_test(&pasid_state->count)) { | |
292 | put_device_state(pasid_state->device_state); | |
028eeacc | 293 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
294 | } |
295 | } | |
296 | ||
028eeacc JR |
297 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
298 | { | |
299 | DEFINE_WAIT(wait); | |
300 | ||
301 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
302 | ||
303 | if (atomic_dec_and_test(&pasid_state->count)) | |
304 | put_device_state(pasid_state->device_state); | |
305 | else | |
306 | schedule(); | |
307 | ||
308 | finish_wait(&pasid_state->wq, &wait); | |
309 | mmput(pasid_state->mm); | |
310 | free_pasid_state(pasid_state); | |
311 | } | |
312 | ||
8736b2c3 JR |
313 | static void __unbind_pasid(struct pasid_state *pasid_state) |
314 | { | |
315 | struct iommu_domain *domain; | |
316 | ||
317 | domain = pasid_state->device_state->domain; | |
318 | ||
319 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); | |
320 | clear_pasid_state(pasid_state->device_state, pasid_state->pasid); | |
321 | ||
322 | /* Make sure no more pending faults are in the queue */ | |
323 | flush_workqueue(iommu_wq); | |
324 | ||
325 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
326 | ||
327 | put_pasid_state(pasid_state); /* Reference taken in bind() function */ | |
328 | } | |
329 | ||
2d5503b6 JR |
330 | static void unbind_pasid(struct device_state *dev_state, int pasid) |
331 | { | |
332 | struct pasid_state *pasid_state; | |
333 | ||
334 | pasid_state = get_pasid_state(dev_state, pasid); | |
335 | if (pasid_state == NULL) | |
336 | return; | |
337 | ||
338 | unlink_pasid_state(pasid_state); | |
8736b2c3 JR |
339 | __unbind_pasid(pasid_state); |
340 | put_pasid_state_wait(pasid_state); /* Reference taken in this function */ | |
2d5503b6 JR |
341 | } |
342 | ||
343 | static void free_pasid_states_level1(struct pasid_state **tbl) | |
344 | { | |
345 | int i; | |
346 | ||
347 | for (i = 0; i < 512; ++i) { | |
348 | if (tbl[i] == NULL) | |
349 | continue; | |
350 | ||
351 | free_page((unsigned long)tbl[i]); | |
352 | } | |
353 | } | |
354 | ||
355 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
356 | { | |
357 | struct pasid_state **ptr; | |
358 | int i; | |
359 | ||
360 | for (i = 0; i < 512; ++i) { | |
361 | if (tbl[i] == NULL) | |
362 | continue; | |
363 | ||
364 | ptr = (struct pasid_state **)tbl[i]; | |
365 | free_pasid_states_level1(ptr); | |
366 | } | |
367 | } | |
368 | ||
369 | static void free_pasid_states(struct device_state *dev_state) | |
370 | { | |
371 | struct pasid_state *pasid_state; | |
372 | int i; | |
373 | ||
374 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
375 | pasid_state = get_pasid_state(dev_state, i); | |
376 | if (pasid_state == NULL) | |
377 | continue; | |
378 | ||
2d5503b6 | 379 | put_pasid_state(pasid_state); |
028eeacc | 380 | unbind_pasid(dev_state, i); |
2d5503b6 JR |
381 | } |
382 | ||
383 | if (dev_state->pasid_levels == 2) | |
384 | free_pasid_states_level2(dev_state->states); | |
385 | else if (dev_state->pasid_levels == 1) | |
386 | free_pasid_states_level1(dev_state->states); | |
387 | else if (dev_state->pasid_levels != 0) | |
388 | BUG(); | |
389 | ||
390 | free_page((unsigned long)dev_state->states); | |
391 | } | |
392 | ||
8736b2c3 JR |
393 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
394 | { | |
395 | return container_of(mn, struct pasid_state, mn); | |
396 | } | |
397 | ||
398 | static void __mn_flush_page(struct mmu_notifier *mn, | |
399 | unsigned long address) | |
400 | { | |
401 | struct pasid_state *pasid_state; | |
402 | struct device_state *dev_state; | |
403 | ||
404 | pasid_state = mn_to_state(mn); | |
405 | dev_state = pasid_state->device_state; | |
406 | ||
407 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
408 | } | |
409 | ||
410 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
411 | struct mm_struct *mm, | |
412 | unsigned long address) | |
413 | { | |
414 | __mn_flush_page(mn, address); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static void mn_change_pte(struct mmu_notifier *mn, | |
420 | struct mm_struct *mm, | |
421 | unsigned long address, | |
422 | pte_t pte) | |
423 | { | |
424 | __mn_flush_page(mn, address); | |
425 | } | |
426 | ||
427 | static void mn_invalidate_page(struct mmu_notifier *mn, | |
428 | struct mm_struct *mm, | |
429 | unsigned long address) | |
430 | { | |
431 | __mn_flush_page(mn, address); | |
432 | } | |
433 | ||
434 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
435 | struct mm_struct *mm, | |
436 | unsigned long start, unsigned long end) | |
437 | { | |
438 | struct pasid_state *pasid_state; | |
439 | struct device_state *dev_state; | |
440 | ||
441 | pasid_state = mn_to_state(mn); | |
442 | dev_state = pasid_state->device_state; | |
443 | ||
444 | amd_iommu_domain_set_gcr3(dev_state->domain, pasid_state->pasid, | |
445 | __pa(empty_page_table)); | |
446 | } | |
447 | ||
448 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
449 | struct mm_struct *mm, | |
450 | unsigned long start, unsigned long end) | |
451 | { | |
452 | struct pasid_state *pasid_state; | |
453 | struct device_state *dev_state; | |
454 | ||
455 | pasid_state = mn_to_state(mn); | |
456 | dev_state = pasid_state->device_state; | |
457 | ||
458 | amd_iommu_domain_set_gcr3(dev_state->domain, pasid_state->pasid, | |
459 | __pa(pasid_state->mm->pgd)); | |
460 | } | |
461 | ||
462 | static struct mmu_notifier_ops iommu_mn = { | |
463 | .clear_flush_young = mn_clear_flush_young, | |
464 | .change_pte = mn_change_pte, | |
465 | .invalidate_page = mn_invalidate_page, | |
466 | .invalidate_range_start = mn_invalidate_range_start, | |
467 | .invalidate_range_end = mn_invalidate_range_end, | |
468 | }; | |
469 | ||
028eeacc JR |
470 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
471 | u16 tag, int status) | |
472 | { | |
473 | unsigned long flags; | |
474 | ||
475 | spin_lock_irqsave(&pasid_state->lock, flags); | |
476 | pasid_state->pri[tag].status = status; | |
477 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
478 | } | |
479 | ||
480 | static void finish_pri_tag(struct device_state *dev_state, | |
481 | struct pasid_state *pasid_state, | |
482 | u16 tag) | |
483 | { | |
484 | unsigned long flags; | |
485 | ||
486 | spin_lock_irqsave(&pasid_state->lock, flags); | |
487 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
488 | pasid_state->pri[tag].finish) { | |
489 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
490 | pasid_state->pri[tag].status, tag); | |
491 | pasid_state->pri[tag].finish = false; | |
492 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
493 | } | |
494 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
495 | } | |
496 | ||
497 | static void do_fault(struct work_struct *work) | |
498 | { | |
499 | struct fault *fault = container_of(work, struct fault, work); | |
500 | int npages, write; | |
501 | struct page *page; | |
502 | ||
503 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
504 | ||
505 | npages = get_user_pages(fault->state->task, fault->state->mm, | |
506 | fault->address, 1, write, 0, &page, NULL); | |
507 | ||
508 | if (npages == 1) | |
509 | put_page(page); | |
510 | else | |
511 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
512 | ||
513 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
514 | ||
515 | put_pasid_state(fault->state); | |
516 | ||
517 | kfree(fault); | |
518 | } | |
519 | ||
520 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
521 | { | |
522 | struct amd_iommu_fault *iommu_fault; | |
523 | struct pasid_state *pasid_state; | |
524 | struct device_state *dev_state; | |
525 | unsigned long flags; | |
526 | struct fault *fault; | |
527 | bool finish; | |
528 | u16 tag; | |
529 | int ret; | |
530 | ||
531 | iommu_fault = data; | |
532 | tag = iommu_fault->tag & 0x1ff; | |
533 | finish = (iommu_fault->tag >> 9) & 1; | |
534 | ||
535 | ret = NOTIFY_DONE; | |
536 | dev_state = get_device_state(iommu_fault->device_id); | |
537 | if (dev_state == NULL) | |
538 | goto out; | |
539 | ||
540 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
541 | if (pasid_state == NULL) { | |
542 | /* We know the device but not the PASID -> send INVALID */ | |
543 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
544 | PPR_INVALID, tag); | |
545 | goto out_drop_state; | |
546 | } | |
547 | ||
548 | spin_lock_irqsave(&pasid_state->lock, flags); | |
549 | atomic_inc(&pasid_state->pri[tag].inflight); | |
550 | if (finish) | |
551 | pasid_state->pri[tag].finish = true; | |
552 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
553 | ||
554 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
555 | if (fault == NULL) { | |
556 | /* We are OOM - send success and let the device re-fault */ | |
557 | finish_pri_tag(dev_state, pasid_state, tag); | |
558 | goto out_drop_state; | |
559 | } | |
560 | ||
561 | fault->dev_state = dev_state; | |
562 | fault->address = iommu_fault->address; | |
563 | fault->state = pasid_state; | |
564 | fault->tag = tag; | |
565 | fault->finish = finish; | |
566 | fault->flags = iommu_fault->flags; | |
567 | INIT_WORK(&fault->work, do_fault); | |
568 | ||
569 | queue_work(iommu_wq, &fault->work); | |
570 | ||
571 | ret = NOTIFY_OK; | |
572 | ||
573 | out_drop_state: | |
574 | put_device_state(dev_state); | |
575 | ||
576 | out: | |
577 | return ret; | |
578 | } | |
579 | ||
580 | static struct notifier_block ppr_nb = { | |
581 | .notifier_call = ppr_notifier, | |
582 | }; | |
583 | ||
8736b2c3 JR |
584 | static int task_exit(struct notifier_block *nb, unsigned long e, void *data) |
585 | { | |
586 | struct pasid_state *pasid_state; | |
587 | struct task_struct *task; | |
588 | ||
589 | task = data; | |
590 | ||
591 | /* | |
592 | * Using this notifier is a hack - but there is no other choice | |
593 | * at the moment. What I really want is a sleeping notifier that | |
594 | * is called when an MM goes down. But such a notifier doesn't | |
595 | * exist yet. The notifier needs to sleep because it has to make | |
596 | * sure that the device does not use the PASID and the address | |
597 | * space anymore before it is destroyed. This includes waiting | |
598 | * for pending PRI requests to pass the workqueue. The | |
599 | * MMU-Notifiers would be a good fit, but they use RCU and so | |
600 | * they are not allowed to sleep. Lets see how we can solve this | |
601 | * in a more intelligent way in the future. | |
602 | */ | |
603 | again: | |
604 | spin_lock(&ps_lock); | |
605 | list_for_each_entry(pasid_state, &pasid_state_list, list) { | |
606 | struct device_state *dev_state; | |
607 | int pasid; | |
608 | ||
609 | if (pasid_state->task != task) | |
610 | continue; | |
611 | ||
612 | /* Drop Lock and unbind */ | |
613 | spin_unlock(&ps_lock); | |
614 | ||
615 | dev_state = pasid_state->device_state; | |
616 | pasid = pasid_state->pasid; | |
617 | ||
618 | unbind_pasid(dev_state, pasid); | |
619 | ||
620 | /* Task may be in the list multiple times */ | |
621 | goto again; | |
622 | } | |
623 | spin_unlock(&ps_lock); | |
624 | ||
625 | return NOTIFY_OK; | |
626 | } | |
627 | ||
2d5503b6 JR |
628 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
629 | struct task_struct *task) | |
630 | { | |
631 | struct pasid_state *pasid_state; | |
632 | struct device_state *dev_state; | |
633 | u16 devid; | |
634 | int ret; | |
635 | ||
636 | might_sleep(); | |
637 | ||
638 | if (!amd_iommu_v2_supported()) | |
639 | return -ENODEV; | |
640 | ||
641 | devid = device_id(pdev); | |
642 | dev_state = get_device_state(devid); | |
643 | ||
644 | if (dev_state == NULL) | |
645 | return -EINVAL; | |
646 | ||
647 | ret = -EINVAL; | |
648 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
649 | goto out; | |
650 | ||
651 | ret = -ENOMEM; | |
652 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
653 | if (pasid_state == NULL) | |
654 | goto out; | |
655 | ||
656 | atomic_set(&pasid_state->count, 1); | |
028eeacc | 657 | init_waitqueue_head(&pasid_state->wq); |
2d5503b6 JR |
658 | pasid_state->task = task; |
659 | pasid_state->mm = get_task_mm(task); | |
660 | pasid_state->device_state = dev_state; | |
661 | pasid_state->pasid = pasid; | |
8736b2c3 | 662 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
663 | |
664 | if (pasid_state->mm == NULL) | |
665 | goto out_free; | |
666 | ||
8736b2c3 JR |
667 | mmu_notifier_register(&pasid_state->mn, pasid_state->mm); |
668 | ||
2d5503b6 JR |
669 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
670 | if (ret) | |
8736b2c3 | 671 | goto out_unregister; |
2d5503b6 JR |
672 | |
673 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
674 | __pa(pasid_state->mm->pgd)); | |
675 | if (ret) | |
676 | goto out_clear_state; | |
677 | ||
678 | link_pasid_state(pasid_state); | |
679 | ||
680 | return 0; | |
681 | ||
682 | out_clear_state: | |
683 | clear_pasid_state(dev_state, pasid); | |
684 | ||
8736b2c3 JR |
685 | out_unregister: |
686 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
687 | ||
2d5503b6 | 688 | out_free: |
028eeacc | 689 | free_pasid_state(pasid_state); |
2d5503b6 JR |
690 | |
691 | out: | |
692 | put_device_state(dev_state); | |
693 | ||
694 | return ret; | |
695 | } | |
696 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
697 | ||
698 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
699 | { | |
700 | struct device_state *dev_state; | |
701 | u16 devid; | |
702 | ||
703 | might_sleep(); | |
704 | ||
705 | if (!amd_iommu_v2_supported()) | |
706 | return; | |
707 | ||
708 | devid = device_id(pdev); | |
709 | dev_state = get_device_state(devid); | |
710 | if (dev_state == NULL) | |
711 | return; | |
712 | ||
713 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
714 | goto out; | |
715 | ||
716 | unbind_pasid(dev_state, pasid); | |
717 | ||
718 | out: | |
719 | put_device_state(dev_state); | |
720 | } | |
721 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
722 | ||
ed96f228 JR |
723 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
724 | { | |
725 | struct device_state *dev_state; | |
726 | unsigned long flags; | |
727 | int ret, tmp; | |
728 | u16 devid; | |
729 | ||
730 | might_sleep(); | |
731 | ||
732 | if (!amd_iommu_v2_supported()) | |
733 | return -ENODEV; | |
734 | ||
735 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
736 | return -EINVAL; | |
737 | ||
738 | devid = device_id(pdev); | |
739 | ||
740 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
741 | if (dev_state == NULL) | |
742 | return -ENOMEM; | |
743 | ||
744 | spin_lock_init(&dev_state->lock); | |
028eeacc | 745 | init_waitqueue_head(&dev_state->wq); |
ed96f228 JR |
746 | dev_state->pdev = pdev; |
747 | ||
748 | tmp = pasids; | |
749 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
750 | dev_state->pasid_levels += 1; | |
751 | ||
752 | atomic_set(&dev_state->count, 1); | |
753 | dev_state->max_pasids = pasids; | |
754 | ||
755 | ret = -ENOMEM; | |
756 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
757 | if (dev_state->states == NULL) | |
758 | goto out_free_dev_state; | |
759 | ||
760 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
761 | if (dev_state->domain == NULL) | |
762 | goto out_free_states; | |
763 | ||
764 | amd_iommu_domain_direct_map(dev_state->domain); | |
765 | ||
766 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
767 | if (ret) | |
768 | goto out_free_domain; | |
769 | ||
770 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
771 | if (ret != 0) | |
772 | goto out_free_domain; | |
773 | ||
774 | spin_lock_irqsave(&state_lock, flags); | |
775 | ||
776 | if (state_table[devid] != NULL) { | |
777 | spin_unlock_irqrestore(&state_lock, flags); | |
778 | ret = -EBUSY; | |
779 | goto out_free_domain; | |
780 | } | |
781 | ||
782 | state_table[devid] = dev_state; | |
783 | ||
784 | spin_unlock_irqrestore(&state_lock, flags); | |
785 | ||
786 | return 0; | |
787 | ||
788 | out_free_domain: | |
789 | iommu_domain_free(dev_state->domain); | |
790 | ||
791 | out_free_states: | |
792 | free_page((unsigned long)dev_state->states); | |
793 | ||
794 | out_free_dev_state: | |
795 | kfree(dev_state); | |
796 | ||
797 | return ret; | |
798 | } | |
799 | EXPORT_SYMBOL(amd_iommu_init_device); | |
800 | ||
801 | void amd_iommu_free_device(struct pci_dev *pdev) | |
802 | { | |
803 | struct device_state *dev_state; | |
804 | unsigned long flags; | |
805 | u16 devid; | |
806 | ||
807 | if (!amd_iommu_v2_supported()) | |
808 | return; | |
809 | ||
810 | devid = device_id(pdev); | |
811 | ||
812 | spin_lock_irqsave(&state_lock, flags); | |
813 | ||
814 | dev_state = state_table[devid]; | |
815 | if (dev_state == NULL) { | |
816 | spin_unlock_irqrestore(&state_lock, flags); | |
817 | return; | |
818 | } | |
819 | ||
820 | state_table[devid] = NULL; | |
821 | ||
822 | spin_unlock_irqrestore(&state_lock, flags); | |
823 | ||
2d5503b6 JR |
824 | /* Get rid of any remaining pasid states */ |
825 | free_pasid_states(dev_state); | |
826 | ||
028eeacc | 827 | put_device_state_wait(dev_state); |
ed96f228 JR |
828 | } |
829 | EXPORT_SYMBOL(amd_iommu_free_device); | |
830 | ||
e3c495c7 JR |
831 | static int __init amd_iommu_v2_init(void) |
832 | { | |
ed96f228 | 833 | size_t state_table_size; |
028eeacc | 834 | int ret; |
ed96f228 | 835 | |
e3c495c7 JR |
836 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>"); |
837 | ||
ed96f228 JR |
838 | spin_lock_init(&state_lock); |
839 | ||
840 | state_table_size = MAX_DEVICES * sizeof(struct device_state *); | |
841 | state_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, | |
842 | get_order(state_table_size)); | |
843 | if (state_table == NULL) | |
844 | return -ENOMEM; | |
845 | ||
028eeacc JR |
846 | ret = -ENOMEM; |
847 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 848 | if (iommu_wq == NULL) |
028eeacc | 849 | goto out_free; |
8736b2c3 JR |
850 | |
851 | ret = -ENOMEM; | |
852 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
853 | if (empty_page_table == NULL) | |
854 | goto out_destroy_wq; | |
028eeacc JR |
855 | |
856 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
8736b2c3 | 857 | profile_event_register(PROFILE_TASK_EXIT, &profile_nb); |
028eeacc | 858 | |
e3c495c7 | 859 | return 0; |
028eeacc | 860 | |
8736b2c3 JR |
861 | out_destroy_wq: |
862 | destroy_workqueue(iommu_wq); | |
863 | ||
028eeacc JR |
864 | out_free: |
865 | free_pages((unsigned long)state_table, get_order(state_table_size)); | |
866 | ||
867 | return ret; | |
e3c495c7 JR |
868 | } |
869 | ||
870 | static void __exit amd_iommu_v2_exit(void) | |
871 | { | |
ed96f228 JR |
872 | struct device_state *dev_state; |
873 | size_t state_table_size; | |
874 | int i; | |
875 | ||
8736b2c3 | 876 | profile_event_unregister(PROFILE_TASK_EXIT, &profile_nb); |
028eeacc JR |
877 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
878 | ||
879 | flush_workqueue(iommu_wq); | |
880 | ||
881 | /* | |
882 | * The loop below might call flush_workqueue(), so call | |
883 | * destroy_workqueue() after it | |
884 | */ | |
ed96f228 JR |
885 | for (i = 0; i < MAX_DEVICES; ++i) { |
886 | dev_state = get_device_state(i); | |
887 | ||
888 | if (dev_state == NULL) | |
889 | continue; | |
890 | ||
891 | WARN_ON_ONCE(1); | |
892 | ||
ed96f228 | 893 | put_device_state(dev_state); |
028eeacc | 894 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
895 | } |
896 | ||
028eeacc JR |
897 | destroy_workqueue(iommu_wq); |
898 | ||
ed96f228 JR |
899 | state_table_size = MAX_DEVICES * sizeof(struct device_state *); |
900 | free_pages((unsigned long)state_table, get_order(state_table_size)); | |
8736b2c3 JR |
901 | |
902 | free_page((unsigned long)empty_page_table); | |
e3c495c7 JR |
903 | } |
904 | ||
905 | module_init(amd_iommu_v2_init); | |
906 | module_exit(amd_iommu_v2_exit); |