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e3c495c7 JR |
1 | /* |
2 | * Copyright (C) 2010-2012 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
8736b2c3 | 19 | #include <linux/mmu_notifier.h> |
ed96f228 JR |
20 | #include <linux/amd-iommu.h> |
21 | #include <linux/mm_types.h> | |
8736b2c3 | 22 | #include <linux/profile.h> |
e3c495c7 | 23 | #include <linux/module.h> |
2d5503b6 | 24 | #include <linux/sched.h> |
ed96f228 | 25 | #include <linux/iommu.h> |
028eeacc | 26 | #include <linux/wait.h> |
ed96f228 JR |
27 | #include <linux/pci.h> |
28 | #include <linux/gfp.h> | |
29 | ||
028eeacc | 30 | #include "amd_iommu_types.h" |
ed96f228 | 31 | #include "amd_iommu_proto.h" |
e3c495c7 JR |
32 | |
33 | MODULE_LICENSE("GPL v2"); | |
34 | MODULE_AUTHOR("Joerg Roedel <joerg.roedel@amd.com>"); | |
35 | ||
ed96f228 JR |
36 | #define MAX_DEVICES 0x10000 |
37 | #define PRI_QUEUE_SIZE 512 | |
38 | ||
39 | struct pri_queue { | |
40 | atomic_t inflight; | |
41 | bool finish; | |
028eeacc | 42 | int status; |
ed96f228 JR |
43 | }; |
44 | ||
45 | struct pasid_state { | |
46 | struct list_head list; /* For global state-list */ | |
47 | atomic_t count; /* Reference count */ | |
d73a6d72 | 48 | unsigned mmu_notifier_count; /* Counting nested mmu_notifier |
e79df31c | 49 | calls */ |
ed96f228 JR |
50 | struct task_struct *task; /* Task bound to this PASID */ |
51 | struct mm_struct *mm; /* mm_struct for the faults */ | |
ff6d0cce | 52 | struct mmu_notifier mn; /* mmu_notifier handle */ |
ed96f228 JR |
53 | struct pri_queue pri[PRI_QUEUE_SIZE]; /* PRI tag states */ |
54 | struct device_state *device_state; /* Link to our device_state */ | |
55 | int pasid; /* PASID index */ | |
d73a6d72 JR |
56 | spinlock_t lock; /* Protect pri_queues and |
57 | mmu_notifer_count */ | |
028eeacc | 58 | wait_queue_head_t wq; /* To wait for count == 0 */ |
ed96f228 JR |
59 | }; |
60 | ||
61 | struct device_state { | |
741669c7 JR |
62 | struct list_head list; |
63 | u16 devid; | |
ed96f228 JR |
64 | atomic_t count; |
65 | struct pci_dev *pdev; | |
66 | struct pasid_state **states; | |
67 | struct iommu_domain *domain; | |
68 | int pasid_levels; | |
69 | int max_pasids; | |
175d6146 | 70 | amd_iommu_invalid_ppr_cb inv_ppr_cb; |
bc21662f | 71 | amd_iommu_invalidate_ctx inv_ctx_cb; |
ed96f228 | 72 | spinlock_t lock; |
028eeacc JR |
73 | wait_queue_head_t wq; |
74 | }; | |
75 | ||
76 | struct fault { | |
77 | struct work_struct work; | |
78 | struct device_state *dev_state; | |
79 | struct pasid_state *state; | |
80 | struct mm_struct *mm; | |
81 | u64 address; | |
82 | u16 devid; | |
83 | u16 pasid; | |
84 | u16 tag; | |
85 | u16 finish; | |
86 | u16 flags; | |
ed96f228 JR |
87 | }; |
88 | ||
741669c7 | 89 | static LIST_HEAD(state_list); |
ed96f228 JR |
90 | static spinlock_t state_lock; |
91 | ||
028eeacc JR |
92 | static struct workqueue_struct *iommu_wq; |
93 | ||
8736b2c3 JR |
94 | /* |
95 | * Empty page table - Used between | |
96 | * mmu_notifier_invalidate_range_start and | |
97 | * mmu_notifier_invalidate_range_end | |
98 | */ | |
99 | static u64 *empty_page_table; | |
100 | ||
2d5503b6 JR |
101 | static void free_pasid_states(struct device_state *dev_state); |
102 | static void unbind_pasid(struct device_state *dev_state, int pasid); | |
ed96f228 JR |
103 | |
104 | static u16 device_id(struct pci_dev *pdev) | |
105 | { | |
106 | u16 devid; | |
107 | ||
108 | devid = pdev->bus->number; | |
109 | devid = (devid << 8) | pdev->devfn; | |
110 | ||
111 | return devid; | |
112 | } | |
113 | ||
b87d2d7c JR |
114 | static struct device_state *__get_device_state(u16 devid) |
115 | { | |
741669c7 JR |
116 | struct device_state *dev_state; |
117 | ||
118 | list_for_each_entry(dev_state, &state_list, list) { | |
119 | if (dev_state->devid == devid) | |
120 | return dev_state; | |
121 | } | |
122 | ||
123 | return NULL; | |
b87d2d7c JR |
124 | } |
125 | ||
ed96f228 JR |
126 | static struct device_state *get_device_state(u16 devid) |
127 | { | |
128 | struct device_state *dev_state; | |
129 | unsigned long flags; | |
130 | ||
131 | spin_lock_irqsave(&state_lock, flags); | |
b87d2d7c | 132 | dev_state = __get_device_state(devid); |
ed96f228 JR |
133 | if (dev_state != NULL) |
134 | atomic_inc(&dev_state->count); | |
135 | spin_unlock_irqrestore(&state_lock, flags); | |
136 | ||
137 | return dev_state; | |
138 | } | |
139 | ||
140 | static void free_device_state(struct device_state *dev_state) | |
141 | { | |
2d5503b6 JR |
142 | /* |
143 | * First detach device from domain - No more PRI requests will arrive | |
144 | * from that device after it is unbound from the IOMMUv2 domain. | |
145 | */ | |
ed96f228 | 146 | iommu_detach_device(dev_state->domain, &dev_state->pdev->dev); |
2d5503b6 JR |
147 | |
148 | /* Everything is down now, free the IOMMUv2 domain */ | |
ed96f228 | 149 | iommu_domain_free(dev_state->domain); |
2d5503b6 JR |
150 | |
151 | /* Finally get rid of the device-state */ | |
ed96f228 JR |
152 | kfree(dev_state); |
153 | } | |
154 | ||
155 | static void put_device_state(struct device_state *dev_state) | |
156 | { | |
157 | if (atomic_dec_and_test(&dev_state->count)) | |
028eeacc | 158 | wake_up(&dev_state->wq); |
ed96f228 JR |
159 | } |
160 | ||
028eeacc JR |
161 | static void put_device_state_wait(struct device_state *dev_state) |
162 | { | |
163 | DEFINE_WAIT(wait); | |
164 | ||
165 | prepare_to_wait(&dev_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
166 | if (!atomic_dec_and_test(&dev_state->count)) | |
167 | schedule(); | |
168 | finish_wait(&dev_state->wq, &wait); | |
169 | ||
170 | free_device_state(dev_state); | |
171 | } | |
8736b2c3 | 172 | |
2d5503b6 JR |
173 | /* Must be called under dev_state->lock */ |
174 | static struct pasid_state **__get_pasid_state_ptr(struct device_state *dev_state, | |
175 | int pasid, bool alloc) | |
176 | { | |
177 | struct pasid_state **root, **ptr; | |
178 | int level, index; | |
179 | ||
180 | level = dev_state->pasid_levels; | |
181 | root = dev_state->states; | |
182 | ||
183 | while (true) { | |
184 | ||
185 | index = (pasid >> (9 * level)) & 0x1ff; | |
186 | ptr = &root[index]; | |
187 | ||
188 | if (level == 0) | |
189 | break; | |
190 | ||
191 | if (*ptr == NULL) { | |
192 | if (!alloc) | |
193 | return NULL; | |
194 | ||
195 | *ptr = (void *)get_zeroed_page(GFP_ATOMIC); | |
196 | if (*ptr == NULL) | |
197 | return NULL; | |
198 | } | |
199 | ||
200 | root = (struct pasid_state **)*ptr; | |
201 | level -= 1; | |
202 | } | |
203 | ||
204 | return ptr; | |
205 | } | |
206 | ||
207 | static int set_pasid_state(struct device_state *dev_state, | |
208 | struct pasid_state *pasid_state, | |
209 | int pasid) | |
210 | { | |
211 | struct pasid_state **ptr; | |
212 | unsigned long flags; | |
213 | int ret; | |
214 | ||
215 | spin_lock_irqsave(&dev_state->lock, flags); | |
216 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
217 | ||
218 | ret = -ENOMEM; | |
219 | if (ptr == NULL) | |
220 | goto out_unlock; | |
221 | ||
222 | ret = -ENOMEM; | |
223 | if (*ptr != NULL) | |
224 | goto out_unlock; | |
225 | ||
226 | *ptr = pasid_state; | |
227 | ||
228 | ret = 0; | |
229 | ||
230 | out_unlock: | |
231 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
232 | ||
233 | return ret; | |
234 | } | |
235 | ||
236 | static void clear_pasid_state(struct device_state *dev_state, int pasid) | |
237 | { | |
238 | struct pasid_state **ptr; | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&dev_state->lock, flags); | |
242 | ptr = __get_pasid_state_ptr(dev_state, pasid, true); | |
243 | ||
244 | if (ptr == NULL) | |
245 | goto out_unlock; | |
246 | ||
247 | *ptr = NULL; | |
248 | ||
249 | out_unlock: | |
250 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
251 | } | |
252 | ||
253 | static struct pasid_state *get_pasid_state(struct device_state *dev_state, | |
254 | int pasid) | |
255 | { | |
256 | struct pasid_state **ptr, *ret = NULL; | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&dev_state->lock, flags); | |
260 | ptr = __get_pasid_state_ptr(dev_state, pasid, false); | |
261 | ||
262 | if (ptr == NULL) | |
263 | goto out_unlock; | |
264 | ||
265 | ret = *ptr; | |
266 | if (ret) | |
267 | atomic_inc(&ret->count); | |
268 | ||
269 | out_unlock: | |
270 | spin_unlock_irqrestore(&dev_state->lock, flags); | |
271 | ||
272 | return ret; | |
273 | } | |
274 | ||
275 | static void free_pasid_state(struct pasid_state *pasid_state) | |
276 | { | |
277 | kfree(pasid_state); | |
278 | } | |
279 | ||
280 | static void put_pasid_state(struct pasid_state *pasid_state) | |
281 | { | |
282 | if (atomic_dec_and_test(&pasid_state->count)) { | |
283 | put_device_state(pasid_state->device_state); | |
028eeacc | 284 | wake_up(&pasid_state->wq); |
2d5503b6 JR |
285 | } |
286 | } | |
287 | ||
028eeacc JR |
288 | static void put_pasid_state_wait(struct pasid_state *pasid_state) |
289 | { | |
290 | DEFINE_WAIT(wait); | |
291 | ||
292 | prepare_to_wait(&pasid_state->wq, &wait, TASK_UNINTERRUPTIBLE); | |
293 | ||
294 | if (atomic_dec_and_test(&pasid_state->count)) | |
295 | put_device_state(pasid_state->device_state); | |
296 | else | |
297 | schedule(); | |
298 | ||
299 | finish_wait(&pasid_state->wq, &wait); | |
300 | mmput(pasid_state->mm); | |
301 | free_pasid_state(pasid_state); | |
302 | } | |
303 | ||
8736b2c3 JR |
304 | static void __unbind_pasid(struct pasid_state *pasid_state) |
305 | { | |
306 | struct iommu_domain *domain; | |
307 | ||
308 | domain = pasid_state->device_state->domain; | |
309 | ||
310 | amd_iommu_domain_clear_gcr3(domain, pasid_state->pasid); | |
311 | clear_pasid_state(pasid_state->device_state, pasid_state->pasid); | |
312 | ||
313 | /* Make sure no more pending faults are in the queue */ | |
314 | flush_workqueue(iommu_wq); | |
315 | ||
8736b2c3 JR |
316 | put_pasid_state(pasid_state); /* Reference taken in bind() function */ |
317 | } | |
318 | ||
2d5503b6 JR |
319 | static void unbind_pasid(struct device_state *dev_state, int pasid) |
320 | { | |
321 | struct pasid_state *pasid_state; | |
322 | ||
323 | pasid_state = get_pasid_state(dev_state, pasid); | |
324 | if (pasid_state == NULL) | |
325 | return; | |
326 | ||
8736b2c3 JR |
327 | __unbind_pasid(pasid_state); |
328 | put_pasid_state_wait(pasid_state); /* Reference taken in this function */ | |
2d5503b6 JR |
329 | } |
330 | ||
331 | static void free_pasid_states_level1(struct pasid_state **tbl) | |
332 | { | |
333 | int i; | |
334 | ||
335 | for (i = 0; i < 512; ++i) { | |
336 | if (tbl[i] == NULL) | |
337 | continue; | |
338 | ||
339 | free_page((unsigned long)tbl[i]); | |
340 | } | |
341 | } | |
342 | ||
343 | static void free_pasid_states_level2(struct pasid_state **tbl) | |
344 | { | |
345 | struct pasid_state **ptr; | |
346 | int i; | |
347 | ||
348 | for (i = 0; i < 512; ++i) { | |
349 | if (tbl[i] == NULL) | |
350 | continue; | |
351 | ||
352 | ptr = (struct pasid_state **)tbl[i]; | |
353 | free_pasid_states_level1(ptr); | |
354 | } | |
355 | } | |
356 | ||
357 | static void free_pasid_states(struct device_state *dev_state) | |
358 | { | |
359 | struct pasid_state *pasid_state; | |
360 | int i; | |
361 | ||
362 | for (i = 0; i < dev_state->max_pasids; ++i) { | |
363 | pasid_state = get_pasid_state(dev_state, i); | |
364 | if (pasid_state == NULL) | |
365 | continue; | |
366 | ||
2d5503b6 | 367 | put_pasid_state(pasid_state); |
a40d4c67 JR |
368 | |
369 | /* | |
370 | * This will call the mn_release function and | |
371 | * unbind the PASID | |
372 | */ | |
373 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
2d5503b6 JR |
374 | } |
375 | ||
376 | if (dev_state->pasid_levels == 2) | |
377 | free_pasid_states_level2(dev_state->states); | |
378 | else if (dev_state->pasid_levels == 1) | |
379 | free_pasid_states_level1(dev_state->states); | |
380 | else if (dev_state->pasid_levels != 0) | |
381 | BUG(); | |
382 | ||
383 | free_page((unsigned long)dev_state->states); | |
384 | } | |
385 | ||
8736b2c3 JR |
386 | static struct pasid_state *mn_to_state(struct mmu_notifier *mn) |
387 | { | |
388 | return container_of(mn, struct pasid_state, mn); | |
389 | } | |
390 | ||
391 | static void __mn_flush_page(struct mmu_notifier *mn, | |
392 | unsigned long address) | |
393 | { | |
394 | struct pasid_state *pasid_state; | |
395 | struct device_state *dev_state; | |
396 | ||
397 | pasid_state = mn_to_state(mn); | |
398 | dev_state = pasid_state->device_state; | |
399 | ||
400 | amd_iommu_flush_page(dev_state->domain, pasid_state->pasid, address); | |
401 | } | |
402 | ||
403 | static int mn_clear_flush_young(struct mmu_notifier *mn, | |
404 | struct mm_struct *mm, | |
405 | unsigned long address) | |
406 | { | |
407 | __mn_flush_page(mn, address); | |
408 | ||
409 | return 0; | |
410 | } | |
411 | ||
412 | static void mn_change_pte(struct mmu_notifier *mn, | |
413 | struct mm_struct *mm, | |
414 | unsigned long address, | |
415 | pte_t pte) | |
416 | { | |
417 | __mn_flush_page(mn, address); | |
418 | } | |
419 | ||
420 | static void mn_invalidate_page(struct mmu_notifier *mn, | |
421 | struct mm_struct *mm, | |
422 | unsigned long address) | |
423 | { | |
424 | __mn_flush_page(mn, address); | |
425 | } | |
426 | ||
427 | static void mn_invalidate_range_start(struct mmu_notifier *mn, | |
428 | struct mm_struct *mm, | |
429 | unsigned long start, unsigned long end) | |
430 | { | |
431 | struct pasid_state *pasid_state; | |
432 | struct device_state *dev_state; | |
d73a6d72 | 433 | unsigned long flags; |
8736b2c3 JR |
434 | |
435 | pasid_state = mn_to_state(mn); | |
436 | dev_state = pasid_state->device_state; | |
437 | ||
d73a6d72 JR |
438 | spin_lock_irqsave(&pasid_state->lock, flags); |
439 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
440 | amd_iommu_domain_set_gcr3(dev_state->domain, |
441 | pasid_state->pasid, | |
442 | __pa(empty_page_table)); | |
443 | } | |
d73a6d72 JR |
444 | pasid_state->mmu_notifier_count += 1; |
445 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
8736b2c3 JR |
446 | } |
447 | ||
448 | static void mn_invalidate_range_end(struct mmu_notifier *mn, | |
449 | struct mm_struct *mm, | |
450 | unsigned long start, unsigned long end) | |
451 | { | |
452 | struct pasid_state *pasid_state; | |
453 | struct device_state *dev_state; | |
d73a6d72 | 454 | unsigned long flags; |
8736b2c3 JR |
455 | |
456 | pasid_state = mn_to_state(mn); | |
457 | dev_state = pasid_state->device_state; | |
458 | ||
d73a6d72 JR |
459 | spin_lock_irqsave(&pasid_state->lock, flags); |
460 | pasid_state->mmu_notifier_count -= 1; | |
461 | if (pasid_state->mmu_notifier_count == 0) { | |
e79df31c JR |
462 | amd_iommu_domain_set_gcr3(dev_state->domain, |
463 | pasid_state->pasid, | |
464 | __pa(pasid_state->mm->pgd)); | |
465 | } | |
d73a6d72 | 466 | spin_unlock_irqrestore(&pasid_state->lock, flags); |
8736b2c3 JR |
467 | } |
468 | ||
a40d4c67 JR |
469 | static void mn_release(struct mmu_notifier *mn, struct mm_struct *mm) |
470 | { | |
471 | struct pasid_state *pasid_state; | |
472 | struct device_state *dev_state; | |
473 | ||
474 | might_sleep(); | |
475 | ||
476 | pasid_state = mn_to_state(mn); | |
477 | dev_state = pasid_state->device_state; | |
478 | ||
479 | if (pasid_state->device_state->inv_ctx_cb) | |
480 | dev_state->inv_ctx_cb(dev_state->pdev, pasid_state->pasid); | |
481 | ||
482 | unbind_pasid(dev_state, pasid_state->pasid); | |
483 | } | |
484 | ||
8736b2c3 | 485 | static struct mmu_notifier_ops iommu_mn = { |
a40d4c67 | 486 | .release = mn_release, |
8736b2c3 JR |
487 | .clear_flush_young = mn_clear_flush_young, |
488 | .change_pte = mn_change_pte, | |
489 | .invalidate_page = mn_invalidate_page, | |
490 | .invalidate_range_start = mn_invalidate_range_start, | |
491 | .invalidate_range_end = mn_invalidate_range_end, | |
492 | }; | |
493 | ||
028eeacc JR |
494 | static void set_pri_tag_status(struct pasid_state *pasid_state, |
495 | u16 tag, int status) | |
496 | { | |
497 | unsigned long flags; | |
498 | ||
499 | spin_lock_irqsave(&pasid_state->lock, flags); | |
500 | pasid_state->pri[tag].status = status; | |
501 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
502 | } | |
503 | ||
504 | static void finish_pri_tag(struct device_state *dev_state, | |
505 | struct pasid_state *pasid_state, | |
506 | u16 tag) | |
507 | { | |
508 | unsigned long flags; | |
509 | ||
510 | spin_lock_irqsave(&pasid_state->lock, flags); | |
511 | if (atomic_dec_and_test(&pasid_state->pri[tag].inflight) && | |
512 | pasid_state->pri[tag].finish) { | |
513 | amd_iommu_complete_ppr(dev_state->pdev, pasid_state->pasid, | |
514 | pasid_state->pri[tag].status, tag); | |
515 | pasid_state->pri[tag].finish = false; | |
516 | pasid_state->pri[tag].status = PPR_SUCCESS; | |
517 | } | |
518 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
519 | } | |
520 | ||
521 | static void do_fault(struct work_struct *work) | |
522 | { | |
523 | struct fault *fault = container_of(work, struct fault, work); | |
524 | int npages, write; | |
525 | struct page *page; | |
526 | ||
527 | write = !!(fault->flags & PPR_FAULT_WRITE); | |
528 | ||
4378d992 | 529 | down_read(&fault->state->mm->mmap_sem); |
028eeacc JR |
530 | npages = get_user_pages(fault->state->task, fault->state->mm, |
531 | fault->address, 1, write, 0, &page, NULL); | |
4378d992 | 532 | up_read(&fault->state->mm->mmap_sem); |
028eeacc | 533 | |
175d6146 | 534 | if (npages == 1) { |
028eeacc | 535 | put_page(page); |
175d6146 JR |
536 | } else if (fault->dev_state->inv_ppr_cb) { |
537 | int status; | |
538 | ||
539 | status = fault->dev_state->inv_ppr_cb(fault->dev_state->pdev, | |
540 | fault->pasid, | |
541 | fault->address, | |
542 | fault->flags); | |
543 | switch (status) { | |
544 | case AMD_IOMMU_INV_PRI_RSP_SUCCESS: | |
545 | set_pri_tag_status(fault->state, fault->tag, PPR_SUCCESS); | |
546 | break; | |
547 | case AMD_IOMMU_INV_PRI_RSP_INVALID: | |
548 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); | |
549 | break; | |
550 | case AMD_IOMMU_INV_PRI_RSP_FAIL: | |
551 | set_pri_tag_status(fault->state, fault->tag, PPR_FAILURE); | |
552 | break; | |
553 | default: | |
554 | BUG(); | |
555 | } | |
556 | } else { | |
028eeacc | 557 | set_pri_tag_status(fault->state, fault->tag, PPR_INVALID); |
175d6146 | 558 | } |
028eeacc JR |
559 | |
560 | finish_pri_tag(fault->dev_state, fault->state, fault->tag); | |
561 | ||
562 | put_pasid_state(fault->state); | |
563 | ||
564 | kfree(fault); | |
565 | } | |
566 | ||
567 | static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) | |
568 | { | |
569 | struct amd_iommu_fault *iommu_fault; | |
570 | struct pasid_state *pasid_state; | |
571 | struct device_state *dev_state; | |
572 | unsigned long flags; | |
573 | struct fault *fault; | |
574 | bool finish; | |
575 | u16 tag; | |
576 | int ret; | |
577 | ||
578 | iommu_fault = data; | |
579 | tag = iommu_fault->tag & 0x1ff; | |
580 | finish = (iommu_fault->tag >> 9) & 1; | |
581 | ||
582 | ret = NOTIFY_DONE; | |
583 | dev_state = get_device_state(iommu_fault->device_id); | |
584 | if (dev_state == NULL) | |
585 | goto out; | |
586 | ||
587 | pasid_state = get_pasid_state(dev_state, iommu_fault->pasid); | |
588 | if (pasid_state == NULL) { | |
589 | /* We know the device but not the PASID -> send INVALID */ | |
590 | amd_iommu_complete_ppr(dev_state->pdev, iommu_fault->pasid, | |
591 | PPR_INVALID, tag); | |
592 | goto out_drop_state; | |
593 | } | |
594 | ||
595 | spin_lock_irqsave(&pasid_state->lock, flags); | |
596 | atomic_inc(&pasid_state->pri[tag].inflight); | |
597 | if (finish) | |
598 | pasid_state->pri[tag].finish = true; | |
599 | spin_unlock_irqrestore(&pasid_state->lock, flags); | |
600 | ||
601 | fault = kzalloc(sizeof(*fault), GFP_ATOMIC); | |
602 | if (fault == NULL) { | |
603 | /* We are OOM - send success and let the device re-fault */ | |
604 | finish_pri_tag(dev_state, pasid_state, tag); | |
605 | goto out_drop_state; | |
606 | } | |
607 | ||
608 | fault->dev_state = dev_state; | |
609 | fault->address = iommu_fault->address; | |
610 | fault->state = pasid_state; | |
611 | fault->tag = tag; | |
612 | fault->finish = finish; | |
b00675b8 | 613 | fault->pasid = iommu_fault->pasid; |
028eeacc JR |
614 | fault->flags = iommu_fault->flags; |
615 | INIT_WORK(&fault->work, do_fault); | |
616 | ||
617 | queue_work(iommu_wq, &fault->work); | |
618 | ||
619 | ret = NOTIFY_OK; | |
620 | ||
621 | out_drop_state: | |
622 | put_device_state(dev_state); | |
623 | ||
624 | out: | |
625 | return ret; | |
626 | } | |
627 | ||
628 | static struct notifier_block ppr_nb = { | |
629 | .notifier_call = ppr_notifier, | |
630 | }; | |
631 | ||
2d5503b6 JR |
632 | int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, |
633 | struct task_struct *task) | |
634 | { | |
635 | struct pasid_state *pasid_state; | |
636 | struct device_state *dev_state; | |
637 | u16 devid; | |
638 | int ret; | |
639 | ||
640 | might_sleep(); | |
641 | ||
642 | if (!amd_iommu_v2_supported()) | |
643 | return -ENODEV; | |
644 | ||
645 | devid = device_id(pdev); | |
646 | dev_state = get_device_state(devid); | |
647 | ||
648 | if (dev_state == NULL) | |
649 | return -EINVAL; | |
650 | ||
651 | ret = -EINVAL; | |
652 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
653 | goto out; | |
654 | ||
655 | ret = -ENOMEM; | |
656 | pasid_state = kzalloc(sizeof(*pasid_state), GFP_KERNEL); | |
657 | if (pasid_state == NULL) | |
658 | goto out; | |
659 | ||
660 | atomic_set(&pasid_state->count, 1); | |
028eeacc | 661 | init_waitqueue_head(&pasid_state->wq); |
2c13d47a JR |
662 | spin_lock_init(&pasid_state->lock); |
663 | ||
2d5503b6 JR |
664 | pasid_state->task = task; |
665 | pasid_state->mm = get_task_mm(task); | |
666 | pasid_state->device_state = dev_state; | |
667 | pasid_state->pasid = pasid; | |
8736b2c3 | 668 | pasid_state->mn.ops = &iommu_mn; |
2d5503b6 JR |
669 | |
670 | if (pasid_state->mm == NULL) | |
671 | goto out_free; | |
672 | ||
8736b2c3 JR |
673 | mmu_notifier_register(&pasid_state->mn, pasid_state->mm); |
674 | ||
2d5503b6 JR |
675 | ret = set_pasid_state(dev_state, pasid_state, pasid); |
676 | if (ret) | |
8736b2c3 | 677 | goto out_unregister; |
2d5503b6 JR |
678 | |
679 | ret = amd_iommu_domain_set_gcr3(dev_state->domain, pasid, | |
680 | __pa(pasid_state->mm->pgd)); | |
681 | if (ret) | |
682 | goto out_clear_state; | |
683 | ||
2d5503b6 JR |
684 | return 0; |
685 | ||
686 | out_clear_state: | |
687 | clear_pasid_state(dev_state, pasid); | |
688 | ||
8736b2c3 JR |
689 | out_unregister: |
690 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
691 | ||
2d5503b6 | 692 | out_free: |
028eeacc | 693 | free_pasid_state(pasid_state); |
2d5503b6 JR |
694 | |
695 | out: | |
696 | put_device_state(dev_state); | |
697 | ||
698 | return ret; | |
699 | } | |
700 | EXPORT_SYMBOL(amd_iommu_bind_pasid); | |
701 | ||
702 | void amd_iommu_unbind_pasid(struct pci_dev *pdev, int pasid) | |
703 | { | |
a40d4c67 | 704 | struct pasid_state *pasid_state; |
2d5503b6 JR |
705 | struct device_state *dev_state; |
706 | u16 devid; | |
707 | ||
708 | might_sleep(); | |
709 | ||
710 | if (!amd_iommu_v2_supported()) | |
711 | return; | |
712 | ||
713 | devid = device_id(pdev); | |
714 | dev_state = get_device_state(devid); | |
715 | if (dev_state == NULL) | |
716 | return; | |
717 | ||
718 | if (pasid < 0 || pasid >= dev_state->max_pasids) | |
719 | goto out; | |
720 | ||
a40d4c67 JR |
721 | pasid_state = get_pasid_state(dev_state, pasid); |
722 | if (pasid_state == NULL) | |
723 | goto out; | |
724 | /* | |
725 | * Drop reference taken here. We are safe because we still hold | |
726 | * the reference taken in the amd_iommu_bind_pasid function. | |
727 | */ | |
728 | put_pasid_state(pasid_state); | |
729 | ||
730 | /* This will call the mn_release function and unbind the PASID */ | |
731 | mmu_notifier_unregister(&pasid_state->mn, pasid_state->mm); | |
2d5503b6 JR |
732 | |
733 | out: | |
734 | put_device_state(dev_state); | |
735 | } | |
736 | EXPORT_SYMBOL(amd_iommu_unbind_pasid); | |
737 | ||
ed96f228 JR |
738 | int amd_iommu_init_device(struct pci_dev *pdev, int pasids) |
739 | { | |
740 | struct device_state *dev_state; | |
741 | unsigned long flags; | |
742 | int ret, tmp; | |
743 | u16 devid; | |
744 | ||
745 | might_sleep(); | |
746 | ||
747 | if (!amd_iommu_v2_supported()) | |
748 | return -ENODEV; | |
749 | ||
750 | if (pasids <= 0 || pasids > (PASID_MASK + 1)) | |
751 | return -EINVAL; | |
752 | ||
753 | devid = device_id(pdev); | |
754 | ||
755 | dev_state = kzalloc(sizeof(*dev_state), GFP_KERNEL); | |
756 | if (dev_state == NULL) | |
757 | return -ENOMEM; | |
758 | ||
759 | spin_lock_init(&dev_state->lock); | |
028eeacc | 760 | init_waitqueue_head(&dev_state->wq); |
741669c7 JR |
761 | dev_state->pdev = pdev; |
762 | dev_state->devid = devid; | |
ed96f228 JR |
763 | |
764 | tmp = pasids; | |
765 | for (dev_state->pasid_levels = 0; (tmp - 1) & ~0x1ff; tmp >>= 9) | |
766 | dev_state->pasid_levels += 1; | |
767 | ||
768 | atomic_set(&dev_state->count, 1); | |
769 | dev_state->max_pasids = pasids; | |
770 | ||
771 | ret = -ENOMEM; | |
772 | dev_state->states = (void *)get_zeroed_page(GFP_KERNEL); | |
773 | if (dev_state->states == NULL) | |
774 | goto out_free_dev_state; | |
775 | ||
776 | dev_state->domain = iommu_domain_alloc(&pci_bus_type); | |
777 | if (dev_state->domain == NULL) | |
778 | goto out_free_states; | |
779 | ||
780 | amd_iommu_domain_direct_map(dev_state->domain); | |
781 | ||
782 | ret = amd_iommu_domain_enable_v2(dev_state->domain, pasids); | |
783 | if (ret) | |
784 | goto out_free_domain; | |
785 | ||
786 | ret = iommu_attach_device(dev_state->domain, &pdev->dev); | |
787 | if (ret != 0) | |
788 | goto out_free_domain; | |
789 | ||
790 | spin_lock_irqsave(&state_lock, flags); | |
791 | ||
741669c7 | 792 | if (__get_device_state(devid) != NULL) { |
ed96f228 JR |
793 | spin_unlock_irqrestore(&state_lock, flags); |
794 | ret = -EBUSY; | |
795 | goto out_free_domain; | |
796 | } | |
797 | ||
741669c7 | 798 | list_add_tail(&dev_state->list, &state_list); |
ed96f228 JR |
799 | |
800 | spin_unlock_irqrestore(&state_lock, flags); | |
801 | ||
802 | return 0; | |
803 | ||
804 | out_free_domain: | |
805 | iommu_domain_free(dev_state->domain); | |
806 | ||
807 | out_free_states: | |
808 | free_page((unsigned long)dev_state->states); | |
809 | ||
810 | out_free_dev_state: | |
811 | kfree(dev_state); | |
812 | ||
813 | return ret; | |
814 | } | |
815 | EXPORT_SYMBOL(amd_iommu_init_device); | |
816 | ||
817 | void amd_iommu_free_device(struct pci_dev *pdev) | |
818 | { | |
819 | struct device_state *dev_state; | |
820 | unsigned long flags; | |
821 | u16 devid; | |
822 | ||
823 | if (!amd_iommu_v2_supported()) | |
824 | return; | |
825 | ||
826 | devid = device_id(pdev); | |
827 | ||
828 | spin_lock_irqsave(&state_lock, flags); | |
829 | ||
b87d2d7c | 830 | dev_state = __get_device_state(devid); |
ed96f228 JR |
831 | if (dev_state == NULL) { |
832 | spin_unlock_irqrestore(&state_lock, flags); | |
833 | return; | |
834 | } | |
835 | ||
741669c7 | 836 | list_del(&dev_state->list); |
ed96f228 JR |
837 | |
838 | spin_unlock_irqrestore(&state_lock, flags); | |
839 | ||
2d5503b6 JR |
840 | /* Get rid of any remaining pasid states */ |
841 | free_pasid_states(dev_state); | |
842 | ||
028eeacc | 843 | put_device_state_wait(dev_state); |
ed96f228 JR |
844 | } |
845 | EXPORT_SYMBOL(amd_iommu_free_device); | |
846 | ||
175d6146 JR |
847 | int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev, |
848 | amd_iommu_invalid_ppr_cb cb) | |
849 | { | |
850 | struct device_state *dev_state; | |
851 | unsigned long flags; | |
852 | u16 devid; | |
853 | int ret; | |
854 | ||
855 | if (!amd_iommu_v2_supported()) | |
856 | return -ENODEV; | |
857 | ||
858 | devid = device_id(pdev); | |
859 | ||
860 | spin_lock_irqsave(&state_lock, flags); | |
861 | ||
862 | ret = -EINVAL; | |
b87d2d7c | 863 | dev_state = __get_device_state(devid); |
175d6146 JR |
864 | if (dev_state == NULL) |
865 | goto out_unlock; | |
866 | ||
867 | dev_state->inv_ppr_cb = cb; | |
868 | ||
869 | ret = 0; | |
870 | ||
871 | out_unlock: | |
872 | spin_unlock_irqrestore(&state_lock, flags); | |
873 | ||
874 | return ret; | |
875 | } | |
876 | EXPORT_SYMBOL(amd_iommu_set_invalid_ppr_cb); | |
877 | ||
bc21662f JR |
878 | int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev, |
879 | amd_iommu_invalidate_ctx cb) | |
880 | { | |
881 | struct device_state *dev_state; | |
882 | unsigned long flags; | |
883 | u16 devid; | |
884 | int ret; | |
885 | ||
886 | if (!amd_iommu_v2_supported()) | |
887 | return -ENODEV; | |
888 | ||
889 | devid = device_id(pdev); | |
890 | ||
891 | spin_lock_irqsave(&state_lock, flags); | |
892 | ||
893 | ret = -EINVAL; | |
b87d2d7c | 894 | dev_state = __get_device_state(devid); |
bc21662f JR |
895 | if (dev_state == NULL) |
896 | goto out_unlock; | |
897 | ||
898 | dev_state->inv_ctx_cb = cb; | |
899 | ||
900 | ret = 0; | |
901 | ||
902 | out_unlock: | |
903 | spin_unlock_irqrestore(&state_lock, flags); | |
904 | ||
905 | return ret; | |
906 | } | |
907 | EXPORT_SYMBOL(amd_iommu_set_invalidate_ctx_cb); | |
908 | ||
e3c495c7 JR |
909 | static int __init amd_iommu_v2_init(void) |
910 | { | |
028eeacc | 911 | int ret; |
ed96f228 | 912 | |
474d567d JR |
913 | pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n"); |
914 | ||
915 | if (!amd_iommu_v2_supported()) { | |
07db0409 | 916 | pr_info("AMD IOMMUv2 functionality not available on this system\n"); |
474d567d JR |
917 | /* |
918 | * Load anyway to provide the symbols to other modules | |
919 | * which may use AMD IOMMUv2 optionally. | |
920 | */ | |
921 | return 0; | |
922 | } | |
e3c495c7 | 923 | |
ed96f228 JR |
924 | spin_lock_init(&state_lock); |
925 | ||
028eeacc JR |
926 | ret = -ENOMEM; |
927 | iommu_wq = create_workqueue("amd_iommu_v2"); | |
8736b2c3 | 928 | if (iommu_wq == NULL) |
741669c7 | 929 | goto out; |
8736b2c3 JR |
930 | |
931 | ret = -ENOMEM; | |
932 | empty_page_table = (u64 *)get_zeroed_page(GFP_KERNEL); | |
933 | if (empty_page_table == NULL) | |
934 | goto out_destroy_wq; | |
028eeacc JR |
935 | |
936 | amd_iommu_register_ppr_notifier(&ppr_nb); | |
937 | ||
e3c495c7 | 938 | return 0; |
028eeacc | 939 | |
8736b2c3 JR |
940 | out_destroy_wq: |
941 | destroy_workqueue(iommu_wq); | |
942 | ||
741669c7 | 943 | out: |
028eeacc | 944 | return ret; |
e3c495c7 JR |
945 | } |
946 | ||
947 | static void __exit amd_iommu_v2_exit(void) | |
948 | { | |
ed96f228 | 949 | struct device_state *dev_state; |
ed96f228 JR |
950 | int i; |
951 | ||
474d567d JR |
952 | if (!amd_iommu_v2_supported()) |
953 | return; | |
954 | ||
028eeacc JR |
955 | amd_iommu_unregister_ppr_notifier(&ppr_nb); |
956 | ||
957 | flush_workqueue(iommu_wq); | |
958 | ||
959 | /* | |
960 | * The loop below might call flush_workqueue(), so call | |
961 | * destroy_workqueue() after it | |
962 | */ | |
ed96f228 JR |
963 | for (i = 0; i < MAX_DEVICES; ++i) { |
964 | dev_state = get_device_state(i); | |
965 | ||
966 | if (dev_state == NULL) | |
967 | continue; | |
968 | ||
969 | WARN_ON_ONCE(1); | |
970 | ||
ed96f228 | 971 | put_device_state(dev_state); |
028eeacc | 972 | amd_iommu_free_device(dev_state->pdev); |
ed96f228 JR |
973 | } |
974 | ||
028eeacc JR |
975 | destroy_workqueue(iommu_wq); |
976 | ||
8736b2c3 | 977 | free_page((unsigned long)empty_page_table); |
e3c495c7 JR |
978 | } |
979 | ||
980 | module_init(amd_iommu_v2_init); | |
981 | module_exit(amd_iommu_v2_exit); |