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45051539 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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2 | /* |
3 | * IOMMU API for ARM architected SMMU implementations. | |
4 | * | |
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5 | * Copyright (C) 2013 ARM Limited |
6 | * | |
7 | * Author: Will Deacon <will.deacon@arm.com> | |
8 | */ | |
9 | ||
10 | #ifndef _ARM_SMMU_REGS_H | |
11 | #define _ARM_SMMU_REGS_H | |
12 | ||
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13 | #include <linux/bits.h> |
14 | ||
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15 | /* Configuration registers */ |
16 | #define ARM_SMMU_GR0_sCR0 0x0 | |
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17 | #define sCR0_VMID16EN BIT(31) |
18 | #define sCR0_BSU GENMASK(15, 14) | |
19 | #define sCR0_FB BIT(13) | |
20 | #define sCR0_PTM BIT(12) | |
21 | #define sCR0_VMIDPNE BIT(11) | |
22 | #define sCR0_USFCFG BIT(10) | |
23 | #define sCR0_GCFGFIE BIT(5) | |
24 | #define sCR0_GCFGFRE BIT(4) | |
25 | #define sCR0_EXIDENABLE BIT(3) | |
26 | #define sCR0_GFIE BIT(2) | |
27 | #define sCR0_GFRE BIT(1) | |
28 | #define sCR0_CLIENTPD BIT(0) | |
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29 | |
30 | /* Auxiliary Configuration register */ | |
31 | #define ARM_SMMU_GR0_sACR 0x10 | |
32 | ||
33 | /* Identification registers */ | |
34 | #define ARM_SMMU_GR0_ID0 0x20 | |
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35 | #define ID0_S1TS BIT(30) |
36 | #define ID0_S2TS BIT(29) | |
37 | #define ID0_NTS BIT(28) | |
38 | #define ID0_SMS BIT(27) | |
39 | #define ID0_ATOSNS BIT(26) | |
40 | #define ID0_PTFS_NO_AARCH32 BIT(25) | |
41 | #define ID0_PTFS_NO_AARCH32S BIT(24) | |
42 | #define ID0_NUMIRPT GENMASK(23, 16) | |
43 | #define ID0_CTTW BIT(14) | |
44 | #define ID0_NUMSIDB GENMASK(12, 9) | |
45 | #define ID0_EXIDS BIT(8) | |
46 | #define ID0_NUMSMRG GENMASK(7, 0) | |
47 | ||
2b03774b | 48 | #define ARM_SMMU_GR0_ID1 0x24 |
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49 | #define ID1_PAGESIZE BIT(31) |
50 | #define ID1_NUMPAGENDXB GENMASK(30, 28) | |
51 | #define ID1_NUMS2CB GENMASK(23, 16) | |
52 | #define ID1_NUMCB GENMASK(7, 0) | |
53 | ||
2b03774b | 54 | #define ARM_SMMU_GR0_ID2 0x28 |
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55 | #define ID2_VMID16 BIT(15) |
56 | #define ID2_PTFS_64K BIT(14) | |
57 | #define ID2_PTFS_16K BIT(13) | |
58 | #define ID2_PTFS_4K BIT(12) | |
59 | #define ID2_UBS GENMASK(11, 8) | |
60 | #define ID2_OAS GENMASK(7, 4) | |
61 | #define ID2_IAS GENMASK(3, 0) | |
62 | ||
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63 | #define ARM_SMMU_GR0_ID3 0x2c |
64 | #define ARM_SMMU_GR0_ID4 0x30 | |
65 | #define ARM_SMMU_GR0_ID5 0x34 | |
66 | #define ARM_SMMU_GR0_ID6 0x38 | |
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2b03774b | 68 | #define ARM_SMMU_GR0_ID7 0x3c |
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69 | #define ID7_MAJOR GENMASK(7, 4) |
70 | #define ID7_MINOR GENMASK(3, 0) | |
71 | ||
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72 | #define ARM_SMMU_GR0_sGFSR 0x48 |
73 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
74 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
75 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
76 | ||
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77 | /* Global TLB invalidation */ |
78 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
79 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
80 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
81 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
0caf5f4e | 82 | |
2b03774b | 83 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 |
0caf5f4e | 84 | #define sTLBGSTATUS_GSACTIVE BIT(0) |
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85 | |
86 | /* Stream mapping registers */ | |
87 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
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88 | #define SMR_VALID BIT(31) |
89 | #define SMR_MASK GENMASK(31, 16) | |
90 | #define SMR_ID GENMASK(15, 0) | |
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91 | |
92 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
0caf5f4e | 93 | #define S2CR_PRIVCFG GENMASK(25, 24) |
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94 | enum arm_smmu_s2cr_privcfg { |
95 | S2CR_PRIVCFG_DEFAULT, | |
96 | S2CR_PRIVCFG_DIPAN, | |
97 | S2CR_PRIVCFG_UNPRIV, | |
98 | S2CR_PRIVCFG_PRIV, | |
99 | }; | |
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100 | #define S2CR_TYPE GENMASK(17, 16) |
101 | enum arm_smmu_s2cr_type { | |
102 | S2CR_TYPE_TRANS, | |
103 | S2CR_TYPE_BYPASS, | |
104 | S2CR_TYPE_FAULT, | |
105 | }; | |
106 | #define S2CR_EXIDVALID BIT(10) | |
107 | #define S2CR_CBNDX GENMASK(7, 0) | |
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108 | |
109 | /* Context bank attribute registers */ | |
110 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
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111 | #define CBAR_IRPTNDX GENMASK(31, 24) |
112 | #define CBAR_TYPE GENMASK(17, 16) | |
113 | enum arm_smmu_cbar_type { | |
114 | CBAR_TYPE_S2_TRANS, | |
115 | CBAR_TYPE_S1_TRANS_S2_BYPASS, | |
116 | CBAR_TYPE_S1_TRANS_S2_FAULT, | |
117 | CBAR_TYPE_S1_TRANS_S2_TRANS, | |
118 | }; | |
119 | #define CBAR_S1_MEMATTR GENMASK(15, 12) | |
2b03774b | 120 | #define CBAR_S1_MEMATTR_WB 0xf |
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121 | #define CBAR_S1_BPSHCFG GENMASK(9, 8) |
122 | #define CBAR_S1_BPSHCFG_NSH 3 | |
123 | #define CBAR_VMID GENMASK(7, 0) | |
2b03774b | 124 | |
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125 | #define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2)) |
126 | ||
2b03774b | 127 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) |
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128 | #define CBA2R_VMID16 GENMASK(31, 16) |
129 | #define CBA2R_VA64 BIT(0) | |
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130 | |
131 | #define ARM_SMMU_CB_SCTLR 0x0 | |
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132 | #define SCTLR_S1_ASIDPNE BIT(12) |
133 | #define SCTLR_CFCFG BIT(7) | |
134 | #define SCTLR_CFIE BIT(6) | |
135 | #define SCTLR_CFRE BIT(5) | |
136 | #define SCTLR_E BIT(4) | |
137 | #define SCTLR_AFE BIT(2) | |
138 | #define SCTLR_TRE BIT(1) | |
139 | #define SCTLR_M BIT(0) | |
140 | ||
2b03774b | 141 | #define ARM_SMMU_CB_ACTLR 0x4 |
620565a7 | 142 | |
2b03774b | 143 | #define ARM_SMMU_CB_RESUME 0x8 |
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144 | #define RESUME_TERMINATE BIT(0) |
145 | ||
146 | #define ARM_SMMU_CB_TCR2 0x10 | |
147 | #define TCR2_SEP GENMASK(17, 15) | |
148 | #define TCR2_SEP_UPSTREAM 0x7 | |
149 | #define TCR2_AS BIT(4) | |
150 | ||
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151 | #define ARM_SMMU_CB_TTBR0 0x20 |
152 | #define ARM_SMMU_CB_TTBR1 0x28 | |
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153 | #define TTBRn_ASID GENMASK_ULL(63, 48) |
154 | ||
155 | #define ARM_SMMU_CB_TCR 0x30 | |
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156 | #define ARM_SMMU_CB_CONTEXTIDR 0x34 |
157 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
158 | #define ARM_SMMU_CB_S1_MAIR1 0x3c | |
620565a7 | 159 | |
2b03774b | 160 | #define ARM_SMMU_CB_PAR 0x50 |
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161 | #define CB_PAR_F BIT(0) |
162 | ||
2b03774b | 163 | #define ARM_SMMU_CB_FSR 0x58 |
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164 | #define FSR_MULTI BIT(31) |
165 | #define FSR_SS BIT(30) | |
166 | #define FSR_UUT BIT(8) | |
167 | #define FSR_ASF BIT(7) | |
168 | #define FSR_TLBLKF BIT(6) | |
169 | #define FSR_TLBMCF BIT(5) | |
170 | #define FSR_EF BIT(4) | |
171 | #define FSR_PF BIT(3) | |
172 | #define FSR_AFF BIT(2) | |
173 | #define FSR_TF BIT(1) | |
174 | ||
175 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ | |
176 | FSR_TLBMCF | FSR_TLBLKF) | |
177 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
178 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) | |
179 | ||
2b03774b | 180 | #define ARM_SMMU_CB_FAR 0x60 |
620565a7 | 181 | |
2b03774b | 182 | #define ARM_SMMU_CB_FSYNR0 0x68 |
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183 | #define FSYNR0_WNR BIT(4) |
184 | ||
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185 | #define ARM_SMMU_CB_S1_TLBIVA 0x600 |
186 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 | |
187 | #define ARM_SMMU_CB_S1_TLBIVAL 0x620 | |
188 | #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 | |
189 | #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 | |
190 | #define ARM_SMMU_CB_TLBSYNC 0x7f0 | |
191 | #define ARM_SMMU_CB_TLBSTATUS 0x7f4 | |
192 | #define ARM_SMMU_CB_ATS1PR 0x800 | |
2b03774b | 193 | |
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194 | #define ARM_SMMU_CB_ATSR 0x8f0 |
195 | #define ATSR_ACTIVE BIT(0) | |
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196 | |
197 | #endif /* _ARM_SMMU_REGS_H */ |