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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
26 | * - 4k and 64k pages, with contiguous pte hints. | |
06f983dd | 27 | * - Up to 42-bit addressing (dependent on VA_BITS) |
45ae7cff WD |
28 | * - Context fault reporting |
29 | */ | |
30 | ||
31 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
32 | ||
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/iommu.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/of.h> | |
a9a1b0b5 | 42 | #include <linux/pci.h> |
45ae7cff WD |
43 | #include <linux/platform_device.h> |
44 | #include <linux/slab.h> | |
45 | #include <linux/spinlock.h> | |
46 | ||
47 | #include <linux/amba/bus.h> | |
48 | ||
49 | #include <asm/pgalloc.h> | |
50 | ||
51 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 52 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
53 | |
54 | /* Maximum number of context banks per SMMU */ | |
55 | #define ARM_SMMU_MAX_CBS 128 | |
56 | ||
57 | /* Maximum number of mapping groups per SMMU */ | |
58 | #define ARM_SMMU_MAX_SMRS 128 | |
59 | ||
45ae7cff WD |
60 | /* SMMU global address space */ |
61 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
62 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) | |
63 | ||
3a5df8ff AH |
64 | /* |
65 | * SMMU global address space with conditional offset to access secure | |
66 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
67 | * nsGFSYNR0: 0x450) | |
68 | */ | |
69 | #define ARM_SMMU_GR0_NS(smmu) \ | |
70 | ((smmu)->base + \ | |
71 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
72 | ? 0x400 : 0)) | |
73 | ||
45ae7cff | 74 | /* Page table bits */ |
cf2d45b1 | 75 | #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) |
45ae7cff WD |
76 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
77 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) | |
78 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) | |
79 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) | |
80 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) | |
cf2d45b1 | 81 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
45ae7cff WD |
82 | |
83 | #if PAGE_SIZE == SZ_4K | |
84 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 | |
85 | #elif PAGE_SIZE == SZ_64K | |
86 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 | |
87 | #else | |
88 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 | |
89 | #endif | |
90 | ||
91 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) | |
92 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) | |
45ae7cff WD |
93 | |
94 | /* Stage-1 PTE */ | |
95 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) | |
96 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) | |
97 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 | |
1463fe44 | 98 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
45ae7cff WD |
99 | |
100 | /* Stage-2 PTE */ | |
101 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) | |
102 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) | |
103 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) | |
104 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) | |
105 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) | |
106 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) | |
107 | ||
108 | /* Configuration registers */ | |
109 | #define ARM_SMMU_GR0_sCR0 0x0 | |
110 | #define sCR0_CLIENTPD (1 << 0) | |
111 | #define sCR0_GFRE (1 << 1) | |
112 | #define sCR0_GFIE (1 << 2) | |
113 | #define sCR0_GCFGFRE (1 << 4) | |
114 | #define sCR0_GCFGFIE (1 << 5) | |
115 | #define sCR0_USFCFG (1 << 10) | |
116 | #define sCR0_VMIDPNE (1 << 11) | |
117 | #define sCR0_PTM (1 << 12) | |
118 | #define sCR0_FB (1 << 13) | |
119 | #define sCR0_BSU_SHIFT 14 | |
120 | #define sCR0_BSU_MASK 0x3 | |
121 | ||
122 | /* Identification registers */ | |
123 | #define ARM_SMMU_GR0_ID0 0x20 | |
124 | #define ARM_SMMU_GR0_ID1 0x24 | |
125 | #define ARM_SMMU_GR0_ID2 0x28 | |
126 | #define ARM_SMMU_GR0_ID3 0x2c | |
127 | #define ARM_SMMU_GR0_ID4 0x30 | |
128 | #define ARM_SMMU_GR0_ID5 0x34 | |
129 | #define ARM_SMMU_GR0_ID6 0x38 | |
130 | #define ARM_SMMU_GR0_ID7 0x3c | |
131 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
132 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
133 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
134 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
135 | #define ARM_SMMU_GR0_PIDR0 0xfe0 | |
136 | #define ARM_SMMU_GR0_PIDR1 0xfe4 | |
137 | #define ARM_SMMU_GR0_PIDR2 0xfe8 | |
138 | ||
139 | #define ID0_S1TS (1 << 30) | |
140 | #define ID0_S2TS (1 << 29) | |
141 | #define ID0_NTS (1 << 28) | |
142 | #define ID0_SMS (1 << 27) | |
143 | #define ID0_PTFS_SHIFT 24 | |
144 | #define ID0_PTFS_MASK 0x2 | |
145 | #define ID0_PTFS_V8_ONLY 0x2 | |
146 | #define ID0_CTTW (1 << 14) | |
147 | #define ID0_NUMIRPT_SHIFT 16 | |
148 | #define ID0_NUMIRPT_MASK 0xff | |
3c8766d0 OH |
149 | #define ID0_NUMSIDB_SHIFT 9 |
150 | #define ID0_NUMSIDB_MASK 0xf | |
45ae7cff WD |
151 | #define ID0_NUMSMRG_SHIFT 0 |
152 | #define ID0_NUMSMRG_MASK 0xff | |
153 | ||
154 | #define ID1_PAGESIZE (1 << 31) | |
155 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
156 | #define ID1_NUMPAGENDXB_MASK 7 | |
157 | #define ID1_NUMS2CB_SHIFT 16 | |
158 | #define ID1_NUMS2CB_MASK 0xff | |
159 | #define ID1_NUMCB_SHIFT 0 | |
160 | #define ID1_NUMCB_MASK 0xff | |
161 | ||
162 | #define ID2_OAS_SHIFT 4 | |
163 | #define ID2_OAS_MASK 0xf | |
164 | #define ID2_IAS_SHIFT 0 | |
165 | #define ID2_IAS_MASK 0xf | |
166 | #define ID2_UBS_SHIFT 8 | |
167 | #define ID2_UBS_MASK 0xf | |
168 | #define ID2_PTFS_4K (1 << 12) | |
169 | #define ID2_PTFS_16K (1 << 13) | |
170 | #define ID2_PTFS_64K (1 << 14) | |
171 | ||
172 | #define PIDR2_ARCH_SHIFT 4 | |
173 | #define PIDR2_ARCH_MASK 0xf | |
174 | ||
175 | /* Global TLB invalidation */ | |
176 | #define ARM_SMMU_GR0_STLBIALL 0x60 | |
177 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
178 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
179 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
180 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
181 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
182 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
183 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
184 | ||
185 | /* Stream mapping registers */ | |
186 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
187 | #define SMR_VALID (1 << 31) | |
188 | #define SMR_MASK_SHIFT 16 | |
189 | #define SMR_MASK_MASK 0x7fff | |
190 | #define SMR_ID_SHIFT 0 | |
191 | #define SMR_ID_MASK 0x7fff | |
192 | ||
193 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
194 | #define S2CR_CBNDX_SHIFT 0 | |
195 | #define S2CR_CBNDX_MASK 0xff | |
196 | #define S2CR_TYPE_SHIFT 16 | |
197 | #define S2CR_TYPE_MASK 0x3 | |
198 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
199 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
200 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
201 | ||
202 | /* Context bank attribute registers */ | |
203 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
204 | #define CBAR_VMID_SHIFT 0 | |
205 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
206 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
207 | #define CBAR_S1_BPSHCFG_MASK 3 | |
208 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
209 | #define CBAR_S1_MEMATTR_SHIFT 12 |
210 | #define CBAR_S1_MEMATTR_MASK 0xf | |
211 | #define CBAR_S1_MEMATTR_WB 0xf | |
212 | #define CBAR_TYPE_SHIFT 16 | |
213 | #define CBAR_TYPE_MASK 0x3 | |
214 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
215 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
216 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
217 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
218 | #define CBAR_IRPTNDX_SHIFT 24 | |
219 | #define CBAR_IRPTNDX_MASK 0xff | |
220 | ||
221 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
222 | #define CBA2R_RW64_32BIT (0 << 0) | |
223 | #define CBA2R_RW64_64BIT (1 << 0) | |
224 | ||
225 | /* Translation context bank */ | |
226 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
227 | #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) | |
228 | ||
229 | #define ARM_SMMU_CB_SCTLR 0x0 | |
230 | #define ARM_SMMU_CB_RESUME 0x8 | |
231 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
232 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
233 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
234 | #define ARM_SMMU_CB_TTBCR 0x30 | |
235 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
236 | #define ARM_SMMU_CB_FSR 0x58 | |
237 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
238 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
239 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
1463fe44 | 240 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
45ae7cff WD |
241 | |
242 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
243 | #define SCTLR_CFCFG (1 << 7) | |
244 | #define SCTLR_CFIE (1 << 6) | |
245 | #define SCTLR_CFRE (1 << 5) | |
246 | #define SCTLR_E (1 << 4) | |
247 | #define SCTLR_AFE (1 << 2) | |
248 | #define SCTLR_TRE (1 << 1) | |
249 | #define SCTLR_M (1 << 0) | |
250 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
251 | ||
252 | #define RESUME_RETRY (0 << 0) | |
253 | #define RESUME_TERMINATE (1 << 0) | |
254 | ||
255 | #define TTBCR_EAE (1 << 31) | |
256 | ||
257 | #define TTBCR_PASIZE_SHIFT 16 | |
258 | #define TTBCR_PASIZE_MASK 0x7 | |
259 | ||
260 | #define TTBCR_TG0_4K (0 << 14) | |
261 | #define TTBCR_TG0_64K (1 << 14) | |
262 | ||
263 | #define TTBCR_SH0_SHIFT 12 | |
264 | #define TTBCR_SH0_MASK 0x3 | |
265 | #define TTBCR_SH_NS 0 | |
266 | #define TTBCR_SH_OS 2 | |
267 | #define TTBCR_SH_IS 3 | |
268 | ||
269 | #define TTBCR_ORGN0_SHIFT 10 | |
270 | #define TTBCR_IRGN0_SHIFT 8 | |
271 | #define TTBCR_RGN_MASK 0x3 | |
272 | #define TTBCR_RGN_NC 0 | |
273 | #define TTBCR_RGN_WBWA 1 | |
274 | #define TTBCR_RGN_WT 2 | |
275 | #define TTBCR_RGN_WB 3 | |
276 | ||
277 | #define TTBCR_SL0_SHIFT 6 | |
278 | #define TTBCR_SL0_MASK 0x3 | |
279 | #define TTBCR_SL0_LVL_2 0 | |
280 | #define TTBCR_SL0_LVL_1 1 | |
281 | ||
282 | #define TTBCR_T1SZ_SHIFT 16 | |
283 | #define TTBCR_T0SZ_SHIFT 0 | |
284 | #define TTBCR_SZ_MASK 0xf | |
285 | ||
286 | #define TTBCR2_SEP_SHIFT 15 | |
287 | #define TTBCR2_SEP_MASK 0x7 | |
288 | ||
289 | #define TTBCR2_PASIZE_SHIFT 0 | |
290 | #define TTBCR2_PASIZE_MASK 0x7 | |
291 | ||
292 | /* Common definitions for PASize and SEP fields */ | |
293 | #define TTBCR2_ADDR_32 0 | |
294 | #define TTBCR2_ADDR_36 1 | |
295 | #define TTBCR2_ADDR_40 2 | |
296 | #define TTBCR2_ADDR_42 3 | |
297 | #define TTBCR2_ADDR_44 4 | |
298 | #define TTBCR2_ADDR_48 5 | |
299 | ||
1463fe44 WD |
300 | #define TTBRn_HI_ASID_SHIFT 16 |
301 | ||
45ae7cff WD |
302 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
303 | #define MAIR_ATTR_MASK 0xff | |
304 | #define MAIR_ATTR_DEVICE 0x04 | |
305 | #define MAIR_ATTR_NC 0x44 | |
306 | #define MAIR_ATTR_WBRWA 0xff | |
307 | #define MAIR_ATTR_IDX_NC 0 | |
308 | #define MAIR_ATTR_IDX_CACHE 1 | |
309 | #define MAIR_ATTR_IDX_DEV 2 | |
310 | ||
311 | #define FSR_MULTI (1 << 31) | |
312 | #define FSR_SS (1 << 30) | |
313 | #define FSR_UUT (1 << 8) | |
314 | #define FSR_ASF (1 << 7) | |
315 | #define FSR_TLBLKF (1 << 6) | |
316 | #define FSR_TLBMCF (1 << 5) | |
317 | #define FSR_EF (1 << 4) | |
318 | #define FSR_PF (1 << 3) | |
319 | #define FSR_AFF (1 << 2) | |
320 | #define FSR_TF (1 << 1) | |
321 | ||
2907320d MH |
322 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
323 | FSR_TLBMCF | FSR_TLBLKF) | |
324 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 325 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
326 | |
327 | #define FSYNR0_WNR (1 << 4) | |
328 | ||
329 | struct arm_smmu_smr { | |
330 | u8 idx; | |
331 | u16 mask; | |
332 | u16 id; | |
333 | }; | |
334 | ||
a9a1b0b5 | 335 | struct arm_smmu_master_cfg { |
45ae7cff WD |
336 | int num_streamids; |
337 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
338 | struct arm_smmu_smr *smrs; |
339 | }; | |
340 | ||
a9a1b0b5 WD |
341 | struct arm_smmu_master { |
342 | struct device_node *of_node; | |
a9a1b0b5 WD |
343 | struct rb_node node; |
344 | struct arm_smmu_master_cfg cfg; | |
345 | }; | |
346 | ||
45ae7cff WD |
347 | struct arm_smmu_device { |
348 | struct device *dev; | |
45ae7cff WD |
349 | |
350 | void __iomem *base; | |
351 | unsigned long size; | |
352 | unsigned long pagesize; | |
353 | ||
354 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
355 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
356 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
357 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
358 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
359 | u32 features; | |
3a5df8ff AH |
360 | |
361 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
362 | u32 options; | |
45ae7cff WD |
363 | int version; |
364 | ||
365 | u32 num_context_banks; | |
366 | u32 num_s2_context_banks; | |
367 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
368 | atomic_t irptndx; | |
369 | ||
370 | u32 num_mapping_groups; | |
371 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
372 | ||
373 | unsigned long input_size; | |
374 | unsigned long s1_output_size; | |
375 | unsigned long s2_output_size; | |
376 | ||
377 | u32 num_global_irqs; | |
378 | u32 num_context_irqs; | |
379 | unsigned int *irqs; | |
380 | ||
45ae7cff WD |
381 | struct list_head list; |
382 | struct rb_root masters; | |
383 | }; | |
384 | ||
385 | struct arm_smmu_cfg { | |
45ae7cff WD |
386 | u8 cbndx; |
387 | u8 irptndx; | |
388 | u32 cbar; | |
389 | pgd_t *pgd; | |
390 | }; | |
faea13b7 | 391 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 392 | |
ecfadb6e WD |
393 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
394 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
395 | ||
45ae7cff | 396 | struct arm_smmu_domain { |
44680eed WD |
397 | struct arm_smmu_device *smmu; |
398 | struct arm_smmu_cfg cfg; | |
c9d09e27 | 399 | spinlock_t lock; |
45ae7cff WD |
400 | }; |
401 | ||
402 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); | |
403 | static LIST_HEAD(arm_smmu_devices); | |
404 | ||
3a5df8ff AH |
405 | struct arm_smmu_option_prop { |
406 | u32 opt; | |
407 | const char *prop; | |
408 | }; | |
409 | ||
2907320d | 410 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
411 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
412 | { 0, NULL}, | |
413 | }; | |
414 | ||
415 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
416 | { | |
417 | int i = 0; | |
2907320d | 418 | |
3a5df8ff AH |
419 | do { |
420 | if (of_property_read_bool(smmu->dev->of_node, | |
421 | arm_smmu_options[i].prop)) { | |
422 | smmu->options |= arm_smmu_options[i].opt; | |
423 | dev_notice(smmu->dev, "option %s\n", | |
424 | arm_smmu_options[i].prop); | |
425 | } | |
426 | } while (arm_smmu_options[++i].opt); | |
427 | } | |
428 | ||
a9a1b0b5 WD |
429 | static struct device *dev_get_master_dev(struct device *dev) |
430 | { | |
431 | if (dev_is_pci(dev)) { | |
432 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 433 | |
a9a1b0b5 WD |
434 | while (!pci_is_root_bus(bus)) |
435 | bus = bus->parent; | |
436 | return bus->bridge->parent; | |
437 | } | |
438 | ||
439 | return dev; | |
440 | } | |
441 | ||
45ae7cff WD |
442 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
443 | struct device_node *dev_node) | |
444 | { | |
445 | struct rb_node *node = smmu->masters.rb_node; | |
446 | ||
447 | while (node) { | |
448 | struct arm_smmu_master *master; | |
2907320d | 449 | |
45ae7cff WD |
450 | master = container_of(node, struct arm_smmu_master, node); |
451 | ||
452 | if (dev_node < master->of_node) | |
453 | node = node->rb_left; | |
454 | else if (dev_node > master->of_node) | |
455 | node = node->rb_right; | |
456 | else | |
457 | return master; | |
458 | } | |
459 | ||
460 | return NULL; | |
461 | } | |
462 | ||
a9a1b0b5 WD |
463 | static struct arm_smmu_master_cfg * |
464 | find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev) | |
465 | { | |
466 | struct arm_smmu_master *master; | |
467 | ||
468 | if (dev_is_pci(dev)) | |
469 | return dev->archdata.iommu; | |
470 | ||
471 | master = find_smmu_master(smmu, dev->of_node); | |
472 | return master ? &master->cfg : NULL; | |
473 | } | |
474 | ||
45ae7cff WD |
475 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
476 | struct arm_smmu_master *master) | |
477 | { | |
478 | struct rb_node **new, *parent; | |
479 | ||
480 | new = &smmu->masters.rb_node; | |
481 | parent = NULL; | |
482 | while (*new) { | |
2907320d MH |
483 | struct arm_smmu_master *this |
484 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
485 | |
486 | parent = *new; | |
487 | if (master->of_node < this->of_node) | |
488 | new = &((*new)->rb_left); | |
489 | else if (master->of_node > this->of_node) | |
490 | new = &((*new)->rb_right); | |
491 | else | |
492 | return -EEXIST; | |
493 | } | |
494 | ||
495 | rb_link_node(&master->node, parent, new); | |
496 | rb_insert_color(&master->node, &smmu->masters); | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
501 | struct device *dev, | |
502 | struct of_phandle_args *masterspec) | |
503 | { | |
504 | int i; | |
505 | struct arm_smmu_master *master; | |
506 | ||
507 | master = find_smmu_master(smmu, masterspec->np); | |
508 | if (master) { | |
509 | dev_err(dev, | |
510 | "rejecting multiple registrations for master device %s\n", | |
511 | masterspec->np->name); | |
512 | return -EBUSY; | |
513 | } | |
514 | ||
515 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
516 | dev_err(dev, | |
517 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
518 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
519 | return -ENOSPC; | |
520 | } | |
521 | ||
522 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
523 | if (!master) | |
524 | return -ENOMEM; | |
525 | ||
a9a1b0b5 WD |
526 | master->of_node = masterspec->np; |
527 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 528 | |
3c8766d0 OH |
529 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
530 | u16 streamid = masterspec->args[i]; | |
45ae7cff | 531 | |
3c8766d0 OH |
532 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
533 | (streamid >= smmu->num_mapping_groups)) { | |
534 | dev_err(dev, | |
535 | "stream ID for master device %s greater than maximum allowed (%d)\n", | |
536 | masterspec->np->name, smmu->num_mapping_groups); | |
537 | return -ERANGE; | |
538 | } | |
539 | master->cfg.streamids[i] = streamid; | |
540 | } | |
45ae7cff WD |
541 | return insert_smmu_master(smmu, master); |
542 | } | |
543 | ||
44680eed | 544 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 545 | { |
44680eed | 546 | struct arm_smmu_device *smmu; |
a9a1b0b5 WD |
547 | struct arm_smmu_master *master = NULL; |
548 | struct device_node *dev_node = dev_get_master_dev(dev)->of_node; | |
45ae7cff WD |
549 | |
550 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 551 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
552 | master = find_smmu_master(smmu, dev_node); |
553 | if (master) | |
554 | break; | |
555 | } | |
45ae7cff | 556 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 557 | |
a9a1b0b5 | 558 | return master ? smmu : NULL; |
45ae7cff WD |
559 | } |
560 | ||
561 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
562 | { | |
563 | int idx; | |
564 | ||
565 | do { | |
566 | idx = find_next_zero_bit(map, end, start); | |
567 | if (idx == end) | |
568 | return -ENOSPC; | |
569 | } while (test_and_set_bit(idx, map)); | |
570 | ||
571 | return idx; | |
572 | } | |
573 | ||
574 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
575 | { | |
576 | clear_bit(idx, map); | |
577 | } | |
578 | ||
579 | /* Wait for any pending TLB invalidations to complete */ | |
580 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) | |
581 | { | |
582 | int count = 0; | |
583 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
584 | ||
585 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
586 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
587 | & sTLBGSTATUS_GSACTIVE) { | |
588 | cpu_relax(); | |
589 | if (++count == TLB_LOOP_TIMEOUT) { | |
590 | dev_err_ratelimited(smmu->dev, | |
591 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
592 | return; | |
593 | } | |
594 | udelay(1); | |
595 | } | |
596 | } | |
597 | ||
44680eed | 598 | static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain) |
1463fe44 | 599 | { |
44680eed WD |
600 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
601 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 WD |
602 | void __iomem *base = ARM_SMMU_GR0(smmu); |
603 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
604 | ||
605 | if (stage1) { | |
606 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
607 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
608 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
609 | } else { |
610 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
611 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
612 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
613 | } |
614 | ||
615 | arm_smmu_tlb_sync(smmu); | |
616 | } | |
617 | ||
45ae7cff WD |
618 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
619 | { | |
620 | int flags, ret; | |
621 | u32 fsr, far, fsynr, resume; | |
622 | unsigned long iova; | |
623 | struct iommu_domain *domain = dev; | |
624 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
625 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
626 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
627 | void __iomem *cb_base; |
628 | ||
44680eed | 629 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
630 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
631 | ||
632 | if (!(fsr & FSR_FAULT)) | |
633 | return IRQ_NONE; | |
634 | ||
635 | if (fsr & FSR_IGN) | |
636 | dev_err_ratelimited(smmu->dev, | |
70c9a7db | 637 | "Unexpected context fault (fsr 0x%x)\n", |
45ae7cff WD |
638 | fsr); |
639 | ||
640 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
641 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
642 | ||
643 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
644 | iova = far; | |
645 | #ifdef CONFIG_64BIT | |
646 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
647 | iova |= ((unsigned long)far << 32); | |
648 | #endif | |
649 | ||
650 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
651 | ret = IRQ_HANDLED; | |
652 | resume = RESUME_RETRY; | |
653 | } else { | |
2ef0f031 AH |
654 | dev_err_ratelimited(smmu->dev, |
655 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 656 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
657 | ret = IRQ_NONE; |
658 | resume = RESUME_TERMINATE; | |
659 | } | |
660 | ||
661 | /* Clear the faulting FSR */ | |
662 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
663 | ||
664 | /* Retry or terminate any stalled transactions */ | |
665 | if (fsr & FSR_SS) | |
666 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
667 | ||
668 | return ret; | |
669 | } | |
670 | ||
671 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
672 | { | |
673 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
674 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 675 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
676 | |
677 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
678 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
679 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
680 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
681 | ||
3a5df8ff AH |
682 | if (!gfsr) |
683 | return IRQ_NONE; | |
684 | ||
45ae7cff WD |
685 | dev_err_ratelimited(smmu->dev, |
686 | "Unexpected global fault, this could be serious\n"); | |
687 | dev_err_ratelimited(smmu->dev, | |
688 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
689 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
690 | ||
691 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 692 | return IRQ_HANDLED; |
45ae7cff WD |
693 | } |
694 | ||
6dd35f45 WD |
695 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
696 | size_t size) | |
697 | { | |
698 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
699 | ||
700 | ||
701 | /* Ensure new page tables are visible to the hardware walker */ | |
702 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
3aa80ea4 | 703 | dsb(ishst); |
6dd35f45 WD |
704 | } else { |
705 | /* | |
706 | * If the SMMU can't walk tables in the CPU caches, treat them | |
707 | * like non-coherent DMA since we need to flush the new entries | |
708 | * all the way out to memory. There's no possibility of | |
709 | * recursion here as the SMMU table walker will not be wired | |
710 | * through another SMMU. | |
711 | */ | |
712 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
713 | DMA_TO_DEVICE); | |
714 | } | |
715 | } | |
716 | ||
45ae7cff WD |
717 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
718 | { | |
719 | u32 reg; | |
720 | bool stage1; | |
44680eed WD |
721 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
722 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
723 | void __iomem *cb_base, *gr0_base, *gr1_base; |
724 | ||
725 | gr0_base = ARM_SMMU_GR0(smmu); | |
726 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
727 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
728 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
729 | |
730 | /* CBAR */ | |
44680eed | 731 | reg = cfg->cbar; |
45ae7cff | 732 | if (smmu->version == 1) |
2907320d | 733 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 734 | |
57ca90f6 WD |
735 | /* |
736 | * Use the weakest shareability/memory types, so they are | |
737 | * overridden by the ttbcr/pte. | |
738 | */ | |
739 | if (stage1) { | |
740 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
741 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
742 | } else { | |
44680eed | 743 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 744 | } |
44680eed | 745 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff WD |
746 | |
747 | if (smmu->version > 1) { | |
748 | /* CBA2R */ | |
749 | #ifdef CONFIG_64BIT | |
750 | reg = CBA2R_RW64_64BIT; | |
751 | #else | |
752 | reg = CBA2R_RW64_32BIT; | |
753 | #endif | |
754 | writel_relaxed(reg, | |
44680eed | 755 | gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
756 | |
757 | /* TTBCR2 */ | |
758 | switch (smmu->input_size) { | |
759 | case 32: | |
760 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); | |
761 | break; | |
762 | case 36: | |
763 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); | |
764 | break; | |
765 | case 39: | |
4d09d99d | 766 | case 40: |
45ae7cff WD |
767 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
768 | break; | |
769 | case 42: | |
770 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); | |
771 | break; | |
772 | case 44: | |
773 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); | |
774 | break; | |
775 | case 48: | |
776 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); | |
777 | break; | |
778 | } | |
779 | ||
780 | switch (smmu->s1_output_size) { | |
781 | case 32: | |
782 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); | |
783 | break; | |
784 | case 36: | |
785 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); | |
786 | break; | |
787 | case 39: | |
4d09d99d | 788 | case 40: |
45ae7cff WD |
789 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); |
790 | break; | |
791 | case 42: | |
792 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); | |
793 | break; | |
794 | case 44: | |
795 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); | |
796 | break; | |
797 | case 48: | |
798 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); | |
799 | break; | |
800 | } | |
801 | ||
802 | if (stage1) | |
803 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); | |
804 | } | |
805 | ||
806 | /* TTBR0 */ | |
44680eed | 807 | arm_smmu_flush_pgtable(smmu, cfg->pgd, |
6dd35f45 | 808 | PTRS_PER_PGD * sizeof(pgd_t)); |
44680eed | 809 | reg = __pa(cfg->pgd); |
45ae7cff | 810 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
44680eed | 811 | reg = (phys_addr_t)__pa(cfg->pgd) >> 32; |
1463fe44 | 812 | if (stage1) |
44680eed | 813 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
45ae7cff | 814 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff WD |
815 | |
816 | /* | |
817 | * TTBCR | |
818 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. | |
819 | */ | |
820 | if (smmu->version > 1) { | |
821 | if (PAGE_SIZE == SZ_4K) | |
822 | reg = TTBCR_TG0_4K; | |
823 | else | |
824 | reg = TTBCR_TG0_64K; | |
825 | ||
826 | if (!stage1) { | |
a65217a4 WD |
827 | reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; |
828 | ||
45ae7cff WD |
829 | switch (smmu->s2_output_size) { |
830 | case 32: | |
831 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); | |
832 | break; | |
833 | case 36: | |
834 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); | |
835 | break; | |
836 | case 40: | |
837 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); | |
838 | break; | |
839 | case 42: | |
840 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); | |
841 | break; | |
842 | case 44: | |
843 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); | |
844 | break; | |
845 | case 48: | |
846 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); | |
847 | break; | |
848 | } | |
849 | } else { | |
a65217a4 | 850 | reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; |
45ae7cff WD |
851 | } |
852 | } else { | |
853 | reg = 0; | |
854 | } | |
855 | ||
856 | reg |= TTBCR_EAE | | |
857 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | | |
858 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | | |
1fc870c7 OH |
859 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); |
860 | ||
861 | if (!stage1) | |
862 | reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); | |
863 | ||
45ae7cff WD |
864 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
865 | ||
866 | /* MAIR0 (stage-1 only) */ | |
867 | if (stage1) { | |
868 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | | |
869 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | | |
870 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); | |
871 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); | |
872 | } | |
873 | ||
45ae7cff WD |
874 | /* SCTLR */ |
875 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
876 | if (stage1) | |
877 | reg |= SCTLR_S1_ASIDPNE; | |
878 | #ifdef __BIG_ENDIAN | |
879 | reg |= SCTLR_E; | |
880 | #endif | |
25724841 | 881 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
882 | } |
883 | ||
884 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 885 | struct arm_smmu_device *smmu) |
45ae7cff | 886 | { |
a18037b2 MH |
887 | int irq, start, ret = 0; |
888 | unsigned long flags; | |
45ae7cff | 889 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 890 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 891 | |
a18037b2 MH |
892 | spin_lock_irqsave(&smmu_domain->lock, flags); |
893 | if (smmu_domain->smmu) | |
894 | goto out_unlock; | |
895 | ||
45ae7cff WD |
896 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
897 | /* | |
898 | * We will likely want to change this if/when KVM gets | |
899 | * involved. | |
900 | */ | |
44680eed | 901 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 902 | start = smmu->num_s2_context_banks; |
9c5c92e3 | 903 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { |
44680eed | 904 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 905 | start = smmu->num_s2_context_banks; |
9c5c92e3 WD |
906 | } else { |
907 | cfg->cbar = CBAR_TYPE_S2_TRANS; | |
908 | start = 0; | |
45ae7cff WD |
909 | } |
910 | ||
911 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
912 | smmu->num_context_banks); | |
913 | if (IS_ERR_VALUE(ret)) | |
a18037b2 | 914 | goto out_unlock; |
45ae7cff | 915 | |
44680eed | 916 | cfg->cbndx = ret; |
45ae7cff | 917 | if (smmu->version == 1) { |
44680eed WD |
918 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
919 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 920 | } else { |
44680eed | 921 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
922 | } |
923 | ||
a18037b2 MH |
924 | ACCESS_ONCE(smmu_domain->smmu) = smmu; |
925 | arm_smmu_init_context_bank(smmu_domain); | |
926 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
927 | ||
44680eed | 928 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
929 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
930 | "arm-smmu-context-fault", domain); | |
931 | if (IS_ERR_VALUE(ret)) { | |
932 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
933 | cfg->irptndx, irq); |
934 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
935 | } |
936 | ||
a9a1b0b5 | 937 | return 0; |
45ae7cff | 938 | |
a18037b2 MH |
939 | out_unlock: |
940 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
45ae7cff WD |
941 | return ret; |
942 | } | |
943 | ||
944 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
945 | { | |
946 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
947 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
948 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 949 | void __iomem *cb_base; |
45ae7cff WD |
950 | int irq; |
951 | ||
952 | if (!smmu) | |
953 | return; | |
954 | ||
1463fe44 | 955 | /* Disable the context bank and nuke the TLB before freeing it. */ |
44680eed | 956 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 957 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
44680eed | 958 | arm_smmu_tlb_inv_context(smmu_domain); |
1463fe44 | 959 | |
44680eed WD |
960 | if (cfg->irptndx != INVALID_IRPTNDX) { |
961 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
962 | free_irq(irq, domain); |
963 | } | |
964 | ||
44680eed | 965 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
966 | } |
967 | ||
968 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
969 | { | |
970 | struct arm_smmu_domain *smmu_domain; | |
971 | pgd_t *pgd; | |
972 | ||
973 | /* | |
974 | * Allocate the domain and initialise some of its data structures. | |
975 | * We can't really do anything meaningful until we've added a | |
976 | * master. | |
977 | */ | |
978 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
979 | if (!smmu_domain) | |
980 | return -ENOMEM; | |
981 | ||
2907320d | 982 | pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); |
45ae7cff WD |
983 | if (!pgd) |
984 | goto out_free_domain; | |
44680eed | 985 | smmu_domain->cfg.pgd = pgd; |
45ae7cff | 986 | |
c9d09e27 | 987 | spin_lock_init(&smmu_domain->lock); |
45ae7cff WD |
988 | domain->priv = smmu_domain; |
989 | return 0; | |
990 | ||
991 | out_free_domain: | |
992 | kfree(smmu_domain); | |
993 | return -ENOMEM; | |
994 | } | |
995 | ||
996 | static void arm_smmu_free_ptes(pmd_t *pmd) | |
997 | { | |
998 | pgtable_t table = pmd_pgtable(*pmd); | |
2907320d | 999 | |
45ae7cff WD |
1000 | __free_page(table); |
1001 | } | |
1002 | ||
1003 | static void arm_smmu_free_pmds(pud_t *pud) | |
1004 | { | |
1005 | int i; | |
1006 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); | |
1007 | ||
1008 | pmd = pmd_base; | |
1009 | for (i = 0; i < PTRS_PER_PMD; ++i) { | |
1010 | if (pmd_none(*pmd)) | |
1011 | continue; | |
1012 | ||
1013 | arm_smmu_free_ptes(pmd); | |
1014 | pmd++; | |
1015 | } | |
1016 | ||
1017 | pmd_free(NULL, pmd_base); | |
1018 | } | |
1019 | ||
1020 | static void arm_smmu_free_puds(pgd_t *pgd) | |
1021 | { | |
1022 | int i; | |
1023 | pud_t *pud, *pud_base = pud_offset(pgd, 0); | |
1024 | ||
1025 | pud = pud_base; | |
1026 | for (i = 0; i < PTRS_PER_PUD; ++i) { | |
1027 | if (pud_none(*pud)) | |
1028 | continue; | |
1029 | ||
1030 | arm_smmu_free_pmds(pud); | |
1031 | pud++; | |
1032 | } | |
1033 | ||
1034 | pud_free(NULL, pud_base); | |
1035 | } | |
1036 | ||
1037 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) | |
1038 | { | |
1039 | int i; | |
44680eed WD |
1040 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
1041 | pgd_t *pgd, *pgd_base = cfg->pgd; | |
45ae7cff WD |
1042 | |
1043 | /* | |
1044 | * Recursively free the page tables for this domain. We don't | |
34fb4b37 WD |
1045 | * care about speculative TLB filling because the tables should |
1046 | * not be active in any context bank at this point (SCTLR.M is 0). | |
45ae7cff WD |
1047 | */ |
1048 | pgd = pgd_base; | |
1049 | for (i = 0; i < PTRS_PER_PGD; ++i) { | |
1050 | if (pgd_none(*pgd)) | |
1051 | continue; | |
1052 | arm_smmu_free_puds(pgd); | |
1053 | pgd++; | |
1054 | } | |
1055 | ||
1056 | kfree(pgd_base); | |
1057 | } | |
1058 | ||
1059 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
1060 | { | |
1061 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
1062 | |
1063 | /* | |
1064 | * Free the domain resources. We assume that all devices have | |
1065 | * already been detached. | |
1066 | */ | |
45ae7cff WD |
1067 | arm_smmu_destroy_domain_context(domain); |
1068 | arm_smmu_free_pgtables(smmu_domain); | |
1069 | kfree(smmu_domain); | |
1070 | } | |
1071 | ||
1072 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1073 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1074 | { |
1075 | int i; | |
1076 | struct arm_smmu_smr *smrs; | |
1077 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1078 | ||
1079 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1080 | return 0; | |
1081 | ||
a9a1b0b5 | 1082 | if (cfg->smrs) |
45ae7cff WD |
1083 | return -EEXIST; |
1084 | ||
2907320d | 1085 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 1086 | if (!smrs) { |
a9a1b0b5 WD |
1087 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1088 | cfg->num_streamids); | |
45ae7cff WD |
1089 | return -ENOMEM; |
1090 | } | |
1091 | ||
44680eed | 1092 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1093 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1094 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1095 | smmu->num_mapping_groups); | |
1096 | if (IS_ERR_VALUE(idx)) { | |
1097 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1098 | goto err_free_smrs; | |
1099 | } | |
1100 | ||
1101 | smrs[i] = (struct arm_smmu_smr) { | |
1102 | .idx = idx, | |
1103 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1104 | .id = cfg->streamids[i], |
45ae7cff WD |
1105 | }; |
1106 | } | |
1107 | ||
1108 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1109 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1110 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1111 | smrs[i].mask << SMR_MASK_SHIFT; | |
1112 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1113 | } | |
1114 | ||
a9a1b0b5 | 1115 | cfg->smrs = smrs; |
45ae7cff WD |
1116 | return 0; |
1117 | ||
1118 | err_free_smrs: | |
1119 | while (--i >= 0) | |
1120 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1121 | kfree(smrs); | |
1122 | return -ENOSPC; | |
1123 | } | |
1124 | ||
1125 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1126 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1127 | { |
1128 | int i; | |
1129 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1130 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff | 1131 | |
43b412be WD |
1132 | if (!smrs) |
1133 | return; | |
1134 | ||
45ae7cff | 1135 | /* Invalidate the SMRs before freeing back to the allocator */ |
a9a1b0b5 | 1136 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1137 | u8 idx = smrs[i].idx; |
2907320d | 1138 | |
45ae7cff WD |
1139 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1140 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1141 | } | |
1142 | ||
a9a1b0b5 | 1143 | cfg->smrs = NULL; |
45ae7cff WD |
1144 | kfree(smrs); |
1145 | } | |
1146 | ||
45ae7cff | 1147 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
a9a1b0b5 | 1148 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1149 | { |
1150 | int i, ret; | |
44680eed | 1151 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1152 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1153 | ||
a9a1b0b5 | 1154 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff WD |
1155 | if (ret) |
1156 | return ret; | |
1157 | ||
a9a1b0b5 | 1158 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1159 | u32 idx, s2cr; |
2907320d | 1160 | |
a9a1b0b5 | 1161 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1162 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1163 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1164 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1165 | } | |
1166 | ||
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1171 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1172 | { |
43b412be | 1173 | int i; |
44680eed | 1174 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
43b412be | 1175 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
45ae7cff WD |
1176 | |
1177 | /* | |
1178 | * We *must* clear the S2CR first, because freeing the SMR means | |
1179 | * that it can be re-allocated immediately. | |
1180 | */ | |
43b412be WD |
1181 | for (i = 0; i < cfg->num_streamids; ++i) { |
1182 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; | |
1183 | ||
1184 | writel_relaxed(S2CR_TYPE_BYPASS, | |
1185 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); | |
1186 | } | |
1187 | ||
a9a1b0b5 | 1188 | arm_smmu_master_free_smrs(smmu, cfg); |
45ae7cff WD |
1189 | } |
1190 | ||
1191 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1192 | { | |
a18037b2 | 1193 | int ret; |
45ae7cff | 1194 | struct arm_smmu_domain *smmu_domain = domain->priv; |
a18037b2 | 1195 | struct arm_smmu_device *smmu, *dom_smmu; |
a9a1b0b5 | 1196 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1197 | |
44680eed WD |
1198 | smmu = dev_get_master_dev(dev)->archdata.iommu; |
1199 | if (!smmu) { | |
45ae7cff WD |
1200 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1201 | return -ENXIO; | |
1202 | } | |
1203 | ||
1204 | /* | |
44680eed WD |
1205 | * Sanity check the domain. We don't support domains across |
1206 | * different SMMUs. | |
45ae7cff | 1207 | */ |
a18037b2 MH |
1208 | dom_smmu = ACCESS_ONCE(smmu_domain->smmu); |
1209 | if (!dom_smmu) { | |
45ae7cff | 1210 | /* Now that we have a master, we can finalise the domain */ |
44680eed | 1211 | ret = arm_smmu_init_domain_context(domain, smmu); |
45ae7cff | 1212 | if (IS_ERR_VALUE(ret)) |
a18037b2 MH |
1213 | return ret; |
1214 | ||
1215 | dom_smmu = smmu_domain->smmu; | |
1216 | } | |
1217 | ||
1218 | if (dom_smmu != smmu) { | |
45ae7cff WD |
1219 | dev_err(dev, |
1220 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
a18037b2 MH |
1221 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
1222 | return -EINVAL; | |
45ae7cff | 1223 | } |
45ae7cff WD |
1224 | |
1225 | /* Looks ok, so add the device to the domain */ | |
44680eed | 1226 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 | 1227 | if (!cfg) |
45ae7cff WD |
1228 | return -ENODEV; |
1229 | ||
a9a1b0b5 | 1230 | return arm_smmu_domain_add_master(smmu_domain, cfg); |
45ae7cff WD |
1231 | } |
1232 | ||
1233 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1234 | { | |
1235 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1236 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1237 | |
44680eed | 1238 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 WD |
1239 | if (cfg) |
1240 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1241 | } |
1242 | ||
45ae7cff WD |
1243 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
1244 | unsigned long end) | |
1245 | { | |
1246 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && | |
1247 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); | |
1248 | } | |
1249 | ||
1250 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, | |
1251 | unsigned long addr, unsigned long end, | |
b410aed9 | 1252 | unsigned long pfn, int prot, int stage) |
45ae7cff WD |
1253 | { |
1254 | pte_t *pte, *start; | |
cf2d45b1 | 1255 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; |
45ae7cff WD |
1256 | |
1257 | if (pmd_none(*pmd)) { | |
1258 | /* Allocate a new set of tables */ | |
c9d09e27 | 1259 | pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO); |
2907320d | 1260 | |
45ae7cff WD |
1261 | if (!table) |
1262 | return -ENOMEM; | |
1263 | ||
6dd35f45 | 1264 | arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE); |
45ae7cff WD |
1265 | pmd_populate(NULL, pmd, table); |
1266 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); | |
1267 | } | |
1268 | ||
1269 | if (stage == 1) { | |
1463fe44 | 1270 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
b410aed9 | 1271 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
45ae7cff WD |
1272 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
1273 | ||
b410aed9 | 1274 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1275 | pteval |= (MAIR_ATTR_IDX_CACHE << |
1276 | ARM_SMMU_PTE_ATTRINDX_SHIFT); | |
1277 | } else { | |
1278 | pteval |= ARM_SMMU_PTE_HAP_FAULT; | |
b410aed9 | 1279 | if (prot & IOMMU_READ) |
45ae7cff | 1280 | pteval |= ARM_SMMU_PTE_HAP_READ; |
b410aed9 | 1281 | if (prot & IOMMU_WRITE) |
45ae7cff | 1282 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
b410aed9 | 1283 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1284 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
1285 | else | |
1286 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; | |
1287 | } | |
1288 | ||
1289 | /* If no access, create a faulting entry to avoid TLB fills */ | |
b410aed9 | 1290 | if (prot & IOMMU_EXEC) |
cf2d45b1 | 1291 | pteval &= ~ARM_SMMU_PTE_XN; |
b410aed9 | 1292 | else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) |
45ae7cff WD |
1293 | pteval &= ~ARM_SMMU_PTE_PAGE; |
1294 | ||
1295 | pteval |= ARM_SMMU_PTE_SH_IS; | |
1296 | start = pmd_page_vaddr(*pmd) + pte_index(addr); | |
1297 | pte = start; | |
1298 | ||
1299 | /* | |
1300 | * Install the page table entries. This is fairly complicated | |
1301 | * since we attempt to make use of the contiguous hint in the | |
1302 | * ptes where possible. The contiguous hint indicates a series | |
1303 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically | |
1304 | * contiguous region with the following constraints: | |
1305 | * | |
1306 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE | |
1307 | * - Each pte in the region has the contiguous hint bit set | |
1308 | * | |
1309 | * This complicates unmapping (also handled by this code, when | |
1310 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is | |
1311 | * possible, yet highly unlikely, that a client may unmap only | |
1312 | * part of a contiguous range. This requires clearing of the | |
1313 | * contiguous hint bits in the range before installing the new | |
1314 | * faulting entries. | |
1315 | * | |
1316 | * Note that re-mapping an address range without first unmapping | |
1317 | * it is not supported, so TLB invalidation is not required here | |
1318 | * and is instead performed at unmap and domain-init time. | |
1319 | */ | |
1320 | do { | |
1321 | int i = 1; | |
2907320d | 1322 | |
45ae7cff WD |
1323 | pteval &= ~ARM_SMMU_PTE_CONT; |
1324 | ||
1325 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { | |
1326 | i = ARM_SMMU_PTE_CONT_ENTRIES; | |
1327 | pteval |= ARM_SMMU_PTE_CONT; | |
1328 | } else if (pte_val(*pte) & | |
1329 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { | |
1330 | int j; | |
1331 | pte_t *cont_start; | |
1332 | unsigned long idx = pte_index(addr); | |
1333 | ||
1334 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); | |
1335 | cont_start = pmd_page_vaddr(*pmd) + idx; | |
1336 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) | |
2907320d MH |
1337 | pte_val(*(cont_start + j)) &= |
1338 | ~ARM_SMMU_PTE_CONT; | |
45ae7cff WD |
1339 | |
1340 | arm_smmu_flush_pgtable(smmu, cont_start, | |
1341 | sizeof(*pte) * | |
1342 | ARM_SMMU_PTE_CONT_ENTRIES); | |
1343 | } | |
1344 | ||
1345 | do { | |
1346 | *pte = pfn_pte(pfn, __pgprot(pteval)); | |
1347 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); | |
1348 | } while (addr != end); | |
1349 | ||
1350 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); | |
1351 | return 0; | |
1352 | } | |
1353 | ||
1354 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, | |
1355 | unsigned long addr, unsigned long end, | |
b410aed9 | 1356 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1357 | { |
1358 | int ret; | |
1359 | pmd_t *pmd; | |
1360 | unsigned long next, pfn = __phys_to_pfn(phys); | |
1361 | ||
1362 | #ifndef __PAGETABLE_PMD_FOLDED | |
1363 | if (pud_none(*pud)) { | |
c9d09e27 | 1364 | pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1365 | if (!pmd) |
1366 | return -ENOMEM; | |
97a64420 | 1367 | |
6dd35f45 | 1368 | arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE); |
97a64420 YZ |
1369 | pud_populate(NULL, pud, pmd); |
1370 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); | |
1371 | ||
1372 | pmd += pmd_index(addr); | |
45ae7cff WD |
1373 | } else |
1374 | #endif | |
1375 | pmd = pmd_offset(pud, addr); | |
1376 | ||
1377 | do { | |
1378 | next = pmd_addr_end(addr, end); | |
aca1bc45 | 1379 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn, |
b410aed9 | 1380 | prot, stage); |
45ae7cff WD |
1381 | phys += next - addr; |
1382 | } while (pmd++, addr = next, addr < end); | |
1383 | ||
1384 | return ret; | |
1385 | } | |
1386 | ||
1387 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, | |
1388 | unsigned long addr, unsigned long end, | |
b410aed9 | 1389 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1390 | { |
1391 | int ret = 0; | |
1392 | pud_t *pud; | |
1393 | unsigned long next; | |
1394 | ||
1395 | #ifndef __PAGETABLE_PUD_FOLDED | |
1396 | if (pgd_none(*pgd)) { | |
c9d09e27 | 1397 | pud = (pud_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1398 | if (!pud) |
1399 | return -ENOMEM; | |
97a64420 | 1400 | |
6dd35f45 | 1401 | arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE); |
97a64420 YZ |
1402 | pgd_populate(NULL, pgd, pud); |
1403 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); | |
1404 | ||
1405 | pud += pud_index(addr); | |
45ae7cff WD |
1406 | } else |
1407 | #endif | |
1408 | pud = pud_offset(pgd, addr); | |
1409 | ||
1410 | do { | |
1411 | next = pud_addr_end(addr, end); | |
1412 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, | |
b410aed9 | 1413 | prot, stage); |
45ae7cff WD |
1414 | phys += next - addr; |
1415 | } while (pud++, addr = next, addr < end); | |
1416 | ||
1417 | return ret; | |
1418 | } | |
1419 | ||
1420 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, | |
1421 | unsigned long iova, phys_addr_t paddr, | |
b410aed9 | 1422 | size_t size, int prot) |
45ae7cff WD |
1423 | { |
1424 | int ret, stage; | |
1425 | unsigned long end; | |
1426 | phys_addr_t input_mask, output_mask; | |
44680eed WD |
1427 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1428 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1429 | pgd_t *pgd = cfg->pgd; | |
b410aed9 | 1430 | unsigned long flags; |
45ae7cff | 1431 | |
44680eed | 1432 | if (cfg->cbar == CBAR_TYPE_S2_TRANS) { |
45ae7cff WD |
1433 | stage = 2; |
1434 | output_mask = (1ULL << smmu->s2_output_size) - 1; | |
1435 | } else { | |
1436 | stage = 1; | |
1437 | output_mask = (1ULL << smmu->s1_output_size) - 1; | |
1438 | } | |
1439 | ||
1440 | if (!pgd) | |
1441 | return -EINVAL; | |
1442 | ||
1443 | if (size & ~PAGE_MASK) | |
1444 | return -EINVAL; | |
1445 | ||
1446 | input_mask = (1ULL << smmu->input_size) - 1; | |
1447 | if ((phys_addr_t)iova & ~input_mask) | |
1448 | return -ERANGE; | |
1449 | ||
1450 | if (paddr & ~output_mask) | |
1451 | return -ERANGE; | |
1452 | ||
b410aed9 | 1453 | spin_lock_irqsave(&smmu_domain->lock, flags); |
45ae7cff WD |
1454 | pgd += pgd_index(iova); |
1455 | end = iova + size; | |
1456 | do { | |
1457 | unsigned long next = pgd_addr_end(iova, end); | |
1458 | ||
1459 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, | |
b410aed9 | 1460 | prot, stage); |
45ae7cff WD |
1461 | if (ret) |
1462 | goto out_unlock; | |
1463 | ||
1464 | paddr += next - iova; | |
1465 | iova = next; | |
1466 | } while (pgd++, iova != end); | |
1467 | ||
1468 | out_unlock: | |
b410aed9 | 1469 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff | 1470 | |
45ae7cff WD |
1471 | return ret; |
1472 | } | |
1473 | ||
1474 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
b410aed9 | 1475 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff WD |
1476 | { |
1477 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff | 1478 | |
5552ecdb | 1479 | if (!smmu_domain) |
45ae7cff WD |
1480 | return -ENODEV; |
1481 | ||
b410aed9 | 1482 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot); |
45ae7cff WD |
1483 | } |
1484 | ||
1485 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1486 | size_t size) | |
1487 | { | |
1488 | int ret; | |
1489 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff WD |
1490 | |
1491 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); | |
44680eed | 1492 | arm_smmu_tlb_inv_context(smmu_domain); |
16c50dcf | 1493 | return ret ? 0 : size; |
45ae7cff WD |
1494 | } |
1495 | ||
1496 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1497 | dma_addr_t iova) | |
1498 | { | |
a44a9791 WD |
1499 | pgd_t *pgdp, pgd; |
1500 | pud_t pud; | |
1501 | pmd_t pmd; | |
1502 | pte_t pte; | |
45ae7cff | 1503 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1504 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 1505 | |
44680eed | 1506 | pgdp = cfg->pgd; |
a44a9791 WD |
1507 | if (!pgdp) |
1508 | return 0; | |
45ae7cff | 1509 | |
a44a9791 WD |
1510 | pgd = *(pgdp + pgd_index(iova)); |
1511 | if (pgd_none(pgd)) | |
1512 | return 0; | |
45ae7cff | 1513 | |
a44a9791 WD |
1514 | pud = *pud_offset(&pgd, iova); |
1515 | if (pud_none(pud)) | |
1516 | return 0; | |
45ae7cff | 1517 | |
a44a9791 WD |
1518 | pmd = *pmd_offset(&pud, iova); |
1519 | if (pmd_none(pmd)) | |
1520 | return 0; | |
45ae7cff | 1521 | |
a44a9791 | 1522 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
45ae7cff | 1523 | if (pte_none(pte)) |
a44a9791 | 1524 | return 0; |
45ae7cff | 1525 | |
a44a9791 | 1526 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
45ae7cff WD |
1527 | } |
1528 | ||
1529 | static int arm_smmu_domain_has_cap(struct iommu_domain *domain, | |
1530 | unsigned long cap) | |
1531 | { | |
45ae7cff | 1532 | struct arm_smmu_domain *smmu_domain = domain->priv; |
d3bca166 WD |
1533 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1534 | u32 features = smmu ? smmu->features : 0; | |
d0948945 WD |
1535 | |
1536 | switch (cap) { | |
1537 | case IOMMU_CAP_CACHE_COHERENCY: | |
1538 | return features & ARM_SMMU_FEAT_COHERENT_WALK; | |
1539 | case IOMMU_CAP_INTR_REMAP: | |
1540 | return 1; /* MSIs are just memory writes */ | |
1541 | default: | |
1542 | return 0; | |
1543 | } | |
45ae7cff | 1544 | } |
45ae7cff | 1545 | |
a9a1b0b5 WD |
1546 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1547 | { | |
1548 | *((u16 *)data) = alias; | |
1549 | return 0; /* Continue walking */ | |
45ae7cff WD |
1550 | } |
1551 | ||
1552 | static int arm_smmu_add_device(struct device *dev) | |
1553 | { | |
a9a1b0b5 | 1554 | struct arm_smmu_device *smmu; |
5fc63a7c AM |
1555 | struct iommu_group *group; |
1556 | int ret; | |
1557 | ||
1558 | if (dev->archdata.iommu) { | |
1559 | dev_warn(dev, "IOMMU driver already assigned to device\n"); | |
1560 | return -EINVAL; | |
1561 | } | |
45ae7cff | 1562 | |
44680eed | 1563 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1564 | if (!smmu) |
45ae7cff WD |
1565 | return -ENODEV; |
1566 | ||
5fc63a7c AM |
1567 | group = iommu_group_alloc(); |
1568 | if (IS_ERR(group)) { | |
1569 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1570 | return PTR_ERR(group); | |
1571 | } | |
1572 | ||
a9a1b0b5 WD |
1573 | if (dev_is_pci(dev)) { |
1574 | struct arm_smmu_master_cfg *cfg; | |
1575 | struct pci_dev *pdev = to_pci_dev(dev); | |
1576 | ||
1577 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1578 | if (!cfg) { | |
1579 | ret = -ENOMEM; | |
1580 | goto out_put_group; | |
1581 | } | |
1582 | ||
1583 | cfg->num_streamids = 1; | |
1584 | /* | |
1585 | * Assume Stream ID == Requester ID for now. | |
1586 | * We need a way to describe the ID mappings in FDT. | |
1587 | */ | |
1588 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1589 | &cfg->streamids[0]); | |
1590 | dev->archdata.iommu = cfg; | |
1591 | } else { | |
1592 | dev->archdata.iommu = smmu; | |
1593 | } | |
1594 | ||
5fc63a7c | 1595 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1596 | |
a9a1b0b5 WD |
1597 | out_put_group: |
1598 | iommu_group_put(group); | |
5fc63a7c | 1599 | return ret; |
45ae7cff WD |
1600 | } |
1601 | ||
1602 | static void arm_smmu_remove_device(struct device *dev) | |
1603 | { | |
a9a1b0b5 WD |
1604 | if (dev_is_pci(dev)) |
1605 | kfree(dev->archdata.iommu); | |
1606 | ||
45ae7cff | 1607 | dev->archdata.iommu = NULL; |
5fc63a7c | 1608 | iommu_group_remove_device(dev); |
45ae7cff WD |
1609 | } |
1610 | ||
b22f6434 | 1611 | static const struct iommu_ops arm_smmu_ops = { |
45ae7cff WD |
1612 | .domain_init = arm_smmu_domain_init, |
1613 | .domain_destroy = arm_smmu_domain_destroy, | |
1614 | .attach_dev = arm_smmu_attach_dev, | |
1615 | .detach_dev = arm_smmu_detach_dev, | |
1616 | .map = arm_smmu_map, | |
1617 | .unmap = arm_smmu_unmap, | |
1618 | .iova_to_phys = arm_smmu_iova_to_phys, | |
1619 | .domain_has_cap = arm_smmu_domain_has_cap, | |
1620 | .add_device = arm_smmu_add_device, | |
1621 | .remove_device = arm_smmu_remove_device, | |
1622 | .pgsize_bitmap = (SECTION_SIZE | | |
1623 | ARM_SMMU_PTE_CONT_SIZE | | |
1624 | PAGE_SIZE), | |
1625 | }; | |
1626 | ||
1627 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1628 | { | |
1629 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1630 | void __iomem *cb_base; |
45ae7cff | 1631 | int i = 0; |
659db6f6 AH |
1632 | u32 reg; |
1633 | ||
3a5df8ff AH |
1634 | /* clear global FSR */ |
1635 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1636 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1637 | |
1638 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1639 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
3c8766d0 | 1640 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
2907320d MH |
1641 | writel_relaxed(S2CR_TYPE_BYPASS, |
1642 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1643 | } |
1644 | ||
659db6f6 AH |
1645 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1646 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1647 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1648 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1649 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1650 | } | |
1463fe44 | 1651 | |
45ae7cff WD |
1652 | /* Invalidate the TLB, just in case */ |
1653 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); | |
1654 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); | |
1655 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1656 | ||
3a5df8ff | 1657 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1658 | |
45ae7cff | 1659 | /* Enable fault reporting */ |
659db6f6 | 1660 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1661 | |
1662 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1663 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1664 | |
1665 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1666 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1667 | |
1668 | /* Disable forced broadcasting */ | |
659db6f6 | 1669 | reg &= ~sCR0_FB; |
45ae7cff WD |
1670 | |
1671 | /* Don't upgrade barriers */ | |
659db6f6 | 1672 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1673 | |
1674 | /* Push the button */ | |
1675 | arm_smmu_tlb_sync(smmu); | |
3a5df8ff | 1676 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1677 | } |
1678 | ||
1679 | static int arm_smmu_id_size_to_bits(int size) | |
1680 | { | |
1681 | switch (size) { | |
1682 | case 0: | |
1683 | return 32; | |
1684 | case 1: | |
1685 | return 36; | |
1686 | case 2: | |
1687 | return 40; | |
1688 | case 3: | |
1689 | return 42; | |
1690 | case 4: | |
1691 | return 44; | |
1692 | case 5: | |
1693 | default: | |
1694 | return 48; | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1699 | { | |
1700 | unsigned long size; | |
1701 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1702 | u32 id; | |
1703 | ||
1704 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
1705 | ||
1706 | /* Primecell ID */ | |
1707 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); | |
1708 | smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; | |
1709 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); | |
1710 | ||
1711 | /* ID0 */ | |
1712 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
1713 | #ifndef CONFIG_64BIT | |
1714 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { | |
1715 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); | |
1716 | return -ENODEV; | |
1717 | } | |
1718 | #endif | |
1719 | if (id & ID0_S1TS) { | |
1720 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1721 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1722 | } | |
1723 | ||
1724 | if (id & ID0_S2TS) { | |
1725 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1726 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1727 | } | |
1728 | ||
1729 | if (id & ID0_NTS) { | |
1730 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1731 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1732 | } | |
1733 | ||
1734 | if (!(smmu->features & | |
1735 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | | |
1736 | ARM_SMMU_FEAT_TRANS_NESTED))) { | |
1737 | dev_err(smmu->dev, "\tno translation support!\n"); | |
1738 | return -ENODEV; | |
1739 | } | |
1740 | ||
1741 | if (id & ID0_CTTW) { | |
1742 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1743 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1744 | } | |
1745 | ||
1746 | if (id & ID0_SMS) { | |
1747 | u32 smr, sid, mask; | |
1748 | ||
1749 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1750 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1751 | ID0_NUMSMRG_MASK; | |
1752 | if (smmu->num_mapping_groups == 0) { | |
1753 | dev_err(smmu->dev, | |
1754 | "stream-matching supported, but no SMRs present!\n"); | |
1755 | return -ENODEV; | |
1756 | } | |
1757 | ||
1758 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1759 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1760 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1761 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1762 | ||
1763 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1764 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1765 | if ((mask & sid) != sid) { | |
1766 | dev_err(smmu->dev, | |
1767 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1768 | mask, sid); | |
1769 | return -ENODEV; | |
1770 | } | |
1771 | ||
1772 | dev_notice(smmu->dev, | |
1773 | "\tstream matching with %u register groups, mask 0x%x", | |
1774 | smmu->num_mapping_groups, mask); | |
3c8766d0 OH |
1775 | } else { |
1776 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & | |
1777 | ID0_NUMSIDB_MASK; | |
45ae7cff WD |
1778 | } |
1779 | ||
1780 | /* ID1 */ | |
1781 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
1782 | smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; | |
1783 | ||
c55af7f7 | 1784 | /* Check for size mismatch of SMMU address space from mapped region */ |
2907320d MH |
1785 | size = 1 << |
1786 | (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); | |
45ae7cff | 1787 | size *= (smmu->pagesize << 1); |
c55af7f7 | 1788 | if (smmu->size != size) |
2907320d MH |
1789 | dev_warn(smmu->dev, |
1790 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1791 | size, smmu->size); | |
45ae7cff WD |
1792 | |
1793 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & | |
1794 | ID1_NUMS2CB_MASK; | |
1795 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; | |
1796 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1797 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1798 | return -ENODEV; | |
1799 | } | |
1800 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1801 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1802 | ||
1803 | /* ID2 */ | |
1804 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1805 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
1806 | ||
1807 | /* | |
1808 | * Stage-1 output limited by stage-2 input size due to pgd | |
1809 | * allocation (PTRS_PER_PGD). | |
1810 | */ | |
4d09d99d | 1811 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
45ae7cff | 1812 | #ifdef CONFIG_64BIT |
4d09d99d | 1813 | smmu->s1_output_size = min_t(unsigned long, VA_BITS, size); |
45ae7cff | 1814 | #else |
4d09d99d | 1815 | smmu->s1_output_size = min(32UL, size); |
45ae7cff | 1816 | #endif |
4d09d99d WD |
1817 | } else { |
1818 | smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, | |
1819 | size); | |
1820 | } | |
45ae7cff WD |
1821 | |
1822 | /* The stage-2 output mask is also applied for bypass */ | |
1823 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); | |
2907320d | 1824 | smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); |
45ae7cff WD |
1825 | |
1826 | if (smmu->version == 1) { | |
1827 | smmu->input_size = 32; | |
1828 | } else { | |
1829 | #ifdef CONFIG_64BIT | |
1830 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; | |
06f983dd | 1831 | size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); |
45ae7cff WD |
1832 | #else |
1833 | size = 32; | |
1834 | #endif | |
1835 | smmu->input_size = size; | |
1836 | ||
1837 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || | |
1838 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || | |
1839 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { | |
1840 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", | |
1841 | PAGE_SIZE); | |
1842 | return -ENODEV; | |
1843 | } | |
1844 | } | |
1845 | ||
1846 | dev_notice(smmu->dev, | |
1847 | "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", | |
2907320d MH |
1848 | smmu->input_size, smmu->s1_output_size, |
1849 | smmu->s2_output_size); | |
45ae7cff WD |
1850 | return 0; |
1851 | } | |
1852 | ||
1853 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) | |
1854 | { | |
1855 | struct resource *res; | |
1856 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1857 | struct device *dev = &pdev->dev; |
1858 | struct rb_node *node; | |
1859 | struct of_phandle_args masterspec; | |
1860 | int num_irqs, i, err; | |
1861 | ||
1862 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1863 | if (!smmu) { | |
1864 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1865 | return -ENOMEM; | |
1866 | } | |
1867 | smmu->dev = dev; | |
1868 | ||
1869 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8a7f4312 JL |
1870 | smmu->base = devm_ioremap_resource(dev, res); |
1871 | if (IS_ERR(smmu->base)) | |
1872 | return PTR_ERR(smmu->base); | |
45ae7cff | 1873 | smmu->size = resource_size(res); |
45ae7cff WD |
1874 | |
1875 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1876 | &smmu->num_global_irqs)) { | |
1877 | dev_err(dev, "missing #global-interrupts property\n"); | |
1878 | return -ENODEV; | |
1879 | } | |
1880 | ||
1881 | num_irqs = 0; | |
1882 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1883 | num_irqs++; | |
1884 | if (num_irqs > smmu->num_global_irqs) | |
1885 | smmu->num_context_irqs++; | |
1886 | } | |
1887 | ||
44a08de2 AH |
1888 | if (!smmu->num_context_irqs) { |
1889 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1890 | num_irqs, smmu->num_global_irqs + 1); | |
1891 | return -ENODEV; | |
45ae7cff | 1892 | } |
45ae7cff WD |
1893 | |
1894 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1895 | GFP_KERNEL); | |
1896 | if (!smmu->irqs) { | |
1897 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1898 | return -ENOMEM; | |
1899 | } | |
1900 | ||
1901 | for (i = 0; i < num_irqs; ++i) { | |
1902 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1903 | |
45ae7cff WD |
1904 | if (irq < 0) { |
1905 | dev_err(dev, "failed to get irq index %d\n", i); | |
1906 | return -ENODEV; | |
1907 | } | |
1908 | smmu->irqs[i] = irq; | |
1909 | } | |
1910 | ||
3c8766d0 OH |
1911 | err = arm_smmu_device_cfg_probe(smmu); |
1912 | if (err) | |
1913 | return err; | |
1914 | ||
45ae7cff WD |
1915 | i = 0; |
1916 | smmu->masters = RB_ROOT; | |
1917 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1918 | "#stream-id-cells", i, | |
1919 | &masterspec)) { | |
1920 | err = register_smmu_master(smmu, dev, &masterspec); | |
1921 | if (err) { | |
1922 | dev_err(dev, "failed to add master %s\n", | |
1923 | masterspec.np->name); | |
1924 | goto out_put_masters; | |
1925 | } | |
1926 | ||
1927 | i++; | |
1928 | } | |
1929 | dev_notice(dev, "registered %d master devices\n", i); | |
1930 | ||
3a5df8ff AH |
1931 | parse_driver_options(smmu); |
1932 | ||
45ae7cff WD |
1933 | if (smmu->version > 1 && |
1934 | smmu->num_context_banks != smmu->num_context_irqs) { | |
1935 | dev_err(dev, | |
1936 | "found only %d context interrupt(s) but %d required\n", | |
1937 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1938 | err = -ENODEV; |
44680eed | 1939 | goto out_put_masters; |
45ae7cff WD |
1940 | } |
1941 | ||
45ae7cff WD |
1942 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1943 | err = request_irq(smmu->irqs[i], | |
1944 | arm_smmu_global_fault, | |
1945 | IRQF_SHARED, | |
1946 | "arm-smmu global fault", | |
1947 | smmu); | |
1948 | if (err) { | |
1949 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1950 | i, smmu->irqs[i]); | |
1951 | goto out_free_irqs; | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | INIT_LIST_HEAD(&smmu->list); | |
1956 | spin_lock(&arm_smmu_devices_lock); | |
1957 | list_add(&smmu->list, &arm_smmu_devices); | |
1958 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1959 | |
1960 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1961 | return 0; |
1962 | ||
1963 | out_free_irqs: | |
1964 | while (i--) | |
1965 | free_irq(smmu->irqs[i], smmu); | |
1966 | ||
45ae7cff WD |
1967 | out_put_masters: |
1968 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
1969 | struct arm_smmu_master *master |
1970 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1971 | of_node_put(master->of_node); |
1972 | } | |
1973 | ||
1974 | return err; | |
1975 | } | |
1976 | ||
1977 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1978 | { | |
1979 | int i; | |
1980 | struct device *dev = &pdev->dev; | |
1981 | struct arm_smmu_device *curr, *smmu = NULL; | |
1982 | struct rb_node *node; | |
1983 | ||
1984 | spin_lock(&arm_smmu_devices_lock); | |
1985 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1986 | if (curr->dev == dev) { | |
1987 | smmu = curr; | |
1988 | list_del(&smmu->list); | |
1989 | break; | |
1990 | } | |
1991 | } | |
1992 | spin_unlock(&arm_smmu_devices_lock); | |
1993 | ||
1994 | if (!smmu) | |
1995 | return -ENODEV; | |
1996 | ||
45ae7cff | 1997 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
1998 | struct arm_smmu_master *master |
1999 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
2000 | of_node_put(master->of_node); |
2001 | } | |
2002 | ||
ecfadb6e | 2003 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
2004 | dev_err(dev, "removing device with active domains!\n"); |
2005 | ||
2006 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
2007 | free_irq(smmu->irqs[i], smmu); | |
2008 | ||
2009 | /* Turn the thing off */ | |
2907320d | 2010 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
2011 | return 0; |
2012 | } | |
2013 | ||
2014 | #ifdef CONFIG_OF | |
2015 | static struct of_device_id arm_smmu_of_match[] = { | |
2016 | { .compatible = "arm,smmu-v1", }, | |
2017 | { .compatible = "arm,smmu-v2", }, | |
2018 | { .compatible = "arm,mmu-400", }, | |
2019 | { .compatible = "arm,mmu-500", }, | |
2020 | { }, | |
2021 | }; | |
2022 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
2023 | #endif | |
2024 | ||
2025 | static struct platform_driver arm_smmu_driver = { | |
2026 | .driver = { | |
2027 | .owner = THIS_MODULE, | |
2028 | .name = "arm-smmu", | |
2029 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
2030 | }, | |
2031 | .probe = arm_smmu_device_dt_probe, | |
2032 | .remove = arm_smmu_device_remove, | |
2033 | }; | |
2034 | ||
2035 | static int __init arm_smmu_init(void) | |
2036 | { | |
2037 | int ret; | |
2038 | ||
2039 | ret = platform_driver_register(&arm_smmu_driver); | |
2040 | if (ret) | |
2041 | return ret; | |
2042 | ||
2043 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 2044 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
2045 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
2046 | ||
d123cf82 | 2047 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 2048 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 2049 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 2050 | #endif |
45ae7cff | 2051 | |
a9a1b0b5 WD |
2052 | #ifdef CONFIG_PCI |
2053 | if (!iommu_present(&pci_bus_type)) | |
2054 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
2055 | #endif | |
2056 | ||
45ae7cff WD |
2057 | return 0; |
2058 | } | |
2059 | ||
2060 | static void __exit arm_smmu_exit(void) | |
2061 | { | |
2062 | return platform_driver_unregister(&arm_smmu_driver); | |
2063 | } | |
2064 | ||
b1950b27 | 2065 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
2066 | module_exit(arm_smmu_exit); |
2067 | ||
2068 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
2069 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
2070 | MODULE_LICENSE("GPL v2"); |