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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
26 | * - 4k and 64k pages, with contiguous pte hints. | |
06f983dd | 27 | * - Up to 42-bit addressing (dependent on VA_BITS) |
45ae7cff WD |
28 | * - Context fault reporting |
29 | */ | |
30 | ||
31 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
32 | ||
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/iommu.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/of.h> | |
a9a1b0b5 | 42 | #include <linux/pci.h> |
45ae7cff WD |
43 | #include <linux/platform_device.h> |
44 | #include <linux/slab.h> | |
45 | #include <linux/spinlock.h> | |
46 | ||
47 | #include <linux/amba/bus.h> | |
48 | ||
49 | #include <asm/pgalloc.h> | |
50 | ||
51 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 52 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
53 | |
54 | /* Maximum number of context banks per SMMU */ | |
55 | #define ARM_SMMU_MAX_CBS 128 | |
56 | ||
57 | /* Maximum number of mapping groups per SMMU */ | |
58 | #define ARM_SMMU_MAX_SMRS 128 | |
59 | ||
45ae7cff WD |
60 | /* SMMU global address space */ |
61 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
62 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) | |
63 | ||
3a5df8ff AH |
64 | /* |
65 | * SMMU global address space with conditional offset to access secure | |
66 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
67 | * nsGFSYNR0: 0x450) | |
68 | */ | |
69 | #define ARM_SMMU_GR0_NS(smmu) \ | |
70 | ((smmu)->base + \ | |
71 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
72 | ? 0x400 : 0)) | |
73 | ||
45ae7cff | 74 | /* Page table bits */ |
cf2d45b1 | 75 | #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) |
45ae7cff WD |
76 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
77 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) | |
78 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) | |
79 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) | |
80 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) | |
cf2d45b1 | 81 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
45ae7cff WD |
82 | |
83 | #if PAGE_SIZE == SZ_4K | |
84 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 | |
85 | #elif PAGE_SIZE == SZ_64K | |
86 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 | |
87 | #else | |
88 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 | |
89 | #endif | |
90 | ||
91 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) | |
92 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) | |
45ae7cff WD |
93 | |
94 | /* Stage-1 PTE */ | |
95 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) | |
96 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) | |
97 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 | |
1463fe44 | 98 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
45ae7cff WD |
99 | |
100 | /* Stage-2 PTE */ | |
101 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) | |
102 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) | |
103 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) | |
104 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) | |
105 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) | |
106 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) | |
107 | ||
108 | /* Configuration registers */ | |
109 | #define ARM_SMMU_GR0_sCR0 0x0 | |
110 | #define sCR0_CLIENTPD (1 << 0) | |
111 | #define sCR0_GFRE (1 << 1) | |
112 | #define sCR0_GFIE (1 << 2) | |
113 | #define sCR0_GCFGFRE (1 << 4) | |
114 | #define sCR0_GCFGFIE (1 << 5) | |
115 | #define sCR0_USFCFG (1 << 10) | |
116 | #define sCR0_VMIDPNE (1 << 11) | |
117 | #define sCR0_PTM (1 << 12) | |
118 | #define sCR0_FB (1 << 13) | |
119 | #define sCR0_BSU_SHIFT 14 | |
120 | #define sCR0_BSU_MASK 0x3 | |
121 | ||
122 | /* Identification registers */ | |
123 | #define ARM_SMMU_GR0_ID0 0x20 | |
124 | #define ARM_SMMU_GR0_ID1 0x24 | |
125 | #define ARM_SMMU_GR0_ID2 0x28 | |
126 | #define ARM_SMMU_GR0_ID3 0x2c | |
127 | #define ARM_SMMU_GR0_ID4 0x30 | |
128 | #define ARM_SMMU_GR0_ID5 0x34 | |
129 | #define ARM_SMMU_GR0_ID6 0x38 | |
130 | #define ARM_SMMU_GR0_ID7 0x3c | |
131 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
132 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
133 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
134 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
135 | #define ARM_SMMU_GR0_PIDR0 0xfe0 | |
136 | #define ARM_SMMU_GR0_PIDR1 0xfe4 | |
137 | #define ARM_SMMU_GR0_PIDR2 0xfe8 | |
138 | ||
139 | #define ID0_S1TS (1 << 30) | |
140 | #define ID0_S2TS (1 << 29) | |
141 | #define ID0_NTS (1 << 28) | |
142 | #define ID0_SMS (1 << 27) | |
143 | #define ID0_PTFS_SHIFT 24 | |
144 | #define ID0_PTFS_MASK 0x2 | |
145 | #define ID0_PTFS_V8_ONLY 0x2 | |
146 | #define ID0_CTTW (1 << 14) | |
147 | #define ID0_NUMIRPT_SHIFT 16 | |
148 | #define ID0_NUMIRPT_MASK 0xff | |
149 | #define ID0_NUMSMRG_SHIFT 0 | |
150 | #define ID0_NUMSMRG_MASK 0xff | |
151 | ||
152 | #define ID1_PAGESIZE (1 << 31) | |
153 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
154 | #define ID1_NUMPAGENDXB_MASK 7 | |
155 | #define ID1_NUMS2CB_SHIFT 16 | |
156 | #define ID1_NUMS2CB_MASK 0xff | |
157 | #define ID1_NUMCB_SHIFT 0 | |
158 | #define ID1_NUMCB_MASK 0xff | |
159 | ||
160 | #define ID2_OAS_SHIFT 4 | |
161 | #define ID2_OAS_MASK 0xf | |
162 | #define ID2_IAS_SHIFT 0 | |
163 | #define ID2_IAS_MASK 0xf | |
164 | #define ID2_UBS_SHIFT 8 | |
165 | #define ID2_UBS_MASK 0xf | |
166 | #define ID2_PTFS_4K (1 << 12) | |
167 | #define ID2_PTFS_16K (1 << 13) | |
168 | #define ID2_PTFS_64K (1 << 14) | |
169 | ||
170 | #define PIDR2_ARCH_SHIFT 4 | |
171 | #define PIDR2_ARCH_MASK 0xf | |
172 | ||
173 | /* Global TLB invalidation */ | |
174 | #define ARM_SMMU_GR0_STLBIALL 0x60 | |
175 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
176 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
177 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
178 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
179 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
180 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
181 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
182 | ||
183 | /* Stream mapping registers */ | |
184 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
185 | #define SMR_VALID (1 << 31) | |
186 | #define SMR_MASK_SHIFT 16 | |
187 | #define SMR_MASK_MASK 0x7fff | |
188 | #define SMR_ID_SHIFT 0 | |
189 | #define SMR_ID_MASK 0x7fff | |
190 | ||
191 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
192 | #define S2CR_CBNDX_SHIFT 0 | |
193 | #define S2CR_CBNDX_MASK 0xff | |
194 | #define S2CR_TYPE_SHIFT 16 | |
195 | #define S2CR_TYPE_MASK 0x3 | |
196 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
197 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
198 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
199 | ||
200 | /* Context bank attribute registers */ | |
201 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
202 | #define CBAR_VMID_SHIFT 0 | |
203 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
204 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
205 | #define CBAR_S1_BPSHCFG_MASK 3 | |
206 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
207 | #define CBAR_S1_MEMATTR_SHIFT 12 |
208 | #define CBAR_S1_MEMATTR_MASK 0xf | |
209 | #define CBAR_S1_MEMATTR_WB 0xf | |
210 | #define CBAR_TYPE_SHIFT 16 | |
211 | #define CBAR_TYPE_MASK 0x3 | |
212 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
213 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
214 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
215 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
216 | #define CBAR_IRPTNDX_SHIFT 24 | |
217 | #define CBAR_IRPTNDX_MASK 0xff | |
218 | ||
219 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
220 | #define CBA2R_RW64_32BIT (0 << 0) | |
221 | #define CBA2R_RW64_64BIT (1 << 0) | |
222 | ||
223 | /* Translation context bank */ | |
224 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
225 | #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) | |
226 | ||
227 | #define ARM_SMMU_CB_SCTLR 0x0 | |
228 | #define ARM_SMMU_CB_RESUME 0x8 | |
229 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
230 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
231 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
232 | #define ARM_SMMU_CB_TTBCR 0x30 | |
233 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
234 | #define ARM_SMMU_CB_FSR 0x58 | |
235 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
236 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
237 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
1463fe44 | 238 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
45ae7cff WD |
239 | |
240 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
241 | #define SCTLR_CFCFG (1 << 7) | |
242 | #define SCTLR_CFIE (1 << 6) | |
243 | #define SCTLR_CFRE (1 << 5) | |
244 | #define SCTLR_E (1 << 4) | |
245 | #define SCTLR_AFE (1 << 2) | |
246 | #define SCTLR_TRE (1 << 1) | |
247 | #define SCTLR_M (1 << 0) | |
248 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
249 | ||
250 | #define RESUME_RETRY (0 << 0) | |
251 | #define RESUME_TERMINATE (1 << 0) | |
252 | ||
253 | #define TTBCR_EAE (1 << 31) | |
254 | ||
255 | #define TTBCR_PASIZE_SHIFT 16 | |
256 | #define TTBCR_PASIZE_MASK 0x7 | |
257 | ||
258 | #define TTBCR_TG0_4K (0 << 14) | |
259 | #define TTBCR_TG0_64K (1 << 14) | |
260 | ||
261 | #define TTBCR_SH0_SHIFT 12 | |
262 | #define TTBCR_SH0_MASK 0x3 | |
263 | #define TTBCR_SH_NS 0 | |
264 | #define TTBCR_SH_OS 2 | |
265 | #define TTBCR_SH_IS 3 | |
266 | ||
267 | #define TTBCR_ORGN0_SHIFT 10 | |
268 | #define TTBCR_IRGN0_SHIFT 8 | |
269 | #define TTBCR_RGN_MASK 0x3 | |
270 | #define TTBCR_RGN_NC 0 | |
271 | #define TTBCR_RGN_WBWA 1 | |
272 | #define TTBCR_RGN_WT 2 | |
273 | #define TTBCR_RGN_WB 3 | |
274 | ||
275 | #define TTBCR_SL0_SHIFT 6 | |
276 | #define TTBCR_SL0_MASK 0x3 | |
277 | #define TTBCR_SL0_LVL_2 0 | |
278 | #define TTBCR_SL0_LVL_1 1 | |
279 | ||
280 | #define TTBCR_T1SZ_SHIFT 16 | |
281 | #define TTBCR_T0SZ_SHIFT 0 | |
282 | #define TTBCR_SZ_MASK 0xf | |
283 | ||
284 | #define TTBCR2_SEP_SHIFT 15 | |
285 | #define TTBCR2_SEP_MASK 0x7 | |
286 | ||
287 | #define TTBCR2_PASIZE_SHIFT 0 | |
288 | #define TTBCR2_PASIZE_MASK 0x7 | |
289 | ||
290 | /* Common definitions for PASize and SEP fields */ | |
291 | #define TTBCR2_ADDR_32 0 | |
292 | #define TTBCR2_ADDR_36 1 | |
293 | #define TTBCR2_ADDR_40 2 | |
294 | #define TTBCR2_ADDR_42 3 | |
295 | #define TTBCR2_ADDR_44 4 | |
296 | #define TTBCR2_ADDR_48 5 | |
297 | ||
1463fe44 WD |
298 | #define TTBRn_HI_ASID_SHIFT 16 |
299 | ||
45ae7cff WD |
300 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
301 | #define MAIR_ATTR_MASK 0xff | |
302 | #define MAIR_ATTR_DEVICE 0x04 | |
303 | #define MAIR_ATTR_NC 0x44 | |
304 | #define MAIR_ATTR_WBRWA 0xff | |
305 | #define MAIR_ATTR_IDX_NC 0 | |
306 | #define MAIR_ATTR_IDX_CACHE 1 | |
307 | #define MAIR_ATTR_IDX_DEV 2 | |
308 | ||
309 | #define FSR_MULTI (1 << 31) | |
310 | #define FSR_SS (1 << 30) | |
311 | #define FSR_UUT (1 << 8) | |
312 | #define FSR_ASF (1 << 7) | |
313 | #define FSR_TLBLKF (1 << 6) | |
314 | #define FSR_TLBMCF (1 << 5) | |
315 | #define FSR_EF (1 << 4) | |
316 | #define FSR_PF (1 << 3) | |
317 | #define FSR_AFF (1 << 2) | |
318 | #define FSR_TF (1 << 1) | |
319 | ||
320 | #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \ | |
321 | FSR_TLBLKF) | |
322 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 323 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
324 | |
325 | #define FSYNR0_WNR (1 << 4) | |
326 | ||
327 | struct arm_smmu_smr { | |
328 | u8 idx; | |
329 | u16 mask; | |
330 | u16 id; | |
331 | }; | |
332 | ||
a9a1b0b5 | 333 | struct arm_smmu_master_cfg { |
45ae7cff WD |
334 | int num_streamids; |
335 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
336 | struct arm_smmu_smr *smrs; |
337 | }; | |
338 | ||
a9a1b0b5 WD |
339 | struct arm_smmu_master { |
340 | struct device_node *of_node; | |
a9a1b0b5 WD |
341 | struct rb_node node; |
342 | struct arm_smmu_master_cfg cfg; | |
343 | }; | |
344 | ||
45ae7cff WD |
345 | struct arm_smmu_device { |
346 | struct device *dev; | |
45ae7cff WD |
347 | |
348 | void __iomem *base; | |
349 | unsigned long size; | |
350 | unsigned long pagesize; | |
351 | ||
352 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
353 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
354 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
355 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
356 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
357 | u32 features; | |
3a5df8ff AH |
358 | |
359 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
360 | u32 options; | |
45ae7cff WD |
361 | int version; |
362 | ||
363 | u32 num_context_banks; | |
364 | u32 num_s2_context_banks; | |
365 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
366 | atomic_t irptndx; | |
367 | ||
368 | u32 num_mapping_groups; | |
369 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
370 | ||
371 | unsigned long input_size; | |
372 | unsigned long s1_output_size; | |
373 | unsigned long s2_output_size; | |
374 | ||
375 | u32 num_global_irqs; | |
376 | u32 num_context_irqs; | |
377 | unsigned int *irqs; | |
378 | ||
45ae7cff WD |
379 | struct list_head list; |
380 | struct rb_root masters; | |
381 | }; | |
382 | ||
383 | struct arm_smmu_cfg { | |
45ae7cff WD |
384 | u8 cbndx; |
385 | u8 irptndx; | |
386 | u32 cbar; | |
387 | pgd_t *pgd; | |
388 | }; | |
faea13b7 | 389 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 390 | |
ecfadb6e WD |
391 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
392 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
393 | ||
45ae7cff | 394 | struct arm_smmu_domain { |
44680eed WD |
395 | struct arm_smmu_device *smmu; |
396 | struct arm_smmu_cfg cfg; | |
c9d09e27 | 397 | spinlock_t lock; |
45ae7cff WD |
398 | }; |
399 | ||
400 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); | |
401 | static LIST_HEAD(arm_smmu_devices); | |
402 | ||
3a5df8ff AH |
403 | struct arm_smmu_option_prop { |
404 | u32 opt; | |
405 | const char *prop; | |
406 | }; | |
407 | ||
408 | static struct arm_smmu_option_prop arm_smmu_options [] = { | |
409 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, | |
410 | { 0, NULL}, | |
411 | }; | |
412 | ||
413 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
414 | { | |
415 | int i = 0; | |
416 | do { | |
417 | if (of_property_read_bool(smmu->dev->of_node, | |
418 | arm_smmu_options[i].prop)) { | |
419 | smmu->options |= arm_smmu_options[i].opt; | |
420 | dev_notice(smmu->dev, "option %s\n", | |
421 | arm_smmu_options[i].prop); | |
422 | } | |
423 | } while (arm_smmu_options[++i].opt); | |
424 | } | |
425 | ||
a9a1b0b5 WD |
426 | static struct device *dev_get_master_dev(struct device *dev) |
427 | { | |
428 | if (dev_is_pci(dev)) { | |
429 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
430 | while (!pci_is_root_bus(bus)) | |
431 | bus = bus->parent; | |
432 | return bus->bridge->parent; | |
433 | } | |
434 | ||
435 | return dev; | |
436 | } | |
437 | ||
45ae7cff WD |
438 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
439 | struct device_node *dev_node) | |
440 | { | |
441 | struct rb_node *node = smmu->masters.rb_node; | |
442 | ||
443 | while (node) { | |
444 | struct arm_smmu_master *master; | |
445 | master = container_of(node, struct arm_smmu_master, node); | |
446 | ||
447 | if (dev_node < master->of_node) | |
448 | node = node->rb_left; | |
449 | else if (dev_node > master->of_node) | |
450 | node = node->rb_right; | |
451 | else | |
452 | return master; | |
453 | } | |
454 | ||
455 | return NULL; | |
456 | } | |
457 | ||
a9a1b0b5 WD |
458 | static struct arm_smmu_master_cfg * |
459 | find_smmu_master_cfg(struct arm_smmu_device *smmu, struct device *dev) | |
460 | { | |
461 | struct arm_smmu_master *master; | |
462 | ||
463 | if (dev_is_pci(dev)) | |
464 | return dev->archdata.iommu; | |
465 | ||
466 | master = find_smmu_master(smmu, dev->of_node); | |
467 | return master ? &master->cfg : NULL; | |
468 | } | |
469 | ||
45ae7cff WD |
470 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
471 | struct arm_smmu_master *master) | |
472 | { | |
473 | struct rb_node **new, *parent; | |
474 | ||
475 | new = &smmu->masters.rb_node; | |
476 | parent = NULL; | |
477 | while (*new) { | |
478 | struct arm_smmu_master *this; | |
479 | this = container_of(*new, struct arm_smmu_master, node); | |
480 | ||
481 | parent = *new; | |
482 | if (master->of_node < this->of_node) | |
483 | new = &((*new)->rb_left); | |
484 | else if (master->of_node > this->of_node) | |
485 | new = &((*new)->rb_right); | |
486 | else | |
487 | return -EEXIST; | |
488 | } | |
489 | ||
490 | rb_link_node(&master->node, parent, new); | |
491 | rb_insert_color(&master->node, &smmu->masters); | |
492 | return 0; | |
493 | } | |
494 | ||
495 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
496 | struct device *dev, | |
497 | struct of_phandle_args *masterspec) | |
498 | { | |
499 | int i; | |
500 | struct arm_smmu_master *master; | |
501 | ||
502 | master = find_smmu_master(smmu, masterspec->np); | |
503 | if (master) { | |
504 | dev_err(dev, | |
505 | "rejecting multiple registrations for master device %s\n", | |
506 | masterspec->np->name); | |
507 | return -EBUSY; | |
508 | } | |
509 | ||
510 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
511 | dev_err(dev, | |
512 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
513 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
514 | return -ENOSPC; | |
515 | } | |
516 | ||
517 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
518 | if (!master) | |
519 | return -ENOMEM; | |
520 | ||
a9a1b0b5 WD |
521 | master->of_node = masterspec->np; |
522 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 523 | |
a9a1b0b5 WD |
524 | for (i = 0; i < master->cfg.num_streamids; ++i) |
525 | master->cfg.streamids[i] = masterspec->args[i]; | |
45ae7cff WD |
526 | |
527 | return insert_smmu_master(smmu, master); | |
528 | } | |
529 | ||
44680eed | 530 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 531 | { |
44680eed | 532 | struct arm_smmu_device *smmu; |
a9a1b0b5 WD |
533 | struct arm_smmu_master *master = NULL; |
534 | struct device_node *dev_node = dev_get_master_dev(dev)->of_node; | |
535 | ||
536 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 537 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
538 | master = find_smmu_master(smmu, dev_node); |
539 | if (master) | |
540 | break; | |
541 | } | |
542 | spin_unlock(&arm_smmu_devices_lock); | |
44680eed | 543 | |
a9a1b0b5 WD |
544 | return master ? smmu : NULL; |
545 | } | |
546 | ||
45ae7cff WD |
547 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) |
548 | { | |
549 | int idx; | |
550 | ||
551 | do { | |
552 | idx = find_next_zero_bit(map, end, start); | |
553 | if (idx == end) | |
554 | return -ENOSPC; | |
555 | } while (test_and_set_bit(idx, map)); | |
556 | ||
557 | return idx; | |
558 | } | |
559 | ||
560 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
561 | { | |
562 | clear_bit(idx, map); | |
563 | } | |
564 | ||
565 | /* Wait for any pending TLB invalidations to complete */ | |
566 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) | |
567 | { | |
568 | int count = 0; | |
569 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
570 | ||
571 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
572 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
573 | & sTLBGSTATUS_GSACTIVE) { | |
574 | cpu_relax(); | |
575 | if (++count == TLB_LOOP_TIMEOUT) { | |
576 | dev_err_ratelimited(smmu->dev, | |
577 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
578 | return; | |
579 | } | |
580 | udelay(1); | |
581 | } | |
582 | } | |
583 | ||
44680eed | 584 | static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain) |
1463fe44 | 585 | { |
44680eed WD |
586 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
587 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 WD |
588 | void __iomem *base = ARM_SMMU_GR0(smmu); |
589 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
590 | ||
591 | if (stage1) { | |
592 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
593 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
594 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
595 | } else { |
596 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
597 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
598 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
599 | } |
600 | ||
601 | arm_smmu_tlb_sync(smmu); | |
602 | } | |
603 | ||
45ae7cff WD |
604 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
605 | { | |
606 | int flags, ret; | |
607 | u32 fsr, far, fsynr, resume; | |
608 | unsigned long iova; | |
609 | struct iommu_domain *domain = dev; | |
610 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
611 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
612 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
613 | void __iomem *cb_base; |
614 | ||
44680eed | 615 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
616 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
617 | ||
618 | if (!(fsr & FSR_FAULT)) | |
619 | return IRQ_NONE; | |
620 | ||
621 | if (fsr & FSR_IGN) | |
622 | dev_err_ratelimited(smmu->dev, | |
623 | "Unexpected context fault (fsr 0x%u)\n", | |
624 | fsr); | |
625 | ||
626 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
627 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
628 | ||
629 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
630 | iova = far; | |
631 | #ifdef CONFIG_64BIT | |
632 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
633 | iova |= ((unsigned long)far << 32); | |
634 | #endif | |
635 | ||
636 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
637 | ret = IRQ_HANDLED; | |
638 | resume = RESUME_RETRY; | |
639 | } else { | |
2ef0f031 AH |
640 | dev_err_ratelimited(smmu->dev, |
641 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 642 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
643 | ret = IRQ_NONE; |
644 | resume = RESUME_TERMINATE; | |
645 | } | |
646 | ||
647 | /* Clear the faulting FSR */ | |
648 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
649 | ||
650 | /* Retry or terminate any stalled transactions */ | |
651 | if (fsr & FSR_SS) | |
652 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
657 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
658 | { | |
659 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
660 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 661 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
662 | |
663 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
664 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
665 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
666 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
667 | ||
3a5df8ff AH |
668 | if (!gfsr) |
669 | return IRQ_NONE; | |
670 | ||
45ae7cff WD |
671 | dev_err_ratelimited(smmu->dev, |
672 | "Unexpected global fault, this could be serious\n"); | |
673 | dev_err_ratelimited(smmu->dev, | |
674 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
675 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
676 | ||
677 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 678 | return IRQ_HANDLED; |
45ae7cff WD |
679 | } |
680 | ||
6dd35f45 WD |
681 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
682 | size_t size) | |
683 | { | |
684 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
685 | ||
686 | ||
687 | /* Ensure new page tables are visible to the hardware walker */ | |
688 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
3aa80ea4 | 689 | dsb(ishst); |
6dd35f45 WD |
690 | } else { |
691 | /* | |
692 | * If the SMMU can't walk tables in the CPU caches, treat them | |
693 | * like non-coherent DMA since we need to flush the new entries | |
694 | * all the way out to memory. There's no possibility of | |
695 | * recursion here as the SMMU table walker will not be wired | |
696 | * through another SMMU. | |
697 | */ | |
698 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
699 | DMA_TO_DEVICE); | |
700 | } | |
701 | } | |
702 | ||
45ae7cff WD |
703 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
704 | { | |
705 | u32 reg; | |
706 | bool stage1; | |
44680eed WD |
707 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
708 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
709 | void __iomem *cb_base, *gr0_base, *gr1_base; |
710 | ||
711 | gr0_base = ARM_SMMU_GR0(smmu); | |
712 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
713 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
714 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
715 | |
716 | /* CBAR */ | |
44680eed | 717 | reg = cfg->cbar; |
45ae7cff | 718 | if (smmu->version == 1) |
44680eed | 719 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 720 | |
57ca90f6 WD |
721 | /* |
722 | * Use the weakest shareability/memory types, so they are | |
723 | * overridden by the ttbcr/pte. | |
724 | */ | |
725 | if (stage1) { | |
726 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
727 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
728 | } else { | |
44680eed | 729 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 730 | } |
44680eed | 731 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff WD |
732 | |
733 | if (smmu->version > 1) { | |
734 | /* CBA2R */ | |
735 | #ifdef CONFIG_64BIT | |
736 | reg = CBA2R_RW64_64BIT; | |
737 | #else | |
738 | reg = CBA2R_RW64_32BIT; | |
739 | #endif | |
740 | writel_relaxed(reg, | |
44680eed | 741 | gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
742 | |
743 | /* TTBCR2 */ | |
744 | switch (smmu->input_size) { | |
745 | case 32: | |
746 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); | |
747 | break; | |
748 | case 36: | |
749 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); | |
750 | break; | |
751 | case 39: | |
752 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); | |
753 | break; | |
754 | case 42: | |
755 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); | |
756 | break; | |
757 | case 44: | |
758 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); | |
759 | break; | |
760 | case 48: | |
761 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); | |
762 | break; | |
763 | } | |
764 | ||
765 | switch (smmu->s1_output_size) { | |
766 | case 32: | |
767 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); | |
768 | break; | |
769 | case 36: | |
770 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); | |
771 | break; | |
772 | case 39: | |
773 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); | |
774 | break; | |
775 | case 42: | |
776 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); | |
777 | break; | |
778 | case 44: | |
779 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); | |
780 | break; | |
781 | case 48: | |
782 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); | |
783 | break; | |
784 | } | |
785 | ||
786 | if (stage1) | |
787 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); | |
788 | } | |
789 | ||
790 | /* TTBR0 */ | |
44680eed | 791 | arm_smmu_flush_pgtable(smmu, cfg->pgd, |
6dd35f45 | 792 | PTRS_PER_PGD * sizeof(pgd_t)); |
44680eed | 793 | reg = __pa(cfg->pgd); |
45ae7cff | 794 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
44680eed | 795 | reg = (phys_addr_t)__pa(cfg->pgd) >> 32; |
1463fe44 | 796 | if (stage1) |
44680eed | 797 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
45ae7cff | 798 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff WD |
799 | |
800 | /* | |
801 | * TTBCR | |
802 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. | |
803 | */ | |
804 | if (smmu->version > 1) { | |
805 | if (PAGE_SIZE == SZ_4K) | |
806 | reg = TTBCR_TG0_4K; | |
807 | else | |
808 | reg = TTBCR_TG0_64K; | |
809 | ||
810 | if (!stage1) { | |
a65217a4 WD |
811 | reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; |
812 | ||
45ae7cff WD |
813 | switch (smmu->s2_output_size) { |
814 | case 32: | |
815 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); | |
816 | break; | |
817 | case 36: | |
818 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); | |
819 | break; | |
820 | case 40: | |
821 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); | |
822 | break; | |
823 | case 42: | |
824 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); | |
825 | break; | |
826 | case 44: | |
827 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); | |
828 | break; | |
829 | case 48: | |
830 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); | |
831 | break; | |
832 | } | |
833 | } else { | |
a65217a4 | 834 | reg |= (64 - smmu->input_size) << TTBCR_T0SZ_SHIFT; |
45ae7cff WD |
835 | } |
836 | } else { | |
837 | reg = 0; | |
838 | } | |
839 | ||
840 | reg |= TTBCR_EAE | | |
841 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | | |
842 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | | |
843 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | | |
844 | (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); | |
845 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
846 | ||
847 | /* MAIR0 (stage-1 only) */ | |
848 | if (stage1) { | |
849 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | | |
850 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | | |
851 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); | |
852 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); | |
853 | } | |
854 | ||
45ae7cff WD |
855 | /* SCTLR */ |
856 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
857 | if (stage1) | |
858 | reg |= SCTLR_S1_ASIDPNE; | |
859 | #ifdef __BIG_ENDIAN | |
860 | reg |= SCTLR_E; | |
861 | #endif | |
25724841 | 862 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
863 | } |
864 | ||
865 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 866 | struct arm_smmu_device *smmu) |
45ae7cff WD |
867 | { |
868 | int irq, ret, start; | |
869 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed | 870 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 871 | |
45ae7cff WD |
872 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
873 | /* | |
874 | * We will likely want to change this if/when KVM gets | |
875 | * involved. | |
876 | */ | |
44680eed | 877 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff WD |
878 | start = smmu->num_s2_context_banks; |
879 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { | |
44680eed | 880 | cfg->cbar = CBAR_TYPE_S2_TRANS; |
45ae7cff WD |
881 | start = 0; |
882 | } else { | |
44680eed | 883 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff WD |
884 | start = smmu->num_s2_context_banks; |
885 | } | |
886 | ||
887 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
888 | smmu->num_context_banks); | |
889 | if (IS_ERR_VALUE(ret)) | |
ecfadb6e | 890 | return ret; |
45ae7cff | 891 | |
44680eed | 892 | cfg->cbndx = ret; |
45ae7cff | 893 | if (smmu->version == 1) { |
44680eed WD |
894 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
895 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 896 | } else { |
44680eed | 897 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
898 | } |
899 | ||
44680eed | 900 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
901 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
902 | "arm-smmu-context-fault", domain); | |
903 | if (IS_ERR_VALUE(ret)) { | |
904 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
905 | cfg->irptndx, irq); |
906 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
907 | goto out_free_context; |
908 | } | |
909 | ||
44680eed | 910 | smmu_domain->smmu = smmu; |
45ae7cff | 911 | arm_smmu_init_context_bank(smmu_domain); |
a9a1b0b5 | 912 | return 0; |
45ae7cff WD |
913 | |
914 | out_free_context: | |
44680eed | 915 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
916 | return ret; |
917 | } | |
918 | ||
919 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
920 | { | |
921 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
922 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
923 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 924 | void __iomem *cb_base; |
45ae7cff WD |
925 | int irq; |
926 | ||
927 | if (!smmu) | |
928 | return; | |
929 | ||
1463fe44 | 930 | /* Disable the context bank and nuke the TLB before freeing it. */ |
44680eed | 931 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 932 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
44680eed | 933 | arm_smmu_tlb_inv_context(smmu_domain); |
1463fe44 | 934 | |
44680eed WD |
935 | if (cfg->irptndx != INVALID_IRPTNDX) { |
936 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
937 | free_irq(irq, domain); |
938 | } | |
939 | ||
44680eed | 940 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
941 | } |
942 | ||
943 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
944 | { | |
945 | struct arm_smmu_domain *smmu_domain; | |
946 | pgd_t *pgd; | |
947 | ||
948 | /* | |
949 | * Allocate the domain and initialise some of its data structures. | |
950 | * We can't really do anything meaningful until we've added a | |
951 | * master. | |
952 | */ | |
953 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
954 | if (!smmu_domain) | |
955 | return -ENOMEM; | |
956 | ||
957 | pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); | |
958 | if (!pgd) | |
959 | goto out_free_domain; | |
44680eed | 960 | smmu_domain->cfg.pgd = pgd; |
45ae7cff | 961 | |
c9d09e27 | 962 | spin_lock_init(&smmu_domain->lock); |
45ae7cff WD |
963 | domain->priv = smmu_domain; |
964 | return 0; | |
965 | ||
966 | out_free_domain: | |
967 | kfree(smmu_domain); | |
968 | return -ENOMEM; | |
969 | } | |
970 | ||
971 | static void arm_smmu_free_ptes(pmd_t *pmd) | |
972 | { | |
973 | pgtable_t table = pmd_pgtable(*pmd); | |
974 | pgtable_page_dtor(table); | |
975 | __free_page(table); | |
976 | } | |
977 | ||
978 | static void arm_smmu_free_pmds(pud_t *pud) | |
979 | { | |
980 | int i; | |
981 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); | |
982 | ||
983 | pmd = pmd_base; | |
984 | for (i = 0; i < PTRS_PER_PMD; ++i) { | |
985 | if (pmd_none(*pmd)) | |
986 | continue; | |
987 | ||
988 | arm_smmu_free_ptes(pmd); | |
989 | pmd++; | |
990 | } | |
991 | ||
992 | pmd_free(NULL, pmd_base); | |
993 | } | |
994 | ||
995 | static void arm_smmu_free_puds(pgd_t *pgd) | |
996 | { | |
997 | int i; | |
998 | pud_t *pud, *pud_base = pud_offset(pgd, 0); | |
999 | ||
1000 | pud = pud_base; | |
1001 | for (i = 0; i < PTRS_PER_PUD; ++i) { | |
1002 | if (pud_none(*pud)) | |
1003 | continue; | |
1004 | ||
1005 | arm_smmu_free_pmds(pud); | |
1006 | pud++; | |
1007 | } | |
1008 | ||
1009 | pud_free(NULL, pud_base); | |
1010 | } | |
1011 | ||
1012 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) | |
1013 | { | |
1014 | int i; | |
44680eed WD |
1015 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
1016 | pgd_t *pgd, *pgd_base = cfg->pgd; | |
45ae7cff WD |
1017 | |
1018 | /* | |
1019 | * Recursively free the page tables for this domain. We don't | |
34fb4b37 WD |
1020 | * care about speculative TLB filling because the tables should |
1021 | * not be active in any context bank at this point (SCTLR.M is 0). | |
45ae7cff WD |
1022 | */ |
1023 | pgd = pgd_base; | |
1024 | for (i = 0; i < PTRS_PER_PGD; ++i) { | |
1025 | if (pgd_none(*pgd)) | |
1026 | continue; | |
1027 | arm_smmu_free_puds(pgd); | |
1028 | pgd++; | |
1029 | } | |
1030 | ||
1031 | kfree(pgd_base); | |
1032 | } | |
1033 | ||
1034 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
1035 | { | |
1036 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
1037 | |
1038 | /* | |
1039 | * Free the domain resources. We assume that all devices have | |
1040 | * already been detached. | |
1041 | */ | |
45ae7cff WD |
1042 | arm_smmu_destroy_domain_context(domain); |
1043 | arm_smmu_free_pgtables(smmu_domain); | |
1044 | kfree(smmu_domain); | |
1045 | } | |
1046 | ||
1047 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1048 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1049 | { |
1050 | int i; | |
1051 | struct arm_smmu_smr *smrs; | |
1052 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1053 | ||
1054 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1055 | return 0; | |
1056 | ||
a9a1b0b5 | 1057 | if (cfg->smrs) |
45ae7cff WD |
1058 | return -EEXIST; |
1059 | ||
a9a1b0b5 | 1060 | smrs = kmalloc(sizeof(*smrs) * cfg->num_streamids, GFP_KERNEL); |
45ae7cff | 1061 | if (!smrs) { |
a9a1b0b5 WD |
1062 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1063 | cfg->num_streamids); | |
45ae7cff WD |
1064 | return -ENOMEM; |
1065 | } | |
1066 | ||
44680eed | 1067 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1068 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1069 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1070 | smmu->num_mapping_groups); | |
1071 | if (IS_ERR_VALUE(idx)) { | |
1072 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1073 | goto err_free_smrs; | |
1074 | } | |
1075 | ||
1076 | smrs[i] = (struct arm_smmu_smr) { | |
1077 | .idx = idx, | |
1078 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1079 | .id = cfg->streamids[i], |
45ae7cff WD |
1080 | }; |
1081 | } | |
1082 | ||
1083 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1084 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1085 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1086 | smrs[i].mask << SMR_MASK_SHIFT; | |
1087 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1088 | } | |
1089 | ||
a9a1b0b5 | 1090 | cfg->smrs = smrs; |
45ae7cff WD |
1091 | return 0; |
1092 | ||
1093 | err_free_smrs: | |
1094 | while (--i >= 0) | |
1095 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1096 | kfree(smrs); | |
1097 | return -ENOSPC; | |
1098 | } | |
1099 | ||
1100 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1101 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1102 | { |
1103 | int i; | |
1104 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1105 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff WD |
1106 | |
1107 | /* Invalidate the SMRs before freeing back to the allocator */ | |
a9a1b0b5 | 1108 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1109 | u8 idx = smrs[i].idx; |
1110 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); | |
1111 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1112 | } | |
1113 | ||
a9a1b0b5 | 1114 | cfg->smrs = NULL; |
45ae7cff WD |
1115 | kfree(smrs); |
1116 | } | |
1117 | ||
1118 | static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1119 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1120 | { |
1121 | int i; | |
1122 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1123 | ||
a9a1b0b5 WD |
1124 | for (i = 0; i < cfg->num_streamids; ++i) { |
1125 | u16 sid = cfg->streamids[i]; | |
45ae7cff WD |
1126 | writel_relaxed(S2CR_TYPE_BYPASS, |
1127 | gr0_base + ARM_SMMU_GR0_S2CR(sid)); | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1132 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1133 | { |
1134 | int i, ret; | |
44680eed | 1135 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1136 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1137 | ||
a9a1b0b5 | 1138 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff WD |
1139 | if (ret) |
1140 | return ret; | |
1141 | ||
a9a1b0b5 | 1142 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1143 | u32 idx, s2cr; |
a9a1b0b5 | 1144 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1145 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1146 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1147 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1148 | } | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1154 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1155 | { |
44680eed | 1156 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1157 | |
1158 | /* | |
1159 | * We *must* clear the S2CR first, because freeing the SMR means | |
1160 | * that it can be re-allocated immediately. | |
1161 | */ | |
a9a1b0b5 WD |
1162 | arm_smmu_bypass_stream_mapping(smmu, cfg); |
1163 | arm_smmu_master_free_smrs(smmu, cfg); | |
45ae7cff WD |
1164 | } |
1165 | ||
1166 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1167 | { | |
1168 | int ret = -EINVAL; | |
1169 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed | 1170 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 1171 | struct arm_smmu_master_cfg *cfg; |
972157ca | 1172 | unsigned long flags; |
45ae7cff | 1173 | |
44680eed WD |
1174 | smmu = dev_get_master_dev(dev)->archdata.iommu; |
1175 | if (!smmu) { | |
45ae7cff WD |
1176 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1177 | return -ENXIO; | |
1178 | } | |
1179 | ||
1180 | /* | |
44680eed WD |
1181 | * Sanity check the domain. We don't support domains across |
1182 | * different SMMUs. | |
45ae7cff | 1183 | */ |
972157ca | 1184 | spin_lock_irqsave(&smmu_domain->lock, flags); |
44680eed | 1185 | if (!smmu_domain->smmu) { |
45ae7cff | 1186 | /* Now that we have a master, we can finalise the domain */ |
44680eed | 1187 | ret = arm_smmu_init_domain_context(domain, smmu); |
45ae7cff WD |
1188 | if (IS_ERR_VALUE(ret)) |
1189 | goto err_unlock; | |
44680eed | 1190 | } else if (smmu_domain->smmu != smmu) { |
45ae7cff WD |
1191 | dev_err(dev, |
1192 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
44680eed WD |
1193 | dev_name(smmu_domain->smmu->dev), |
1194 | dev_name(smmu->dev)); | |
45ae7cff WD |
1195 | goto err_unlock; |
1196 | } | |
972157ca | 1197 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff WD |
1198 | |
1199 | /* Looks ok, so add the device to the domain */ | |
44680eed | 1200 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 | 1201 | if (!cfg) |
45ae7cff WD |
1202 | return -ENODEV; |
1203 | ||
a9a1b0b5 | 1204 | return arm_smmu_domain_add_master(smmu_domain, cfg); |
45ae7cff WD |
1205 | |
1206 | err_unlock: | |
972157ca | 1207 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff WD |
1208 | return ret; |
1209 | } | |
1210 | ||
1211 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1212 | { | |
1213 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1214 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1215 | |
44680eed | 1216 | cfg = find_smmu_master_cfg(smmu_domain->smmu, dev); |
a9a1b0b5 WD |
1217 | if (cfg) |
1218 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1219 | } |
1220 | ||
45ae7cff WD |
1221 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
1222 | unsigned long end) | |
1223 | { | |
1224 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && | |
1225 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); | |
1226 | } | |
1227 | ||
1228 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, | |
1229 | unsigned long addr, unsigned long end, | |
b410aed9 | 1230 | unsigned long pfn, int prot, int stage) |
45ae7cff WD |
1231 | { |
1232 | pte_t *pte, *start; | |
cf2d45b1 | 1233 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; |
45ae7cff WD |
1234 | |
1235 | if (pmd_none(*pmd)) { | |
1236 | /* Allocate a new set of tables */ | |
c9d09e27 | 1237 | pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO); |
45ae7cff WD |
1238 | if (!table) |
1239 | return -ENOMEM; | |
1240 | ||
6dd35f45 | 1241 | arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE); |
01058e70 KS |
1242 | if (!pgtable_page_ctor(table)) { |
1243 | __free_page(table); | |
1244 | return -ENOMEM; | |
1245 | } | |
45ae7cff WD |
1246 | pmd_populate(NULL, pmd, table); |
1247 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); | |
1248 | } | |
1249 | ||
1250 | if (stage == 1) { | |
1463fe44 | 1251 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
b410aed9 | 1252 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
45ae7cff WD |
1253 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
1254 | ||
b410aed9 | 1255 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1256 | pteval |= (MAIR_ATTR_IDX_CACHE << |
1257 | ARM_SMMU_PTE_ATTRINDX_SHIFT); | |
1258 | } else { | |
1259 | pteval |= ARM_SMMU_PTE_HAP_FAULT; | |
b410aed9 | 1260 | if (prot & IOMMU_READ) |
45ae7cff | 1261 | pteval |= ARM_SMMU_PTE_HAP_READ; |
b410aed9 | 1262 | if (prot & IOMMU_WRITE) |
45ae7cff | 1263 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
b410aed9 | 1264 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1265 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
1266 | else | |
1267 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; | |
1268 | } | |
1269 | ||
1270 | /* If no access, create a faulting entry to avoid TLB fills */ | |
b410aed9 | 1271 | if (prot & IOMMU_EXEC) |
cf2d45b1 | 1272 | pteval &= ~ARM_SMMU_PTE_XN; |
b410aed9 | 1273 | else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) |
45ae7cff WD |
1274 | pteval &= ~ARM_SMMU_PTE_PAGE; |
1275 | ||
1276 | pteval |= ARM_SMMU_PTE_SH_IS; | |
1277 | start = pmd_page_vaddr(*pmd) + pte_index(addr); | |
1278 | pte = start; | |
1279 | ||
1280 | /* | |
1281 | * Install the page table entries. This is fairly complicated | |
1282 | * since we attempt to make use of the contiguous hint in the | |
1283 | * ptes where possible. The contiguous hint indicates a series | |
1284 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically | |
1285 | * contiguous region with the following constraints: | |
1286 | * | |
1287 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE | |
1288 | * - Each pte in the region has the contiguous hint bit set | |
1289 | * | |
1290 | * This complicates unmapping (also handled by this code, when | |
1291 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is | |
1292 | * possible, yet highly unlikely, that a client may unmap only | |
1293 | * part of a contiguous range. This requires clearing of the | |
1294 | * contiguous hint bits in the range before installing the new | |
1295 | * faulting entries. | |
1296 | * | |
1297 | * Note that re-mapping an address range without first unmapping | |
1298 | * it is not supported, so TLB invalidation is not required here | |
1299 | * and is instead performed at unmap and domain-init time. | |
1300 | */ | |
1301 | do { | |
1302 | int i = 1; | |
1303 | pteval &= ~ARM_SMMU_PTE_CONT; | |
1304 | ||
1305 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { | |
1306 | i = ARM_SMMU_PTE_CONT_ENTRIES; | |
1307 | pteval |= ARM_SMMU_PTE_CONT; | |
1308 | } else if (pte_val(*pte) & | |
1309 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { | |
1310 | int j; | |
1311 | pte_t *cont_start; | |
1312 | unsigned long idx = pte_index(addr); | |
1313 | ||
1314 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); | |
1315 | cont_start = pmd_page_vaddr(*pmd) + idx; | |
1316 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) | |
1317 | pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT; | |
1318 | ||
1319 | arm_smmu_flush_pgtable(smmu, cont_start, | |
1320 | sizeof(*pte) * | |
1321 | ARM_SMMU_PTE_CONT_ENTRIES); | |
1322 | } | |
1323 | ||
1324 | do { | |
1325 | *pte = pfn_pte(pfn, __pgprot(pteval)); | |
1326 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); | |
1327 | } while (addr != end); | |
1328 | ||
1329 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, | |
1334 | unsigned long addr, unsigned long end, | |
b410aed9 | 1335 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1336 | { |
1337 | int ret; | |
1338 | pmd_t *pmd; | |
1339 | unsigned long next, pfn = __phys_to_pfn(phys); | |
1340 | ||
1341 | #ifndef __PAGETABLE_PMD_FOLDED | |
1342 | if (pud_none(*pud)) { | |
c9d09e27 | 1343 | pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1344 | if (!pmd) |
1345 | return -ENOMEM; | |
97a64420 | 1346 | |
6dd35f45 | 1347 | arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE); |
97a64420 YZ |
1348 | pud_populate(NULL, pud, pmd); |
1349 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); | |
1350 | ||
1351 | pmd += pmd_index(addr); | |
45ae7cff WD |
1352 | } else |
1353 | #endif | |
1354 | pmd = pmd_offset(pud, addr); | |
1355 | ||
1356 | do { | |
1357 | next = pmd_addr_end(addr, end); | |
aca1bc45 | 1358 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn, |
b410aed9 | 1359 | prot, stage); |
45ae7cff WD |
1360 | phys += next - addr; |
1361 | } while (pmd++, addr = next, addr < end); | |
1362 | ||
1363 | return ret; | |
1364 | } | |
1365 | ||
1366 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, | |
1367 | unsigned long addr, unsigned long end, | |
b410aed9 | 1368 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1369 | { |
1370 | int ret = 0; | |
1371 | pud_t *pud; | |
1372 | unsigned long next; | |
1373 | ||
1374 | #ifndef __PAGETABLE_PUD_FOLDED | |
1375 | if (pgd_none(*pgd)) { | |
c9d09e27 | 1376 | pud = (pud_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1377 | if (!pud) |
1378 | return -ENOMEM; | |
97a64420 | 1379 | |
6dd35f45 | 1380 | arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE); |
97a64420 YZ |
1381 | pgd_populate(NULL, pgd, pud); |
1382 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); | |
1383 | ||
1384 | pud += pud_index(addr); | |
45ae7cff WD |
1385 | } else |
1386 | #endif | |
1387 | pud = pud_offset(pgd, addr); | |
1388 | ||
1389 | do { | |
1390 | next = pud_addr_end(addr, end); | |
1391 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, | |
b410aed9 | 1392 | prot, stage); |
45ae7cff WD |
1393 | phys += next - addr; |
1394 | } while (pud++, addr = next, addr < end); | |
1395 | ||
1396 | return ret; | |
1397 | } | |
1398 | ||
1399 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, | |
1400 | unsigned long iova, phys_addr_t paddr, | |
b410aed9 | 1401 | size_t size, int prot) |
45ae7cff WD |
1402 | { |
1403 | int ret, stage; | |
1404 | unsigned long end; | |
1405 | phys_addr_t input_mask, output_mask; | |
44680eed WD |
1406 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1407 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1408 | pgd_t *pgd = cfg->pgd; | |
b410aed9 | 1409 | unsigned long flags; |
45ae7cff | 1410 | |
44680eed | 1411 | if (cfg->cbar == CBAR_TYPE_S2_TRANS) { |
45ae7cff WD |
1412 | stage = 2; |
1413 | output_mask = (1ULL << smmu->s2_output_size) - 1; | |
1414 | } else { | |
1415 | stage = 1; | |
1416 | output_mask = (1ULL << smmu->s1_output_size) - 1; | |
1417 | } | |
1418 | ||
1419 | if (!pgd) | |
1420 | return -EINVAL; | |
1421 | ||
1422 | if (size & ~PAGE_MASK) | |
1423 | return -EINVAL; | |
1424 | ||
1425 | input_mask = (1ULL << smmu->input_size) - 1; | |
1426 | if ((phys_addr_t)iova & ~input_mask) | |
1427 | return -ERANGE; | |
1428 | ||
1429 | if (paddr & ~output_mask) | |
1430 | return -ERANGE; | |
1431 | ||
b410aed9 | 1432 | spin_lock_irqsave(&smmu_domain->lock, flags); |
45ae7cff WD |
1433 | pgd += pgd_index(iova); |
1434 | end = iova + size; | |
1435 | do { | |
1436 | unsigned long next = pgd_addr_end(iova, end); | |
1437 | ||
1438 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, | |
b410aed9 | 1439 | prot, stage); |
45ae7cff WD |
1440 | if (ret) |
1441 | goto out_unlock; | |
1442 | ||
1443 | paddr += next - iova; | |
1444 | iova = next; | |
1445 | } while (pgd++, iova != end); | |
1446 | ||
1447 | out_unlock: | |
b410aed9 | 1448 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff | 1449 | |
45ae7cff WD |
1450 | return ret; |
1451 | } | |
1452 | ||
1453 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
b410aed9 | 1454 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff WD |
1455 | { |
1456 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff | 1457 | |
5552ecdb | 1458 | if (!smmu_domain) |
45ae7cff WD |
1459 | return -ENODEV; |
1460 | ||
b410aed9 | 1461 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot); |
45ae7cff WD |
1462 | } |
1463 | ||
1464 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1465 | size_t size) | |
1466 | { | |
1467 | int ret; | |
1468 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff WD |
1469 | |
1470 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); | |
44680eed | 1471 | arm_smmu_tlb_inv_context(smmu_domain); |
16c50dcf | 1472 | return ret ? 0 : size; |
45ae7cff WD |
1473 | } |
1474 | ||
1475 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1476 | dma_addr_t iova) | |
1477 | { | |
a44a9791 WD |
1478 | pgd_t *pgdp, pgd; |
1479 | pud_t pud; | |
1480 | pmd_t pmd; | |
1481 | pte_t pte; | |
45ae7cff | 1482 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1483 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 1484 | |
44680eed | 1485 | pgdp = cfg->pgd; |
a44a9791 WD |
1486 | if (!pgdp) |
1487 | return 0; | |
45ae7cff | 1488 | |
a44a9791 WD |
1489 | pgd = *(pgdp + pgd_index(iova)); |
1490 | if (pgd_none(pgd)) | |
1491 | return 0; | |
45ae7cff | 1492 | |
a44a9791 WD |
1493 | pud = *pud_offset(&pgd, iova); |
1494 | if (pud_none(pud)) | |
1495 | return 0; | |
45ae7cff | 1496 | |
a44a9791 WD |
1497 | pmd = *pmd_offset(&pud, iova); |
1498 | if (pmd_none(pmd)) | |
1499 | return 0; | |
45ae7cff | 1500 | |
a44a9791 | 1501 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
45ae7cff | 1502 | if (pte_none(pte)) |
a44a9791 | 1503 | return 0; |
45ae7cff | 1504 | |
a44a9791 | 1505 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
45ae7cff WD |
1506 | } |
1507 | ||
1508 | static int arm_smmu_domain_has_cap(struct iommu_domain *domain, | |
1509 | unsigned long cap) | |
1510 | { | |
45ae7cff | 1511 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1512 | u32 features = smmu_domain->smmu->features; |
d0948945 WD |
1513 | |
1514 | switch (cap) { | |
1515 | case IOMMU_CAP_CACHE_COHERENCY: | |
1516 | return features & ARM_SMMU_FEAT_COHERENT_WALK; | |
1517 | case IOMMU_CAP_INTR_REMAP: | |
1518 | return 1; /* MSIs are just memory writes */ | |
1519 | default: | |
1520 | return 0; | |
1521 | } | |
45ae7cff WD |
1522 | } |
1523 | ||
a9a1b0b5 WD |
1524 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1525 | { | |
1526 | *((u16 *)data) = alias; | |
1527 | return 0; /* Continue walking */ | |
1528 | } | |
1529 | ||
45ae7cff WD |
1530 | static int arm_smmu_add_device(struct device *dev) |
1531 | { | |
a9a1b0b5 | 1532 | struct arm_smmu_device *smmu; |
5fc63a7c AM |
1533 | struct iommu_group *group; |
1534 | int ret; | |
1535 | ||
1536 | if (dev->archdata.iommu) { | |
1537 | dev_warn(dev, "IOMMU driver already assigned to device\n"); | |
1538 | return -EINVAL; | |
1539 | } | |
45ae7cff | 1540 | |
44680eed | 1541 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1542 | if (!smmu) |
45ae7cff WD |
1543 | return -ENODEV; |
1544 | ||
5fc63a7c AM |
1545 | group = iommu_group_alloc(); |
1546 | if (IS_ERR(group)) { | |
1547 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1548 | return PTR_ERR(group); | |
1549 | } | |
1550 | ||
a9a1b0b5 WD |
1551 | if (dev_is_pci(dev)) { |
1552 | struct arm_smmu_master_cfg *cfg; | |
1553 | struct pci_dev *pdev = to_pci_dev(dev); | |
1554 | ||
1555 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1556 | if (!cfg) { | |
1557 | ret = -ENOMEM; | |
1558 | goto out_put_group; | |
1559 | } | |
1560 | ||
1561 | cfg->num_streamids = 1; | |
1562 | /* | |
1563 | * Assume Stream ID == Requester ID for now. | |
1564 | * We need a way to describe the ID mappings in FDT. | |
1565 | */ | |
1566 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1567 | &cfg->streamids[0]); | |
1568 | dev->archdata.iommu = cfg; | |
1569 | } else { | |
1570 | dev->archdata.iommu = smmu; | |
1571 | } | |
1572 | ||
5fc63a7c | 1573 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1574 | |
a9a1b0b5 WD |
1575 | out_put_group: |
1576 | iommu_group_put(group); | |
5fc63a7c | 1577 | return ret; |
45ae7cff WD |
1578 | } |
1579 | ||
1580 | static void arm_smmu_remove_device(struct device *dev) | |
1581 | { | |
a9a1b0b5 WD |
1582 | if (dev_is_pci(dev)) |
1583 | kfree(dev->archdata.iommu); | |
1584 | ||
45ae7cff | 1585 | dev->archdata.iommu = NULL; |
5fc63a7c | 1586 | iommu_group_remove_device(dev); |
45ae7cff WD |
1587 | } |
1588 | ||
1589 | static struct iommu_ops arm_smmu_ops = { | |
1590 | .domain_init = arm_smmu_domain_init, | |
1591 | .domain_destroy = arm_smmu_domain_destroy, | |
1592 | .attach_dev = arm_smmu_attach_dev, | |
1593 | .detach_dev = arm_smmu_detach_dev, | |
1594 | .map = arm_smmu_map, | |
1595 | .unmap = arm_smmu_unmap, | |
1596 | .iova_to_phys = arm_smmu_iova_to_phys, | |
1597 | .domain_has_cap = arm_smmu_domain_has_cap, | |
1598 | .add_device = arm_smmu_add_device, | |
1599 | .remove_device = arm_smmu_remove_device, | |
1600 | .pgsize_bitmap = (SECTION_SIZE | | |
1601 | ARM_SMMU_PTE_CONT_SIZE | | |
1602 | PAGE_SIZE), | |
1603 | }; | |
1604 | ||
1605 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1606 | { | |
1607 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1608 | void __iomem *cb_base; |
45ae7cff | 1609 | int i = 0; |
659db6f6 AH |
1610 | u32 reg; |
1611 | ||
3a5df8ff AH |
1612 | /* clear global FSR */ |
1613 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1614 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1615 | |
1616 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1617 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
1618 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); | |
1619 | writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
1620 | } | |
1621 | ||
659db6f6 AH |
1622 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1623 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1624 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1625 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1626 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1627 | } | |
1463fe44 | 1628 | |
45ae7cff WD |
1629 | /* Invalidate the TLB, just in case */ |
1630 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); | |
1631 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); | |
1632 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1633 | ||
3a5df8ff | 1634 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1635 | |
45ae7cff | 1636 | /* Enable fault reporting */ |
659db6f6 | 1637 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1638 | |
1639 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1640 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1641 | |
1642 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1643 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1644 | |
1645 | /* Disable forced broadcasting */ | |
659db6f6 | 1646 | reg &= ~sCR0_FB; |
45ae7cff WD |
1647 | |
1648 | /* Don't upgrade barriers */ | |
659db6f6 | 1649 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1650 | |
1651 | /* Push the button */ | |
1652 | arm_smmu_tlb_sync(smmu); | |
3a5df8ff | 1653 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1654 | } |
1655 | ||
1656 | static int arm_smmu_id_size_to_bits(int size) | |
1657 | { | |
1658 | switch (size) { | |
1659 | case 0: | |
1660 | return 32; | |
1661 | case 1: | |
1662 | return 36; | |
1663 | case 2: | |
1664 | return 40; | |
1665 | case 3: | |
1666 | return 42; | |
1667 | case 4: | |
1668 | return 44; | |
1669 | case 5: | |
1670 | default: | |
1671 | return 48; | |
1672 | } | |
1673 | } | |
1674 | ||
1675 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1676 | { | |
1677 | unsigned long size; | |
1678 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1679 | u32 id; | |
1680 | ||
1681 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
1682 | ||
1683 | /* Primecell ID */ | |
1684 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); | |
1685 | smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; | |
1686 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); | |
1687 | ||
1688 | /* ID0 */ | |
1689 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
1690 | #ifndef CONFIG_64BIT | |
1691 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { | |
1692 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); | |
1693 | return -ENODEV; | |
1694 | } | |
1695 | #endif | |
1696 | if (id & ID0_S1TS) { | |
1697 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1698 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1699 | } | |
1700 | ||
1701 | if (id & ID0_S2TS) { | |
1702 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1703 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1704 | } | |
1705 | ||
1706 | if (id & ID0_NTS) { | |
1707 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1708 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1709 | } | |
1710 | ||
1711 | if (!(smmu->features & | |
1712 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | | |
1713 | ARM_SMMU_FEAT_TRANS_NESTED))) { | |
1714 | dev_err(smmu->dev, "\tno translation support!\n"); | |
1715 | return -ENODEV; | |
1716 | } | |
1717 | ||
1718 | if (id & ID0_CTTW) { | |
1719 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1720 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1721 | } | |
1722 | ||
1723 | if (id & ID0_SMS) { | |
1724 | u32 smr, sid, mask; | |
1725 | ||
1726 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1727 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1728 | ID0_NUMSMRG_MASK; | |
1729 | if (smmu->num_mapping_groups == 0) { | |
1730 | dev_err(smmu->dev, | |
1731 | "stream-matching supported, but no SMRs present!\n"); | |
1732 | return -ENODEV; | |
1733 | } | |
1734 | ||
1735 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1736 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1737 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1738 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1739 | ||
1740 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1741 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1742 | if ((mask & sid) != sid) { | |
1743 | dev_err(smmu->dev, | |
1744 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1745 | mask, sid); | |
1746 | return -ENODEV; | |
1747 | } | |
1748 | ||
1749 | dev_notice(smmu->dev, | |
1750 | "\tstream matching with %u register groups, mask 0x%x", | |
1751 | smmu->num_mapping_groups, mask); | |
1752 | } | |
1753 | ||
1754 | /* ID1 */ | |
1755 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
1756 | smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; | |
1757 | ||
c55af7f7 | 1758 | /* Check for size mismatch of SMMU address space from mapped region */ |
45ae7cff WD |
1759 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
1760 | size *= (smmu->pagesize << 1); | |
c55af7f7 AH |
1761 | if (smmu->size != size) |
1762 | dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs " | |
1763 | "from mapped region size (0x%lx)!\n", size, smmu->size); | |
45ae7cff WD |
1764 | |
1765 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & | |
1766 | ID1_NUMS2CB_MASK; | |
1767 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; | |
1768 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1769 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1770 | return -ENODEV; | |
1771 | } | |
1772 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1773 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1774 | ||
1775 | /* ID2 */ | |
1776 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1777 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
1778 | ||
1779 | /* | |
1780 | * Stage-1 output limited by stage-2 input size due to pgd | |
1781 | * allocation (PTRS_PER_PGD). | |
1782 | */ | |
1783 | #ifdef CONFIG_64BIT | |
c4430841 | 1784 | smmu->s1_output_size = min((unsigned long)VA_BITS, size); |
45ae7cff WD |
1785 | #else |
1786 | smmu->s1_output_size = min(32UL, size); | |
1787 | #endif | |
1788 | ||
1789 | /* The stage-2 output mask is also applied for bypass */ | |
1790 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); | |
1791 | smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size); | |
1792 | ||
1793 | if (smmu->version == 1) { | |
1794 | smmu->input_size = 32; | |
1795 | } else { | |
1796 | #ifdef CONFIG_64BIT | |
1797 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; | |
06f983dd | 1798 | size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); |
45ae7cff WD |
1799 | #else |
1800 | size = 32; | |
1801 | #endif | |
1802 | smmu->input_size = size; | |
1803 | ||
1804 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || | |
1805 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || | |
1806 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { | |
1807 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", | |
1808 | PAGE_SIZE); | |
1809 | return -ENODEV; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | dev_notice(smmu->dev, | |
1814 | "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", | |
1815 | smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); | |
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) | |
1820 | { | |
1821 | struct resource *res; | |
1822 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1823 | struct device *dev = &pdev->dev; |
1824 | struct rb_node *node; | |
1825 | struct of_phandle_args masterspec; | |
1826 | int num_irqs, i, err; | |
1827 | ||
1828 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1829 | if (!smmu) { | |
1830 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1831 | return -ENOMEM; | |
1832 | } | |
1833 | smmu->dev = dev; | |
1834 | ||
1835 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
8a7f4312 JL |
1836 | smmu->base = devm_ioremap_resource(dev, res); |
1837 | if (IS_ERR(smmu->base)) | |
1838 | return PTR_ERR(smmu->base); | |
45ae7cff | 1839 | smmu->size = resource_size(res); |
45ae7cff WD |
1840 | |
1841 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1842 | &smmu->num_global_irqs)) { | |
1843 | dev_err(dev, "missing #global-interrupts property\n"); | |
1844 | return -ENODEV; | |
1845 | } | |
1846 | ||
1847 | num_irqs = 0; | |
1848 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1849 | num_irqs++; | |
1850 | if (num_irqs > smmu->num_global_irqs) | |
1851 | smmu->num_context_irqs++; | |
1852 | } | |
1853 | ||
44a08de2 AH |
1854 | if (!smmu->num_context_irqs) { |
1855 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1856 | num_irqs, smmu->num_global_irqs + 1); | |
1857 | return -ENODEV; | |
45ae7cff | 1858 | } |
45ae7cff WD |
1859 | |
1860 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1861 | GFP_KERNEL); | |
1862 | if (!smmu->irqs) { | |
1863 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1864 | return -ENOMEM; | |
1865 | } | |
1866 | ||
1867 | for (i = 0; i < num_irqs; ++i) { | |
1868 | int irq = platform_get_irq(pdev, i); | |
1869 | if (irq < 0) { | |
1870 | dev_err(dev, "failed to get irq index %d\n", i); | |
1871 | return -ENODEV; | |
1872 | } | |
1873 | smmu->irqs[i] = irq; | |
1874 | } | |
1875 | ||
1876 | i = 0; | |
1877 | smmu->masters = RB_ROOT; | |
1878 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1879 | "#stream-id-cells", i, | |
1880 | &masterspec)) { | |
1881 | err = register_smmu_master(smmu, dev, &masterspec); | |
1882 | if (err) { | |
1883 | dev_err(dev, "failed to add master %s\n", | |
1884 | masterspec.np->name); | |
1885 | goto out_put_masters; | |
1886 | } | |
1887 | ||
1888 | i++; | |
1889 | } | |
1890 | dev_notice(dev, "registered %d master devices\n", i); | |
1891 | ||
45ae7cff WD |
1892 | err = arm_smmu_device_cfg_probe(smmu); |
1893 | if (err) | |
44680eed | 1894 | goto out_put_masters; |
45ae7cff | 1895 | |
3a5df8ff AH |
1896 | parse_driver_options(smmu); |
1897 | ||
45ae7cff WD |
1898 | if (smmu->version > 1 && |
1899 | smmu->num_context_banks != smmu->num_context_irqs) { | |
1900 | dev_err(dev, | |
1901 | "found only %d context interrupt(s) but %d required\n", | |
1902 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1903 | err = -ENODEV; |
44680eed | 1904 | goto out_put_masters; |
45ae7cff WD |
1905 | } |
1906 | ||
45ae7cff WD |
1907 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1908 | err = request_irq(smmu->irqs[i], | |
1909 | arm_smmu_global_fault, | |
1910 | IRQF_SHARED, | |
1911 | "arm-smmu global fault", | |
1912 | smmu); | |
1913 | if (err) { | |
1914 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1915 | i, smmu->irqs[i]); | |
1916 | goto out_free_irqs; | |
1917 | } | |
1918 | } | |
1919 | ||
1920 | INIT_LIST_HEAD(&smmu->list); | |
1921 | spin_lock(&arm_smmu_devices_lock); | |
1922 | list_add(&smmu->list, &arm_smmu_devices); | |
1923 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1924 | |
1925 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1926 | return 0; |
1927 | ||
1928 | out_free_irqs: | |
1929 | while (i--) | |
1930 | free_irq(smmu->irqs[i], smmu); | |
1931 | ||
45ae7cff WD |
1932 | out_put_masters: |
1933 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
1934 | struct arm_smmu_master *master; | |
1935 | master = container_of(node, struct arm_smmu_master, node); | |
1936 | of_node_put(master->of_node); | |
1937 | } | |
1938 | ||
1939 | return err; | |
1940 | } | |
1941 | ||
1942 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1943 | { | |
1944 | int i; | |
1945 | struct device *dev = &pdev->dev; | |
1946 | struct arm_smmu_device *curr, *smmu = NULL; | |
1947 | struct rb_node *node; | |
1948 | ||
1949 | spin_lock(&arm_smmu_devices_lock); | |
1950 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1951 | if (curr->dev == dev) { | |
1952 | smmu = curr; | |
1953 | list_del(&smmu->list); | |
1954 | break; | |
1955 | } | |
1956 | } | |
1957 | spin_unlock(&arm_smmu_devices_lock); | |
1958 | ||
1959 | if (!smmu) | |
1960 | return -ENODEV; | |
1961 | ||
45ae7cff WD |
1962 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
1963 | struct arm_smmu_master *master; | |
1964 | master = container_of(node, struct arm_smmu_master, node); | |
1965 | of_node_put(master->of_node); | |
1966 | } | |
1967 | ||
ecfadb6e | 1968 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
1969 | dev_err(dev, "removing device with active domains!\n"); |
1970 | ||
1971 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
1972 | free_irq(smmu->irqs[i], smmu); | |
1973 | ||
1974 | /* Turn the thing off */ | |
3a5df8ff | 1975 | writel(sCR0_CLIENTPD,ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1976 | return 0; |
1977 | } | |
1978 | ||
1979 | #ifdef CONFIG_OF | |
1980 | static struct of_device_id arm_smmu_of_match[] = { | |
1981 | { .compatible = "arm,smmu-v1", }, | |
1982 | { .compatible = "arm,smmu-v2", }, | |
1983 | { .compatible = "arm,mmu-400", }, | |
1984 | { .compatible = "arm,mmu-500", }, | |
1985 | { }, | |
1986 | }; | |
1987 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
1988 | #endif | |
1989 | ||
1990 | static struct platform_driver arm_smmu_driver = { | |
1991 | .driver = { | |
1992 | .owner = THIS_MODULE, | |
1993 | .name = "arm-smmu", | |
1994 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
1995 | }, | |
1996 | .probe = arm_smmu_device_dt_probe, | |
1997 | .remove = arm_smmu_device_remove, | |
1998 | }; | |
1999 | ||
2000 | static int __init arm_smmu_init(void) | |
2001 | { | |
2002 | int ret; | |
2003 | ||
2004 | ret = platform_driver_register(&arm_smmu_driver); | |
2005 | if (ret) | |
2006 | return ret; | |
2007 | ||
2008 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 2009 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
2010 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
2011 | ||
d123cf82 | 2012 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 2013 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 2014 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 2015 | #endif |
45ae7cff | 2016 | |
a9a1b0b5 WD |
2017 | #ifdef CONFIG_PCI |
2018 | if (!iommu_present(&pci_bus_type)) | |
2019 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
2020 | #endif | |
2021 | ||
45ae7cff WD |
2022 | return 0; |
2023 | } | |
2024 | ||
2025 | static void __exit arm_smmu_exit(void) | |
2026 | { | |
2027 | return platform_driver_unregister(&arm_smmu_driver); | |
2028 | } | |
2029 | ||
b1950b27 | 2030 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
2031 | module_exit(arm_smmu_exit); |
2032 | ||
2033 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
2034 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
2035 | MODULE_LICENSE("GPL v2"); |