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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
45ae7cff WD |
26 | * - Context fault reporting |
27 | */ | |
28 | ||
29 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
30 | ||
31 | #include <linux/delay.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/err.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/iommu.h> | |
45ae7cff WD |
37 | #include <linux/module.h> |
38 | #include <linux/of.h> | |
a9a1b0b5 | 39 | #include <linux/pci.h> |
45ae7cff WD |
40 | #include <linux/platform_device.h> |
41 | #include <linux/slab.h> | |
42 | #include <linux/spinlock.h> | |
43 | ||
44 | #include <linux/amba/bus.h> | |
45 | ||
518f7136 | 46 | #include "io-pgtable.h" |
45ae7cff WD |
47 | |
48 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 49 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
50 | |
51 | /* Maximum number of context banks per SMMU */ | |
52 | #define ARM_SMMU_MAX_CBS 128 | |
53 | ||
54 | /* Maximum number of mapping groups per SMMU */ | |
55 | #define ARM_SMMU_MAX_SMRS 128 | |
56 | ||
45ae7cff WD |
57 | /* SMMU global address space */ |
58 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
c757e852 | 59 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) |
45ae7cff | 60 | |
3a5df8ff AH |
61 | /* |
62 | * SMMU global address space with conditional offset to access secure | |
63 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
64 | * nsGFSYNR0: 0x450) | |
65 | */ | |
66 | #define ARM_SMMU_GR0_NS(smmu) \ | |
67 | ((smmu)->base + \ | |
68 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
69 | ? 0x400 : 0)) | |
70 | ||
45ae7cff WD |
71 | /* Configuration registers */ |
72 | #define ARM_SMMU_GR0_sCR0 0x0 | |
73 | #define sCR0_CLIENTPD (1 << 0) | |
74 | #define sCR0_GFRE (1 << 1) | |
75 | #define sCR0_GFIE (1 << 2) | |
76 | #define sCR0_GCFGFRE (1 << 4) | |
77 | #define sCR0_GCFGFIE (1 << 5) | |
78 | #define sCR0_USFCFG (1 << 10) | |
79 | #define sCR0_VMIDPNE (1 << 11) | |
80 | #define sCR0_PTM (1 << 12) | |
81 | #define sCR0_FB (1 << 13) | |
82 | #define sCR0_BSU_SHIFT 14 | |
83 | #define sCR0_BSU_MASK 0x3 | |
84 | ||
85 | /* Identification registers */ | |
86 | #define ARM_SMMU_GR0_ID0 0x20 | |
87 | #define ARM_SMMU_GR0_ID1 0x24 | |
88 | #define ARM_SMMU_GR0_ID2 0x28 | |
89 | #define ARM_SMMU_GR0_ID3 0x2c | |
90 | #define ARM_SMMU_GR0_ID4 0x30 | |
91 | #define ARM_SMMU_GR0_ID5 0x34 | |
92 | #define ARM_SMMU_GR0_ID6 0x38 | |
93 | #define ARM_SMMU_GR0_ID7 0x3c | |
94 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
95 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
96 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
97 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
45ae7cff WD |
98 | |
99 | #define ID0_S1TS (1 << 30) | |
100 | #define ID0_S2TS (1 << 29) | |
101 | #define ID0_NTS (1 << 28) | |
102 | #define ID0_SMS (1 << 27) | |
45ae7cff WD |
103 | #define ID0_CTTW (1 << 14) |
104 | #define ID0_NUMIRPT_SHIFT 16 | |
105 | #define ID0_NUMIRPT_MASK 0xff | |
3c8766d0 OH |
106 | #define ID0_NUMSIDB_SHIFT 9 |
107 | #define ID0_NUMSIDB_MASK 0xf | |
45ae7cff WD |
108 | #define ID0_NUMSMRG_SHIFT 0 |
109 | #define ID0_NUMSMRG_MASK 0xff | |
110 | ||
111 | #define ID1_PAGESIZE (1 << 31) | |
112 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
113 | #define ID1_NUMPAGENDXB_MASK 7 | |
114 | #define ID1_NUMS2CB_SHIFT 16 | |
115 | #define ID1_NUMS2CB_MASK 0xff | |
116 | #define ID1_NUMCB_SHIFT 0 | |
117 | #define ID1_NUMCB_MASK 0xff | |
118 | ||
119 | #define ID2_OAS_SHIFT 4 | |
120 | #define ID2_OAS_MASK 0xf | |
121 | #define ID2_IAS_SHIFT 0 | |
122 | #define ID2_IAS_MASK 0xf | |
123 | #define ID2_UBS_SHIFT 8 | |
124 | #define ID2_UBS_MASK 0xf | |
125 | #define ID2_PTFS_4K (1 << 12) | |
126 | #define ID2_PTFS_16K (1 << 13) | |
127 | #define ID2_PTFS_64K (1 << 14) | |
128 | ||
45ae7cff | 129 | /* Global TLB invalidation */ |
45ae7cff WD |
130 | #define ARM_SMMU_GR0_TLBIVMID 0x64 |
131 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
132 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
133 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
134 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
135 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
136 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
137 | ||
138 | /* Stream mapping registers */ | |
139 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
140 | #define SMR_VALID (1 << 31) | |
141 | #define SMR_MASK_SHIFT 16 | |
142 | #define SMR_MASK_MASK 0x7fff | |
143 | #define SMR_ID_SHIFT 0 | |
144 | #define SMR_ID_MASK 0x7fff | |
145 | ||
146 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
147 | #define S2CR_CBNDX_SHIFT 0 | |
148 | #define S2CR_CBNDX_MASK 0xff | |
149 | #define S2CR_TYPE_SHIFT 16 | |
150 | #define S2CR_TYPE_MASK 0x3 | |
151 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
152 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
153 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
154 | ||
155 | /* Context bank attribute registers */ | |
156 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
157 | #define CBAR_VMID_SHIFT 0 | |
158 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
159 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
160 | #define CBAR_S1_BPSHCFG_MASK 3 | |
161 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
162 | #define CBAR_S1_MEMATTR_SHIFT 12 |
163 | #define CBAR_S1_MEMATTR_MASK 0xf | |
164 | #define CBAR_S1_MEMATTR_WB 0xf | |
165 | #define CBAR_TYPE_SHIFT 16 | |
166 | #define CBAR_TYPE_MASK 0x3 | |
167 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
168 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
169 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
170 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
171 | #define CBAR_IRPTNDX_SHIFT 24 | |
172 | #define CBAR_IRPTNDX_MASK 0xff | |
173 | ||
174 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
175 | #define CBA2R_RW64_32BIT (0 << 0) | |
176 | #define CBA2R_RW64_64BIT (1 << 0) | |
177 | ||
178 | /* Translation context bank */ | |
179 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
c757e852 | 180 | #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) |
45ae7cff WD |
181 | |
182 | #define ARM_SMMU_CB_SCTLR 0x0 | |
183 | #define ARM_SMMU_CB_RESUME 0x8 | |
184 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
185 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
186 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
518f7136 WD |
187 | #define ARM_SMMU_CB_TTBR1_LO 0x28 |
188 | #define ARM_SMMU_CB_TTBR1_HI 0x2c | |
45ae7cff WD |
189 | #define ARM_SMMU_CB_TTBCR 0x30 |
190 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
518f7136 | 191 | #define ARM_SMMU_CB_S1_MAIR1 0x3c |
45ae7cff WD |
192 | #define ARM_SMMU_CB_FSR 0x58 |
193 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
194 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
195 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
518f7136 | 196 | #define ARM_SMMU_CB_S1_TLBIVA 0x600 |
1463fe44 | 197 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
518f7136 WD |
198 | #define ARM_SMMU_CB_S1_TLBIVAL 0x620 |
199 | #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630 | |
200 | #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638 | |
45ae7cff WD |
201 | |
202 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
203 | #define SCTLR_CFCFG (1 << 7) | |
204 | #define SCTLR_CFIE (1 << 6) | |
205 | #define SCTLR_CFRE (1 << 5) | |
206 | #define SCTLR_E (1 << 4) | |
207 | #define SCTLR_AFE (1 << 2) | |
208 | #define SCTLR_TRE (1 << 1) | |
209 | #define SCTLR_M (1 << 0) | |
210 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
211 | ||
212 | #define RESUME_RETRY (0 << 0) | |
213 | #define RESUME_TERMINATE (1 << 0) | |
214 | ||
45ae7cff WD |
215 | #define TTBCR2_SEP_SHIFT 15 |
216 | #define TTBCR2_SEP_MASK 0x7 | |
217 | ||
45ae7cff WD |
218 | #define TTBCR2_ADDR_32 0 |
219 | #define TTBCR2_ADDR_36 1 | |
220 | #define TTBCR2_ADDR_40 2 | |
221 | #define TTBCR2_ADDR_42 3 | |
222 | #define TTBCR2_ADDR_44 4 | |
223 | #define TTBCR2_ADDR_48 5 | |
224 | ||
518f7136 | 225 | #define TTBRn_HI_ASID_SHIFT 16 |
45ae7cff WD |
226 | |
227 | #define FSR_MULTI (1 << 31) | |
228 | #define FSR_SS (1 << 30) | |
229 | #define FSR_UUT (1 << 8) | |
230 | #define FSR_ASF (1 << 7) | |
231 | #define FSR_TLBLKF (1 << 6) | |
232 | #define FSR_TLBMCF (1 << 5) | |
233 | #define FSR_EF (1 << 4) | |
234 | #define FSR_PF (1 << 3) | |
235 | #define FSR_AFF (1 << 2) | |
236 | #define FSR_TF (1 << 1) | |
237 | ||
2907320d MH |
238 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
239 | FSR_TLBMCF | FSR_TLBLKF) | |
240 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 241 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
242 | |
243 | #define FSYNR0_WNR (1 << 4) | |
244 | ||
4cf740b0 WD |
245 | static int force_stage; |
246 | module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); | |
247 | MODULE_PARM_DESC(force_stage, | |
248 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); | |
249 | ||
09360403 RM |
250 | enum arm_smmu_arch_version { |
251 | ARM_SMMU_V1 = 1, | |
252 | ARM_SMMU_V2, | |
253 | }; | |
254 | ||
45ae7cff WD |
255 | struct arm_smmu_smr { |
256 | u8 idx; | |
257 | u16 mask; | |
258 | u16 id; | |
259 | }; | |
260 | ||
a9a1b0b5 | 261 | struct arm_smmu_master_cfg { |
45ae7cff WD |
262 | int num_streamids; |
263 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
264 | struct arm_smmu_smr *smrs; |
265 | }; | |
266 | ||
a9a1b0b5 WD |
267 | struct arm_smmu_master { |
268 | struct device_node *of_node; | |
a9a1b0b5 WD |
269 | struct rb_node node; |
270 | struct arm_smmu_master_cfg cfg; | |
271 | }; | |
272 | ||
45ae7cff WD |
273 | struct arm_smmu_device { |
274 | struct device *dev; | |
45ae7cff WD |
275 | |
276 | void __iomem *base; | |
277 | unsigned long size; | |
c757e852 | 278 | unsigned long pgshift; |
45ae7cff WD |
279 | |
280 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
281 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
282 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
283 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
284 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
285 | u32 features; | |
3a5df8ff AH |
286 | |
287 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
288 | u32 options; | |
09360403 | 289 | enum arm_smmu_arch_version version; |
45ae7cff WD |
290 | |
291 | u32 num_context_banks; | |
292 | u32 num_s2_context_banks; | |
293 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
294 | atomic_t irptndx; | |
295 | ||
296 | u32 num_mapping_groups; | |
297 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
298 | ||
518f7136 WD |
299 | unsigned long va_size; |
300 | unsigned long ipa_size; | |
301 | unsigned long pa_size; | |
45ae7cff WD |
302 | |
303 | u32 num_global_irqs; | |
304 | u32 num_context_irqs; | |
305 | unsigned int *irqs; | |
306 | ||
45ae7cff WD |
307 | struct list_head list; |
308 | struct rb_root masters; | |
309 | }; | |
310 | ||
311 | struct arm_smmu_cfg { | |
45ae7cff WD |
312 | u8 cbndx; |
313 | u8 irptndx; | |
314 | u32 cbar; | |
45ae7cff | 315 | }; |
faea13b7 | 316 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 317 | |
ecfadb6e WD |
318 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
319 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
320 | ||
c752ce45 WD |
321 | enum arm_smmu_domain_stage { |
322 | ARM_SMMU_DOMAIN_S1 = 0, | |
323 | ARM_SMMU_DOMAIN_S2, | |
324 | ARM_SMMU_DOMAIN_NESTED, | |
325 | }; | |
326 | ||
45ae7cff | 327 | struct arm_smmu_domain { |
44680eed | 328 | struct arm_smmu_device *smmu; |
518f7136 WD |
329 | struct io_pgtable_ops *pgtbl_ops; |
330 | spinlock_t pgtbl_lock; | |
44680eed | 331 | struct arm_smmu_cfg cfg; |
c752ce45 | 332 | enum arm_smmu_domain_stage stage; |
518f7136 | 333 | struct mutex init_mutex; /* Protects smmu pointer */ |
45ae7cff WD |
334 | }; |
335 | ||
518f7136 WD |
336 | static struct iommu_ops arm_smmu_ops; |
337 | ||
45ae7cff WD |
338 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); |
339 | static LIST_HEAD(arm_smmu_devices); | |
340 | ||
3a5df8ff AH |
341 | struct arm_smmu_option_prop { |
342 | u32 opt; | |
343 | const char *prop; | |
344 | }; | |
345 | ||
2907320d | 346 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
347 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
348 | { 0, NULL}, | |
349 | }; | |
350 | ||
351 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
352 | { | |
353 | int i = 0; | |
2907320d | 354 | |
3a5df8ff AH |
355 | do { |
356 | if (of_property_read_bool(smmu->dev->of_node, | |
357 | arm_smmu_options[i].prop)) { | |
358 | smmu->options |= arm_smmu_options[i].opt; | |
359 | dev_notice(smmu->dev, "option %s\n", | |
360 | arm_smmu_options[i].prop); | |
361 | } | |
362 | } while (arm_smmu_options[++i].opt); | |
363 | } | |
364 | ||
8f68f8e2 | 365 | static struct device_node *dev_get_dev_node(struct device *dev) |
a9a1b0b5 WD |
366 | { |
367 | if (dev_is_pci(dev)) { | |
368 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 369 | |
a9a1b0b5 WD |
370 | while (!pci_is_root_bus(bus)) |
371 | bus = bus->parent; | |
8f68f8e2 | 372 | return bus->bridge->parent->of_node; |
a9a1b0b5 WD |
373 | } |
374 | ||
8f68f8e2 | 375 | return dev->of_node; |
a9a1b0b5 WD |
376 | } |
377 | ||
45ae7cff WD |
378 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
379 | struct device_node *dev_node) | |
380 | { | |
381 | struct rb_node *node = smmu->masters.rb_node; | |
382 | ||
383 | while (node) { | |
384 | struct arm_smmu_master *master; | |
2907320d | 385 | |
45ae7cff WD |
386 | master = container_of(node, struct arm_smmu_master, node); |
387 | ||
388 | if (dev_node < master->of_node) | |
389 | node = node->rb_left; | |
390 | else if (dev_node > master->of_node) | |
391 | node = node->rb_right; | |
392 | else | |
393 | return master; | |
394 | } | |
395 | ||
396 | return NULL; | |
397 | } | |
398 | ||
a9a1b0b5 | 399 | static struct arm_smmu_master_cfg * |
8f68f8e2 | 400 | find_smmu_master_cfg(struct device *dev) |
a9a1b0b5 | 401 | { |
8f68f8e2 WD |
402 | struct arm_smmu_master_cfg *cfg = NULL; |
403 | struct iommu_group *group = iommu_group_get(dev); | |
a9a1b0b5 | 404 | |
8f68f8e2 WD |
405 | if (group) { |
406 | cfg = iommu_group_get_iommudata(group); | |
407 | iommu_group_put(group); | |
408 | } | |
a9a1b0b5 | 409 | |
8f68f8e2 | 410 | return cfg; |
a9a1b0b5 WD |
411 | } |
412 | ||
45ae7cff WD |
413 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
414 | struct arm_smmu_master *master) | |
415 | { | |
416 | struct rb_node **new, *parent; | |
417 | ||
418 | new = &smmu->masters.rb_node; | |
419 | parent = NULL; | |
420 | while (*new) { | |
2907320d MH |
421 | struct arm_smmu_master *this |
422 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
423 | |
424 | parent = *new; | |
425 | if (master->of_node < this->of_node) | |
426 | new = &((*new)->rb_left); | |
427 | else if (master->of_node > this->of_node) | |
428 | new = &((*new)->rb_right); | |
429 | else | |
430 | return -EEXIST; | |
431 | } | |
432 | ||
433 | rb_link_node(&master->node, parent, new); | |
434 | rb_insert_color(&master->node, &smmu->masters); | |
435 | return 0; | |
436 | } | |
437 | ||
438 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
439 | struct device *dev, | |
440 | struct of_phandle_args *masterspec) | |
441 | { | |
442 | int i; | |
443 | struct arm_smmu_master *master; | |
444 | ||
445 | master = find_smmu_master(smmu, masterspec->np); | |
446 | if (master) { | |
447 | dev_err(dev, | |
448 | "rejecting multiple registrations for master device %s\n", | |
449 | masterspec->np->name); | |
450 | return -EBUSY; | |
451 | } | |
452 | ||
453 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
454 | dev_err(dev, | |
455 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
456 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
457 | return -ENOSPC; | |
458 | } | |
459 | ||
460 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
461 | if (!master) | |
462 | return -ENOMEM; | |
463 | ||
a9a1b0b5 WD |
464 | master->of_node = masterspec->np; |
465 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 466 | |
3c8766d0 OH |
467 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
468 | u16 streamid = masterspec->args[i]; | |
45ae7cff | 469 | |
3c8766d0 OH |
470 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
471 | (streamid >= smmu->num_mapping_groups)) { | |
472 | dev_err(dev, | |
473 | "stream ID for master device %s greater than maximum allowed (%d)\n", | |
474 | masterspec->np->name, smmu->num_mapping_groups); | |
475 | return -ERANGE; | |
476 | } | |
477 | master->cfg.streamids[i] = streamid; | |
478 | } | |
45ae7cff WD |
479 | return insert_smmu_master(smmu, master); |
480 | } | |
481 | ||
44680eed | 482 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 483 | { |
44680eed | 484 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 485 | struct arm_smmu_master *master = NULL; |
8f68f8e2 | 486 | struct device_node *dev_node = dev_get_dev_node(dev); |
45ae7cff WD |
487 | |
488 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 489 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
490 | master = find_smmu_master(smmu, dev_node); |
491 | if (master) | |
492 | break; | |
493 | } | |
45ae7cff | 494 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 495 | |
a9a1b0b5 | 496 | return master ? smmu : NULL; |
45ae7cff WD |
497 | } |
498 | ||
499 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
500 | { | |
501 | int idx; | |
502 | ||
503 | do { | |
504 | idx = find_next_zero_bit(map, end, start); | |
505 | if (idx == end) | |
506 | return -ENOSPC; | |
507 | } while (test_and_set_bit(idx, map)); | |
508 | ||
509 | return idx; | |
510 | } | |
511 | ||
512 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
513 | { | |
514 | clear_bit(idx, map); | |
515 | } | |
516 | ||
517 | /* Wait for any pending TLB invalidations to complete */ | |
518f7136 | 518 | static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu) |
45ae7cff WD |
519 | { |
520 | int count = 0; | |
521 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
522 | ||
523 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
524 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
525 | & sTLBGSTATUS_GSACTIVE) { | |
526 | cpu_relax(); | |
527 | if (++count == TLB_LOOP_TIMEOUT) { | |
528 | dev_err_ratelimited(smmu->dev, | |
529 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
530 | return; | |
531 | } | |
532 | udelay(1); | |
533 | } | |
534 | } | |
535 | ||
518f7136 WD |
536 | static void arm_smmu_tlb_sync(void *cookie) |
537 | { | |
538 | struct arm_smmu_domain *smmu_domain = cookie; | |
539 | __arm_smmu_tlb_sync(smmu_domain->smmu); | |
540 | } | |
541 | ||
542 | static void arm_smmu_tlb_inv_context(void *cookie) | |
1463fe44 | 543 | { |
518f7136 | 544 | struct arm_smmu_domain *smmu_domain = cookie; |
44680eed WD |
545 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
546 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 | 547 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
518f7136 | 548 | void __iomem *base; |
1463fe44 WD |
549 | |
550 | if (stage1) { | |
551 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
552 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
553 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
554 | } else { |
555 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
556 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
557 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
558 | } |
559 | ||
518f7136 WD |
560 | __arm_smmu_tlb_sync(smmu); |
561 | } | |
562 | ||
563 | static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size, | |
564 | bool leaf, void *cookie) | |
565 | { | |
566 | struct arm_smmu_domain *smmu_domain = cookie; | |
567 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
568 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
569 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
570 | void __iomem *reg; | |
571 | ||
572 | if (stage1) { | |
573 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
574 | reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA; | |
575 | ||
576 | if (!IS_ENABLED(CONFIG_64BIT) || smmu->version == ARM_SMMU_V1) { | |
577 | iova &= ~12UL; | |
578 | iova |= ARM_SMMU_CB_ASID(cfg); | |
579 | writel_relaxed(iova, reg); | |
580 | #ifdef CONFIG_64BIT | |
581 | } else { | |
582 | iova >>= 12; | |
583 | iova |= (u64)ARM_SMMU_CB_ASID(cfg) << 48; | |
584 | writeq_relaxed(iova, reg); | |
585 | #endif | |
586 | } | |
587 | #ifdef CONFIG_64BIT | |
588 | } else if (smmu->version == ARM_SMMU_V2) { | |
589 | reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
590 | reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L : | |
591 | ARM_SMMU_CB_S2_TLBIIPAS2; | |
592 | writeq_relaxed(iova >> 12, reg); | |
593 | #endif | |
594 | } else { | |
595 | reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID; | |
596 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), reg); | |
597 | } | |
598 | } | |
599 | ||
600 | static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie) | |
601 | { | |
602 | struct arm_smmu_domain *smmu_domain = cookie; | |
603 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
604 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
605 | ||
606 | ||
607 | /* Ensure new page tables are visible to the hardware walker */ | |
608 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
609 | dsb(ishst); | |
610 | } else { | |
611 | /* | |
612 | * If the SMMU can't walk tables in the CPU caches, treat them | |
613 | * like non-coherent DMA since we need to flush the new entries | |
614 | * all the way out to memory. There's no possibility of | |
615 | * recursion here as the SMMU table walker will not be wired | |
616 | * through another SMMU. | |
617 | */ | |
618 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
619 | DMA_TO_DEVICE); | |
620 | } | |
1463fe44 WD |
621 | } |
622 | ||
518f7136 WD |
623 | static struct iommu_gather_ops arm_smmu_gather_ops = { |
624 | .tlb_flush_all = arm_smmu_tlb_inv_context, | |
625 | .tlb_add_flush = arm_smmu_tlb_inv_range_nosync, | |
626 | .tlb_sync = arm_smmu_tlb_sync, | |
627 | .flush_pgtable = arm_smmu_flush_pgtable, | |
628 | }; | |
629 | ||
45ae7cff WD |
630 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
631 | { | |
632 | int flags, ret; | |
633 | u32 fsr, far, fsynr, resume; | |
634 | unsigned long iova; | |
635 | struct iommu_domain *domain = dev; | |
636 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
637 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
638 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
639 | void __iomem *cb_base; |
640 | ||
44680eed | 641 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
642 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
643 | ||
644 | if (!(fsr & FSR_FAULT)) | |
645 | return IRQ_NONE; | |
646 | ||
647 | if (fsr & FSR_IGN) | |
648 | dev_err_ratelimited(smmu->dev, | |
70c9a7db | 649 | "Unexpected context fault (fsr 0x%x)\n", |
45ae7cff WD |
650 | fsr); |
651 | ||
652 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
653 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
654 | ||
655 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
656 | iova = far; | |
657 | #ifdef CONFIG_64BIT | |
658 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
659 | iova |= ((unsigned long)far << 32); | |
660 | #endif | |
661 | ||
662 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
663 | ret = IRQ_HANDLED; | |
664 | resume = RESUME_RETRY; | |
665 | } else { | |
2ef0f031 AH |
666 | dev_err_ratelimited(smmu->dev, |
667 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 668 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
669 | ret = IRQ_NONE; |
670 | resume = RESUME_TERMINATE; | |
671 | } | |
672 | ||
673 | /* Clear the faulting FSR */ | |
674 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
675 | ||
676 | /* Retry or terminate any stalled transactions */ | |
677 | if (fsr & FSR_SS) | |
678 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
679 | ||
680 | return ret; | |
681 | } | |
682 | ||
683 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
684 | { | |
685 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
686 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 687 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
688 | |
689 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
690 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
691 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
692 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
693 | ||
3a5df8ff AH |
694 | if (!gfsr) |
695 | return IRQ_NONE; | |
696 | ||
45ae7cff WD |
697 | dev_err_ratelimited(smmu->dev, |
698 | "Unexpected global fault, this could be serious\n"); | |
699 | dev_err_ratelimited(smmu->dev, | |
700 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
701 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
702 | ||
703 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 704 | return IRQ_HANDLED; |
45ae7cff WD |
705 | } |
706 | ||
518f7136 WD |
707 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, |
708 | struct io_pgtable_cfg *pgtbl_cfg) | |
45ae7cff WD |
709 | { |
710 | u32 reg; | |
711 | bool stage1; | |
44680eed WD |
712 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
713 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
714 | void __iomem *cb_base, *gr0_base, *gr1_base; |
715 | ||
716 | gr0_base = ARM_SMMU_GR0(smmu); | |
717 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
718 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
719 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
720 | |
721 | /* CBAR */ | |
44680eed | 722 | reg = cfg->cbar; |
09360403 | 723 | if (smmu->version == ARM_SMMU_V1) |
2907320d | 724 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 725 | |
57ca90f6 WD |
726 | /* |
727 | * Use the weakest shareability/memory types, so they are | |
728 | * overridden by the ttbcr/pte. | |
729 | */ | |
730 | if (stage1) { | |
731 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
732 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
733 | } else { | |
44680eed | 734 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 735 | } |
44680eed | 736 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff | 737 | |
09360403 | 738 | if (smmu->version > ARM_SMMU_V1) { |
45ae7cff WD |
739 | /* CBA2R */ |
740 | #ifdef CONFIG_64BIT | |
741 | reg = CBA2R_RW64_64BIT; | |
742 | #else | |
743 | reg = CBA2R_RW64_32BIT; | |
744 | #endif | |
518f7136 | 745 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
746 | } |
747 | ||
518f7136 WD |
748 | /* TTBRs */ |
749 | if (stage1) { | |
750 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; | |
751 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); | |
752 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0] >> 32; | |
44680eed | 753 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
518f7136 | 754 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff | 755 | |
518f7136 WD |
756 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; |
757 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_LO); | |
758 | reg = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1] >> 32; | |
759 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; | |
760 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR1_HI); | |
761 | } else { | |
762 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; | |
763 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); | |
764 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vttbr >> 32; | |
765 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); | |
766 | } | |
a65217a4 | 767 | |
518f7136 WD |
768 | /* TTBCR */ |
769 | if (stage1) { | |
770 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr; | |
771 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
772 | if (smmu->version > ARM_SMMU_V1) { | |
773 | reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; | |
774 | switch (smmu->va_size) { | |
45ae7cff | 775 | case 32: |
518f7136 | 776 | reg |= (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
777 | break; |
778 | case 36: | |
518f7136 | 779 | reg |= (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
780 | break; |
781 | case 40: | |
518f7136 | 782 | reg |= (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
783 | break; |
784 | case 42: | |
518f7136 | 785 | reg |= (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
786 | break; |
787 | case 44: | |
518f7136 | 788 | reg |= (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
789 | break; |
790 | case 48: | |
518f7136 | 791 | reg |= (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); |
45ae7cff WD |
792 | break; |
793 | } | |
518f7136 | 794 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); |
45ae7cff WD |
795 | } |
796 | } else { | |
518f7136 WD |
797 | reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; |
798 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); | |
45ae7cff WD |
799 | } |
800 | ||
518f7136 | 801 | /* MAIRs (stage-1 only) */ |
45ae7cff | 802 | if (stage1) { |
518f7136 | 803 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; |
45ae7cff | 804 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); |
518f7136 WD |
805 | reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; |
806 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1); | |
45ae7cff WD |
807 | } |
808 | ||
45ae7cff WD |
809 | /* SCTLR */ |
810 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
811 | if (stage1) | |
812 | reg |= SCTLR_S1_ASIDPNE; | |
813 | #ifdef __BIG_ENDIAN | |
814 | reg |= SCTLR_E; | |
815 | #endif | |
25724841 | 816 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
817 | } |
818 | ||
819 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 820 | struct arm_smmu_device *smmu) |
45ae7cff | 821 | { |
a18037b2 | 822 | int irq, start, ret = 0; |
518f7136 WD |
823 | unsigned long ias, oas; |
824 | struct io_pgtable_ops *pgtbl_ops; | |
825 | struct io_pgtable_cfg pgtbl_cfg; | |
826 | enum io_pgtable_fmt fmt; | |
45ae7cff | 827 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 828 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 829 | |
518f7136 | 830 | mutex_lock(&smmu_domain->init_mutex); |
a18037b2 MH |
831 | if (smmu_domain->smmu) |
832 | goto out_unlock; | |
833 | ||
c752ce45 WD |
834 | /* |
835 | * Mapping the requested stage onto what we support is surprisingly | |
836 | * complicated, mainly because the spec allows S1+S2 SMMUs without | |
837 | * support for nested translation. That means we end up with the | |
838 | * following table: | |
839 | * | |
840 | * Requested Supported Actual | |
841 | * S1 N S1 | |
842 | * S1 S1+S2 S1 | |
843 | * S1 S2 S2 | |
844 | * S1 S1 S1 | |
845 | * N N N | |
846 | * N S1+S2 S2 | |
847 | * N S2 S2 | |
848 | * N S1 S1 | |
849 | * | |
850 | * Note that you can't actually request stage-2 mappings. | |
851 | */ | |
852 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) | |
853 | smmu_domain->stage = ARM_SMMU_DOMAIN_S2; | |
854 | if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) | |
855 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; | |
856 | ||
857 | switch (smmu_domain->stage) { | |
858 | case ARM_SMMU_DOMAIN_S1: | |
859 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; | |
860 | start = smmu->num_s2_context_banks; | |
518f7136 WD |
861 | ias = smmu->va_size; |
862 | oas = smmu->ipa_size; | |
863 | if (IS_ENABLED(CONFIG_64BIT)) | |
864 | fmt = ARM_64_LPAE_S1; | |
865 | else | |
866 | fmt = ARM_32_LPAE_S1; | |
c752ce45 WD |
867 | break; |
868 | case ARM_SMMU_DOMAIN_NESTED: | |
45ae7cff WD |
869 | /* |
870 | * We will likely want to change this if/when KVM gets | |
871 | * involved. | |
872 | */ | |
c752ce45 | 873 | case ARM_SMMU_DOMAIN_S2: |
9c5c92e3 WD |
874 | cfg->cbar = CBAR_TYPE_S2_TRANS; |
875 | start = 0; | |
518f7136 WD |
876 | ias = smmu->ipa_size; |
877 | oas = smmu->pa_size; | |
878 | if (IS_ENABLED(CONFIG_64BIT)) | |
879 | fmt = ARM_64_LPAE_S2; | |
880 | else | |
881 | fmt = ARM_32_LPAE_S2; | |
c752ce45 WD |
882 | break; |
883 | default: | |
884 | ret = -EINVAL; | |
885 | goto out_unlock; | |
45ae7cff WD |
886 | } |
887 | ||
888 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
889 | smmu->num_context_banks); | |
890 | if (IS_ERR_VALUE(ret)) | |
a18037b2 | 891 | goto out_unlock; |
45ae7cff | 892 | |
44680eed | 893 | cfg->cbndx = ret; |
09360403 | 894 | if (smmu->version == ARM_SMMU_V1) { |
44680eed WD |
895 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
896 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 897 | } else { |
44680eed | 898 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
899 | } |
900 | ||
518f7136 WD |
901 | pgtbl_cfg = (struct io_pgtable_cfg) { |
902 | .pgsize_bitmap = arm_smmu_ops.pgsize_bitmap, | |
903 | .ias = ias, | |
904 | .oas = oas, | |
905 | .tlb = &arm_smmu_gather_ops, | |
906 | }; | |
907 | ||
908 | smmu_domain->smmu = smmu; | |
909 | pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); | |
910 | if (!pgtbl_ops) { | |
911 | ret = -ENOMEM; | |
912 | goto out_clear_smmu; | |
913 | } | |
914 | ||
915 | /* Update our support page sizes to reflect the page table format */ | |
916 | arm_smmu_ops.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; | |
a18037b2 | 917 | |
518f7136 WD |
918 | /* Initialise the context bank with our page table cfg */ |
919 | arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); | |
920 | ||
921 | /* | |
922 | * Request context fault interrupt. Do this last to avoid the | |
923 | * handler seeing a half-initialised domain state. | |
924 | */ | |
44680eed | 925 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
926 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
927 | "arm-smmu-context-fault", domain); | |
928 | if (IS_ERR_VALUE(ret)) { | |
929 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
930 | cfg->irptndx, irq); |
931 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
932 | } |
933 | ||
518f7136 WD |
934 | mutex_unlock(&smmu_domain->init_mutex); |
935 | ||
936 | /* Publish page table ops for map/unmap */ | |
937 | smmu_domain->pgtbl_ops = pgtbl_ops; | |
a9a1b0b5 | 938 | return 0; |
45ae7cff | 939 | |
518f7136 WD |
940 | out_clear_smmu: |
941 | smmu_domain->smmu = NULL; | |
a18037b2 | 942 | out_unlock: |
518f7136 | 943 | mutex_unlock(&smmu_domain->init_mutex); |
45ae7cff WD |
944 | return ret; |
945 | } | |
946 | ||
947 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
948 | { | |
949 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
950 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
951 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 952 | void __iomem *cb_base; |
45ae7cff WD |
953 | int irq; |
954 | ||
955 | if (!smmu) | |
956 | return; | |
957 | ||
518f7136 WD |
958 | /* |
959 | * Disable the context bank and free the page tables before freeing | |
960 | * it. | |
961 | */ | |
44680eed | 962 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 963 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
1463fe44 | 964 | |
44680eed WD |
965 | if (cfg->irptndx != INVALID_IRPTNDX) { |
966 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
967 | free_irq(irq, domain); |
968 | } | |
969 | ||
518f7136 WD |
970 | if (smmu_domain->pgtbl_ops) |
971 | free_io_pgtable_ops(smmu_domain->pgtbl_ops); | |
972 | ||
44680eed | 973 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
974 | } |
975 | ||
976 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
977 | { | |
978 | struct arm_smmu_domain *smmu_domain; | |
45ae7cff WD |
979 | |
980 | /* | |
981 | * Allocate the domain and initialise some of its data structures. | |
982 | * We can't really do anything meaningful until we've added a | |
983 | * master. | |
984 | */ | |
985 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
986 | if (!smmu_domain) | |
987 | return -ENOMEM; | |
988 | ||
518f7136 WD |
989 | mutex_init(&smmu_domain->init_mutex); |
990 | spin_lock_init(&smmu_domain->pgtbl_lock); | |
45ae7cff WD |
991 | domain->priv = smmu_domain; |
992 | return 0; | |
45ae7cff WD |
993 | } |
994 | ||
995 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
996 | { | |
997 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
998 | |
999 | /* | |
1000 | * Free the domain resources. We assume that all devices have | |
1001 | * already been detached. | |
1002 | */ | |
45ae7cff | 1003 | arm_smmu_destroy_domain_context(domain); |
45ae7cff WD |
1004 | kfree(smmu_domain); |
1005 | } | |
1006 | ||
1007 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1008 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1009 | { |
1010 | int i; | |
1011 | struct arm_smmu_smr *smrs; | |
1012 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1013 | ||
1014 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1015 | return 0; | |
1016 | ||
a9a1b0b5 | 1017 | if (cfg->smrs) |
45ae7cff WD |
1018 | return -EEXIST; |
1019 | ||
2907320d | 1020 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 1021 | if (!smrs) { |
a9a1b0b5 WD |
1022 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1023 | cfg->num_streamids); | |
45ae7cff WD |
1024 | return -ENOMEM; |
1025 | } | |
1026 | ||
44680eed | 1027 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1028 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1029 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1030 | smmu->num_mapping_groups); | |
1031 | if (IS_ERR_VALUE(idx)) { | |
1032 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1033 | goto err_free_smrs; | |
1034 | } | |
1035 | ||
1036 | smrs[i] = (struct arm_smmu_smr) { | |
1037 | .idx = idx, | |
1038 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1039 | .id = cfg->streamids[i], |
45ae7cff WD |
1040 | }; |
1041 | } | |
1042 | ||
1043 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1044 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1045 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1046 | smrs[i].mask << SMR_MASK_SHIFT; | |
1047 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1048 | } | |
1049 | ||
a9a1b0b5 | 1050 | cfg->smrs = smrs; |
45ae7cff WD |
1051 | return 0; |
1052 | ||
1053 | err_free_smrs: | |
1054 | while (--i >= 0) | |
1055 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1056 | kfree(smrs); | |
1057 | return -ENOSPC; | |
1058 | } | |
1059 | ||
1060 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1061 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1062 | { |
1063 | int i; | |
1064 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1065 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff | 1066 | |
43b412be WD |
1067 | if (!smrs) |
1068 | return; | |
1069 | ||
45ae7cff | 1070 | /* Invalidate the SMRs before freeing back to the allocator */ |
a9a1b0b5 | 1071 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1072 | u8 idx = smrs[i].idx; |
2907320d | 1073 | |
45ae7cff WD |
1074 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1075 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1076 | } | |
1077 | ||
a9a1b0b5 | 1078 | cfg->smrs = NULL; |
45ae7cff WD |
1079 | kfree(smrs); |
1080 | } | |
1081 | ||
45ae7cff | 1082 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
a9a1b0b5 | 1083 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1084 | { |
1085 | int i, ret; | |
44680eed | 1086 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1087 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1088 | ||
8f68f8e2 | 1089 | /* Devices in an IOMMU group may already be configured */ |
a9a1b0b5 | 1090 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff | 1091 | if (ret) |
8f68f8e2 | 1092 | return ret == -EEXIST ? 0 : ret; |
45ae7cff | 1093 | |
a9a1b0b5 | 1094 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1095 | u32 idx, s2cr; |
2907320d | 1096 | |
a9a1b0b5 | 1097 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1098 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1099 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1100 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1107 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1108 | { |
43b412be | 1109 | int i; |
44680eed | 1110 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
43b412be | 1111 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
45ae7cff | 1112 | |
8f68f8e2 WD |
1113 | /* An IOMMU group is torn down by the first device to be removed */ |
1114 | if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) | |
1115 | return; | |
45ae7cff WD |
1116 | |
1117 | /* | |
1118 | * We *must* clear the S2CR first, because freeing the SMR means | |
1119 | * that it can be re-allocated immediately. | |
1120 | */ | |
43b412be WD |
1121 | for (i = 0; i < cfg->num_streamids; ++i) { |
1122 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; | |
1123 | ||
1124 | writel_relaxed(S2CR_TYPE_BYPASS, | |
1125 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); | |
1126 | } | |
1127 | ||
a9a1b0b5 | 1128 | arm_smmu_master_free_smrs(smmu, cfg); |
45ae7cff WD |
1129 | } |
1130 | ||
1131 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1132 | { | |
a18037b2 | 1133 | int ret; |
45ae7cff | 1134 | struct arm_smmu_domain *smmu_domain = domain->priv; |
518f7136 | 1135 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 1136 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1137 | |
8f68f8e2 | 1138 | smmu = find_smmu_for_device(dev); |
44680eed | 1139 | if (!smmu) { |
45ae7cff WD |
1140 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1141 | return -ENXIO; | |
1142 | } | |
1143 | ||
844e35bd WD |
1144 | if (dev->archdata.iommu) { |
1145 | dev_err(dev, "already attached to IOMMU domain\n"); | |
1146 | return -EEXIST; | |
1147 | } | |
1148 | ||
518f7136 WD |
1149 | /* Ensure that the domain is finalised */ |
1150 | ret = arm_smmu_init_domain_context(domain, smmu); | |
1151 | if (IS_ERR_VALUE(ret)) | |
1152 | return ret; | |
1153 | ||
45ae7cff | 1154 | /* |
44680eed WD |
1155 | * Sanity check the domain. We don't support domains across |
1156 | * different SMMUs. | |
45ae7cff | 1157 | */ |
518f7136 | 1158 | if (smmu_domain->smmu != smmu) { |
45ae7cff WD |
1159 | dev_err(dev, |
1160 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
a18037b2 MH |
1161 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
1162 | return -EINVAL; | |
45ae7cff | 1163 | } |
45ae7cff WD |
1164 | |
1165 | /* Looks ok, so add the device to the domain */ | |
8f68f8e2 | 1166 | cfg = find_smmu_master_cfg(dev); |
a9a1b0b5 | 1167 | if (!cfg) |
45ae7cff WD |
1168 | return -ENODEV; |
1169 | ||
844e35bd WD |
1170 | ret = arm_smmu_domain_add_master(smmu_domain, cfg); |
1171 | if (!ret) | |
1172 | dev->archdata.iommu = domain; | |
45ae7cff WD |
1173 | return ret; |
1174 | } | |
1175 | ||
1176 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1177 | { | |
1178 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1179 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1180 | |
8f68f8e2 | 1181 | cfg = find_smmu_master_cfg(dev); |
844e35bd WD |
1182 | if (!cfg) |
1183 | return; | |
1184 | ||
1185 | dev->archdata.iommu = NULL; | |
1186 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1187 | } |
1188 | ||
45ae7cff | 1189 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, |
b410aed9 | 1190 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff | 1191 | { |
518f7136 WD |
1192 | int ret; |
1193 | unsigned long flags; | |
45ae7cff | 1194 | struct arm_smmu_domain *smmu_domain = domain->priv; |
518f7136 | 1195 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1196 | |
518f7136 | 1197 | if (!ops) |
45ae7cff WD |
1198 | return -ENODEV; |
1199 | ||
518f7136 WD |
1200 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
1201 | ret = ops->map(ops, iova, paddr, size, prot); | |
1202 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); | |
1203 | return ret; | |
45ae7cff WD |
1204 | } |
1205 | ||
1206 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1207 | size_t size) | |
1208 | { | |
518f7136 WD |
1209 | size_t ret; |
1210 | unsigned long flags; | |
45ae7cff | 1211 | struct arm_smmu_domain *smmu_domain = domain->priv; |
518f7136 | 1212 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1213 | |
518f7136 WD |
1214 | if (!ops) |
1215 | return 0; | |
1216 | ||
1217 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); | |
1218 | ret = ops->unmap(ops, iova, size); | |
1219 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); | |
1220 | return ret; | |
45ae7cff WD |
1221 | } |
1222 | ||
1223 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1224 | dma_addr_t iova) | |
1225 | { | |
518f7136 WD |
1226 | phys_addr_t ret; |
1227 | unsigned long flags; | |
45ae7cff | 1228 | struct arm_smmu_domain *smmu_domain = domain->priv; |
518f7136 | 1229 | struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops; |
45ae7cff | 1230 | |
518f7136 | 1231 | if (!ops) |
a44a9791 | 1232 | return 0; |
45ae7cff | 1233 | |
518f7136 WD |
1234 | spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); |
1235 | ret = ops->iova_to_phys(ops, iova); | |
1236 | spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); | |
1237 | return ret; | |
45ae7cff WD |
1238 | } |
1239 | ||
1fd0c775 | 1240 | static bool arm_smmu_capable(enum iommu_cap cap) |
45ae7cff | 1241 | { |
d0948945 WD |
1242 | switch (cap) { |
1243 | case IOMMU_CAP_CACHE_COHERENCY: | |
1fd0c775 JR |
1244 | /* |
1245 | * Return true here as the SMMU can always send out coherent | |
1246 | * requests. | |
1247 | */ | |
1248 | return true; | |
d0948945 | 1249 | case IOMMU_CAP_INTR_REMAP: |
1fd0c775 | 1250 | return true; /* MSIs are just memory writes */ |
0029a8dd AM |
1251 | case IOMMU_CAP_NOEXEC: |
1252 | return true; | |
d0948945 | 1253 | default: |
1fd0c775 | 1254 | return false; |
d0948945 | 1255 | } |
45ae7cff | 1256 | } |
45ae7cff | 1257 | |
a9a1b0b5 WD |
1258 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1259 | { | |
1260 | *((u16 *)data) = alias; | |
1261 | return 0; /* Continue walking */ | |
45ae7cff WD |
1262 | } |
1263 | ||
8f68f8e2 WD |
1264 | static void __arm_smmu_release_pci_iommudata(void *data) |
1265 | { | |
1266 | kfree(data); | |
1267 | } | |
1268 | ||
45ae7cff WD |
1269 | static int arm_smmu_add_device(struct device *dev) |
1270 | { | |
a9a1b0b5 | 1271 | struct arm_smmu_device *smmu; |
8f68f8e2 | 1272 | struct arm_smmu_master_cfg *cfg; |
5fc63a7c | 1273 | struct iommu_group *group; |
8f68f8e2 | 1274 | void (*releasefn)(void *) = NULL; |
5fc63a7c AM |
1275 | int ret; |
1276 | ||
44680eed | 1277 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1278 | if (!smmu) |
45ae7cff WD |
1279 | return -ENODEV; |
1280 | ||
5fc63a7c AM |
1281 | group = iommu_group_alloc(); |
1282 | if (IS_ERR(group)) { | |
1283 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1284 | return PTR_ERR(group); | |
1285 | } | |
1286 | ||
a9a1b0b5 | 1287 | if (dev_is_pci(dev)) { |
a9a1b0b5 WD |
1288 | struct pci_dev *pdev = to_pci_dev(dev); |
1289 | ||
1290 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1291 | if (!cfg) { | |
1292 | ret = -ENOMEM; | |
1293 | goto out_put_group; | |
1294 | } | |
1295 | ||
1296 | cfg->num_streamids = 1; | |
1297 | /* | |
1298 | * Assume Stream ID == Requester ID for now. | |
1299 | * We need a way to describe the ID mappings in FDT. | |
1300 | */ | |
1301 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1302 | &cfg->streamids[0]); | |
8f68f8e2 | 1303 | releasefn = __arm_smmu_release_pci_iommudata; |
a9a1b0b5 | 1304 | } else { |
8f68f8e2 WD |
1305 | struct arm_smmu_master *master; |
1306 | ||
1307 | master = find_smmu_master(smmu, dev->of_node); | |
1308 | if (!master) { | |
1309 | ret = -ENODEV; | |
1310 | goto out_put_group; | |
1311 | } | |
1312 | ||
1313 | cfg = &master->cfg; | |
a9a1b0b5 WD |
1314 | } |
1315 | ||
8f68f8e2 | 1316 | iommu_group_set_iommudata(group, cfg, releasefn); |
5fc63a7c | 1317 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1318 | |
a9a1b0b5 WD |
1319 | out_put_group: |
1320 | iommu_group_put(group); | |
5fc63a7c | 1321 | return ret; |
45ae7cff WD |
1322 | } |
1323 | ||
1324 | static void arm_smmu_remove_device(struct device *dev) | |
1325 | { | |
5fc63a7c | 1326 | iommu_group_remove_device(dev); |
45ae7cff WD |
1327 | } |
1328 | ||
c752ce45 WD |
1329 | static int arm_smmu_domain_get_attr(struct iommu_domain *domain, |
1330 | enum iommu_attr attr, void *data) | |
1331 | { | |
1332 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1333 | ||
1334 | switch (attr) { | |
1335 | case DOMAIN_ATTR_NESTING: | |
1336 | *(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED); | |
1337 | return 0; | |
1338 | default: | |
1339 | return -ENODEV; | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | static int arm_smmu_domain_set_attr(struct iommu_domain *domain, | |
1344 | enum iommu_attr attr, void *data) | |
1345 | { | |
518f7136 | 1346 | int ret = 0; |
c752ce45 WD |
1347 | struct arm_smmu_domain *smmu_domain = domain->priv; |
1348 | ||
518f7136 WD |
1349 | mutex_lock(&smmu_domain->init_mutex); |
1350 | ||
c752ce45 WD |
1351 | switch (attr) { |
1352 | case DOMAIN_ATTR_NESTING: | |
518f7136 WD |
1353 | if (smmu_domain->smmu) { |
1354 | ret = -EPERM; | |
1355 | goto out_unlock; | |
1356 | } | |
1357 | ||
c752ce45 WD |
1358 | if (*(int *)data) |
1359 | smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; | |
1360 | else | |
1361 | smmu_domain->stage = ARM_SMMU_DOMAIN_S1; | |
1362 | ||
518f7136 | 1363 | break; |
c752ce45 | 1364 | default: |
518f7136 | 1365 | ret = -ENODEV; |
c752ce45 | 1366 | } |
518f7136 WD |
1367 | |
1368 | out_unlock: | |
1369 | mutex_unlock(&smmu_domain->init_mutex); | |
1370 | return ret; | |
c752ce45 WD |
1371 | } |
1372 | ||
518f7136 | 1373 | static struct iommu_ops arm_smmu_ops = { |
c752ce45 WD |
1374 | .capable = arm_smmu_capable, |
1375 | .domain_init = arm_smmu_domain_init, | |
1376 | .domain_destroy = arm_smmu_domain_destroy, | |
1377 | .attach_dev = arm_smmu_attach_dev, | |
1378 | .detach_dev = arm_smmu_detach_dev, | |
1379 | .map = arm_smmu_map, | |
1380 | .unmap = arm_smmu_unmap, | |
76771c93 | 1381 | .map_sg = default_iommu_map_sg, |
c752ce45 WD |
1382 | .iova_to_phys = arm_smmu_iova_to_phys, |
1383 | .add_device = arm_smmu_add_device, | |
1384 | .remove_device = arm_smmu_remove_device, | |
1385 | .domain_get_attr = arm_smmu_domain_get_attr, | |
1386 | .domain_set_attr = arm_smmu_domain_set_attr, | |
518f7136 | 1387 | .pgsize_bitmap = -1UL, /* Restricted during device attach */ |
45ae7cff WD |
1388 | }; |
1389 | ||
1390 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1391 | { | |
1392 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1393 | void __iomem *cb_base; |
45ae7cff | 1394 | int i = 0; |
659db6f6 AH |
1395 | u32 reg; |
1396 | ||
3a5df8ff AH |
1397 | /* clear global FSR */ |
1398 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1399 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1400 | |
1401 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1402 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
3c8766d0 | 1403 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
2907320d MH |
1404 | writel_relaxed(S2CR_TYPE_BYPASS, |
1405 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1406 | } |
1407 | ||
659db6f6 AH |
1408 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1409 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1410 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1411 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1412 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1413 | } | |
1463fe44 | 1414 | |
45ae7cff | 1415 | /* Invalidate the TLB, just in case */ |
45ae7cff WD |
1416 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); |
1417 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1418 | ||
3a5df8ff | 1419 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1420 | |
45ae7cff | 1421 | /* Enable fault reporting */ |
659db6f6 | 1422 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1423 | |
1424 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1425 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1426 | |
1427 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1428 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1429 | |
1430 | /* Disable forced broadcasting */ | |
659db6f6 | 1431 | reg &= ~sCR0_FB; |
45ae7cff WD |
1432 | |
1433 | /* Don't upgrade barriers */ | |
659db6f6 | 1434 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1435 | |
1436 | /* Push the button */ | |
518f7136 | 1437 | __arm_smmu_tlb_sync(smmu); |
3a5df8ff | 1438 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1439 | } |
1440 | ||
1441 | static int arm_smmu_id_size_to_bits(int size) | |
1442 | { | |
1443 | switch (size) { | |
1444 | case 0: | |
1445 | return 32; | |
1446 | case 1: | |
1447 | return 36; | |
1448 | case 2: | |
1449 | return 40; | |
1450 | case 3: | |
1451 | return 42; | |
1452 | case 4: | |
1453 | return 44; | |
1454 | case 5: | |
1455 | default: | |
1456 | return 48; | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1461 | { | |
1462 | unsigned long size; | |
1463 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1464 | u32 id; | |
1465 | ||
1466 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
45ae7cff WD |
1467 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); |
1468 | ||
1469 | /* ID0 */ | |
1470 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
4cf740b0 WD |
1471 | |
1472 | /* Restrict available stages based on module parameter */ | |
1473 | if (force_stage == 1) | |
1474 | id &= ~(ID0_S2TS | ID0_NTS); | |
1475 | else if (force_stage == 2) | |
1476 | id &= ~(ID0_S1TS | ID0_NTS); | |
1477 | ||
45ae7cff WD |
1478 | if (id & ID0_S1TS) { |
1479 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1480 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1481 | } | |
1482 | ||
1483 | if (id & ID0_S2TS) { | |
1484 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1485 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1486 | } | |
1487 | ||
1488 | if (id & ID0_NTS) { | |
1489 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1490 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1491 | } | |
1492 | ||
1493 | if (!(smmu->features & | |
4cf740b0 | 1494 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
45ae7cff WD |
1495 | dev_err(smmu->dev, "\tno translation support!\n"); |
1496 | return -ENODEV; | |
1497 | } | |
1498 | ||
1499 | if (id & ID0_CTTW) { | |
1500 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1501 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1502 | } | |
1503 | ||
1504 | if (id & ID0_SMS) { | |
1505 | u32 smr, sid, mask; | |
1506 | ||
1507 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1508 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1509 | ID0_NUMSMRG_MASK; | |
1510 | if (smmu->num_mapping_groups == 0) { | |
1511 | dev_err(smmu->dev, | |
1512 | "stream-matching supported, but no SMRs present!\n"); | |
1513 | return -ENODEV; | |
1514 | } | |
1515 | ||
1516 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1517 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1518 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1519 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1520 | ||
1521 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1522 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1523 | if ((mask & sid) != sid) { | |
1524 | dev_err(smmu->dev, | |
1525 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1526 | mask, sid); | |
1527 | return -ENODEV; | |
1528 | } | |
1529 | ||
1530 | dev_notice(smmu->dev, | |
1531 | "\tstream matching with %u register groups, mask 0x%x", | |
1532 | smmu->num_mapping_groups, mask); | |
3c8766d0 OH |
1533 | } else { |
1534 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & | |
1535 | ID0_NUMSIDB_MASK; | |
45ae7cff WD |
1536 | } |
1537 | ||
1538 | /* ID1 */ | |
1539 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
c757e852 | 1540 | smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12; |
45ae7cff | 1541 | |
c55af7f7 | 1542 | /* Check for size mismatch of SMMU address space from mapped region */ |
518f7136 | 1543 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
c757e852 | 1544 | size *= 2 << smmu->pgshift; |
c55af7f7 | 1545 | if (smmu->size != size) |
2907320d MH |
1546 | dev_warn(smmu->dev, |
1547 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1548 | size, smmu->size); | |
45ae7cff | 1549 | |
518f7136 | 1550 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK; |
45ae7cff WD |
1551 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; |
1552 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1553 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1554 | return -ENODEV; | |
1555 | } | |
1556 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1557 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1558 | ||
1559 | /* ID2 */ | |
1560 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1561 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
518f7136 | 1562 | smmu->ipa_size = size; |
45ae7cff | 1563 | |
518f7136 | 1564 | /* The output mask is also applied for bypass */ |
45ae7cff | 1565 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); |
518f7136 | 1566 | smmu->pa_size = size; |
45ae7cff | 1567 | |
09360403 | 1568 | if (smmu->version == ARM_SMMU_V1) { |
518f7136 WD |
1569 | smmu->va_size = smmu->ipa_size; |
1570 | size = SZ_4K | SZ_2M | SZ_1G; | |
45ae7cff | 1571 | } else { |
45ae7cff | 1572 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; |
518f7136 WD |
1573 | smmu->va_size = arm_smmu_id_size_to_bits(size); |
1574 | #ifndef CONFIG_64BIT | |
1575 | smmu->va_size = min(32UL, smmu->va_size); | |
45ae7cff | 1576 | #endif |
518f7136 WD |
1577 | size = 0; |
1578 | if (id & ID2_PTFS_4K) | |
1579 | size |= SZ_4K | SZ_2M | SZ_1G; | |
1580 | if (id & ID2_PTFS_16K) | |
1581 | size |= SZ_16K | SZ_32M; | |
1582 | if (id & ID2_PTFS_64K) | |
1583 | size |= SZ_64K | SZ_512M; | |
45ae7cff WD |
1584 | } |
1585 | ||
518f7136 WD |
1586 | arm_smmu_ops.pgsize_bitmap &= size; |
1587 | dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", size); | |
1588 | ||
28d6007b WD |
1589 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) |
1590 | dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", | |
518f7136 | 1591 | smmu->va_size, smmu->ipa_size); |
28d6007b WD |
1592 | |
1593 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) | |
1594 | dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", | |
518f7136 | 1595 | smmu->ipa_size, smmu->pa_size); |
28d6007b | 1596 | |
45ae7cff WD |
1597 | return 0; |
1598 | } | |
1599 | ||
09b5269a | 1600 | static const struct of_device_id arm_smmu_of_match[] = { |
09360403 RM |
1601 | { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 }, |
1602 | { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 }, | |
1603 | { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, | |
d3aba046 | 1604 | { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, |
09360403 RM |
1605 | { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, |
1606 | { }, | |
1607 | }; | |
1608 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
1609 | ||
45ae7cff WD |
1610 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
1611 | { | |
09360403 | 1612 | const struct of_device_id *of_id; |
45ae7cff WD |
1613 | struct resource *res; |
1614 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1615 | struct device *dev = &pdev->dev; |
1616 | struct rb_node *node; | |
1617 | struct of_phandle_args masterspec; | |
1618 | int num_irqs, i, err; | |
1619 | ||
1620 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1621 | if (!smmu) { | |
1622 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1623 | return -ENOMEM; | |
1624 | } | |
1625 | smmu->dev = dev; | |
1626 | ||
09360403 RM |
1627 | of_id = of_match_node(arm_smmu_of_match, dev->of_node); |
1628 | smmu->version = (enum arm_smmu_arch_version)of_id->data; | |
1629 | ||
45ae7cff | 1630 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8a7f4312 JL |
1631 | smmu->base = devm_ioremap_resource(dev, res); |
1632 | if (IS_ERR(smmu->base)) | |
1633 | return PTR_ERR(smmu->base); | |
45ae7cff | 1634 | smmu->size = resource_size(res); |
45ae7cff WD |
1635 | |
1636 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1637 | &smmu->num_global_irqs)) { | |
1638 | dev_err(dev, "missing #global-interrupts property\n"); | |
1639 | return -ENODEV; | |
1640 | } | |
1641 | ||
1642 | num_irqs = 0; | |
1643 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1644 | num_irqs++; | |
1645 | if (num_irqs > smmu->num_global_irqs) | |
1646 | smmu->num_context_irqs++; | |
1647 | } | |
1648 | ||
44a08de2 AH |
1649 | if (!smmu->num_context_irqs) { |
1650 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1651 | num_irqs, smmu->num_global_irqs + 1); | |
1652 | return -ENODEV; | |
45ae7cff | 1653 | } |
45ae7cff WD |
1654 | |
1655 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1656 | GFP_KERNEL); | |
1657 | if (!smmu->irqs) { | |
1658 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1659 | return -ENOMEM; | |
1660 | } | |
1661 | ||
1662 | for (i = 0; i < num_irqs; ++i) { | |
1663 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1664 | |
45ae7cff WD |
1665 | if (irq < 0) { |
1666 | dev_err(dev, "failed to get irq index %d\n", i); | |
1667 | return -ENODEV; | |
1668 | } | |
1669 | smmu->irqs[i] = irq; | |
1670 | } | |
1671 | ||
3c8766d0 OH |
1672 | err = arm_smmu_device_cfg_probe(smmu); |
1673 | if (err) | |
1674 | return err; | |
1675 | ||
45ae7cff WD |
1676 | i = 0; |
1677 | smmu->masters = RB_ROOT; | |
1678 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1679 | "#stream-id-cells", i, | |
1680 | &masterspec)) { | |
1681 | err = register_smmu_master(smmu, dev, &masterspec); | |
1682 | if (err) { | |
1683 | dev_err(dev, "failed to add master %s\n", | |
1684 | masterspec.np->name); | |
1685 | goto out_put_masters; | |
1686 | } | |
1687 | ||
1688 | i++; | |
1689 | } | |
1690 | dev_notice(dev, "registered %d master devices\n", i); | |
1691 | ||
3a5df8ff AH |
1692 | parse_driver_options(smmu); |
1693 | ||
09360403 | 1694 | if (smmu->version > ARM_SMMU_V1 && |
45ae7cff WD |
1695 | smmu->num_context_banks != smmu->num_context_irqs) { |
1696 | dev_err(dev, | |
1697 | "found only %d context interrupt(s) but %d required\n", | |
1698 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1699 | err = -ENODEV; |
44680eed | 1700 | goto out_put_masters; |
45ae7cff WD |
1701 | } |
1702 | ||
45ae7cff WD |
1703 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1704 | err = request_irq(smmu->irqs[i], | |
1705 | arm_smmu_global_fault, | |
1706 | IRQF_SHARED, | |
1707 | "arm-smmu global fault", | |
1708 | smmu); | |
1709 | if (err) { | |
1710 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1711 | i, smmu->irqs[i]); | |
1712 | goto out_free_irqs; | |
1713 | } | |
1714 | } | |
1715 | ||
1716 | INIT_LIST_HEAD(&smmu->list); | |
1717 | spin_lock(&arm_smmu_devices_lock); | |
1718 | list_add(&smmu->list, &arm_smmu_devices); | |
1719 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
1720 | |
1721 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
1722 | return 0; |
1723 | ||
1724 | out_free_irqs: | |
1725 | while (i--) | |
1726 | free_irq(smmu->irqs[i], smmu); | |
1727 | ||
45ae7cff WD |
1728 | out_put_masters: |
1729 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
1730 | struct arm_smmu_master *master |
1731 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1732 | of_node_put(master->of_node); |
1733 | } | |
1734 | ||
1735 | return err; | |
1736 | } | |
1737 | ||
1738 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
1739 | { | |
1740 | int i; | |
1741 | struct device *dev = &pdev->dev; | |
1742 | struct arm_smmu_device *curr, *smmu = NULL; | |
1743 | struct rb_node *node; | |
1744 | ||
1745 | spin_lock(&arm_smmu_devices_lock); | |
1746 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
1747 | if (curr->dev == dev) { | |
1748 | smmu = curr; | |
1749 | list_del(&smmu->list); | |
1750 | break; | |
1751 | } | |
1752 | } | |
1753 | spin_unlock(&arm_smmu_devices_lock); | |
1754 | ||
1755 | if (!smmu) | |
1756 | return -ENODEV; | |
1757 | ||
45ae7cff | 1758 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
1759 | struct arm_smmu_master *master |
1760 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
1761 | of_node_put(master->of_node); |
1762 | } | |
1763 | ||
ecfadb6e | 1764 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
1765 | dev_err(dev, "removing device with active domains!\n"); |
1766 | ||
1767 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
1768 | free_irq(smmu->irqs[i], smmu); | |
1769 | ||
1770 | /* Turn the thing off */ | |
2907320d | 1771 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1772 | return 0; |
1773 | } | |
1774 | ||
45ae7cff WD |
1775 | static struct platform_driver arm_smmu_driver = { |
1776 | .driver = { | |
45ae7cff WD |
1777 | .name = "arm-smmu", |
1778 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
1779 | }, | |
1780 | .probe = arm_smmu_device_dt_probe, | |
1781 | .remove = arm_smmu_device_remove, | |
1782 | }; | |
1783 | ||
1784 | static int __init arm_smmu_init(void) | |
1785 | { | |
0e7d37ad | 1786 | struct device_node *np; |
45ae7cff WD |
1787 | int ret; |
1788 | ||
0e7d37ad TR |
1789 | /* |
1790 | * Play nice with systems that don't have an ARM SMMU by checking that | |
1791 | * an ARM SMMU exists in the system before proceeding with the driver | |
1792 | * and IOMMU bus operation registration. | |
1793 | */ | |
1794 | np = of_find_matching_node(NULL, arm_smmu_of_match); | |
1795 | if (!np) | |
1796 | return 0; | |
1797 | ||
1798 | of_node_put(np); | |
1799 | ||
45ae7cff WD |
1800 | ret = platform_driver_register(&arm_smmu_driver); |
1801 | if (ret) | |
1802 | return ret; | |
1803 | ||
1804 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 1805 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
1806 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
1807 | ||
d123cf82 | 1808 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 1809 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 1810 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 1811 | #endif |
45ae7cff | 1812 | |
a9a1b0b5 WD |
1813 | #ifdef CONFIG_PCI |
1814 | if (!iommu_present(&pci_bus_type)) | |
1815 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
1816 | #endif | |
1817 | ||
45ae7cff WD |
1818 | return 0; |
1819 | } | |
1820 | ||
1821 | static void __exit arm_smmu_exit(void) | |
1822 | { | |
1823 | return platform_driver_unregister(&arm_smmu_driver); | |
1824 | } | |
1825 | ||
b1950b27 | 1826 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
1827 | module_exit(arm_smmu_exit); |
1828 | ||
1829 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
1830 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
1831 | MODULE_LICENSE("GPL v2"); |