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45ae7cff WD |
1 | /* |
2 | * IOMMU API for ARM architected SMMU implementations. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
16 | * | |
17 | * Copyright (C) 2013 ARM Limited | |
18 | * | |
19 | * Author: Will Deacon <will.deacon@arm.com> | |
20 | * | |
21 | * This driver currently supports: | |
22 | * - SMMUv1 and v2 implementations | |
23 | * - Stream-matching and stream-indexing | |
24 | * - v7/v8 long-descriptor format | |
25 | * - Non-secure access to the SMMU | |
26 | * - 4k and 64k pages, with contiguous pte hints. | |
28d6007b | 27 | * - Up to 48-bit addressing (dependent on VA_BITS) |
45ae7cff WD |
28 | * - Context fault reporting |
29 | */ | |
30 | ||
31 | #define pr_fmt(fmt) "arm-smmu: " fmt | |
32 | ||
33 | #include <linux/delay.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/err.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/iommu.h> | |
39 | #include <linux/mm.h> | |
40 | #include <linux/module.h> | |
41 | #include <linux/of.h> | |
a9a1b0b5 | 42 | #include <linux/pci.h> |
45ae7cff WD |
43 | #include <linux/platform_device.h> |
44 | #include <linux/slab.h> | |
45 | #include <linux/spinlock.h> | |
46 | ||
47 | #include <linux/amba/bus.h> | |
48 | ||
49 | #include <asm/pgalloc.h> | |
50 | ||
51 | /* Maximum number of stream IDs assigned to a single device */ | |
636e97b0 | 52 | #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS |
45ae7cff WD |
53 | |
54 | /* Maximum number of context banks per SMMU */ | |
55 | #define ARM_SMMU_MAX_CBS 128 | |
56 | ||
57 | /* Maximum number of mapping groups per SMMU */ | |
58 | #define ARM_SMMU_MAX_SMRS 128 | |
59 | ||
45ae7cff WD |
60 | /* SMMU global address space */ |
61 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) | |
c757e852 | 62 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift)) |
45ae7cff | 63 | |
3a5df8ff AH |
64 | /* |
65 | * SMMU global address space with conditional offset to access secure | |
66 | * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448, | |
67 | * nsGFSYNR0: 0x450) | |
68 | */ | |
69 | #define ARM_SMMU_GR0_NS(smmu) \ | |
70 | ((smmu)->base + \ | |
71 | ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \ | |
72 | ? 0x400 : 0)) | |
73 | ||
45ae7cff | 74 | /* Page table bits */ |
cf2d45b1 | 75 | #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53) |
45ae7cff WD |
76 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
77 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) | |
78 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) | |
79 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) | |
80 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) | |
cf2d45b1 | 81 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
45ae7cff WD |
82 | |
83 | #if PAGE_SIZE == SZ_4K | |
84 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 | |
85 | #elif PAGE_SIZE == SZ_64K | |
86 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 | |
87 | #else | |
88 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 | |
89 | #endif | |
90 | ||
91 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) | |
92 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) | |
45ae7cff WD |
93 | |
94 | /* Stage-1 PTE */ | |
95 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) | |
96 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) | |
97 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 | |
1463fe44 | 98 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
45ae7cff WD |
99 | |
100 | /* Stage-2 PTE */ | |
101 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) | |
102 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) | |
103 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) | |
104 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) | |
105 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) | |
106 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) | |
107 | ||
108 | /* Configuration registers */ | |
109 | #define ARM_SMMU_GR0_sCR0 0x0 | |
110 | #define sCR0_CLIENTPD (1 << 0) | |
111 | #define sCR0_GFRE (1 << 1) | |
112 | #define sCR0_GFIE (1 << 2) | |
113 | #define sCR0_GCFGFRE (1 << 4) | |
114 | #define sCR0_GCFGFIE (1 << 5) | |
115 | #define sCR0_USFCFG (1 << 10) | |
116 | #define sCR0_VMIDPNE (1 << 11) | |
117 | #define sCR0_PTM (1 << 12) | |
118 | #define sCR0_FB (1 << 13) | |
119 | #define sCR0_BSU_SHIFT 14 | |
120 | #define sCR0_BSU_MASK 0x3 | |
121 | ||
122 | /* Identification registers */ | |
123 | #define ARM_SMMU_GR0_ID0 0x20 | |
124 | #define ARM_SMMU_GR0_ID1 0x24 | |
125 | #define ARM_SMMU_GR0_ID2 0x28 | |
126 | #define ARM_SMMU_GR0_ID3 0x2c | |
127 | #define ARM_SMMU_GR0_ID4 0x30 | |
128 | #define ARM_SMMU_GR0_ID5 0x34 | |
129 | #define ARM_SMMU_GR0_ID6 0x38 | |
130 | #define ARM_SMMU_GR0_ID7 0x3c | |
131 | #define ARM_SMMU_GR0_sGFSR 0x48 | |
132 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 | |
133 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 | |
134 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 | |
135 | #define ARM_SMMU_GR0_PIDR0 0xfe0 | |
136 | #define ARM_SMMU_GR0_PIDR1 0xfe4 | |
137 | #define ARM_SMMU_GR0_PIDR2 0xfe8 | |
138 | ||
139 | #define ID0_S1TS (1 << 30) | |
140 | #define ID0_S2TS (1 << 29) | |
141 | #define ID0_NTS (1 << 28) | |
142 | #define ID0_SMS (1 << 27) | |
143 | #define ID0_PTFS_SHIFT 24 | |
144 | #define ID0_PTFS_MASK 0x2 | |
145 | #define ID0_PTFS_V8_ONLY 0x2 | |
146 | #define ID0_CTTW (1 << 14) | |
147 | #define ID0_NUMIRPT_SHIFT 16 | |
148 | #define ID0_NUMIRPT_MASK 0xff | |
3c8766d0 OH |
149 | #define ID0_NUMSIDB_SHIFT 9 |
150 | #define ID0_NUMSIDB_MASK 0xf | |
45ae7cff WD |
151 | #define ID0_NUMSMRG_SHIFT 0 |
152 | #define ID0_NUMSMRG_MASK 0xff | |
153 | ||
154 | #define ID1_PAGESIZE (1 << 31) | |
155 | #define ID1_NUMPAGENDXB_SHIFT 28 | |
156 | #define ID1_NUMPAGENDXB_MASK 7 | |
157 | #define ID1_NUMS2CB_SHIFT 16 | |
158 | #define ID1_NUMS2CB_MASK 0xff | |
159 | #define ID1_NUMCB_SHIFT 0 | |
160 | #define ID1_NUMCB_MASK 0xff | |
161 | ||
162 | #define ID2_OAS_SHIFT 4 | |
163 | #define ID2_OAS_MASK 0xf | |
164 | #define ID2_IAS_SHIFT 0 | |
165 | #define ID2_IAS_MASK 0xf | |
166 | #define ID2_UBS_SHIFT 8 | |
167 | #define ID2_UBS_MASK 0xf | |
168 | #define ID2_PTFS_4K (1 << 12) | |
169 | #define ID2_PTFS_16K (1 << 13) | |
170 | #define ID2_PTFS_64K (1 << 14) | |
171 | ||
172 | #define PIDR2_ARCH_SHIFT 4 | |
173 | #define PIDR2_ARCH_MASK 0xf | |
174 | ||
175 | /* Global TLB invalidation */ | |
176 | #define ARM_SMMU_GR0_STLBIALL 0x60 | |
177 | #define ARM_SMMU_GR0_TLBIVMID 0x64 | |
178 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 | |
179 | #define ARM_SMMU_GR0_TLBIALLH 0x6c | |
180 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 | |
181 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 | |
182 | #define sTLBGSTATUS_GSACTIVE (1 << 0) | |
183 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ | |
184 | ||
185 | /* Stream mapping registers */ | |
186 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) | |
187 | #define SMR_VALID (1 << 31) | |
188 | #define SMR_MASK_SHIFT 16 | |
189 | #define SMR_MASK_MASK 0x7fff | |
190 | #define SMR_ID_SHIFT 0 | |
191 | #define SMR_ID_MASK 0x7fff | |
192 | ||
193 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) | |
194 | #define S2CR_CBNDX_SHIFT 0 | |
195 | #define S2CR_CBNDX_MASK 0xff | |
196 | #define S2CR_TYPE_SHIFT 16 | |
197 | #define S2CR_TYPE_MASK 0x3 | |
198 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) | |
199 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) | |
200 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) | |
201 | ||
202 | /* Context bank attribute registers */ | |
203 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) | |
204 | #define CBAR_VMID_SHIFT 0 | |
205 | #define CBAR_VMID_MASK 0xff | |
57ca90f6 WD |
206 | #define CBAR_S1_BPSHCFG_SHIFT 8 |
207 | #define CBAR_S1_BPSHCFG_MASK 3 | |
208 | #define CBAR_S1_BPSHCFG_NSH 3 | |
45ae7cff WD |
209 | #define CBAR_S1_MEMATTR_SHIFT 12 |
210 | #define CBAR_S1_MEMATTR_MASK 0xf | |
211 | #define CBAR_S1_MEMATTR_WB 0xf | |
212 | #define CBAR_TYPE_SHIFT 16 | |
213 | #define CBAR_TYPE_MASK 0x3 | |
214 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) | |
215 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) | |
216 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) | |
217 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) | |
218 | #define CBAR_IRPTNDX_SHIFT 24 | |
219 | #define CBAR_IRPTNDX_MASK 0xff | |
220 | ||
221 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) | |
222 | #define CBA2R_RW64_32BIT (0 << 0) | |
223 | #define CBA2R_RW64_64BIT (1 << 0) | |
224 | ||
225 | /* Translation context bank */ | |
226 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) | |
c757e852 | 227 | #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift)) |
45ae7cff WD |
228 | |
229 | #define ARM_SMMU_CB_SCTLR 0x0 | |
230 | #define ARM_SMMU_CB_RESUME 0x8 | |
231 | #define ARM_SMMU_CB_TTBCR2 0x10 | |
232 | #define ARM_SMMU_CB_TTBR0_LO 0x20 | |
233 | #define ARM_SMMU_CB_TTBR0_HI 0x24 | |
234 | #define ARM_SMMU_CB_TTBCR 0x30 | |
235 | #define ARM_SMMU_CB_S1_MAIR0 0x38 | |
236 | #define ARM_SMMU_CB_FSR 0x58 | |
237 | #define ARM_SMMU_CB_FAR_LO 0x60 | |
238 | #define ARM_SMMU_CB_FAR_HI 0x64 | |
239 | #define ARM_SMMU_CB_FSYNR0 0x68 | |
1463fe44 | 240 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
45ae7cff WD |
241 | |
242 | #define SCTLR_S1_ASIDPNE (1 << 12) | |
243 | #define SCTLR_CFCFG (1 << 7) | |
244 | #define SCTLR_CFIE (1 << 6) | |
245 | #define SCTLR_CFRE (1 << 5) | |
246 | #define SCTLR_E (1 << 4) | |
247 | #define SCTLR_AFE (1 << 2) | |
248 | #define SCTLR_TRE (1 << 1) | |
249 | #define SCTLR_M (1 << 0) | |
250 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) | |
251 | ||
252 | #define RESUME_RETRY (0 << 0) | |
253 | #define RESUME_TERMINATE (1 << 0) | |
254 | ||
255 | #define TTBCR_EAE (1 << 31) | |
256 | ||
257 | #define TTBCR_PASIZE_SHIFT 16 | |
258 | #define TTBCR_PASIZE_MASK 0x7 | |
259 | ||
260 | #define TTBCR_TG0_4K (0 << 14) | |
261 | #define TTBCR_TG0_64K (1 << 14) | |
262 | ||
263 | #define TTBCR_SH0_SHIFT 12 | |
264 | #define TTBCR_SH0_MASK 0x3 | |
265 | #define TTBCR_SH_NS 0 | |
266 | #define TTBCR_SH_OS 2 | |
267 | #define TTBCR_SH_IS 3 | |
268 | ||
269 | #define TTBCR_ORGN0_SHIFT 10 | |
270 | #define TTBCR_IRGN0_SHIFT 8 | |
271 | #define TTBCR_RGN_MASK 0x3 | |
272 | #define TTBCR_RGN_NC 0 | |
273 | #define TTBCR_RGN_WBWA 1 | |
274 | #define TTBCR_RGN_WT 2 | |
275 | #define TTBCR_RGN_WB 3 | |
276 | ||
277 | #define TTBCR_SL0_SHIFT 6 | |
278 | #define TTBCR_SL0_MASK 0x3 | |
279 | #define TTBCR_SL0_LVL_2 0 | |
280 | #define TTBCR_SL0_LVL_1 1 | |
281 | ||
282 | #define TTBCR_T1SZ_SHIFT 16 | |
283 | #define TTBCR_T0SZ_SHIFT 0 | |
284 | #define TTBCR_SZ_MASK 0xf | |
285 | ||
286 | #define TTBCR2_SEP_SHIFT 15 | |
287 | #define TTBCR2_SEP_MASK 0x7 | |
288 | ||
289 | #define TTBCR2_PASIZE_SHIFT 0 | |
290 | #define TTBCR2_PASIZE_MASK 0x7 | |
291 | ||
292 | /* Common definitions for PASize and SEP fields */ | |
293 | #define TTBCR2_ADDR_32 0 | |
294 | #define TTBCR2_ADDR_36 1 | |
295 | #define TTBCR2_ADDR_40 2 | |
296 | #define TTBCR2_ADDR_42 3 | |
297 | #define TTBCR2_ADDR_44 4 | |
298 | #define TTBCR2_ADDR_48 5 | |
299 | ||
1463fe44 WD |
300 | #define TTBRn_HI_ASID_SHIFT 16 |
301 | ||
45ae7cff WD |
302 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
303 | #define MAIR_ATTR_MASK 0xff | |
304 | #define MAIR_ATTR_DEVICE 0x04 | |
305 | #define MAIR_ATTR_NC 0x44 | |
306 | #define MAIR_ATTR_WBRWA 0xff | |
307 | #define MAIR_ATTR_IDX_NC 0 | |
308 | #define MAIR_ATTR_IDX_CACHE 1 | |
309 | #define MAIR_ATTR_IDX_DEV 2 | |
310 | ||
311 | #define FSR_MULTI (1 << 31) | |
312 | #define FSR_SS (1 << 30) | |
313 | #define FSR_UUT (1 << 8) | |
314 | #define FSR_ASF (1 << 7) | |
315 | #define FSR_TLBLKF (1 << 6) | |
316 | #define FSR_TLBMCF (1 << 5) | |
317 | #define FSR_EF (1 << 4) | |
318 | #define FSR_PF (1 << 3) | |
319 | #define FSR_AFF (1 << 2) | |
320 | #define FSR_TF (1 << 1) | |
321 | ||
2907320d MH |
322 | #define FSR_IGN (FSR_AFF | FSR_ASF | \ |
323 | FSR_TLBMCF | FSR_TLBLKF) | |
324 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ | |
adaba320 | 325 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
45ae7cff WD |
326 | |
327 | #define FSYNR0_WNR (1 << 4) | |
328 | ||
4cf740b0 WD |
329 | static int force_stage; |
330 | module_param_named(force_stage, force_stage, int, S_IRUGO | S_IWUSR); | |
331 | MODULE_PARM_DESC(force_stage, | |
332 | "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation."); | |
333 | ||
09360403 RM |
334 | enum arm_smmu_arch_version { |
335 | ARM_SMMU_V1 = 1, | |
336 | ARM_SMMU_V2, | |
337 | }; | |
338 | ||
45ae7cff WD |
339 | struct arm_smmu_smr { |
340 | u8 idx; | |
341 | u16 mask; | |
342 | u16 id; | |
343 | }; | |
344 | ||
a9a1b0b5 | 345 | struct arm_smmu_master_cfg { |
45ae7cff WD |
346 | int num_streamids; |
347 | u16 streamids[MAX_MASTER_STREAMIDS]; | |
45ae7cff WD |
348 | struct arm_smmu_smr *smrs; |
349 | }; | |
350 | ||
a9a1b0b5 WD |
351 | struct arm_smmu_master { |
352 | struct device_node *of_node; | |
a9a1b0b5 WD |
353 | struct rb_node node; |
354 | struct arm_smmu_master_cfg cfg; | |
355 | }; | |
356 | ||
45ae7cff WD |
357 | struct arm_smmu_device { |
358 | struct device *dev; | |
45ae7cff WD |
359 | |
360 | void __iomem *base; | |
361 | unsigned long size; | |
c757e852 | 362 | unsigned long pgshift; |
45ae7cff WD |
363 | |
364 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) | |
365 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) | |
366 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) | |
367 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) | |
368 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) | |
369 | u32 features; | |
3a5df8ff AH |
370 | |
371 | #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0) | |
372 | u32 options; | |
09360403 | 373 | enum arm_smmu_arch_version version; |
45ae7cff WD |
374 | |
375 | u32 num_context_banks; | |
376 | u32 num_s2_context_banks; | |
377 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); | |
378 | atomic_t irptndx; | |
379 | ||
380 | u32 num_mapping_groups; | |
381 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); | |
382 | ||
28d6007b | 383 | unsigned long s1_input_size; |
45ae7cff | 384 | unsigned long s1_output_size; |
28d6007b | 385 | unsigned long s2_input_size; |
45ae7cff WD |
386 | unsigned long s2_output_size; |
387 | ||
388 | u32 num_global_irqs; | |
389 | u32 num_context_irqs; | |
390 | unsigned int *irqs; | |
391 | ||
45ae7cff WD |
392 | struct list_head list; |
393 | struct rb_root masters; | |
394 | }; | |
395 | ||
396 | struct arm_smmu_cfg { | |
45ae7cff WD |
397 | u8 cbndx; |
398 | u8 irptndx; | |
399 | u32 cbar; | |
400 | pgd_t *pgd; | |
401 | }; | |
faea13b7 | 402 | #define INVALID_IRPTNDX 0xff |
45ae7cff | 403 | |
ecfadb6e WD |
404 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
405 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) | |
406 | ||
45ae7cff | 407 | struct arm_smmu_domain { |
44680eed WD |
408 | struct arm_smmu_device *smmu; |
409 | struct arm_smmu_cfg cfg; | |
c9d09e27 | 410 | spinlock_t lock; |
45ae7cff WD |
411 | }; |
412 | ||
413 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); | |
414 | static LIST_HEAD(arm_smmu_devices); | |
415 | ||
3a5df8ff AH |
416 | struct arm_smmu_option_prop { |
417 | u32 opt; | |
418 | const char *prop; | |
419 | }; | |
420 | ||
2907320d | 421 | static struct arm_smmu_option_prop arm_smmu_options[] = { |
3a5df8ff AH |
422 | { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" }, |
423 | { 0, NULL}, | |
424 | }; | |
425 | ||
426 | static void parse_driver_options(struct arm_smmu_device *smmu) | |
427 | { | |
428 | int i = 0; | |
2907320d | 429 | |
3a5df8ff AH |
430 | do { |
431 | if (of_property_read_bool(smmu->dev->of_node, | |
432 | arm_smmu_options[i].prop)) { | |
433 | smmu->options |= arm_smmu_options[i].opt; | |
434 | dev_notice(smmu->dev, "option %s\n", | |
435 | arm_smmu_options[i].prop); | |
436 | } | |
437 | } while (arm_smmu_options[++i].opt); | |
438 | } | |
439 | ||
8f68f8e2 | 440 | static struct device_node *dev_get_dev_node(struct device *dev) |
a9a1b0b5 WD |
441 | { |
442 | if (dev_is_pci(dev)) { | |
443 | struct pci_bus *bus = to_pci_dev(dev)->bus; | |
2907320d | 444 | |
a9a1b0b5 WD |
445 | while (!pci_is_root_bus(bus)) |
446 | bus = bus->parent; | |
8f68f8e2 | 447 | return bus->bridge->parent->of_node; |
a9a1b0b5 WD |
448 | } |
449 | ||
8f68f8e2 | 450 | return dev->of_node; |
a9a1b0b5 WD |
451 | } |
452 | ||
45ae7cff WD |
453 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
454 | struct device_node *dev_node) | |
455 | { | |
456 | struct rb_node *node = smmu->masters.rb_node; | |
457 | ||
458 | while (node) { | |
459 | struct arm_smmu_master *master; | |
2907320d | 460 | |
45ae7cff WD |
461 | master = container_of(node, struct arm_smmu_master, node); |
462 | ||
463 | if (dev_node < master->of_node) | |
464 | node = node->rb_left; | |
465 | else if (dev_node > master->of_node) | |
466 | node = node->rb_right; | |
467 | else | |
468 | return master; | |
469 | } | |
470 | ||
471 | return NULL; | |
472 | } | |
473 | ||
a9a1b0b5 | 474 | static struct arm_smmu_master_cfg * |
8f68f8e2 | 475 | find_smmu_master_cfg(struct device *dev) |
a9a1b0b5 | 476 | { |
8f68f8e2 WD |
477 | struct arm_smmu_master_cfg *cfg = NULL; |
478 | struct iommu_group *group = iommu_group_get(dev); | |
a9a1b0b5 | 479 | |
8f68f8e2 WD |
480 | if (group) { |
481 | cfg = iommu_group_get_iommudata(group); | |
482 | iommu_group_put(group); | |
483 | } | |
a9a1b0b5 | 484 | |
8f68f8e2 | 485 | return cfg; |
a9a1b0b5 WD |
486 | } |
487 | ||
45ae7cff WD |
488 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
489 | struct arm_smmu_master *master) | |
490 | { | |
491 | struct rb_node **new, *parent; | |
492 | ||
493 | new = &smmu->masters.rb_node; | |
494 | parent = NULL; | |
495 | while (*new) { | |
2907320d MH |
496 | struct arm_smmu_master *this |
497 | = container_of(*new, struct arm_smmu_master, node); | |
45ae7cff WD |
498 | |
499 | parent = *new; | |
500 | if (master->of_node < this->of_node) | |
501 | new = &((*new)->rb_left); | |
502 | else if (master->of_node > this->of_node) | |
503 | new = &((*new)->rb_right); | |
504 | else | |
505 | return -EEXIST; | |
506 | } | |
507 | ||
508 | rb_link_node(&master->node, parent, new); | |
509 | rb_insert_color(&master->node, &smmu->masters); | |
510 | return 0; | |
511 | } | |
512 | ||
513 | static int register_smmu_master(struct arm_smmu_device *smmu, | |
514 | struct device *dev, | |
515 | struct of_phandle_args *masterspec) | |
516 | { | |
517 | int i; | |
518 | struct arm_smmu_master *master; | |
519 | ||
520 | master = find_smmu_master(smmu, masterspec->np); | |
521 | if (master) { | |
522 | dev_err(dev, | |
523 | "rejecting multiple registrations for master device %s\n", | |
524 | masterspec->np->name); | |
525 | return -EBUSY; | |
526 | } | |
527 | ||
528 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { | |
529 | dev_err(dev, | |
530 | "reached maximum number (%d) of stream IDs for master device %s\n", | |
531 | MAX_MASTER_STREAMIDS, masterspec->np->name); | |
532 | return -ENOSPC; | |
533 | } | |
534 | ||
535 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); | |
536 | if (!master) | |
537 | return -ENOMEM; | |
538 | ||
a9a1b0b5 WD |
539 | master->of_node = masterspec->np; |
540 | master->cfg.num_streamids = masterspec->args_count; | |
45ae7cff | 541 | |
3c8766d0 OH |
542 | for (i = 0; i < master->cfg.num_streamids; ++i) { |
543 | u16 streamid = masterspec->args[i]; | |
45ae7cff | 544 | |
3c8766d0 OH |
545 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && |
546 | (streamid >= smmu->num_mapping_groups)) { | |
547 | dev_err(dev, | |
548 | "stream ID for master device %s greater than maximum allowed (%d)\n", | |
549 | masterspec->np->name, smmu->num_mapping_groups); | |
550 | return -ERANGE; | |
551 | } | |
552 | master->cfg.streamids[i] = streamid; | |
553 | } | |
45ae7cff WD |
554 | return insert_smmu_master(smmu, master); |
555 | } | |
556 | ||
44680eed | 557 | static struct arm_smmu_device *find_smmu_for_device(struct device *dev) |
45ae7cff | 558 | { |
44680eed | 559 | struct arm_smmu_device *smmu; |
a9a1b0b5 | 560 | struct arm_smmu_master *master = NULL; |
8f68f8e2 | 561 | struct device_node *dev_node = dev_get_dev_node(dev); |
45ae7cff WD |
562 | |
563 | spin_lock(&arm_smmu_devices_lock); | |
44680eed | 564 | list_for_each_entry(smmu, &arm_smmu_devices, list) { |
a9a1b0b5 WD |
565 | master = find_smmu_master(smmu, dev_node); |
566 | if (master) | |
567 | break; | |
568 | } | |
45ae7cff | 569 | spin_unlock(&arm_smmu_devices_lock); |
44680eed | 570 | |
a9a1b0b5 | 571 | return master ? smmu : NULL; |
45ae7cff WD |
572 | } |
573 | ||
574 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) | |
575 | { | |
576 | int idx; | |
577 | ||
578 | do { | |
579 | idx = find_next_zero_bit(map, end, start); | |
580 | if (idx == end) | |
581 | return -ENOSPC; | |
582 | } while (test_and_set_bit(idx, map)); | |
583 | ||
584 | return idx; | |
585 | } | |
586 | ||
587 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) | |
588 | { | |
589 | clear_bit(idx, map); | |
590 | } | |
591 | ||
592 | /* Wait for any pending TLB invalidations to complete */ | |
593 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) | |
594 | { | |
595 | int count = 0; | |
596 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
597 | ||
598 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); | |
599 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) | |
600 | & sTLBGSTATUS_GSACTIVE) { | |
601 | cpu_relax(); | |
602 | if (++count == TLB_LOOP_TIMEOUT) { | |
603 | dev_err_ratelimited(smmu->dev, | |
604 | "TLB sync timed out -- SMMU may be deadlocked\n"); | |
605 | return; | |
606 | } | |
607 | udelay(1); | |
608 | } | |
609 | } | |
610 | ||
44680eed | 611 | static void arm_smmu_tlb_inv_context(struct arm_smmu_domain *smmu_domain) |
1463fe44 | 612 | { |
44680eed WD |
613 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
614 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
1463fe44 WD |
615 | void __iomem *base = ARM_SMMU_GR0(smmu); |
616 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; | |
617 | ||
618 | if (stage1) { | |
619 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
ecfadb6e WD |
620 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
621 | base + ARM_SMMU_CB_S1_TLBIASID); | |
1463fe44 WD |
622 | } else { |
623 | base = ARM_SMMU_GR0(smmu); | |
ecfadb6e WD |
624 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
625 | base + ARM_SMMU_GR0_TLBIVMID); | |
1463fe44 WD |
626 | } |
627 | ||
628 | arm_smmu_tlb_sync(smmu); | |
629 | } | |
630 | ||
45ae7cff WD |
631 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
632 | { | |
633 | int flags, ret; | |
634 | u32 fsr, far, fsynr, resume; | |
635 | unsigned long iova; | |
636 | struct iommu_domain *domain = dev; | |
637 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
638 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
639 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
640 | void __iomem *cb_base; |
641 | ||
44680eed | 642 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
45ae7cff WD |
643 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
644 | ||
645 | if (!(fsr & FSR_FAULT)) | |
646 | return IRQ_NONE; | |
647 | ||
648 | if (fsr & FSR_IGN) | |
649 | dev_err_ratelimited(smmu->dev, | |
70c9a7db | 650 | "Unexpected context fault (fsr 0x%x)\n", |
45ae7cff WD |
651 | fsr); |
652 | ||
653 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); | |
654 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; | |
655 | ||
656 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); | |
657 | iova = far; | |
658 | #ifdef CONFIG_64BIT | |
659 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); | |
660 | iova |= ((unsigned long)far << 32); | |
661 | #endif | |
662 | ||
663 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { | |
664 | ret = IRQ_HANDLED; | |
665 | resume = RESUME_RETRY; | |
666 | } else { | |
2ef0f031 AH |
667 | dev_err_ratelimited(smmu->dev, |
668 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", | |
44680eed | 669 | iova, fsynr, cfg->cbndx); |
45ae7cff WD |
670 | ret = IRQ_NONE; |
671 | resume = RESUME_TERMINATE; | |
672 | } | |
673 | ||
674 | /* Clear the faulting FSR */ | |
675 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); | |
676 | ||
677 | /* Retry or terminate any stalled transactions */ | |
678 | if (fsr & FSR_SS) | |
679 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); | |
680 | ||
681 | return ret; | |
682 | } | |
683 | ||
684 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) | |
685 | { | |
686 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; | |
687 | struct arm_smmu_device *smmu = dev; | |
3a5df8ff | 688 | void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); |
45ae7cff WD |
689 | |
690 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); | |
691 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); | |
692 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); | |
693 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); | |
694 | ||
3a5df8ff AH |
695 | if (!gfsr) |
696 | return IRQ_NONE; | |
697 | ||
45ae7cff WD |
698 | dev_err_ratelimited(smmu->dev, |
699 | "Unexpected global fault, this could be serious\n"); | |
700 | dev_err_ratelimited(smmu->dev, | |
701 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", | |
702 | gfsr, gfsynr0, gfsynr1, gfsynr2); | |
703 | ||
704 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); | |
adaba320 | 705 | return IRQ_HANDLED; |
45ae7cff WD |
706 | } |
707 | ||
6dd35f45 WD |
708 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
709 | size_t size) | |
710 | { | |
711 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; | |
712 | ||
713 | ||
714 | /* Ensure new page tables are visible to the hardware walker */ | |
715 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) { | |
3aa80ea4 | 716 | dsb(ishst); |
6dd35f45 WD |
717 | } else { |
718 | /* | |
719 | * If the SMMU can't walk tables in the CPU caches, treat them | |
720 | * like non-coherent DMA since we need to flush the new entries | |
721 | * all the way out to memory. There's no possibility of | |
722 | * recursion here as the SMMU table walker will not be wired | |
723 | * through another SMMU. | |
724 | */ | |
725 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, | |
726 | DMA_TO_DEVICE); | |
727 | } | |
728 | } | |
729 | ||
45ae7cff WD |
730 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
731 | { | |
732 | u32 reg; | |
733 | bool stage1; | |
44680eed WD |
734 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
735 | struct arm_smmu_device *smmu = smmu_domain->smmu; | |
45ae7cff WD |
736 | void __iomem *cb_base, *gr0_base, *gr1_base; |
737 | ||
738 | gr0_base = ARM_SMMU_GR0(smmu); | |
739 | gr1_base = ARM_SMMU_GR1(smmu); | |
44680eed WD |
740 | stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
741 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); | |
45ae7cff WD |
742 | |
743 | /* CBAR */ | |
44680eed | 744 | reg = cfg->cbar; |
09360403 | 745 | if (smmu->version == ARM_SMMU_V1) |
2907320d | 746 | reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
45ae7cff | 747 | |
57ca90f6 WD |
748 | /* |
749 | * Use the weakest shareability/memory types, so they are | |
750 | * overridden by the ttbcr/pte. | |
751 | */ | |
752 | if (stage1) { | |
753 | reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) | | |
754 | (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); | |
755 | } else { | |
44680eed | 756 | reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; |
57ca90f6 | 757 | } |
44680eed | 758 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); |
45ae7cff | 759 | |
09360403 | 760 | if (smmu->version > ARM_SMMU_V1) { |
45ae7cff WD |
761 | /* CBA2R */ |
762 | #ifdef CONFIG_64BIT | |
763 | reg = CBA2R_RW64_64BIT; | |
764 | #else | |
765 | reg = CBA2R_RW64_32BIT; | |
766 | #endif | |
767 | writel_relaxed(reg, | |
44680eed | 768 | gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); |
45ae7cff WD |
769 | |
770 | /* TTBCR2 */ | |
28d6007b | 771 | switch (smmu->s1_input_size) { |
45ae7cff WD |
772 | case 32: |
773 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); | |
774 | break; | |
775 | case 36: | |
776 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); | |
777 | break; | |
778 | case 39: | |
4d09d99d | 779 | case 40: |
45ae7cff WD |
780 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
781 | break; | |
782 | case 42: | |
783 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); | |
784 | break; | |
785 | case 44: | |
786 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); | |
787 | break; | |
788 | case 48: | |
789 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); | |
790 | break; | |
791 | } | |
792 | ||
793 | switch (smmu->s1_output_size) { | |
794 | case 32: | |
795 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); | |
796 | break; | |
797 | case 36: | |
798 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); | |
799 | break; | |
800 | case 39: | |
4d09d99d | 801 | case 40: |
45ae7cff WD |
802 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); |
803 | break; | |
804 | case 42: | |
805 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); | |
806 | break; | |
807 | case 44: | |
808 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); | |
809 | break; | |
810 | case 48: | |
811 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); | |
812 | break; | |
813 | } | |
814 | ||
815 | if (stage1) | |
816 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); | |
817 | } | |
818 | ||
819 | /* TTBR0 */ | |
44680eed | 820 | arm_smmu_flush_pgtable(smmu, cfg->pgd, |
6dd35f45 | 821 | PTRS_PER_PGD * sizeof(pgd_t)); |
44680eed | 822 | reg = __pa(cfg->pgd); |
45ae7cff | 823 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
44680eed | 824 | reg = (phys_addr_t)__pa(cfg->pgd) >> 32; |
1463fe44 | 825 | if (stage1) |
44680eed | 826 | reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; |
45ae7cff | 827 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
45ae7cff WD |
828 | |
829 | /* | |
830 | * TTBCR | |
831 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. | |
832 | */ | |
09360403 | 833 | if (smmu->version > ARM_SMMU_V1) { |
45ae7cff WD |
834 | if (PAGE_SIZE == SZ_4K) |
835 | reg = TTBCR_TG0_4K; | |
836 | else | |
837 | reg = TTBCR_TG0_64K; | |
838 | ||
839 | if (!stage1) { | |
28d6007b | 840 | reg |= (64 - smmu->s2_input_size) << TTBCR_T0SZ_SHIFT; |
a65217a4 | 841 | |
45ae7cff WD |
842 | switch (smmu->s2_output_size) { |
843 | case 32: | |
844 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); | |
845 | break; | |
846 | case 36: | |
847 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); | |
848 | break; | |
849 | case 40: | |
850 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); | |
851 | break; | |
852 | case 42: | |
853 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); | |
854 | break; | |
855 | case 44: | |
856 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); | |
857 | break; | |
858 | case 48: | |
859 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); | |
860 | break; | |
861 | } | |
862 | } else { | |
28d6007b | 863 | reg |= (64 - smmu->s1_input_size) << TTBCR_T0SZ_SHIFT; |
45ae7cff WD |
864 | } |
865 | } else { | |
866 | reg = 0; | |
867 | } | |
868 | ||
869 | reg |= TTBCR_EAE | | |
870 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | | |
871 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | | |
1fc870c7 OH |
872 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT); |
873 | ||
874 | if (!stage1) | |
875 | reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); | |
876 | ||
45ae7cff WD |
877 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
878 | ||
879 | /* MAIR0 (stage-1 only) */ | |
880 | if (stage1) { | |
881 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | | |
882 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | | |
883 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); | |
884 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); | |
885 | } | |
886 | ||
45ae7cff WD |
887 | /* SCTLR */ |
888 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; | |
889 | if (stage1) | |
890 | reg |= SCTLR_S1_ASIDPNE; | |
891 | #ifdef __BIG_ENDIAN | |
892 | reg |= SCTLR_E; | |
893 | #endif | |
25724841 | 894 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
45ae7cff WD |
895 | } |
896 | ||
897 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, | |
44680eed | 898 | struct arm_smmu_device *smmu) |
45ae7cff | 899 | { |
a18037b2 MH |
900 | int irq, start, ret = 0; |
901 | unsigned long flags; | |
45ae7cff | 902 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 903 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 904 | |
a18037b2 MH |
905 | spin_lock_irqsave(&smmu_domain->lock, flags); |
906 | if (smmu_domain->smmu) | |
907 | goto out_unlock; | |
908 | ||
45ae7cff WD |
909 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
910 | /* | |
911 | * We will likely want to change this if/when KVM gets | |
912 | * involved. | |
913 | */ | |
44680eed | 914 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 915 | start = smmu->num_s2_context_banks; |
9c5c92e3 | 916 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) { |
44680eed | 917 | cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
45ae7cff | 918 | start = smmu->num_s2_context_banks; |
9c5c92e3 WD |
919 | } else { |
920 | cfg->cbar = CBAR_TYPE_S2_TRANS; | |
921 | start = 0; | |
45ae7cff WD |
922 | } |
923 | ||
924 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, | |
925 | smmu->num_context_banks); | |
926 | if (IS_ERR_VALUE(ret)) | |
a18037b2 | 927 | goto out_unlock; |
45ae7cff | 928 | |
44680eed | 929 | cfg->cbndx = ret; |
09360403 | 930 | if (smmu->version == ARM_SMMU_V1) { |
44680eed WD |
931 | cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
932 | cfg->irptndx %= smmu->num_context_irqs; | |
45ae7cff | 933 | } else { |
44680eed | 934 | cfg->irptndx = cfg->cbndx; |
45ae7cff WD |
935 | } |
936 | ||
a18037b2 MH |
937 | ACCESS_ONCE(smmu_domain->smmu) = smmu; |
938 | arm_smmu_init_context_bank(smmu_domain); | |
939 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
940 | ||
44680eed | 941 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; |
45ae7cff WD |
942 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
943 | "arm-smmu-context-fault", domain); | |
944 | if (IS_ERR_VALUE(ret)) { | |
945 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", | |
44680eed WD |
946 | cfg->irptndx, irq); |
947 | cfg->irptndx = INVALID_IRPTNDX; | |
45ae7cff WD |
948 | } |
949 | ||
a9a1b0b5 | 950 | return 0; |
45ae7cff | 951 | |
a18037b2 MH |
952 | out_unlock: |
953 | spin_unlock_irqrestore(&smmu_domain->lock, flags); | |
45ae7cff WD |
954 | return ret; |
955 | } | |
956 | ||
957 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) | |
958 | { | |
959 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
44680eed WD |
960 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
961 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1463fe44 | 962 | void __iomem *cb_base; |
45ae7cff WD |
963 | int irq; |
964 | ||
965 | if (!smmu) | |
966 | return; | |
967 | ||
1463fe44 | 968 | /* Disable the context bank and nuke the TLB before freeing it. */ |
44680eed | 969 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
1463fe44 | 970 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
44680eed | 971 | arm_smmu_tlb_inv_context(smmu_domain); |
1463fe44 | 972 | |
44680eed WD |
973 | if (cfg->irptndx != INVALID_IRPTNDX) { |
974 | irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; | |
45ae7cff WD |
975 | free_irq(irq, domain); |
976 | } | |
977 | ||
44680eed | 978 | __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); |
45ae7cff WD |
979 | } |
980 | ||
981 | static int arm_smmu_domain_init(struct iommu_domain *domain) | |
982 | { | |
983 | struct arm_smmu_domain *smmu_domain; | |
984 | pgd_t *pgd; | |
985 | ||
986 | /* | |
987 | * Allocate the domain and initialise some of its data structures. | |
988 | * We can't really do anything meaningful until we've added a | |
989 | * master. | |
990 | */ | |
991 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); | |
992 | if (!smmu_domain) | |
993 | return -ENOMEM; | |
994 | ||
2907320d | 995 | pgd = kcalloc(PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); |
45ae7cff WD |
996 | if (!pgd) |
997 | goto out_free_domain; | |
44680eed | 998 | smmu_domain->cfg.pgd = pgd; |
45ae7cff | 999 | |
c9d09e27 | 1000 | spin_lock_init(&smmu_domain->lock); |
45ae7cff WD |
1001 | domain->priv = smmu_domain; |
1002 | return 0; | |
1003 | ||
1004 | out_free_domain: | |
1005 | kfree(smmu_domain); | |
1006 | return -ENOMEM; | |
1007 | } | |
1008 | ||
1009 | static void arm_smmu_free_ptes(pmd_t *pmd) | |
1010 | { | |
1011 | pgtable_t table = pmd_pgtable(*pmd); | |
2907320d | 1012 | |
45ae7cff WD |
1013 | __free_page(table); |
1014 | } | |
1015 | ||
1016 | static void arm_smmu_free_pmds(pud_t *pud) | |
1017 | { | |
1018 | int i; | |
1019 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); | |
1020 | ||
1021 | pmd = pmd_base; | |
1022 | for (i = 0; i < PTRS_PER_PMD; ++i) { | |
1023 | if (pmd_none(*pmd)) | |
1024 | continue; | |
1025 | ||
1026 | arm_smmu_free_ptes(pmd); | |
1027 | pmd++; | |
1028 | } | |
1029 | ||
1030 | pmd_free(NULL, pmd_base); | |
1031 | } | |
1032 | ||
1033 | static void arm_smmu_free_puds(pgd_t *pgd) | |
1034 | { | |
1035 | int i; | |
1036 | pud_t *pud, *pud_base = pud_offset(pgd, 0); | |
1037 | ||
1038 | pud = pud_base; | |
1039 | for (i = 0; i < PTRS_PER_PUD; ++i) { | |
1040 | if (pud_none(*pud)) | |
1041 | continue; | |
1042 | ||
1043 | arm_smmu_free_pmds(pud); | |
1044 | pud++; | |
1045 | } | |
1046 | ||
1047 | pud_free(NULL, pud_base); | |
1048 | } | |
1049 | ||
1050 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) | |
1051 | { | |
1052 | int i; | |
44680eed WD |
1053 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
1054 | pgd_t *pgd, *pgd_base = cfg->pgd; | |
45ae7cff WD |
1055 | |
1056 | /* | |
1057 | * Recursively free the page tables for this domain. We don't | |
34fb4b37 WD |
1058 | * care about speculative TLB filling because the tables should |
1059 | * not be active in any context bank at this point (SCTLR.M is 0). | |
45ae7cff WD |
1060 | */ |
1061 | pgd = pgd_base; | |
1062 | for (i = 0; i < PTRS_PER_PGD; ++i) { | |
1063 | if (pgd_none(*pgd)) | |
1064 | continue; | |
1065 | arm_smmu_free_puds(pgd); | |
1066 | pgd++; | |
1067 | } | |
1068 | ||
1069 | kfree(pgd_base); | |
1070 | } | |
1071 | ||
1072 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) | |
1073 | { | |
1074 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
1463fe44 WD |
1075 | |
1076 | /* | |
1077 | * Free the domain resources. We assume that all devices have | |
1078 | * already been detached. | |
1079 | */ | |
45ae7cff WD |
1080 | arm_smmu_destroy_domain_context(domain); |
1081 | arm_smmu_free_pgtables(smmu_domain); | |
1082 | kfree(smmu_domain); | |
1083 | } | |
1084 | ||
1085 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1086 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1087 | { |
1088 | int i; | |
1089 | struct arm_smmu_smr *smrs; | |
1090 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1091 | ||
1092 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) | |
1093 | return 0; | |
1094 | ||
a9a1b0b5 | 1095 | if (cfg->smrs) |
45ae7cff WD |
1096 | return -EEXIST; |
1097 | ||
2907320d | 1098 | smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); |
45ae7cff | 1099 | if (!smrs) { |
a9a1b0b5 WD |
1100 | dev_err(smmu->dev, "failed to allocate %d SMRs\n", |
1101 | cfg->num_streamids); | |
45ae7cff WD |
1102 | return -ENOMEM; |
1103 | } | |
1104 | ||
44680eed | 1105 | /* Allocate the SMRs on the SMMU */ |
a9a1b0b5 | 1106 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1107 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
1108 | smmu->num_mapping_groups); | |
1109 | if (IS_ERR_VALUE(idx)) { | |
1110 | dev_err(smmu->dev, "failed to allocate free SMR\n"); | |
1111 | goto err_free_smrs; | |
1112 | } | |
1113 | ||
1114 | smrs[i] = (struct arm_smmu_smr) { | |
1115 | .idx = idx, | |
1116 | .mask = 0, /* We don't currently share SMRs */ | |
a9a1b0b5 | 1117 | .id = cfg->streamids[i], |
45ae7cff WD |
1118 | }; |
1119 | } | |
1120 | ||
1121 | /* It worked! Now, poke the actual hardware */ | |
a9a1b0b5 | 1122 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff WD |
1123 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
1124 | smrs[i].mask << SMR_MASK_SHIFT; | |
1125 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); | |
1126 | } | |
1127 | ||
a9a1b0b5 | 1128 | cfg->smrs = smrs; |
45ae7cff WD |
1129 | return 0; |
1130 | ||
1131 | err_free_smrs: | |
1132 | while (--i >= 0) | |
1133 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); | |
1134 | kfree(smrs); | |
1135 | return -ENOSPC; | |
1136 | } | |
1137 | ||
1138 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, | |
a9a1b0b5 | 1139 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1140 | { |
1141 | int i; | |
1142 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
a9a1b0b5 | 1143 | struct arm_smmu_smr *smrs = cfg->smrs; |
45ae7cff | 1144 | |
43b412be WD |
1145 | if (!smrs) |
1146 | return; | |
1147 | ||
45ae7cff | 1148 | /* Invalidate the SMRs before freeing back to the allocator */ |
a9a1b0b5 | 1149 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1150 | u8 idx = smrs[i].idx; |
2907320d | 1151 | |
45ae7cff WD |
1152 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
1153 | __arm_smmu_free_bitmap(smmu->smr_map, idx); | |
1154 | } | |
1155 | ||
a9a1b0b5 | 1156 | cfg->smrs = NULL; |
45ae7cff WD |
1157 | kfree(smrs); |
1158 | } | |
1159 | ||
45ae7cff | 1160 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
a9a1b0b5 | 1161 | struct arm_smmu_master_cfg *cfg) |
45ae7cff WD |
1162 | { |
1163 | int i, ret; | |
44680eed | 1164 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
45ae7cff WD |
1165 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
1166 | ||
8f68f8e2 | 1167 | /* Devices in an IOMMU group may already be configured */ |
a9a1b0b5 | 1168 | ret = arm_smmu_master_configure_smrs(smmu, cfg); |
45ae7cff | 1169 | if (ret) |
8f68f8e2 | 1170 | return ret == -EEXIST ? 0 : ret; |
45ae7cff | 1171 | |
a9a1b0b5 | 1172 | for (i = 0; i < cfg->num_streamids; ++i) { |
45ae7cff | 1173 | u32 idx, s2cr; |
2907320d | 1174 | |
a9a1b0b5 | 1175 | idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; |
6069d23c | 1176 | s2cr = S2CR_TYPE_TRANS | |
44680eed | 1177 | (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); |
45ae7cff WD |
1178 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
1179 | } | |
1180 | ||
1181 | return 0; | |
1182 | } | |
1183 | ||
1184 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, | |
a9a1b0b5 | 1185 | struct arm_smmu_master_cfg *cfg) |
45ae7cff | 1186 | { |
43b412be | 1187 | int i; |
44680eed | 1188 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
43b412be | 1189 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
45ae7cff | 1190 | |
8f68f8e2 WD |
1191 | /* An IOMMU group is torn down by the first device to be removed */ |
1192 | if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) | |
1193 | return; | |
45ae7cff WD |
1194 | |
1195 | /* | |
1196 | * We *must* clear the S2CR first, because freeing the SMR means | |
1197 | * that it can be re-allocated immediately. | |
1198 | */ | |
43b412be WD |
1199 | for (i = 0; i < cfg->num_streamids; ++i) { |
1200 | u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; | |
1201 | ||
1202 | writel_relaxed(S2CR_TYPE_BYPASS, | |
1203 | gr0_base + ARM_SMMU_GR0_S2CR(idx)); | |
1204 | } | |
1205 | ||
a9a1b0b5 | 1206 | arm_smmu_master_free_smrs(smmu, cfg); |
45ae7cff WD |
1207 | } |
1208 | ||
1209 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) | |
1210 | { | |
a18037b2 | 1211 | int ret; |
45ae7cff | 1212 | struct arm_smmu_domain *smmu_domain = domain->priv; |
a18037b2 | 1213 | struct arm_smmu_device *smmu, *dom_smmu; |
a9a1b0b5 | 1214 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1215 | |
8f68f8e2 | 1216 | smmu = find_smmu_for_device(dev); |
44680eed | 1217 | if (!smmu) { |
45ae7cff WD |
1218 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
1219 | return -ENXIO; | |
1220 | } | |
1221 | ||
844e35bd WD |
1222 | if (dev->archdata.iommu) { |
1223 | dev_err(dev, "already attached to IOMMU domain\n"); | |
1224 | return -EEXIST; | |
1225 | } | |
1226 | ||
45ae7cff | 1227 | /* |
44680eed WD |
1228 | * Sanity check the domain. We don't support domains across |
1229 | * different SMMUs. | |
45ae7cff | 1230 | */ |
a18037b2 MH |
1231 | dom_smmu = ACCESS_ONCE(smmu_domain->smmu); |
1232 | if (!dom_smmu) { | |
45ae7cff | 1233 | /* Now that we have a master, we can finalise the domain */ |
44680eed | 1234 | ret = arm_smmu_init_domain_context(domain, smmu); |
45ae7cff | 1235 | if (IS_ERR_VALUE(ret)) |
a18037b2 MH |
1236 | return ret; |
1237 | ||
1238 | dom_smmu = smmu_domain->smmu; | |
1239 | } | |
1240 | ||
1241 | if (dom_smmu != smmu) { | |
45ae7cff WD |
1242 | dev_err(dev, |
1243 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", | |
a18037b2 MH |
1244 | dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev)); |
1245 | return -EINVAL; | |
45ae7cff | 1246 | } |
45ae7cff WD |
1247 | |
1248 | /* Looks ok, so add the device to the domain */ | |
8f68f8e2 | 1249 | cfg = find_smmu_master_cfg(dev); |
a9a1b0b5 | 1250 | if (!cfg) |
45ae7cff WD |
1251 | return -ENODEV; |
1252 | ||
844e35bd WD |
1253 | ret = arm_smmu_domain_add_master(smmu_domain, cfg); |
1254 | if (!ret) | |
1255 | dev->archdata.iommu = domain; | |
45ae7cff WD |
1256 | return ret; |
1257 | } | |
1258 | ||
1259 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) | |
1260 | { | |
1261 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
a9a1b0b5 | 1262 | struct arm_smmu_master_cfg *cfg; |
45ae7cff | 1263 | |
8f68f8e2 | 1264 | cfg = find_smmu_master_cfg(dev); |
844e35bd WD |
1265 | if (!cfg) |
1266 | return; | |
1267 | ||
1268 | dev->archdata.iommu = NULL; | |
1269 | arm_smmu_domain_remove_master(smmu_domain, cfg); | |
45ae7cff WD |
1270 | } |
1271 | ||
45ae7cff WD |
1272 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
1273 | unsigned long end) | |
1274 | { | |
1275 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && | |
1276 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); | |
1277 | } | |
1278 | ||
1279 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, | |
1280 | unsigned long addr, unsigned long end, | |
b410aed9 | 1281 | unsigned long pfn, int prot, int stage) |
45ae7cff WD |
1282 | { |
1283 | pte_t *pte, *start; | |
cf2d45b1 | 1284 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN; |
45ae7cff WD |
1285 | |
1286 | if (pmd_none(*pmd)) { | |
1287 | /* Allocate a new set of tables */ | |
c9d09e27 | 1288 | pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO); |
2907320d | 1289 | |
45ae7cff WD |
1290 | if (!table) |
1291 | return -ENOMEM; | |
1292 | ||
6dd35f45 | 1293 | arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE); |
45ae7cff WD |
1294 | pmd_populate(NULL, pmd, table); |
1295 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); | |
1296 | } | |
1297 | ||
1298 | if (stage == 1) { | |
1463fe44 | 1299 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
b410aed9 | 1300 | if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) |
45ae7cff WD |
1301 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
1302 | ||
b410aed9 | 1303 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1304 | pteval |= (MAIR_ATTR_IDX_CACHE << |
1305 | ARM_SMMU_PTE_ATTRINDX_SHIFT); | |
1306 | } else { | |
1307 | pteval |= ARM_SMMU_PTE_HAP_FAULT; | |
b410aed9 | 1308 | if (prot & IOMMU_READ) |
45ae7cff | 1309 | pteval |= ARM_SMMU_PTE_HAP_READ; |
b410aed9 | 1310 | if (prot & IOMMU_WRITE) |
45ae7cff | 1311 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
b410aed9 | 1312 | if (prot & IOMMU_CACHE) |
45ae7cff WD |
1313 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
1314 | else | |
1315 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; | |
1316 | } | |
1317 | ||
1318 | /* If no access, create a faulting entry to avoid TLB fills */ | |
b410aed9 | 1319 | if (prot & IOMMU_EXEC) |
cf2d45b1 | 1320 | pteval &= ~ARM_SMMU_PTE_XN; |
b410aed9 | 1321 | else if (!(prot & (IOMMU_READ | IOMMU_WRITE))) |
45ae7cff WD |
1322 | pteval &= ~ARM_SMMU_PTE_PAGE; |
1323 | ||
1324 | pteval |= ARM_SMMU_PTE_SH_IS; | |
1325 | start = pmd_page_vaddr(*pmd) + pte_index(addr); | |
1326 | pte = start; | |
1327 | ||
1328 | /* | |
1329 | * Install the page table entries. This is fairly complicated | |
1330 | * since we attempt to make use of the contiguous hint in the | |
1331 | * ptes where possible. The contiguous hint indicates a series | |
1332 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically | |
1333 | * contiguous region with the following constraints: | |
1334 | * | |
1335 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE | |
1336 | * - Each pte in the region has the contiguous hint bit set | |
1337 | * | |
1338 | * This complicates unmapping (also handled by this code, when | |
1339 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is | |
1340 | * possible, yet highly unlikely, that a client may unmap only | |
1341 | * part of a contiguous range. This requires clearing of the | |
1342 | * contiguous hint bits in the range before installing the new | |
1343 | * faulting entries. | |
1344 | * | |
1345 | * Note that re-mapping an address range without first unmapping | |
1346 | * it is not supported, so TLB invalidation is not required here | |
1347 | * and is instead performed at unmap and domain-init time. | |
1348 | */ | |
1349 | do { | |
1350 | int i = 1; | |
2907320d | 1351 | |
45ae7cff WD |
1352 | pteval &= ~ARM_SMMU_PTE_CONT; |
1353 | ||
1354 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { | |
1355 | i = ARM_SMMU_PTE_CONT_ENTRIES; | |
1356 | pteval |= ARM_SMMU_PTE_CONT; | |
1357 | } else if (pte_val(*pte) & | |
1358 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { | |
1359 | int j; | |
1360 | pte_t *cont_start; | |
1361 | unsigned long idx = pte_index(addr); | |
1362 | ||
1363 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); | |
1364 | cont_start = pmd_page_vaddr(*pmd) + idx; | |
1365 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) | |
2907320d MH |
1366 | pte_val(*(cont_start + j)) &= |
1367 | ~ARM_SMMU_PTE_CONT; | |
45ae7cff WD |
1368 | |
1369 | arm_smmu_flush_pgtable(smmu, cont_start, | |
1370 | sizeof(*pte) * | |
1371 | ARM_SMMU_PTE_CONT_ENTRIES); | |
1372 | } | |
1373 | ||
1374 | do { | |
1375 | *pte = pfn_pte(pfn, __pgprot(pteval)); | |
1376 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); | |
1377 | } while (addr != end); | |
1378 | ||
1379 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); | |
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, | |
1384 | unsigned long addr, unsigned long end, | |
b410aed9 | 1385 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1386 | { |
1387 | int ret; | |
1388 | pmd_t *pmd; | |
1389 | unsigned long next, pfn = __phys_to_pfn(phys); | |
1390 | ||
1391 | #ifndef __PAGETABLE_PMD_FOLDED | |
1392 | if (pud_none(*pud)) { | |
c9d09e27 | 1393 | pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1394 | if (!pmd) |
1395 | return -ENOMEM; | |
97a64420 | 1396 | |
6dd35f45 | 1397 | arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE); |
97a64420 YZ |
1398 | pud_populate(NULL, pud, pmd); |
1399 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); | |
1400 | ||
1401 | pmd += pmd_index(addr); | |
45ae7cff WD |
1402 | } else |
1403 | #endif | |
1404 | pmd = pmd_offset(pud, addr); | |
1405 | ||
1406 | do { | |
1407 | next = pmd_addr_end(addr, end); | |
aca1bc45 | 1408 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, next, pfn, |
b410aed9 | 1409 | prot, stage); |
45ae7cff | 1410 | phys += next - addr; |
ccd359f2 | 1411 | pfn = __phys_to_pfn(phys); |
45ae7cff WD |
1412 | } while (pmd++, addr = next, addr < end); |
1413 | ||
1414 | return ret; | |
1415 | } | |
1416 | ||
1417 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, | |
1418 | unsigned long addr, unsigned long end, | |
b410aed9 | 1419 | phys_addr_t phys, int prot, int stage) |
45ae7cff WD |
1420 | { |
1421 | int ret = 0; | |
1422 | pud_t *pud; | |
1423 | unsigned long next; | |
1424 | ||
1425 | #ifndef __PAGETABLE_PUD_FOLDED | |
1426 | if (pgd_none(*pgd)) { | |
c9d09e27 | 1427 | pud = (pud_t *)get_zeroed_page(GFP_ATOMIC); |
45ae7cff WD |
1428 | if (!pud) |
1429 | return -ENOMEM; | |
97a64420 | 1430 | |
6dd35f45 | 1431 | arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE); |
97a64420 YZ |
1432 | pgd_populate(NULL, pgd, pud); |
1433 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); | |
1434 | ||
1435 | pud += pud_index(addr); | |
45ae7cff WD |
1436 | } else |
1437 | #endif | |
1438 | pud = pud_offset(pgd, addr); | |
1439 | ||
1440 | do { | |
1441 | next = pud_addr_end(addr, end); | |
1442 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, | |
b410aed9 | 1443 | prot, stage); |
45ae7cff WD |
1444 | phys += next - addr; |
1445 | } while (pud++, addr = next, addr < end); | |
1446 | ||
1447 | return ret; | |
1448 | } | |
1449 | ||
1450 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, | |
1451 | unsigned long iova, phys_addr_t paddr, | |
b410aed9 | 1452 | size_t size, int prot) |
45ae7cff WD |
1453 | { |
1454 | int ret, stage; | |
1455 | unsigned long end; | |
1456 | phys_addr_t input_mask, output_mask; | |
44680eed WD |
1457 | struct arm_smmu_device *smmu = smmu_domain->smmu; |
1458 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; | |
1459 | pgd_t *pgd = cfg->pgd; | |
b410aed9 | 1460 | unsigned long flags; |
45ae7cff | 1461 | |
44680eed | 1462 | if (cfg->cbar == CBAR_TYPE_S2_TRANS) { |
45ae7cff | 1463 | stage = 2; |
28d6007b | 1464 | input_mask = (1ULL << smmu->s2_input_size) - 1; |
45ae7cff WD |
1465 | output_mask = (1ULL << smmu->s2_output_size) - 1; |
1466 | } else { | |
1467 | stage = 1; | |
28d6007b | 1468 | input_mask = (1ULL << smmu->s1_input_size) - 1; |
45ae7cff WD |
1469 | output_mask = (1ULL << smmu->s1_output_size) - 1; |
1470 | } | |
1471 | ||
1472 | if (!pgd) | |
1473 | return -EINVAL; | |
1474 | ||
1475 | if (size & ~PAGE_MASK) | |
1476 | return -EINVAL; | |
1477 | ||
45ae7cff WD |
1478 | if ((phys_addr_t)iova & ~input_mask) |
1479 | return -ERANGE; | |
1480 | ||
1481 | if (paddr & ~output_mask) | |
1482 | return -ERANGE; | |
1483 | ||
b410aed9 | 1484 | spin_lock_irqsave(&smmu_domain->lock, flags); |
45ae7cff WD |
1485 | pgd += pgd_index(iova); |
1486 | end = iova + size; | |
1487 | do { | |
1488 | unsigned long next = pgd_addr_end(iova, end); | |
1489 | ||
1490 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, | |
b410aed9 | 1491 | prot, stage); |
45ae7cff WD |
1492 | if (ret) |
1493 | goto out_unlock; | |
1494 | ||
1495 | paddr += next - iova; | |
1496 | iova = next; | |
1497 | } while (pgd++, iova != end); | |
1498 | ||
1499 | out_unlock: | |
b410aed9 | 1500 | spin_unlock_irqrestore(&smmu_domain->lock, flags); |
45ae7cff | 1501 | |
45ae7cff WD |
1502 | return ret; |
1503 | } | |
1504 | ||
1505 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, | |
b410aed9 | 1506 | phys_addr_t paddr, size_t size, int prot) |
45ae7cff WD |
1507 | { |
1508 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff | 1509 | |
5552ecdb | 1510 | if (!smmu_domain) |
45ae7cff WD |
1511 | return -ENODEV; |
1512 | ||
b410aed9 | 1513 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, prot); |
45ae7cff WD |
1514 | } |
1515 | ||
1516 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, | |
1517 | size_t size) | |
1518 | { | |
1519 | int ret; | |
1520 | struct arm_smmu_domain *smmu_domain = domain->priv; | |
45ae7cff WD |
1521 | |
1522 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); | |
44680eed | 1523 | arm_smmu_tlb_inv_context(smmu_domain); |
16c50dcf | 1524 | return ret ? 0 : size; |
45ae7cff WD |
1525 | } |
1526 | ||
1527 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, | |
1528 | dma_addr_t iova) | |
1529 | { | |
a44a9791 WD |
1530 | pgd_t *pgdp, pgd; |
1531 | pud_t pud; | |
1532 | pmd_t pmd; | |
1533 | pte_t pte; | |
45ae7cff | 1534 | struct arm_smmu_domain *smmu_domain = domain->priv; |
44680eed | 1535 | struct arm_smmu_cfg *cfg = &smmu_domain->cfg; |
45ae7cff | 1536 | |
44680eed | 1537 | pgdp = cfg->pgd; |
a44a9791 WD |
1538 | if (!pgdp) |
1539 | return 0; | |
45ae7cff | 1540 | |
a44a9791 WD |
1541 | pgd = *(pgdp + pgd_index(iova)); |
1542 | if (pgd_none(pgd)) | |
1543 | return 0; | |
45ae7cff | 1544 | |
a44a9791 WD |
1545 | pud = *pud_offset(&pgd, iova); |
1546 | if (pud_none(pud)) | |
1547 | return 0; | |
45ae7cff | 1548 | |
a44a9791 WD |
1549 | pmd = *pmd_offset(&pud, iova); |
1550 | if (pmd_none(pmd)) | |
1551 | return 0; | |
45ae7cff | 1552 | |
a44a9791 | 1553 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
45ae7cff | 1554 | if (pte_none(pte)) |
a44a9791 | 1555 | return 0; |
45ae7cff | 1556 | |
a44a9791 | 1557 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
45ae7cff WD |
1558 | } |
1559 | ||
1fd0c775 | 1560 | static bool arm_smmu_capable(enum iommu_cap cap) |
45ae7cff | 1561 | { |
d0948945 WD |
1562 | switch (cap) { |
1563 | case IOMMU_CAP_CACHE_COHERENCY: | |
1fd0c775 JR |
1564 | /* |
1565 | * Return true here as the SMMU can always send out coherent | |
1566 | * requests. | |
1567 | */ | |
1568 | return true; | |
d0948945 | 1569 | case IOMMU_CAP_INTR_REMAP: |
1fd0c775 | 1570 | return true; /* MSIs are just memory writes */ |
d0948945 | 1571 | default: |
1fd0c775 | 1572 | return false; |
d0948945 | 1573 | } |
45ae7cff | 1574 | } |
45ae7cff | 1575 | |
a9a1b0b5 WD |
1576 | static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data) |
1577 | { | |
1578 | *((u16 *)data) = alias; | |
1579 | return 0; /* Continue walking */ | |
45ae7cff WD |
1580 | } |
1581 | ||
8f68f8e2 WD |
1582 | static void __arm_smmu_release_pci_iommudata(void *data) |
1583 | { | |
1584 | kfree(data); | |
1585 | } | |
1586 | ||
45ae7cff WD |
1587 | static int arm_smmu_add_device(struct device *dev) |
1588 | { | |
a9a1b0b5 | 1589 | struct arm_smmu_device *smmu; |
8f68f8e2 | 1590 | struct arm_smmu_master_cfg *cfg; |
5fc63a7c | 1591 | struct iommu_group *group; |
8f68f8e2 | 1592 | void (*releasefn)(void *) = NULL; |
5fc63a7c AM |
1593 | int ret; |
1594 | ||
44680eed | 1595 | smmu = find_smmu_for_device(dev); |
a9a1b0b5 | 1596 | if (!smmu) |
45ae7cff WD |
1597 | return -ENODEV; |
1598 | ||
5fc63a7c AM |
1599 | group = iommu_group_alloc(); |
1600 | if (IS_ERR(group)) { | |
1601 | dev_err(dev, "Failed to allocate IOMMU group\n"); | |
1602 | return PTR_ERR(group); | |
1603 | } | |
1604 | ||
a9a1b0b5 | 1605 | if (dev_is_pci(dev)) { |
a9a1b0b5 WD |
1606 | struct pci_dev *pdev = to_pci_dev(dev); |
1607 | ||
1608 | cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); | |
1609 | if (!cfg) { | |
1610 | ret = -ENOMEM; | |
1611 | goto out_put_group; | |
1612 | } | |
1613 | ||
1614 | cfg->num_streamids = 1; | |
1615 | /* | |
1616 | * Assume Stream ID == Requester ID for now. | |
1617 | * We need a way to describe the ID mappings in FDT. | |
1618 | */ | |
1619 | pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, | |
1620 | &cfg->streamids[0]); | |
8f68f8e2 | 1621 | releasefn = __arm_smmu_release_pci_iommudata; |
a9a1b0b5 | 1622 | } else { |
8f68f8e2 WD |
1623 | struct arm_smmu_master *master; |
1624 | ||
1625 | master = find_smmu_master(smmu, dev->of_node); | |
1626 | if (!master) { | |
1627 | ret = -ENODEV; | |
1628 | goto out_put_group; | |
1629 | } | |
1630 | ||
1631 | cfg = &master->cfg; | |
a9a1b0b5 WD |
1632 | } |
1633 | ||
8f68f8e2 | 1634 | iommu_group_set_iommudata(group, cfg, releasefn); |
5fc63a7c | 1635 | ret = iommu_group_add_device(group, dev); |
5fc63a7c | 1636 | |
a9a1b0b5 WD |
1637 | out_put_group: |
1638 | iommu_group_put(group); | |
5fc63a7c | 1639 | return ret; |
45ae7cff WD |
1640 | } |
1641 | ||
1642 | static void arm_smmu_remove_device(struct device *dev) | |
1643 | { | |
5fc63a7c | 1644 | iommu_group_remove_device(dev); |
45ae7cff WD |
1645 | } |
1646 | ||
b22f6434 | 1647 | static const struct iommu_ops arm_smmu_ops = { |
1fd0c775 | 1648 | .capable = arm_smmu_capable, |
45ae7cff WD |
1649 | .domain_init = arm_smmu_domain_init, |
1650 | .domain_destroy = arm_smmu_domain_destroy, | |
1651 | .attach_dev = arm_smmu_attach_dev, | |
1652 | .detach_dev = arm_smmu_detach_dev, | |
1653 | .map = arm_smmu_map, | |
1654 | .unmap = arm_smmu_unmap, | |
1655 | .iova_to_phys = arm_smmu_iova_to_phys, | |
45ae7cff WD |
1656 | .add_device = arm_smmu_add_device, |
1657 | .remove_device = arm_smmu_remove_device, | |
1658 | .pgsize_bitmap = (SECTION_SIZE | | |
1659 | ARM_SMMU_PTE_CONT_SIZE | | |
1660 | PAGE_SIZE), | |
1661 | }; | |
1662 | ||
1663 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) | |
1664 | { | |
1665 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
659db6f6 | 1666 | void __iomem *cb_base; |
45ae7cff | 1667 | int i = 0; |
659db6f6 AH |
1668 | u32 reg; |
1669 | ||
3a5df8ff AH |
1670 | /* clear global FSR */ |
1671 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
1672 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR); | |
45ae7cff WD |
1673 | |
1674 | /* Mark all SMRn as invalid and all S2CRn as bypass */ | |
1675 | for (i = 0; i < smmu->num_mapping_groups; ++i) { | |
3c8766d0 | 1676 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i)); |
2907320d MH |
1677 | writel_relaxed(S2CR_TYPE_BYPASS, |
1678 | gr0_base + ARM_SMMU_GR0_S2CR(i)); | |
45ae7cff WD |
1679 | } |
1680 | ||
659db6f6 AH |
1681 | /* Make sure all context banks are disabled and clear CB_FSR */ |
1682 | for (i = 0; i < smmu->num_context_banks; ++i) { | |
1683 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); | |
1684 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); | |
1685 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); | |
1686 | } | |
1463fe44 | 1687 | |
45ae7cff WD |
1688 | /* Invalidate the TLB, just in case */ |
1689 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); | |
1690 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); | |
1691 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); | |
1692 | ||
3a5df8ff | 1693 | reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
659db6f6 | 1694 | |
45ae7cff | 1695 | /* Enable fault reporting */ |
659db6f6 | 1696 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
45ae7cff WD |
1697 | |
1698 | /* Disable TLB broadcasting. */ | |
659db6f6 | 1699 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
45ae7cff WD |
1700 | |
1701 | /* Enable client access, but bypass when no mapping is found */ | |
659db6f6 | 1702 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
45ae7cff WD |
1703 | |
1704 | /* Disable forced broadcasting */ | |
659db6f6 | 1705 | reg &= ~sCR0_FB; |
45ae7cff WD |
1706 | |
1707 | /* Don't upgrade barriers */ | |
659db6f6 | 1708 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
45ae7cff WD |
1709 | |
1710 | /* Push the button */ | |
1711 | arm_smmu_tlb_sync(smmu); | |
3a5df8ff | 1712 | writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
1713 | } |
1714 | ||
1715 | static int arm_smmu_id_size_to_bits(int size) | |
1716 | { | |
1717 | switch (size) { | |
1718 | case 0: | |
1719 | return 32; | |
1720 | case 1: | |
1721 | return 36; | |
1722 | case 2: | |
1723 | return 40; | |
1724 | case 3: | |
1725 | return 42; | |
1726 | case 4: | |
1727 | return 44; | |
1728 | case 5: | |
1729 | default: | |
1730 | return 48; | |
1731 | } | |
1732 | } | |
1733 | ||
1734 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) | |
1735 | { | |
1736 | unsigned long size; | |
1737 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); | |
1738 | u32 id; | |
1739 | ||
1740 | dev_notice(smmu->dev, "probing hardware configuration...\n"); | |
45ae7cff WD |
1741 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); |
1742 | ||
1743 | /* ID0 */ | |
1744 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); | |
1745 | #ifndef CONFIG_64BIT | |
1746 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { | |
1747 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); | |
1748 | return -ENODEV; | |
1749 | } | |
1750 | #endif | |
4cf740b0 WD |
1751 | |
1752 | /* Restrict available stages based on module parameter */ | |
1753 | if (force_stage == 1) | |
1754 | id &= ~(ID0_S2TS | ID0_NTS); | |
1755 | else if (force_stage == 2) | |
1756 | id &= ~(ID0_S1TS | ID0_NTS); | |
1757 | ||
45ae7cff WD |
1758 | if (id & ID0_S1TS) { |
1759 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; | |
1760 | dev_notice(smmu->dev, "\tstage 1 translation\n"); | |
1761 | } | |
1762 | ||
1763 | if (id & ID0_S2TS) { | |
1764 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; | |
1765 | dev_notice(smmu->dev, "\tstage 2 translation\n"); | |
1766 | } | |
1767 | ||
1768 | if (id & ID0_NTS) { | |
1769 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; | |
1770 | dev_notice(smmu->dev, "\tnested translation\n"); | |
1771 | } | |
1772 | ||
1773 | if (!(smmu->features & | |
4cf740b0 | 1774 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { |
45ae7cff WD |
1775 | dev_err(smmu->dev, "\tno translation support!\n"); |
1776 | return -ENODEV; | |
1777 | } | |
1778 | ||
1779 | if (id & ID0_CTTW) { | |
1780 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; | |
1781 | dev_notice(smmu->dev, "\tcoherent table walk\n"); | |
1782 | } | |
1783 | ||
1784 | if (id & ID0_SMS) { | |
1785 | u32 smr, sid, mask; | |
1786 | ||
1787 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; | |
1788 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & | |
1789 | ID0_NUMSMRG_MASK; | |
1790 | if (smmu->num_mapping_groups == 0) { | |
1791 | dev_err(smmu->dev, | |
1792 | "stream-matching supported, but no SMRs present!\n"); | |
1793 | return -ENODEV; | |
1794 | } | |
1795 | ||
1796 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; | |
1797 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); | |
1798 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1799 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); | |
1800 | ||
1801 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; | |
1802 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; | |
1803 | if ((mask & sid) != sid) { | |
1804 | dev_err(smmu->dev, | |
1805 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", | |
1806 | mask, sid); | |
1807 | return -ENODEV; | |
1808 | } | |
1809 | ||
1810 | dev_notice(smmu->dev, | |
1811 | "\tstream matching with %u register groups, mask 0x%x", | |
1812 | smmu->num_mapping_groups, mask); | |
3c8766d0 OH |
1813 | } else { |
1814 | smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) & | |
1815 | ID0_NUMSIDB_MASK; | |
45ae7cff WD |
1816 | } |
1817 | ||
1818 | /* ID1 */ | |
1819 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); | |
c757e852 | 1820 | smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12; |
45ae7cff | 1821 | |
c55af7f7 | 1822 | /* Check for size mismatch of SMMU address space from mapped region */ |
2907320d MH |
1823 | size = 1 << |
1824 | (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); | |
c757e852 | 1825 | size *= 2 << smmu->pgshift; |
c55af7f7 | 1826 | if (smmu->size != size) |
2907320d MH |
1827 | dev_warn(smmu->dev, |
1828 | "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n", | |
1829 | size, smmu->size); | |
45ae7cff WD |
1830 | |
1831 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & | |
1832 | ID1_NUMS2CB_MASK; | |
1833 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; | |
1834 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { | |
1835 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); | |
1836 | return -ENODEV; | |
1837 | } | |
1838 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", | |
1839 | smmu->num_context_banks, smmu->num_s2_context_banks); | |
1840 | ||
1841 | /* ID2 */ | |
1842 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); | |
1843 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); | |
28d6007b | 1844 | smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); |
45ae7cff | 1845 | |
28d6007b | 1846 | /* Stage-2 input size limited due to pgd allocation (PTRS_PER_PGD) */ |
45ae7cff | 1847 | #ifdef CONFIG_64BIT |
28d6007b | 1848 | smmu->s2_input_size = min_t(unsigned long, VA_BITS, size); |
45ae7cff | 1849 | #else |
28d6007b | 1850 | smmu->s2_input_size = min(32UL, size); |
45ae7cff WD |
1851 | #endif |
1852 | ||
1853 | /* The stage-2 output mask is also applied for bypass */ | |
1854 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); | |
2907320d | 1855 | smmu->s2_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size); |
45ae7cff | 1856 | |
09360403 | 1857 | if (smmu->version == ARM_SMMU_V1) { |
28d6007b | 1858 | smmu->s1_input_size = 32; |
45ae7cff WD |
1859 | } else { |
1860 | #ifdef CONFIG_64BIT | |
1861 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; | |
06f983dd | 1862 | size = min(VA_BITS, arm_smmu_id_size_to_bits(size)); |
45ae7cff WD |
1863 | #else |
1864 | size = 32; | |
1865 | #endif | |
28d6007b | 1866 | smmu->s1_input_size = size; |
45ae7cff WD |
1867 | |
1868 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || | |
1869 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || | |
1870 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { | |
1871 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", | |
1872 | PAGE_SIZE); | |
1873 | return -ENODEV; | |
1874 | } | |
1875 | } | |
1876 | ||
28d6007b WD |
1877 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) |
1878 | dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", | |
1879 | smmu->s1_input_size, smmu->s1_output_size); | |
1880 | ||
1881 | if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) | |
1882 | dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", | |
1883 | smmu->s2_input_size, smmu->s2_output_size); | |
1884 | ||
45ae7cff WD |
1885 | return 0; |
1886 | } | |
1887 | ||
09b5269a | 1888 | static const struct of_device_id arm_smmu_of_match[] = { |
09360403 RM |
1889 | { .compatible = "arm,smmu-v1", .data = (void *)ARM_SMMU_V1 }, |
1890 | { .compatible = "arm,smmu-v2", .data = (void *)ARM_SMMU_V2 }, | |
1891 | { .compatible = "arm,mmu-400", .data = (void *)ARM_SMMU_V1 }, | |
d3aba046 | 1892 | { .compatible = "arm,mmu-401", .data = (void *)ARM_SMMU_V1 }, |
09360403 RM |
1893 | { .compatible = "arm,mmu-500", .data = (void *)ARM_SMMU_V2 }, |
1894 | { }, | |
1895 | }; | |
1896 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); | |
1897 | ||
45ae7cff WD |
1898 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
1899 | { | |
09360403 | 1900 | const struct of_device_id *of_id; |
45ae7cff WD |
1901 | struct resource *res; |
1902 | struct arm_smmu_device *smmu; | |
45ae7cff WD |
1903 | struct device *dev = &pdev->dev; |
1904 | struct rb_node *node; | |
1905 | struct of_phandle_args masterspec; | |
1906 | int num_irqs, i, err; | |
1907 | ||
1908 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); | |
1909 | if (!smmu) { | |
1910 | dev_err(dev, "failed to allocate arm_smmu_device\n"); | |
1911 | return -ENOMEM; | |
1912 | } | |
1913 | smmu->dev = dev; | |
1914 | ||
09360403 RM |
1915 | of_id = of_match_node(arm_smmu_of_match, dev->of_node); |
1916 | smmu->version = (enum arm_smmu_arch_version)of_id->data; | |
1917 | ||
45ae7cff | 1918 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
8a7f4312 JL |
1919 | smmu->base = devm_ioremap_resource(dev, res); |
1920 | if (IS_ERR(smmu->base)) | |
1921 | return PTR_ERR(smmu->base); | |
45ae7cff | 1922 | smmu->size = resource_size(res); |
45ae7cff WD |
1923 | |
1924 | if (of_property_read_u32(dev->of_node, "#global-interrupts", | |
1925 | &smmu->num_global_irqs)) { | |
1926 | dev_err(dev, "missing #global-interrupts property\n"); | |
1927 | return -ENODEV; | |
1928 | } | |
1929 | ||
1930 | num_irqs = 0; | |
1931 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { | |
1932 | num_irqs++; | |
1933 | if (num_irqs > smmu->num_global_irqs) | |
1934 | smmu->num_context_irqs++; | |
1935 | } | |
1936 | ||
44a08de2 AH |
1937 | if (!smmu->num_context_irqs) { |
1938 | dev_err(dev, "found %d interrupts but expected at least %d\n", | |
1939 | num_irqs, smmu->num_global_irqs + 1); | |
1940 | return -ENODEV; | |
45ae7cff | 1941 | } |
45ae7cff WD |
1942 | |
1943 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, | |
1944 | GFP_KERNEL); | |
1945 | if (!smmu->irqs) { | |
1946 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); | |
1947 | return -ENOMEM; | |
1948 | } | |
1949 | ||
1950 | for (i = 0; i < num_irqs; ++i) { | |
1951 | int irq = platform_get_irq(pdev, i); | |
2907320d | 1952 | |
45ae7cff WD |
1953 | if (irq < 0) { |
1954 | dev_err(dev, "failed to get irq index %d\n", i); | |
1955 | return -ENODEV; | |
1956 | } | |
1957 | smmu->irqs[i] = irq; | |
1958 | } | |
1959 | ||
3c8766d0 OH |
1960 | err = arm_smmu_device_cfg_probe(smmu); |
1961 | if (err) | |
1962 | return err; | |
1963 | ||
45ae7cff WD |
1964 | i = 0; |
1965 | smmu->masters = RB_ROOT; | |
1966 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", | |
1967 | "#stream-id-cells", i, | |
1968 | &masterspec)) { | |
1969 | err = register_smmu_master(smmu, dev, &masterspec); | |
1970 | if (err) { | |
1971 | dev_err(dev, "failed to add master %s\n", | |
1972 | masterspec.np->name); | |
1973 | goto out_put_masters; | |
1974 | } | |
1975 | ||
1976 | i++; | |
1977 | } | |
1978 | dev_notice(dev, "registered %d master devices\n", i); | |
1979 | ||
3a5df8ff AH |
1980 | parse_driver_options(smmu); |
1981 | ||
09360403 | 1982 | if (smmu->version > ARM_SMMU_V1 && |
45ae7cff WD |
1983 | smmu->num_context_banks != smmu->num_context_irqs) { |
1984 | dev_err(dev, | |
1985 | "found only %d context interrupt(s) but %d required\n", | |
1986 | smmu->num_context_irqs, smmu->num_context_banks); | |
89a23cde | 1987 | err = -ENODEV; |
44680eed | 1988 | goto out_put_masters; |
45ae7cff WD |
1989 | } |
1990 | ||
45ae7cff WD |
1991 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
1992 | err = request_irq(smmu->irqs[i], | |
1993 | arm_smmu_global_fault, | |
1994 | IRQF_SHARED, | |
1995 | "arm-smmu global fault", | |
1996 | smmu); | |
1997 | if (err) { | |
1998 | dev_err(dev, "failed to request global IRQ %d (%u)\n", | |
1999 | i, smmu->irqs[i]); | |
2000 | goto out_free_irqs; | |
2001 | } | |
2002 | } | |
2003 | ||
2004 | INIT_LIST_HEAD(&smmu->list); | |
2005 | spin_lock(&arm_smmu_devices_lock); | |
2006 | list_add(&smmu->list, &arm_smmu_devices); | |
2007 | spin_unlock(&arm_smmu_devices_lock); | |
fd90cecb WD |
2008 | |
2009 | arm_smmu_device_reset(smmu); | |
45ae7cff WD |
2010 | return 0; |
2011 | ||
2012 | out_free_irqs: | |
2013 | while (i--) | |
2014 | free_irq(smmu->irqs[i], smmu); | |
2015 | ||
45ae7cff WD |
2016 | out_put_masters: |
2017 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { | |
2907320d MH |
2018 | struct arm_smmu_master *master |
2019 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
2020 | of_node_put(master->of_node); |
2021 | } | |
2022 | ||
2023 | return err; | |
2024 | } | |
2025 | ||
2026 | static int arm_smmu_device_remove(struct platform_device *pdev) | |
2027 | { | |
2028 | int i; | |
2029 | struct device *dev = &pdev->dev; | |
2030 | struct arm_smmu_device *curr, *smmu = NULL; | |
2031 | struct rb_node *node; | |
2032 | ||
2033 | spin_lock(&arm_smmu_devices_lock); | |
2034 | list_for_each_entry(curr, &arm_smmu_devices, list) { | |
2035 | if (curr->dev == dev) { | |
2036 | smmu = curr; | |
2037 | list_del(&smmu->list); | |
2038 | break; | |
2039 | } | |
2040 | } | |
2041 | spin_unlock(&arm_smmu_devices_lock); | |
2042 | ||
2043 | if (!smmu) | |
2044 | return -ENODEV; | |
2045 | ||
45ae7cff | 2046 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
2907320d MH |
2047 | struct arm_smmu_master *master |
2048 | = container_of(node, struct arm_smmu_master, node); | |
45ae7cff WD |
2049 | of_node_put(master->of_node); |
2050 | } | |
2051 | ||
ecfadb6e | 2052 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
45ae7cff WD |
2053 | dev_err(dev, "removing device with active domains!\n"); |
2054 | ||
2055 | for (i = 0; i < smmu->num_global_irqs; ++i) | |
2056 | free_irq(smmu->irqs[i], smmu); | |
2057 | ||
2058 | /* Turn the thing off */ | |
2907320d | 2059 | writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0); |
45ae7cff WD |
2060 | return 0; |
2061 | } | |
2062 | ||
45ae7cff WD |
2063 | static struct platform_driver arm_smmu_driver = { |
2064 | .driver = { | |
2065 | .owner = THIS_MODULE, | |
2066 | .name = "arm-smmu", | |
2067 | .of_match_table = of_match_ptr(arm_smmu_of_match), | |
2068 | }, | |
2069 | .probe = arm_smmu_device_dt_probe, | |
2070 | .remove = arm_smmu_device_remove, | |
2071 | }; | |
2072 | ||
2073 | static int __init arm_smmu_init(void) | |
2074 | { | |
2075 | int ret; | |
2076 | ||
2077 | ret = platform_driver_register(&arm_smmu_driver); | |
2078 | if (ret) | |
2079 | return ret; | |
2080 | ||
2081 | /* Oh, for a proper bus abstraction */ | |
6614ee77 | 2082 | if (!iommu_present(&platform_bus_type)) |
45ae7cff WD |
2083 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
2084 | ||
d123cf82 | 2085 | #ifdef CONFIG_ARM_AMBA |
6614ee77 | 2086 | if (!iommu_present(&amba_bustype)) |
45ae7cff | 2087 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
d123cf82 | 2088 | #endif |
45ae7cff | 2089 | |
a9a1b0b5 WD |
2090 | #ifdef CONFIG_PCI |
2091 | if (!iommu_present(&pci_bus_type)) | |
2092 | bus_set_iommu(&pci_bus_type, &arm_smmu_ops); | |
2093 | #endif | |
2094 | ||
45ae7cff WD |
2095 | return 0; |
2096 | } | |
2097 | ||
2098 | static void __exit arm_smmu_exit(void) | |
2099 | { | |
2100 | return platform_driver_unregister(&arm_smmu_driver); | |
2101 | } | |
2102 | ||
b1950b27 | 2103 | subsys_initcall(arm_smmu_init); |
45ae7cff WD |
2104 | module_exit(arm_smmu_exit); |
2105 | ||
2106 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); | |
2107 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); | |
2108 | MODULE_LICENSE("GPL v2"); |