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0db2e5d1 RM |
1 | /* |
2 | * A fairly generic DMA-API to IOMMU-API glue layer. | |
3 | * | |
4 | * Copyright (C) 2014-2015 ARM Ltd. | |
5 | * | |
6 | * based in part on arch/arm/mm/dma-mapping.c: | |
7 | * Copyright (C) 2000-2004 Russell King | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <linux/device.h> | |
23 | #include <linux/dma-iommu.h> | |
5b11e9cd | 24 | #include <linux/gfp.h> |
0db2e5d1 RM |
25 | #include <linux/huge_mm.h> |
26 | #include <linux/iommu.h> | |
27 | #include <linux/iova.h> | |
44bb7e24 | 28 | #include <linux/irq.h> |
0db2e5d1 | 29 | #include <linux/mm.h> |
fade1ec0 | 30 | #include <linux/pci.h> |
5b11e9cd RM |
31 | #include <linux/scatterlist.h> |
32 | #include <linux/vmalloc.h> | |
0db2e5d1 | 33 | |
44bb7e24 RM |
34 | struct iommu_dma_msi_page { |
35 | struct list_head list; | |
36 | dma_addr_t iova; | |
37 | phys_addr_t phys; | |
38 | }; | |
39 | ||
fdbe574e RM |
40 | enum iommu_dma_cookie_type { |
41 | IOMMU_DMA_IOVA_COOKIE, | |
42 | IOMMU_DMA_MSI_COOKIE, | |
43 | }; | |
44 | ||
44bb7e24 | 45 | struct iommu_dma_cookie { |
fdbe574e RM |
46 | enum iommu_dma_cookie_type type; |
47 | union { | |
48 | /* Full allocator for IOMMU_DMA_IOVA_COOKIE */ | |
49 | struct iova_domain iovad; | |
50 | /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */ | |
51 | dma_addr_t msi_iova; | |
52 | }; | |
53 | struct list_head msi_page_list; | |
54 | spinlock_t msi_lock; | |
44bb7e24 RM |
55 | }; |
56 | ||
fdbe574e RM |
57 | static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie) |
58 | { | |
59 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) | |
60 | return cookie->iovad.granule; | |
61 | return PAGE_SIZE; | |
62 | } | |
63 | ||
44bb7e24 RM |
64 | static inline struct iova_domain *cookie_iovad(struct iommu_domain *domain) |
65 | { | |
fdbe574e RM |
66 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
67 | ||
68 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE) | |
69 | return &cookie->iovad; | |
70 | return NULL; | |
71 | } | |
72 | ||
73 | static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type) | |
74 | { | |
75 | struct iommu_dma_cookie *cookie; | |
76 | ||
77 | cookie = kzalloc(sizeof(*cookie), GFP_KERNEL); | |
78 | if (cookie) { | |
79 | spin_lock_init(&cookie->msi_lock); | |
80 | INIT_LIST_HEAD(&cookie->msi_page_list); | |
81 | cookie->type = type; | |
82 | } | |
83 | return cookie; | |
44bb7e24 RM |
84 | } |
85 | ||
0db2e5d1 RM |
86 | int iommu_dma_init(void) |
87 | { | |
88 | return iova_cache_get(); | |
89 | } | |
90 | ||
91 | /** | |
92 | * iommu_get_dma_cookie - Acquire DMA-API resources for a domain | |
93 | * @domain: IOMMU domain to prepare for DMA-API usage | |
94 | * | |
95 | * IOMMU drivers should normally call this from their domain_alloc | |
96 | * callback when domain->type == IOMMU_DOMAIN_DMA. | |
97 | */ | |
98 | int iommu_get_dma_cookie(struct iommu_domain *domain) | |
fdbe574e RM |
99 | { |
100 | if (domain->iova_cookie) | |
101 | return -EEXIST; | |
102 | ||
103 | domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE); | |
104 | if (!domain->iova_cookie) | |
105 | return -ENOMEM; | |
106 | ||
107 | return 0; | |
108 | } | |
109 | EXPORT_SYMBOL(iommu_get_dma_cookie); | |
110 | ||
111 | /** | |
112 | * iommu_get_msi_cookie - Acquire just MSI remapping resources | |
113 | * @domain: IOMMU domain to prepare | |
114 | * @base: Start address of IOVA region for MSI mappings | |
115 | * | |
116 | * Users who manage their own IOVA allocation and do not want DMA API support, | |
117 | * but would still like to take advantage of automatic MSI remapping, can use | |
118 | * this to initialise their own domain appropriately. Users should reserve a | |
119 | * contiguous IOVA region, starting at @base, large enough to accommodate the | |
120 | * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address | |
121 | * used by the devices attached to @domain. | |
122 | */ | |
123 | int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base) | |
0db2e5d1 | 124 | { |
44bb7e24 | 125 | struct iommu_dma_cookie *cookie; |
0db2e5d1 | 126 | |
fdbe574e RM |
127 | if (domain->type != IOMMU_DOMAIN_UNMANAGED) |
128 | return -EINVAL; | |
129 | ||
0db2e5d1 RM |
130 | if (domain->iova_cookie) |
131 | return -EEXIST; | |
132 | ||
fdbe574e | 133 | cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE); |
44bb7e24 RM |
134 | if (!cookie) |
135 | return -ENOMEM; | |
0db2e5d1 | 136 | |
fdbe574e | 137 | cookie->msi_iova = base; |
44bb7e24 RM |
138 | domain->iova_cookie = cookie; |
139 | return 0; | |
0db2e5d1 | 140 | } |
fdbe574e | 141 | EXPORT_SYMBOL(iommu_get_msi_cookie); |
0db2e5d1 RM |
142 | |
143 | /** | |
144 | * iommu_put_dma_cookie - Release a domain's DMA mapping resources | |
fdbe574e RM |
145 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or |
146 | * iommu_get_msi_cookie() | |
0db2e5d1 RM |
147 | * |
148 | * IOMMU drivers should normally call this from their domain_free callback. | |
149 | */ | |
150 | void iommu_put_dma_cookie(struct iommu_domain *domain) | |
151 | { | |
44bb7e24 RM |
152 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
153 | struct iommu_dma_msi_page *msi, *tmp; | |
0db2e5d1 | 154 | |
44bb7e24 | 155 | if (!cookie) |
0db2e5d1 RM |
156 | return; |
157 | ||
fdbe574e | 158 | if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule) |
44bb7e24 RM |
159 | put_iova_domain(&cookie->iovad); |
160 | ||
161 | list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) { | |
162 | list_del(&msi->list); | |
163 | kfree(msi); | |
164 | } | |
165 | kfree(cookie); | |
0db2e5d1 RM |
166 | domain->iova_cookie = NULL; |
167 | } | |
168 | EXPORT_SYMBOL(iommu_put_dma_cookie); | |
169 | ||
273df963 RM |
170 | /** |
171 | * iommu_dma_get_resv_regions - Reserved region driver helper | |
172 | * @dev: Device from iommu_get_resv_regions() | |
173 | * @list: Reserved region list from iommu_get_resv_regions() | |
174 | * | |
175 | * IOMMU drivers can use this to implement their .get_resv_regions callback | |
176 | * for general non-IOMMU-specific reservations. Currently, this covers host | |
177 | * bridge windows for PCI devices. | |
178 | */ | |
179 | void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list) | |
fade1ec0 | 180 | { |
273df963 | 181 | struct pci_host_bridge *bridge; |
fade1ec0 | 182 | struct resource_entry *window; |
fade1ec0 | 183 | |
273df963 RM |
184 | if (!dev_is_pci(dev)) |
185 | return; | |
186 | ||
187 | bridge = pci_find_host_bridge(to_pci_dev(dev)->bus); | |
fade1ec0 | 188 | resource_list_for_each_entry(window, &bridge->windows) { |
273df963 RM |
189 | struct iommu_resv_region *region; |
190 | phys_addr_t start; | |
191 | size_t length; | |
192 | ||
938f1bbe | 193 | if (resource_type(window->res) != IORESOURCE_MEM) |
fade1ec0 RM |
194 | continue; |
195 | ||
273df963 RM |
196 | start = window->res->start - window->offset; |
197 | length = window->res->end - window->res->start + 1; | |
198 | region = iommu_alloc_resv_region(start, length, 0, | |
199 | IOMMU_RESV_RESERVED); | |
200 | if (!region) | |
201 | return; | |
202 | ||
203 | list_add_tail(®ion->list, list); | |
fade1ec0 RM |
204 | } |
205 | } | |
273df963 | 206 | EXPORT_SYMBOL(iommu_dma_get_resv_regions); |
fade1ec0 | 207 | |
7c1b058c RM |
208 | static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie, |
209 | phys_addr_t start, phys_addr_t end) | |
210 | { | |
211 | struct iova_domain *iovad = &cookie->iovad; | |
212 | struct iommu_dma_msi_page *msi_page; | |
213 | int i, num_pages; | |
214 | ||
215 | start -= iova_offset(iovad, start); | |
216 | num_pages = iova_align(iovad, end - start) >> iova_shift(iovad); | |
217 | ||
218 | msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL); | |
219 | if (!msi_page) | |
220 | return -ENOMEM; | |
221 | ||
222 | for (i = 0; i < num_pages; i++) { | |
223 | msi_page[i].phys = start; | |
224 | msi_page[i].iova = start; | |
225 | INIT_LIST_HEAD(&msi_page[i].list); | |
226 | list_add(&msi_page[i].list, &cookie->msi_page_list); | |
227 | start += iovad->granule; | |
228 | } | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | static int iova_reserve_iommu_regions(struct device *dev, | |
234 | struct iommu_domain *domain) | |
235 | { | |
236 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
237 | struct iova_domain *iovad = &cookie->iovad; | |
238 | struct iommu_resv_region *region; | |
239 | LIST_HEAD(resv_regions); | |
240 | int ret = 0; | |
241 | ||
7c1b058c RM |
242 | iommu_get_resv_regions(dev, &resv_regions); |
243 | list_for_each_entry(region, &resv_regions, list) { | |
244 | unsigned long lo, hi; | |
245 | ||
246 | /* We ARE the software that manages these! */ | |
247 | if (region->type == IOMMU_RESV_SW_MSI) | |
248 | continue; | |
249 | ||
250 | lo = iova_pfn(iovad, region->start); | |
251 | hi = iova_pfn(iovad, region->start + region->length - 1); | |
252 | reserve_iova(iovad, lo, hi); | |
253 | ||
254 | if (region->type == IOMMU_RESV_MSI) | |
255 | ret = cookie_init_hw_msi_region(cookie, region->start, | |
256 | region->start + region->length); | |
257 | if (ret) | |
258 | break; | |
259 | } | |
260 | iommu_put_resv_regions(dev, &resv_regions); | |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
0db2e5d1 RM |
265 | /** |
266 | * iommu_dma_init_domain - Initialise a DMA mapping domain | |
267 | * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() | |
268 | * @base: IOVA at which the mappable address space starts | |
269 | * @size: Size of IOVA space | |
fade1ec0 | 270 | * @dev: Device the domain is being initialised for |
0db2e5d1 RM |
271 | * |
272 | * @base and @size should be exact multiples of IOMMU page granularity to | |
273 | * avoid rounding surprises. If necessary, we reserve the page at address 0 | |
274 | * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but | |
275 | * any change which could make prior IOVAs invalid will fail. | |
276 | */ | |
fade1ec0 RM |
277 | int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base, |
278 | u64 size, struct device *dev) | |
0db2e5d1 | 279 | { |
fdbe574e RM |
280 | struct iommu_dma_cookie *cookie = domain->iova_cookie; |
281 | struct iova_domain *iovad = &cookie->iovad; | |
0db2e5d1 RM |
282 | unsigned long order, base_pfn, end_pfn; |
283 | ||
fdbe574e RM |
284 | if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE) |
285 | return -EINVAL; | |
0db2e5d1 RM |
286 | |
287 | /* Use the smallest supported page size for IOVA granularity */ | |
d16e0faa | 288 | order = __ffs(domain->pgsize_bitmap); |
0db2e5d1 RM |
289 | base_pfn = max_t(unsigned long, 1, base >> order); |
290 | end_pfn = (base + size - 1) >> order; | |
291 | ||
292 | /* Check the domain allows at least some access to the device... */ | |
293 | if (domain->geometry.force_aperture) { | |
294 | if (base > domain->geometry.aperture_end || | |
295 | base + size <= domain->geometry.aperture_start) { | |
296 | pr_warn("specified DMA range outside IOMMU capability\n"); | |
297 | return -EFAULT; | |
298 | } | |
299 | /* ...then finally give it a kicking to make sure it fits */ | |
300 | base_pfn = max_t(unsigned long, base_pfn, | |
301 | domain->geometry.aperture_start >> order); | |
302 | end_pfn = min_t(unsigned long, end_pfn, | |
303 | domain->geometry.aperture_end >> order); | |
304 | } | |
f51d7bb7 RM |
305 | /* |
306 | * PCI devices may have larger DMA masks, but still prefer allocating | |
307 | * within a 32-bit mask to avoid DAC addressing. Such limitations don't | |
308 | * apply to the typical platform device, so for those we may as well | |
309 | * leave the cache limit at the top of their range to save an rb_last() | |
310 | * traversal on every allocation. | |
311 | */ | |
7c1b058c | 312 | if (dev && dev_is_pci(dev)) |
f51d7bb7 | 313 | end_pfn &= DMA_BIT_MASK(32) >> order; |
0db2e5d1 | 314 | |
f51d7bb7 | 315 | /* start_pfn is always nonzero for an already-initialised domain */ |
0db2e5d1 RM |
316 | if (iovad->start_pfn) { |
317 | if (1UL << order != iovad->granule || | |
f51d7bb7 | 318 | base_pfn != iovad->start_pfn) { |
0db2e5d1 RM |
319 | pr_warn("Incompatible range for DMA domain\n"); |
320 | return -EFAULT; | |
321 | } | |
f51d7bb7 RM |
322 | /* |
323 | * If we have devices with different DMA masks, move the free | |
324 | * area cache limit down for the benefit of the smaller one. | |
325 | */ | |
326 | iovad->dma_32bit_pfn = min(end_pfn, iovad->dma_32bit_pfn); | |
7c1b058c RM |
327 | |
328 | return 0; | |
0db2e5d1 | 329 | } |
7c1b058c RM |
330 | |
331 | init_iova_domain(iovad, 1UL << order, base_pfn, end_pfn); | |
332 | if (!dev) | |
333 | return 0; | |
334 | ||
335 | return iova_reserve_iommu_regions(dev, domain); | |
0db2e5d1 RM |
336 | } |
337 | EXPORT_SYMBOL(iommu_dma_init_domain); | |
338 | ||
339 | /** | |
737c85ca MH |
340 | * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API |
341 | * page flags. | |
0db2e5d1 RM |
342 | * @dir: Direction of DMA transfer |
343 | * @coherent: Is the DMA master cache-coherent? | |
737c85ca | 344 | * @attrs: DMA attributes for the mapping |
0db2e5d1 RM |
345 | * |
346 | * Return: corresponding IOMMU API page protection flags | |
347 | */ | |
737c85ca MH |
348 | int dma_info_to_prot(enum dma_data_direction dir, bool coherent, |
349 | unsigned long attrs) | |
0db2e5d1 RM |
350 | { |
351 | int prot = coherent ? IOMMU_CACHE : 0; | |
352 | ||
737c85ca MH |
353 | if (attrs & DMA_ATTR_PRIVILEGED) |
354 | prot |= IOMMU_PRIV; | |
355 | ||
0db2e5d1 RM |
356 | switch (dir) { |
357 | case DMA_BIDIRECTIONAL: | |
358 | return prot | IOMMU_READ | IOMMU_WRITE; | |
359 | case DMA_TO_DEVICE: | |
360 | return prot | IOMMU_READ; | |
361 | case DMA_FROM_DEVICE: | |
362 | return prot | IOMMU_WRITE; | |
363 | default: | |
364 | return 0; | |
365 | } | |
366 | } | |
367 | ||
c987ff0d | 368 | static struct iova *__alloc_iova(struct iommu_domain *domain, size_t size, |
122fac03 | 369 | dma_addr_t dma_limit, struct device *dev) |
0db2e5d1 | 370 | { |
44bb7e24 | 371 | struct iova_domain *iovad = cookie_iovad(domain); |
0db2e5d1 RM |
372 | unsigned long shift = iova_shift(iovad); |
373 | unsigned long length = iova_align(iovad, size) >> shift; | |
122fac03 | 374 | struct iova *iova = NULL; |
0db2e5d1 | 375 | |
c987ff0d RM |
376 | if (domain->geometry.force_aperture) |
377 | dma_limit = min(dma_limit, domain->geometry.aperture_end); | |
122fac03 RM |
378 | |
379 | /* Try to get PCI devices a SAC address */ | |
380 | if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) | |
381 | iova = alloc_iova(iovad, length, DMA_BIT_MASK(32) >> shift, | |
382 | true); | |
0db2e5d1 RM |
383 | /* |
384 | * Enforce size-alignment to be safe - there could perhaps be an | |
385 | * attribute to control this per-device, or at least per-domain... | |
386 | */ | |
122fac03 RM |
387 | if (!iova) |
388 | iova = alloc_iova(iovad, length, dma_limit >> shift, true); | |
389 | ||
390 | return iova; | |
0db2e5d1 RM |
391 | } |
392 | ||
393 | /* The IOVA allocator knows what we mapped, so just unmap whatever that was */ | |
394 | static void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr) | |
395 | { | |
44bb7e24 | 396 | struct iova_domain *iovad = cookie_iovad(domain); |
0db2e5d1 RM |
397 | unsigned long shift = iova_shift(iovad); |
398 | unsigned long pfn = dma_addr >> shift; | |
399 | struct iova *iova = find_iova(iovad, pfn); | |
400 | size_t size; | |
401 | ||
402 | if (WARN_ON(!iova)) | |
403 | return; | |
404 | ||
405 | size = iova_size(iova) << shift; | |
406 | size -= iommu_unmap(domain, pfn << shift, size); | |
407 | /* ...and if we can't, then something is horribly, horribly wrong */ | |
408 | WARN_ON(size > 0); | |
409 | __free_iova(iovad, iova); | |
410 | } | |
411 | ||
412 | static void __iommu_dma_free_pages(struct page **pages, int count) | |
413 | { | |
414 | while (count--) | |
415 | __free_page(pages[count]); | |
416 | kvfree(pages); | |
417 | } | |
418 | ||
3b6b7e19 RM |
419 | static struct page **__iommu_dma_alloc_pages(unsigned int count, |
420 | unsigned long order_mask, gfp_t gfp) | |
0db2e5d1 RM |
421 | { |
422 | struct page **pages; | |
423 | unsigned int i = 0, array_size = count * sizeof(*pages); | |
3b6b7e19 RM |
424 | |
425 | order_mask &= (2U << MAX_ORDER) - 1; | |
426 | if (!order_mask) | |
427 | return NULL; | |
0db2e5d1 RM |
428 | |
429 | if (array_size <= PAGE_SIZE) | |
430 | pages = kzalloc(array_size, GFP_KERNEL); | |
431 | else | |
432 | pages = vzalloc(array_size); | |
433 | if (!pages) | |
434 | return NULL; | |
435 | ||
436 | /* IOMMU can map any pages, so himem can also be used here */ | |
437 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
438 | ||
439 | while (count) { | |
440 | struct page *page = NULL; | |
3b6b7e19 | 441 | unsigned int order_size; |
0db2e5d1 RM |
442 | |
443 | /* | |
444 | * Higher-order allocations are a convenience rather | |
445 | * than a necessity, hence using __GFP_NORETRY until | |
3b6b7e19 | 446 | * falling back to minimum-order allocations. |
0db2e5d1 | 447 | */ |
3b6b7e19 RM |
448 | for (order_mask &= (2U << __fls(count)) - 1; |
449 | order_mask; order_mask &= ~order_size) { | |
450 | unsigned int order = __fls(order_mask); | |
451 | ||
452 | order_size = 1U << order; | |
453 | page = alloc_pages((order_mask - order_size) ? | |
454 | gfp | __GFP_NORETRY : gfp, order); | |
0db2e5d1 RM |
455 | if (!page) |
456 | continue; | |
3b6b7e19 RM |
457 | if (!order) |
458 | break; | |
459 | if (!PageCompound(page)) { | |
0db2e5d1 RM |
460 | split_page(page, order); |
461 | break; | |
3b6b7e19 RM |
462 | } else if (!split_huge_page(page)) { |
463 | break; | |
0db2e5d1 | 464 | } |
3b6b7e19 | 465 | __free_pages(page, order); |
0db2e5d1 | 466 | } |
0db2e5d1 RM |
467 | if (!page) { |
468 | __iommu_dma_free_pages(pages, i); | |
469 | return NULL; | |
470 | } | |
3b6b7e19 RM |
471 | count -= order_size; |
472 | while (order_size--) | |
0db2e5d1 RM |
473 | pages[i++] = page++; |
474 | } | |
475 | return pages; | |
476 | } | |
477 | ||
478 | /** | |
479 | * iommu_dma_free - Free a buffer allocated by iommu_dma_alloc() | |
480 | * @dev: Device which owns this buffer | |
481 | * @pages: Array of buffer pages as returned by iommu_dma_alloc() | |
482 | * @size: Size of buffer in bytes | |
483 | * @handle: DMA address of buffer | |
484 | * | |
485 | * Frees both the pages associated with the buffer, and the array | |
486 | * describing them | |
487 | */ | |
488 | void iommu_dma_free(struct device *dev, struct page **pages, size_t size, | |
489 | dma_addr_t *handle) | |
490 | { | |
491 | __iommu_dma_unmap(iommu_get_domain_for_dev(dev), *handle); | |
492 | __iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT); | |
493 | *handle = DMA_ERROR_CODE; | |
494 | } | |
495 | ||
496 | /** | |
497 | * iommu_dma_alloc - Allocate and map a buffer contiguous in IOVA space | |
498 | * @dev: Device to allocate memory for. Must be a real device | |
499 | * attached to an iommu_dma_domain | |
500 | * @size: Size of buffer in bytes | |
501 | * @gfp: Allocation flags | |
3b6b7e19 | 502 | * @attrs: DMA attributes for this allocation |
0db2e5d1 RM |
503 | * @prot: IOMMU mapping flags |
504 | * @handle: Out argument for allocated DMA handle | |
505 | * @flush_page: Arch callback which must ensure PAGE_SIZE bytes from the | |
506 | * given VA/PA are visible to the given non-coherent device. | |
507 | * | |
508 | * If @size is less than PAGE_SIZE, then a full CPU page will be allocated, | |
509 | * but an IOMMU which supports smaller pages might not map the whole thing. | |
510 | * | |
511 | * Return: Array of struct page pointers describing the buffer, | |
512 | * or NULL on failure. | |
513 | */ | |
3b6b7e19 | 514 | struct page **iommu_dma_alloc(struct device *dev, size_t size, gfp_t gfp, |
00085f1e | 515 | unsigned long attrs, int prot, dma_addr_t *handle, |
0db2e5d1 RM |
516 | void (*flush_page)(struct device *, const void *, phys_addr_t)) |
517 | { | |
518 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
44bb7e24 | 519 | struct iova_domain *iovad = cookie_iovad(domain); |
0db2e5d1 RM |
520 | struct iova *iova; |
521 | struct page **pages; | |
522 | struct sg_table sgt; | |
523 | dma_addr_t dma_addr; | |
3b6b7e19 | 524 | unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap; |
0db2e5d1 RM |
525 | |
526 | *handle = DMA_ERROR_CODE; | |
527 | ||
3b6b7e19 RM |
528 | min_size = alloc_sizes & -alloc_sizes; |
529 | if (min_size < PAGE_SIZE) { | |
530 | min_size = PAGE_SIZE; | |
531 | alloc_sizes |= PAGE_SIZE; | |
532 | } else { | |
533 | size = ALIGN(size, min_size); | |
534 | } | |
00085f1e | 535 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
3b6b7e19 RM |
536 | alloc_sizes = min_size; |
537 | ||
538 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
539 | pages = __iommu_dma_alloc_pages(count, alloc_sizes >> PAGE_SHIFT, gfp); | |
0db2e5d1 RM |
540 | if (!pages) |
541 | return NULL; | |
542 | ||
122fac03 | 543 | iova = __alloc_iova(domain, size, dev->coherent_dma_mask, dev); |
0db2e5d1 RM |
544 | if (!iova) |
545 | goto out_free_pages; | |
546 | ||
547 | size = iova_align(iovad, size); | |
548 | if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL)) | |
549 | goto out_free_iova; | |
550 | ||
551 | if (!(prot & IOMMU_CACHE)) { | |
552 | struct sg_mapping_iter miter; | |
553 | /* | |
554 | * The CPU-centric flushing implied by SG_MITER_TO_SG isn't | |
555 | * sufficient here, so skip it by using the "wrong" direction. | |
556 | */ | |
557 | sg_miter_start(&miter, sgt.sgl, sgt.orig_nents, SG_MITER_FROM_SG); | |
558 | while (sg_miter_next(&miter)) | |
559 | flush_page(dev, miter.addr, page_to_phys(miter.page)); | |
560 | sg_miter_stop(&miter); | |
561 | } | |
562 | ||
563 | dma_addr = iova_dma_addr(iovad, iova); | |
564 | if (iommu_map_sg(domain, dma_addr, sgt.sgl, sgt.orig_nents, prot) | |
565 | < size) | |
566 | goto out_free_sg; | |
567 | ||
568 | *handle = dma_addr; | |
569 | sg_free_table(&sgt); | |
570 | return pages; | |
571 | ||
572 | out_free_sg: | |
573 | sg_free_table(&sgt); | |
574 | out_free_iova: | |
575 | __free_iova(iovad, iova); | |
576 | out_free_pages: | |
577 | __iommu_dma_free_pages(pages, count); | |
578 | return NULL; | |
579 | } | |
580 | ||
581 | /** | |
582 | * iommu_dma_mmap - Map a buffer into provided user VMA | |
583 | * @pages: Array representing buffer from iommu_dma_alloc() | |
584 | * @size: Size of buffer in bytes | |
585 | * @vma: VMA describing requested userspace mapping | |
586 | * | |
587 | * Maps the pages of the buffer in @pages into @vma. The caller is responsible | |
588 | * for verifying the correct size and protection of @vma beforehand. | |
589 | */ | |
590 | ||
591 | int iommu_dma_mmap(struct page **pages, size_t size, struct vm_area_struct *vma) | |
592 | { | |
593 | unsigned long uaddr = vma->vm_start; | |
594 | unsigned int i, count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
595 | int ret = -ENXIO; | |
596 | ||
597 | for (i = vma->vm_pgoff; i < count && uaddr < vma->vm_end; i++) { | |
598 | ret = vm_insert_page(vma, uaddr, pages[i]); | |
599 | if (ret) | |
600 | break; | |
601 | uaddr += PAGE_SIZE; | |
602 | } | |
603 | return ret; | |
604 | } | |
605 | ||
51f8cc9e RM |
606 | static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys, |
607 | size_t size, int prot) | |
0db2e5d1 RM |
608 | { |
609 | dma_addr_t dma_addr; | |
610 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
44bb7e24 | 611 | struct iova_domain *iovad = cookie_iovad(domain); |
0db2e5d1 RM |
612 | size_t iova_off = iova_offset(iovad, phys); |
613 | size_t len = iova_align(iovad, size + iova_off); | |
122fac03 | 614 | struct iova *iova = __alloc_iova(domain, len, dma_get_mask(dev), dev); |
0db2e5d1 RM |
615 | |
616 | if (!iova) | |
617 | return DMA_ERROR_CODE; | |
618 | ||
619 | dma_addr = iova_dma_addr(iovad, iova); | |
620 | if (iommu_map(domain, dma_addr, phys - iova_off, len, prot)) { | |
621 | __free_iova(iovad, iova); | |
622 | return DMA_ERROR_CODE; | |
623 | } | |
624 | return dma_addr + iova_off; | |
625 | } | |
626 | ||
51f8cc9e RM |
627 | dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page, |
628 | unsigned long offset, size_t size, int prot) | |
629 | { | |
630 | return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot); | |
631 | } | |
632 | ||
0db2e5d1 | 633 | void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size, |
00085f1e | 634 | enum dma_data_direction dir, unsigned long attrs) |
0db2e5d1 RM |
635 | { |
636 | __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle); | |
637 | } | |
638 | ||
639 | /* | |
640 | * Prepare a successfully-mapped scatterlist to give back to the caller. | |
809eac54 RM |
641 | * |
642 | * At this point the segments are already laid out by iommu_dma_map_sg() to | |
643 | * avoid individually crossing any boundaries, so we merely need to check a | |
644 | * segment's start address to avoid concatenating across one. | |
0db2e5d1 RM |
645 | */ |
646 | static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents, | |
647 | dma_addr_t dma_addr) | |
648 | { | |
809eac54 RM |
649 | struct scatterlist *s, *cur = sg; |
650 | unsigned long seg_mask = dma_get_seg_boundary(dev); | |
651 | unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev); | |
652 | int i, count = 0; | |
0db2e5d1 RM |
653 | |
654 | for_each_sg(sg, s, nents, i) { | |
809eac54 RM |
655 | /* Restore this segment's original unaligned fields first */ |
656 | unsigned int s_iova_off = sg_dma_address(s); | |
0db2e5d1 | 657 | unsigned int s_length = sg_dma_len(s); |
809eac54 | 658 | unsigned int s_iova_len = s->length; |
0db2e5d1 | 659 | |
809eac54 | 660 | s->offset += s_iova_off; |
0db2e5d1 | 661 | s->length = s_length; |
809eac54 RM |
662 | sg_dma_address(s) = DMA_ERROR_CODE; |
663 | sg_dma_len(s) = 0; | |
664 | ||
665 | /* | |
666 | * Now fill in the real DMA data. If... | |
667 | * - there is a valid output segment to append to | |
668 | * - and this segment starts on an IOVA page boundary | |
669 | * - but doesn't fall at a segment boundary | |
670 | * - and wouldn't make the resulting output segment too long | |
671 | */ | |
672 | if (cur_len && !s_iova_off && (dma_addr & seg_mask) && | |
673 | (cur_len + s_length <= max_len)) { | |
674 | /* ...then concatenate it with the previous one */ | |
675 | cur_len += s_length; | |
676 | } else { | |
677 | /* Otherwise start the next output segment */ | |
678 | if (i > 0) | |
679 | cur = sg_next(cur); | |
680 | cur_len = s_length; | |
681 | count++; | |
682 | ||
683 | sg_dma_address(cur) = dma_addr + s_iova_off; | |
684 | } | |
685 | ||
686 | sg_dma_len(cur) = cur_len; | |
687 | dma_addr += s_iova_len; | |
688 | ||
689 | if (s_length + s_iova_off < s_iova_len) | |
690 | cur_len = 0; | |
0db2e5d1 | 691 | } |
809eac54 | 692 | return count; |
0db2e5d1 RM |
693 | } |
694 | ||
695 | /* | |
696 | * If mapping failed, then just restore the original list, | |
697 | * but making sure the DMA fields are invalidated. | |
698 | */ | |
699 | static void __invalidate_sg(struct scatterlist *sg, int nents) | |
700 | { | |
701 | struct scatterlist *s; | |
702 | int i; | |
703 | ||
704 | for_each_sg(sg, s, nents, i) { | |
705 | if (sg_dma_address(s) != DMA_ERROR_CODE) | |
07b48ac4 | 706 | s->offset += sg_dma_address(s); |
0db2e5d1 RM |
707 | if (sg_dma_len(s)) |
708 | s->length = sg_dma_len(s); | |
709 | sg_dma_address(s) = DMA_ERROR_CODE; | |
710 | sg_dma_len(s) = 0; | |
711 | } | |
712 | } | |
713 | ||
714 | /* | |
715 | * The DMA API client is passing in a scatterlist which could describe | |
716 | * any old buffer layout, but the IOMMU API requires everything to be | |
717 | * aligned to IOMMU pages. Hence the need for this complicated bit of | |
718 | * impedance-matching, to be able to hand off a suitably-aligned list, | |
719 | * but still preserve the original offsets and sizes for the caller. | |
720 | */ | |
721 | int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg, | |
722 | int nents, int prot) | |
723 | { | |
724 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
44bb7e24 | 725 | struct iova_domain *iovad = cookie_iovad(domain); |
0db2e5d1 RM |
726 | struct iova *iova; |
727 | struct scatterlist *s, *prev = NULL; | |
728 | dma_addr_t dma_addr; | |
729 | size_t iova_len = 0; | |
809eac54 | 730 | unsigned long mask = dma_get_seg_boundary(dev); |
0db2e5d1 RM |
731 | int i; |
732 | ||
733 | /* | |
734 | * Work out how much IOVA space we need, and align the segments to | |
735 | * IOVA granules for the IOMMU driver to handle. With some clever | |
736 | * trickery we can modify the list in-place, but reversibly, by | |
809eac54 | 737 | * stashing the unaligned parts in the as-yet-unused DMA fields. |
0db2e5d1 RM |
738 | */ |
739 | for_each_sg(sg, s, nents, i) { | |
809eac54 | 740 | size_t s_iova_off = iova_offset(iovad, s->offset); |
0db2e5d1 | 741 | size_t s_length = s->length; |
809eac54 | 742 | size_t pad_len = (mask - iova_len + 1) & mask; |
0db2e5d1 | 743 | |
809eac54 | 744 | sg_dma_address(s) = s_iova_off; |
0db2e5d1 | 745 | sg_dma_len(s) = s_length; |
809eac54 RM |
746 | s->offset -= s_iova_off; |
747 | s_length = iova_align(iovad, s_length + s_iova_off); | |
0db2e5d1 RM |
748 | s->length = s_length; |
749 | ||
750 | /* | |
809eac54 RM |
751 | * Due to the alignment of our single IOVA allocation, we can |
752 | * depend on these assumptions about the segment boundary mask: | |
753 | * - If mask size >= IOVA size, then the IOVA range cannot | |
754 | * possibly fall across a boundary, so we don't care. | |
755 | * - If mask size < IOVA size, then the IOVA range must start | |
756 | * exactly on a boundary, therefore we can lay things out | |
757 | * based purely on segment lengths without needing to know | |
758 | * the actual addresses beforehand. | |
759 | * - The mask must be a power of 2, so pad_len == 0 if | |
760 | * iova_len == 0, thus we cannot dereference prev the first | |
761 | * time through here (i.e. before it has a meaningful value). | |
0db2e5d1 | 762 | */ |
809eac54 | 763 | if (pad_len && pad_len < s_length - 1) { |
0db2e5d1 RM |
764 | prev->length += pad_len; |
765 | iova_len += pad_len; | |
766 | } | |
767 | ||
768 | iova_len += s_length; | |
769 | prev = s; | |
770 | } | |
771 | ||
122fac03 | 772 | iova = __alloc_iova(domain, iova_len, dma_get_mask(dev), dev); |
0db2e5d1 RM |
773 | if (!iova) |
774 | goto out_restore_sg; | |
775 | ||
776 | /* | |
777 | * We'll leave any physical concatenation to the IOMMU driver's | |
778 | * implementation - it knows better than we do. | |
779 | */ | |
780 | dma_addr = iova_dma_addr(iovad, iova); | |
781 | if (iommu_map_sg(domain, dma_addr, sg, nents, prot) < iova_len) | |
782 | goto out_free_iova; | |
783 | ||
784 | return __finalise_sg(dev, sg, nents, dma_addr); | |
785 | ||
786 | out_free_iova: | |
787 | __free_iova(iovad, iova); | |
788 | out_restore_sg: | |
789 | __invalidate_sg(sg, nents); | |
790 | return 0; | |
791 | } | |
792 | ||
793 | void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
00085f1e | 794 | enum dma_data_direction dir, unsigned long attrs) |
0db2e5d1 RM |
795 | { |
796 | /* | |
797 | * The scatterlist segments are mapped into a single | |
798 | * contiguous IOVA allocation, so this is incredibly easy. | |
799 | */ | |
800 | __iommu_dma_unmap(iommu_get_domain_for_dev(dev), sg_dma_address(sg)); | |
801 | } | |
802 | ||
51f8cc9e RM |
803 | dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys, |
804 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
805 | { | |
806 | return __iommu_dma_map(dev, phys, size, | |
737c85ca | 807 | dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO); |
51f8cc9e RM |
808 | } |
809 | ||
810 | void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle, | |
811 | size_t size, enum dma_data_direction dir, unsigned long attrs) | |
812 | { | |
813 | __iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle); | |
814 | } | |
815 | ||
0db2e5d1 RM |
816 | int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
817 | { | |
818 | return dma_addr == DMA_ERROR_CODE; | |
819 | } | |
44bb7e24 RM |
820 | |
821 | static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, | |
822 | phys_addr_t msi_addr, struct iommu_domain *domain) | |
823 | { | |
824 | struct iommu_dma_cookie *cookie = domain->iova_cookie; | |
825 | struct iommu_dma_msi_page *msi_page; | |
fdbe574e | 826 | struct iova_domain *iovad = cookie_iovad(domain); |
44bb7e24 RM |
827 | struct iova *iova; |
828 | int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; | |
fdbe574e | 829 | size_t size = cookie_msi_granule(cookie); |
44bb7e24 | 830 | |
fdbe574e | 831 | msi_addr &= ~(phys_addr_t)(size - 1); |
44bb7e24 RM |
832 | list_for_each_entry(msi_page, &cookie->msi_page_list, list) |
833 | if (msi_page->phys == msi_addr) | |
834 | return msi_page; | |
835 | ||
836 | msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC); | |
837 | if (!msi_page) | |
838 | return NULL; | |
839 | ||
44bb7e24 | 840 | msi_page->phys = msi_addr; |
fdbe574e | 841 | if (iovad) { |
122fac03 | 842 | iova = __alloc_iova(domain, size, dma_get_mask(dev), dev); |
fdbe574e RM |
843 | if (!iova) |
844 | goto out_free_page; | |
845 | msi_page->iova = iova_dma_addr(iovad, iova); | |
846 | } else { | |
847 | msi_page->iova = cookie->msi_iova; | |
848 | cookie->msi_iova += size; | |
849 | } | |
850 | ||
851 | if (iommu_map(domain, msi_page->iova, msi_addr, size, prot)) | |
44bb7e24 RM |
852 | goto out_free_iova; |
853 | ||
854 | INIT_LIST_HEAD(&msi_page->list); | |
855 | list_add(&msi_page->list, &cookie->msi_page_list); | |
856 | return msi_page; | |
857 | ||
858 | out_free_iova: | |
fdbe574e RM |
859 | if (iovad) |
860 | __free_iova(iovad, iova); | |
861 | else | |
862 | cookie->msi_iova -= size; | |
44bb7e24 RM |
863 | out_free_page: |
864 | kfree(msi_page); | |
865 | return NULL; | |
866 | } | |
867 | ||
868 | void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg) | |
869 | { | |
870 | struct device *dev = msi_desc_to_dev(irq_get_msi_desc(irq)); | |
871 | struct iommu_domain *domain = iommu_get_domain_for_dev(dev); | |
872 | struct iommu_dma_cookie *cookie; | |
873 | struct iommu_dma_msi_page *msi_page; | |
874 | phys_addr_t msi_addr = (u64)msg->address_hi << 32 | msg->address_lo; | |
875 | unsigned long flags; | |
876 | ||
877 | if (!domain || !domain->iova_cookie) | |
878 | return; | |
879 | ||
880 | cookie = domain->iova_cookie; | |
881 | ||
882 | /* | |
883 | * We disable IRQs to rule out a possible inversion against | |
884 | * irq_desc_lock if, say, someone tries to retarget the affinity | |
885 | * of an MSI from within an IPI handler. | |
886 | */ | |
887 | spin_lock_irqsave(&cookie->msi_lock, flags); | |
888 | msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain); | |
889 | spin_unlock_irqrestore(&cookie->msi_lock, flags); | |
890 | ||
891 | if (WARN_ON(!msi_page)) { | |
892 | /* | |
893 | * We're called from a void callback, so the best we can do is | |
894 | * 'fail' by filling the message with obviously bogus values. | |
895 | * Since we got this far due to an IOMMU being present, it's | |
896 | * not like the existing address would have worked anyway... | |
897 | */ | |
898 | msg->address_hi = ~0U; | |
899 | msg->address_lo = ~0U; | |
900 | msg->data = ~0U; | |
901 | } else { | |
902 | msg->address_hi = upper_32_bits(msi_page->iova); | |
fdbe574e | 903 | msg->address_lo &= cookie_msi_granule(cookie) - 1; |
44bb7e24 RM |
904 | msg->address_lo += lower_32_bits(msi_page->iova); |
905 | } | |
906 | } |