]>
Commit | Line | Data |
---|---|---|
10e5247f KA |
1 | /* |
2 | * Copyright (c) 2006, Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program; if not, write to the Free Software Foundation, Inc., 59 Temple | |
15 | * Place - Suite 330, Boston, MA 02111-1307 USA. | |
16 | * | |
98bcef56 | 17 | * Copyright (C) 2006-2008 Intel Corporation |
18 | * Author: Ashok Raj <ashok.raj@intel.com> | |
19 | * Author: Shaohua Li <shaohua.li@intel.com> | |
20 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 21 | * |
e61d98d8 | 22 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
23 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
24 | * tables. | |
e61d98d8 SS |
25 | * |
26 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
27 | */ |
28 | ||
9f10e5bf | 29 | #define pr_fmt(fmt) "DMAR: " fmt |
e9071b0b | 30 | |
10e5247f KA |
31 | #include <linux/pci.h> |
32 | #include <linux/dmar.h> | |
38717946 KA |
33 | #include <linux/iova.h> |
34 | #include <linux/intel-iommu.h> | |
fe962e90 | 35 | #include <linux/timer.h> |
0ac2491f SS |
36 | #include <linux/irq.h> |
37 | #include <linux/interrupt.h> | |
69575d38 | 38 | #include <linux/tboot.h> |
eb27cae8 | 39 | #include <linux/dmi.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
a5459cfe | 41 | #include <linux/iommu.h> |
8a8f422d | 42 | #include <asm/irq_remapping.h> |
4db77ff3 | 43 | #include <asm/iommu_table.h> |
10e5247f | 44 | |
078e1ee2 JR |
45 | #include "irq_remapping.h" |
46 | ||
c2a0b538 JL |
47 | typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *); |
48 | struct dmar_res_callback { | |
49 | dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED]; | |
50 | void *arg[ACPI_DMAR_TYPE_RESERVED]; | |
51 | bool ignore_unhandled; | |
52 | bool print_entry; | |
53 | }; | |
54 | ||
3a5670e8 JL |
55 | /* |
56 | * Assumptions: | |
57 | * 1) The hotplug framework guarentees that DMAR unit will be hot-added | |
58 | * before IO devices managed by that unit. | |
59 | * 2) The hotplug framework guarantees that DMAR unit will be hot-removed | |
60 | * after IO devices managed by that unit. | |
61 | * 3) Hotplug events are rare. | |
62 | * | |
63 | * Locking rules for DMA and interrupt remapping related global data structures: | |
64 | * 1) Use dmar_global_lock in process context | |
65 | * 2) Use RCU in interrupt context | |
10e5247f | 66 | */ |
3a5670e8 | 67 | DECLARE_RWSEM(dmar_global_lock); |
10e5247f | 68 | LIST_HEAD(dmar_drhd_units); |
10e5247f | 69 | |
41750d31 | 70 | struct acpi_table_header * __initdata dmar_tbl; |
2e455289 | 71 | static int dmar_dev_scope_status = 1; |
78d8e704 | 72 | static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)]; |
10e5247f | 73 | |
694835dc | 74 | static int alloc_iommu(struct dmar_drhd_unit *drhd); |
a868e6b7 | 75 | static void free_iommu(struct intel_iommu *iommu); |
694835dc | 76 | |
b0119e87 JR |
77 | extern const struct iommu_ops intel_iommu_ops; |
78 | ||
6b197249 | 79 | static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) |
10e5247f KA |
80 | { |
81 | /* | |
82 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
83 | * the very end. | |
84 | */ | |
85 | if (drhd->include_all) | |
0e242612 | 86 | list_add_tail_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f | 87 | else |
0e242612 | 88 | list_add_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f KA |
89 | } |
90 | ||
bb3a6b78 | 91 | void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) |
10e5247f KA |
92 | { |
93 | struct acpi_dmar_device_scope *scope; | |
10e5247f KA |
94 | |
95 | *cnt = 0; | |
96 | while (start < end) { | |
97 | scope = start; | |
83118b0d | 98 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || |
07cb52ff | 99 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || |
10e5247f KA |
100 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) |
101 | (*cnt)++; | |
ae3e7f3a LC |
102 | else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && |
103 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { | |
e9071b0b | 104 | pr_warn("Unsupported device scope\n"); |
5715f0f9 | 105 | } |
10e5247f KA |
106 | start += scope->length; |
107 | } | |
108 | if (*cnt == 0) | |
bb3a6b78 JL |
109 | return NULL; |
110 | ||
832bd858 | 111 | return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL); |
bb3a6b78 JL |
112 | } |
113 | ||
832bd858 | 114 | void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt) |
ada4d4b2 | 115 | { |
b683b230 | 116 | int i; |
832bd858 | 117 | struct device *tmp_dev; |
b683b230 | 118 | |
ada4d4b2 | 119 | if (*devices && *cnt) { |
b683b230 | 120 | for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) |
832bd858 | 121 | put_device(tmp_dev); |
ada4d4b2 | 122 | kfree(*devices); |
ada4d4b2 | 123 | } |
0e242612 JL |
124 | |
125 | *devices = NULL; | |
126 | *cnt = 0; | |
ada4d4b2 JL |
127 | } |
128 | ||
59ce0515 JL |
129 | /* Optimize out kzalloc()/kfree() for normal cases */ |
130 | static char dmar_pci_notify_info_buf[64]; | |
131 | ||
132 | static struct dmar_pci_notify_info * | |
133 | dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) | |
134 | { | |
135 | int level = 0; | |
136 | size_t size; | |
137 | struct pci_dev *tmp; | |
138 | struct dmar_pci_notify_info *info; | |
139 | ||
140 | BUG_ON(dev->is_virtfn); | |
141 | ||
142 | /* Only generate path[] for device addition event */ | |
143 | if (event == BUS_NOTIFY_ADD_DEVICE) | |
144 | for (tmp = dev; tmp; tmp = tmp->bus->self) | |
145 | level++; | |
146 | ||
147 | size = sizeof(*info) + level * sizeof(struct acpi_dmar_pci_path); | |
148 | if (size <= sizeof(dmar_pci_notify_info_buf)) { | |
149 | info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; | |
150 | } else { | |
151 | info = kzalloc(size, GFP_KERNEL); | |
152 | if (!info) { | |
153 | pr_warn("Out of memory when allocating notify_info " | |
154 | "for %s.\n", pci_name(dev)); | |
2e455289 JL |
155 | if (dmar_dev_scope_status == 0) |
156 | dmar_dev_scope_status = -ENOMEM; | |
59ce0515 JL |
157 | return NULL; |
158 | } | |
159 | } | |
160 | ||
161 | info->event = event; | |
162 | info->dev = dev; | |
163 | info->seg = pci_domain_nr(dev->bus); | |
164 | info->level = level; | |
165 | if (event == BUS_NOTIFY_ADD_DEVICE) { | |
5ae0566a JL |
166 | for (tmp = dev; tmp; tmp = tmp->bus->self) { |
167 | level--; | |
57384592 | 168 | info->path[level].bus = tmp->bus->number; |
59ce0515 JL |
169 | info->path[level].device = PCI_SLOT(tmp->devfn); |
170 | info->path[level].function = PCI_FUNC(tmp->devfn); | |
171 | if (pci_is_root_bus(tmp->bus)) | |
172 | info->bus = tmp->bus->number; | |
173 | } | |
174 | } | |
175 | ||
176 | return info; | |
177 | } | |
178 | ||
179 | static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) | |
180 | { | |
181 | if ((void *)info != dmar_pci_notify_info_buf) | |
182 | kfree(info); | |
183 | } | |
184 | ||
185 | static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, | |
186 | struct acpi_dmar_pci_path *path, int count) | |
187 | { | |
188 | int i; | |
189 | ||
190 | if (info->bus != bus) | |
80f7b3d1 | 191 | goto fallback; |
59ce0515 | 192 | if (info->level != count) |
80f7b3d1 | 193 | goto fallback; |
59ce0515 JL |
194 | |
195 | for (i = 0; i < count; i++) { | |
196 | if (path[i].device != info->path[i].device || | |
197 | path[i].function != info->path[i].function) | |
80f7b3d1 | 198 | goto fallback; |
59ce0515 JL |
199 | } |
200 | ||
201 | return true; | |
80f7b3d1 JR |
202 | |
203 | fallback: | |
204 | ||
205 | if (count != 1) | |
206 | return false; | |
207 | ||
208 | i = info->level - 1; | |
209 | if (bus == info->path[i].bus && | |
210 | path[0].device == info->path[i].device && | |
211 | path[0].function == info->path[i].function) { | |
212 | pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", | |
213 | bus, path[0].device, path[0].function); | |
214 | return true; | |
215 | } | |
216 | ||
217 | return false; | |
59ce0515 JL |
218 | } |
219 | ||
220 | /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ | |
221 | int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, | |
222 | void *start, void*end, u16 segment, | |
832bd858 DW |
223 | struct dmar_dev_scope *devices, |
224 | int devices_cnt) | |
59ce0515 JL |
225 | { |
226 | int i, level; | |
832bd858 | 227 | struct device *tmp, *dev = &info->dev->dev; |
59ce0515 JL |
228 | struct acpi_dmar_device_scope *scope; |
229 | struct acpi_dmar_pci_path *path; | |
230 | ||
231 | if (segment != info->seg) | |
232 | return 0; | |
233 | ||
234 | for (; start < end; start += scope->length) { | |
235 | scope = start; | |
236 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
237 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
238 | continue; | |
239 | ||
240 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
241 | level = (scope->length - sizeof(*scope)) / sizeof(*path); | |
242 | if (!dmar_match_pci_path(info, scope->bus, path, level)) | |
243 | continue; | |
244 | ||
ffb2d1eb RD |
245 | /* |
246 | * We expect devices with endpoint scope to have normal PCI | |
247 | * headers, and devices with bridge scope to have bridge PCI | |
248 | * headers. However PCI NTB devices may be listed in the | |
249 | * DMAR table with bridge scope, even though they have a | |
250 | * normal PCI header. NTB devices are identified by class | |
251 | * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch | |
252 | * for this special case. | |
253 | */ | |
254 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
255 | info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || | |
256 | (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && | |
257 | (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
258 | info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) { | |
59ce0515 | 259 | pr_warn("Device scope type does not match for %s\n", |
832bd858 | 260 | pci_name(info->dev)); |
59ce0515 JL |
261 | return -EINVAL; |
262 | } | |
263 | ||
264 | for_each_dev_scope(devices, devices_cnt, i, tmp) | |
265 | if (tmp == NULL) { | |
832bd858 DW |
266 | devices[i].bus = info->dev->bus->number; |
267 | devices[i].devfn = info->dev->devfn; | |
268 | rcu_assign_pointer(devices[i].dev, | |
269 | get_device(dev)); | |
59ce0515 JL |
270 | return 1; |
271 | } | |
272 | BUG_ON(i >= devices_cnt); | |
273 | } | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, | |
832bd858 | 279 | struct dmar_dev_scope *devices, int count) |
59ce0515 JL |
280 | { |
281 | int index; | |
832bd858 | 282 | struct device *tmp; |
59ce0515 JL |
283 | |
284 | if (info->seg != segment) | |
285 | return 0; | |
286 | ||
287 | for_each_active_dev_scope(devices, count, index, tmp) | |
832bd858 | 288 | if (tmp == &info->dev->dev) { |
eecbad7d | 289 | RCU_INIT_POINTER(devices[index].dev, NULL); |
59ce0515 | 290 | synchronize_rcu(); |
832bd858 | 291 | put_device(tmp); |
59ce0515 JL |
292 | return 1; |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) | |
299 | { | |
300 | int ret = 0; | |
301 | struct dmar_drhd_unit *dmaru; | |
302 | struct acpi_dmar_hardware_unit *drhd; | |
303 | ||
304 | for_each_drhd_unit(dmaru) { | |
305 | if (dmaru->include_all) | |
306 | continue; | |
307 | ||
308 | drhd = container_of(dmaru->hdr, | |
309 | struct acpi_dmar_hardware_unit, header); | |
310 | ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), | |
311 | ((void *)drhd) + drhd->header.length, | |
312 | dmaru->segment, | |
313 | dmaru->devices, dmaru->devices_cnt); | |
f9808079 | 314 | if (ret) |
59ce0515 JL |
315 | break; |
316 | } | |
317 | if (ret >= 0) | |
318 | ret = dmar_iommu_notify_scope_dev(info); | |
2e455289 JL |
319 | if (ret < 0 && dmar_dev_scope_status == 0) |
320 | dmar_dev_scope_status = ret; | |
59ce0515 JL |
321 | |
322 | return ret; | |
323 | } | |
324 | ||
325 | static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) | |
326 | { | |
327 | struct dmar_drhd_unit *dmaru; | |
328 | ||
329 | for_each_drhd_unit(dmaru) | |
330 | if (dmar_remove_dev_scope(info, dmaru->segment, | |
331 | dmaru->devices, dmaru->devices_cnt)) | |
332 | break; | |
333 | dmar_iommu_notify_scope_dev(info); | |
334 | } | |
335 | ||
336 | static int dmar_pci_bus_notifier(struct notifier_block *nb, | |
337 | unsigned long action, void *data) | |
338 | { | |
339 | struct pci_dev *pdev = to_pci_dev(data); | |
340 | struct dmar_pci_notify_info *info; | |
341 | ||
1c387188 AR |
342 | /* Only care about add/remove events for physical functions. |
343 | * For VFs we actually do the lookup based on the corresponding | |
344 | * PF in device_to_iommu() anyway. */ | |
59ce0515 JL |
345 | if (pdev->is_virtfn) |
346 | return NOTIFY_DONE; | |
e6a8c9b3 JR |
347 | if (action != BUS_NOTIFY_ADD_DEVICE && |
348 | action != BUS_NOTIFY_REMOVED_DEVICE) | |
59ce0515 JL |
349 | return NOTIFY_DONE; |
350 | ||
351 | info = dmar_alloc_pci_notify_info(pdev, action); | |
352 | if (!info) | |
353 | return NOTIFY_DONE; | |
354 | ||
355 | down_write(&dmar_global_lock); | |
356 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
357 | dmar_pci_bus_add_dev(info); | |
e6a8c9b3 | 358 | else if (action == BUS_NOTIFY_REMOVED_DEVICE) |
59ce0515 JL |
359 | dmar_pci_bus_del_dev(info); |
360 | up_write(&dmar_global_lock); | |
361 | ||
362 | dmar_free_pci_notify_info(info); | |
363 | ||
364 | return NOTIFY_OK; | |
365 | } | |
366 | ||
367 | static struct notifier_block dmar_pci_bus_nb = { | |
368 | .notifier_call = dmar_pci_bus_notifier, | |
369 | .priority = INT_MIN, | |
370 | }; | |
371 | ||
6b197249 JL |
372 | static struct dmar_drhd_unit * |
373 | dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd) | |
374 | { | |
375 | struct dmar_drhd_unit *dmaru; | |
376 | ||
377 | list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list) | |
378 | if (dmaru->segment == drhd->segment && | |
379 | dmaru->reg_base_addr == drhd->address) | |
380 | return dmaru; | |
381 | ||
382 | return NULL; | |
383 | } | |
384 | ||
10e5247f KA |
385 | /** |
386 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition | |
387 | * structure which uniquely represent one DMA remapping hardware unit | |
388 | * present in the platform | |
389 | */ | |
6b197249 | 390 | static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg) |
10e5247f KA |
391 | { |
392 | struct acpi_dmar_hardware_unit *drhd; | |
393 | struct dmar_drhd_unit *dmaru; | |
3f6db659 | 394 | int ret; |
10e5247f | 395 | |
e523b38e | 396 | drhd = (struct acpi_dmar_hardware_unit *)header; |
6b197249 JL |
397 | dmaru = dmar_find_dmaru(drhd); |
398 | if (dmaru) | |
399 | goto out; | |
400 | ||
401 | dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); | |
10e5247f KA |
402 | if (!dmaru) |
403 | return -ENOMEM; | |
404 | ||
6b197249 JL |
405 | /* |
406 | * If header is allocated from slab by ACPI _DSM method, we need to | |
407 | * copy the content because the memory buffer will be freed on return. | |
408 | */ | |
409 | dmaru->hdr = (void *)(dmaru + 1); | |
410 | memcpy(dmaru->hdr, header, header->length); | |
10e5247f | 411 | dmaru->reg_base_addr = drhd->address; |
276dbf99 | 412 | dmaru->segment = drhd->segment; |
10e5247f | 413 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ |
07cb52ff DW |
414 | dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), |
415 | ((void *)drhd) + drhd->header.length, | |
416 | &dmaru->devices_cnt); | |
417 | if (dmaru->devices_cnt && dmaru->devices == NULL) { | |
418 | kfree(dmaru); | |
419 | return -ENOMEM; | |
2e455289 | 420 | } |
10e5247f | 421 | |
1886e8a9 SS |
422 | ret = alloc_iommu(dmaru); |
423 | if (ret) { | |
07cb52ff DW |
424 | dmar_free_dev_scope(&dmaru->devices, |
425 | &dmaru->devices_cnt); | |
1886e8a9 SS |
426 | kfree(dmaru); |
427 | return ret; | |
428 | } | |
429 | dmar_register_drhd_unit(dmaru); | |
c2a0b538 | 430 | |
6b197249 | 431 | out: |
c2a0b538 JL |
432 | if (arg) |
433 | (*(int *)arg)++; | |
434 | ||
1886e8a9 SS |
435 | return 0; |
436 | } | |
437 | ||
a868e6b7 JL |
438 | static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) |
439 | { | |
440 | if (dmaru->devices && dmaru->devices_cnt) | |
441 | dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); | |
442 | if (dmaru->iommu) | |
443 | free_iommu(dmaru->iommu); | |
444 | kfree(dmaru); | |
445 | } | |
446 | ||
c2a0b538 JL |
447 | static int __init dmar_parse_one_andd(struct acpi_dmar_header *header, |
448 | void *arg) | |
e625b4a9 DW |
449 | { |
450 | struct acpi_dmar_andd *andd = (void *)header; | |
451 | ||
452 | /* Check for NUL termination within the designated length */ | |
83118b0d | 453 | if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { |
e625b4a9 DW |
454 | WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND, |
455 | "Your BIOS is broken; ANDD object name is not NUL-terminated\n" | |
456 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
457 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
458 | dmi_get_system_info(DMI_BIOS_VERSION), | |
459 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
460 | return -EINVAL; | |
461 | } | |
462 | pr_info("ANDD device: %x name: %s\n", andd->device_number, | |
83118b0d | 463 | andd->device_name); |
e625b4a9 DW |
464 | |
465 | return 0; | |
466 | } | |
467 | ||
aa697079 | 468 | #ifdef CONFIG_ACPI_NUMA |
6b197249 | 469 | static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) |
ee34b32d SS |
470 | { |
471 | struct acpi_dmar_rhsa *rhsa; | |
472 | struct dmar_drhd_unit *drhd; | |
473 | ||
474 | rhsa = (struct acpi_dmar_rhsa *)header; | |
aa697079 | 475 | for_each_drhd_unit(drhd) { |
ee34b32d SS |
476 | if (drhd->reg_base_addr == rhsa->base_address) { |
477 | int node = acpi_map_pxm_to_node(rhsa->proximity_domain); | |
478 | ||
479 | if (!node_online(node)) | |
480 | node = -1; | |
481 | drhd->iommu->node = node; | |
aa697079 DW |
482 | return 0; |
483 | } | |
ee34b32d | 484 | } |
fd0c8894 BH |
485 | WARN_TAINT( |
486 | 1, TAINT_FIRMWARE_WORKAROUND, | |
487 | "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" | |
488 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
489 | drhd->reg_base_addr, | |
490 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
491 | dmi_get_system_info(DMI_BIOS_VERSION), | |
492 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
ee34b32d | 493 | |
aa697079 | 494 | return 0; |
ee34b32d | 495 | } |
c2a0b538 JL |
496 | #else |
497 | #define dmar_parse_one_rhsa dmar_res_noop | |
aa697079 | 498 | #endif |
ee34b32d | 499 | |
3bd71e18 | 500 | static void |
10e5247f KA |
501 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) |
502 | { | |
503 | struct acpi_dmar_hardware_unit *drhd; | |
504 | struct acpi_dmar_reserved_memory *rmrr; | |
aa5d2b51 | 505 | struct acpi_dmar_atsr *atsr; |
17b60977 | 506 | struct acpi_dmar_rhsa *rhsa; |
10e5247f KA |
507 | |
508 | switch (header->type) { | |
509 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
aa5d2b51 YZ |
510 | drhd = container_of(header, struct acpi_dmar_hardware_unit, |
511 | header); | |
e9071b0b | 512 | pr_info("DRHD base: %#016Lx flags: %#x\n", |
aa5d2b51 | 513 | (unsigned long long)drhd->address, drhd->flags); |
10e5247f KA |
514 | break; |
515 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aa5d2b51 YZ |
516 | rmrr = container_of(header, struct acpi_dmar_reserved_memory, |
517 | header); | |
e9071b0b | 518 | pr_info("RMRR base: %#016Lx end: %#016Lx\n", |
5b6985ce FY |
519 | (unsigned long long)rmrr->base_address, |
520 | (unsigned long long)rmrr->end_address); | |
10e5247f | 521 | break; |
83118b0d | 522 | case ACPI_DMAR_TYPE_ROOT_ATS: |
aa5d2b51 | 523 | atsr = container_of(header, struct acpi_dmar_atsr, header); |
e9071b0b | 524 | pr_info("ATSR flags: %#x\n", atsr->flags); |
aa5d2b51 | 525 | break; |
83118b0d | 526 | case ACPI_DMAR_TYPE_HARDWARE_AFFINITY: |
17b60977 | 527 | rhsa = container_of(header, struct acpi_dmar_rhsa, header); |
e9071b0b | 528 | pr_info("RHSA base: %#016Lx proximity domain: %#x\n", |
17b60977 RD |
529 | (unsigned long long)rhsa->base_address, |
530 | rhsa->proximity_domain); | |
531 | break; | |
83118b0d | 532 | case ACPI_DMAR_TYPE_NAMESPACE: |
e625b4a9 DW |
533 | /* We don't print this here because we need to sanity-check |
534 | it first. So print it in dmar_parse_one_andd() instead. */ | |
535 | break; | |
10e5247f KA |
536 | } |
537 | } | |
538 | ||
f6dd5c31 YL |
539 | /** |
540 | * dmar_table_detect - checks to see if the platform supports DMAR devices | |
541 | */ | |
542 | static int __init dmar_table_detect(void) | |
543 | { | |
544 | acpi_status status = AE_OK; | |
545 | ||
546 | /* if we could find DMAR table, then there are DMAR devices */ | |
6b11d1d6 | 547 | status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); |
f6dd5c31 YL |
548 | |
549 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
e9071b0b | 550 | pr_warn("Unable to map DMAR\n"); |
f6dd5c31 YL |
551 | status = AE_NOT_FOUND; |
552 | } | |
553 | ||
8326c5d2 | 554 | return ACPI_SUCCESS(status) ? 0 : -ENOENT; |
f6dd5c31 | 555 | } |
aaa9d1dd | 556 | |
c2a0b538 JL |
557 | static int dmar_walk_remapping_entries(struct acpi_dmar_header *start, |
558 | size_t len, struct dmar_res_callback *cb) | |
559 | { | |
c2a0b538 JL |
560 | struct acpi_dmar_header *iter, *next; |
561 | struct acpi_dmar_header *end = ((void *)start) + len; | |
562 | ||
4a8ed2b8 | 563 | for (iter = start; iter < end; iter = next) { |
c2a0b538 JL |
564 | next = (void *)iter + iter->length; |
565 | if (iter->length == 0) { | |
566 | /* Avoid looping forever on bad ACPI tables */ | |
567 | pr_debug(FW_BUG "Invalid 0-length structure\n"); | |
568 | break; | |
569 | } else if (next > end) { | |
570 | /* Avoid passing table end */ | |
9f10e5bf | 571 | pr_warn(FW_BUG "Record passes table end\n"); |
4a8ed2b8 | 572 | return -EINVAL; |
c2a0b538 JL |
573 | } |
574 | ||
575 | if (cb->print_entry) | |
576 | dmar_table_print_dmar_entry(iter); | |
577 | ||
578 | if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { | |
579 | /* continue for forward compatibility */ | |
580 | pr_debug("Unknown DMAR structure type %d\n", | |
581 | iter->type); | |
582 | } else if (cb->cb[iter->type]) { | |
4a8ed2b8 AS |
583 | int ret; |
584 | ||
c2a0b538 | 585 | ret = cb->cb[iter->type](iter, cb->arg[iter->type]); |
4a8ed2b8 AS |
586 | if (ret) |
587 | return ret; | |
c2a0b538 JL |
588 | } else if (!cb->ignore_unhandled) { |
589 | pr_warn("No handler for DMAR structure type %d\n", | |
590 | iter->type); | |
4a8ed2b8 | 591 | return -EINVAL; |
c2a0b538 JL |
592 | } |
593 | } | |
594 | ||
4a8ed2b8 | 595 | return 0; |
c2a0b538 JL |
596 | } |
597 | ||
598 | static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar, | |
599 | struct dmar_res_callback *cb) | |
600 | { | |
601 | return dmar_walk_remapping_entries((void *)(dmar + 1), | |
602 | dmar->header.length - sizeof(*dmar), cb); | |
603 | } | |
604 | ||
10e5247f KA |
605 | /** |
606 | * parse_dmar_table - parses the DMA reporting table | |
607 | */ | |
608 | static int __init | |
609 | parse_dmar_table(void) | |
610 | { | |
611 | struct acpi_table_dmar *dmar; | |
7cef3347 | 612 | int drhd_count = 0; |
3f6db659 | 613 | int ret; |
c2a0b538 JL |
614 | struct dmar_res_callback cb = { |
615 | .print_entry = true, | |
616 | .ignore_unhandled = true, | |
617 | .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count, | |
618 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd, | |
619 | .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr, | |
620 | .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr, | |
621 | .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa, | |
622 | .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd, | |
623 | }; | |
10e5247f | 624 | |
f6dd5c31 YL |
625 | /* |
626 | * Do it again, earlier dmar_tbl mapping could be mapped with | |
627 | * fixed map. | |
628 | */ | |
629 | dmar_table_detect(); | |
630 | ||
a59b50e9 JC |
631 | /* |
632 | * ACPI tables may not be DMA protected by tboot, so use DMAR copy | |
633 | * SINIT saved in SinitMleData in TXT heap (which is DMA protected) | |
634 | */ | |
635 | dmar_tbl = tboot_get_dmar_table(dmar_tbl); | |
636 | ||
10e5247f KA |
637 | dmar = (struct acpi_table_dmar *)dmar_tbl; |
638 | if (!dmar) | |
639 | return -ENODEV; | |
640 | ||
5b6985ce | 641 | if (dmar->width < PAGE_SHIFT - 1) { |
e9071b0b | 642 | pr_warn("Invalid DMAR haw\n"); |
10e5247f KA |
643 | return -EINVAL; |
644 | } | |
645 | ||
e9071b0b | 646 | pr_info("Host address width %d\n", dmar->width + 1); |
c2a0b538 JL |
647 | ret = dmar_walk_dmar_table(dmar, &cb); |
648 | if (ret == 0 && drhd_count == 0) | |
7cef3347 | 649 | pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); |
c2a0b538 | 650 | |
10e5247f KA |
651 | return ret; |
652 | } | |
653 | ||
832bd858 DW |
654 | static int dmar_pci_device_match(struct dmar_dev_scope devices[], |
655 | int cnt, struct pci_dev *dev) | |
e61d98d8 SS |
656 | { |
657 | int index; | |
832bd858 | 658 | struct device *tmp; |
e61d98d8 SS |
659 | |
660 | while (dev) { | |
b683b230 | 661 | for_each_active_dev_scope(devices, cnt, index, tmp) |
832bd858 | 662 | if (dev_is_pci(tmp) && dev == to_pci_dev(tmp)) |
e61d98d8 SS |
663 | return 1; |
664 | ||
665 | /* Check our parent */ | |
666 | dev = dev->bus->self; | |
667 | } | |
668 | ||
669 | return 0; | |
670 | } | |
671 | ||
672 | struct dmar_drhd_unit * | |
673 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
674 | { | |
0e242612 | 675 | struct dmar_drhd_unit *dmaru; |
2e824f79 YZ |
676 | struct acpi_dmar_hardware_unit *drhd; |
677 | ||
dda56549 Y |
678 | dev = pci_physfn(dev); |
679 | ||
0e242612 | 680 | rcu_read_lock(); |
8b161f0e | 681 | for_each_drhd_unit(dmaru) { |
2e824f79 YZ |
682 | drhd = container_of(dmaru->hdr, |
683 | struct acpi_dmar_hardware_unit, | |
684 | header); | |
685 | ||
686 | if (dmaru->include_all && | |
687 | drhd->segment == pci_domain_nr(dev->bus)) | |
0e242612 | 688 | goto out; |
e61d98d8 | 689 | |
2e824f79 YZ |
690 | if (dmar_pci_device_match(dmaru->devices, |
691 | dmaru->devices_cnt, dev)) | |
0e242612 | 692 | goto out; |
e61d98d8 | 693 | } |
0e242612 JL |
694 | dmaru = NULL; |
695 | out: | |
696 | rcu_read_unlock(); | |
e61d98d8 | 697 | |
0e242612 | 698 | return dmaru; |
e61d98d8 SS |
699 | } |
700 | ||
ed40356b DW |
701 | static void __init dmar_acpi_insert_dev_scope(u8 device_number, |
702 | struct acpi_device *adev) | |
703 | { | |
704 | struct dmar_drhd_unit *dmaru; | |
705 | struct acpi_dmar_hardware_unit *drhd; | |
706 | struct acpi_dmar_device_scope *scope; | |
707 | struct device *tmp; | |
708 | int i; | |
709 | struct acpi_dmar_pci_path *path; | |
710 | ||
711 | for_each_drhd_unit(dmaru) { | |
712 | drhd = container_of(dmaru->hdr, | |
713 | struct acpi_dmar_hardware_unit, | |
714 | header); | |
715 | ||
716 | for (scope = (void *)(drhd + 1); | |
717 | (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; | |
718 | scope = ((void *)scope) + scope->length) { | |
83118b0d | 719 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) |
ed40356b DW |
720 | continue; |
721 | if (scope->enumeration_id != device_number) | |
722 | continue; | |
723 | ||
724 | path = (void *)(scope + 1); | |
725 | pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", | |
726 | dev_name(&adev->dev), dmaru->reg_base_addr, | |
727 | scope->bus, path->device, path->function); | |
728 | for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) | |
729 | if (tmp == NULL) { | |
730 | dmaru->devices[i].bus = scope->bus; | |
731 | dmaru->devices[i].devfn = PCI_DEVFN(path->device, | |
732 | path->function); | |
733 | rcu_assign_pointer(dmaru->devices[i].dev, | |
734 | get_device(&adev->dev)); | |
735 | return; | |
736 | } | |
737 | BUG_ON(i >= dmaru->devices_cnt); | |
738 | } | |
739 | } | |
740 | pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", | |
741 | device_number, dev_name(&adev->dev)); | |
742 | } | |
743 | ||
744 | static int __init dmar_acpi_dev_scope_init(void) | |
745 | { | |
11f1a776 JR |
746 | struct acpi_dmar_andd *andd; |
747 | ||
748 | if (dmar_tbl == NULL) | |
749 | return -ENODEV; | |
750 | ||
7713ec06 DW |
751 | for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar); |
752 | ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; | |
753 | andd = ((void *)andd) + andd->header.length) { | |
83118b0d | 754 | if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { |
ed40356b DW |
755 | acpi_handle h; |
756 | struct acpi_device *adev; | |
757 | ||
758 | if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT, | |
83118b0d | 759 | andd->device_name, |
ed40356b DW |
760 | &h))) { |
761 | pr_err("Failed to find handle for ACPI object %s\n", | |
83118b0d | 762 | andd->device_name); |
ed40356b DW |
763 | continue; |
764 | } | |
c0df975f | 765 | if (acpi_bus_get_device(h, &adev)) { |
ed40356b | 766 | pr_err("Failed to get device for ACPI object %s\n", |
83118b0d | 767 | andd->device_name); |
ed40356b DW |
768 | continue; |
769 | } | |
770 | dmar_acpi_insert_dev_scope(andd->device_number, adev); | |
771 | } | |
ed40356b DW |
772 | } |
773 | return 0; | |
774 | } | |
775 | ||
1886e8a9 SS |
776 | int __init dmar_dev_scope_init(void) |
777 | { | |
2e455289 JL |
778 | struct pci_dev *dev = NULL; |
779 | struct dmar_pci_notify_info *info; | |
1886e8a9 | 780 | |
2e455289 JL |
781 | if (dmar_dev_scope_status != 1) |
782 | return dmar_dev_scope_status; | |
c2c7286a | 783 | |
2e455289 JL |
784 | if (list_empty(&dmar_drhd_units)) { |
785 | dmar_dev_scope_status = -ENODEV; | |
786 | } else { | |
787 | dmar_dev_scope_status = 0; | |
788 | ||
63b42624 DW |
789 | dmar_acpi_dev_scope_init(); |
790 | ||
2e455289 JL |
791 | for_each_pci_dev(dev) { |
792 | if (dev->is_virtfn) | |
793 | continue; | |
794 | ||
795 | info = dmar_alloc_pci_notify_info(dev, | |
796 | BUS_NOTIFY_ADD_DEVICE); | |
797 | if (!info) { | |
798 | return dmar_dev_scope_status; | |
799 | } else { | |
800 | dmar_pci_bus_add_dev(info); | |
801 | dmar_free_pci_notify_info(info); | |
802 | } | |
803 | } | |
1886e8a9 SS |
804 | } |
805 | ||
2e455289 | 806 | return dmar_dev_scope_status; |
1886e8a9 SS |
807 | } |
808 | ||
ec154bf5 JR |
809 | void dmar_register_bus_notifier(void) |
810 | { | |
811 | bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
812 | } | |
813 | ||
10e5247f KA |
814 | |
815 | int __init dmar_table_init(void) | |
816 | { | |
1886e8a9 | 817 | static int dmar_table_initialized; |
093f87d2 FY |
818 | int ret; |
819 | ||
cc05301f JL |
820 | if (dmar_table_initialized == 0) { |
821 | ret = parse_dmar_table(); | |
822 | if (ret < 0) { | |
823 | if (ret != -ENODEV) | |
9f10e5bf | 824 | pr_info("Parse DMAR table failure.\n"); |
cc05301f JL |
825 | } else if (list_empty(&dmar_drhd_units)) { |
826 | pr_info("No DMAR devices found\n"); | |
827 | ret = -ENODEV; | |
828 | } | |
093f87d2 | 829 | |
cc05301f JL |
830 | if (ret < 0) |
831 | dmar_table_initialized = ret; | |
832 | else | |
833 | dmar_table_initialized = 1; | |
10e5247f | 834 | } |
093f87d2 | 835 | |
cc05301f | 836 | return dmar_table_initialized < 0 ? dmar_table_initialized : 0; |
10e5247f KA |
837 | } |
838 | ||
3a8663ee BH |
839 | static void warn_invalid_dmar(u64 addr, const char *message) |
840 | { | |
fd0c8894 BH |
841 | WARN_TAINT_ONCE( |
842 | 1, TAINT_FIRMWARE_WORKAROUND, | |
843 | "Your BIOS is broken; DMAR reported at address %llx%s!\n" | |
844 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
845 | addr, message, | |
846 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
847 | dmi_get_system_info(DMI_BIOS_VERSION), | |
848 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
3a8663ee | 849 | } |
6ecbf01c | 850 | |
c2a0b538 JL |
851 | static int __ref |
852 | dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) | |
86cf898e | 853 | { |
86cf898e | 854 | struct acpi_dmar_hardware_unit *drhd; |
c2a0b538 JL |
855 | void __iomem *addr; |
856 | u64 cap, ecap; | |
86cf898e | 857 | |
c2a0b538 JL |
858 | drhd = (void *)entry; |
859 | if (!drhd->address) { | |
860 | warn_invalid_dmar(0, ""); | |
861 | return -EINVAL; | |
862 | } | |
2c992208 | 863 | |
6b197249 JL |
864 | if (arg) |
865 | addr = ioremap(drhd->address, VTD_PAGE_SIZE); | |
866 | else | |
867 | addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); | |
c2a0b538 | 868 | if (!addr) { |
9f10e5bf | 869 | pr_warn("Can't validate DRHD address: %llx\n", drhd->address); |
c2a0b538 JL |
870 | return -EINVAL; |
871 | } | |
6b197249 | 872 | |
c2a0b538 JL |
873 | cap = dmar_readq(addr + DMAR_CAP_REG); |
874 | ecap = dmar_readq(addr + DMAR_ECAP_REG); | |
6b197249 JL |
875 | |
876 | if (arg) | |
877 | iounmap(addr); | |
878 | else | |
879 | early_iounmap(addr, VTD_PAGE_SIZE); | |
86cf898e | 880 | |
c2a0b538 JL |
881 | if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { |
882 | warn_invalid_dmar(drhd->address, " returns all ones"); | |
883 | return -EINVAL; | |
86cf898e | 884 | } |
2c992208 | 885 | |
2c992208 | 886 | return 0; |
86cf898e DW |
887 | } |
888 | ||
480125ba | 889 | int __init detect_intel_iommu(void) |
2ae21010 SS |
890 | { |
891 | int ret; | |
c2a0b538 JL |
892 | struct dmar_res_callback validate_drhd_cb = { |
893 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd, | |
894 | .ignore_unhandled = true, | |
895 | }; | |
2ae21010 | 896 | |
3a5670e8 | 897 | down_write(&dmar_global_lock); |
f6dd5c31 | 898 | ret = dmar_table_detect(); |
8326c5d2 AS |
899 | if (!ret) |
900 | ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl, | |
901 | &validate_drhd_cb); | |
902 | if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) { | |
c2a0b538 JL |
903 | iommu_detected = 1; |
904 | /* Make sure ACS will be enabled */ | |
905 | pci_request_acs(); | |
906 | } | |
f5d1b97b | 907 | |
9d5ce73a | 908 | #ifdef CONFIG_X86 |
8326c5d2 | 909 | if (!ret) |
c2a0b538 | 910 | x86_init.iommu.iommu_init = intel_iommu_init; |
2ae21010 | 911 | #endif |
c2a0b538 | 912 | |
696c7f8e RW |
913 | if (dmar_tbl) { |
914 | acpi_put_table(dmar_tbl); | |
915 | dmar_tbl = NULL; | |
916 | } | |
3a5670e8 | 917 | up_write(&dmar_global_lock); |
480125ba | 918 | |
8326c5d2 | 919 | return ret ? ret : 1; |
2ae21010 SS |
920 | } |
921 | ||
6f5cf521 DD |
922 | static void unmap_iommu(struct intel_iommu *iommu) |
923 | { | |
924 | iounmap(iommu->reg); | |
925 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
926 | } | |
927 | ||
928 | /** | |
929 | * map_iommu: map the iommu's registers | |
930 | * @iommu: the iommu to map | |
931 | * @phys_addr: the physical address of the base resgister | |
e9071b0b | 932 | * |
6f5cf521 | 933 | * Memory map the iommu's registers. Start w/ a single page, and |
e9071b0b | 934 | * possibly expand if that turns out to be insufficent. |
6f5cf521 DD |
935 | */ |
936 | static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) | |
937 | { | |
938 | int map_size, err=0; | |
939 | ||
940 | iommu->reg_phys = phys_addr; | |
941 | iommu->reg_size = VTD_PAGE_SIZE; | |
942 | ||
943 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { | |
9f10e5bf | 944 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
945 | err = -EBUSY; |
946 | goto out; | |
947 | } | |
948 | ||
949 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
950 | if (!iommu->reg) { | |
9f10e5bf | 951 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
952 | err = -ENOMEM; |
953 | goto release; | |
954 | } | |
955 | ||
956 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
957 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
958 | ||
959 | if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { | |
960 | err = -EINVAL; | |
961 | warn_invalid_dmar(phys_addr, " returns all ones"); | |
962 | goto unmap; | |
963 | } | |
964 | ||
965 | /* the registers might be more than one page */ | |
966 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
967 | cap_max_fault_reg_offset(iommu->cap)); | |
968 | map_size = VTD_PAGE_ALIGN(map_size); | |
969 | if (map_size > iommu->reg_size) { | |
970 | iounmap(iommu->reg); | |
971 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
972 | iommu->reg_size = map_size; | |
973 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, | |
974 | iommu->name)) { | |
9f10e5bf | 975 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
976 | err = -EBUSY; |
977 | goto out; | |
978 | } | |
979 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
980 | if (!iommu->reg) { | |
9f10e5bf | 981 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
982 | err = -ENOMEM; |
983 | goto release; | |
984 | } | |
985 | } | |
986 | err = 0; | |
987 | goto out; | |
988 | ||
989 | unmap: | |
990 | iounmap(iommu->reg); | |
991 | release: | |
992 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
993 | out: | |
994 | return err; | |
995 | } | |
996 | ||
78d8e704 JL |
997 | static int dmar_alloc_seq_id(struct intel_iommu *iommu) |
998 | { | |
999 | iommu->seq_id = find_first_zero_bit(dmar_seq_ids, | |
1000 | DMAR_UNITS_SUPPORTED); | |
1001 | if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) { | |
1002 | iommu->seq_id = -1; | |
1003 | } else { | |
1004 | set_bit(iommu->seq_id, dmar_seq_ids); | |
1005 | sprintf(iommu->name, "dmar%d", iommu->seq_id); | |
1006 | } | |
1007 | ||
1008 | return iommu->seq_id; | |
1009 | } | |
1010 | ||
1011 | static void dmar_free_seq_id(struct intel_iommu *iommu) | |
1012 | { | |
1013 | if (iommu->seq_id >= 0) { | |
1014 | clear_bit(iommu->seq_id, dmar_seq_ids); | |
1015 | iommu->seq_id = -1; | |
1016 | } | |
1017 | } | |
1018 | ||
694835dc | 1019 | static int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 1020 | { |
c42d9f32 | 1021 | struct intel_iommu *iommu; |
3a93c841 | 1022 | u32 ver, sts; |
43f7392b | 1023 | int agaw = 0; |
4ed0d3e6 | 1024 | int msagaw = 0; |
6f5cf521 | 1025 | int err; |
c42d9f32 | 1026 | |
6ecbf01c | 1027 | if (!drhd->reg_base_addr) { |
3a8663ee | 1028 | warn_invalid_dmar(0, ""); |
6ecbf01c DW |
1029 | return -EINVAL; |
1030 | } | |
1031 | ||
c42d9f32 SS |
1032 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
1033 | if (!iommu) | |
1886e8a9 | 1034 | return -ENOMEM; |
c42d9f32 | 1035 | |
78d8e704 | 1036 | if (dmar_alloc_seq_id(iommu) < 0) { |
9f10e5bf | 1037 | pr_err("Failed to allocate seq_id\n"); |
78d8e704 JL |
1038 | err = -ENOSPC; |
1039 | goto error; | |
1040 | } | |
e61d98d8 | 1041 | |
6f5cf521 DD |
1042 | err = map_iommu(iommu, drhd->reg_base_addr); |
1043 | if (err) { | |
9f10e5bf | 1044 | pr_err("Failed to map %s\n", iommu->name); |
78d8e704 | 1045 | goto error_free_seq_id; |
e61d98d8 | 1046 | } |
0815565a | 1047 | |
6f5cf521 | 1048 | err = -EINVAL; |
1b573683 WH |
1049 | agaw = iommu_calculate_agaw(iommu); |
1050 | if (agaw < 0) { | |
bf947fcb DD |
1051 | pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", |
1052 | iommu->seq_id); | |
0815565a | 1053 | goto err_unmap; |
4ed0d3e6 FY |
1054 | } |
1055 | msagaw = iommu_calculate_max_sagaw(iommu); | |
1056 | if (msagaw < 0) { | |
bf947fcb | 1057 | pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", |
1b573683 | 1058 | iommu->seq_id); |
0815565a | 1059 | goto err_unmap; |
1b573683 WH |
1060 | } |
1061 | iommu->agaw = agaw; | |
4ed0d3e6 | 1062 | iommu->msagaw = msagaw; |
67ccac41 | 1063 | iommu->segment = drhd->segment; |
1b573683 | 1064 | |
ee34b32d SS |
1065 | iommu->node = -1; |
1066 | ||
e61d98d8 | 1067 | ver = readl(iommu->reg + DMAR_VER_REG); |
9f10e5bf JR |
1068 | pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", |
1069 | iommu->name, | |
5b6985ce FY |
1070 | (unsigned long long)drhd->reg_base_addr, |
1071 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
1072 | (unsigned long long)iommu->cap, | |
1073 | (unsigned long long)iommu->ecap); | |
e61d98d8 | 1074 | |
3a93c841 TI |
1075 | /* Reflect status in gcmd */ |
1076 | sts = readl(iommu->reg + DMAR_GSTS_REG); | |
1077 | if (sts & DMA_GSTS_IRES) | |
1078 | iommu->gcmd |= DMA_GCMD_IRE; | |
1079 | if (sts & DMA_GSTS_TES) | |
1080 | iommu->gcmd |= DMA_GCMD_TE; | |
1081 | if (sts & DMA_GSTS_QIES) | |
1082 | iommu->gcmd |= DMA_GCMD_QIE; | |
1083 | ||
1f5b3c3f | 1084 | raw_spin_lock_init(&iommu->register_lock); |
e61d98d8 | 1085 | |
bc847454 | 1086 | if (intel_iommu_enabled) { |
39ab9555 JR |
1087 | err = iommu_device_sysfs_add(&iommu->iommu, NULL, |
1088 | intel_iommu_groups, | |
1089 | "%s", iommu->name); | |
1090 | if (err) | |
bc847454 | 1091 | goto err_unmap; |
a5459cfe | 1092 | |
b0119e87 JR |
1093 | iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); |
1094 | ||
1095 | err = iommu_device_register(&iommu->iommu); | |
1096 | if (err) | |
bc847454 | 1097 | goto err_unmap; |
59203379 NK |
1098 | } |
1099 | ||
bc847454 JR |
1100 | drhd->iommu = iommu; |
1101 | ||
1886e8a9 | 1102 | return 0; |
0815565a | 1103 | |
78d8e704 | 1104 | err_unmap: |
6f5cf521 | 1105 | unmap_iommu(iommu); |
78d8e704 JL |
1106 | error_free_seq_id: |
1107 | dmar_free_seq_id(iommu); | |
1108 | error: | |
e61d98d8 | 1109 | kfree(iommu); |
6f5cf521 | 1110 | return err; |
e61d98d8 SS |
1111 | } |
1112 | ||
a868e6b7 | 1113 | static void free_iommu(struct intel_iommu *iommu) |
e61d98d8 | 1114 | { |
c37a0177 AS |
1115 | if (intel_iommu_enabled) { |
1116 | iommu_device_unregister(&iommu->iommu); | |
1117 | iommu_device_sysfs_remove(&iommu->iommu); | |
1118 | } | |
a5459cfe | 1119 | |
a868e6b7 | 1120 | if (iommu->irq) { |
1208225c DW |
1121 | if (iommu->pr_irq) { |
1122 | free_irq(iommu->pr_irq, iommu); | |
1123 | dmar_free_hwirq(iommu->pr_irq); | |
1124 | iommu->pr_irq = 0; | |
1125 | } | |
a868e6b7 | 1126 | free_irq(iommu->irq, iommu); |
a553b142 | 1127 | dmar_free_hwirq(iommu->irq); |
34742db8 | 1128 | iommu->irq = 0; |
a868e6b7 | 1129 | } |
e61d98d8 | 1130 | |
a84da70b JL |
1131 | if (iommu->qi) { |
1132 | free_page((unsigned long)iommu->qi->desc); | |
1133 | kfree(iommu->qi->desc_status); | |
1134 | kfree(iommu->qi); | |
1135 | } | |
1136 | ||
e61d98d8 | 1137 | if (iommu->reg) |
6f5cf521 DD |
1138 | unmap_iommu(iommu); |
1139 | ||
78d8e704 | 1140 | dmar_free_seq_id(iommu); |
e61d98d8 SS |
1141 | kfree(iommu); |
1142 | } | |
fe962e90 SS |
1143 | |
1144 | /* | |
1145 | * Reclaim all the submitted descriptors which have completed its work. | |
1146 | */ | |
1147 | static inline void reclaim_free_desc(struct q_inval *qi) | |
1148 | { | |
6ba6c3a4 YZ |
1149 | while (qi->desc_status[qi->free_tail] == QI_DONE || |
1150 | qi->desc_status[qi->free_tail] == QI_ABORT) { | |
fe962e90 SS |
1151 | qi->desc_status[qi->free_tail] = QI_FREE; |
1152 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
1153 | qi->free_cnt++; | |
1154 | } | |
1155 | } | |
1156 | ||
704126ad YZ |
1157 | static int qi_check_fault(struct intel_iommu *iommu, int index) |
1158 | { | |
1159 | u32 fault; | |
6ba6c3a4 | 1160 | int head, tail; |
704126ad YZ |
1161 | struct q_inval *qi = iommu->qi; |
1162 | int wait_index = (index + 1) % QI_LENGTH; | |
1163 | ||
6ba6c3a4 YZ |
1164 | if (qi->desc_status[wait_index] == QI_ABORT) |
1165 | return -EAGAIN; | |
1166 | ||
704126ad YZ |
1167 | fault = readl(iommu->reg + DMAR_FSTS_REG); |
1168 | ||
1169 | /* | |
1170 | * If IQE happens, the head points to the descriptor associated | |
1171 | * with the error. No new descriptors are fetched until the IQE | |
1172 | * is cleared. | |
1173 | */ | |
1174 | if (fault & DMA_FSTS_IQE) { | |
1175 | head = readl(iommu->reg + DMAR_IQH_REG); | |
6ba6c3a4 | 1176 | if ((head >> DMAR_IQ_SHIFT) == index) { |
bf947fcb | 1177 | pr_err("VT-d detected invalid descriptor: " |
6ba6c3a4 YZ |
1178 | "low=%llx, high=%llx\n", |
1179 | (unsigned long long)qi->desc[index].low, | |
1180 | (unsigned long long)qi->desc[index].high); | |
704126ad YZ |
1181 | memcpy(&qi->desc[index], &qi->desc[wait_index], |
1182 | sizeof(struct qi_desc)); | |
704126ad YZ |
1183 | writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); |
1184 | return -EINVAL; | |
1185 | } | |
1186 | } | |
1187 | ||
6ba6c3a4 YZ |
1188 | /* |
1189 | * If ITE happens, all pending wait_desc commands are aborted. | |
1190 | * No new descriptors are fetched until the ITE is cleared. | |
1191 | */ | |
1192 | if (fault & DMA_FSTS_ITE) { | |
1193 | head = readl(iommu->reg + DMAR_IQH_REG); | |
1194 | head = ((head >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH; | |
1195 | head |= 1; | |
1196 | tail = readl(iommu->reg + DMAR_IQT_REG); | |
1197 | tail = ((tail >> DMAR_IQ_SHIFT) - 1 + QI_LENGTH) % QI_LENGTH; | |
1198 | ||
1199 | writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); | |
1200 | ||
1201 | do { | |
1202 | if (qi->desc_status[head] == QI_IN_USE) | |
1203 | qi->desc_status[head] = QI_ABORT; | |
1204 | head = (head - 2 + QI_LENGTH) % QI_LENGTH; | |
1205 | } while (head != tail); | |
1206 | ||
1207 | if (qi->desc_status[wait_index] == QI_ABORT) | |
1208 | return -EAGAIN; | |
1209 | } | |
1210 | ||
1211 | if (fault & DMA_FSTS_ICE) | |
1212 | writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); | |
1213 | ||
704126ad YZ |
1214 | return 0; |
1215 | } | |
1216 | ||
fe962e90 SS |
1217 | /* |
1218 | * Submit the queued invalidation descriptor to the remapping | |
1219 | * hardware unit and wait for its completion. | |
1220 | */ | |
704126ad | 1221 | int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) |
fe962e90 | 1222 | { |
6ba6c3a4 | 1223 | int rc; |
fe962e90 SS |
1224 | struct q_inval *qi = iommu->qi; |
1225 | struct qi_desc *hw, wait_desc; | |
1226 | int wait_index, index; | |
1227 | unsigned long flags; | |
1228 | ||
1229 | if (!qi) | |
704126ad | 1230 | return 0; |
fe962e90 SS |
1231 | |
1232 | hw = qi->desc; | |
1233 | ||
6ba6c3a4 YZ |
1234 | restart: |
1235 | rc = 0; | |
1236 | ||
3b8f4048 | 1237 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 | 1238 | while (qi->free_cnt < 3) { |
3b8f4048 | 1239 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
fe962e90 | 1240 | cpu_relax(); |
3b8f4048 | 1241 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 SS |
1242 | } |
1243 | ||
1244 | index = qi->free_head; | |
1245 | wait_index = (index + 1) % QI_LENGTH; | |
1246 | ||
1247 | qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE; | |
1248 | ||
1249 | hw[index] = *desc; | |
1250 | ||
704126ad YZ |
1251 | wait_desc.low = QI_IWD_STATUS_DATA(QI_DONE) | |
1252 | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; | |
fe962e90 SS |
1253 | wait_desc.high = virt_to_phys(&qi->desc_status[wait_index]); |
1254 | ||
1255 | hw[wait_index] = wait_desc; | |
1256 | ||
fe962e90 SS |
1257 | qi->free_head = (qi->free_head + 2) % QI_LENGTH; |
1258 | qi->free_cnt -= 2; | |
1259 | ||
fe962e90 SS |
1260 | /* |
1261 | * update the HW tail register indicating the presence of | |
1262 | * new descriptors. | |
1263 | */ | |
6ba6c3a4 | 1264 | writel(qi->free_head << DMAR_IQ_SHIFT, iommu->reg + DMAR_IQT_REG); |
fe962e90 SS |
1265 | |
1266 | while (qi->desc_status[wait_index] != QI_DONE) { | |
f05810c9 SS |
1267 | /* |
1268 | * We will leave the interrupts disabled, to prevent interrupt | |
1269 | * context to queue another cmd while a cmd is already submitted | |
1270 | * and waiting for completion on this cpu. This is to avoid | |
1271 | * a deadlock where the interrupt context can wait indefinitely | |
1272 | * for free slots in the queue. | |
1273 | */ | |
704126ad YZ |
1274 | rc = qi_check_fault(iommu, index); |
1275 | if (rc) | |
6ba6c3a4 | 1276 | break; |
704126ad | 1277 | |
3b8f4048 | 1278 | raw_spin_unlock(&qi->q_lock); |
fe962e90 | 1279 | cpu_relax(); |
3b8f4048 | 1280 | raw_spin_lock(&qi->q_lock); |
fe962e90 | 1281 | } |
6ba6c3a4 YZ |
1282 | |
1283 | qi->desc_status[index] = QI_DONE; | |
fe962e90 SS |
1284 | |
1285 | reclaim_free_desc(qi); | |
3b8f4048 | 1286 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
704126ad | 1287 | |
6ba6c3a4 YZ |
1288 | if (rc == -EAGAIN) |
1289 | goto restart; | |
1290 | ||
704126ad | 1291 | return rc; |
fe962e90 SS |
1292 | } |
1293 | ||
1294 | /* | |
1295 | * Flush the global interrupt entry cache. | |
1296 | */ | |
1297 | void qi_global_iec(struct intel_iommu *iommu) | |
1298 | { | |
1299 | struct qi_desc desc; | |
1300 | ||
1301 | desc.low = QI_IEC_TYPE; | |
1302 | desc.high = 0; | |
1303 | ||
704126ad | 1304 | /* should never fail */ |
fe962e90 SS |
1305 | qi_submit_sync(&desc, iommu); |
1306 | } | |
1307 | ||
4c25a2c1 DW |
1308 | void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, |
1309 | u64 type) | |
3481f210 | 1310 | { |
3481f210 YS |
1311 | struct qi_desc desc; |
1312 | ||
3481f210 YS |
1313 | desc.low = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) |
1314 | | QI_CC_GRAN(type) | QI_CC_TYPE; | |
1315 | desc.high = 0; | |
1316 | ||
4c25a2c1 | 1317 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1318 | } |
1319 | ||
1f0ef2aa DW |
1320 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
1321 | unsigned int size_order, u64 type) | |
3481f210 YS |
1322 | { |
1323 | u8 dw = 0, dr = 0; | |
1324 | ||
1325 | struct qi_desc desc; | |
1326 | int ih = 0; | |
1327 | ||
3481f210 YS |
1328 | if (cap_write_drain(iommu->cap)) |
1329 | dw = 1; | |
1330 | ||
1331 | if (cap_read_drain(iommu->cap)) | |
1332 | dr = 1; | |
1333 | ||
1334 | desc.low = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) | |
1335 | | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; | |
1336 | desc.high = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) | |
1337 | | QI_IOTLB_AM(size_order); | |
1338 | ||
1f0ef2aa | 1339 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1340 | } |
1341 | ||
6ba6c3a4 YZ |
1342 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep, |
1343 | u64 addr, unsigned mask) | |
1344 | { | |
1345 | struct qi_desc desc; | |
1346 | ||
1347 | if (mask) { | |
d18b02ea | 1348 | BUG_ON(addr & ((1ULL << (VTD_PAGE_SHIFT + mask)) - 1)); |
c8acb28b | 1349 | addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; |
6ba6c3a4 YZ |
1350 | desc.high = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; |
1351 | } else | |
1352 | desc.high = QI_DEV_IOTLB_ADDR(addr); | |
1353 | ||
1354 | if (qdep >= QI_DEV_IOTLB_MAX_INVS) | |
1355 | qdep = 0; | |
1356 | ||
1357 | desc.low = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | | |
1358 | QI_DIOTLB_TYPE; | |
1359 | ||
1360 | qi_submit_sync(&desc, iommu); | |
1361 | } | |
1362 | ||
eba67e5d SS |
1363 | /* |
1364 | * Disable Queued Invalidation interface. | |
1365 | */ | |
1366 | void dmar_disable_qi(struct intel_iommu *iommu) | |
1367 | { | |
1368 | unsigned long flags; | |
1369 | u32 sts; | |
1370 | cycles_t start_time = get_cycles(); | |
1371 | ||
1372 | if (!ecap_qis(iommu->ecap)) | |
1373 | return; | |
1374 | ||
1f5b3c3f | 1375 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 1376 | |
fda3bec1 | 1377 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
1378 | if (!(sts & DMA_GSTS_QIES)) |
1379 | goto end; | |
1380 | ||
1381 | /* | |
1382 | * Give a chance to HW to complete the pending invalidation requests. | |
1383 | */ | |
1384 | while ((readl(iommu->reg + DMAR_IQT_REG) != | |
1385 | readl(iommu->reg + DMAR_IQH_REG)) && | |
1386 | (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) | |
1387 | cpu_relax(); | |
1388 | ||
1389 | iommu->gcmd &= ~DMA_GCMD_QIE; | |
eba67e5d SS |
1390 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
1391 | ||
1392 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | |
1393 | !(sts & DMA_GSTS_QIES), sts); | |
1394 | end: | |
1f5b3c3f | 1395 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
1396 | } |
1397 | ||
eb4a52bc FY |
1398 | /* |
1399 | * Enable queued invalidation. | |
1400 | */ | |
1401 | static void __dmar_enable_qi(struct intel_iommu *iommu) | |
1402 | { | |
c416daa9 | 1403 | u32 sts; |
eb4a52bc FY |
1404 | unsigned long flags; |
1405 | struct q_inval *qi = iommu->qi; | |
1406 | ||
1407 | qi->free_head = qi->free_tail = 0; | |
1408 | qi->free_cnt = QI_LENGTH; | |
1409 | ||
1f5b3c3f | 1410 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eb4a52bc FY |
1411 | |
1412 | /* write zero to the tail reg */ | |
1413 | writel(0, iommu->reg + DMAR_IQT_REG); | |
1414 | ||
1415 | dmar_writeq(iommu->reg + DMAR_IQA_REG, virt_to_phys(qi->desc)); | |
1416 | ||
eb4a52bc | 1417 | iommu->gcmd |= DMA_GCMD_QIE; |
c416daa9 | 1418 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
eb4a52bc FY |
1419 | |
1420 | /* Make sure hardware complete it */ | |
1421 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
1422 | ||
1f5b3c3f | 1423 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eb4a52bc FY |
1424 | } |
1425 | ||
fe962e90 SS |
1426 | /* |
1427 | * Enable Queued Invalidation interface. This is a must to support | |
1428 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
1429 | * register based IOTLB invalidation. | |
1430 | */ | |
1431 | int dmar_enable_qi(struct intel_iommu *iommu) | |
1432 | { | |
fe962e90 | 1433 | struct q_inval *qi; |
751cafe3 | 1434 | struct page *desc_page; |
fe962e90 SS |
1435 | |
1436 | if (!ecap_qis(iommu->ecap)) | |
1437 | return -ENOENT; | |
1438 | ||
1439 | /* | |
1440 | * queued invalidation is already setup and enabled. | |
1441 | */ | |
1442 | if (iommu->qi) | |
1443 | return 0; | |
1444 | ||
fa4b57cc | 1445 | iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); |
fe962e90 SS |
1446 | if (!iommu->qi) |
1447 | return -ENOMEM; | |
1448 | ||
1449 | qi = iommu->qi; | |
1450 | ||
751cafe3 SS |
1451 | |
1452 | desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0); | |
1453 | if (!desc_page) { | |
fe962e90 | 1454 | kfree(qi); |
b707cb02 | 1455 | iommu->qi = NULL; |
fe962e90 SS |
1456 | return -ENOMEM; |
1457 | } | |
1458 | ||
751cafe3 SS |
1459 | qi->desc = page_address(desc_page); |
1460 | ||
37a40710 | 1461 | qi->desc_status = kzalloc(QI_LENGTH * sizeof(int), GFP_ATOMIC); |
fe962e90 SS |
1462 | if (!qi->desc_status) { |
1463 | free_page((unsigned long) qi->desc); | |
1464 | kfree(qi); | |
b707cb02 | 1465 | iommu->qi = NULL; |
fe962e90 SS |
1466 | return -ENOMEM; |
1467 | } | |
1468 | ||
3b8f4048 | 1469 | raw_spin_lock_init(&qi->q_lock); |
fe962e90 | 1470 | |
eb4a52bc | 1471 | __dmar_enable_qi(iommu); |
fe962e90 SS |
1472 | |
1473 | return 0; | |
1474 | } | |
0ac2491f SS |
1475 | |
1476 | /* iommu interrupt handling. Most stuff are MSI-like. */ | |
1477 | ||
9d783ba0 SS |
1478 | enum faulttype { |
1479 | DMA_REMAP, | |
1480 | INTR_REMAP, | |
1481 | UNKNOWN, | |
1482 | }; | |
1483 | ||
1484 | static const char *dma_remap_fault_reasons[] = | |
0ac2491f SS |
1485 | { |
1486 | "Software", | |
1487 | "Present bit in root entry is clear", | |
1488 | "Present bit in context entry is clear", | |
1489 | "Invalid context entry", | |
1490 | "Access beyond MGAW", | |
1491 | "PTE Write access is not set", | |
1492 | "PTE Read access is not set", | |
1493 | "Next page table ptr is invalid", | |
1494 | "Root table address invalid", | |
1495 | "Context table ptr is invalid", | |
1496 | "non-zero reserved fields in RTP", | |
1497 | "non-zero reserved fields in CTP", | |
1498 | "non-zero reserved fields in PTE", | |
4ecccd9e | 1499 | "PCE for translation request specifies blocking", |
0ac2491f | 1500 | }; |
9d783ba0 | 1501 | |
95a02e97 | 1502 | static const char *irq_remap_fault_reasons[] = |
9d783ba0 SS |
1503 | { |
1504 | "Detected reserved fields in the decoded interrupt-remapped request", | |
1505 | "Interrupt index exceeded the interrupt-remapping table size", | |
1506 | "Present field in the IRTE entry is clear", | |
1507 | "Error accessing interrupt-remapping table pointed by IRTA_REG", | |
1508 | "Detected reserved fields in the IRTE entry", | |
1509 | "Blocked a compatibility format interrupt request", | |
1510 | "Blocked an interrupt request due to source-id verification failure", | |
1511 | }; | |
1512 | ||
21004dcd | 1513 | static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) |
0ac2491f | 1514 | { |
fefe1ed1 DC |
1515 | if (fault_reason >= 0x20 && (fault_reason - 0x20 < |
1516 | ARRAY_SIZE(irq_remap_fault_reasons))) { | |
9d783ba0 | 1517 | *fault_type = INTR_REMAP; |
95a02e97 | 1518 | return irq_remap_fault_reasons[fault_reason - 0x20]; |
9d783ba0 SS |
1519 | } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { |
1520 | *fault_type = DMA_REMAP; | |
1521 | return dma_remap_fault_reasons[fault_reason]; | |
1522 | } else { | |
1523 | *fault_type = UNKNOWN; | |
0ac2491f | 1524 | return "Unknown"; |
9d783ba0 | 1525 | } |
0ac2491f SS |
1526 | } |
1527 | ||
1208225c DW |
1528 | |
1529 | static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) | |
1530 | { | |
1531 | if (iommu->irq == irq) | |
1532 | return DMAR_FECTL_REG; | |
1533 | else if (iommu->pr_irq == irq) | |
1534 | return DMAR_PECTL_REG; | |
1535 | else | |
1536 | BUG(); | |
1537 | } | |
1538 | ||
5c2837fb | 1539 | void dmar_msi_unmask(struct irq_data *data) |
0ac2491f | 1540 | { |
dced35ae | 1541 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c | 1542 | int reg = dmar_msi_reg(iommu, data->irq); |
0ac2491f SS |
1543 | unsigned long flag; |
1544 | ||
1545 | /* unmask it */ | |
1f5b3c3f | 1546 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1547 | writel(0, iommu->reg + reg); |
0ac2491f | 1548 | /* Read a reg to force flush the post write */ |
1208225c | 1549 | readl(iommu->reg + reg); |
1f5b3c3f | 1550 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1551 | } |
1552 | ||
5c2837fb | 1553 | void dmar_msi_mask(struct irq_data *data) |
0ac2491f | 1554 | { |
dced35ae | 1555 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c DW |
1556 | int reg = dmar_msi_reg(iommu, data->irq); |
1557 | unsigned long flag; | |
0ac2491f SS |
1558 | |
1559 | /* mask it */ | |
1f5b3c3f | 1560 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1561 | writel(DMA_FECTL_IM, iommu->reg + reg); |
0ac2491f | 1562 | /* Read a reg to force flush the post write */ |
1208225c | 1563 | readl(iommu->reg + reg); |
1f5b3c3f | 1564 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1565 | } |
1566 | ||
1567 | void dmar_msi_write(int irq, struct msi_msg *msg) | |
1568 | { | |
dced35ae | 1569 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1570 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1571 | unsigned long flag; |
1572 | ||
1f5b3c3f | 1573 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1574 | writel(msg->data, iommu->reg + reg + 4); |
1575 | writel(msg->address_lo, iommu->reg + reg + 8); | |
1576 | writel(msg->address_hi, iommu->reg + reg + 12); | |
1f5b3c3f | 1577 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1578 | } |
1579 | ||
1580 | void dmar_msi_read(int irq, struct msi_msg *msg) | |
1581 | { | |
dced35ae | 1582 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1583 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1584 | unsigned long flag; |
1585 | ||
1f5b3c3f | 1586 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1587 | msg->data = readl(iommu->reg + reg + 4); |
1588 | msg->address_lo = readl(iommu->reg + reg + 8); | |
1589 | msg->address_hi = readl(iommu->reg + reg + 12); | |
1f5b3c3f | 1590 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1591 | } |
1592 | ||
1593 | static int dmar_fault_do_one(struct intel_iommu *iommu, int type, | |
1594 | u8 fault_reason, u16 source_id, unsigned long long addr) | |
1595 | { | |
1596 | const char *reason; | |
9d783ba0 | 1597 | int fault_type; |
0ac2491f | 1598 | |
9d783ba0 | 1599 | reason = dmar_get_fault_reason(fault_reason, &fault_type); |
0ac2491f | 1600 | |
9d783ba0 | 1601 | if (fault_type == INTR_REMAP) |
a0fe14d7 AW |
1602 | pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n", |
1603 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
9d783ba0 SS |
1604 | PCI_FUNC(source_id & 0xFF), addr >> 48, |
1605 | fault_reason, reason); | |
1606 | else | |
a0fe14d7 AW |
1607 | pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n", |
1608 | type ? "DMA Read" : "DMA Write", | |
1609 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
9d783ba0 | 1610 | PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason); |
0ac2491f SS |
1611 | return 0; |
1612 | } | |
1613 | ||
1614 | #define PRIMARY_FAULT_REG_LEN (16) | |
1531a6a6 | 1615 | irqreturn_t dmar_fault(int irq, void *dev_id) |
0ac2491f SS |
1616 | { |
1617 | struct intel_iommu *iommu = dev_id; | |
1618 | int reg, fault_index; | |
1619 | u32 fault_status; | |
1620 | unsigned long flag; | |
c43fce4e AW |
1621 | bool ratelimited; |
1622 | static DEFINE_RATELIMIT_STATE(rs, | |
1623 | DEFAULT_RATELIMIT_INTERVAL, | |
1624 | DEFAULT_RATELIMIT_BURST); | |
1625 | ||
1626 | /* Disable printing, simply clear the fault when ratelimited */ | |
1627 | ratelimited = !__ratelimit(&rs); | |
0ac2491f | 1628 | |
1f5b3c3f | 1629 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1630 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
c43fce4e | 1631 | if (fault_status && !ratelimited) |
bf947fcb | 1632 | pr_err("DRHD: handling fault status reg %x\n", fault_status); |
0ac2491f SS |
1633 | |
1634 | /* TBD: ignore advanced fault log currently */ | |
1635 | if (!(fault_status & DMA_FSTS_PPF)) | |
bd5cdad0 | 1636 | goto unlock_exit; |
0ac2491f SS |
1637 | |
1638 | fault_index = dma_fsts_fault_record_index(fault_status); | |
1639 | reg = cap_fault_reg_offset(iommu->cap); | |
1640 | while (1) { | |
1641 | u8 fault_reason; | |
1642 | u16 source_id; | |
1643 | u64 guest_addr; | |
1644 | int type; | |
1645 | u32 data; | |
1646 | ||
1647 | /* highest 32 bits */ | |
1648 | data = readl(iommu->reg + reg + | |
1649 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1650 | if (!(data & DMA_FRCD_F)) | |
1651 | break; | |
1652 | ||
c43fce4e AW |
1653 | if (!ratelimited) { |
1654 | fault_reason = dma_frcd_fault_reason(data); | |
1655 | type = dma_frcd_type(data); | |
0ac2491f | 1656 | |
c43fce4e AW |
1657 | data = readl(iommu->reg + reg + |
1658 | fault_index * PRIMARY_FAULT_REG_LEN + 8); | |
1659 | source_id = dma_frcd_source_id(data); | |
1660 | ||
1661 | guest_addr = dmar_readq(iommu->reg + reg + | |
1662 | fault_index * PRIMARY_FAULT_REG_LEN); | |
1663 | guest_addr = dma_frcd_page_addr(guest_addr); | |
1664 | } | |
0ac2491f | 1665 | |
0ac2491f SS |
1666 | /* clear the fault */ |
1667 | writel(DMA_FRCD_F, iommu->reg + reg + | |
1668 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1669 | ||
1f5b3c3f | 1670 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f | 1671 | |
c43fce4e AW |
1672 | if (!ratelimited) |
1673 | dmar_fault_do_one(iommu, type, fault_reason, | |
1674 | source_id, guest_addr); | |
0ac2491f SS |
1675 | |
1676 | fault_index++; | |
8211a7b5 | 1677 | if (fault_index >= cap_num_fault_regs(iommu->cap)) |
0ac2491f | 1678 | fault_index = 0; |
1f5b3c3f | 1679 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1680 | } |
0ac2491f | 1681 | |
973b5464 LB |
1682 | writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO, |
1683 | iommu->reg + DMAR_FSTS_REG); | |
bd5cdad0 LZH |
1684 | |
1685 | unlock_exit: | |
1f5b3c3f | 1686 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1687 | return IRQ_HANDLED; |
1688 | } | |
1689 | ||
1690 | int dmar_set_interrupt(struct intel_iommu *iommu) | |
1691 | { | |
1692 | int irq, ret; | |
1693 | ||
9d783ba0 SS |
1694 | /* |
1695 | * Check if the fault interrupt is already initialized. | |
1696 | */ | |
1697 | if (iommu->irq) | |
1698 | return 0; | |
1699 | ||
34742db8 JL |
1700 | irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); |
1701 | if (irq > 0) { | |
1702 | iommu->irq = irq; | |
1703 | } else { | |
9f10e5bf | 1704 | pr_err("No free IRQ vectors\n"); |
0ac2491f SS |
1705 | return -EINVAL; |
1706 | } | |
1707 | ||
477694e7 | 1708 | ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); |
0ac2491f | 1709 | if (ret) |
9f10e5bf | 1710 | pr_err("Can't request irq\n"); |
0ac2491f SS |
1711 | return ret; |
1712 | } | |
9d783ba0 SS |
1713 | |
1714 | int __init enable_drhd_fault_handling(void) | |
1715 | { | |
1716 | struct dmar_drhd_unit *drhd; | |
7c919779 | 1717 | struct intel_iommu *iommu; |
9d783ba0 SS |
1718 | |
1719 | /* | |
1720 | * Enable fault control interrupt. | |
1721 | */ | |
7c919779 | 1722 | for_each_iommu(iommu, drhd) { |
bd5cdad0 | 1723 | u32 fault_status; |
7c919779 | 1724 | int ret = dmar_set_interrupt(iommu); |
9d783ba0 SS |
1725 | |
1726 | if (ret) { | |
e9071b0b | 1727 | pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", |
9d783ba0 SS |
1728 | (unsigned long long)drhd->reg_base_addr, ret); |
1729 | return -1; | |
1730 | } | |
7f99d946 SS |
1731 | |
1732 | /* | |
1733 | * Clear any previous faults. | |
1734 | */ | |
1735 | dmar_fault(iommu->irq, iommu); | |
bd5cdad0 LZH |
1736 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
1737 | writel(fault_status, iommu->reg + DMAR_FSTS_REG); | |
9d783ba0 SS |
1738 | } |
1739 | ||
1740 | return 0; | |
1741 | } | |
eb4a52bc FY |
1742 | |
1743 | /* | |
1744 | * Re-enable Queued Invalidation interface. | |
1745 | */ | |
1746 | int dmar_reenable_qi(struct intel_iommu *iommu) | |
1747 | { | |
1748 | if (!ecap_qis(iommu->ecap)) | |
1749 | return -ENOENT; | |
1750 | ||
1751 | if (!iommu->qi) | |
1752 | return -ENOENT; | |
1753 | ||
1754 | /* | |
1755 | * First disable queued invalidation. | |
1756 | */ | |
1757 | dmar_disable_qi(iommu); | |
1758 | /* | |
1759 | * Then enable queued invalidation again. Since there is no pending | |
1760 | * invalidation requests now, it's safe to re-enable queued | |
1761 | * invalidation. | |
1762 | */ | |
1763 | __dmar_enable_qi(iommu); | |
1764 | ||
1765 | return 0; | |
1766 | } | |
074835f0 YS |
1767 | |
1768 | /* | |
1769 | * Check interrupt remapping support in DMAR table description. | |
1770 | */ | |
0b8973a8 | 1771 | int __init dmar_ir_support(void) |
074835f0 YS |
1772 | { |
1773 | struct acpi_table_dmar *dmar; | |
1774 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
4f506e07 AP |
1775 | if (!dmar) |
1776 | return 0; | |
074835f0 YS |
1777 | return dmar->flags & 0x1; |
1778 | } | |
694835dc | 1779 | |
6b197249 JL |
1780 | /* Check whether DMAR units are in use */ |
1781 | static inline bool dmar_in_use(void) | |
1782 | { | |
1783 | return irq_remapping_enabled || intel_iommu_enabled; | |
1784 | } | |
1785 | ||
a868e6b7 JL |
1786 | static int __init dmar_free_unused_resources(void) |
1787 | { | |
1788 | struct dmar_drhd_unit *dmaru, *dmaru_n; | |
1789 | ||
6b197249 | 1790 | if (dmar_in_use()) |
a868e6b7 JL |
1791 | return 0; |
1792 | ||
2e455289 JL |
1793 | if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units)) |
1794 | bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
59ce0515 | 1795 | |
3a5670e8 | 1796 | down_write(&dmar_global_lock); |
a868e6b7 JL |
1797 | list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { |
1798 | list_del(&dmaru->list); | |
1799 | dmar_free_drhd(dmaru); | |
1800 | } | |
3a5670e8 | 1801 | up_write(&dmar_global_lock); |
a868e6b7 JL |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
1806 | late_initcall(dmar_free_unused_resources); | |
4db77ff3 | 1807 | IOMMU_INIT_POST(detect_intel_iommu); |
6b197249 JL |
1808 | |
1809 | /* | |
1810 | * DMAR Hotplug Support | |
1811 | * For more details, please refer to Intel(R) Virtualization Technology | |
1812 | * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8 | |
1813 | * "Remapping Hardware Unit Hot Plug". | |
1814 | */ | |
94116f81 AS |
1815 | static guid_t dmar_hp_guid = |
1816 | GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B, | |
1817 | 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF); | |
6b197249 JL |
1818 | |
1819 | /* | |
1820 | * Currently there's only one revision and BIOS will not check the revision id, | |
1821 | * so use 0 for safety. | |
1822 | */ | |
1823 | #define DMAR_DSM_REV_ID 0 | |
1824 | #define DMAR_DSM_FUNC_DRHD 1 | |
1825 | #define DMAR_DSM_FUNC_ATSR 2 | |
1826 | #define DMAR_DSM_FUNC_RHSA 3 | |
1827 | ||
1828 | static inline bool dmar_detect_dsm(acpi_handle handle, int func) | |
1829 | { | |
94116f81 | 1830 | return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func); |
6b197249 JL |
1831 | } |
1832 | ||
1833 | static int dmar_walk_dsm_resource(acpi_handle handle, int func, | |
1834 | dmar_res_handler_t handler, void *arg) | |
1835 | { | |
1836 | int ret = -ENODEV; | |
1837 | union acpi_object *obj; | |
1838 | struct acpi_dmar_header *start; | |
1839 | struct dmar_res_callback callback; | |
1840 | static int res_type[] = { | |
1841 | [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT, | |
1842 | [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS, | |
1843 | [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY, | |
1844 | }; | |
1845 | ||
1846 | if (!dmar_detect_dsm(handle, func)) | |
1847 | return 0; | |
1848 | ||
94116f81 | 1849 | obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, |
6b197249 JL |
1850 | func, NULL, ACPI_TYPE_BUFFER); |
1851 | if (!obj) | |
1852 | return -ENODEV; | |
1853 | ||
1854 | memset(&callback, 0, sizeof(callback)); | |
1855 | callback.cb[res_type[func]] = handler; | |
1856 | callback.arg[res_type[func]] = arg; | |
1857 | start = (struct acpi_dmar_header *)obj->buffer.pointer; | |
1858 | ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); | |
1859 | ||
1860 | ACPI_FREE(obj); | |
1861 | ||
1862 | return ret; | |
1863 | } | |
1864 | ||
1865 | static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg) | |
1866 | { | |
1867 | int ret; | |
1868 | struct dmar_drhd_unit *dmaru; | |
1869 | ||
1870 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1871 | if (!dmaru) | |
1872 | return -ENODEV; | |
1873 | ||
1874 | ret = dmar_ir_hotplug(dmaru, true); | |
1875 | if (ret == 0) | |
1876 | ret = dmar_iommu_hotplug(dmaru, true); | |
1877 | ||
1878 | return ret; | |
1879 | } | |
1880 | ||
1881 | static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg) | |
1882 | { | |
1883 | int i, ret; | |
1884 | struct device *dev; | |
1885 | struct dmar_drhd_unit *dmaru; | |
1886 | ||
1887 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1888 | if (!dmaru) | |
1889 | return 0; | |
1890 | ||
1891 | /* | |
1892 | * All PCI devices managed by this unit should have been destroyed. | |
1893 | */ | |
194dc870 | 1894 | if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { |
6b197249 JL |
1895 | for_each_active_dev_scope(dmaru->devices, |
1896 | dmaru->devices_cnt, i, dev) | |
1897 | return -EBUSY; | |
194dc870 | 1898 | } |
6b197249 JL |
1899 | |
1900 | ret = dmar_ir_hotplug(dmaru, false); | |
1901 | if (ret == 0) | |
1902 | ret = dmar_iommu_hotplug(dmaru, false); | |
1903 | ||
1904 | return ret; | |
1905 | } | |
1906 | ||
1907 | static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg) | |
1908 | { | |
1909 | struct dmar_drhd_unit *dmaru; | |
1910 | ||
1911 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1912 | if (dmaru) { | |
1913 | list_del_rcu(&dmaru->list); | |
1914 | synchronize_rcu(); | |
1915 | dmar_free_drhd(dmaru); | |
1916 | } | |
1917 | ||
1918 | return 0; | |
1919 | } | |
1920 | ||
1921 | static int dmar_hotplug_insert(acpi_handle handle) | |
1922 | { | |
1923 | int ret; | |
1924 | int drhd_count = 0; | |
1925 | ||
1926 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1927 | &dmar_validate_one_drhd, (void *)1); | |
1928 | if (ret) | |
1929 | goto out; | |
1930 | ||
1931 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1932 | &dmar_parse_one_drhd, (void *)&drhd_count); | |
1933 | if (ret == 0 && drhd_count == 0) { | |
1934 | pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); | |
1935 | goto out; | |
1936 | } else if (ret) { | |
1937 | goto release_drhd; | |
1938 | } | |
1939 | ||
1940 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA, | |
1941 | &dmar_parse_one_rhsa, NULL); | |
1942 | if (ret) | |
1943 | goto release_drhd; | |
1944 | ||
1945 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1946 | &dmar_parse_one_atsr, NULL); | |
1947 | if (ret) | |
1948 | goto release_atsr; | |
1949 | ||
1950 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1951 | &dmar_hp_add_drhd, NULL); | |
1952 | if (!ret) | |
1953 | return 0; | |
1954 | ||
1955 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1956 | &dmar_hp_remove_drhd, NULL); | |
1957 | release_atsr: | |
1958 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1959 | &dmar_release_one_atsr, NULL); | |
1960 | release_drhd: | |
1961 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1962 | &dmar_hp_release_drhd, NULL); | |
1963 | out: | |
1964 | return ret; | |
1965 | } | |
1966 | ||
1967 | static int dmar_hotplug_remove(acpi_handle handle) | |
1968 | { | |
1969 | int ret; | |
1970 | ||
1971 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1972 | &dmar_check_one_atsr, NULL); | |
1973 | if (ret) | |
1974 | return ret; | |
1975 | ||
1976 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1977 | &dmar_hp_remove_drhd, NULL); | |
1978 | if (ret == 0) { | |
1979 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1980 | &dmar_release_one_atsr, NULL)); | |
1981 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1982 | &dmar_hp_release_drhd, NULL)); | |
1983 | } else { | |
1984 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1985 | &dmar_hp_add_drhd, NULL); | |
1986 | } | |
1987 | ||
1988 | return ret; | |
1989 | } | |
1990 | ||
d35165a9 JL |
1991 | static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl, |
1992 | void *context, void **retval) | |
1993 | { | |
1994 | acpi_handle *phdl = retval; | |
1995 | ||
1996 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { | |
1997 | *phdl = handle; | |
1998 | return AE_CTRL_TERMINATE; | |
1999 | } | |
2000 | ||
2001 | return AE_OK; | |
2002 | } | |
2003 | ||
6b197249 JL |
2004 | static int dmar_device_hotplug(acpi_handle handle, bool insert) |
2005 | { | |
2006 | int ret; | |
d35165a9 JL |
2007 | acpi_handle tmp = NULL; |
2008 | acpi_status status; | |
6b197249 JL |
2009 | |
2010 | if (!dmar_in_use()) | |
2011 | return 0; | |
2012 | ||
d35165a9 JL |
2013 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { |
2014 | tmp = handle; | |
2015 | } else { | |
2016 | status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, | |
2017 | ACPI_UINT32_MAX, | |
2018 | dmar_get_dsm_handle, | |
2019 | NULL, NULL, &tmp); | |
2020 | if (ACPI_FAILURE(status)) { | |
2021 | pr_warn("Failed to locate _DSM method.\n"); | |
2022 | return -ENXIO; | |
2023 | } | |
2024 | } | |
2025 | if (tmp == NULL) | |
6b197249 JL |
2026 | return 0; |
2027 | ||
2028 | down_write(&dmar_global_lock); | |
2029 | if (insert) | |
d35165a9 | 2030 | ret = dmar_hotplug_insert(tmp); |
6b197249 | 2031 | else |
d35165a9 | 2032 | ret = dmar_hotplug_remove(tmp); |
6b197249 JL |
2033 | up_write(&dmar_global_lock); |
2034 | ||
2035 | return ret; | |
2036 | } | |
2037 | ||
2038 | int dmar_device_add(acpi_handle handle) | |
2039 | { | |
2040 | return dmar_device_hotplug(handle, true); | |
2041 | } | |
2042 | ||
2043 | int dmar_device_remove(acpi_handle handle) | |
2044 | { | |
2045 | return dmar_device_hotplug(handle, false); | |
2046 | } |