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3b20eb23 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
10e5247f KA |
2 | /* |
3 | * Copyright (c) 2006, Intel Corporation. | |
4 | * | |
98bcef56 | 5 | * Copyright (C) 2006-2008 Intel Corporation |
6 | * Author: Ashok Raj <ashok.raj@intel.com> | |
7 | * Author: Shaohua Li <shaohua.li@intel.com> | |
8 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 9 | * |
e61d98d8 | 10 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
11 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
12 | * tables. | |
e61d98d8 SS |
13 | * |
14 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
15 | */ |
16 | ||
9f10e5bf | 17 | #define pr_fmt(fmt) "DMAR: " fmt |
e9071b0b | 18 | |
10e5247f KA |
19 | #include <linux/pci.h> |
20 | #include <linux/dmar.h> | |
38717946 KA |
21 | #include <linux/iova.h> |
22 | #include <linux/intel-iommu.h> | |
fe962e90 | 23 | #include <linux/timer.h> |
0ac2491f SS |
24 | #include <linux/irq.h> |
25 | #include <linux/interrupt.h> | |
69575d38 | 26 | #include <linux/tboot.h> |
eb27cae8 | 27 | #include <linux/dmi.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
a5459cfe | 29 | #include <linux/iommu.h> |
98fa15f3 | 30 | #include <linux/numa.h> |
8a8f422d | 31 | #include <asm/irq_remapping.h> |
4db77ff3 | 32 | #include <asm/iommu_table.h> |
10e5247f | 33 | |
078e1ee2 JR |
34 | #include "irq_remapping.h" |
35 | ||
c2a0b538 JL |
36 | typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *); |
37 | struct dmar_res_callback { | |
38 | dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED]; | |
39 | void *arg[ACPI_DMAR_TYPE_RESERVED]; | |
40 | bool ignore_unhandled; | |
41 | bool print_entry; | |
42 | }; | |
43 | ||
3a5670e8 JL |
44 | /* |
45 | * Assumptions: | |
46 | * 1) The hotplug framework guarentees that DMAR unit will be hot-added | |
47 | * before IO devices managed by that unit. | |
48 | * 2) The hotplug framework guarantees that DMAR unit will be hot-removed | |
49 | * after IO devices managed by that unit. | |
50 | * 3) Hotplug events are rare. | |
51 | * | |
52 | * Locking rules for DMA and interrupt remapping related global data structures: | |
53 | * 1) Use dmar_global_lock in process context | |
54 | * 2) Use RCU in interrupt context | |
10e5247f | 55 | */ |
3a5670e8 | 56 | DECLARE_RWSEM(dmar_global_lock); |
10e5247f | 57 | LIST_HEAD(dmar_drhd_units); |
10e5247f | 58 | |
41750d31 | 59 | struct acpi_table_header * __initdata dmar_tbl; |
2e455289 | 60 | static int dmar_dev_scope_status = 1; |
78d8e704 | 61 | static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)]; |
10e5247f | 62 | |
694835dc | 63 | static int alloc_iommu(struct dmar_drhd_unit *drhd); |
a868e6b7 | 64 | static void free_iommu(struct intel_iommu *iommu); |
694835dc | 65 | |
b0119e87 JR |
66 | extern const struct iommu_ops intel_iommu_ops; |
67 | ||
6b197249 | 68 | static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) |
10e5247f KA |
69 | { |
70 | /* | |
71 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
72 | * the very end. | |
73 | */ | |
74 | if (drhd->include_all) | |
0e242612 | 75 | list_add_tail_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f | 76 | else |
0e242612 | 77 | list_add_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f KA |
78 | } |
79 | ||
bb3a6b78 | 80 | void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) |
10e5247f KA |
81 | { |
82 | struct acpi_dmar_device_scope *scope; | |
10e5247f KA |
83 | |
84 | *cnt = 0; | |
85 | while (start < end) { | |
86 | scope = start; | |
83118b0d | 87 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || |
07cb52ff | 88 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || |
10e5247f KA |
89 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) |
90 | (*cnt)++; | |
ae3e7f3a LC |
91 | else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && |
92 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { | |
e9071b0b | 93 | pr_warn("Unsupported device scope\n"); |
5715f0f9 | 94 | } |
10e5247f KA |
95 | start += scope->length; |
96 | } | |
97 | if (*cnt == 0) | |
bb3a6b78 JL |
98 | return NULL; |
99 | ||
832bd858 | 100 | return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL); |
bb3a6b78 JL |
101 | } |
102 | ||
832bd858 | 103 | void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt) |
ada4d4b2 | 104 | { |
b683b230 | 105 | int i; |
832bd858 | 106 | struct device *tmp_dev; |
b683b230 | 107 | |
ada4d4b2 | 108 | if (*devices && *cnt) { |
b683b230 | 109 | for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) |
832bd858 | 110 | put_device(tmp_dev); |
ada4d4b2 | 111 | kfree(*devices); |
ada4d4b2 | 112 | } |
0e242612 JL |
113 | |
114 | *devices = NULL; | |
115 | *cnt = 0; | |
ada4d4b2 JL |
116 | } |
117 | ||
59ce0515 JL |
118 | /* Optimize out kzalloc()/kfree() for normal cases */ |
119 | static char dmar_pci_notify_info_buf[64]; | |
120 | ||
121 | static struct dmar_pci_notify_info * | |
122 | dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) | |
123 | { | |
124 | int level = 0; | |
125 | size_t size; | |
126 | struct pci_dev *tmp; | |
127 | struct dmar_pci_notify_info *info; | |
128 | ||
129 | BUG_ON(dev->is_virtfn); | |
130 | ||
131 | /* Only generate path[] for device addition event */ | |
132 | if (event == BUS_NOTIFY_ADD_DEVICE) | |
133 | for (tmp = dev; tmp; tmp = tmp->bus->self) | |
134 | level++; | |
135 | ||
553d66cb | 136 | size = struct_size(info, path, level); |
59ce0515 JL |
137 | if (size <= sizeof(dmar_pci_notify_info_buf)) { |
138 | info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; | |
139 | } else { | |
140 | info = kzalloc(size, GFP_KERNEL); | |
141 | if (!info) { | |
142 | pr_warn("Out of memory when allocating notify_info " | |
143 | "for %s.\n", pci_name(dev)); | |
2e455289 JL |
144 | if (dmar_dev_scope_status == 0) |
145 | dmar_dev_scope_status = -ENOMEM; | |
59ce0515 JL |
146 | return NULL; |
147 | } | |
148 | } | |
149 | ||
150 | info->event = event; | |
151 | info->dev = dev; | |
152 | info->seg = pci_domain_nr(dev->bus); | |
153 | info->level = level; | |
154 | if (event == BUS_NOTIFY_ADD_DEVICE) { | |
5ae0566a JL |
155 | for (tmp = dev; tmp; tmp = tmp->bus->self) { |
156 | level--; | |
57384592 | 157 | info->path[level].bus = tmp->bus->number; |
59ce0515 JL |
158 | info->path[level].device = PCI_SLOT(tmp->devfn); |
159 | info->path[level].function = PCI_FUNC(tmp->devfn); | |
160 | if (pci_is_root_bus(tmp->bus)) | |
161 | info->bus = tmp->bus->number; | |
162 | } | |
163 | } | |
164 | ||
165 | return info; | |
166 | } | |
167 | ||
168 | static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) | |
169 | { | |
170 | if ((void *)info != dmar_pci_notify_info_buf) | |
171 | kfree(info); | |
172 | } | |
173 | ||
174 | static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, | |
175 | struct acpi_dmar_pci_path *path, int count) | |
176 | { | |
177 | int i; | |
178 | ||
179 | if (info->bus != bus) | |
80f7b3d1 | 180 | goto fallback; |
59ce0515 | 181 | if (info->level != count) |
80f7b3d1 | 182 | goto fallback; |
59ce0515 JL |
183 | |
184 | for (i = 0; i < count; i++) { | |
185 | if (path[i].device != info->path[i].device || | |
186 | path[i].function != info->path[i].function) | |
80f7b3d1 | 187 | goto fallback; |
59ce0515 JL |
188 | } |
189 | ||
190 | return true; | |
80f7b3d1 JR |
191 | |
192 | fallback: | |
193 | ||
194 | if (count != 1) | |
195 | return false; | |
196 | ||
197 | i = info->level - 1; | |
198 | if (bus == info->path[i].bus && | |
199 | path[0].device == info->path[i].device && | |
200 | path[0].function == info->path[i].function) { | |
201 | pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", | |
202 | bus, path[0].device, path[0].function); | |
203 | return true; | |
204 | } | |
205 | ||
206 | return false; | |
59ce0515 JL |
207 | } |
208 | ||
209 | /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ | |
210 | int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, | |
211 | void *start, void*end, u16 segment, | |
832bd858 DW |
212 | struct dmar_dev_scope *devices, |
213 | int devices_cnt) | |
59ce0515 JL |
214 | { |
215 | int i, level; | |
832bd858 | 216 | struct device *tmp, *dev = &info->dev->dev; |
59ce0515 JL |
217 | struct acpi_dmar_device_scope *scope; |
218 | struct acpi_dmar_pci_path *path; | |
219 | ||
220 | if (segment != info->seg) | |
221 | return 0; | |
222 | ||
223 | for (; start < end; start += scope->length) { | |
224 | scope = start; | |
225 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
226 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
227 | continue; | |
228 | ||
229 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
230 | level = (scope->length - sizeof(*scope)) / sizeof(*path); | |
231 | if (!dmar_match_pci_path(info, scope->bus, path, level)) | |
232 | continue; | |
233 | ||
ffb2d1eb RD |
234 | /* |
235 | * We expect devices with endpoint scope to have normal PCI | |
236 | * headers, and devices with bridge scope to have bridge PCI | |
237 | * headers. However PCI NTB devices may be listed in the | |
238 | * DMAR table with bridge scope, even though they have a | |
239 | * normal PCI header. NTB devices are identified by class | |
240 | * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch | |
241 | * for this special case. | |
242 | */ | |
243 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
244 | info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || | |
245 | (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && | |
246 | (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
247 | info->dev->class >> 8 != PCI_CLASS_BRIDGE_OTHER))) { | |
59ce0515 | 248 | pr_warn("Device scope type does not match for %s\n", |
832bd858 | 249 | pci_name(info->dev)); |
59ce0515 JL |
250 | return -EINVAL; |
251 | } | |
252 | ||
253 | for_each_dev_scope(devices, devices_cnt, i, tmp) | |
254 | if (tmp == NULL) { | |
832bd858 DW |
255 | devices[i].bus = info->dev->bus->number; |
256 | devices[i].devfn = info->dev->devfn; | |
257 | rcu_assign_pointer(devices[i].dev, | |
258 | get_device(dev)); | |
59ce0515 JL |
259 | return 1; |
260 | } | |
261 | BUG_ON(i >= devices_cnt); | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, | |
832bd858 | 268 | struct dmar_dev_scope *devices, int count) |
59ce0515 JL |
269 | { |
270 | int index; | |
832bd858 | 271 | struct device *tmp; |
59ce0515 JL |
272 | |
273 | if (info->seg != segment) | |
274 | return 0; | |
275 | ||
276 | for_each_active_dev_scope(devices, count, index, tmp) | |
832bd858 | 277 | if (tmp == &info->dev->dev) { |
eecbad7d | 278 | RCU_INIT_POINTER(devices[index].dev, NULL); |
59ce0515 | 279 | synchronize_rcu(); |
832bd858 | 280 | put_device(tmp); |
59ce0515 JL |
281 | return 1; |
282 | } | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
287 | static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) | |
288 | { | |
289 | int ret = 0; | |
290 | struct dmar_drhd_unit *dmaru; | |
291 | struct acpi_dmar_hardware_unit *drhd; | |
292 | ||
293 | for_each_drhd_unit(dmaru) { | |
294 | if (dmaru->include_all) | |
295 | continue; | |
296 | ||
297 | drhd = container_of(dmaru->hdr, | |
298 | struct acpi_dmar_hardware_unit, header); | |
299 | ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), | |
300 | ((void *)drhd) + drhd->header.length, | |
301 | dmaru->segment, | |
302 | dmaru->devices, dmaru->devices_cnt); | |
f9808079 | 303 | if (ret) |
59ce0515 JL |
304 | break; |
305 | } | |
306 | if (ret >= 0) | |
307 | ret = dmar_iommu_notify_scope_dev(info); | |
2e455289 JL |
308 | if (ret < 0 && dmar_dev_scope_status == 0) |
309 | dmar_dev_scope_status = ret; | |
59ce0515 JL |
310 | |
311 | return ret; | |
312 | } | |
313 | ||
314 | static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) | |
315 | { | |
316 | struct dmar_drhd_unit *dmaru; | |
317 | ||
318 | for_each_drhd_unit(dmaru) | |
319 | if (dmar_remove_dev_scope(info, dmaru->segment, | |
320 | dmaru->devices, dmaru->devices_cnt)) | |
321 | break; | |
322 | dmar_iommu_notify_scope_dev(info); | |
323 | } | |
324 | ||
325 | static int dmar_pci_bus_notifier(struct notifier_block *nb, | |
326 | unsigned long action, void *data) | |
327 | { | |
328 | struct pci_dev *pdev = to_pci_dev(data); | |
329 | struct dmar_pci_notify_info *info; | |
330 | ||
1c387188 AR |
331 | /* Only care about add/remove events for physical functions. |
332 | * For VFs we actually do the lookup based on the corresponding | |
333 | * PF in device_to_iommu() anyway. */ | |
59ce0515 JL |
334 | if (pdev->is_virtfn) |
335 | return NOTIFY_DONE; | |
e6a8c9b3 JR |
336 | if (action != BUS_NOTIFY_ADD_DEVICE && |
337 | action != BUS_NOTIFY_REMOVED_DEVICE) | |
59ce0515 JL |
338 | return NOTIFY_DONE; |
339 | ||
340 | info = dmar_alloc_pci_notify_info(pdev, action); | |
341 | if (!info) | |
342 | return NOTIFY_DONE; | |
343 | ||
344 | down_write(&dmar_global_lock); | |
345 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
346 | dmar_pci_bus_add_dev(info); | |
e6a8c9b3 | 347 | else if (action == BUS_NOTIFY_REMOVED_DEVICE) |
59ce0515 JL |
348 | dmar_pci_bus_del_dev(info); |
349 | up_write(&dmar_global_lock); | |
350 | ||
351 | dmar_free_pci_notify_info(info); | |
352 | ||
353 | return NOTIFY_OK; | |
354 | } | |
355 | ||
356 | static struct notifier_block dmar_pci_bus_nb = { | |
357 | .notifier_call = dmar_pci_bus_notifier, | |
358 | .priority = INT_MIN, | |
359 | }; | |
360 | ||
6b197249 JL |
361 | static struct dmar_drhd_unit * |
362 | dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd) | |
363 | { | |
364 | struct dmar_drhd_unit *dmaru; | |
365 | ||
366 | list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list) | |
367 | if (dmaru->segment == drhd->segment && | |
368 | dmaru->reg_base_addr == drhd->address) | |
369 | return dmaru; | |
370 | ||
371 | return NULL; | |
372 | } | |
373 | ||
10e5247f KA |
374 | /** |
375 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition | |
376 | * structure which uniquely represent one DMA remapping hardware unit | |
377 | * present in the platform | |
378 | */ | |
6b197249 | 379 | static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg) |
10e5247f KA |
380 | { |
381 | struct acpi_dmar_hardware_unit *drhd; | |
382 | struct dmar_drhd_unit *dmaru; | |
3f6db659 | 383 | int ret; |
10e5247f | 384 | |
e523b38e | 385 | drhd = (struct acpi_dmar_hardware_unit *)header; |
6b197249 JL |
386 | dmaru = dmar_find_dmaru(drhd); |
387 | if (dmaru) | |
388 | goto out; | |
389 | ||
390 | dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); | |
10e5247f KA |
391 | if (!dmaru) |
392 | return -ENOMEM; | |
393 | ||
6b197249 JL |
394 | /* |
395 | * If header is allocated from slab by ACPI _DSM method, we need to | |
396 | * copy the content because the memory buffer will be freed on return. | |
397 | */ | |
398 | dmaru->hdr = (void *)(dmaru + 1); | |
399 | memcpy(dmaru->hdr, header, header->length); | |
10e5247f | 400 | dmaru->reg_base_addr = drhd->address; |
276dbf99 | 401 | dmaru->segment = drhd->segment; |
10e5247f | 402 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ |
07cb52ff DW |
403 | dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), |
404 | ((void *)drhd) + drhd->header.length, | |
405 | &dmaru->devices_cnt); | |
406 | if (dmaru->devices_cnt && dmaru->devices == NULL) { | |
407 | kfree(dmaru); | |
408 | return -ENOMEM; | |
2e455289 | 409 | } |
10e5247f | 410 | |
1886e8a9 SS |
411 | ret = alloc_iommu(dmaru); |
412 | if (ret) { | |
07cb52ff DW |
413 | dmar_free_dev_scope(&dmaru->devices, |
414 | &dmaru->devices_cnt); | |
1886e8a9 SS |
415 | kfree(dmaru); |
416 | return ret; | |
417 | } | |
418 | dmar_register_drhd_unit(dmaru); | |
c2a0b538 | 419 | |
6b197249 | 420 | out: |
c2a0b538 JL |
421 | if (arg) |
422 | (*(int *)arg)++; | |
423 | ||
1886e8a9 SS |
424 | return 0; |
425 | } | |
426 | ||
a868e6b7 JL |
427 | static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) |
428 | { | |
429 | if (dmaru->devices && dmaru->devices_cnt) | |
430 | dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); | |
431 | if (dmaru->iommu) | |
432 | free_iommu(dmaru->iommu); | |
433 | kfree(dmaru); | |
434 | } | |
435 | ||
c2a0b538 JL |
436 | static int __init dmar_parse_one_andd(struct acpi_dmar_header *header, |
437 | void *arg) | |
e625b4a9 DW |
438 | { |
439 | struct acpi_dmar_andd *andd = (void *)header; | |
440 | ||
441 | /* Check for NUL termination within the designated length */ | |
83118b0d | 442 | if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { |
e625b4a9 DW |
443 | WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND, |
444 | "Your BIOS is broken; ANDD object name is not NUL-terminated\n" | |
445 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
446 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
447 | dmi_get_system_info(DMI_BIOS_VERSION), | |
448 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
449 | return -EINVAL; | |
450 | } | |
451 | pr_info("ANDD device: %x name: %s\n", andd->device_number, | |
83118b0d | 452 | andd->device_name); |
e625b4a9 DW |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
aa697079 | 457 | #ifdef CONFIG_ACPI_NUMA |
6b197249 | 458 | static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) |
ee34b32d SS |
459 | { |
460 | struct acpi_dmar_rhsa *rhsa; | |
461 | struct dmar_drhd_unit *drhd; | |
462 | ||
463 | rhsa = (struct acpi_dmar_rhsa *)header; | |
aa697079 | 464 | for_each_drhd_unit(drhd) { |
ee34b32d SS |
465 | if (drhd->reg_base_addr == rhsa->base_address) { |
466 | int node = acpi_map_pxm_to_node(rhsa->proximity_domain); | |
467 | ||
468 | if (!node_online(node)) | |
98fa15f3 | 469 | node = NUMA_NO_NODE; |
ee34b32d | 470 | drhd->iommu->node = node; |
aa697079 DW |
471 | return 0; |
472 | } | |
ee34b32d | 473 | } |
fd0c8894 BH |
474 | WARN_TAINT( |
475 | 1, TAINT_FIRMWARE_WORKAROUND, | |
476 | "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" | |
477 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
478 | drhd->reg_base_addr, | |
479 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
480 | dmi_get_system_info(DMI_BIOS_VERSION), | |
481 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
ee34b32d | 482 | |
aa697079 | 483 | return 0; |
ee34b32d | 484 | } |
c2a0b538 JL |
485 | #else |
486 | #define dmar_parse_one_rhsa dmar_res_noop | |
aa697079 | 487 | #endif |
ee34b32d | 488 | |
3bd71e18 | 489 | static void |
10e5247f KA |
490 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) |
491 | { | |
492 | struct acpi_dmar_hardware_unit *drhd; | |
493 | struct acpi_dmar_reserved_memory *rmrr; | |
aa5d2b51 | 494 | struct acpi_dmar_atsr *atsr; |
17b60977 | 495 | struct acpi_dmar_rhsa *rhsa; |
10e5247f KA |
496 | |
497 | switch (header->type) { | |
498 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
aa5d2b51 YZ |
499 | drhd = container_of(header, struct acpi_dmar_hardware_unit, |
500 | header); | |
e9071b0b | 501 | pr_info("DRHD base: %#016Lx flags: %#x\n", |
aa5d2b51 | 502 | (unsigned long long)drhd->address, drhd->flags); |
10e5247f KA |
503 | break; |
504 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aa5d2b51 YZ |
505 | rmrr = container_of(header, struct acpi_dmar_reserved_memory, |
506 | header); | |
e9071b0b | 507 | pr_info("RMRR base: %#016Lx end: %#016Lx\n", |
5b6985ce FY |
508 | (unsigned long long)rmrr->base_address, |
509 | (unsigned long long)rmrr->end_address); | |
10e5247f | 510 | break; |
83118b0d | 511 | case ACPI_DMAR_TYPE_ROOT_ATS: |
aa5d2b51 | 512 | atsr = container_of(header, struct acpi_dmar_atsr, header); |
e9071b0b | 513 | pr_info("ATSR flags: %#x\n", atsr->flags); |
aa5d2b51 | 514 | break; |
83118b0d | 515 | case ACPI_DMAR_TYPE_HARDWARE_AFFINITY: |
17b60977 | 516 | rhsa = container_of(header, struct acpi_dmar_rhsa, header); |
e9071b0b | 517 | pr_info("RHSA base: %#016Lx proximity domain: %#x\n", |
17b60977 RD |
518 | (unsigned long long)rhsa->base_address, |
519 | rhsa->proximity_domain); | |
520 | break; | |
83118b0d | 521 | case ACPI_DMAR_TYPE_NAMESPACE: |
e625b4a9 DW |
522 | /* We don't print this here because we need to sanity-check |
523 | it first. So print it in dmar_parse_one_andd() instead. */ | |
524 | break; | |
10e5247f KA |
525 | } |
526 | } | |
527 | ||
f6dd5c31 YL |
528 | /** |
529 | * dmar_table_detect - checks to see if the platform supports DMAR devices | |
530 | */ | |
531 | static int __init dmar_table_detect(void) | |
532 | { | |
533 | acpi_status status = AE_OK; | |
534 | ||
535 | /* if we could find DMAR table, then there are DMAR devices */ | |
6b11d1d6 | 536 | status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); |
f6dd5c31 YL |
537 | |
538 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
e9071b0b | 539 | pr_warn("Unable to map DMAR\n"); |
f6dd5c31 YL |
540 | status = AE_NOT_FOUND; |
541 | } | |
542 | ||
8326c5d2 | 543 | return ACPI_SUCCESS(status) ? 0 : -ENOENT; |
f6dd5c31 | 544 | } |
aaa9d1dd | 545 | |
c2a0b538 JL |
546 | static int dmar_walk_remapping_entries(struct acpi_dmar_header *start, |
547 | size_t len, struct dmar_res_callback *cb) | |
548 | { | |
c2a0b538 JL |
549 | struct acpi_dmar_header *iter, *next; |
550 | struct acpi_dmar_header *end = ((void *)start) + len; | |
551 | ||
4a8ed2b8 | 552 | for (iter = start; iter < end; iter = next) { |
c2a0b538 JL |
553 | next = (void *)iter + iter->length; |
554 | if (iter->length == 0) { | |
555 | /* Avoid looping forever on bad ACPI tables */ | |
556 | pr_debug(FW_BUG "Invalid 0-length structure\n"); | |
557 | break; | |
558 | } else if (next > end) { | |
559 | /* Avoid passing table end */ | |
9f10e5bf | 560 | pr_warn(FW_BUG "Record passes table end\n"); |
4a8ed2b8 | 561 | return -EINVAL; |
c2a0b538 JL |
562 | } |
563 | ||
564 | if (cb->print_entry) | |
565 | dmar_table_print_dmar_entry(iter); | |
566 | ||
567 | if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { | |
568 | /* continue for forward compatibility */ | |
569 | pr_debug("Unknown DMAR structure type %d\n", | |
570 | iter->type); | |
571 | } else if (cb->cb[iter->type]) { | |
4a8ed2b8 AS |
572 | int ret; |
573 | ||
c2a0b538 | 574 | ret = cb->cb[iter->type](iter, cb->arg[iter->type]); |
4a8ed2b8 AS |
575 | if (ret) |
576 | return ret; | |
c2a0b538 JL |
577 | } else if (!cb->ignore_unhandled) { |
578 | pr_warn("No handler for DMAR structure type %d\n", | |
579 | iter->type); | |
4a8ed2b8 | 580 | return -EINVAL; |
c2a0b538 JL |
581 | } |
582 | } | |
583 | ||
4a8ed2b8 | 584 | return 0; |
c2a0b538 JL |
585 | } |
586 | ||
587 | static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar, | |
588 | struct dmar_res_callback *cb) | |
589 | { | |
590 | return dmar_walk_remapping_entries((void *)(dmar + 1), | |
591 | dmar->header.length - sizeof(*dmar), cb); | |
592 | } | |
593 | ||
10e5247f KA |
594 | /** |
595 | * parse_dmar_table - parses the DMA reporting table | |
596 | */ | |
597 | static int __init | |
598 | parse_dmar_table(void) | |
599 | { | |
600 | struct acpi_table_dmar *dmar; | |
7cef3347 | 601 | int drhd_count = 0; |
3f6db659 | 602 | int ret; |
c2a0b538 JL |
603 | struct dmar_res_callback cb = { |
604 | .print_entry = true, | |
605 | .ignore_unhandled = true, | |
606 | .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count, | |
607 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd, | |
608 | .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr, | |
609 | .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr, | |
610 | .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa, | |
611 | .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd, | |
612 | }; | |
10e5247f | 613 | |
f6dd5c31 YL |
614 | /* |
615 | * Do it again, earlier dmar_tbl mapping could be mapped with | |
616 | * fixed map. | |
617 | */ | |
618 | dmar_table_detect(); | |
619 | ||
a59b50e9 JC |
620 | /* |
621 | * ACPI tables may not be DMA protected by tboot, so use DMAR copy | |
622 | * SINIT saved in SinitMleData in TXT heap (which is DMA protected) | |
623 | */ | |
624 | dmar_tbl = tboot_get_dmar_table(dmar_tbl); | |
625 | ||
10e5247f KA |
626 | dmar = (struct acpi_table_dmar *)dmar_tbl; |
627 | if (!dmar) | |
628 | return -ENODEV; | |
629 | ||
5b6985ce | 630 | if (dmar->width < PAGE_SHIFT - 1) { |
e9071b0b | 631 | pr_warn("Invalid DMAR haw\n"); |
10e5247f KA |
632 | return -EINVAL; |
633 | } | |
634 | ||
e9071b0b | 635 | pr_info("Host address width %d\n", dmar->width + 1); |
c2a0b538 JL |
636 | ret = dmar_walk_dmar_table(dmar, &cb); |
637 | if (ret == 0 && drhd_count == 0) | |
7cef3347 | 638 | pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); |
c2a0b538 | 639 | |
10e5247f KA |
640 | return ret; |
641 | } | |
642 | ||
832bd858 DW |
643 | static int dmar_pci_device_match(struct dmar_dev_scope devices[], |
644 | int cnt, struct pci_dev *dev) | |
e61d98d8 SS |
645 | { |
646 | int index; | |
832bd858 | 647 | struct device *tmp; |
e61d98d8 SS |
648 | |
649 | while (dev) { | |
b683b230 | 650 | for_each_active_dev_scope(devices, cnt, index, tmp) |
832bd858 | 651 | if (dev_is_pci(tmp) && dev == to_pci_dev(tmp)) |
e61d98d8 SS |
652 | return 1; |
653 | ||
654 | /* Check our parent */ | |
655 | dev = dev->bus->self; | |
656 | } | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | struct dmar_drhd_unit * | |
662 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
663 | { | |
0e242612 | 664 | struct dmar_drhd_unit *dmaru; |
2e824f79 YZ |
665 | struct acpi_dmar_hardware_unit *drhd; |
666 | ||
dda56549 Y |
667 | dev = pci_physfn(dev); |
668 | ||
0e242612 | 669 | rcu_read_lock(); |
8b161f0e | 670 | for_each_drhd_unit(dmaru) { |
2e824f79 YZ |
671 | drhd = container_of(dmaru->hdr, |
672 | struct acpi_dmar_hardware_unit, | |
673 | header); | |
674 | ||
675 | if (dmaru->include_all && | |
676 | drhd->segment == pci_domain_nr(dev->bus)) | |
0e242612 | 677 | goto out; |
e61d98d8 | 678 | |
2e824f79 YZ |
679 | if (dmar_pci_device_match(dmaru->devices, |
680 | dmaru->devices_cnt, dev)) | |
0e242612 | 681 | goto out; |
e61d98d8 | 682 | } |
0e242612 JL |
683 | dmaru = NULL; |
684 | out: | |
685 | rcu_read_unlock(); | |
e61d98d8 | 686 | |
0e242612 | 687 | return dmaru; |
e61d98d8 SS |
688 | } |
689 | ||
ed40356b DW |
690 | static void __init dmar_acpi_insert_dev_scope(u8 device_number, |
691 | struct acpi_device *adev) | |
692 | { | |
693 | struct dmar_drhd_unit *dmaru; | |
694 | struct acpi_dmar_hardware_unit *drhd; | |
695 | struct acpi_dmar_device_scope *scope; | |
696 | struct device *tmp; | |
697 | int i; | |
698 | struct acpi_dmar_pci_path *path; | |
699 | ||
700 | for_each_drhd_unit(dmaru) { | |
701 | drhd = container_of(dmaru->hdr, | |
702 | struct acpi_dmar_hardware_unit, | |
703 | header); | |
704 | ||
705 | for (scope = (void *)(drhd + 1); | |
706 | (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; | |
707 | scope = ((void *)scope) + scope->length) { | |
83118b0d | 708 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) |
ed40356b DW |
709 | continue; |
710 | if (scope->enumeration_id != device_number) | |
711 | continue; | |
712 | ||
713 | path = (void *)(scope + 1); | |
714 | pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", | |
715 | dev_name(&adev->dev), dmaru->reg_base_addr, | |
716 | scope->bus, path->device, path->function); | |
717 | for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) | |
718 | if (tmp == NULL) { | |
719 | dmaru->devices[i].bus = scope->bus; | |
720 | dmaru->devices[i].devfn = PCI_DEVFN(path->device, | |
721 | path->function); | |
722 | rcu_assign_pointer(dmaru->devices[i].dev, | |
723 | get_device(&adev->dev)); | |
724 | return; | |
725 | } | |
726 | BUG_ON(i >= dmaru->devices_cnt); | |
727 | } | |
728 | } | |
729 | pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", | |
730 | device_number, dev_name(&adev->dev)); | |
731 | } | |
732 | ||
733 | static int __init dmar_acpi_dev_scope_init(void) | |
734 | { | |
11f1a776 JR |
735 | struct acpi_dmar_andd *andd; |
736 | ||
737 | if (dmar_tbl == NULL) | |
738 | return -ENODEV; | |
739 | ||
7713ec06 DW |
740 | for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar); |
741 | ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; | |
742 | andd = ((void *)andd) + andd->header.length) { | |
83118b0d | 743 | if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { |
ed40356b DW |
744 | acpi_handle h; |
745 | struct acpi_device *adev; | |
746 | ||
747 | if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT, | |
83118b0d | 748 | andd->device_name, |
ed40356b DW |
749 | &h))) { |
750 | pr_err("Failed to find handle for ACPI object %s\n", | |
83118b0d | 751 | andd->device_name); |
ed40356b DW |
752 | continue; |
753 | } | |
c0df975f | 754 | if (acpi_bus_get_device(h, &adev)) { |
ed40356b | 755 | pr_err("Failed to get device for ACPI object %s\n", |
83118b0d | 756 | andd->device_name); |
ed40356b DW |
757 | continue; |
758 | } | |
759 | dmar_acpi_insert_dev_scope(andd->device_number, adev); | |
760 | } | |
ed40356b DW |
761 | } |
762 | return 0; | |
763 | } | |
764 | ||
1886e8a9 SS |
765 | int __init dmar_dev_scope_init(void) |
766 | { | |
2e455289 JL |
767 | struct pci_dev *dev = NULL; |
768 | struct dmar_pci_notify_info *info; | |
1886e8a9 | 769 | |
2e455289 JL |
770 | if (dmar_dev_scope_status != 1) |
771 | return dmar_dev_scope_status; | |
c2c7286a | 772 | |
2e455289 JL |
773 | if (list_empty(&dmar_drhd_units)) { |
774 | dmar_dev_scope_status = -ENODEV; | |
775 | } else { | |
776 | dmar_dev_scope_status = 0; | |
777 | ||
63b42624 DW |
778 | dmar_acpi_dev_scope_init(); |
779 | ||
2e455289 JL |
780 | for_each_pci_dev(dev) { |
781 | if (dev->is_virtfn) | |
782 | continue; | |
783 | ||
784 | info = dmar_alloc_pci_notify_info(dev, | |
785 | BUS_NOTIFY_ADD_DEVICE); | |
786 | if (!info) { | |
787 | return dmar_dev_scope_status; | |
788 | } else { | |
789 | dmar_pci_bus_add_dev(info); | |
790 | dmar_free_pci_notify_info(info); | |
791 | } | |
792 | } | |
1886e8a9 SS |
793 | } |
794 | ||
2e455289 | 795 | return dmar_dev_scope_status; |
1886e8a9 SS |
796 | } |
797 | ||
d15a339e | 798 | void __init dmar_register_bus_notifier(void) |
ec154bf5 JR |
799 | { |
800 | bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
801 | } | |
802 | ||
10e5247f KA |
803 | |
804 | int __init dmar_table_init(void) | |
805 | { | |
1886e8a9 | 806 | static int dmar_table_initialized; |
093f87d2 FY |
807 | int ret; |
808 | ||
cc05301f JL |
809 | if (dmar_table_initialized == 0) { |
810 | ret = parse_dmar_table(); | |
811 | if (ret < 0) { | |
812 | if (ret != -ENODEV) | |
9f10e5bf | 813 | pr_info("Parse DMAR table failure.\n"); |
cc05301f JL |
814 | } else if (list_empty(&dmar_drhd_units)) { |
815 | pr_info("No DMAR devices found\n"); | |
816 | ret = -ENODEV; | |
817 | } | |
093f87d2 | 818 | |
cc05301f JL |
819 | if (ret < 0) |
820 | dmar_table_initialized = ret; | |
821 | else | |
822 | dmar_table_initialized = 1; | |
10e5247f | 823 | } |
093f87d2 | 824 | |
cc05301f | 825 | return dmar_table_initialized < 0 ? dmar_table_initialized : 0; |
10e5247f KA |
826 | } |
827 | ||
3a8663ee BH |
828 | static void warn_invalid_dmar(u64 addr, const char *message) |
829 | { | |
fd0c8894 BH |
830 | WARN_TAINT_ONCE( |
831 | 1, TAINT_FIRMWARE_WORKAROUND, | |
832 | "Your BIOS is broken; DMAR reported at address %llx%s!\n" | |
833 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
834 | addr, message, | |
835 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
836 | dmi_get_system_info(DMI_BIOS_VERSION), | |
837 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
3a8663ee | 838 | } |
6ecbf01c | 839 | |
c2a0b538 JL |
840 | static int __ref |
841 | dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) | |
86cf898e | 842 | { |
86cf898e | 843 | struct acpi_dmar_hardware_unit *drhd; |
c2a0b538 JL |
844 | void __iomem *addr; |
845 | u64 cap, ecap; | |
86cf898e | 846 | |
c2a0b538 JL |
847 | drhd = (void *)entry; |
848 | if (!drhd->address) { | |
849 | warn_invalid_dmar(0, ""); | |
850 | return -EINVAL; | |
851 | } | |
2c992208 | 852 | |
6b197249 JL |
853 | if (arg) |
854 | addr = ioremap(drhd->address, VTD_PAGE_SIZE); | |
855 | else | |
856 | addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); | |
c2a0b538 | 857 | if (!addr) { |
9f10e5bf | 858 | pr_warn("Can't validate DRHD address: %llx\n", drhd->address); |
c2a0b538 JL |
859 | return -EINVAL; |
860 | } | |
6b197249 | 861 | |
c2a0b538 JL |
862 | cap = dmar_readq(addr + DMAR_CAP_REG); |
863 | ecap = dmar_readq(addr + DMAR_ECAP_REG); | |
6b197249 JL |
864 | |
865 | if (arg) | |
866 | iounmap(addr); | |
867 | else | |
868 | early_iounmap(addr, VTD_PAGE_SIZE); | |
86cf898e | 869 | |
c2a0b538 JL |
870 | if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { |
871 | warn_invalid_dmar(drhd->address, " returns all ones"); | |
872 | return -EINVAL; | |
86cf898e | 873 | } |
2c992208 | 874 | |
2c992208 | 875 | return 0; |
86cf898e DW |
876 | } |
877 | ||
480125ba | 878 | int __init detect_intel_iommu(void) |
2ae21010 SS |
879 | { |
880 | int ret; | |
c2a0b538 JL |
881 | struct dmar_res_callback validate_drhd_cb = { |
882 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd, | |
883 | .ignore_unhandled = true, | |
884 | }; | |
2ae21010 | 885 | |
3a5670e8 | 886 | down_write(&dmar_global_lock); |
f6dd5c31 | 887 | ret = dmar_table_detect(); |
8326c5d2 AS |
888 | if (!ret) |
889 | ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl, | |
890 | &validate_drhd_cb); | |
891 | if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) { | |
c2a0b538 JL |
892 | iommu_detected = 1; |
893 | /* Make sure ACS will be enabled */ | |
894 | pci_request_acs(); | |
895 | } | |
f5d1b97b | 896 | |
9d5ce73a | 897 | #ifdef CONFIG_X86 |
8326c5d2 | 898 | if (!ret) |
c2a0b538 | 899 | x86_init.iommu.iommu_init = intel_iommu_init; |
2ae21010 | 900 | #endif |
c2a0b538 | 901 | |
696c7f8e RW |
902 | if (dmar_tbl) { |
903 | acpi_put_table(dmar_tbl); | |
904 | dmar_tbl = NULL; | |
905 | } | |
3a5670e8 | 906 | up_write(&dmar_global_lock); |
480125ba | 907 | |
8326c5d2 | 908 | return ret ? ret : 1; |
2ae21010 SS |
909 | } |
910 | ||
6f5cf521 DD |
911 | static void unmap_iommu(struct intel_iommu *iommu) |
912 | { | |
913 | iounmap(iommu->reg); | |
914 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
915 | } | |
916 | ||
917 | /** | |
918 | * map_iommu: map the iommu's registers | |
919 | * @iommu: the iommu to map | |
920 | * @phys_addr: the physical address of the base resgister | |
e9071b0b | 921 | * |
6f5cf521 | 922 | * Memory map the iommu's registers. Start w/ a single page, and |
e9071b0b | 923 | * possibly expand if that turns out to be insufficent. |
6f5cf521 DD |
924 | */ |
925 | static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) | |
926 | { | |
927 | int map_size, err=0; | |
928 | ||
929 | iommu->reg_phys = phys_addr; | |
930 | iommu->reg_size = VTD_PAGE_SIZE; | |
931 | ||
932 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { | |
9f10e5bf | 933 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
934 | err = -EBUSY; |
935 | goto out; | |
936 | } | |
937 | ||
938 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
939 | if (!iommu->reg) { | |
9f10e5bf | 940 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
941 | err = -ENOMEM; |
942 | goto release; | |
943 | } | |
944 | ||
945 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
946 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
947 | ||
948 | if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { | |
949 | err = -EINVAL; | |
950 | warn_invalid_dmar(phys_addr, " returns all ones"); | |
951 | goto unmap; | |
952 | } | |
953 | ||
954 | /* the registers might be more than one page */ | |
955 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
956 | cap_max_fault_reg_offset(iommu->cap)); | |
957 | map_size = VTD_PAGE_ALIGN(map_size); | |
958 | if (map_size > iommu->reg_size) { | |
959 | iounmap(iommu->reg); | |
960 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
961 | iommu->reg_size = map_size; | |
962 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, | |
963 | iommu->name)) { | |
9f10e5bf | 964 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
965 | err = -EBUSY; |
966 | goto out; | |
967 | } | |
968 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
969 | if (!iommu->reg) { | |
9f10e5bf | 970 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
971 | err = -ENOMEM; |
972 | goto release; | |
973 | } | |
974 | } | |
975 | err = 0; | |
976 | goto out; | |
977 | ||
978 | unmap: | |
979 | iounmap(iommu->reg); | |
980 | release: | |
981 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
982 | out: | |
983 | return err; | |
984 | } | |
985 | ||
78d8e704 JL |
986 | static int dmar_alloc_seq_id(struct intel_iommu *iommu) |
987 | { | |
988 | iommu->seq_id = find_first_zero_bit(dmar_seq_ids, | |
989 | DMAR_UNITS_SUPPORTED); | |
990 | if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) { | |
991 | iommu->seq_id = -1; | |
992 | } else { | |
993 | set_bit(iommu->seq_id, dmar_seq_ids); | |
994 | sprintf(iommu->name, "dmar%d", iommu->seq_id); | |
995 | } | |
996 | ||
997 | return iommu->seq_id; | |
998 | } | |
999 | ||
1000 | static void dmar_free_seq_id(struct intel_iommu *iommu) | |
1001 | { | |
1002 | if (iommu->seq_id >= 0) { | |
1003 | clear_bit(iommu->seq_id, dmar_seq_ids); | |
1004 | iommu->seq_id = -1; | |
1005 | } | |
1006 | } | |
1007 | ||
694835dc | 1008 | static int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 1009 | { |
c42d9f32 | 1010 | struct intel_iommu *iommu; |
3a93c841 | 1011 | u32 ver, sts; |
43f7392b | 1012 | int agaw = 0; |
4ed0d3e6 | 1013 | int msagaw = 0; |
6f5cf521 | 1014 | int err; |
c42d9f32 | 1015 | |
6ecbf01c | 1016 | if (!drhd->reg_base_addr) { |
3a8663ee | 1017 | warn_invalid_dmar(0, ""); |
6ecbf01c DW |
1018 | return -EINVAL; |
1019 | } | |
1020 | ||
c42d9f32 SS |
1021 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
1022 | if (!iommu) | |
1886e8a9 | 1023 | return -ENOMEM; |
c42d9f32 | 1024 | |
78d8e704 | 1025 | if (dmar_alloc_seq_id(iommu) < 0) { |
9f10e5bf | 1026 | pr_err("Failed to allocate seq_id\n"); |
78d8e704 JL |
1027 | err = -ENOSPC; |
1028 | goto error; | |
1029 | } | |
e61d98d8 | 1030 | |
6f5cf521 DD |
1031 | err = map_iommu(iommu, drhd->reg_base_addr); |
1032 | if (err) { | |
9f10e5bf | 1033 | pr_err("Failed to map %s\n", iommu->name); |
78d8e704 | 1034 | goto error_free_seq_id; |
e61d98d8 | 1035 | } |
0815565a | 1036 | |
6f5cf521 | 1037 | err = -EINVAL; |
1b573683 WH |
1038 | agaw = iommu_calculate_agaw(iommu); |
1039 | if (agaw < 0) { | |
bf947fcb DD |
1040 | pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", |
1041 | iommu->seq_id); | |
0815565a | 1042 | goto err_unmap; |
4ed0d3e6 FY |
1043 | } |
1044 | msagaw = iommu_calculate_max_sagaw(iommu); | |
1045 | if (msagaw < 0) { | |
bf947fcb | 1046 | pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", |
1b573683 | 1047 | iommu->seq_id); |
0815565a | 1048 | goto err_unmap; |
1b573683 WH |
1049 | } |
1050 | iommu->agaw = agaw; | |
4ed0d3e6 | 1051 | iommu->msagaw = msagaw; |
67ccac41 | 1052 | iommu->segment = drhd->segment; |
1b573683 | 1053 | |
98fa15f3 | 1054 | iommu->node = NUMA_NO_NODE; |
ee34b32d | 1055 | |
e61d98d8 | 1056 | ver = readl(iommu->reg + DMAR_VER_REG); |
9f10e5bf JR |
1057 | pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", |
1058 | iommu->name, | |
5b6985ce FY |
1059 | (unsigned long long)drhd->reg_base_addr, |
1060 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
1061 | (unsigned long long)iommu->cap, | |
1062 | (unsigned long long)iommu->ecap); | |
e61d98d8 | 1063 | |
3a93c841 TI |
1064 | /* Reflect status in gcmd */ |
1065 | sts = readl(iommu->reg + DMAR_GSTS_REG); | |
1066 | if (sts & DMA_GSTS_IRES) | |
1067 | iommu->gcmd |= DMA_GCMD_IRE; | |
1068 | if (sts & DMA_GSTS_TES) | |
1069 | iommu->gcmd |= DMA_GCMD_TE; | |
1070 | if (sts & DMA_GSTS_QIES) | |
1071 | iommu->gcmd |= DMA_GCMD_QIE; | |
1072 | ||
1f5b3c3f | 1073 | raw_spin_lock_init(&iommu->register_lock); |
e61d98d8 | 1074 | |
bc847454 | 1075 | if (intel_iommu_enabled) { |
39ab9555 JR |
1076 | err = iommu_device_sysfs_add(&iommu->iommu, NULL, |
1077 | intel_iommu_groups, | |
1078 | "%s", iommu->name); | |
1079 | if (err) | |
bc847454 | 1080 | goto err_unmap; |
a5459cfe | 1081 | |
b0119e87 JR |
1082 | iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); |
1083 | ||
1084 | err = iommu_device_register(&iommu->iommu); | |
1085 | if (err) | |
bc847454 | 1086 | goto err_unmap; |
59203379 NK |
1087 | } |
1088 | ||
bc847454 JR |
1089 | drhd->iommu = iommu; |
1090 | ||
1886e8a9 | 1091 | return 0; |
0815565a | 1092 | |
78d8e704 | 1093 | err_unmap: |
6f5cf521 | 1094 | unmap_iommu(iommu); |
78d8e704 JL |
1095 | error_free_seq_id: |
1096 | dmar_free_seq_id(iommu); | |
1097 | error: | |
e61d98d8 | 1098 | kfree(iommu); |
6f5cf521 | 1099 | return err; |
e61d98d8 SS |
1100 | } |
1101 | ||
a868e6b7 | 1102 | static void free_iommu(struct intel_iommu *iommu) |
e61d98d8 | 1103 | { |
c37a0177 AS |
1104 | if (intel_iommu_enabled) { |
1105 | iommu_device_unregister(&iommu->iommu); | |
1106 | iommu_device_sysfs_remove(&iommu->iommu); | |
1107 | } | |
a5459cfe | 1108 | |
a868e6b7 | 1109 | if (iommu->irq) { |
1208225c DW |
1110 | if (iommu->pr_irq) { |
1111 | free_irq(iommu->pr_irq, iommu); | |
1112 | dmar_free_hwirq(iommu->pr_irq); | |
1113 | iommu->pr_irq = 0; | |
1114 | } | |
a868e6b7 | 1115 | free_irq(iommu->irq, iommu); |
a553b142 | 1116 | dmar_free_hwirq(iommu->irq); |
34742db8 | 1117 | iommu->irq = 0; |
a868e6b7 | 1118 | } |
e61d98d8 | 1119 | |
a84da70b JL |
1120 | if (iommu->qi) { |
1121 | free_page((unsigned long)iommu->qi->desc); | |
1122 | kfree(iommu->qi->desc_status); | |
1123 | kfree(iommu->qi); | |
1124 | } | |
1125 | ||
e61d98d8 | 1126 | if (iommu->reg) |
6f5cf521 DD |
1127 | unmap_iommu(iommu); |
1128 | ||
78d8e704 | 1129 | dmar_free_seq_id(iommu); |
e61d98d8 SS |
1130 | kfree(iommu); |
1131 | } | |
fe962e90 SS |
1132 | |
1133 | /* | |
1134 | * Reclaim all the submitted descriptors which have completed its work. | |
1135 | */ | |
1136 | static inline void reclaim_free_desc(struct q_inval *qi) | |
1137 | { | |
6ba6c3a4 YZ |
1138 | while (qi->desc_status[qi->free_tail] == QI_DONE || |
1139 | qi->desc_status[qi->free_tail] == QI_ABORT) { | |
fe962e90 SS |
1140 | qi->desc_status[qi->free_tail] = QI_FREE; |
1141 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
1142 | qi->free_cnt++; | |
1143 | } | |
1144 | } | |
1145 | ||
704126ad YZ |
1146 | static int qi_check_fault(struct intel_iommu *iommu, int index) |
1147 | { | |
1148 | u32 fault; | |
6ba6c3a4 | 1149 | int head, tail; |
704126ad YZ |
1150 | struct q_inval *qi = iommu->qi; |
1151 | int wait_index = (index + 1) % QI_LENGTH; | |
5d308fc1 | 1152 | int shift = qi_shift(iommu); |
704126ad | 1153 | |
6ba6c3a4 YZ |
1154 | if (qi->desc_status[wait_index] == QI_ABORT) |
1155 | return -EAGAIN; | |
1156 | ||
704126ad YZ |
1157 | fault = readl(iommu->reg + DMAR_FSTS_REG); |
1158 | ||
1159 | /* | |
1160 | * If IQE happens, the head points to the descriptor associated | |
1161 | * with the error. No new descriptors are fetched until the IQE | |
1162 | * is cleared. | |
1163 | */ | |
1164 | if (fault & DMA_FSTS_IQE) { | |
1165 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 LB |
1166 | if ((head >> shift) == index) { |
1167 | struct qi_desc *desc = qi->desc + head; | |
1168 | ||
1169 | /* | |
1170 | * desc->qw2 and desc->qw3 are either reserved or | |
1171 | * used by software as private data. We won't print | |
1172 | * out these two qw's for security consideration. | |
1173 | */ | |
1174 | pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n", | |
1175 | (unsigned long long)desc->qw0, | |
1176 | (unsigned long long)desc->qw1); | |
1177 | memcpy(desc, qi->desc + (wait_index << shift), | |
1178 | 1 << shift); | |
704126ad YZ |
1179 | writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); |
1180 | return -EINVAL; | |
1181 | } | |
1182 | } | |
1183 | ||
6ba6c3a4 YZ |
1184 | /* |
1185 | * If ITE happens, all pending wait_desc commands are aborted. | |
1186 | * No new descriptors are fetched until the ITE is cleared. | |
1187 | */ | |
1188 | if (fault & DMA_FSTS_ITE) { | |
1189 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 | 1190 | head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1191 | head |= 1; |
1192 | tail = readl(iommu->reg + DMAR_IQT_REG); | |
5d308fc1 | 1193 | tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1194 | |
1195 | writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); | |
1196 | ||
1197 | do { | |
1198 | if (qi->desc_status[head] == QI_IN_USE) | |
1199 | qi->desc_status[head] = QI_ABORT; | |
1200 | head = (head - 2 + QI_LENGTH) % QI_LENGTH; | |
1201 | } while (head != tail); | |
1202 | ||
1203 | if (qi->desc_status[wait_index] == QI_ABORT) | |
1204 | return -EAGAIN; | |
1205 | } | |
1206 | ||
1207 | if (fault & DMA_FSTS_ICE) | |
1208 | writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); | |
1209 | ||
704126ad YZ |
1210 | return 0; |
1211 | } | |
1212 | ||
fe962e90 SS |
1213 | /* |
1214 | * Submit the queued invalidation descriptor to the remapping | |
1215 | * hardware unit and wait for its completion. | |
1216 | */ | |
704126ad | 1217 | int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) |
fe962e90 | 1218 | { |
6ba6c3a4 | 1219 | int rc; |
fe962e90 | 1220 | struct q_inval *qi = iommu->qi; |
5d308fc1 LB |
1221 | int offset, shift, length; |
1222 | struct qi_desc wait_desc; | |
fe962e90 SS |
1223 | int wait_index, index; |
1224 | unsigned long flags; | |
1225 | ||
1226 | if (!qi) | |
704126ad | 1227 | return 0; |
fe962e90 | 1228 | |
6ba6c3a4 YZ |
1229 | restart: |
1230 | rc = 0; | |
1231 | ||
3b8f4048 | 1232 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 | 1233 | while (qi->free_cnt < 3) { |
3b8f4048 | 1234 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
fe962e90 | 1235 | cpu_relax(); |
3b8f4048 | 1236 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 SS |
1237 | } |
1238 | ||
1239 | index = qi->free_head; | |
1240 | wait_index = (index + 1) % QI_LENGTH; | |
5d308fc1 LB |
1241 | shift = qi_shift(iommu); |
1242 | length = 1 << shift; | |
fe962e90 SS |
1243 | |
1244 | qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE; | |
1245 | ||
5d308fc1 LB |
1246 | offset = index << shift; |
1247 | memcpy(qi->desc + offset, desc, length); | |
1248 | wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) | | |
704126ad | 1249 | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; |
5d308fc1 LB |
1250 | wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); |
1251 | wait_desc.qw2 = 0; | |
1252 | wait_desc.qw3 = 0; | |
fe962e90 | 1253 | |
5d308fc1 LB |
1254 | offset = wait_index << shift; |
1255 | memcpy(qi->desc + offset, &wait_desc, length); | |
fe962e90 | 1256 | |
fe962e90 SS |
1257 | qi->free_head = (qi->free_head + 2) % QI_LENGTH; |
1258 | qi->free_cnt -= 2; | |
1259 | ||
fe962e90 SS |
1260 | /* |
1261 | * update the HW tail register indicating the presence of | |
1262 | * new descriptors. | |
1263 | */ | |
5d308fc1 | 1264 | writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); |
fe962e90 SS |
1265 | |
1266 | while (qi->desc_status[wait_index] != QI_DONE) { | |
f05810c9 SS |
1267 | /* |
1268 | * We will leave the interrupts disabled, to prevent interrupt | |
1269 | * context to queue another cmd while a cmd is already submitted | |
1270 | * and waiting for completion on this cpu. This is to avoid | |
1271 | * a deadlock where the interrupt context can wait indefinitely | |
1272 | * for free slots in the queue. | |
1273 | */ | |
704126ad YZ |
1274 | rc = qi_check_fault(iommu, index); |
1275 | if (rc) | |
6ba6c3a4 | 1276 | break; |
704126ad | 1277 | |
3b8f4048 | 1278 | raw_spin_unlock(&qi->q_lock); |
fe962e90 | 1279 | cpu_relax(); |
3b8f4048 | 1280 | raw_spin_lock(&qi->q_lock); |
fe962e90 | 1281 | } |
6ba6c3a4 YZ |
1282 | |
1283 | qi->desc_status[index] = QI_DONE; | |
fe962e90 SS |
1284 | |
1285 | reclaim_free_desc(qi); | |
3b8f4048 | 1286 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
704126ad | 1287 | |
6ba6c3a4 YZ |
1288 | if (rc == -EAGAIN) |
1289 | goto restart; | |
1290 | ||
704126ad | 1291 | return rc; |
fe962e90 SS |
1292 | } |
1293 | ||
1294 | /* | |
1295 | * Flush the global interrupt entry cache. | |
1296 | */ | |
1297 | void qi_global_iec(struct intel_iommu *iommu) | |
1298 | { | |
1299 | struct qi_desc desc; | |
1300 | ||
5d308fc1 LB |
1301 | desc.qw0 = QI_IEC_TYPE; |
1302 | desc.qw1 = 0; | |
1303 | desc.qw2 = 0; | |
1304 | desc.qw3 = 0; | |
fe962e90 | 1305 | |
704126ad | 1306 | /* should never fail */ |
fe962e90 SS |
1307 | qi_submit_sync(&desc, iommu); |
1308 | } | |
1309 | ||
4c25a2c1 DW |
1310 | void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, |
1311 | u64 type) | |
3481f210 | 1312 | { |
3481f210 YS |
1313 | struct qi_desc desc; |
1314 | ||
5d308fc1 | 1315 | desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) |
3481f210 | 1316 | | QI_CC_GRAN(type) | QI_CC_TYPE; |
5d308fc1 LB |
1317 | desc.qw1 = 0; |
1318 | desc.qw2 = 0; | |
1319 | desc.qw3 = 0; | |
3481f210 | 1320 | |
4c25a2c1 | 1321 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1322 | } |
1323 | ||
1f0ef2aa DW |
1324 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
1325 | unsigned int size_order, u64 type) | |
3481f210 YS |
1326 | { |
1327 | u8 dw = 0, dr = 0; | |
1328 | ||
1329 | struct qi_desc desc; | |
1330 | int ih = 0; | |
1331 | ||
3481f210 YS |
1332 | if (cap_write_drain(iommu->cap)) |
1333 | dw = 1; | |
1334 | ||
1335 | if (cap_read_drain(iommu->cap)) | |
1336 | dr = 1; | |
1337 | ||
5d308fc1 | 1338 | desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) |
3481f210 | 1339 | | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; |
5d308fc1 | 1340 | desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) |
3481f210 | 1341 | | QI_IOTLB_AM(size_order); |
5d308fc1 LB |
1342 | desc.qw2 = 0; |
1343 | desc.qw3 = 0; | |
3481f210 | 1344 | |
1f0ef2aa | 1345 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1346 | } |
1347 | ||
1c48db44 JP |
1348 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, |
1349 | u16 qdep, u64 addr, unsigned mask) | |
6ba6c3a4 YZ |
1350 | { |
1351 | struct qi_desc desc; | |
1352 | ||
1353 | if (mask) { | |
a85894cd | 1354 | WARN_ON_ONCE(addr & ((1ULL << (VTD_PAGE_SHIFT + mask)) - 1)); |
c8acb28b | 1355 | addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; |
5d308fc1 | 1356 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; |
6ba6c3a4 | 1357 | } else |
5d308fc1 | 1358 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr); |
6ba6c3a4 YZ |
1359 | |
1360 | if (qdep >= QI_DEV_IOTLB_MAX_INVS) | |
1361 | qdep = 0; | |
1362 | ||
5d308fc1 | 1363 | desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | |
1c48db44 | 1364 | QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); |
5d308fc1 LB |
1365 | desc.qw2 = 0; |
1366 | desc.qw3 = 0; | |
6ba6c3a4 YZ |
1367 | |
1368 | qi_submit_sync(&desc, iommu); | |
1369 | } | |
1370 | ||
eba67e5d SS |
1371 | /* |
1372 | * Disable Queued Invalidation interface. | |
1373 | */ | |
1374 | void dmar_disable_qi(struct intel_iommu *iommu) | |
1375 | { | |
1376 | unsigned long flags; | |
1377 | u32 sts; | |
1378 | cycles_t start_time = get_cycles(); | |
1379 | ||
1380 | if (!ecap_qis(iommu->ecap)) | |
1381 | return; | |
1382 | ||
1f5b3c3f | 1383 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 1384 | |
fda3bec1 | 1385 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
1386 | if (!(sts & DMA_GSTS_QIES)) |
1387 | goto end; | |
1388 | ||
1389 | /* | |
1390 | * Give a chance to HW to complete the pending invalidation requests. | |
1391 | */ | |
1392 | while ((readl(iommu->reg + DMAR_IQT_REG) != | |
1393 | readl(iommu->reg + DMAR_IQH_REG)) && | |
1394 | (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) | |
1395 | cpu_relax(); | |
1396 | ||
1397 | iommu->gcmd &= ~DMA_GCMD_QIE; | |
eba67e5d SS |
1398 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
1399 | ||
1400 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | |
1401 | !(sts & DMA_GSTS_QIES), sts); | |
1402 | end: | |
1f5b3c3f | 1403 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
1404 | } |
1405 | ||
eb4a52bc FY |
1406 | /* |
1407 | * Enable queued invalidation. | |
1408 | */ | |
1409 | static void __dmar_enable_qi(struct intel_iommu *iommu) | |
1410 | { | |
c416daa9 | 1411 | u32 sts; |
eb4a52bc FY |
1412 | unsigned long flags; |
1413 | struct q_inval *qi = iommu->qi; | |
5d308fc1 | 1414 | u64 val = virt_to_phys(qi->desc); |
eb4a52bc FY |
1415 | |
1416 | qi->free_head = qi->free_tail = 0; | |
1417 | qi->free_cnt = QI_LENGTH; | |
1418 | ||
5d308fc1 LB |
1419 | /* |
1420 | * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability | |
1421 | * is present. | |
1422 | */ | |
1423 | if (ecap_smts(iommu->ecap)) | |
1424 | val |= (1 << 11) | 1; | |
1425 | ||
1f5b3c3f | 1426 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eb4a52bc FY |
1427 | |
1428 | /* write zero to the tail reg */ | |
1429 | writel(0, iommu->reg + DMAR_IQT_REG); | |
1430 | ||
5d308fc1 | 1431 | dmar_writeq(iommu->reg + DMAR_IQA_REG, val); |
eb4a52bc | 1432 | |
eb4a52bc | 1433 | iommu->gcmd |= DMA_GCMD_QIE; |
c416daa9 | 1434 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
eb4a52bc FY |
1435 | |
1436 | /* Make sure hardware complete it */ | |
1437 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
1438 | ||
1f5b3c3f | 1439 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eb4a52bc FY |
1440 | } |
1441 | ||
fe962e90 SS |
1442 | /* |
1443 | * Enable Queued Invalidation interface. This is a must to support | |
1444 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
1445 | * register based IOTLB invalidation. | |
1446 | */ | |
1447 | int dmar_enable_qi(struct intel_iommu *iommu) | |
1448 | { | |
fe962e90 | 1449 | struct q_inval *qi; |
751cafe3 | 1450 | struct page *desc_page; |
fe962e90 SS |
1451 | |
1452 | if (!ecap_qis(iommu->ecap)) | |
1453 | return -ENOENT; | |
1454 | ||
1455 | /* | |
1456 | * queued invalidation is already setup and enabled. | |
1457 | */ | |
1458 | if (iommu->qi) | |
1459 | return 0; | |
1460 | ||
fa4b57cc | 1461 | iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); |
fe962e90 SS |
1462 | if (!iommu->qi) |
1463 | return -ENOMEM; | |
1464 | ||
1465 | qi = iommu->qi; | |
1466 | ||
5d308fc1 LB |
1467 | /* |
1468 | * Need two pages to accommodate 256 descriptors of 256 bits each | |
1469 | * if the remapping hardware supports scalable mode translation. | |
1470 | */ | |
1471 | desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, | |
1472 | !!ecap_smts(iommu->ecap)); | |
751cafe3 | 1473 | if (!desc_page) { |
fe962e90 | 1474 | kfree(qi); |
b707cb02 | 1475 | iommu->qi = NULL; |
fe962e90 SS |
1476 | return -ENOMEM; |
1477 | } | |
1478 | ||
751cafe3 SS |
1479 | qi->desc = page_address(desc_page); |
1480 | ||
6396bb22 | 1481 | qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); |
fe962e90 SS |
1482 | if (!qi->desc_status) { |
1483 | free_page((unsigned long) qi->desc); | |
1484 | kfree(qi); | |
b707cb02 | 1485 | iommu->qi = NULL; |
fe962e90 SS |
1486 | return -ENOMEM; |
1487 | } | |
1488 | ||
3b8f4048 | 1489 | raw_spin_lock_init(&qi->q_lock); |
fe962e90 | 1490 | |
eb4a52bc | 1491 | __dmar_enable_qi(iommu); |
fe962e90 SS |
1492 | |
1493 | return 0; | |
1494 | } | |
0ac2491f SS |
1495 | |
1496 | /* iommu interrupt handling. Most stuff are MSI-like. */ | |
1497 | ||
9d783ba0 SS |
1498 | enum faulttype { |
1499 | DMA_REMAP, | |
1500 | INTR_REMAP, | |
1501 | UNKNOWN, | |
1502 | }; | |
1503 | ||
1504 | static const char *dma_remap_fault_reasons[] = | |
0ac2491f SS |
1505 | { |
1506 | "Software", | |
1507 | "Present bit in root entry is clear", | |
1508 | "Present bit in context entry is clear", | |
1509 | "Invalid context entry", | |
1510 | "Access beyond MGAW", | |
1511 | "PTE Write access is not set", | |
1512 | "PTE Read access is not set", | |
1513 | "Next page table ptr is invalid", | |
1514 | "Root table address invalid", | |
1515 | "Context table ptr is invalid", | |
1516 | "non-zero reserved fields in RTP", | |
1517 | "non-zero reserved fields in CTP", | |
1518 | "non-zero reserved fields in PTE", | |
4ecccd9e | 1519 | "PCE for translation request specifies blocking", |
0ac2491f | 1520 | }; |
9d783ba0 | 1521 | |
95a02e97 | 1522 | static const char *irq_remap_fault_reasons[] = |
9d783ba0 SS |
1523 | { |
1524 | "Detected reserved fields in the decoded interrupt-remapped request", | |
1525 | "Interrupt index exceeded the interrupt-remapping table size", | |
1526 | "Present field in the IRTE entry is clear", | |
1527 | "Error accessing interrupt-remapping table pointed by IRTA_REG", | |
1528 | "Detected reserved fields in the IRTE entry", | |
1529 | "Blocked a compatibility format interrupt request", | |
1530 | "Blocked an interrupt request due to source-id verification failure", | |
1531 | }; | |
1532 | ||
21004dcd | 1533 | static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) |
0ac2491f | 1534 | { |
fefe1ed1 DC |
1535 | if (fault_reason >= 0x20 && (fault_reason - 0x20 < |
1536 | ARRAY_SIZE(irq_remap_fault_reasons))) { | |
9d783ba0 | 1537 | *fault_type = INTR_REMAP; |
95a02e97 | 1538 | return irq_remap_fault_reasons[fault_reason - 0x20]; |
9d783ba0 SS |
1539 | } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { |
1540 | *fault_type = DMA_REMAP; | |
1541 | return dma_remap_fault_reasons[fault_reason]; | |
1542 | } else { | |
1543 | *fault_type = UNKNOWN; | |
0ac2491f | 1544 | return "Unknown"; |
9d783ba0 | 1545 | } |
0ac2491f SS |
1546 | } |
1547 | ||
1208225c DW |
1548 | |
1549 | static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) | |
1550 | { | |
1551 | if (iommu->irq == irq) | |
1552 | return DMAR_FECTL_REG; | |
1553 | else if (iommu->pr_irq == irq) | |
1554 | return DMAR_PECTL_REG; | |
1555 | else | |
1556 | BUG(); | |
1557 | } | |
1558 | ||
5c2837fb | 1559 | void dmar_msi_unmask(struct irq_data *data) |
0ac2491f | 1560 | { |
dced35ae | 1561 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c | 1562 | int reg = dmar_msi_reg(iommu, data->irq); |
0ac2491f SS |
1563 | unsigned long flag; |
1564 | ||
1565 | /* unmask it */ | |
1f5b3c3f | 1566 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1567 | writel(0, iommu->reg + reg); |
0ac2491f | 1568 | /* Read a reg to force flush the post write */ |
1208225c | 1569 | readl(iommu->reg + reg); |
1f5b3c3f | 1570 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1571 | } |
1572 | ||
5c2837fb | 1573 | void dmar_msi_mask(struct irq_data *data) |
0ac2491f | 1574 | { |
dced35ae | 1575 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c DW |
1576 | int reg = dmar_msi_reg(iommu, data->irq); |
1577 | unsigned long flag; | |
0ac2491f SS |
1578 | |
1579 | /* mask it */ | |
1f5b3c3f | 1580 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1581 | writel(DMA_FECTL_IM, iommu->reg + reg); |
0ac2491f | 1582 | /* Read a reg to force flush the post write */ |
1208225c | 1583 | readl(iommu->reg + reg); |
1f5b3c3f | 1584 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1585 | } |
1586 | ||
1587 | void dmar_msi_write(int irq, struct msi_msg *msg) | |
1588 | { | |
dced35ae | 1589 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1590 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1591 | unsigned long flag; |
1592 | ||
1f5b3c3f | 1593 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1594 | writel(msg->data, iommu->reg + reg + 4); |
1595 | writel(msg->address_lo, iommu->reg + reg + 8); | |
1596 | writel(msg->address_hi, iommu->reg + reg + 12); | |
1f5b3c3f | 1597 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1598 | } |
1599 | ||
1600 | void dmar_msi_read(int irq, struct msi_msg *msg) | |
1601 | { | |
dced35ae | 1602 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1603 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1604 | unsigned long flag; |
1605 | ||
1f5b3c3f | 1606 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1607 | msg->data = readl(iommu->reg + reg + 4); |
1608 | msg->address_lo = readl(iommu->reg + reg + 8); | |
1609 | msg->address_hi = readl(iommu->reg + reg + 12); | |
1f5b3c3f | 1610 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1611 | } |
1612 | ||
1613 | static int dmar_fault_do_one(struct intel_iommu *iommu, int type, | |
1614 | u8 fault_reason, u16 source_id, unsigned long long addr) | |
1615 | { | |
1616 | const char *reason; | |
9d783ba0 | 1617 | int fault_type; |
0ac2491f | 1618 | |
9d783ba0 | 1619 | reason = dmar_get_fault_reason(fault_reason, &fault_type); |
0ac2491f | 1620 | |
9d783ba0 | 1621 | if (fault_type == INTR_REMAP) |
a0fe14d7 AW |
1622 | pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n", |
1623 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
9d783ba0 SS |
1624 | PCI_FUNC(source_id & 0xFF), addr >> 48, |
1625 | fault_reason, reason); | |
1626 | else | |
a0fe14d7 AW |
1627 | pr_err("[%s] Request device [%02x:%02x.%d] fault addr %llx [fault reason %02d] %s\n", |
1628 | type ? "DMA Read" : "DMA Write", | |
1629 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
9d783ba0 | 1630 | PCI_FUNC(source_id & 0xFF), addr, fault_reason, reason); |
0ac2491f SS |
1631 | return 0; |
1632 | } | |
1633 | ||
1634 | #define PRIMARY_FAULT_REG_LEN (16) | |
1531a6a6 | 1635 | irqreturn_t dmar_fault(int irq, void *dev_id) |
0ac2491f SS |
1636 | { |
1637 | struct intel_iommu *iommu = dev_id; | |
1638 | int reg, fault_index; | |
1639 | u32 fault_status; | |
1640 | unsigned long flag; | |
c43fce4e AW |
1641 | static DEFINE_RATELIMIT_STATE(rs, |
1642 | DEFAULT_RATELIMIT_INTERVAL, | |
1643 | DEFAULT_RATELIMIT_BURST); | |
1644 | ||
1f5b3c3f | 1645 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1646 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
6c50d79f | 1647 | if (fault_status && __ratelimit(&rs)) |
bf947fcb | 1648 | pr_err("DRHD: handling fault status reg %x\n", fault_status); |
0ac2491f SS |
1649 | |
1650 | /* TBD: ignore advanced fault log currently */ | |
1651 | if (!(fault_status & DMA_FSTS_PPF)) | |
bd5cdad0 | 1652 | goto unlock_exit; |
0ac2491f SS |
1653 | |
1654 | fault_index = dma_fsts_fault_record_index(fault_status); | |
1655 | reg = cap_fault_reg_offset(iommu->cap); | |
1656 | while (1) { | |
6c50d79f DS |
1657 | /* Disable printing, simply clear the fault when ratelimited */ |
1658 | bool ratelimited = !__ratelimit(&rs); | |
0ac2491f SS |
1659 | u8 fault_reason; |
1660 | u16 source_id; | |
1661 | u64 guest_addr; | |
1662 | int type; | |
1663 | u32 data; | |
1664 | ||
1665 | /* highest 32 bits */ | |
1666 | data = readl(iommu->reg + reg + | |
1667 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1668 | if (!(data & DMA_FRCD_F)) | |
1669 | break; | |
1670 | ||
c43fce4e AW |
1671 | if (!ratelimited) { |
1672 | fault_reason = dma_frcd_fault_reason(data); | |
1673 | type = dma_frcd_type(data); | |
0ac2491f | 1674 | |
c43fce4e AW |
1675 | data = readl(iommu->reg + reg + |
1676 | fault_index * PRIMARY_FAULT_REG_LEN + 8); | |
1677 | source_id = dma_frcd_source_id(data); | |
1678 | ||
1679 | guest_addr = dmar_readq(iommu->reg + reg + | |
1680 | fault_index * PRIMARY_FAULT_REG_LEN); | |
1681 | guest_addr = dma_frcd_page_addr(guest_addr); | |
1682 | } | |
0ac2491f | 1683 | |
0ac2491f SS |
1684 | /* clear the fault */ |
1685 | writel(DMA_FRCD_F, iommu->reg + reg + | |
1686 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1687 | ||
1f5b3c3f | 1688 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f | 1689 | |
c43fce4e AW |
1690 | if (!ratelimited) |
1691 | dmar_fault_do_one(iommu, type, fault_reason, | |
1692 | source_id, guest_addr); | |
0ac2491f SS |
1693 | |
1694 | fault_index++; | |
8211a7b5 | 1695 | if (fault_index >= cap_num_fault_regs(iommu->cap)) |
0ac2491f | 1696 | fault_index = 0; |
1f5b3c3f | 1697 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1698 | } |
0ac2491f | 1699 | |
973b5464 LB |
1700 | writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO, |
1701 | iommu->reg + DMAR_FSTS_REG); | |
bd5cdad0 LZH |
1702 | |
1703 | unlock_exit: | |
1f5b3c3f | 1704 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1705 | return IRQ_HANDLED; |
1706 | } | |
1707 | ||
1708 | int dmar_set_interrupt(struct intel_iommu *iommu) | |
1709 | { | |
1710 | int irq, ret; | |
1711 | ||
9d783ba0 SS |
1712 | /* |
1713 | * Check if the fault interrupt is already initialized. | |
1714 | */ | |
1715 | if (iommu->irq) | |
1716 | return 0; | |
1717 | ||
34742db8 JL |
1718 | irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); |
1719 | if (irq > 0) { | |
1720 | iommu->irq = irq; | |
1721 | } else { | |
9f10e5bf | 1722 | pr_err("No free IRQ vectors\n"); |
0ac2491f SS |
1723 | return -EINVAL; |
1724 | } | |
1725 | ||
477694e7 | 1726 | ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); |
0ac2491f | 1727 | if (ret) |
9f10e5bf | 1728 | pr_err("Can't request irq\n"); |
0ac2491f SS |
1729 | return ret; |
1730 | } | |
9d783ba0 SS |
1731 | |
1732 | int __init enable_drhd_fault_handling(void) | |
1733 | { | |
1734 | struct dmar_drhd_unit *drhd; | |
7c919779 | 1735 | struct intel_iommu *iommu; |
9d783ba0 SS |
1736 | |
1737 | /* | |
1738 | * Enable fault control interrupt. | |
1739 | */ | |
7c919779 | 1740 | for_each_iommu(iommu, drhd) { |
bd5cdad0 | 1741 | u32 fault_status; |
7c919779 | 1742 | int ret = dmar_set_interrupt(iommu); |
9d783ba0 SS |
1743 | |
1744 | if (ret) { | |
e9071b0b | 1745 | pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", |
9d783ba0 SS |
1746 | (unsigned long long)drhd->reg_base_addr, ret); |
1747 | return -1; | |
1748 | } | |
7f99d946 SS |
1749 | |
1750 | /* | |
1751 | * Clear any previous faults. | |
1752 | */ | |
1753 | dmar_fault(iommu->irq, iommu); | |
bd5cdad0 LZH |
1754 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
1755 | writel(fault_status, iommu->reg + DMAR_FSTS_REG); | |
9d783ba0 SS |
1756 | } |
1757 | ||
1758 | return 0; | |
1759 | } | |
eb4a52bc FY |
1760 | |
1761 | /* | |
1762 | * Re-enable Queued Invalidation interface. | |
1763 | */ | |
1764 | int dmar_reenable_qi(struct intel_iommu *iommu) | |
1765 | { | |
1766 | if (!ecap_qis(iommu->ecap)) | |
1767 | return -ENOENT; | |
1768 | ||
1769 | if (!iommu->qi) | |
1770 | return -ENOENT; | |
1771 | ||
1772 | /* | |
1773 | * First disable queued invalidation. | |
1774 | */ | |
1775 | dmar_disable_qi(iommu); | |
1776 | /* | |
1777 | * Then enable queued invalidation again. Since there is no pending | |
1778 | * invalidation requests now, it's safe to re-enable queued | |
1779 | * invalidation. | |
1780 | */ | |
1781 | __dmar_enable_qi(iommu); | |
1782 | ||
1783 | return 0; | |
1784 | } | |
074835f0 YS |
1785 | |
1786 | /* | |
1787 | * Check interrupt remapping support in DMAR table description. | |
1788 | */ | |
0b8973a8 | 1789 | int __init dmar_ir_support(void) |
074835f0 YS |
1790 | { |
1791 | struct acpi_table_dmar *dmar; | |
1792 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
4f506e07 AP |
1793 | if (!dmar) |
1794 | return 0; | |
074835f0 YS |
1795 | return dmar->flags & 0x1; |
1796 | } | |
694835dc | 1797 | |
6b197249 JL |
1798 | /* Check whether DMAR units are in use */ |
1799 | static inline bool dmar_in_use(void) | |
1800 | { | |
1801 | return irq_remapping_enabled || intel_iommu_enabled; | |
1802 | } | |
1803 | ||
a868e6b7 JL |
1804 | static int __init dmar_free_unused_resources(void) |
1805 | { | |
1806 | struct dmar_drhd_unit *dmaru, *dmaru_n; | |
1807 | ||
6b197249 | 1808 | if (dmar_in_use()) |
a868e6b7 JL |
1809 | return 0; |
1810 | ||
2e455289 JL |
1811 | if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units)) |
1812 | bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
59ce0515 | 1813 | |
3a5670e8 | 1814 | down_write(&dmar_global_lock); |
a868e6b7 JL |
1815 | list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { |
1816 | list_del(&dmaru->list); | |
1817 | dmar_free_drhd(dmaru); | |
1818 | } | |
3a5670e8 | 1819 | up_write(&dmar_global_lock); |
a868e6b7 JL |
1820 | |
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | late_initcall(dmar_free_unused_resources); | |
4db77ff3 | 1825 | IOMMU_INIT_POST(detect_intel_iommu); |
6b197249 JL |
1826 | |
1827 | /* | |
1828 | * DMAR Hotplug Support | |
1829 | * For more details, please refer to Intel(R) Virtualization Technology | |
1830 | * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8 | |
1831 | * "Remapping Hardware Unit Hot Plug". | |
1832 | */ | |
94116f81 AS |
1833 | static guid_t dmar_hp_guid = |
1834 | GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B, | |
1835 | 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF); | |
6b197249 JL |
1836 | |
1837 | /* | |
1838 | * Currently there's only one revision and BIOS will not check the revision id, | |
1839 | * so use 0 for safety. | |
1840 | */ | |
1841 | #define DMAR_DSM_REV_ID 0 | |
1842 | #define DMAR_DSM_FUNC_DRHD 1 | |
1843 | #define DMAR_DSM_FUNC_ATSR 2 | |
1844 | #define DMAR_DSM_FUNC_RHSA 3 | |
1845 | ||
1846 | static inline bool dmar_detect_dsm(acpi_handle handle, int func) | |
1847 | { | |
94116f81 | 1848 | return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func); |
6b197249 JL |
1849 | } |
1850 | ||
1851 | static int dmar_walk_dsm_resource(acpi_handle handle, int func, | |
1852 | dmar_res_handler_t handler, void *arg) | |
1853 | { | |
1854 | int ret = -ENODEV; | |
1855 | union acpi_object *obj; | |
1856 | struct acpi_dmar_header *start; | |
1857 | struct dmar_res_callback callback; | |
1858 | static int res_type[] = { | |
1859 | [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT, | |
1860 | [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS, | |
1861 | [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY, | |
1862 | }; | |
1863 | ||
1864 | if (!dmar_detect_dsm(handle, func)) | |
1865 | return 0; | |
1866 | ||
94116f81 | 1867 | obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, |
6b197249 JL |
1868 | func, NULL, ACPI_TYPE_BUFFER); |
1869 | if (!obj) | |
1870 | return -ENODEV; | |
1871 | ||
1872 | memset(&callback, 0, sizeof(callback)); | |
1873 | callback.cb[res_type[func]] = handler; | |
1874 | callback.arg[res_type[func]] = arg; | |
1875 | start = (struct acpi_dmar_header *)obj->buffer.pointer; | |
1876 | ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); | |
1877 | ||
1878 | ACPI_FREE(obj); | |
1879 | ||
1880 | return ret; | |
1881 | } | |
1882 | ||
1883 | static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg) | |
1884 | { | |
1885 | int ret; | |
1886 | struct dmar_drhd_unit *dmaru; | |
1887 | ||
1888 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1889 | if (!dmaru) | |
1890 | return -ENODEV; | |
1891 | ||
1892 | ret = dmar_ir_hotplug(dmaru, true); | |
1893 | if (ret == 0) | |
1894 | ret = dmar_iommu_hotplug(dmaru, true); | |
1895 | ||
1896 | return ret; | |
1897 | } | |
1898 | ||
1899 | static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg) | |
1900 | { | |
1901 | int i, ret; | |
1902 | struct device *dev; | |
1903 | struct dmar_drhd_unit *dmaru; | |
1904 | ||
1905 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1906 | if (!dmaru) | |
1907 | return 0; | |
1908 | ||
1909 | /* | |
1910 | * All PCI devices managed by this unit should have been destroyed. | |
1911 | */ | |
194dc870 | 1912 | if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { |
6b197249 JL |
1913 | for_each_active_dev_scope(dmaru->devices, |
1914 | dmaru->devices_cnt, i, dev) | |
1915 | return -EBUSY; | |
194dc870 | 1916 | } |
6b197249 JL |
1917 | |
1918 | ret = dmar_ir_hotplug(dmaru, false); | |
1919 | if (ret == 0) | |
1920 | ret = dmar_iommu_hotplug(dmaru, false); | |
1921 | ||
1922 | return ret; | |
1923 | } | |
1924 | ||
1925 | static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg) | |
1926 | { | |
1927 | struct dmar_drhd_unit *dmaru; | |
1928 | ||
1929 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
1930 | if (dmaru) { | |
1931 | list_del_rcu(&dmaru->list); | |
1932 | synchronize_rcu(); | |
1933 | dmar_free_drhd(dmaru); | |
1934 | } | |
1935 | ||
1936 | return 0; | |
1937 | } | |
1938 | ||
1939 | static int dmar_hotplug_insert(acpi_handle handle) | |
1940 | { | |
1941 | int ret; | |
1942 | int drhd_count = 0; | |
1943 | ||
1944 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1945 | &dmar_validate_one_drhd, (void *)1); | |
1946 | if (ret) | |
1947 | goto out; | |
1948 | ||
1949 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1950 | &dmar_parse_one_drhd, (void *)&drhd_count); | |
1951 | if (ret == 0 && drhd_count == 0) { | |
1952 | pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); | |
1953 | goto out; | |
1954 | } else if (ret) { | |
1955 | goto release_drhd; | |
1956 | } | |
1957 | ||
1958 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA, | |
1959 | &dmar_parse_one_rhsa, NULL); | |
1960 | if (ret) | |
1961 | goto release_drhd; | |
1962 | ||
1963 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1964 | &dmar_parse_one_atsr, NULL); | |
1965 | if (ret) | |
1966 | goto release_atsr; | |
1967 | ||
1968 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1969 | &dmar_hp_add_drhd, NULL); | |
1970 | if (!ret) | |
1971 | return 0; | |
1972 | ||
1973 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1974 | &dmar_hp_remove_drhd, NULL); | |
1975 | release_atsr: | |
1976 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1977 | &dmar_release_one_atsr, NULL); | |
1978 | release_drhd: | |
1979 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1980 | &dmar_hp_release_drhd, NULL); | |
1981 | out: | |
1982 | return ret; | |
1983 | } | |
1984 | ||
1985 | static int dmar_hotplug_remove(acpi_handle handle) | |
1986 | { | |
1987 | int ret; | |
1988 | ||
1989 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1990 | &dmar_check_one_atsr, NULL); | |
1991 | if (ret) | |
1992 | return ret; | |
1993 | ||
1994 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
1995 | &dmar_hp_remove_drhd, NULL); | |
1996 | if (ret == 0) { | |
1997 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
1998 | &dmar_release_one_atsr, NULL)); | |
1999 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2000 | &dmar_hp_release_drhd, NULL)); | |
2001 | } else { | |
2002 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2003 | &dmar_hp_add_drhd, NULL); | |
2004 | } | |
2005 | ||
2006 | return ret; | |
2007 | } | |
2008 | ||
d35165a9 JL |
2009 | static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl, |
2010 | void *context, void **retval) | |
2011 | { | |
2012 | acpi_handle *phdl = retval; | |
2013 | ||
2014 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { | |
2015 | *phdl = handle; | |
2016 | return AE_CTRL_TERMINATE; | |
2017 | } | |
2018 | ||
2019 | return AE_OK; | |
2020 | } | |
2021 | ||
6b197249 JL |
2022 | static int dmar_device_hotplug(acpi_handle handle, bool insert) |
2023 | { | |
2024 | int ret; | |
d35165a9 JL |
2025 | acpi_handle tmp = NULL; |
2026 | acpi_status status; | |
6b197249 JL |
2027 | |
2028 | if (!dmar_in_use()) | |
2029 | return 0; | |
2030 | ||
d35165a9 JL |
2031 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { |
2032 | tmp = handle; | |
2033 | } else { | |
2034 | status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, | |
2035 | ACPI_UINT32_MAX, | |
2036 | dmar_get_dsm_handle, | |
2037 | NULL, NULL, &tmp); | |
2038 | if (ACPI_FAILURE(status)) { | |
2039 | pr_warn("Failed to locate _DSM method.\n"); | |
2040 | return -ENXIO; | |
2041 | } | |
2042 | } | |
2043 | if (tmp == NULL) | |
6b197249 JL |
2044 | return 0; |
2045 | ||
2046 | down_write(&dmar_global_lock); | |
2047 | if (insert) | |
d35165a9 | 2048 | ret = dmar_hotplug_insert(tmp); |
6b197249 | 2049 | else |
d35165a9 | 2050 | ret = dmar_hotplug_remove(tmp); |
6b197249 JL |
2051 | up_write(&dmar_global_lock); |
2052 | ||
2053 | return ret; | |
2054 | } | |
2055 | ||
2056 | int dmar_device_add(acpi_handle handle) | |
2057 | { | |
2058 | return dmar_device_hotplug(handle, true); | |
2059 | } | |
2060 | ||
2061 | int dmar_device_remove(acpi_handle handle) | |
2062 | { | |
2063 | return dmar_device_hotplug(handle, false); | |
2064 | } | |
89a6079d LB |
2065 | |
2066 | /* | |
2067 | * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table | |
2068 | * | |
2069 | * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in | |
2070 | * the ACPI DMAR table. This means that the platform boot firmware has made | |
2071 | * sure no device can issue DMA outside of RMRR regions. | |
2072 | */ | |
2073 | bool dmar_platform_optin(void) | |
2074 | { | |
2075 | struct acpi_table_dmar *dmar; | |
2076 | acpi_status status; | |
2077 | bool ret; | |
2078 | ||
2079 | status = acpi_get_table(ACPI_SIG_DMAR, 0, | |
2080 | (struct acpi_table_header **)&dmar); | |
2081 | if (ACPI_FAILURE(status)) | |
2082 | return false; | |
2083 | ||
2084 | ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); | |
2085 | acpi_put_table((struct acpi_table_header *)dmar); | |
2086 | ||
2087 | return ret; | |
2088 | } | |
2089 | EXPORT_SYMBOL_GPL(dmar_platform_optin); |