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3b20eb23 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
10e5247f KA |
2 | /* |
3 | * Copyright (c) 2006, Intel Corporation. | |
4 | * | |
98bcef56 | 5 | * Copyright (C) 2006-2008 Intel Corporation |
6 | * Author: Ashok Raj <ashok.raj@intel.com> | |
7 | * Author: Shaohua Li <shaohua.li@intel.com> | |
8 | * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> | |
10e5247f | 9 | * |
e61d98d8 | 10 | * This file implements early detection/parsing of Remapping Devices |
10e5247f KA |
11 | * reported to OS through BIOS via DMA remapping reporting (DMAR) ACPI |
12 | * tables. | |
e61d98d8 SS |
13 | * |
14 | * These routines are used by both DMA-remapping and Interrupt-remapping | |
10e5247f KA |
15 | */ |
16 | ||
9f10e5bf | 17 | #define pr_fmt(fmt) "DMAR: " fmt |
e9071b0b | 18 | |
10e5247f KA |
19 | #include <linux/pci.h> |
20 | #include <linux/dmar.h> | |
38717946 KA |
21 | #include <linux/iova.h> |
22 | #include <linux/intel-iommu.h> | |
fe962e90 | 23 | #include <linux/timer.h> |
0ac2491f SS |
24 | #include <linux/irq.h> |
25 | #include <linux/interrupt.h> | |
69575d38 | 26 | #include <linux/tboot.h> |
eb27cae8 | 27 | #include <linux/dmi.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
a5459cfe | 29 | #include <linux/iommu.h> |
98fa15f3 | 30 | #include <linux/numa.h> |
da72a379 | 31 | #include <linux/limits.h> |
8a8f422d | 32 | #include <asm/irq_remapping.h> |
4db77ff3 | 33 | #include <asm/iommu_table.h> |
10e5247f | 34 | |
078e1ee2 JR |
35 | #include "irq_remapping.h" |
36 | ||
c2a0b538 JL |
37 | typedef int (*dmar_res_handler_t)(struct acpi_dmar_header *, void *); |
38 | struct dmar_res_callback { | |
39 | dmar_res_handler_t cb[ACPI_DMAR_TYPE_RESERVED]; | |
40 | void *arg[ACPI_DMAR_TYPE_RESERVED]; | |
41 | bool ignore_unhandled; | |
42 | bool print_entry; | |
43 | }; | |
44 | ||
3a5670e8 JL |
45 | /* |
46 | * Assumptions: | |
47 | * 1) The hotplug framework guarentees that DMAR unit will be hot-added | |
48 | * before IO devices managed by that unit. | |
49 | * 2) The hotplug framework guarantees that DMAR unit will be hot-removed | |
50 | * after IO devices managed by that unit. | |
51 | * 3) Hotplug events are rare. | |
52 | * | |
53 | * Locking rules for DMA and interrupt remapping related global data structures: | |
54 | * 1) Use dmar_global_lock in process context | |
55 | * 2) Use RCU in interrupt context | |
10e5247f | 56 | */ |
3a5670e8 | 57 | DECLARE_RWSEM(dmar_global_lock); |
10e5247f | 58 | LIST_HEAD(dmar_drhd_units); |
10e5247f | 59 | |
41750d31 | 60 | struct acpi_table_header * __initdata dmar_tbl; |
2e455289 | 61 | static int dmar_dev_scope_status = 1; |
78d8e704 | 62 | static unsigned long dmar_seq_ids[BITS_TO_LONGS(DMAR_UNITS_SUPPORTED)]; |
10e5247f | 63 | |
694835dc | 64 | static int alloc_iommu(struct dmar_drhd_unit *drhd); |
a868e6b7 | 65 | static void free_iommu(struct intel_iommu *iommu); |
694835dc | 66 | |
b0119e87 JR |
67 | extern const struct iommu_ops intel_iommu_ops; |
68 | ||
6b197249 | 69 | static void dmar_register_drhd_unit(struct dmar_drhd_unit *drhd) |
10e5247f KA |
70 | { |
71 | /* | |
72 | * add INCLUDE_ALL at the tail, so scan the list will find it at | |
73 | * the very end. | |
74 | */ | |
75 | if (drhd->include_all) | |
0e242612 | 76 | list_add_tail_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f | 77 | else |
0e242612 | 78 | list_add_rcu(&drhd->list, &dmar_drhd_units); |
10e5247f KA |
79 | } |
80 | ||
bb3a6b78 | 81 | void *dmar_alloc_dev_scope(void *start, void *end, int *cnt) |
10e5247f KA |
82 | { |
83 | struct acpi_dmar_device_scope *scope; | |
10e5247f KA |
84 | |
85 | *cnt = 0; | |
86 | while (start < end) { | |
87 | scope = start; | |
83118b0d | 88 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || |
07cb52ff | 89 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || |
10e5247f KA |
90 | scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) |
91 | (*cnt)++; | |
ae3e7f3a LC |
92 | else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && |
93 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { | |
e9071b0b | 94 | pr_warn("Unsupported device scope\n"); |
5715f0f9 | 95 | } |
10e5247f KA |
96 | start += scope->length; |
97 | } | |
98 | if (*cnt == 0) | |
bb3a6b78 JL |
99 | return NULL; |
100 | ||
832bd858 | 101 | return kcalloc(*cnt, sizeof(struct dmar_dev_scope), GFP_KERNEL); |
bb3a6b78 JL |
102 | } |
103 | ||
832bd858 | 104 | void dmar_free_dev_scope(struct dmar_dev_scope **devices, int *cnt) |
ada4d4b2 | 105 | { |
b683b230 | 106 | int i; |
832bd858 | 107 | struct device *tmp_dev; |
b683b230 | 108 | |
ada4d4b2 | 109 | if (*devices && *cnt) { |
b683b230 | 110 | for_each_active_dev_scope(*devices, *cnt, i, tmp_dev) |
832bd858 | 111 | put_device(tmp_dev); |
ada4d4b2 | 112 | kfree(*devices); |
ada4d4b2 | 113 | } |
0e242612 JL |
114 | |
115 | *devices = NULL; | |
116 | *cnt = 0; | |
ada4d4b2 JL |
117 | } |
118 | ||
59ce0515 JL |
119 | /* Optimize out kzalloc()/kfree() for normal cases */ |
120 | static char dmar_pci_notify_info_buf[64]; | |
121 | ||
122 | static struct dmar_pci_notify_info * | |
123 | dmar_alloc_pci_notify_info(struct pci_dev *dev, unsigned long event) | |
124 | { | |
125 | int level = 0; | |
126 | size_t size; | |
127 | struct pci_dev *tmp; | |
128 | struct dmar_pci_notify_info *info; | |
129 | ||
130 | BUG_ON(dev->is_virtfn); | |
131 | ||
da72a379 DD |
132 | /* |
133 | * Ignore devices that have a domain number higher than what can | |
134 | * be looked up in DMAR, e.g. VMD subdevices with domain 0x10000 | |
135 | */ | |
136 | if (pci_domain_nr(dev->bus) > U16_MAX) | |
137 | return NULL; | |
138 | ||
59ce0515 JL |
139 | /* Only generate path[] for device addition event */ |
140 | if (event == BUS_NOTIFY_ADD_DEVICE) | |
141 | for (tmp = dev; tmp; tmp = tmp->bus->self) | |
142 | level++; | |
143 | ||
553d66cb | 144 | size = struct_size(info, path, level); |
59ce0515 JL |
145 | if (size <= sizeof(dmar_pci_notify_info_buf)) { |
146 | info = (struct dmar_pci_notify_info *)dmar_pci_notify_info_buf; | |
147 | } else { | |
148 | info = kzalloc(size, GFP_KERNEL); | |
149 | if (!info) { | |
150 | pr_warn("Out of memory when allocating notify_info " | |
151 | "for %s.\n", pci_name(dev)); | |
2e455289 JL |
152 | if (dmar_dev_scope_status == 0) |
153 | dmar_dev_scope_status = -ENOMEM; | |
59ce0515 JL |
154 | return NULL; |
155 | } | |
156 | } | |
157 | ||
158 | info->event = event; | |
159 | info->dev = dev; | |
160 | info->seg = pci_domain_nr(dev->bus); | |
161 | info->level = level; | |
162 | if (event == BUS_NOTIFY_ADD_DEVICE) { | |
5ae0566a JL |
163 | for (tmp = dev; tmp; tmp = tmp->bus->self) { |
164 | level--; | |
57384592 | 165 | info->path[level].bus = tmp->bus->number; |
59ce0515 JL |
166 | info->path[level].device = PCI_SLOT(tmp->devfn); |
167 | info->path[level].function = PCI_FUNC(tmp->devfn); | |
168 | if (pci_is_root_bus(tmp->bus)) | |
169 | info->bus = tmp->bus->number; | |
170 | } | |
171 | } | |
172 | ||
173 | return info; | |
174 | } | |
175 | ||
176 | static inline void dmar_free_pci_notify_info(struct dmar_pci_notify_info *info) | |
177 | { | |
178 | if ((void *)info != dmar_pci_notify_info_buf) | |
179 | kfree(info); | |
180 | } | |
181 | ||
182 | static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, | |
183 | struct acpi_dmar_pci_path *path, int count) | |
184 | { | |
185 | int i; | |
186 | ||
187 | if (info->bus != bus) | |
80f7b3d1 | 188 | goto fallback; |
59ce0515 | 189 | if (info->level != count) |
80f7b3d1 | 190 | goto fallback; |
59ce0515 JL |
191 | |
192 | for (i = 0; i < count; i++) { | |
193 | if (path[i].device != info->path[i].device || | |
194 | path[i].function != info->path[i].function) | |
80f7b3d1 | 195 | goto fallback; |
59ce0515 JL |
196 | } |
197 | ||
198 | return true; | |
80f7b3d1 JR |
199 | |
200 | fallback: | |
201 | ||
202 | if (count != 1) | |
203 | return false; | |
204 | ||
205 | i = info->level - 1; | |
206 | if (bus == info->path[i].bus && | |
207 | path[0].device == info->path[i].device && | |
208 | path[0].function == info->path[i].function) { | |
209 | pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", | |
210 | bus, path[0].device, path[0].function); | |
211 | return true; | |
212 | } | |
213 | ||
214 | return false; | |
59ce0515 JL |
215 | } |
216 | ||
217 | /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ | |
218 | int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, | |
219 | void *start, void*end, u16 segment, | |
832bd858 DW |
220 | struct dmar_dev_scope *devices, |
221 | int devices_cnt) | |
59ce0515 JL |
222 | { |
223 | int i, level; | |
832bd858 | 224 | struct device *tmp, *dev = &info->dev->dev; |
59ce0515 JL |
225 | struct acpi_dmar_device_scope *scope; |
226 | struct acpi_dmar_pci_path *path; | |
227 | ||
228 | if (segment != info->seg) | |
229 | return 0; | |
230 | ||
231 | for (; start < end; start += scope->length) { | |
232 | scope = start; | |
233 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
234 | scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) | |
235 | continue; | |
236 | ||
237 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
238 | level = (scope->length - sizeof(*scope)) / sizeof(*path); | |
239 | if (!dmar_match_pci_path(info, scope->bus, path, level)) | |
240 | continue; | |
241 | ||
ffb2d1eb RD |
242 | /* |
243 | * We expect devices with endpoint scope to have normal PCI | |
244 | * headers, and devices with bridge scope to have bridge PCI | |
245 | * headers. However PCI NTB devices may be listed in the | |
246 | * DMAR table with bridge scope, even though they have a | |
247 | * normal PCI header. NTB devices are identified by class | |
248 | * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch | |
249 | * for this special case. | |
250 | */ | |
251 | if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && | |
252 | info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || | |
253 | (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && | |
254 | (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && | |
53291622 | 255 | info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { |
59ce0515 | 256 | pr_warn("Device scope type does not match for %s\n", |
832bd858 | 257 | pci_name(info->dev)); |
59ce0515 JL |
258 | return -EINVAL; |
259 | } | |
260 | ||
261 | for_each_dev_scope(devices, devices_cnt, i, tmp) | |
262 | if (tmp == NULL) { | |
832bd858 DW |
263 | devices[i].bus = info->dev->bus->number; |
264 | devices[i].devfn = info->dev->devfn; | |
265 | rcu_assign_pointer(devices[i].dev, | |
266 | get_device(dev)); | |
59ce0515 JL |
267 | return 1; |
268 | } | |
269 | BUG_ON(i >= devices_cnt); | |
270 | } | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, | |
832bd858 | 276 | struct dmar_dev_scope *devices, int count) |
59ce0515 JL |
277 | { |
278 | int index; | |
832bd858 | 279 | struct device *tmp; |
59ce0515 JL |
280 | |
281 | if (info->seg != segment) | |
282 | return 0; | |
283 | ||
284 | for_each_active_dev_scope(devices, count, index, tmp) | |
832bd858 | 285 | if (tmp == &info->dev->dev) { |
eecbad7d | 286 | RCU_INIT_POINTER(devices[index].dev, NULL); |
59ce0515 | 287 | synchronize_rcu(); |
832bd858 | 288 | put_device(tmp); |
59ce0515 JL |
289 | return 1; |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) | |
296 | { | |
297 | int ret = 0; | |
298 | struct dmar_drhd_unit *dmaru; | |
299 | struct acpi_dmar_hardware_unit *drhd; | |
300 | ||
301 | for_each_drhd_unit(dmaru) { | |
302 | if (dmaru->include_all) | |
303 | continue; | |
304 | ||
305 | drhd = container_of(dmaru->hdr, | |
306 | struct acpi_dmar_hardware_unit, header); | |
307 | ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), | |
308 | ((void *)drhd) + drhd->header.length, | |
309 | dmaru->segment, | |
310 | dmaru->devices, dmaru->devices_cnt); | |
f9808079 | 311 | if (ret) |
59ce0515 JL |
312 | break; |
313 | } | |
314 | if (ret >= 0) | |
315 | ret = dmar_iommu_notify_scope_dev(info); | |
2e455289 JL |
316 | if (ret < 0 && dmar_dev_scope_status == 0) |
317 | dmar_dev_scope_status = ret; | |
59ce0515 JL |
318 | |
319 | return ret; | |
320 | } | |
321 | ||
322 | static void dmar_pci_bus_del_dev(struct dmar_pci_notify_info *info) | |
323 | { | |
324 | struct dmar_drhd_unit *dmaru; | |
325 | ||
326 | for_each_drhd_unit(dmaru) | |
327 | if (dmar_remove_dev_scope(info, dmaru->segment, | |
328 | dmaru->devices, dmaru->devices_cnt)) | |
329 | break; | |
330 | dmar_iommu_notify_scope_dev(info); | |
331 | } | |
332 | ||
333 | static int dmar_pci_bus_notifier(struct notifier_block *nb, | |
334 | unsigned long action, void *data) | |
335 | { | |
336 | struct pci_dev *pdev = to_pci_dev(data); | |
337 | struct dmar_pci_notify_info *info; | |
338 | ||
1c387188 AR |
339 | /* Only care about add/remove events for physical functions. |
340 | * For VFs we actually do the lookup based on the corresponding | |
341 | * PF in device_to_iommu() anyway. */ | |
59ce0515 JL |
342 | if (pdev->is_virtfn) |
343 | return NOTIFY_DONE; | |
e6a8c9b3 JR |
344 | if (action != BUS_NOTIFY_ADD_DEVICE && |
345 | action != BUS_NOTIFY_REMOVED_DEVICE) | |
59ce0515 JL |
346 | return NOTIFY_DONE; |
347 | ||
348 | info = dmar_alloc_pci_notify_info(pdev, action); | |
349 | if (!info) | |
350 | return NOTIFY_DONE; | |
351 | ||
352 | down_write(&dmar_global_lock); | |
353 | if (action == BUS_NOTIFY_ADD_DEVICE) | |
354 | dmar_pci_bus_add_dev(info); | |
e6a8c9b3 | 355 | else if (action == BUS_NOTIFY_REMOVED_DEVICE) |
59ce0515 JL |
356 | dmar_pci_bus_del_dev(info); |
357 | up_write(&dmar_global_lock); | |
358 | ||
359 | dmar_free_pci_notify_info(info); | |
360 | ||
361 | return NOTIFY_OK; | |
362 | } | |
363 | ||
364 | static struct notifier_block dmar_pci_bus_nb = { | |
365 | .notifier_call = dmar_pci_bus_notifier, | |
366 | .priority = INT_MIN, | |
367 | }; | |
368 | ||
6b197249 JL |
369 | static struct dmar_drhd_unit * |
370 | dmar_find_dmaru(struct acpi_dmar_hardware_unit *drhd) | |
371 | { | |
372 | struct dmar_drhd_unit *dmaru; | |
373 | ||
f5152416 QC |
374 | list_for_each_entry_rcu(dmaru, &dmar_drhd_units, list, |
375 | dmar_rcu_check()) | |
6b197249 JL |
376 | if (dmaru->segment == drhd->segment && |
377 | dmaru->reg_base_addr == drhd->address) | |
378 | return dmaru; | |
379 | ||
380 | return NULL; | |
381 | } | |
382 | ||
10e5247f KA |
383 | /** |
384 | * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition | |
385 | * structure which uniquely represent one DMA remapping hardware unit | |
386 | * present in the platform | |
387 | */ | |
6b197249 | 388 | static int dmar_parse_one_drhd(struct acpi_dmar_header *header, void *arg) |
10e5247f KA |
389 | { |
390 | struct acpi_dmar_hardware_unit *drhd; | |
391 | struct dmar_drhd_unit *dmaru; | |
3f6db659 | 392 | int ret; |
10e5247f | 393 | |
e523b38e | 394 | drhd = (struct acpi_dmar_hardware_unit *)header; |
6b197249 JL |
395 | dmaru = dmar_find_dmaru(drhd); |
396 | if (dmaru) | |
397 | goto out; | |
398 | ||
399 | dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); | |
10e5247f KA |
400 | if (!dmaru) |
401 | return -ENOMEM; | |
402 | ||
6b197249 JL |
403 | /* |
404 | * If header is allocated from slab by ACPI _DSM method, we need to | |
405 | * copy the content because the memory buffer will be freed on return. | |
406 | */ | |
407 | dmaru->hdr = (void *)(dmaru + 1); | |
408 | memcpy(dmaru->hdr, header, header->length); | |
10e5247f | 409 | dmaru->reg_base_addr = drhd->address; |
276dbf99 | 410 | dmaru->segment = drhd->segment; |
10e5247f | 411 | dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ |
07cb52ff DW |
412 | dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), |
413 | ((void *)drhd) + drhd->header.length, | |
414 | &dmaru->devices_cnt); | |
415 | if (dmaru->devices_cnt && dmaru->devices == NULL) { | |
416 | kfree(dmaru); | |
417 | return -ENOMEM; | |
2e455289 | 418 | } |
10e5247f | 419 | |
1886e8a9 SS |
420 | ret = alloc_iommu(dmaru); |
421 | if (ret) { | |
07cb52ff DW |
422 | dmar_free_dev_scope(&dmaru->devices, |
423 | &dmaru->devices_cnt); | |
1886e8a9 SS |
424 | kfree(dmaru); |
425 | return ret; | |
426 | } | |
427 | dmar_register_drhd_unit(dmaru); | |
c2a0b538 | 428 | |
6b197249 | 429 | out: |
c2a0b538 JL |
430 | if (arg) |
431 | (*(int *)arg)++; | |
432 | ||
1886e8a9 SS |
433 | return 0; |
434 | } | |
435 | ||
a868e6b7 JL |
436 | static void dmar_free_drhd(struct dmar_drhd_unit *dmaru) |
437 | { | |
438 | if (dmaru->devices && dmaru->devices_cnt) | |
439 | dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); | |
440 | if (dmaru->iommu) | |
441 | free_iommu(dmaru->iommu); | |
442 | kfree(dmaru); | |
443 | } | |
444 | ||
c2a0b538 JL |
445 | static int __init dmar_parse_one_andd(struct acpi_dmar_header *header, |
446 | void *arg) | |
e625b4a9 DW |
447 | { |
448 | struct acpi_dmar_andd *andd = (void *)header; | |
449 | ||
450 | /* Check for NUL termination within the designated length */ | |
83118b0d | 451 | if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { |
59833696 | 452 | pr_warn(FW_BUG |
e625b4a9 DW |
453 | "Your BIOS is broken; ANDD object name is not NUL-terminated\n" |
454 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
455 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
456 | dmi_get_system_info(DMI_BIOS_VERSION), | |
457 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 458 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
e625b4a9 DW |
459 | return -EINVAL; |
460 | } | |
461 | pr_info("ANDD device: %x name: %s\n", andd->device_number, | |
83118b0d | 462 | andd->device_name); |
e625b4a9 DW |
463 | |
464 | return 0; | |
465 | } | |
466 | ||
aa697079 | 467 | #ifdef CONFIG_ACPI_NUMA |
6b197249 | 468 | static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) |
ee34b32d SS |
469 | { |
470 | struct acpi_dmar_rhsa *rhsa; | |
471 | struct dmar_drhd_unit *drhd; | |
472 | ||
473 | rhsa = (struct acpi_dmar_rhsa *)header; | |
aa697079 | 474 | for_each_drhd_unit(drhd) { |
ee34b32d SS |
475 | if (drhd->reg_base_addr == rhsa->base_address) { |
476 | int node = acpi_map_pxm_to_node(rhsa->proximity_domain); | |
477 | ||
478 | if (!node_online(node)) | |
98fa15f3 | 479 | node = NUMA_NO_NODE; |
ee34b32d | 480 | drhd->iommu->node = node; |
aa697079 DW |
481 | return 0; |
482 | } | |
ee34b32d | 483 | } |
59833696 | 484 | pr_warn(FW_BUG |
fd0c8894 BH |
485 | "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" |
486 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
b0bb0c22 | 487 | rhsa->base_address, |
fd0c8894 BH |
488 | dmi_get_system_info(DMI_BIOS_VENDOR), |
489 | dmi_get_system_info(DMI_BIOS_VERSION), | |
490 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 491 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
ee34b32d | 492 | |
aa697079 | 493 | return 0; |
ee34b32d | 494 | } |
c2a0b538 JL |
495 | #else |
496 | #define dmar_parse_one_rhsa dmar_res_noop | |
aa697079 | 497 | #endif |
ee34b32d | 498 | |
3bd71e18 | 499 | static void |
10e5247f KA |
500 | dmar_table_print_dmar_entry(struct acpi_dmar_header *header) |
501 | { | |
502 | struct acpi_dmar_hardware_unit *drhd; | |
503 | struct acpi_dmar_reserved_memory *rmrr; | |
aa5d2b51 | 504 | struct acpi_dmar_atsr *atsr; |
17b60977 | 505 | struct acpi_dmar_rhsa *rhsa; |
10e5247f KA |
506 | |
507 | switch (header->type) { | |
508 | case ACPI_DMAR_TYPE_HARDWARE_UNIT: | |
aa5d2b51 YZ |
509 | drhd = container_of(header, struct acpi_dmar_hardware_unit, |
510 | header); | |
e9071b0b | 511 | pr_info("DRHD base: %#016Lx flags: %#x\n", |
aa5d2b51 | 512 | (unsigned long long)drhd->address, drhd->flags); |
10e5247f KA |
513 | break; |
514 | case ACPI_DMAR_TYPE_RESERVED_MEMORY: | |
aa5d2b51 YZ |
515 | rmrr = container_of(header, struct acpi_dmar_reserved_memory, |
516 | header); | |
e9071b0b | 517 | pr_info("RMRR base: %#016Lx end: %#016Lx\n", |
5b6985ce FY |
518 | (unsigned long long)rmrr->base_address, |
519 | (unsigned long long)rmrr->end_address); | |
10e5247f | 520 | break; |
83118b0d | 521 | case ACPI_DMAR_TYPE_ROOT_ATS: |
aa5d2b51 | 522 | atsr = container_of(header, struct acpi_dmar_atsr, header); |
e9071b0b | 523 | pr_info("ATSR flags: %#x\n", atsr->flags); |
aa5d2b51 | 524 | break; |
83118b0d | 525 | case ACPI_DMAR_TYPE_HARDWARE_AFFINITY: |
17b60977 | 526 | rhsa = container_of(header, struct acpi_dmar_rhsa, header); |
e9071b0b | 527 | pr_info("RHSA base: %#016Lx proximity domain: %#x\n", |
17b60977 RD |
528 | (unsigned long long)rhsa->base_address, |
529 | rhsa->proximity_domain); | |
530 | break; | |
83118b0d | 531 | case ACPI_DMAR_TYPE_NAMESPACE: |
e625b4a9 DW |
532 | /* We don't print this here because we need to sanity-check |
533 | it first. So print it in dmar_parse_one_andd() instead. */ | |
534 | break; | |
10e5247f KA |
535 | } |
536 | } | |
537 | ||
f6dd5c31 YL |
538 | /** |
539 | * dmar_table_detect - checks to see if the platform supports DMAR devices | |
540 | */ | |
541 | static int __init dmar_table_detect(void) | |
542 | { | |
543 | acpi_status status = AE_OK; | |
544 | ||
545 | /* if we could find DMAR table, then there are DMAR devices */ | |
6b11d1d6 | 546 | status = acpi_get_table(ACPI_SIG_DMAR, 0, &dmar_tbl); |
f6dd5c31 YL |
547 | |
548 | if (ACPI_SUCCESS(status) && !dmar_tbl) { | |
e9071b0b | 549 | pr_warn("Unable to map DMAR\n"); |
f6dd5c31 YL |
550 | status = AE_NOT_FOUND; |
551 | } | |
552 | ||
8326c5d2 | 553 | return ACPI_SUCCESS(status) ? 0 : -ENOENT; |
f6dd5c31 | 554 | } |
aaa9d1dd | 555 | |
c2a0b538 JL |
556 | static int dmar_walk_remapping_entries(struct acpi_dmar_header *start, |
557 | size_t len, struct dmar_res_callback *cb) | |
558 | { | |
c2a0b538 JL |
559 | struct acpi_dmar_header *iter, *next; |
560 | struct acpi_dmar_header *end = ((void *)start) + len; | |
561 | ||
4a8ed2b8 | 562 | for (iter = start; iter < end; iter = next) { |
c2a0b538 JL |
563 | next = (void *)iter + iter->length; |
564 | if (iter->length == 0) { | |
565 | /* Avoid looping forever on bad ACPI tables */ | |
566 | pr_debug(FW_BUG "Invalid 0-length structure\n"); | |
567 | break; | |
568 | } else if (next > end) { | |
569 | /* Avoid passing table end */ | |
9f10e5bf | 570 | pr_warn(FW_BUG "Record passes table end\n"); |
4a8ed2b8 | 571 | return -EINVAL; |
c2a0b538 JL |
572 | } |
573 | ||
574 | if (cb->print_entry) | |
575 | dmar_table_print_dmar_entry(iter); | |
576 | ||
577 | if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { | |
578 | /* continue for forward compatibility */ | |
579 | pr_debug("Unknown DMAR structure type %d\n", | |
580 | iter->type); | |
581 | } else if (cb->cb[iter->type]) { | |
4a8ed2b8 AS |
582 | int ret; |
583 | ||
c2a0b538 | 584 | ret = cb->cb[iter->type](iter, cb->arg[iter->type]); |
4a8ed2b8 AS |
585 | if (ret) |
586 | return ret; | |
c2a0b538 JL |
587 | } else if (!cb->ignore_unhandled) { |
588 | pr_warn("No handler for DMAR structure type %d\n", | |
589 | iter->type); | |
4a8ed2b8 | 590 | return -EINVAL; |
c2a0b538 JL |
591 | } |
592 | } | |
593 | ||
4a8ed2b8 | 594 | return 0; |
c2a0b538 JL |
595 | } |
596 | ||
597 | static inline int dmar_walk_dmar_table(struct acpi_table_dmar *dmar, | |
598 | struct dmar_res_callback *cb) | |
599 | { | |
600 | return dmar_walk_remapping_entries((void *)(dmar + 1), | |
601 | dmar->header.length - sizeof(*dmar), cb); | |
602 | } | |
603 | ||
10e5247f KA |
604 | /** |
605 | * parse_dmar_table - parses the DMA reporting table | |
606 | */ | |
607 | static int __init | |
608 | parse_dmar_table(void) | |
609 | { | |
610 | struct acpi_table_dmar *dmar; | |
7cef3347 | 611 | int drhd_count = 0; |
3f6db659 | 612 | int ret; |
c2a0b538 JL |
613 | struct dmar_res_callback cb = { |
614 | .print_entry = true, | |
615 | .ignore_unhandled = true, | |
616 | .arg[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &drhd_count, | |
617 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_parse_one_drhd, | |
618 | .cb[ACPI_DMAR_TYPE_RESERVED_MEMORY] = &dmar_parse_one_rmrr, | |
619 | .cb[ACPI_DMAR_TYPE_ROOT_ATS] = &dmar_parse_one_atsr, | |
620 | .cb[ACPI_DMAR_TYPE_HARDWARE_AFFINITY] = &dmar_parse_one_rhsa, | |
621 | .cb[ACPI_DMAR_TYPE_NAMESPACE] = &dmar_parse_one_andd, | |
622 | }; | |
10e5247f | 623 | |
f6dd5c31 YL |
624 | /* |
625 | * Do it again, earlier dmar_tbl mapping could be mapped with | |
626 | * fixed map. | |
627 | */ | |
628 | dmar_table_detect(); | |
629 | ||
a59b50e9 JC |
630 | /* |
631 | * ACPI tables may not be DMA protected by tboot, so use DMAR copy | |
632 | * SINIT saved in SinitMleData in TXT heap (which is DMA protected) | |
633 | */ | |
634 | dmar_tbl = tboot_get_dmar_table(dmar_tbl); | |
635 | ||
10e5247f KA |
636 | dmar = (struct acpi_table_dmar *)dmar_tbl; |
637 | if (!dmar) | |
638 | return -ENODEV; | |
639 | ||
5b6985ce | 640 | if (dmar->width < PAGE_SHIFT - 1) { |
e9071b0b | 641 | pr_warn("Invalid DMAR haw\n"); |
10e5247f KA |
642 | return -EINVAL; |
643 | } | |
644 | ||
e9071b0b | 645 | pr_info("Host address width %d\n", dmar->width + 1); |
c2a0b538 JL |
646 | ret = dmar_walk_dmar_table(dmar, &cb); |
647 | if (ret == 0 && drhd_count == 0) | |
7cef3347 | 648 | pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); |
c2a0b538 | 649 | |
10e5247f KA |
650 | return ret; |
651 | } | |
652 | ||
832bd858 DW |
653 | static int dmar_pci_device_match(struct dmar_dev_scope devices[], |
654 | int cnt, struct pci_dev *dev) | |
e61d98d8 SS |
655 | { |
656 | int index; | |
832bd858 | 657 | struct device *tmp; |
e61d98d8 SS |
658 | |
659 | while (dev) { | |
b683b230 | 660 | for_each_active_dev_scope(devices, cnt, index, tmp) |
832bd858 | 661 | if (dev_is_pci(tmp) && dev == to_pci_dev(tmp)) |
e61d98d8 SS |
662 | return 1; |
663 | ||
664 | /* Check our parent */ | |
665 | dev = dev->bus->self; | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | struct dmar_drhd_unit * | |
672 | dmar_find_matched_drhd_unit(struct pci_dev *dev) | |
673 | { | |
0e242612 | 674 | struct dmar_drhd_unit *dmaru; |
2e824f79 YZ |
675 | struct acpi_dmar_hardware_unit *drhd; |
676 | ||
dda56549 Y |
677 | dev = pci_physfn(dev); |
678 | ||
0e242612 | 679 | rcu_read_lock(); |
8b161f0e | 680 | for_each_drhd_unit(dmaru) { |
2e824f79 YZ |
681 | drhd = container_of(dmaru->hdr, |
682 | struct acpi_dmar_hardware_unit, | |
683 | header); | |
684 | ||
685 | if (dmaru->include_all && | |
686 | drhd->segment == pci_domain_nr(dev->bus)) | |
0e242612 | 687 | goto out; |
e61d98d8 | 688 | |
2e824f79 YZ |
689 | if (dmar_pci_device_match(dmaru->devices, |
690 | dmaru->devices_cnt, dev)) | |
0e242612 | 691 | goto out; |
e61d98d8 | 692 | } |
0e242612 JL |
693 | dmaru = NULL; |
694 | out: | |
695 | rcu_read_unlock(); | |
e61d98d8 | 696 | |
0e242612 | 697 | return dmaru; |
e61d98d8 SS |
698 | } |
699 | ||
ed40356b DW |
700 | static void __init dmar_acpi_insert_dev_scope(u8 device_number, |
701 | struct acpi_device *adev) | |
702 | { | |
703 | struct dmar_drhd_unit *dmaru; | |
704 | struct acpi_dmar_hardware_unit *drhd; | |
705 | struct acpi_dmar_device_scope *scope; | |
706 | struct device *tmp; | |
707 | int i; | |
708 | struct acpi_dmar_pci_path *path; | |
709 | ||
710 | for_each_drhd_unit(dmaru) { | |
711 | drhd = container_of(dmaru->hdr, | |
712 | struct acpi_dmar_hardware_unit, | |
713 | header); | |
714 | ||
715 | for (scope = (void *)(drhd + 1); | |
716 | (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; | |
717 | scope = ((void *)scope) + scope->length) { | |
83118b0d | 718 | if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) |
ed40356b DW |
719 | continue; |
720 | if (scope->enumeration_id != device_number) | |
721 | continue; | |
722 | ||
723 | path = (void *)(scope + 1); | |
724 | pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", | |
725 | dev_name(&adev->dev), dmaru->reg_base_addr, | |
726 | scope->bus, path->device, path->function); | |
727 | for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) | |
728 | if (tmp == NULL) { | |
729 | dmaru->devices[i].bus = scope->bus; | |
730 | dmaru->devices[i].devfn = PCI_DEVFN(path->device, | |
731 | path->function); | |
732 | rcu_assign_pointer(dmaru->devices[i].dev, | |
733 | get_device(&adev->dev)); | |
734 | return; | |
735 | } | |
736 | BUG_ON(i >= dmaru->devices_cnt); | |
737 | } | |
738 | } | |
739 | pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", | |
740 | device_number, dev_name(&adev->dev)); | |
741 | } | |
742 | ||
743 | static int __init dmar_acpi_dev_scope_init(void) | |
744 | { | |
11f1a776 JR |
745 | struct acpi_dmar_andd *andd; |
746 | ||
747 | if (dmar_tbl == NULL) | |
748 | return -ENODEV; | |
749 | ||
7713ec06 DW |
750 | for (andd = (void *)dmar_tbl + sizeof(struct acpi_table_dmar); |
751 | ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; | |
752 | andd = ((void *)andd) + andd->header.length) { | |
83118b0d | 753 | if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { |
ed40356b DW |
754 | acpi_handle h; |
755 | struct acpi_device *adev; | |
756 | ||
757 | if (!ACPI_SUCCESS(acpi_get_handle(ACPI_ROOT_OBJECT, | |
83118b0d | 758 | andd->device_name, |
ed40356b DW |
759 | &h))) { |
760 | pr_err("Failed to find handle for ACPI object %s\n", | |
83118b0d | 761 | andd->device_name); |
ed40356b DW |
762 | continue; |
763 | } | |
c0df975f | 764 | if (acpi_bus_get_device(h, &adev)) { |
ed40356b | 765 | pr_err("Failed to get device for ACPI object %s\n", |
83118b0d | 766 | andd->device_name); |
ed40356b DW |
767 | continue; |
768 | } | |
769 | dmar_acpi_insert_dev_scope(andd->device_number, adev); | |
770 | } | |
ed40356b DW |
771 | } |
772 | return 0; | |
773 | } | |
774 | ||
1886e8a9 SS |
775 | int __init dmar_dev_scope_init(void) |
776 | { | |
2e455289 JL |
777 | struct pci_dev *dev = NULL; |
778 | struct dmar_pci_notify_info *info; | |
1886e8a9 | 779 | |
2e455289 JL |
780 | if (dmar_dev_scope_status != 1) |
781 | return dmar_dev_scope_status; | |
c2c7286a | 782 | |
2e455289 JL |
783 | if (list_empty(&dmar_drhd_units)) { |
784 | dmar_dev_scope_status = -ENODEV; | |
785 | } else { | |
786 | dmar_dev_scope_status = 0; | |
787 | ||
63b42624 DW |
788 | dmar_acpi_dev_scope_init(); |
789 | ||
2e455289 JL |
790 | for_each_pci_dev(dev) { |
791 | if (dev->is_virtfn) | |
792 | continue; | |
793 | ||
794 | info = dmar_alloc_pci_notify_info(dev, | |
795 | BUS_NOTIFY_ADD_DEVICE); | |
796 | if (!info) { | |
797 | return dmar_dev_scope_status; | |
798 | } else { | |
799 | dmar_pci_bus_add_dev(info); | |
800 | dmar_free_pci_notify_info(info); | |
801 | } | |
802 | } | |
1886e8a9 SS |
803 | } |
804 | ||
2e455289 | 805 | return dmar_dev_scope_status; |
1886e8a9 SS |
806 | } |
807 | ||
d15a339e | 808 | void __init dmar_register_bus_notifier(void) |
ec154bf5 JR |
809 | { |
810 | bus_register_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
811 | } | |
812 | ||
10e5247f KA |
813 | |
814 | int __init dmar_table_init(void) | |
815 | { | |
1886e8a9 | 816 | static int dmar_table_initialized; |
093f87d2 FY |
817 | int ret; |
818 | ||
cc05301f JL |
819 | if (dmar_table_initialized == 0) { |
820 | ret = parse_dmar_table(); | |
821 | if (ret < 0) { | |
822 | if (ret != -ENODEV) | |
9f10e5bf | 823 | pr_info("Parse DMAR table failure.\n"); |
cc05301f JL |
824 | } else if (list_empty(&dmar_drhd_units)) { |
825 | pr_info("No DMAR devices found\n"); | |
826 | ret = -ENODEV; | |
827 | } | |
093f87d2 | 828 | |
cc05301f JL |
829 | if (ret < 0) |
830 | dmar_table_initialized = ret; | |
831 | else | |
832 | dmar_table_initialized = 1; | |
10e5247f | 833 | } |
093f87d2 | 834 | |
cc05301f | 835 | return dmar_table_initialized < 0 ? dmar_table_initialized : 0; |
10e5247f KA |
836 | } |
837 | ||
3a8663ee BH |
838 | static void warn_invalid_dmar(u64 addr, const char *message) |
839 | { | |
59833696 | 840 | pr_warn_once(FW_BUG |
fd0c8894 BH |
841 | "Your BIOS is broken; DMAR reported at address %llx%s!\n" |
842 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
843 | addr, message, | |
844 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
845 | dmi_get_system_info(DMI_BIOS_VERSION), | |
846 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
59833696 | 847 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
3a8663ee | 848 | } |
6ecbf01c | 849 | |
c2a0b538 JL |
850 | static int __ref |
851 | dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg) | |
86cf898e | 852 | { |
86cf898e | 853 | struct acpi_dmar_hardware_unit *drhd; |
c2a0b538 JL |
854 | void __iomem *addr; |
855 | u64 cap, ecap; | |
86cf898e | 856 | |
c2a0b538 JL |
857 | drhd = (void *)entry; |
858 | if (!drhd->address) { | |
859 | warn_invalid_dmar(0, ""); | |
860 | return -EINVAL; | |
861 | } | |
2c992208 | 862 | |
6b197249 JL |
863 | if (arg) |
864 | addr = ioremap(drhd->address, VTD_PAGE_SIZE); | |
865 | else | |
866 | addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); | |
c2a0b538 | 867 | if (!addr) { |
9f10e5bf | 868 | pr_warn("Can't validate DRHD address: %llx\n", drhd->address); |
c2a0b538 JL |
869 | return -EINVAL; |
870 | } | |
6b197249 | 871 | |
c2a0b538 JL |
872 | cap = dmar_readq(addr + DMAR_CAP_REG); |
873 | ecap = dmar_readq(addr + DMAR_ECAP_REG); | |
6b197249 JL |
874 | |
875 | if (arg) | |
876 | iounmap(addr); | |
877 | else | |
878 | early_iounmap(addr, VTD_PAGE_SIZE); | |
86cf898e | 879 | |
c2a0b538 JL |
880 | if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { |
881 | warn_invalid_dmar(drhd->address, " returns all ones"); | |
882 | return -EINVAL; | |
86cf898e | 883 | } |
2c992208 | 884 | |
2c992208 | 885 | return 0; |
86cf898e DW |
886 | } |
887 | ||
480125ba | 888 | int __init detect_intel_iommu(void) |
2ae21010 SS |
889 | { |
890 | int ret; | |
c2a0b538 JL |
891 | struct dmar_res_callback validate_drhd_cb = { |
892 | .cb[ACPI_DMAR_TYPE_HARDWARE_UNIT] = &dmar_validate_one_drhd, | |
893 | .ignore_unhandled = true, | |
894 | }; | |
2ae21010 | 895 | |
3a5670e8 | 896 | down_write(&dmar_global_lock); |
f6dd5c31 | 897 | ret = dmar_table_detect(); |
8326c5d2 AS |
898 | if (!ret) |
899 | ret = dmar_walk_dmar_table((struct acpi_table_dmar *)dmar_tbl, | |
900 | &validate_drhd_cb); | |
901 | if (!ret && !no_iommu && !iommu_detected && !dmar_disabled) { | |
c2a0b538 JL |
902 | iommu_detected = 1; |
903 | /* Make sure ACS will be enabled */ | |
904 | pci_request_acs(); | |
905 | } | |
f5d1b97b | 906 | |
9d5ce73a | 907 | #ifdef CONFIG_X86 |
6c3a44ed | 908 | if (!ret) { |
c2a0b538 | 909 | x86_init.iommu.iommu_init = intel_iommu_init; |
6c3a44ed DD |
910 | x86_platform.iommu_shutdown = intel_iommu_shutdown; |
911 | } | |
912 | ||
2ae21010 | 913 | #endif |
c2a0b538 | 914 | |
696c7f8e RW |
915 | if (dmar_tbl) { |
916 | acpi_put_table(dmar_tbl); | |
917 | dmar_tbl = NULL; | |
918 | } | |
3a5670e8 | 919 | up_write(&dmar_global_lock); |
480125ba | 920 | |
8326c5d2 | 921 | return ret ? ret : 1; |
2ae21010 SS |
922 | } |
923 | ||
6f5cf521 DD |
924 | static void unmap_iommu(struct intel_iommu *iommu) |
925 | { | |
926 | iounmap(iommu->reg); | |
927 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
928 | } | |
929 | ||
930 | /** | |
931 | * map_iommu: map the iommu's registers | |
932 | * @iommu: the iommu to map | |
933 | * @phys_addr: the physical address of the base resgister | |
e9071b0b | 934 | * |
6f5cf521 | 935 | * Memory map the iommu's registers. Start w/ a single page, and |
e9071b0b | 936 | * possibly expand if that turns out to be insufficent. |
6f5cf521 DD |
937 | */ |
938 | static int map_iommu(struct intel_iommu *iommu, u64 phys_addr) | |
939 | { | |
940 | int map_size, err=0; | |
941 | ||
942 | iommu->reg_phys = phys_addr; | |
943 | iommu->reg_size = VTD_PAGE_SIZE; | |
944 | ||
945 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { | |
9f10e5bf | 946 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
947 | err = -EBUSY; |
948 | goto out; | |
949 | } | |
950 | ||
951 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
952 | if (!iommu->reg) { | |
9f10e5bf | 953 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
954 | err = -ENOMEM; |
955 | goto release; | |
956 | } | |
957 | ||
958 | iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); | |
959 | iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); | |
960 | ||
961 | if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { | |
962 | err = -EINVAL; | |
963 | warn_invalid_dmar(phys_addr, " returns all ones"); | |
964 | goto unmap; | |
965 | } | |
966 | ||
967 | /* the registers might be more than one page */ | |
968 | map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), | |
969 | cap_max_fault_reg_offset(iommu->cap)); | |
970 | map_size = VTD_PAGE_ALIGN(map_size); | |
971 | if (map_size > iommu->reg_size) { | |
972 | iounmap(iommu->reg); | |
973 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
974 | iommu->reg_size = map_size; | |
975 | if (!request_mem_region(iommu->reg_phys, iommu->reg_size, | |
976 | iommu->name)) { | |
9f10e5bf | 977 | pr_err("Can't reserve memory\n"); |
6f5cf521 DD |
978 | err = -EBUSY; |
979 | goto out; | |
980 | } | |
981 | iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); | |
982 | if (!iommu->reg) { | |
9f10e5bf | 983 | pr_err("Can't map the region\n"); |
6f5cf521 DD |
984 | err = -ENOMEM; |
985 | goto release; | |
986 | } | |
987 | } | |
988 | err = 0; | |
989 | goto out; | |
990 | ||
991 | unmap: | |
992 | iounmap(iommu->reg); | |
993 | release: | |
994 | release_mem_region(iommu->reg_phys, iommu->reg_size); | |
995 | out: | |
996 | return err; | |
997 | } | |
998 | ||
78d8e704 JL |
999 | static int dmar_alloc_seq_id(struct intel_iommu *iommu) |
1000 | { | |
1001 | iommu->seq_id = find_first_zero_bit(dmar_seq_ids, | |
1002 | DMAR_UNITS_SUPPORTED); | |
1003 | if (iommu->seq_id >= DMAR_UNITS_SUPPORTED) { | |
1004 | iommu->seq_id = -1; | |
1005 | } else { | |
1006 | set_bit(iommu->seq_id, dmar_seq_ids); | |
1007 | sprintf(iommu->name, "dmar%d", iommu->seq_id); | |
1008 | } | |
1009 | ||
1010 | return iommu->seq_id; | |
1011 | } | |
1012 | ||
1013 | static void dmar_free_seq_id(struct intel_iommu *iommu) | |
1014 | { | |
1015 | if (iommu->seq_id >= 0) { | |
1016 | clear_bit(iommu->seq_id, dmar_seq_ids); | |
1017 | iommu->seq_id = -1; | |
1018 | } | |
1019 | } | |
1020 | ||
694835dc | 1021 | static int alloc_iommu(struct dmar_drhd_unit *drhd) |
e61d98d8 | 1022 | { |
c42d9f32 | 1023 | struct intel_iommu *iommu; |
3a93c841 | 1024 | u32 ver, sts; |
43f7392b | 1025 | int agaw = 0; |
4ed0d3e6 | 1026 | int msagaw = 0; |
6f5cf521 | 1027 | int err; |
c42d9f32 | 1028 | |
6ecbf01c | 1029 | if (!drhd->reg_base_addr) { |
3a8663ee | 1030 | warn_invalid_dmar(0, ""); |
6ecbf01c DW |
1031 | return -EINVAL; |
1032 | } | |
1033 | ||
c42d9f32 SS |
1034 | iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); |
1035 | if (!iommu) | |
1886e8a9 | 1036 | return -ENOMEM; |
c42d9f32 | 1037 | |
78d8e704 | 1038 | if (dmar_alloc_seq_id(iommu) < 0) { |
9f10e5bf | 1039 | pr_err("Failed to allocate seq_id\n"); |
78d8e704 JL |
1040 | err = -ENOSPC; |
1041 | goto error; | |
1042 | } | |
e61d98d8 | 1043 | |
6f5cf521 DD |
1044 | err = map_iommu(iommu, drhd->reg_base_addr); |
1045 | if (err) { | |
9f10e5bf | 1046 | pr_err("Failed to map %s\n", iommu->name); |
78d8e704 | 1047 | goto error_free_seq_id; |
e61d98d8 | 1048 | } |
0815565a | 1049 | |
6f5cf521 | 1050 | err = -EINVAL; |
1b573683 WH |
1051 | agaw = iommu_calculate_agaw(iommu); |
1052 | if (agaw < 0) { | |
bf947fcb DD |
1053 | pr_err("Cannot get a valid agaw for iommu (seq_id = %d)\n", |
1054 | iommu->seq_id); | |
0815565a | 1055 | goto err_unmap; |
4ed0d3e6 FY |
1056 | } |
1057 | msagaw = iommu_calculate_max_sagaw(iommu); | |
1058 | if (msagaw < 0) { | |
bf947fcb | 1059 | pr_err("Cannot get a valid max agaw for iommu (seq_id = %d)\n", |
1b573683 | 1060 | iommu->seq_id); |
0815565a | 1061 | goto err_unmap; |
1b573683 WH |
1062 | } |
1063 | iommu->agaw = agaw; | |
4ed0d3e6 | 1064 | iommu->msagaw = msagaw; |
67ccac41 | 1065 | iommu->segment = drhd->segment; |
1b573683 | 1066 | |
98fa15f3 | 1067 | iommu->node = NUMA_NO_NODE; |
ee34b32d | 1068 | |
e61d98d8 | 1069 | ver = readl(iommu->reg + DMAR_VER_REG); |
9f10e5bf JR |
1070 | pr_info("%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\n", |
1071 | iommu->name, | |
5b6985ce FY |
1072 | (unsigned long long)drhd->reg_base_addr, |
1073 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver), | |
1074 | (unsigned long long)iommu->cap, | |
1075 | (unsigned long long)iommu->ecap); | |
e61d98d8 | 1076 | |
3a93c841 TI |
1077 | /* Reflect status in gcmd */ |
1078 | sts = readl(iommu->reg + DMAR_GSTS_REG); | |
1079 | if (sts & DMA_GSTS_IRES) | |
1080 | iommu->gcmd |= DMA_GCMD_IRE; | |
1081 | if (sts & DMA_GSTS_TES) | |
1082 | iommu->gcmd |= DMA_GCMD_TE; | |
1083 | if (sts & DMA_GSTS_QIES) | |
1084 | iommu->gcmd |= DMA_GCMD_QIE; | |
1085 | ||
1f5b3c3f | 1086 | raw_spin_lock_init(&iommu->register_lock); |
e61d98d8 | 1087 | |
bc847454 | 1088 | if (intel_iommu_enabled) { |
39ab9555 JR |
1089 | err = iommu_device_sysfs_add(&iommu->iommu, NULL, |
1090 | intel_iommu_groups, | |
1091 | "%s", iommu->name); | |
1092 | if (err) | |
bc847454 | 1093 | goto err_unmap; |
a5459cfe | 1094 | |
b0119e87 JR |
1095 | iommu_device_set_ops(&iommu->iommu, &intel_iommu_ops); |
1096 | ||
1097 | err = iommu_device_register(&iommu->iommu); | |
1098 | if (err) | |
bc847454 | 1099 | goto err_unmap; |
59203379 NK |
1100 | } |
1101 | ||
bc847454 JR |
1102 | drhd->iommu = iommu; |
1103 | ||
1886e8a9 | 1104 | return 0; |
0815565a | 1105 | |
78d8e704 | 1106 | err_unmap: |
6f5cf521 | 1107 | unmap_iommu(iommu); |
78d8e704 JL |
1108 | error_free_seq_id: |
1109 | dmar_free_seq_id(iommu); | |
1110 | error: | |
e61d98d8 | 1111 | kfree(iommu); |
6f5cf521 | 1112 | return err; |
e61d98d8 SS |
1113 | } |
1114 | ||
a868e6b7 | 1115 | static void free_iommu(struct intel_iommu *iommu) |
e61d98d8 | 1116 | { |
c37a0177 AS |
1117 | if (intel_iommu_enabled) { |
1118 | iommu_device_unregister(&iommu->iommu); | |
1119 | iommu_device_sysfs_remove(&iommu->iommu); | |
1120 | } | |
a5459cfe | 1121 | |
a868e6b7 | 1122 | if (iommu->irq) { |
1208225c DW |
1123 | if (iommu->pr_irq) { |
1124 | free_irq(iommu->pr_irq, iommu); | |
1125 | dmar_free_hwirq(iommu->pr_irq); | |
1126 | iommu->pr_irq = 0; | |
1127 | } | |
a868e6b7 | 1128 | free_irq(iommu->irq, iommu); |
a553b142 | 1129 | dmar_free_hwirq(iommu->irq); |
34742db8 | 1130 | iommu->irq = 0; |
a868e6b7 | 1131 | } |
e61d98d8 | 1132 | |
a84da70b JL |
1133 | if (iommu->qi) { |
1134 | free_page((unsigned long)iommu->qi->desc); | |
1135 | kfree(iommu->qi->desc_status); | |
1136 | kfree(iommu->qi); | |
1137 | } | |
1138 | ||
e61d98d8 | 1139 | if (iommu->reg) |
6f5cf521 DD |
1140 | unmap_iommu(iommu); |
1141 | ||
78d8e704 | 1142 | dmar_free_seq_id(iommu); |
e61d98d8 SS |
1143 | kfree(iommu); |
1144 | } | |
fe962e90 SS |
1145 | |
1146 | /* | |
1147 | * Reclaim all the submitted descriptors which have completed its work. | |
1148 | */ | |
1149 | static inline void reclaim_free_desc(struct q_inval *qi) | |
1150 | { | |
6ba6c3a4 YZ |
1151 | while (qi->desc_status[qi->free_tail] == QI_DONE || |
1152 | qi->desc_status[qi->free_tail] == QI_ABORT) { | |
fe962e90 SS |
1153 | qi->desc_status[qi->free_tail] = QI_FREE; |
1154 | qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; | |
1155 | qi->free_cnt++; | |
1156 | } | |
1157 | } | |
1158 | ||
704126ad YZ |
1159 | static int qi_check_fault(struct intel_iommu *iommu, int index) |
1160 | { | |
1161 | u32 fault; | |
6ba6c3a4 | 1162 | int head, tail; |
704126ad YZ |
1163 | struct q_inval *qi = iommu->qi; |
1164 | int wait_index = (index + 1) % QI_LENGTH; | |
5d308fc1 | 1165 | int shift = qi_shift(iommu); |
704126ad | 1166 | |
6ba6c3a4 YZ |
1167 | if (qi->desc_status[wait_index] == QI_ABORT) |
1168 | return -EAGAIN; | |
1169 | ||
704126ad YZ |
1170 | fault = readl(iommu->reg + DMAR_FSTS_REG); |
1171 | ||
1172 | /* | |
1173 | * If IQE happens, the head points to the descriptor associated | |
1174 | * with the error. No new descriptors are fetched until the IQE | |
1175 | * is cleared. | |
1176 | */ | |
1177 | if (fault & DMA_FSTS_IQE) { | |
1178 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 LB |
1179 | if ((head >> shift) == index) { |
1180 | struct qi_desc *desc = qi->desc + head; | |
1181 | ||
1182 | /* | |
1183 | * desc->qw2 and desc->qw3 are either reserved or | |
1184 | * used by software as private data. We won't print | |
1185 | * out these two qw's for security consideration. | |
1186 | */ | |
1187 | pr_err("VT-d detected invalid descriptor: qw0 = %llx, qw1 = %llx\n", | |
1188 | (unsigned long long)desc->qw0, | |
1189 | (unsigned long long)desc->qw1); | |
1190 | memcpy(desc, qi->desc + (wait_index << shift), | |
1191 | 1 << shift); | |
704126ad YZ |
1192 | writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); |
1193 | return -EINVAL; | |
1194 | } | |
1195 | } | |
1196 | ||
6ba6c3a4 YZ |
1197 | /* |
1198 | * If ITE happens, all pending wait_desc commands are aborted. | |
1199 | * No new descriptors are fetched until the ITE is cleared. | |
1200 | */ | |
1201 | if (fault & DMA_FSTS_ITE) { | |
1202 | head = readl(iommu->reg + DMAR_IQH_REG); | |
5d308fc1 | 1203 | head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1204 | head |= 1; |
1205 | tail = readl(iommu->reg + DMAR_IQT_REG); | |
5d308fc1 | 1206 | tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; |
6ba6c3a4 YZ |
1207 | |
1208 | writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); | |
1209 | ||
1210 | do { | |
1211 | if (qi->desc_status[head] == QI_IN_USE) | |
1212 | qi->desc_status[head] = QI_ABORT; | |
1213 | head = (head - 2 + QI_LENGTH) % QI_LENGTH; | |
1214 | } while (head != tail); | |
1215 | ||
1216 | if (qi->desc_status[wait_index] == QI_ABORT) | |
1217 | return -EAGAIN; | |
1218 | } | |
1219 | ||
1220 | if (fault & DMA_FSTS_ICE) | |
1221 | writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); | |
1222 | ||
704126ad YZ |
1223 | return 0; |
1224 | } | |
1225 | ||
fe962e90 SS |
1226 | /* |
1227 | * Submit the queued invalidation descriptor to the remapping | |
1228 | * hardware unit and wait for its completion. | |
1229 | */ | |
704126ad | 1230 | int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu) |
fe962e90 | 1231 | { |
6ba6c3a4 | 1232 | int rc; |
fe962e90 | 1233 | struct q_inval *qi = iommu->qi; |
5d308fc1 LB |
1234 | int offset, shift, length; |
1235 | struct qi_desc wait_desc; | |
fe962e90 SS |
1236 | int wait_index, index; |
1237 | unsigned long flags; | |
1238 | ||
1239 | if (!qi) | |
704126ad | 1240 | return 0; |
fe962e90 | 1241 | |
6ba6c3a4 YZ |
1242 | restart: |
1243 | rc = 0; | |
1244 | ||
3b8f4048 | 1245 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 | 1246 | while (qi->free_cnt < 3) { |
3b8f4048 | 1247 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
fe962e90 | 1248 | cpu_relax(); |
3b8f4048 | 1249 | raw_spin_lock_irqsave(&qi->q_lock, flags); |
fe962e90 SS |
1250 | } |
1251 | ||
1252 | index = qi->free_head; | |
1253 | wait_index = (index + 1) % QI_LENGTH; | |
5d308fc1 LB |
1254 | shift = qi_shift(iommu); |
1255 | length = 1 << shift; | |
fe962e90 SS |
1256 | |
1257 | qi->desc_status[index] = qi->desc_status[wait_index] = QI_IN_USE; | |
1258 | ||
5d308fc1 LB |
1259 | offset = index << shift; |
1260 | memcpy(qi->desc + offset, desc, length); | |
1261 | wait_desc.qw0 = QI_IWD_STATUS_DATA(QI_DONE) | | |
704126ad | 1262 | QI_IWD_STATUS_WRITE | QI_IWD_TYPE; |
5d308fc1 LB |
1263 | wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); |
1264 | wait_desc.qw2 = 0; | |
1265 | wait_desc.qw3 = 0; | |
fe962e90 | 1266 | |
5d308fc1 LB |
1267 | offset = wait_index << shift; |
1268 | memcpy(qi->desc + offset, &wait_desc, length); | |
fe962e90 | 1269 | |
fe962e90 SS |
1270 | qi->free_head = (qi->free_head + 2) % QI_LENGTH; |
1271 | qi->free_cnt -= 2; | |
1272 | ||
fe962e90 SS |
1273 | /* |
1274 | * update the HW tail register indicating the presence of | |
1275 | * new descriptors. | |
1276 | */ | |
5d308fc1 | 1277 | writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); |
fe962e90 SS |
1278 | |
1279 | while (qi->desc_status[wait_index] != QI_DONE) { | |
f05810c9 SS |
1280 | /* |
1281 | * We will leave the interrupts disabled, to prevent interrupt | |
1282 | * context to queue another cmd while a cmd is already submitted | |
1283 | * and waiting for completion on this cpu. This is to avoid | |
1284 | * a deadlock where the interrupt context can wait indefinitely | |
1285 | * for free slots in the queue. | |
1286 | */ | |
704126ad YZ |
1287 | rc = qi_check_fault(iommu, index); |
1288 | if (rc) | |
6ba6c3a4 | 1289 | break; |
704126ad | 1290 | |
3b8f4048 | 1291 | raw_spin_unlock(&qi->q_lock); |
fe962e90 | 1292 | cpu_relax(); |
3b8f4048 | 1293 | raw_spin_lock(&qi->q_lock); |
fe962e90 | 1294 | } |
6ba6c3a4 YZ |
1295 | |
1296 | qi->desc_status[index] = QI_DONE; | |
fe962e90 SS |
1297 | |
1298 | reclaim_free_desc(qi); | |
3b8f4048 | 1299 | raw_spin_unlock_irqrestore(&qi->q_lock, flags); |
704126ad | 1300 | |
6ba6c3a4 YZ |
1301 | if (rc == -EAGAIN) |
1302 | goto restart; | |
1303 | ||
704126ad | 1304 | return rc; |
fe962e90 SS |
1305 | } |
1306 | ||
1307 | /* | |
1308 | * Flush the global interrupt entry cache. | |
1309 | */ | |
1310 | void qi_global_iec(struct intel_iommu *iommu) | |
1311 | { | |
1312 | struct qi_desc desc; | |
1313 | ||
5d308fc1 LB |
1314 | desc.qw0 = QI_IEC_TYPE; |
1315 | desc.qw1 = 0; | |
1316 | desc.qw2 = 0; | |
1317 | desc.qw3 = 0; | |
fe962e90 | 1318 | |
704126ad | 1319 | /* should never fail */ |
fe962e90 SS |
1320 | qi_submit_sync(&desc, iommu); |
1321 | } | |
1322 | ||
4c25a2c1 DW |
1323 | void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm, |
1324 | u64 type) | |
3481f210 | 1325 | { |
3481f210 YS |
1326 | struct qi_desc desc; |
1327 | ||
5d308fc1 | 1328 | desc.qw0 = QI_CC_FM(fm) | QI_CC_SID(sid) | QI_CC_DID(did) |
3481f210 | 1329 | | QI_CC_GRAN(type) | QI_CC_TYPE; |
5d308fc1 LB |
1330 | desc.qw1 = 0; |
1331 | desc.qw2 = 0; | |
1332 | desc.qw3 = 0; | |
3481f210 | 1333 | |
4c25a2c1 | 1334 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1335 | } |
1336 | ||
1f0ef2aa DW |
1337 | void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr, |
1338 | unsigned int size_order, u64 type) | |
3481f210 YS |
1339 | { |
1340 | u8 dw = 0, dr = 0; | |
1341 | ||
1342 | struct qi_desc desc; | |
1343 | int ih = 0; | |
1344 | ||
3481f210 YS |
1345 | if (cap_write_drain(iommu->cap)) |
1346 | dw = 1; | |
1347 | ||
1348 | if (cap_read_drain(iommu->cap)) | |
1349 | dr = 1; | |
1350 | ||
5d308fc1 | 1351 | desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw) |
3481f210 | 1352 | | QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE; |
5d308fc1 | 1353 | desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih) |
3481f210 | 1354 | | QI_IOTLB_AM(size_order); |
5d308fc1 LB |
1355 | desc.qw2 = 0; |
1356 | desc.qw3 = 0; | |
3481f210 | 1357 | |
1f0ef2aa | 1358 | qi_submit_sync(&desc, iommu); |
3481f210 YS |
1359 | } |
1360 | ||
1c48db44 JP |
1361 | void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid, |
1362 | u16 qdep, u64 addr, unsigned mask) | |
6ba6c3a4 YZ |
1363 | { |
1364 | struct qi_desc desc; | |
1365 | ||
1366 | if (mask) { | |
c8acb28b | 1367 | addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; |
5d308fc1 | 1368 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; |
6ba6c3a4 | 1369 | } else |
5d308fc1 | 1370 | desc.qw1 = QI_DEV_IOTLB_ADDR(addr); |
6ba6c3a4 YZ |
1371 | |
1372 | if (qdep >= QI_DEV_IOTLB_MAX_INVS) | |
1373 | qdep = 0; | |
1374 | ||
5d308fc1 | 1375 | desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) | |
1c48db44 | 1376 | QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); |
5d308fc1 LB |
1377 | desc.qw2 = 0; |
1378 | desc.qw3 = 0; | |
6ba6c3a4 YZ |
1379 | |
1380 | qi_submit_sync(&desc, iommu); | |
1381 | } | |
1382 | ||
33cd6e64 LB |
1383 | /* PASID-based IOTLB invalidation */ |
1384 | void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, | |
1385 | unsigned long npages, bool ih) | |
1386 | { | |
1387 | struct qi_desc desc = {.qw2 = 0, .qw3 = 0}; | |
1388 | ||
1389 | /* | |
1390 | * npages == -1 means a PASID-selective invalidation, otherwise, | |
1391 | * a positive value for Page-selective-within-PASID invalidation. | |
1392 | * 0 is not a valid input. | |
1393 | */ | |
1394 | if (WARN_ON(!npages)) { | |
1395 | pr_err("Invalid input npages = %ld\n", npages); | |
1396 | return; | |
1397 | } | |
1398 | ||
1399 | if (npages == -1) { | |
1400 | desc.qw0 = QI_EIOTLB_PASID(pasid) | | |
1401 | QI_EIOTLB_DID(did) | | |
1402 | QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | | |
1403 | QI_EIOTLB_TYPE; | |
1404 | desc.qw1 = 0; | |
1405 | } else { | |
1406 | int mask = ilog2(__roundup_pow_of_two(npages)); | |
1407 | unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask)); | |
1408 | ||
1409 | if (WARN_ON_ONCE(!ALIGN(addr, align))) | |
1410 | addr &= ~(align - 1); | |
1411 | ||
1412 | desc.qw0 = QI_EIOTLB_PASID(pasid) | | |
1413 | QI_EIOTLB_DID(did) | | |
1414 | QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | | |
1415 | QI_EIOTLB_TYPE; | |
1416 | desc.qw1 = QI_EIOTLB_ADDR(addr) | | |
1417 | QI_EIOTLB_IH(ih) | | |
1418 | QI_EIOTLB_AM(mask); | |
1419 | } | |
1420 | ||
1421 | qi_submit_sync(&desc, iommu); | |
1422 | } | |
1423 | ||
eba67e5d SS |
1424 | /* |
1425 | * Disable Queued Invalidation interface. | |
1426 | */ | |
1427 | void dmar_disable_qi(struct intel_iommu *iommu) | |
1428 | { | |
1429 | unsigned long flags; | |
1430 | u32 sts; | |
1431 | cycles_t start_time = get_cycles(); | |
1432 | ||
1433 | if (!ecap_qis(iommu->ecap)) | |
1434 | return; | |
1435 | ||
1f5b3c3f | 1436 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d | 1437 | |
fda3bec1 | 1438 | sts = readl(iommu->reg + DMAR_GSTS_REG); |
eba67e5d SS |
1439 | if (!(sts & DMA_GSTS_QIES)) |
1440 | goto end; | |
1441 | ||
1442 | /* | |
1443 | * Give a chance to HW to complete the pending invalidation requests. | |
1444 | */ | |
1445 | while ((readl(iommu->reg + DMAR_IQT_REG) != | |
1446 | readl(iommu->reg + DMAR_IQH_REG)) && | |
1447 | (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) | |
1448 | cpu_relax(); | |
1449 | ||
1450 | iommu->gcmd &= ~DMA_GCMD_QIE; | |
eba67e5d SS |
1451 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
1452 | ||
1453 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, | |
1454 | !(sts & DMA_GSTS_QIES), sts); | |
1455 | end: | |
1f5b3c3f | 1456 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
1457 | } |
1458 | ||
eb4a52bc FY |
1459 | /* |
1460 | * Enable queued invalidation. | |
1461 | */ | |
1462 | static void __dmar_enable_qi(struct intel_iommu *iommu) | |
1463 | { | |
c416daa9 | 1464 | u32 sts; |
eb4a52bc FY |
1465 | unsigned long flags; |
1466 | struct q_inval *qi = iommu->qi; | |
5d308fc1 | 1467 | u64 val = virt_to_phys(qi->desc); |
eb4a52bc FY |
1468 | |
1469 | qi->free_head = qi->free_tail = 0; | |
1470 | qi->free_cnt = QI_LENGTH; | |
1471 | ||
5d308fc1 LB |
1472 | /* |
1473 | * Set DW=1 and QS=1 in IQA_REG when Scalable Mode capability | |
1474 | * is present. | |
1475 | */ | |
1476 | if (ecap_smts(iommu->ecap)) | |
1477 | val |= (1 << 11) | 1; | |
1478 | ||
1f5b3c3f | 1479 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eb4a52bc FY |
1480 | |
1481 | /* write zero to the tail reg */ | |
1482 | writel(0, iommu->reg + DMAR_IQT_REG); | |
1483 | ||
5d308fc1 | 1484 | dmar_writeq(iommu->reg + DMAR_IQA_REG, val); |
eb4a52bc | 1485 | |
eb4a52bc | 1486 | iommu->gcmd |= DMA_GCMD_QIE; |
c416daa9 | 1487 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
eb4a52bc FY |
1488 | |
1489 | /* Make sure hardware complete it */ | |
1490 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts); | |
1491 | ||
1f5b3c3f | 1492 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eb4a52bc FY |
1493 | } |
1494 | ||
fe962e90 SS |
1495 | /* |
1496 | * Enable Queued Invalidation interface. This is a must to support | |
1497 | * interrupt-remapping. Also used by DMA-remapping, which replaces | |
1498 | * register based IOTLB invalidation. | |
1499 | */ | |
1500 | int dmar_enable_qi(struct intel_iommu *iommu) | |
1501 | { | |
fe962e90 | 1502 | struct q_inval *qi; |
751cafe3 | 1503 | struct page *desc_page; |
fe962e90 SS |
1504 | |
1505 | if (!ecap_qis(iommu->ecap)) | |
1506 | return -ENOENT; | |
1507 | ||
1508 | /* | |
1509 | * queued invalidation is already setup and enabled. | |
1510 | */ | |
1511 | if (iommu->qi) | |
1512 | return 0; | |
1513 | ||
fa4b57cc | 1514 | iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); |
fe962e90 SS |
1515 | if (!iommu->qi) |
1516 | return -ENOMEM; | |
1517 | ||
1518 | qi = iommu->qi; | |
1519 | ||
5d308fc1 LB |
1520 | /* |
1521 | * Need two pages to accommodate 256 descriptors of 256 bits each | |
1522 | * if the remapping hardware supports scalable mode translation. | |
1523 | */ | |
1524 | desc_page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, | |
1525 | !!ecap_smts(iommu->ecap)); | |
751cafe3 | 1526 | if (!desc_page) { |
fe962e90 | 1527 | kfree(qi); |
b707cb02 | 1528 | iommu->qi = NULL; |
fe962e90 SS |
1529 | return -ENOMEM; |
1530 | } | |
1531 | ||
751cafe3 SS |
1532 | qi->desc = page_address(desc_page); |
1533 | ||
6396bb22 | 1534 | qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); |
fe962e90 SS |
1535 | if (!qi->desc_status) { |
1536 | free_page((unsigned long) qi->desc); | |
1537 | kfree(qi); | |
b707cb02 | 1538 | iommu->qi = NULL; |
fe962e90 SS |
1539 | return -ENOMEM; |
1540 | } | |
1541 | ||
3b8f4048 | 1542 | raw_spin_lock_init(&qi->q_lock); |
fe962e90 | 1543 | |
eb4a52bc | 1544 | __dmar_enable_qi(iommu); |
fe962e90 SS |
1545 | |
1546 | return 0; | |
1547 | } | |
0ac2491f SS |
1548 | |
1549 | /* iommu interrupt handling. Most stuff are MSI-like. */ | |
1550 | ||
9d783ba0 SS |
1551 | enum faulttype { |
1552 | DMA_REMAP, | |
1553 | INTR_REMAP, | |
1554 | UNKNOWN, | |
1555 | }; | |
1556 | ||
1557 | static const char *dma_remap_fault_reasons[] = | |
0ac2491f SS |
1558 | { |
1559 | "Software", | |
1560 | "Present bit in root entry is clear", | |
1561 | "Present bit in context entry is clear", | |
1562 | "Invalid context entry", | |
1563 | "Access beyond MGAW", | |
1564 | "PTE Write access is not set", | |
1565 | "PTE Read access is not set", | |
1566 | "Next page table ptr is invalid", | |
1567 | "Root table address invalid", | |
1568 | "Context table ptr is invalid", | |
1569 | "non-zero reserved fields in RTP", | |
1570 | "non-zero reserved fields in CTP", | |
1571 | "non-zero reserved fields in PTE", | |
4ecccd9e | 1572 | "PCE for translation request specifies blocking", |
0ac2491f | 1573 | }; |
9d783ba0 | 1574 | |
fd730007 KMP |
1575 | static const char * const dma_remap_sm_fault_reasons[] = { |
1576 | "SM: Invalid Root Table Address", | |
1577 | "SM: TTM 0 for request with PASID", | |
1578 | "SM: TTM 0 for page group request", | |
1579 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */ | |
1580 | "SM: Error attempting to access Root Entry", | |
1581 | "SM: Present bit in Root Entry is clear", | |
1582 | "SM: Non-zero reserved field set in Root Entry", | |
1583 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */ | |
1584 | "SM: Error attempting to access Context Entry", | |
1585 | "SM: Present bit in Context Entry is clear", | |
1586 | "SM: Non-zero reserved field set in the Context Entry", | |
1587 | "SM: Invalid Context Entry", | |
1588 | "SM: DTE field in Context Entry is clear", | |
1589 | "SM: PASID Enable field in Context Entry is clear", | |
1590 | "SM: PASID is larger than the max in Context Entry", | |
1591 | "SM: PRE field in Context-Entry is clear", | |
1592 | "SM: RID_PASID field error in Context-Entry", | |
1593 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */ | |
1594 | "SM: Error attempting to access the PASID Directory Entry", | |
1595 | "SM: Present bit in Directory Entry is clear", | |
1596 | "SM: Non-zero reserved field set in PASID Directory Entry", | |
1597 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */ | |
1598 | "SM: Error attempting to access PASID Table Entry", | |
1599 | "SM: Present bit in PASID Table Entry is clear", | |
1600 | "SM: Non-zero reserved field set in PASID Table Entry", | |
1601 | "SM: Invalid Scalable-Mode PASID Table Entry", | |
1602 | "SM: ERE field is clear in PASID Table Entry", | |
1603 | "SM: SRE field is clear in PASID Table Entry", | |
1604 | "Unknown", "Unknown",/* 0x5E-0x5F */ | |
1605 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x67 */ | |
1606 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x6F */ | |
1607 | "SM: Error attempting to access first-level paging entry", | |
1608 | "SM: Present bit in first-level paging entry is clear", | |
1609 | "SM: Non-zero reserved field set in first-level paging entry", | |
1610 | "SM: Error attempting to access FL-PML4 entry", | |
1611 | "SM: First-level entry address beyond MGAW in Nested translation", | |
1612 | "SM: Read permission error in FL-PML4 entry in Nested translation", | |
1613 | "SM: Read permission error in first-level paging entry in Nested translation", | |
1614 | "SM: Write permission error in first-level paging entry in Nested translation", | |
1615 | "SM: Error attempting to access second-level paging entry", | |
1616 | "SM: Read/Write permission error in second-level paging entry", | |
1617 | "SM: Non-zero reserved field set in second-level paging entry", | |
1618 | "SM: Invalid second-level page table pointer", | |
1619 | "SM: A/D bit update needed in second-level entry when set up in no snoop", | |
1620 | "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */ | |
1621 | "SM: Address in first-level translation is not canonical", | |
1622 | "SM: U/S set 0 for first-level translation with user privilege", | |
1623 | "SM: No execute permission for request with PASID and ER=1", | |
1624 | "SM: Address beyond the DMA hardware max", | |
1625 | "SM: Second-level entry address beyond the max", | |
1626 | "SM: No write permission for Write/AtomicOp request", | |
1627 | "SM: No read permission for Read/AtomicOp request", | |
1628 | "SM: Invalid address-interrupt address", | |
1629 | "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x8F */ | |
1630 | "SM: A/D bit update needed in first-level entry when set up in no snoop", | |
1631 | }; | |
1632 | ||
95a02e97 | 1633 | static const char *irq_remap_fault_reasons[] = |
9d783ba0 SS |
1634 | { |
1635 | "Detected reserved fields in the decoded interrupt-remapped request", | |
1636 | "Interrupt index exceeded the interrupt-remapping table size", | |
1637 | "Present field in the IRTE entry is clear", | |
1638 | "Error accessing interrupt-remapping table pointed by IRTA_REG", | |
1639 | "Detected reserved fields in the IRTE entry", | |
1640 | "Blocked a compatibility format interrupt request", | |
1641 | "Blocked an interrupt request due to source-id verification failure", | |
1642 | }; | |
1643 | ||
21004dcd | 1644 | static const char *dmar_get_fault_reason(u8 fault_reason, int *fault_type) |
0ac2491f | 1645 | { |
fefe1ed1 DC |
1646 | if (fault_reason >= 0x20 && (fault_reason - 0x20 < |
1647 | ARRAY_SIZE(irq_remap_fault_reasons))) { | |
9d783ba0 | 1648 | *fault_type = INTR_REMAP; |
95a02e97 | 1649 | return irq_remap_fault_reasons[fault_reason - 0x20]; |
fd730007 KMP |
1650 | } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < |
1651 | ARRAY_SIZE(dma_remap_sm_fault_reasons))) { | |
1652 | *fault_type = DMA_REMAP; | |
1653 | return dma_remap_sm_fault_reasons[fault_reason - 0x30]; | |
9d783ba0 SS |
1654 | } else if (fault_reason < ARRAY_SIZE(dma_remap_fault_reasons)) { |
1655 | *fault_type = DMA_REMAP; | |
1656 | return dma_remap_fault_reasons[fault_reason]; | |
1657 | } else { | |
1658 | *fault_type = UNKNOWN; | |
0ac2491f | 1659 | return "Unknown"; |
9d783ba0 | 1660 | } |
0ac2491f SS |
1661 | } |
1662 | ||
1208225c DW |
1663 | |
1664 | static inline int dmar_msi_reg(struct intel_iommu *iommu, int irq) | |
1665 | { | |
1666 | if (iommu->irq == irq) | |
1667 | return DMAR_FECTL_REG; | |
1668 | else if (iommu->pr_irq == irq) | |
1669 | return DMAR_PECTL_REG; | |
1670 | else | |
1671 | BUG(); | |
1672 | } | |
1673 | ||
5c2837fb | 1674 | void dmar_msi_unmask(struct irq_data *data) |
0ac2491f | 1675 | { |
dced35ae | 1676 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c | 1677 | int reg = dmar_msi_reg(iommu, data->irq); |
0ac2491f SS |
1678 | unsigned long flag; |
1679 | ||
1680 | /* unmask it */ | |
1f5b3c3f | 1681 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1682 | writel(0, iommu->reg + reg); |
0ac2491f | 1683 | /* Read a reg to force flush the post write */ |
1208225c | 1684 | readl(iommu->reg + reg); |
1f5b3c3f | 1685 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1686 | } |
1687 | ||
5c2837fb | 1688 | void dmar_msi_mask(struct irq_data *data) |
0ac2491f | 1689 | { |
dced35ae | 1690 | struct intel_iommu *iommu = irq_data_get_irq_handler_data(data); |
1208225c DW |
1691 | int reg = dmar_msi_reg(iommu, data->irq); |
1692 | unsigned long flag; | |
0ac2491f SS |
1693 | |
1694 | /* mask it */ | |
1f5b3c3f | 1695 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c | 1696 | writel(DMA_FECTL_IM, iommu->reg + reg); |
0ac2491f | 1697 | /* Read a reg to force flush the post write */ |
1208225c | 1698 | readl(iommu->reg + reg); |
1f5b3c3f | 1699 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1700 | } |
1701 | ||
1702 | void dmar_msi_write(int irq, struct msi_msg *msg) | |
1703 | { | |
dced35ae | 1704 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1705 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1706 | unsigned long flag; |
1707 | ||
1f5b3c3f | 1708 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1709 | writel(msg->data, iommu->reg + reg + 4); |
1710 | writel(msg->address_lo, iommu->reg + reg + 8); | |
1711 | writel(msg->address_hi, iommu->reg + reg + 12); | |
1f5b3c3f | 1712 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1713 | } |
1714 | ||
1715 | void dmar_msi_read(int irq, struct msi_msg *msg) | |
1716 | { | |
dced35ae | 1717 | struct intel_iommu *iommu = irq_get_handler_data(irq); |
1208225c | 1718 | int reg = dmar_msi_reg(iommu, irq); |
0ac2491f SS |
1719 | unsigned long flag; |
1720 | ||
1f5b3c3f | 1721 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
1208225c DW |
1722 | msg->data = readl(iommu->reg + reg + 4); |
1723 | msg->address_lo = readl(iommu->reg + reg + 8); | |
1724 | msg->address_hi = readl(iommu->reg + reg + 12); | |
1f5b3c3f | 1725 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1726 | } |
1727 | ||
1728 | static int dmar_fault_do_one(struct intel_iommu *iommu, int type, | |
fd730007 KMP |
1729 | u8 fault_reason, int pasid, u16 source_id, |
1730 | unsigned long long addr) | |
0ac2491f SS |
1731 | { |
1732 | const char *reason; | |
9d783ba0 | 1733 | int fault_type; |
0ac2491f | 1734 | |
9d783ba0 | 1735 | reason = dmar_get_fault_reason(fault_reason, &fault_type); |
0ac2491f | 1736 | |
9d783ba0 | 1737 | if (fault_type == INTR_REMAP) |
a0fe14d7 AW |
1738 | pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index %llx [fault reason %02d] %s\n", |
1739 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
9d783ba0 SS |
1740 | PCI_FUNC(source_id & 0xFF), addr >> 48, |
1741 | fault_reason, reason); | |
1742 | else | |
fd730007 | 1743 | pr_err("[%s] Request device [%02x:%02x.%d] PASID %x fault addr %llx [fault reason %02d] %s\n", |
a0fe14d7 AW |
1744 | type ? "DMA Read" : "DMA Write", |
1745 | source_id >> 8, PCI_SLOT(source_id & 0xFF), | |
fd730007 KMP |
1746 | PCI_FUNC(source_id & 0xFF), pasid, addr, |
1747 | fault_reason, reason); | |
0ac2491f SS |
1748 | return 0; |
1749 | } | |
1750 | ||
1751 | #define PRIMARY_FAULT_REG_LEN (16) | |
1531a6a6 | 1752 | irqreturn_t dmar_fault(int irq, void *dev_id) |
0ac2491f SS |
1753 | { |
1754 | struct intel_iommu *iommu = dev_id; | |
1755 | int reg, fault_index; | |
1756 | u32 fault_status; | |
1757 | unsigned long flag; | |
c43fce4e AW |
1758 | static DEFINE_RATELIMIT_STATE(rs, |
1759 | DEFAULT_RATELIMIT_INTERVAL, | |
1760 | DEFAULT_RATELIMIT_BURST); | |
1761 | ||
1f5b3c3f | 1762 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1763 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
6c50d79f | 1764 | if (fault_status && __ratelimit(&rs)) |
bf947fcb | 1765 | pr_err("DRHD: handling fault status reg %x\n", fault_status); |
0ac2491f SS |
1766 | |
1767 | /* TBD: ignore advanced fault log currently */ | |
1768 | if (!(fault_status & DMA_FSTS_PPF)) | |
bd5cdad0 | 1769 | goto unlock_exit; |
0ac2491f SS |
1770 | |
1771 | fault_index = dma_fsts_fault_record_index(fault_status); | |
1772 | reg = cap_fault_reg_offset(iommu->cap); | |
1773 | while (1) { | |
6c50d79f DS |
1774 | /* Disable printing, simply clear the fault when ratelimited */ |
1775 | bool ratelimited = !__ratelimit(&rs); | |
0ac2491f SS |
1776 | u8 fault_reason; |
1777 | u16 source_id; | |
1778 | u64 guest_addr; | |
fd730007 | 1779 | int type, pasid; |
0ac2491f | 1780 | u32 data; |
fd730007 | 1781 | bool pasid_present; |
0ac2491f SS |
1782 | |
1783 | /* highest 32 bits */ | |
1784 | data = readl(iommu->reg + reg + | |
1785 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1786 | if (!(data & DMA_FRCD_F)) | |
1787 | break; | |
1788 | ||
c43fce4e AW |
1789 | if (!ratelimited) { |
1790 | fault_reason = dma_frcd_fault_reason(data); | |
1791 | type = dma_frcd_type(data); | |
0ac2491f | 1792 | |
fd730007 | 1793 | pasid = dma_frcd_pasid_value(data); |
c43fce4e AW |
1794 | data = readl(iommu->reg + reg + |
1795 | fault_index * PRIMARY_FAULT_REG_LEN + 8); | |
1796 | source_id = dma_frcd_source_id(data); | |
1797 | ||
fd730007 | 1798 | pasid_present = dma_frcd_pasid_present(data); |
c43fce4e AW |
1799 | guest_addr = dmar_readq(iommu->reg + reg + |
1800 | fault_index * PRIMARY_FAULT_REG_LEN); | |
1801 | guest_addr = dma_frcd_page_addr(guest_addr); | |
1802 | } | |
0ac2491f | 1803 | |
0ac2491f SS |
1804 | /* clear the fault */ |
1805 | writel(DMA_FRCD_F, iommu->reg + reg + | |
1806 | fault_index * PRIMARY_FAULT_REG_LEN + 12); | |
1807 | ||
1f5b3c3f | 1808 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f | 1809 | |
c43fce4e | 1810 | if (!ratelimited) |
fd730007 | 1811 | /* Using pasid -1 if pasid is not present */ |
c43fce4e | 1812 | dmar_fault_do_one(iommu, type, fault_reason, |
fd730007 | 1813 | pasid_present ? pasid : -1, |
c43fce4e | 1814 | source_id, guest_addr); |
0ac2491f SS |
1815 | |
1816 | fault_index++; | |
8211a7b5 | 1817 | if (fault_index >= cap_num_fault_regs(iommu->cap)) |
0ac2491f | 1818 | fault_index = 0; |
1f5b3c3f | 1819 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
0ac2491f | 1820 | } |
0ac2491f | 1821 | |
973b5464 LB |
1822 | writel(DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_PRO, |
1823 | iommu->reg + DMAR_FSTS_REG); | |
bd5cdad0 LZH |
1824 | |
1825 | unlock_exit: | |
1f5b3c3f | 1826 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
0ac2491f SS |
1827 | return IRQ_HANDLED; |
1828 | } | |
1829 | ||
1830 | int dmar_set_interrupt(struct intel_iommu *iommu) | |
1831 | { | |
1832 | int irq, ret; | |
1833 | ||
9d783ba0 SS |
1834 | /* |
1835 | * Check if the fault interrupt is already initialized. | |
1836 | */ | |
1837 | if (iommu->irq) | |
1838 | return 0; | |
1839 | ||
34742db8 JL |
1840 | irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); |
1841 | if (irq > 0) { | |
1842 | iommu->irq = irq; | |
1843 | } else { | |
9f10e5bf | 1844 | pr_err("No free IRQ vectors\n"); |
0ac2491f SS |
1845 | return -EINVAL; |
1846 | } | |
1847 | ||
477694e7 | 1848 | ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); |
0ac2491f | 1849 | if (ret) |
9f10e5bf | 1850 | pr_err("Can't request irq\n"); |
0ac2491f SS |
1851 | return ret; |
1852 | } | |
9d783ba0 SS |
1853 | |
1854 | int __init enable_drhd_fault_handling(void) | |
1855 | { | |
1856 | struct dmar_drhd_unit *drhd; | |
7c919779 | 1857 | struct intel_iommu *iommu; |
9d783ba0 SS |
1858 | |
1859 | /* | |
1860 | * Enable fault control interrupt. | |
1861 | */ | |
7c919779 | 1862 | for_each_iommu(iommu, drhd) { |
bd5cdad0 | 1863 | u32 fault_status; |
7c919779 | 1864 | int ret = dmar_set_interrupt(iommu); |
9d783ba0 SS |
1865 | |
1866 | if (ret) { | |
e9071b0b | 1867 | pr_err("DRHD %Lx: failed to enable fault, interrupt, ret %d\n", |
9d783ba0 SS |
1868 | (unsigned long long)drhd->reg_base_addr, ret); |
1869 | return -1; | |
1870 | } | |
7f99d946 SS |
1871 | |
1872 | /* | |
1873 | * Clear any previous faults. | |
1874 | */ | |
1875 | dmar_fault(iommu->irq, iommu); | |
bd5cdad0 LZH |
1876 | fault_status = readl(iommu->reg + DMAR_FSTS_REG); |
1877 | writel(fault_status, iommu->reg + DMAR_FSTS_REG); | |
9d783ba0 SS |
1878 | } |
1879 | ||
1880 | return 0; | |
1881 | } | |
eb4a52bc FY |
1882 | |
1883 | /* | |
1884 | * Re-enable Queued Invalidation interface. | |
1885 | */ | |
1886 | int dmar_reenable_qi(struct intel_iommu *iommu) | |
1887 | { | |
1888 | if (!ecap_qis(iommu->ecap)) | |
1889 | return -ENOENT; | |
1890 | ||
1891 | if (!iommu->qi) | |
1892 | return -ENOENT; | |
1893 | ||
1894 | /* | |
1895 | * First disable queued invalidation. | |
1896 | */ | |
1897 | dmar_disable_qi(iommu); | |
1898 | /* | |
1899 | * Then enable queued invalidation again. Since there is no pending | |
1900 | * invalidation requests now, it's safe to re-enable queued | |
1901 | * invalidation. | |
1902 | */ | |
1903 | __dmar_enable_qi(iommu); | |
1904 | ||
1905 | return 0; | |
1906 | } | |
074835f0 YS |
1907 | |
1908 | /* | |
1909 | * Check interrupt remapping support in DMAR table description. | |
1910 | */ | |
0b8973a8 | 1911 | int __init dmar_ir_support(void) |
074835f0 YS |
1912 | { |
1913 | struct acpi_table_dmar *dmar; | |
1914 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
4f506e07 AP |
1915 | if (!dmar) |
1916 | return 0; | |
074835f0 YS |
1917 | return dmar->flags & 0x1; |
1918 | } | |
694835dc | 1919 | |
6b197249 JL |
1920 | /* Check whether DMAR units are in use */ |
1921 | static inline bool dmar_in_use(void) | |
1922 | { | |
1923 | return irq_remapping_enabled || intel_iommu_enabled; | |
1924 | } | |
1925 | ||
a868e6b7 JL |
1926 | static int __init dmar_free_unused_resources(void) |
1927 | { | |
1928 | struct dmar_drhd_unit *dmaru, *dmaru_n; | |
1929 | ||
6b197249 | 1930 | if (dmar_in_use()) |
a868e6b7 JL |
1931 | return 0; |
1932 | ||
2e455289 JL |
1933 | if (dmar_dev_scope_status != 1 && !list_empty(&dmar_drhd_units)) |
1934 | bus_unregister_notifier(&pci_bus_type, &dmar_pci_bus_nb); | |
59ce0515 | 1935 | |
3a5670e8 | 1936 | down_write(&dmar_global_lock); |
a868e6b7 JL |
1937 | list_for_each_entry_safe(dmaru, dmaru_n, &dmar_drhd_units, list) { |
1938 | list_del(&dmaru->list); | |
1939 | dmar_free_drhd(dmaru); | |
1940 | } | |
3a5670e8 | 1941 | up_write(&dmar_global_lock); |
a868e6b7 JL |
1942 | |
1943 | return 0; | |
1944 | } | |
1945 | ||
1946 | late_initcall(dmar_free_unused_resources); | |
4db77ff3 | 1947 | IOMMU_INIT_POST(detect_intel_iommu); |
6b197249 JL |
1948 | |
1949 | /* | |
1950 | * DMAR Hotplug Support | |
1951 | * For more details, please refer to Intel(R) Virtualization Technology | |
1952 | * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8 | |
1953 | * "Remapping Hardware Unit Hot Plug". | |
1954 | */ | |
94116f81 AS |
1955 | static guid_t dmar_hp_guid = |
1956 | GUID_INIT(0xD8C1A3A6, 0xBE9B, 0x4C9B, | |
1957 | 0x91, 0xBF, 0xC3, 0xCB, 0x81, 0xFC, 0x5D, 0xAF); | |
6b197249 JL |
1958 | |
1959 | /* | |
1960 | * Currently there's only one revision and BIOS will not check the revision id, | |
1961 | * so use 0 for safety. | |
1962 | */ | |
1963 | #define DMAR_DSM_REV_ID 0 | |
1964 | #define DMAR_DSM_FUNC_DRHD 1 | |
1965 | #define DMAR_DSM_FUNC_ATSR 2 | |
1966 | #define DMAR_DSM_FUNC_RHSA 3 | |
1967 | ||
1968 | static inline bool dmar_detect_dsm(acpi_handle handle, int func) | |
1969 | { | |
94116f81 | 1970 | return acpi_check_dsm(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, 1 << func); |
6b197249 JL |
1971 | } |
1972 | ||
1973 | static int dmar_walk_dsm_resource(acpi_handle handle, int func, | |
1974 | dmar_res_handler_t handler, void *arg) | |
1975 | { | |
1976 | int ret = -ENODEV; | |
1977 | union acpi_object *obj; | |
1978 | struct acpi_dmar_header *start; | |
1979 | struct dmar_res_callback callback; | |
1980 | static int res_type[] = { | |
1981 | [DMAR_DSM_FUNC_DRHD] = ACPI_DMAR_TYPE_HARDWARE_UNIT, | |
1982 | [DMAR_DSM_FUNC_ATSR] = ACPI_DMAR_TYPE_ROOT_ATS, | |
1983 | [DMAR_DSM_FUNC_RHSA] = ACPI_DMAR_TYPE_HARDWARE_AFFINITY, | |
1984 | }; | |
1985 | ||
1986 | if (!dmar_detect_dsm(handle, func)) | |
1987 | return 0; | |
1988 | ||
94116f81 | 1989 | obj = acpi_evaluate_dsm_typed(handle, &dmar_hp_guid, DMAR_DSM_REV_ID, |
6b197249 JL |
1990 | func, NULL, ACPI_TYPE_BUFFER); |
1991 | if (!obj) | |
1992 | return -ENODEV; | |
1993 | ||
1994 | memset(&callback, 0, sizeof(callback)); | |
1995 | callback.cb[res_type[func]] = handler; | |
1996 | callback.arg[res_type[func]] = arg; | |
1997 | start = (struct acpi_dmar_header *)obj->buffer.pointer; | |
1998 | ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); | |
1999 | ||
2000 | ACPI_FREE(obj); | |
2001 | ||
2002 | return ret; | |
2003 | } | |
2004 | ||
2005 | static int dmar_hp_add_drhd(struct acpi_dmar_header *header, void *arg) | |
2006 | { | |
2007 | int ret; | |
2008 | struct dmar_drhd_unit *dmaru; | |
2009 | ||
2010 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2011 | if (!dmaru) | |
2012 | return -ENODEV; | |
2013 | ||
2014 | ret = dmar_ir_hotplug(dmaru, true); | |
2015 | if (ret == 0) | |
2016 | ret = dmar_iommu_hotplug(dmaru, true); | |
2017 | ||
2018 | return ret; | |
2019 | } | |
2020 | ||
2021 | static int dmar_hp_remove_drhd(struct acpi_dmar_header *header, void *arg) | |
2022 | { | |
2023 | int i, ret; | |
2024 | struct device *dev; | |
2025 | struct dmar_drhd_unit *dmaru; | |
2026 | ||
2027 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2028 | if (!dmaru) | |
2029 | return 0; | |
2030 | ||
2031 | /* | |
2032 | * All PCI devices managed by this unit should have been destroyed. | |
2033 | */ | |
194dc870 | 2034 | if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { |
6b197249 JL |
2035 | for_each_active_dev_scope(dmaru->devices, |
2036 | dmaru->devices_cnt, i, dev) | |
2037 | return -EBUSY; | |
194dc870 | 2038 | } |
6b197249 JL |
2039 | |
2040 | ret = dmar_ir_hotplug(dmaru, false); | |
2041 | if (ret == 0) | |
2042 | ret = dmar_iommu_hotplug(dmaru, false); | |
2043 | ||
2044 | return ret; | |
2045 | } | |
2046 | ||
2047 | static int dmar_hp_release_drhd(struct acpi_dmar_header *header, void *arg) | |
2048 | { | |
2049 | struct dmar_drhd_unit *dmaru; | |
2050 | ||
2051 | dmaru = dmar_find_dmaru((struct acpi_dmar_hardware_unit *)header); | |
2052 | if (dmaru) { | |
2053 | list_del_rcu(&dmaru->list); | |
2054 | synchronize_rcu(); | |
2055 | dmar_free_drhd(dmaru); | |
2056 | } | |
2057 | ||
2058 | return 0; | |
2059 | } | |
2060 | ||
2061 | static int dmar_hotplug_insert(acpi_handle handle) | |
2062 | { | |
2063 | int ret; | |
2064 | int drhd_count = 0; | |
2065 | ||
2066 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2067 | &dmar_validate_one_drhd, (void *)1); | |
2068 | if (ret) | |
2069 | goto out; | |
2070 | ||
2071 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2072 | &dmar_parse_one_drhd, (void *)&drhd_count); | |
2073 | if (ret == 0 && drhd_count == 0) { | |
2074 | pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); | |
2075 | goto out; | |
2076 | } else if (ret) { | |
2077 | goto release_drhd; | |
2078 | } | |
2079 | ||
2080 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_RHSA, | |
2081 | &dmar_parse_one_rhsa, NULL); | |
2082 | if (ret) | |
2083 | goto release_drhd; | |
2084 | ||
2085 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2086 | &dmar_parse_one_atsr, NULL); | |
2087 | if (ret) | |
2088 | goto release_atsr; | |
2089 | ||
2090 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2091 | &dmar_hp_add_drhd, NULL); | |
2092 | if (!ret) | |
2093 | return 0; | |
2094 | ||
2095 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2096 | &dmar_hp_remove_drhd, NULL); | |
2097 | release_atsr: | |
2098 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2099 | &dmar_release_one_atsr, NULL); | |
2100 | release_drhd: | |
2101 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2102 | &dmar_hp_release_drhd, NULL); | |
2103 | out: | |
2104 | return ret; | |
2105 | } | |
2106 | ||
2107 | static int dmar_hotplug_remove(acpi_handle handle) | |
2108 | { | |
2109 | int ret; | |
2110 | ||
2111 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2112 | &dmar_check_one_atsr, NULL); | |
2113 | if (ret) | |
2114 | return ret; | |
2115 | ||
2116 | ret = dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2117 | &dmar_hp_remove_drhd, NULL); | |
2118 | if (ret == 0) { | |
2119 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_ATSR, | |
2120 | &dmar_release_one_atsr, NULL)); | |
2121 | WARN_ON(dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2122 | &dmar_hp_release_drhd, NULL)); | |
2123 | } else { | |
2124 | dmar_walk_dsm_resource(handle, DMAR_DSM_FUNC_DRHD, | |
2125 | &dmar_hp_add_drhd, NULL); | |
2126 | } | |
2127 | ||
2128 | return ret; | |
2129 | } | |
2130 | ||
d35165a9 JL |
2131 | static acpi_status dmar_get_dsm_handle(acpi_handle handle, u32 lvl, |
2132 | void *context, void **retval) | |
2133 | { | |
2134 | acpi_handle *phdl = retval; | |
2135 | ||
2136 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { | |
2137 | *phdl = handle; | |
2138 | return AE_CTRL_TERMINATE; | |
2139 | } | |
2140 | ||
2141 | return AE_OK; | |
2142 | } | |
2143 | ||
6b197249 JL |
2144 | static int dmar_device_hotplug(acpi_handle handle, bool insert) |
2145 | { | |
2146 | int ret; | |
d35165a9 JL |
2147 | acpi_handle tmp = NULL; |
2148 | acpi_status status; | |
6b197249 JL |
2149 | |
2150 | if (!dmar_in_use()) | |
2151 | return 0; | |
2152 | ||
d35165a9 JL |
2153 | if (dmar_detect_dsm(handle, DMAR_DSM_FUNC_DRHD)) { |
2154 | tmp = handle; | |
2155 | } else { | |
2156 | status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, | |
2157 | ACPI_UINT32_MAX, | |
2158 | dmar_get_dsm_handle, | |
2159 | NULL, NULL, &tmp); | |
2160 | if (ACPI_FAILURE(status)) { | |
2161 | pr_warn("Failed to locate _DSM method.\n"); | |
2162 | return -ENXIO; | |
2163 | } | |
2164 | } | |
2165 | if (tmp == NULL) | |
6b197249 JL |
2166 | return 0; |
2167 | ||
2168 | down_write(&dmar_global_lock); | |
2169 | if (insert) | |
d35165a9 | 2170 | ret = dmar_hotplug_insert(tmp); |
6b197249 | 2171 | else |
d35165a9 | 2172 | ret = dmar_hotplug_remove(tmp); |
6b197249 JL |
2173 | up_write(&dmar_global_lock); |
2174 | ||
2175 | return ret; | |
2176 | } | |
2177 | ||
2178 | int dmar_device_add(acpi_handle handle) | |
2179 | { | |
2180 | return dmar_device_hotplug(handle, true); | |
2181 | } | |
2182 | ||
2183 | int dmar_device_remove(acpi_handle handle) | |
2184 | { | |
2185 | return dmar_device_hotplug(handle, false); | |
2186 | } | |
89a6079d LB |
2187 | |
2188 | /* | |
2189 | * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table | |
2190 | * | |
2191 | * Returns true if the platform has %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in | |
2192 | * the ACPI DMAR table. This means that the platform boot firmware has made | |
2193 | * sure no device can issue DMA outside of RMRR regions. | |
2194 | */ | |
2195 | bool dmar_platform_optin(void) | |
2196 | { | |
2197 | struct acpi_table_dmar *dmar; | |
2198 | acpi_status status; | |
2199 | bool ret; | |
2200 | ||
2201 | status = acpi_get_table(ACPI_SIG_DMAR, 0, | |
2202 | (struct acpi_table_header **)&dmar); | |
2203 | if (ACPI_FAILURE(status)) | |
2204 | return false; | |
2205 | ||
2206 | ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); | |
2207 | acpi_put_table((struct acpi_table_header *)dmar); | |
2208 | ||
2209 | return ret; | |
2210 | } | |
2211 | EXPORT_SYMBOL_GPL(dmar_platform_optin); |