]>
Commit | Line | Data |
---|---|---|
740a01ee MS |
1 | /* |
2 | * Copyright (c) 2011,2016 Samsung Electronics Co., Ltd. | |
2a96536e KC |
3 | * http://www.samsung.com |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | ||
10 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
11 | #define DEBUG | |
12 | #endif | |
13 | ||
2a96536e | 14 | #include <linux/clk.h> |
8ed55c81 | 15 | #include <linux/dma-mapping.h> |
2a96536e | 16 | #include <linux/err.h> |
312900c6 | 17 | #include <linux/io.h> |
2a96536e | 18 | #include <linux/iommu.h> |
312900c6 | 19 | #include <linux/interrupt.h> |
2a96536e | 20 | #include <linux/list.h> |
8ed55c81 MS |
21 | #include <linux/of.h> |
22 | #include <linux/of_iommu.h> | |
23 | #include <linux/of_platform.h> | |
312900c6 MS |
24 | #include <linux/platform_device.h> |
25 | #include <linux/pm_runtime.h> | |
26 | #include <linux/slab.h> | |
58c6f6a3 | 27 | #include <linux/dma-iommu.h> |
2a96536e | 28 | |
d09d78fc CK |
29 | typedef u32 sysmmu_iova_t; |
30 | typedef u32 sysmmu_pte_t; | |
31 | ||
f171abab | 32 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
33 | #define SECT_ORDER 20 |
34 | #define LPAGE_ORDER 16 | |
35 | #define SPAGE_ORDER 12 | |
36 | ||
37 | #define SECT_SIZE (1 << SECT_ORDER) | |
38 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
39 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
40 | ||
41 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
42 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
43 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
44 | ||
66a7ed84 CK |
45 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
46 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
47 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
48 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
49 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
50 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
51 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
52 | ||
53 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
54 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
55 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
56 | ||
740a01ee MS |
57 | /* |
58 | * v1.x - v3.x SYSMMU supports 32bit physical and 32bit virtual address spaces | |
59 | * v5.0 introduced support for 36bit physical address space by shifting | |
60 | * all page entry values by 4 bits. | |
61 | * All SYSMMU controllers in the system support the address spaces of the same | |
62 | * size, so PG_ENT_SHIFT can be initialized on first SYSMMU probe to proper | |
63 | * value (0 or 4). | |
64 | */ | |
65 | static short PG_ENT_SHIFT = -1; | |
66 | #define SYSMMU_PG_ENT_SHIFT 0 | |
67 | #define SYSMMU_V5_PG_ENT_SHIFT 4 | |
68 | ||
1a0d8dac MS |
69 | static const sysmmu_pte_t *LV1_PROT; |
70 | static const sysmmu_pte_t SYSMMU_LV1_PROT[] = { | |
71 | ((0 << 15) | (0 << 10)), /* no access */ | |
72 | ((1 << 15) | (1 << 10)), /* IOMMU_READ only */ | |
73 | ((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */ | |
74 | ((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */ | |
75 | }; | |
76 | static const sysmmu_pte_t SYSMMU_V5_LV1_PROT[] = { | |
77 | (0 << 4), /* no access */ | |
78 | (1 << 4), /* IOMMU_READ only */ | |
79 | (2 << 4), /* IOMMU_WRITE only */ | |
80 | (3 << 4), /* IOMMU_READ | IOMMU_WRITE */ | |
81 | }; | |
82 | ||
83 | static const sysmmu_pte_t *LV2_PROT; | |
84 | static const sysmmu_pte_t SYSMMU_LV2_PROT[] = { | |
85 | ((0 << 9) | (0 << 4)), /* no access */ | |
86 | ((1 << 9) | (1 << 4)), /* IOMMU_READ only */ | |
87 | ((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */ | |
88 | ((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */ | |
89 | }; | |
90 | static const sysmmu_pte_t SYSMMU_V5_LV2_PROT[] = { | |
91 | (0 << 2), /* no access */ | |
92 | (1 << 2), /* IOMMU_READ only */ | |
93 | (2 << 2), /* IOMMU_WRITE only */ | |
94 | (3 << 2), /* IOMMU_READ | IOMMU_WRITE */ | |
95 | }; | |
96 | ||
97 | #define SYSMMU_SUPPORTED_PROT_BITS (IOMMU_READ | IOMMU_WRITE) | |
98 | ||
740a01ee MS |
99 | #define sect_to_phys(ent) (((phys_addr_t) ent) << PG_ENT_SHIFT) |
100 | #define section_phys(sent) (sect_to_phys(*(sent)) & SECT_MASK) | |
101 | #define section_offs(iova) (iova & (SECT_SIZE - 1)) | |
102 | #define lpage_phys(pent) (sect_to_phys(*(pent)) & LPAGE_MASK) | |
103 | #define lpage_offs(iova) (iova & (LPAGE_SIZE - 1)) | |
104 | #define spage_phys(pent) (sect_to_phys(*(pent)) & SPAGE_MASK) | |
105 | #define spage_offs(iova) (iova & (SPAGE_SIZE - 1)) | |
2a96536e KC |
106 | |
107 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 108 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 109 | |
d09d78fc CK |
110 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
111 | { | |
112 | return iova >> SECT_ORDER; | |
113 | } | |
114 | ||
115 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
116 | { | |
117 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
118 | } | |
119 | ||
5e3435eb | 120 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 121 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
122 | |
123 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
740a01ee | 124 | #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0)) |
2a96536e | 125 | |
1a0d8dac | 126 | #define mk_lv1ent_sect(pa, prot) ((pa >> PG_ENT_SHIFT) | LV1_PROT[prot] | 2) |
740a01ee | 127 | #define mk_lv1ent_page(pa) ((pa >> PG_ENT_SHIFT) | 1) |
1a0d8dac MS |
128 | #define mk_lv2ent_lpage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 1) |
129 | #define mk_lv2ent_spage(pa, prot) ((pa >> PG_ENT_SHIFT) | LV2_PROT[prot] | 2) | |
2a96536e KC |
130 | |
131 | #define CTRL_ENABLE 0x5 | |
132 | #define CTRL_BLOCK 0x7 | |
133 | #define CTRL_DISABLE 0x0 | |
134 | ||
eeb5184b | 135 | #define CFG_LRU 0x1 |
1a0d8dac | 136 | #define CFG_EAP (1 << 2) |
eeb5184b | 137 | #define CFG_QOS(n) ((n & 0xF) << 7) |
eeb5184b CK |
138 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ |
139 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
140 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
141 | ||
740a01ee | 142 | /* common registers */ |
2a96536e KC |
143 | #define REG_MMU_CTRL 0x000 |
144 | #define REG_MMU_CFG 0x004 | |
145 | #define REG_MMU_STATUS 0x008 | |
740a01ee MS |
146 | #define REG_MMU_VERSION 0x034 |
147 | ||
148 | #define MMU_MAJ_VER(val) ((val) >> 7) | |
149 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
150 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
151 | ||
152 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
153 | ||
154 | /* v1.x - v3.x registers */ | |
2a96536e KC |
155 | #define REG_MMU_FLUSH 0x00C |
156 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
157 | #define REG_PT_BASE_ADDR 0x014 | |
158 | #define REG_INT_STATUS 0x018 | |
159 | #define REG_INT_CLEAR 0x01C | |
160 | ||
161 | #define REG_PAGE_FAULT_ADDR 0x024 | |
162 | #define REG_AW_FAULT_ADDR 0x028 | |
163 | #define REG_AR_FAULT_ADDR 0x02C | |
164 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
165 | ||
740a01ee MS |
166 | /* v5.x registers */ |
167 | #define REG_V5_PT_BASE_PFN 0x00C | |
168 | #define REG_V5_MMU_FLUSH_ALL 0x010 | |
169 | #define REG_V5_MMU_FLUSH_ENTRY 0x014 | |
d5bf739d MS |
170 | #define REG_V5_MMU_FLUSH_RANGE 0x018 |
171 | #define REG_V5_MMU_FLUSH_START 0x020 | |
172 | #define REG_V5_MMU_FLUSH_END 0x024 | |
740a01ee MS |
173 | #define REG_V5_INT_STATUS 0x060 |
174 | #define REG_V5_INT_CLEAR 0x064 | |
175 | #define REG_V5_FAULT_AR_VA 0x070 | |
176 | #define REG_V5_FAULT_AW_VA 0x080 | |
2a96536e | 177 | |
6b21a5db CK |
178 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
179 | ||
5e3435eb | 180 | static struct device *dma_dev; |
734c3c73 | 181 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
182 | static sysmmu_pte_t *zero_lv2_table; |
183 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 184 | |
d09d78fc | 185 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
186 | { |
187 | return pgtable + lv1ent_offset(iova); | |
188 | } | |
189 | ||
d09d78fc | 190 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 191 | { |
d09d78fc | 192 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 193 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
194 | } |
195 | ||
d093fc7e MS |
196 | /* |
197 | * IOMMU fault information register | |
198 | */ | |
199 | struct sysmmu_fault_info { | |
200 | unsigned int bit; /* bit number in STATUS register */ | |
201 | unsigned short addr_reg; /* register to read VA fault address */ | |
202 | const char *name; /* human readable fault name */ | |
203 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
204 | }; |
205 | ||
d093fc7e MS |
206 | static const struct sysmmu_fault_info sysmmu_faults[] = { |
207 | { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
208 | { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
209 | { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
210 | { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
211 | { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
212 | { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
213 | { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
214 | { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
215 | }; |
216 | ||
740a01ee MS |
217 | static const struct sysmmu_fault_info sysmmu_v5_faults[] = { |
218 | { 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ }, | |
219 | { 1, REG_V5_FAULT_AR_VA, "AR PAGE", IOMMU_FAULT_READ }, | |
220 | { 2, REG_V5_FAULT_AR_VA, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
221 | { 3, REG_V5_FAULT_AR_VA, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
222 | { 4, REG_V5_FAULT_AR_VA, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
223 | { 16, REG_V5_FAULT_AW_VA, "AW PTW", IOMMU_FAULT_WRITE }, | |
224 | { 17, REG_V5_FAULT_AW_VA, "AW PAGE", IOMMU_FAULT_WRITE }, | |
225 | { 18, REG_V5_FAULT_AW_VA, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
226 | { 19, REG_V5_FAULT_AW_VA, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
227 | { 20, REG_V5_FAULT_AW_VA, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
228 | }; | |
229 | ||
2860af3c MS |
230 | /* |
231 | * This structure is attached to dev.archdata.iommu of the master device | |
232 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
233 | * which are bound to given master device. It is usually referenced by 'owner' | |
234 | * pointer. | |
235 | */ | |
6b21a5db | 236 | struct exynos_iommu_owner { |
1b092054 | 237 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
5fa61cbf | 238 | struct iommu_domain *domain; /* domain this device is attached */ |
9b265536 | 239 | struct mutex rpm_lock; /* for runtime pm of all sysmmus */ |
6b21a5db CK |
240 | }; |
241 | ||
2860af3c MS |
242 | /* |
243 | * This structure exynos specific generalization of struct iommu_domain. | |
244 | * It contains list of SYSMMU controllers from all master devices, which has | |
245 | * been attached to this domain and page tables of IO address space defined by | |
246 | * it. It is usually referenced by 'domain' pointer. | |
247 | */ | |
2a96536e | 248 | struct exynos_iommu_domain { |
2860af3c MS |
249 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
250 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
251 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
252 | spinlock_t lock; /* lock for modyfying list of clients */ | |
253 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 254 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
255 | }; |
256 | ||
2860af3c MS |
257 | /* |
258 | * This structure hold all data of a single SYSMMU controller, this includes | |
259 | * hw resources like registers and clocks, pointers and list nodes to connect | |
260 | * it to all other structures, internal state and parameters read from device | |
261 | * tree. It is usually referenced by 'data' pointer. | |
262 | */ | |
2a96536e | 263 | struct sysmmu_drvdata { |
2860af3c MS |
264 | struct device *sysmmu; /* SYSMMU controller device */ |
265 | struct device *master; /* master device (owner) */ | |
7a974b29 | 266 | struct device_link *link; /* runtime PM link to master */ |
2860af3c MS |
267 | void __iomem *sfrbase; /* our registers */ |
268 | struct clk *clk; /* SYSMMU's clock */ | |
740a01ee MS |
269 | struct clk *aclk; /* SYSMMU's aclk clock */ |
270 | struct clk *pclk; /* SYSMMU's pclk clock */ | |
2860af3c | 271 | struct clk *clk_master; /* master's device clock */ |
2860af3c | 272 | spinlock_t lock; /* lock for modyfying state */ |
47a574ff | 273 | bool active; /* current status */ |
2860af3c MS |
274 | struct exynos_iommu_domain *domain; /* domain we belong to */ |
275 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 276 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
277 | phys_addr_t pgtable; /* assigned page table structure */ |
278 | unsigned int version; /* our version */ | |
d2c302b6 JR |
279 | |
280 | struct iommu_device iommu; /* IOMMU core handle */ | |
2a96536e KC |
281 | }; |
282 | ||
e1fd1eaa JR |
283 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
284 | { | |
285 | return container_of(dom, struct exynos_iommu_domain, domain); | |
286 | } | |
287 | ||
02cdc365 | 288 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 289 | { |
84bd0428 | 290 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
291 | } |
292 | ||
02cdc365 | 293 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
294 | { |
295 | int i = 120; | |
296 | ||
84bd0428 MS |
297 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
298 | while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
299 | --i; |
300 | ||
84bd0428 | 301 | if (!(readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
02cdc365 | 302 | sysmmu_unblock(data); |
2a96536e KC |
303 | return false; |
304 | } | |
305 | ||
306 | return true; | |
307 | } | |
308 | ||
02cdc365 | 309 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 310 | { |
740a01ee | 311 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 312 | writel(0x1, data->sfrbase + REG_MMU_FLUSH); |
740a01ee | 313 | else |
84bd0428 | 314 | writel(0x1, data->sfrbase + REG_V5_MMU_FLUSH_ALL); |
2a96536e KC |
315 | } |
316 | ||
02cdc365 | 317 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 318 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 319 | { |
3ad6b7f3 | 320 | unsigned int i; |
365409db | 321 | |
d5bf739d MS |
322 | if (MMU_MAJ_VER(data->version) < 5) { |
323 | for (i = 0; i < num_inv; i++) { | |
84bd0428 | 324 | writel((iova & SPAGE_MASK) | 1, |
740a01ee | 325 | data->sfrbase + REG_MMU_FLUSH_ENTRY); |
d5bf739d MS |
326 | iova += SPAGE_SIZE; |
327 | } | |
328 | } else { | |
329 | if (num_inv == 1) { | |
84bd0428 | 330 | writel((iova & SPAGE_MASK) | 1, |
740a01ee | 331 | data->sfrbase + REG_V5_MMU_FLUSH_ENTRY); |
d5bf739d MS |
332 | } else { |
333 | writel((iova & SPAGE_MASK), | |
334 | data->sfrbase + REG_V5_MMU_FLUSH_START); | |
335 | writel((iova & SPAGE_MASK) + (num_inv - 1) * SPAGE_SIZE, | |
336 | data->sfrbase + REG_V5_MMU_FLUSH_END); | |
337 | writel(1, data->sfrbase + REG_V5_MMU_FLUSH_RANGE); | |
338 | } | |
3ad6b7f3 | 339 | } |
2a96536e KC |
340 | } |
341 | ||
02cdc365 | 342 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 343 | { |
740a01ee | 344 | if (MMU_MAJ_VER(data->version) < 5) |
84bd0428 | 345 | writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); |
740a01ee | 346 | else |
84bd0428 | 347 | writel(pgd >> PAGE_SHIFT, |
740a01ee | 348 | data->sfrbase + REG_V5_PT_BASE_PFN); |
2a96536e | 349 | |
02cdc365 | 350 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
351 | } |
352 | ||
fecc49db MS |
353 | static void __sysmmu_enable_clocks(struct sysmmu_drvdata *data) |
354 | { | |
355 | BUG_ON(clk_prepare_enable(data->clk_master)); | |
356 | BUG_ON(clk_prepare_enable(data->clk)); | |
357 | BUG_ON(clk_prepare_enable(data->pclk)); | |
358 | BUG_ON(clk_prepare_enable(data->aclk)); | |
359 | } | |
360 | ||
361 | static void __sysmmu_disable_clocks(struct sysmmu_drvdata *data) | |
362 | { | |
363 | clk_disable_unprepare(data->aclk); | |
364 | clk_disable_unprepare(data->pclk); | |
365 | clk_disable_unprepare(data->clk); | |
366 | clk_disable_unprepare(data->clk_master); | |
367 | } | |
368 | ||
850d313e MS |
369 | static void __sysmmu_get_version(struct sysmmu_drvdata *data) |
370 | { | |
371 | u32 ver; | |
372 | ||
fecc49db | 373 | __sysmmu_enable_clocks(data); |
850d313e | 374 | |
84bd0428 | 375 | ver = readl(data->sfrbase + REG_MMU_VERSION); |
850d313e MS |
376 | |
377 | /* controllers on some SoCs don't report proper version */ | |
378 | if (ver == 0x80000001u) | |
379 | data->version = MAKE_MMU_VER(1, 0); | |
380 | else | |
381 | data->version = MMU_RAW_VER(ver); | |
382 | ||
383 | dev_dbg(data->sysmmu, "hardware version: %d.%d\n", | |
384 | MMU_MAJ_VER(data->version), MMU_MIN_VER(data->version)); | |
385 | ||
fecc49db | 386 | __sysmmu_disable_clocks(data); |
850d313e MS |
387 | } |
388 | ||
d093fc7e MS |
389 | static void show_fault_information(struct sysmmu_drvdata *data, |
390 | const struct sysmmu_fault_info *finfo, | |
391 | sysmmu_iova_t fault_addr) | |
2a96536e | 392 | { |
d09d78fc | 393 | sysmmu_pte_t *ent; |
2a96536e | 394 | |
ec5d241b MS |
395 | dev_err(data->sysmmu, "%s: %s FAULT occurred at %#x\n", |
396 | dev_name(data->master), finfo->name, fault_addr); | |
397 | dev_dbg(data->sysmmu, "Page table base: %pa\n", &data->pgtable); | |
d093fc7e | 398 | ent = section_entry(phys_to_virt(data->pgtable), fault_addr); |
ec5d241b | 399 | dev_dbg(data->sysmmu, "\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
400 | if (lv1ent_page(ent)) { |
401 | ent = page_entry(ent, fault_addr); | |
ec5d241b | 402 | dev_dbg(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 403 | } |
2a96536e KC |
404 | } |
405 | ||
406 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
407 | { | |
f171abab | 408 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 409 | struct sysmmu_drvdata *data = dev_id; |
740a01ee MS |
410 | const struct sysmmu_fault_info *finfo; |
411 | unsigned int i, n, itype; | |
d093fc7e | 412 | sysmmu_iova_t fault_addr = -1; |
740a01ee | 413 | unsigned short reg_status, reg_clear; |
7222e8db | 414 | int ret = -ENOSYS; |
2a96536e | 415 | |
47a574ff | 416 | WARN_ON(!data->active); |
2a96536e | 417 | |
740a01ee MS |
418 | if (MMU_MAJ_VER(data->version) < 5) { |
419 | reg_status = REG_INT_STATUS; | |
420 | reg_clear = REG_INT_CLEAR; | |
421 | finfo = sysmmu_faults; | |
422 | n = ARRAY_SIZE(sysmmu_faults); | |
423 | } else { | |
424 | reg_status = REG_V5_INT_STATUS; | |
425 | reg_clear = REG_V5_INT_CLEAR; | |
426 | finfo = sysmmu_v5_faults; | |
427 | n = ARRAY_SIZE(sysmmu_v5_faults); | |
428 | } | |
429 | ||
9d4e7a24 CK |
430 | spin_lock(&data->lock); |
431 | ||
b398af21 | 432 | clk_enable(data->clk_master); |
9d4e7a24 | 433 | |
84bd0428 | 434 | itype = __ffs(readl(data->sfrbase + reg_status)); |
d093fc7e MS |
435 | for (i = 0; i < n; i++, finfo++) |
436 | if (finfo->bit == itype) | |
437 | break; | |
438 | /* unknown/unsupported fault */ | |
439 | BUG_ON(i == n); | |
440 | ||
441 | /* print debug message */ | |
84bd0428 | 442 | fault_addr = readl(data->sfrbase + finfo->addr_reg); |
d093fc7e | 443 | show_fault_information(data, finfo, fault_addr); |
2a96536e | 444 | |
d093fc7e MS |
445 | if (data->domain) |
446 | ret = report_iommu_fault(&data->domain->domain, | |
447 | data->master, fault_addr, finfo->type); | |
1fab7fa7 CK |
448 | /* fault is not recovered by fault handler */ |
449 | BUG_ON(ret != 0); | |
2a96536e | 450 | |
84bd0428 | 451 | writel(1 << itype, data->sfrbase + reg_clear); |
1fab7fa7 | 452 | |
02cdc365 | 453 | sysmmu_unblock(data); |
2a96536e | 454 | |
b398af21 | 455 | clk_disable(data->clk_master); |
70605870 | 456 | |
9d4e7a24 | 457 | spin_unlock(&data->lock); |
2a96536e KC |
458 | |
459 | return IRQ_HANDLED; | |
460 | } | |
461 | ||
47a574ff | 462 | static void __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 463 | { |
47a574ff MS |
464 | unsigned long flags; |
465 | ||
b398af21 | 466 | clk_enable(data->clk_master); |
70605870 | 467 | |
47a574ff | 468 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 MS |
469 | writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
470 | writel(0, data->sfrbase + REG_MMU_CFG); | |
47a574ff | 471 | data->active = false; |
6b21a5db CK |
472 | spin_unlock_irqrestore(&data->lock, flags); |
473 | ||
47a574ff | 474 | __sysmmu_disable_clocks(data); |
6b21a5db | 475 | } |
2a96536e | 476 | |
6b21a5db CK |
477 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
478 | { | |
83addecd MS |
479 | unsigned int cfg; |
480 | ||
83addecd MS |
481 | if (data->version <= MAKE_MMU_VER(3, 1)) |
482 | cfg = CFG_LRU | CFG_QOS(15); | |
483 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
484 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
485 | else | |
486 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db | 487 | |
1a0d8dac MS |
488 | cfg |= CFG_EAP; /* enable access protection bits check */ |
489 | ||
84bd0428 | 490 | writel(cfg, data->sfrbase + REG_MMU_CFG); |
6b21a5db CK |
491 | } |
492 | ||
47a574ff | 493 | static void __sysmmu_enable(struct sysmmu_drvdata *data) |
6b21a5db | 494 | { |
47a574ff MS |
495 | unsigned long flags; |
496 | ||
fecc49db | 497 | __sysmmu_enable_clocks(data); |
70605870 | 498 | |
47a574ff | 499 | spin_lock_irqsave(&data->lock, flags); |
84bd0428 | 500 | writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 501 | __sysmmu_init_config(data); |
02cdc365 | 502 | __sysmmu_set_ptbase(data, data->pgtable); |
84bd0428 | 503 | writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
47a574ff MS |
504 | data->active = true; |
505 | spin_unlock_irqrestore(&data->lock, flags); | |
7222e8db | 506 | |
fecc49db MS |
507 | /* |
508 | * SYSMMU driver keeps master's clock enabled only for the short | |
509 | * time, while accessing the registers. For performing address | |
510 | * translation during DMA transaction it relies on the client | |
511 | * driver to enable it. | |
512 | */ | |
b398af21 | 513 | clk_disable(data->clk_master); |
6b21a5db | 514 | } |
70605870 | 515 | |
469acebe | 516 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
517 | sysmmu_iova_t iova) |
518 | { | |
519 | unsigned long flags; | |
66a7ed84 | 520 | |
66a7ed84 | 521 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 522 | if (data->active && data->version >= MAKE_MMU_VER(3, 3)) { |
01324ab2 | 523 | clk_enable(data->clk_master); |
7d2aa6b8 | 524 | if (sysmmu_block(data)) { |
cd37a296 MS |
525 | if (data->version >= MAKE_MMU_VER(5, 0)) |
526 | __sysmmu_tlb_invalidate(data); | |
527 | else | |
528 | __sysmmu_tlb_invalidate_entry(data, iova, 1); | |
7d2aa6b8 MS |
529 | sysmmu_unblock(data); |
530 | } | |
01324ab2 | 531 | clk_disable(data->clk_master); |
d631ea98 | 532 | } |
66a7ed84 | 533 | spin_unlock_irqrestore(&data->lock, flags); |
66a7ed84 CK |
534 | } |
535 | ||
469acebe MS |
536 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
537 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
538 | { |
539 | unsigned long flags; | |
2a96536e | 540 | |
6b21a5db | 541 | spin_lock_irqsave(&data->lock, flags); |
47a574ff | 542 | if (data->active) { |
3ad6b7f3 | 543 | unsigned int num_inv = 1; |
70605870 | 544 | |
b398af21 | 545 | clk_enable(data->clk_master); |
70605870 | 546 | |
3ad6b7f3 CK |
547 | /* |
548 | * L2TLB invalidation required | |
549 | * 4KB page: 1 invalidation | |
f171abab SK |
550 | * 64KB page: 16 invalidations |
551 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
552 | * because it is set-associative TLB |
553 | * with 8-way and 64 sets. | |
554 | * 1MB page can be cached in one of all sets. | |
555 | * 64KB page can be one of 16 consecutive sets. | |
556 | */ | |
512bd0c6 | 557 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
558 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
559 | ||
02cdc365 MS |
560 | if (sysmmu_block(data)) { |
561 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
562 | sysmmu_unblock(data); | |
2a96536e | 563 | } |
b398af21 | 564 | clk_disable(data->clk_master); |
2a96536e | 565 | } |
9d4e7a24 | 566 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
567 | } |
568 | ||
0b9a3694 | 569 | static const struct iommu_ops exynos_iommu_ops; |
96f66557 | 570 | |
6b21a5db | 571 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 572 | { |
46c16d1e | 573 | int irq, ret; |
7222e8db | 574 | struct device *dev = &pdev->dev; |
2a96536e | 575 | struct sysmmu_drvdata *data; |
7222e8db | 576 | struct resource *res; |
2a96536e | 577 | |
46c16d1e CK |
578 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
579 | if (!data) | |
580 | return -ENOMEM; | |
2a96536e | 581 | |
7222e8db | 582 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
583 | data->sfrbase = devm_ioremap_resource(dev, res); |
584 | if (IS_ERR(data->sfrbase)) | |
585 | return PTR_ERR(data->sfrbase); | |
2a96536e | 586 | |
46c16d1e CK |
587 | irq = platform_get_irq(pdev, 0); |
588 | if (irq <= 0) { | |
0bf4e54d | 589 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 590 | return irq; |
2a96536e KC |
591 | } |
592 | ||
46c16d1e | 593 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
594 | dev_name(dev), data); |
595 | if (ret) { | |
46c16d1e CK |
596 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
597 | return ret; | |
2a96536e KC |
598 | } |
599 | ||
46c16d1e | 600 | data->clk = devm_clk_get(dev, "sysmmu"); |
0c2b063f | 601 | if (PTR_ERR(data->clk) == -ENOENT) |
740a01ee | 602 | data->clk = NULL; |
0c2b063f MS |
603 | else if (IS_ERR(data->clk)) |
604 | return PTR_ERR(data->clk); | |
740a01ee MS |
605 | |
606 | data->aclk = devm_clk_get(dev, "aclk"); | |
0c2b063f | 607 | if (PTR_ERR(data->aclk) == -ENOENT) |
740a01ee | 608 | data->aclk = NULL; |
0c2b063f MS |
609 | else if (IS_ERR(data->aclk)) |
610 | return PTR_ERR(data->aclk); | |
740a01ee MS |
611 | |
612 | data->pclk = devm_clk_get(dev, "pclk"); | |
0c2b063f | 613 | if (PTR_ERR(data->pclk) == -ENOENT) |
740a01ee | 614 | data->pclk = NULL; |
0c2b063f MS |
615 | else if (IS_ERR(data->pclk)) |
616 | return PTR_ERR(data->pclk); | |
740a01ee MS |
617 | |
618 | if (!data->clk && (!data->aclk || !data->pclk)) { | |
619 | dev_err(dev, "Failed to get device clock(s)!\n"); | |
620 | return -ENOSYS; | |
2a96536e KC |
621 | } |
622 | ||
70605870 | 623 | data->clk_master = devm_clk_get(dev, "master"); |
0c2b063f | 624 | if (PTR_ERR(data->clk_master) == -ENOENT) |
b398af21 | 625 | data->clk_master = NULL; |
0c2b063f MS |
626 | else if (IS_ERR(data->clk_master)) |
627 | return PTR_ERR(data->clk_master); | |
70605870 | 628 | |
2a96536e | 629 | data->sysmmu = dev; |
9d4e7a24 | 630 | spin_lock_init(&data->lock); |
2a96536e | 631 | |
d2c302b6 JR |
632 | ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, |
633 | dev_name(data->sysmmu)); | |
634 | if (ret) | |
635 | return ret; | |
636 | ||
637 | iommu_device_set_ops(&data->iommu, &exynos_iommu_ops); | |
638 | iommu_device_set_fwnode(&data->iommu, &dev->of_node->fwnode); | |
639 | ||
640 | ret = iommu_device_register(&data->iommu); | |
641 | if (ret) | |
642 | return ret; | |
643 | ||
7222e8db CK |
644 | platform_set_drvdata(pdev, data); |
645 | ||
850d313e | 646 | __sysmmu_get_version(data); |
740a01ee | 647 | if (PG_ENT_SHIFT < 0) { |
1a0d8dac | 648 | if (MMU_MAJ_VER(data->version) < 5) { |
740a01ee | 649 | PG_ENT_SHIFT = SYSMMU_PG_ENT_SHIFT; |
1a0d8dac MS |
650 | LV1_PROT = SYSMMU_LV1_PROT; |
651 | LV2_PROT = SYSMMU_LV2_PROT; | |
652 | } else { | |
740a01ee | 653 | PG_ENT_SHIFT = SYSMMU_V5_PG_ENT_SHIFT; |
1a0d8dac MS |
654 | LV1_PROT = SYSMMU_V5_LV1_PROT; |
655 | LV2_PROT = SYSMMU_V5_LV2_PROT; | |
656 | } | |
740a01ee MS |
657 | } |
658 | ||
928055a0 MS |
659 | /* |
660 | * use the first registered sysmmu device for performing | |
661 | * dma mapping operations on iommu page tables (cpu cache flush) | |
662 | */ | |
663 | if (!dma_dev) | |
664 | dma_dev = &pdev->dev; | |
665 | ||
f4723ec1 | 666 | pm_runtime_enable(dev); |
2a96536e | 667 | |
2a96536e | 668 | return 0; |
2a96536e KC |
669 | } |
670 | ||
9b265536 | 671 | static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) |
622015e4 MS |
672 | { |
673 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 674 | struct device *master = data->master; |
622015e4 | 675 | |
47a574ff | 676 | if (master) { |
9b265536 MS |
677 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
678 | ||
679 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
680 | if (data->domain) { |
681 | dev_dbg(data->sysmmu, "saving state\n"); | |
682 | __sysmmu_disable(data); | |
683 | } | |
9b265536 | 684 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
685 | } |
686 | return 0; | |
687 | } | |
688 | ||
9b265536 | 689 | static int __maybe_unused exynos_sysmmu_resume(struct device *dev) |
622015e4 MS |
690 | { |
691 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
47a574ff | 692 | struct device *master = data->master; |
622015e4 | 693 | |
47a574ff | 694 | if (master) { |
9b265536 MS |
695 | struct exynos_iommu_owner *owner = master->archdata.iommu; |
696 | ||
697 | mutex_lock(&owner->rpm_lock); | |
92798b45 MS |
698 | if (data->domain) { |
699 | dev_dbg(data->sysmmu, "restoring state\n"); | |
700 | __sysmmu_enable(data); | |
701 | } | |
9b265536 | 702 | mutex_unlock(&owner->rpm_lock); |
622015e4 MS |
703 | } |
704 | return 0; | |
705 | } | |
622015e4 MS |
706 | |
707 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
9b265536 | 708 | SET_RUNTIME_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume, NULL) |
2f5f44f2 MS |
709 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
710 | pm_runtime_force_resume) | |
622015e4 MS |
711 | }; |
712 | ||
9d25e3cc | 713 | static const struct of_device_id sysmmu_of_match[] = { |
6b21a5db CK |
714 | { .compatible = "samsung,exynos-sysmmu", }, |
715 | { }, | |
716 | }; | |
717 | ||
718 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
719 | .probe = exynos_sysmmu_probe, | |
720 | .driver = { | |
2a96536e | 721 | .name = "exynos-sysmmu", |
6b21a5db | 722 | .of_match_table = sysmmu_of_match, |
622015e4 | 723 | .pm = &sysmmu_pm_ops, |
b54b874f | 724 | .suppress_bind_attrs = true, |
2a96536e KC |
725 | } |
726 | }; | |
727 | ||
5e3435eb | 728 | static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 729 | { |
5e3435eb MS |
730 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
731 | DMA_TO_DEVICE); | |
6ae5343c | 732 | *ent = cpu_to_le32(val); |
5e3435eb MS |
733 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), |
734 | DMA_TO_DEVICE); | |
2a96536e KC |
735 | } |
736 | ||
e1fd1eaa | 737 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 738 | { |
bfa00489 | 739 | struct exynos_iommu_domain *domain; |
5e3435eb | 740 | dma_addr_t handle; |
66a7ed84 | 741 | int i; |
2a96536e | 742 | |
740a01ee MS |
743 | /* Check if correct PTE offsets are initialized */ |
744 | BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev); | |
e1fd1eaa | 745 | |
bfa00489 MS |
746 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
747 | if (!domain) | |
e1fd1eaa | 748 | return NULL; |
2a96536e | 749 | |
58c6f6a3 MS |
750 | if (type == IOMMU_DOMAIN_DMA) { |
751 | if (iommu_get_dma_cookie(&domain->domain) != 0) | |
752 | goto err_pgtable; | |
753 | } else if (type != IOMMU_DOMAIN_UNMANAGED) { | |
754 | goto err_pgtable; | |
755 | } | |
756 | ||
bfa00489 MS |
757 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
758 | if (!domain->pgtable) | |
58c6f6a3 | 759 | goto err_dma_cookie; |
2a96536e | 760 | |
bfa00489 MS |
761 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
762 | if (!domain->lv2entcnt) | |
2a96536e KC |
763 | goto err_counter; |
764 | ||
f171abab | 765 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
e7527663 MS |
766 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
767 | domain->pgtable[i] = ZERO_LV2LINK; | |
66a7ed84 | 768 | |
5e3435eb MS |
769 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
770 | DMA_TO_DEVICE); | |
771 | /* For mapping page table entries we rely on dma == phys */ | |
772 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
0d6d3da4 MS |
773 | if (dma_mapping_error(dma_dev, handle)) |
774 | goto err_lv2ent; | |
2a96536e | 775 | |
bfa00489 MS |
776 | spin_lock_init(&domain->lock); |
777 | spin_lock_init(&domain->pgtablelock); | |
778 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 779 | |
bfa00489 MS |
780 | domain->domain.geometry.aperture_start = 0; |
781 | domain->domain.geometry.aperture_end = ~0UL; | |
782 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 783 | |
bfa00489 | 784 | return &domain->domain; |
2a96536e | 785 | |
0d6d3da4 MS |
786 | err_lv2ent: |
787 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
2a96536e | 788 | err_counter: |
bfa00489 | 789 | free_pages((unsigned long)domain->pgtable, 2); |
58c6f6a3 MS |
790 | err_dma_cookie: |
791 | if (type == IOMMU_DOMAIN_DMA) | |
792 | iommu_put_dma_cookie(&domain->domain); | |
2a96536e | 793 | err_pgtable: |
bfa00489 | 794 | kfree(domain); |
e1fd1eaa | 795 | return NULL; |
2a96536e KC |
796 | } |
797 | ||
bfa00489 | 798 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 799 | { |
bfa00489 | 800 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 801 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
802 | unsigned long flags; |
803 | int i; | |
804 | ||
bfa00489 | 805 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 806 | |
bfa00489 | 807 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 808 | |
bfa00489 | 809 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
e1172300 | 810 | spin_lock(&data->lock); |
b0d4c861 | 811 | __sysmmu_disable(data); |
47a574ff MS |
812 | data->pgtable = 0; |
813 | data->domain = NULL; | |
469acebe | 814 | list_del_init(&data->domain_node); |
e1172300 | 815 | spin_unlock(&data->lock); |
2a96536e KC |
816 | } |
817 | ||
bfa00489 | 818 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 819 | |
58c6f6a3 MS |
820 | if (iommu_domain->type == IOMMU_DOMAIN_DMA) |
821 | iommu_put_dma_cookie(iommu_domain); | |
822 | ||
5e3435eb MS |
823 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
824 | DMA_TO_DEVICE); | |
825 | ||
2a96536e | 826 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
827 | if (lv1ent_page(domain->pgtable + i)) { |
828 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
829 | ||
830 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
831 | DMA_TO_DEVICE); | |
734c3c73 | 832 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
833 | phys_to_virt(base)); |
834 | } | |
2a96536e | 835 | |
bfa00489 MS |
836 | free_pages((unsigned long)domain->pgtable, 2); |
837 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
838 | kfree(domain); | |
2a96536e KC |
839 | } |
840 | ||
5fa61cbf MS |
841 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
842 | struct device *dev) | |
843 | { | |
844 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
845 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); | |
846 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
847 | struct sysmmu_drvdata *data, *next; | |
848 | unsigned long flags; | |
5fa61cbf MS |
849 | |
850 | if (!has_sysmmu(dev) || owner->domain != iommu_domain) | |
851 | return; | |
852 | ||
9b265536 MS |
853 | mutex_lock(&owner->rpm_lock); |
854 | ||
855 | list_for_each_entry(data, &owner->controllers, owner_node) { | |
856 | pm_runtime_get_noresume(data->sysmmu); | |
857 | if (pm_runtime_active(data->sysmmu)) | |
858 | __sysmmu_disable(data); | |
e1172300 MS |
859 | pm_runtime_put(data->sysmmu); |
860 | } | |
861 | ||
5fa61cbf MS |
862 | spin_lock_irqsave(&domain->lock, flags); |
863 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { | |
e1172300 | 864 | spin_lock(&data->lock); |
47a574ff MS |
865 | data->pgtable = 0; |
866 | data->domain = NULL; | |
b0d4c861 | 867 | list_del_init(&data->domain_node); |
e1172300 | 868 | spin_unlock(&data->lock); |
5fa61cbf | 869 | } |
e1172300 | 870 | owner->domain = NULL; |
5fa61cbf MS |
871 | spin_unlock_irqrestore(&domain->lock, flags); |
872 | ||
9b265536 | 873 | mutex_unlock(&owner->rpm_lock); |
5fa61cbf | 874 | |
b0d4c861 MS |
875 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", __func__, |
876 | &pagetable); | |
5fa61cbf MS |
877 | } |
878 | ||
bfa00489 | 879 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
880 | struct device *dev) |
881 | { | |
6b21a5db | 882 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 883 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 884 | struct sysmmu_drvdata *data; |
bfa00489 | 885 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 886 | unsigned long flags; |
2a96536e | 887 | |
469acebe MS |
888 | if (!has_sysmmu(dev)) |
889 | return -ENODEV; | |
2a96536e | 890 | |
5fa61cbf MS |
891 | if (owner->domain) |
892 | exynos_iommu_detach_device(owner->domain, dev); | |
893 | ||
9b265536 MS |
894 | mutex_lock(&owner->rpm_lock); |
895 | ||
e1172300 | 896 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 897 | list_for_each_entry(data, &owner->controllers, owner_node) { |
e1172300 | 898 | spin_lock(&data->lock); |
47a574ff MS |
899 | data->pgtable = pagetable; |
900 | data->domain = domain; | |
e1172300 MS |
901 | list_add_tail(&data->domain_node, &domain->clients); |
902 | spin_unlock(&data->lock); | |
903 | } | |
904 | owner->domain = iommu_domain; | |
905 | spin_unlock_irqrestore(&domain->lock, flags); | |
906 | ||
9b265536 MS |
907 | list_for_each_entry(data, &owner->controllers, owner_node) { |
908 | pm_runtime_get_noresume(data->sysmmu); | |
909 | if (pm_runtime_active(data->sysmmu)) | |
910 | __sysmmu_enable(data); | |
911 | pm_runtime_put(data->sysmmu); | |
912 | } | |
913 | ||
914 | mutex_unlock(&owner->rpm_lock); | |
915 | ||
b0d4c861 MS |
916 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa\n", __func__, |
917 | &pagetable); | |
7222e8db | 918 | |
b0d4c861 | 919 | return 0; |
2a96536e KC |
920 | } |
921 | ||
bfa00489 | 922 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 923 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 924 | { |
61128f08 | 925 | if (lv1ent_section(sent)) { |
d09d78fc | 926 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
927 | return ERR_PTR(-EADDRINUSE); |
928 | } | |
929 | ||
2a96536e | 930 | if (lv1ent_fault(sent)) { |
0d6d3da4 | 931 | dma_addr_t handle; |
d09d78fc | 932 | sysmmu_pte_t *pent; |
66a7ed84 | 933 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 934 | |
734c3c73 | 935 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
dbf6c6ef | 936 | BUG_ON((uintptr_t)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 937 | if (!pent) |
61128f08 | 938 | return ERR_PTR(-ENOMEM); |
2a96536e | 939 | |
5e3435eb | 940 | update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 941 | kmemleak_ignore(pent); |
2a96536e | 942 | *pgcounter = NUM_LV2ENTRIES; |
0d6d3da4 MS |
943 | handle = dma_map_single(dma_dev, pent, LV2TABLE_SIZE, |
944 | DMA_TO_DEVICE); | |
945 | if (dma_mapping_error(dma_dev, handle)) { | |
946 | kmem_cache_free(lv2table_kmem_cache, pent); | |
947 | return ERR_PTR(-EADDRINUSE); | |
948 | } | |
66a7ed84 CK |
949 | |
950 | /* | |
f171abab SK |
951 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
952 | * FLPD cache may cache the address of zero_l2_table. This | |
953 | * function replaces the zero_l2_table with new L2 page table | |
954 | * to write valid mappings. | |
66a7ed84 | 955 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
956 | * cache may still cache zero_l2_table for the valid area |
957 | * instead of new L2 page table that has the mapping | |
958 | * information of the valid area. | |
66a7ed84 CK |
959 | * Thus any replacement of zero_l2_table with other valid L2 |
960 | * page table must involve FLPD cache invalidation for System | |
961 | * MMU v3.3. | |
962 | * FLPD cache invalidation is performed with TLB invalidation | |
963 | * by VPN without blocking. It is safe to invalidate TLB without | |
964 | * blocking because the target address of TLB invalidation is | |
965 | * not currently mapped. | |
966 | */ | |
967 | if (need_flush_flpd_cache) { | |
469acebe | 968 | struct sysmmu_drvdata *data; |
365409db | 969 | |
bfa00489 MS |
970 | spin_lock(&domain->lock); |
971 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 972 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 973 | spin_unlock(&domain->lock); |
66a7ed84 | 974 | } |
2a96536e KC |
975 | } |
976 | ||
977 | return page_entry(sent, iova); | |
978 | } | |
979 | ||
bfa00489 | 980 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 981 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
1a0d8dac | 982 | phys_addr_t paddr, int prot, short *pgcnt) |
2a96536e | 983 | { |
61128f08 | 984 | if (lv1ent_section(sent)) { |
d09d78fc | 985 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 986 | iova); |
2a96536e | 987 | return -EADDRINUSE; |
61128f08 | 988 | } |
2a96536e KC |
989 | |
990 | if (lv1ent_page(sent)) { | |
61128f08 | 991 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 992 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 993 | iova); |
2a96536e | 994 | return -EADDRINUSE; |
61128f08 | 995 | } |
2a96536e | 996 | |
734c3c73 | 997 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
998 | *pgcnt = 0; |
999 | } | |
1000 | ||
1a0d8dac | 1001 | update_pte(sent, mk_lv1ent_sect(paddr, prot)); |
2a96536e | 1002 | |
bfa00489 | 1003 | spin_lock(&domain->lock); |
66a7ed84 | 1004 | if (lv1ent_page_zero(sent)) { |
469acebe | 1005 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1006 | /* |
1007 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
1008 | * entry by speculative prefetch of SLPD which has no mapping. | |
1009 | */ | |
bfa00489 | 1010 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1011 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 1012 | } |
bfa00489 | 1013 | spin_unlock(&domain->lock); |
66a7ed84 | 1014 | |
2a96536e KC |
1015 | return 0; |
1016 | } | |
1017 | ||
d09d78fc | 1018 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
1a0d8dac | 1019 | int prot, short *pgcnt) |
2a96536e KC |
1020 | { |
1021 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 1022 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
1023 | return -EADDRINUSE; |
1024 | ||
1a0d8dac | 1025 | update_pte(pent, mk_lv2ent_spage(paddr, prot)); |
2a96536e KC |
1026 | *pgcnt -= 1; |
1027 | } else { /* size == LPAGE_SIZE */ | |
1028 | int i; | |
5e3435eb | 1029 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 1030 | |
5e3435eb MS |
1031 | dma_sync_single_for_cpu(dma_dev, pent_base, |
1032 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1033 | DMA_TO_DEVICE); | |
2a96536e | 1034 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 1035 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
1036 | if (i > 0) |
1037 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
1038 | return -EADDRINUSE; |
1039 | } | |
1040 | ||
1a0d8dac | 1041 | *pent = mk_lv2ent_lpage(paddr, prot); |
2a96536e | 1042 | } |
5e3435eb MS |
1043 | dma_sync_single_for_device(dma_dev, pent_base, |
1044 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
1045 | DMA_TO_DEVICE); | |
2a96536e KC |
1046 | *pgcnt -= SPAGES_PER_LPAGE; |
1047 | } | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
66a7ed84 CK |
1052 | /* |
1053 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
1054 | * | |
f171abab | 1055 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 1056 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
1057 | * However, the logic has a bug that while caching faulty page table entries, |
1058 | * System MMU reports page fault if the cached fault entry is hit even though | |
1059 | * the fault entry is updated to a valid entry after the entry is cached. | |
1060 | * To prevent caching faulty page table entries which may be updated to valid | |
1061 | * entries later, the virtual memory manager should care about the workaround | |
1062 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
1063 | * |
1064 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 1065 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 1066 | * |
f171abab | 1067 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
1068 | * the following sizes for System MMU v3.1 and v3.2. |
1069 | * System MMU v3.1: 128KiB | |
1070 | * System MMU v3.2: 256KiB | |
1071 | * | |
1072 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
1073 | * more workarounds. |
1074 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
1075 | * than or equal to 128KiB. | |
66a7ed84 CK |
1076 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
1077 | */ | |
bfa00489 MS |
1078 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
1079 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
1080 | int prot) | |
2a96536e | 1081 | { |
bfa00489 | 1082 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1083 | sysmmu_pte_t *entry; |
1084 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
1085 | unsigned long flags; |
1086 | int ret = -ENOMEM; | |
1087 | ||
bfa00489 | 1088 | BUG_ON(domain->pgtable == NULL); |
1a0d8dac | 1089 | prot &= SYSMMU_SUPPORTED_PROT_BITS; |
2a96536e | 1090 | |
bfa00489 | 1091 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1092 | |
bfa00489 | 1093 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1094 | |
1095 | if (size == SECT_SIZE) { | |
1a0d8dac | 1096 | ret = lv1set_section(domain, entry, iova, paddr, prot, |
bfa00489 | 1097 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e | 1098 | } else { |
d09d78fc | 1099 | sysmmu_pte_t *pent; |
2a96536e | 1100 | |
bfa00489 MS |
1101 | pent = alloc_lv2entry(domain, entry, iova, |
1102 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 1103 | |
61128f08 CK |
1104 | if (IS_ERR(pent)) |
1105 | ret = PTR_ERR(pent); | |
2a96536e | 1106 | else |
1a0d8dac | 1107 | ret = lv2set_page(pent, paddr, size, prot, |
bfa00489 | 1108 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1109 | } |
1110 | ||
61128f08 | 1111 | if (ret) |
0bf4e54d CK |
1112 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1113 | __func__, ret, size, iova); | |
2a96536e | 1114 | |
bfa00489 | 1115 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1116 | |
1117 | return ret; | |
1118 | } | |
1119 | ||
bfa00489 MS |
1120 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1121 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1122 | { |
469acebe | 1123 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1124 | unsigned long flags; |
1125 | ||
bfa00489 | 1126 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1127 | |
bfa00489 | 1128 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1129 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1130 | |
bfa00489 | 1131 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1132 | } |
1133 | ||
bfa00489 MS |
1134 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1135 | unsigned long l_iova, size_t size) | |
2a96536e | 1136 | { |
bfa00489 | 1137 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1138 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1139 | sysmmu_pte_t *ent; | |
61128f08 | 1140 | size_t err_pgsize; |
d09d78fc | 1141 | unsigned long flags; |
2a96536e | 1142 | |
bfa00489 | 1143 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1144 | |
bfa00489 | 1145 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1146 | |
bfa00489 | 1147 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1148 | |
1149 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1150 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1151 | err_pgsize = SECT_SIZE; |
1152 | goto err; | |
1153 | } | |
2a96536e | 1154 | |
f171abab | 1155 | /* workaround for h/w bug in System MMU v3.3 */ |
5e3435eb | 1156 | update_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1157 | size = SECT_SIZE; |
1158 | goto done; | |
1159 | } | |
1160 | ||
1161 | if (unlikely(lv1ent_fault(ent))) { | |
1162 | if (size > SECT_SIZE) | |
1163 | size = SECT_SIZE; | |
1164 | goto done; | |
1165 | } | |
1166 | ||
1167 | /* lv1ent_page(sent) == true here */ | |
1168 | ||
1169 | ent = page_entry(ent, iova); | |
1170 | ||
1171 | if (unlikely(lv2ent_fault(ent))) { | |
1172 | size = SPAGE_SIZE; | |
1173 | goto done; | |
1174 | } | |
1175 | ||
1176 | if (lv2ent_small(ent)) { | |
5e3435eb | 1177 | update_pte(ent, 0); |
2a96536e | 1178 | size = SPAGE_SIZE; |
bfa00489 | 1179 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1180 | goto done; |
1181 | } | |
1182 | ||
1183 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1184 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1185 | err_pgsize = LPAGE_SIZE; |
1186 | goto err; | |
1187 | } | |
2a96536e | 1188 | |
5e3435eb MS |
1189 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1190 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1191 | DMA_TO_DEVICE); | |
2a96536e | 1192 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1193 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1194 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1195 | DMA_TO_DEVICE); | |
2a96536e | 1196 | size = LPAGE_SIZE; |
bfa00489 | 1197 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1198 | done: |
bfa00489 | 1199 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1200 | |
bfa00489 | 1201 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1202 | |
2a96536e | 1203 | return size; |
61128f08 | 1204 | err: |
bfa00489 | 1205 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1206 | |
0bf4e54d CK |
1207 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1208 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1209 | |
1210 | return 0; | |
2a96536e KC |
1211 | } |
1212 | ||
bfa00489 | 1213 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1214 | dma_addr_t iova) |
2a96536e | 1215 | { |
bfa00489 | 1216 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1217 | sysmmu_pte_t *entry; |
2a96536e KC |
1218 | unsigned long flags; |
1219 | phys_addr_t phys = 0; | |
1220 | ||
bfa00489 | 1221 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1222 | |
bfa00489 | 1223 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1224 | |
1225 | if (lv1ent_section(entry)) { | |
1226 | phys = section_phys(entry) + section_offs(iova); | |
1227 | } else if (lv1ent_page(entry)) { | |
1228 | entry = page_entry(entry, iova); | |
1229 | ||
1230 | if (lv2ent_large(entry)) | |
1231 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1232 | else if (lv2ent_small(entry)) | |
1233 | phys = spage_phys(entry) + spage_offs(iova); | |
1234 | } | |
1235 | ||
bfa00489 | 1236 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1237 | |
1238 | return phys; | |
1239 | } | |
1240 | ||
6c2ae7e2 MS |
1241 | static struct iommu_group *get_device_iommu_group(struct device *dev) |
1242 | { | |
1243 | struct iommu_group *group; | |
1244 | ||
1245 | group = iommu_group_get(dev); | |
1246 | if (!group) | |
1247 | group = iommu_group_alloc(); | |
1248 | ||
1249 | return group; | |
1250 | } | |
1251 | ||
bf4a1c92 AM |
1252 | static int exynos_iommu_add_device(struct device *dev) |
1253 | { | |
7a974b29 MS |
1254 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
1255 | struct sysmmu_drvdata *data; | |
bf4a1c92 | 1256 | struct iommu_group *group; |
bf4a1c92 | 1257 | |
06801db0 MS |
1258 | if (!has_sysmmu(dev)) |
1259 | return -ENODEV; | |
1260 | ||
6c2ae7e2 | 1261 | group = iommu_group_get_for_dev(dev); |
bf4a1c92 | 1262 | |
6c2ae7e2 MS |
1263 | if (IS_ERR(group)) |
1264 | return PTR_ERR(group); | |
bf4a1c92 | 1265 | |
7a974b29 MS |
1266 | list_for_each_entry(data, &owner->controllers, owner_node) { |
1267 | /* | |
1268 | * SYSMMU will be runtime activated via device link | |
1269 | * (dependency) to its master device, so there are no | |
1270 | * direct calls to pm_runtime_get/put in this driver. | |
1271 | */ | |
1272 | data->link = device_link_add(dev, data->sysmmu, | |
1273 | DL_FLAG_PM_RUNTIME); | |
1274 | } | |
bf4a1c92 AM |
1275 | iommu_group_put(group); |
1276 | ||
6c2ae7e2 | 1277 | return 0; |
bf4a1c92 AM |
1278 | } |
1279 | ||
1280 | static void exynos_iommu_remove_device(struct device *dev) | |
1281 | { | |
fff2fd1a | 1282 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
7a974b29 | 1283 | struct sysmmu_drvdata *data; |
fff2fd1a | 1284 | |
06801db0 MS |
1285 | if (!has_sysmmu(dev)) |
1286 | return; | |
1287 | ||
fff2fd1a MS |
1288 | if (owner->domain) { |
1289 | struct iommu_group *group = iommu_group_get(dev); | |
1290 | ||
1291 | if (group) { | |
1292 | WARN_ON(owner->domain != | |
1293 | iommu_group_default_domain(group)); | |
1294 | exynos_iommu_detach_device(owner->domain, dev); | |
1295 | iommu_group_put(group); | |
1296 | } | |
1297 | } | |
bf4a1c92 | 1298 | iommu_group_remove_device(dev); |
7a974b29 MS |
1299 | |
1300 | list_for_each_entry(data, &owner->controllers, owner_node) | |
1301 | device_link_del(data->link); | |
bf4a1c92 AM |
1302 | } |
1303 | ||
aa759fd3 MS |
1304 | static int exynos_iommu_of_xlate(struct device *dev, |
1305 | struct of_phandle_args *spec) | |
1306 | { | |
1307 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1308 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
0bd5a0c7 | 1309 | struct sysmmu_drvdata *data, *entry; |
aa759fd3 MS |
1310 | |
1311 | if (!sysmmu) | |
1312 | return -ENODEV; | |
1313 | ||
1314 | data = platform_get_drvdata(sysmmu); | |
1315 | if (!data) | |
1316 | return -ENODEV; | |
1317 | ||
1318 | if (!owner) { | |
1319 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1320 | if (!owner) | |
1321 | return -ENOMEM; | |
1322 | ||
1323 | INIT_LIST_HEAD(&owner->controllers); | |
9b265536 | 1324 | mutex_init(&owner->rpm_lock); |
aa759fd3 MS |
1325 | dev->archdata.iommu = owner; |
1326 | } | |
1327 | ||
0bd5a0c7 MS |
1328 | list_for_each_entry(entry, &owner->controllers, owner_node) |
1329 | if (entry == data) | |
1330 | return 0; | |
1331 | ||
aa759fd3 | 1332 | list_add_tail(&data->owner_node, &owner->controllers); |
92798b45 | 1333 | data->master = dev; |
2f5f44f2 | 1334 | |
aa759fd3 MS |
1335 | return 0; |
1336 | } | |
1337 | ||
0b9a3694 | 1338 | static const struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1339 | .domain_alloc = exynos_iommu_domain_alloc, |
1340 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1341 | .attach_dev = exynos_iommu_attach_device, |
1342 | .detach_dev = exynos_iommu_detach_device, | |
1343 | .map = exynos_iommu_map, | |
1344 | .unmap = exynos_iommu_unmap, | |
315786eb | 1345 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 | 1346 | .iova_to_phys = exynos_iommu_iova_to_phys, |
6c2ae7e2 | 1347 | .device_group = get_device_iommu_group, |
ba5fa6f6 BH |
1348 | .add_device = exynos_iommu_add_device, |
1349 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1350 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1351 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1352 | }; |
1353 | ||
1354 | static int __init exynos_iommu_init(void) | |
1355 | { | |
905c423b | 1356 | struct device_node *np; |
2a96536e KC |
1357 | int ret; |
1358 | ||
905c423b RM |
1359 | np = of_find_matching_node(NULL, sysmmu_of_match); |
1360 | if (!np) | |
1361 | return 0; | |
1362 | ||
1363 | of_node_put(np); | |
1364 | ||
734c3c73 CK |
1365 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1366 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1367 | if (!lv2table_kmem_cache) { | |
1368 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1369 | return -ENOMEM; | |
1370 | } | |
1371 | ||
2a96536e | 1372 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1373 | if (ret) { |
1374 | pr_err("%s: Failed to register driver\n", __func__); | |
1375 | goto err_reg_driver; | |
1376 | } | |
2a96536e | 1377 | |
66a7ed84 CK |
1378 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1379 | if (zero_lv2_table == NULL) { | |
1380 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1381 | __func__); | |
1382 | ret = -ENOMEM; | |
1383 | goto err_zero_lv2; | |
1384 | } | |
1385 | ||
734c3c73 CK |
1386 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1387 | if (ret) { | |
1388 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1389 | __func__); | |
1390 | goto err_set_iommu; | |
1391 | } | |
2a96536e | 1392 | |
734c3c73 CK |
1393 | return 0; |
1394 | err_set_iommu: | |
66a7ed84 CK |
1395 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1396 | err_zero_lv2: | |
734c3c73 CK |
1397 | platform_driver_unregister(&exynos_sysmmu_driver); |
1398 | err_reg_driver: | |
1399 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1400 | return ret; |
1401 | } | |
928055a0 | 1402 | core_initcall(exynos_iommu_init); |
8ed55c81 | 1403 | |
928055a0 | 1404 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", NULL); |