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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
2a96536e | 15 | #include <linux/clk.h> |
8ed55c81 | 16 | #include <linux/dma-mapping.h> |
2a96536e | 17 | #include <linux/err.h> |
312900c6 | 18 | #include <linux/io.h> |
2a96536e | 19 | #include <linux/iommu.h> |
312900c6 | 20 | #include <linux/interrupt.h> |
2a96536e | 21 | #include <linux/list.h> |
8ed55c81 MS |
22 | #include <linux/of.h> |
23 | #include <linux/of_iommu.h> | |
24 | #include <linux/of_platform.h> | |
312900c6 MS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
58c6f6a3 | 28 | #include <linux/dma-iommu.h> |
2a96536e | 29 | |
d09d78fc CK |
30 | typedef u32 sysmmu_iova_t; |
31 | typedef u32 sysmmu_pte_t; | |
32 | ||
f171abab | 33 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
34 | #define SECT_ORDER 20 |
35 | #define LPAGE_ORDER 16 | |
36 | #define SPAGE_ORDER 12 | |
37 | ||
38 | #define SECT_SIZE (1 << SECT_ORDER) | |
39 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
40 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
41 | ||
42 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
43 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
44 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
45 | ||
66a7ed84 CK |
46 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
47 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
48 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
49 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
50 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
51 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
52 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
53 | ||
54 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
55 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
56 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
57 | ||
d09d78fc CK |
58 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
59 | { | |
60 | return iova & (size - 1); | |
61 | } | |
62 | ||
2a96536e | 63 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 64 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 65 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 66 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 67 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 68 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
69 | |
70 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 71 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 72 | |
d09d78fc CK |
73 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
74 | { | |
75 | return iova >> SECT_ORDER; | |
76 | } | |
77 | ||
78 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
79 | { | |
80 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
81 | } | |
82 | ||
5e3435eb | 83 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 84 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
85 | |
86 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
87 | ||
88 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
89 | ||
90 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
91 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
92 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
93 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
94 | ||
95 | #define CTRL_ENABLE 0x5 | |
96 | #define CTRL_BLOCK 0x7 | |
97 | #define CTRL_DISABLE 0x0 | |
98 | ||
eeb5184b CK |
99 | #define CFG_LRU 0x1 |
100 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
101 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
102 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
103 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
104 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
105 | ||
2a96536e KC |
106 | #define REG_MMU_CTRL 0x000 |
107 | #define REG_MMU_CFG 0x004 | |
108 | #define REG_MMU_STATUS 0x008 | |
109 | #define REG_MMU_FLUSH 0x00C | |
110 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
111 | #define REG_PT_BASE_ADDR 0x014 | |
112 | #define REG_INT_STATUS 0x018 | |
113 | #define REG_INT_CLEAR 0x01C | |
114 | ||
115 | #define REG_PAGE_FAULT_ADDR 0x024 | |
116 | #define REG_AW_FAULT_ADDR 0x028 | |
117 | #define REG_AR_FAULT_ADDR 0x02C | |
118 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
119 | ||
120 | #define REG_MMU_VERSION 0x034 | |
121 | ||
eeb5184b CK |
122 | #define MMU_MAJ_VER(val) ((val) >> 7) |
123 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
124 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
125 | ||
126 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
127 | ||
2a96536e KC |
128 | #define REG_PB0_SADDR 0x04C |
129 | #define REG_PB0_EADDR 0x050 | |
130 | #define REG_PB1_SADDR 0x054 | |
131 | #define REG_PB1_EADDR 0x058 | |
132 | ||
6b21a5db CK |
133 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
134 | ||
5e3435eb | 135 | static struct device *dma_dev; |
734c3c73 | 136 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
137 | static sysmmu_pte_t *zero_lv2_table; |
138 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 139 | |
d09d78fc | 140 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
141 | { |
142 | return pgtable + lv1ent_offset(iova); | |
143 | } | |
144 | ||
d09d78fc | 145 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 146 | { |
d09d78fc | 147 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 148 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
149 | } |
150 | ||
d093fc7e MS |
151 | /* |
152 | * IOMMU fault information register | |
153 | */ | |
154 | struct sysmmu_fault_info { | |
155 | unsigned int bit; /* bit number in STATUS register */ | |
156 | unsigned short addr_reg; /* register to read VA fault address */ | |
157 | const char *name; /* human readable fault name */ | |
158 | unsigned int type; /* fault type for report_iommu_fault */ | |
2a96536e KC |
159 | }; |
160 | ||
d093fc7e MS |
161 | static const struct sysmmu_fault_info sysmmu_faults[] = { |
162 | { 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ }, | |
163 | { 1, REG_AR_FAULT_ADDR, "AR MULTI-HIT", IOMMU_FAULT_READ }, | |
164 | { 2, REG_AW_FAULT_ADDR, "AW MULTI-HIT", IOMMU_FAULT_WRITE }, | |
165 | { 3, REG_DEFAULT_SLAVE_ADDR, "BUS ERROR", IOMMU_FAULT_READ }, | |
166 | { 4, REG_AR_FAULT_ADDR, "AR SECURITY PROTECTION", IOMMU_FAULT_READ }, | |
167 | { 5, REG_AR_FAULT_ADDR, "AR ACCESS PROTECTION", IOMMU_FAULT_READ }, | |
168 | { 6, REG_AW_FAULT_ADDR, "AW SECURITY PROTECTION", IOMMU_FAULT_WRITE }, | |
169 | { 7, REG_AW_FAULT_ADDR, "AW ACCESS PROTECTION", IOMMU_FAULT_WRITE }, | |
2a96536e KC |
170 | }; |
171 | ||
2860af3c MS |
172 | /* |
173 | * This structure is attached to dev.archdata.iommu of the master device | |
174 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
175 | * which are bound to given master device. It is usually referenced by 'owner' | |
176 | * pointer. | |
177 | */ | |
6b21a5db | 178 | struct exynos_iommu_owner { |
1b092054 | 179 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
6b21a5db CK |
180 | }; |
181 | ||
2860af3c MS |
182 | /* |
183 | * This structure exynos specific generalization of struct iommu_domain. | |
184 | * It contains list of SYSMMU controllers from all master devices, which has | |
185 | * been attached to this domain and page tables of IO address space defined by | |
186 | * it. It is usually referenced by 'domain' pointer. | |
187 | */ | |
2a96536e | 188 | struct exynos_iommu_domain { |
2860af3c MS |
189 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
190 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
191 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
192 | spinlock_t lock; /* lock for modyfying list of clients */ | |
193 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 194 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
195 | }; |
196 | ||
2860af3c MS |
197 | /* |
198 | * This structure hold all data of a single SYSMMU controller, this includes | |
199 | * hw resources like registers and clocks, pointers and list nodes to connect | |
200 | * it to all other structures, internal state and parameters read from device | |
201 | * tree. It is usually referenced by 'data' pointer. | |
202 | */ | |
2a96536e | 203 | struct sysmmu_drvdata { |
2860af3c MS |
204 | struct device *sysmmu; /* SYSMMU controller device */ |
205 | struct device *master; /* master device (owner) */ | |
206 | void __iomem *sfrbase; /* our registers */ | |
207 | struct clk *clk; /* SYSMMU's clock */ | |
208 | struct clk *clk_master; /* master's device clock */ | |
209 | int activations; /* number of calls to sysmmu_enable */ | |
210 | spinlock_t lock; /* lock for modyfying state */ | |
211 | struct exynos_iommu_domain *domain; /* domain we belong to */ | |
212 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 213 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
214 | phys_addr_t pgtable; /* assigned page table structure */ |
215 | unsigned int version; /* our version */ | |
2a96536e KC |
216 | }; |
217 | ||
e1fd1eaa JR |
218 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
219 | { | |
220 | return container_of(dom, struct exynos_iommu_domain, domain); | |
221 | } | |
222 | ||
2a96536e KC |
223 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
224 | { | |
225 | /* return true if the System MMU was not active previously | |
226 | and it needs to be initialized */ | |
227 | return ++data->activations == 1; | |
228 | } | |
229 | ||
230 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
231 | { | |
232 | /* return true if the System MMU is needed to be disabled */ | |
233 | BUG_ON(data->activations < 1); | |
234 | return --data->activations == 0; | |
235 | } | |
236 | ||
237 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
238 | { | |
239 | return data->activations > 0; | |
240 | } | |
241 | ||
02cdc365 | 242 | static void sysmmu_unblock(struct sysmmu_drvdata *data) |
2a96536e | 243 | { |
02cdc365 | 244 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
2a96536e KC |
245 | } |
246 | ||
02cdc365 | 247 | static bool sysmmu_block(struct sysmmu_drvdata *data) |
2a96536e KC |
248 | { |
249 | int i = 120; | |
250 | ||
02cdc365 MS |
251 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
252 | while ((i > 0) && !(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1)) | |
2a96536e KC |
253 | --i; |
254 | ||
02cdc365 MS |
255 | if (!(__raw_readl(data->sfrbase + REG_MMU_STATUS) & 1)) { |
256 | sysmmu_unblock(data); | |
2a96536e KC |
257 | return false; |
258 | } | |
259 | ||
260 | return true; | |
261 | } | |
262 | ||
02cdc365 | 263 | static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *data) |
2a96536e | 264 | { |
02cdc365 | 265 | __raw_writel(0x1, data->sfrbase + REG_MMU_FLUSH); |
2a96536e KC |
266 | } |
267 | ||
02cdc365 | 268 | static void __sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
d09d78fc | 269 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 270 | { |
3ad6b7f3 | 271 | unsigned int i; |
365409db | 272 | |
3ad6b7f3 CK |
273 | for (i = 0; i < num_inv; i++) { |
274 | __raw_writel((iova & SPAGE_MASK) | 1, | |
02cdc365 | 275 | data->sfrbase + REG_MMU_FLUSH_ENTRY); |
3ad6b7f3 CK |
276 | iova += SPAGE_SIZE; |
277 | } | |
2a96536e KC |
278 | } |
279 | ||
02cdc365 | 280 | static void __sysmmu_set_ptbase(struct sysmmu_drvdata *data, phys_addr_t pgd) |
2a96536e | 281 | { |
02cdc365 | 282 | __raw_writel(pgd, data->sfrbase + REG_PT_BASE_ADDR); |
2a96536e | 283 | |
02cdc365 | 284 | __sysmmu_tlb_invalidate(data); |
2a96536e KC |
285 | } |
286 | ||
d093fc7e MS |
287 | static void show_fault_information(struct sysmmu_drvdata *data, |
288 | const struct sysmmu_fault_info *finfo, | |
289 | sysmmu_iova_t fault_addr) | |
2a96536e | 290 | { |
d09d78fc | 291 | sysmmu_pte_t *ent; |
2a96536e | 292 | |
d093fc7e MS |
293 | dev_err(data->sysmmu, "%s FAULT occurred at %#x (page table base: %pa)\n", |
294 | finfo->name, fault_addr, &data->pgtable); | |
295 | ent = section_entry(phys_to_virt(data->pgtable), fault_addr); | |
296 | dev_err(data->sysmmu, "\tLv1 entry: %#x\n", *ent); | |
2a96536e KC |
297 | if (lv1ent_page(ent)) { |
298 | ent = page_entry(ent, fault_addr); | |
d093fc7e | 299 | dev_err(data->sysmmu, "\t Lv2 entry: %#x\n", *ent); |
2a96536e | 300 | } |
2a96536e KC |
301 | } |
302 | ||
303 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
304 | { | |
f171abab | 305 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 306 | struct sysmmu_drvdata *data = dev_id; |
d093fc7e MS |
307 | const struct sysmmu_fault_info *finfo = sysmmu_faults; |
308 | int i, n = ARRAY_SIZE(sysmmu_faults); | |
309 | unsigned int itype; | |
310 | sysmmu_iova_t fault_addr = -1; | |
7222e8db | 311 | int ret = -ENOSYS; |
2a96536e | 312 | |
2a96536e KC |
313 | WARN_ON(!is_sysmmu_active(data)); |
314 | ||
9d4e7a24 CK |
315 | spin_lock(&data->lock); |
316 | ||
b398af21 | 317 | clk_enable(data->clk_master); |
9d4e7a24 | 318 | |
d093fc7e MS |
319 | itype = __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); |
320 | for (i = 0; i < n; i++, finfo++) | |
321 | if (finfo->bit == itype) | |
322 | break; | |
323 | /* unknown/unsupported fault */ | |
324 | BUG_ON(i == n); | |
325 | ||
326 | /* print debug message */ | |
327 | fault_addr = __raw_readl(data->sfrbase + finfo->addr_reg); | |
328 | show_fault_information(data, finfo, fault_addr); | |
2a96536e | 329 | |
d093fc7e MS |
330 | if (data->domain) |
331 | ret = report_iommu_fault(&data->domain->domain, | |
332 | data->master, fault_addr, finfo->type); | |
1fab7fa7 CK |
333 | /* fault is not recovered by fault handler */ |
334 | BUG_ON(ret != 0); | |
2a96536e | 335 | |
1fab7fa7 CK |
336 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
337 | ||
02cdc365 | 338 | sysmmu_unblock(data); |
2a96536e | 339 | |
b398af21 | 340 | clk_disable(data->clk_master); |
70605870 | 341 | |
9d4e7a24 | 342 | spin_unlock(&data->lock); |
2a96536e KC |
343 | |
344 | return IRQ_HANDLED; | |
345 | } | |
346 | ||
6b21a5db | 347 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 348 | { |
b398af21 | 349 | clk_enable(data->clk_master); |
70605870 | 350 | |
7222e8db | 351 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 352 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 353 | |
46c16d1e | 354 | clk_disable(data->clk); |
b398af21 | 355 | clk_disable(data->clk_master); |
2a96536e KC |
356 | } |
357 | ||
6b21a5db | 358 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 359 | { |
6b21a5db | 360 | bool disabled; |
2a96536e KC |
361 | unsigned long flags; |
362 | ||
9d4e7a24 | 363 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 364 | |
6b21a5db CK |
365 | disabled = set_sysmmu_inactive(data); |
366 | ||
367 | if (disabled) { | |
368 | data->pgtable = 0; | |
369 | data->domain = NULL; | |
370 | ||
371 | __sysmmu_disable_nocount(data); | |
2a96536e | 372 | |
6b21a5db CK |
373 | dev_dbg(data->sysmmu, "Disabled\n"); |
374 | } else { | |
375 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
376 | data->activations); | |
2a96536e KC |
377 | } |
378 | ||
6b21a5db CK |
379 | spin_unlock_irqrestore(&data->lock, flags); |
380 | ||
381 | return disabled; | |
382 | } | |
2a96536e | 383 | |
6b21a5db CK |
384 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
385 | { | |
83addecd MS |
386 | unsigned int cfg; |
387 | ||
388 | data->version = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); | |
389 | if (data->version <= MAKE_MMU_VER(3, 1)) | |
390 | cfg = CFG_LRU | CFG_QOS(15); | |
391 | else if (data->version <= MAKE_MMU_VER(3, 2)) | |
392 | cfg = CFG_LRU | CFG_QOS(15) | CFG_FLPDCACHE | CFG_SYSSEL; | |
393 | else | |
394 | cfg = CFG_QOS(15) | CFG_FLPDCACHE | CFG_ACGEN; | |
6b21a5db CK |
395 | |
396 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
397 | } | |
398 | ||
399 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
400 | { | |
b398af21 | 401 | clk_enable(data->clk_master); |
70605870 CK |
402 | clk_enable(data->clk); |
403 | ||
6b21a5db CK |
404 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
405 | ||
406 | __sysmmu_init_config(data); | |
407 | ||
02cdc365 | 408 | __sysmmu_set_ptbase(data, data->pgtable); |
2a96536e | 409 | |
7222e8db CK |
410 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
411 | ||
b398af21 | 412 | clk_disable(data->clk_master); |
6b21a5db | 413 | } |
70605870 | 414 | |
bfa00489 | 415 | static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable, |
a9133b99 | 416 | struct exynos_iommu_domain *domain) |
6b21a5db CK |
417 | { |
418 | int ret = 0; | |
419 | unsigned long flags; | |
420 | ||
421 | spin_lock_irqsave(&data->lock, flags); | |
422 | if (set_sysmmu_active(data)) { | |
423 | data->pgtable = pgtable; | |
a9133b99 | 424 | data->domain = domain; |
6b21a5db CK |
425 | |
426 | __sysmmu_enable_nocount(data); | |
427 | ||
428 | dev_dbg(data->sysmmu, "Enabled\n"); | |
429 | } else { | |
430 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
431 | ||
432 | dev_dbg(data->sysmmu, "already enabled\n"); | |
433 | } | |
434 | ||
435 | if (WARN_ON(ret < 0)) | |
436 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 437 | |
9d4e7a24 | 438 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
439 | |
440 | return ret; | |
441 | } | |
442 | ||
66a7ed84 CK |
443 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
444 | sysmmu_iova_t iova) | |
445 | { | |
512bd0c6 | 446 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
447 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
448 | } | |
449 | ||
469acebe | 450 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
451 | sysmmu_iova_t iova) |
452 | { | |
453 | unsigned long flags; | |
66a7ed84 | 454 | |
b398af21 | 455 | clk_enable(data->clk_master); |
66a7ed84 CK |
456 | |
457 | spin_lock_irqsave(&data->lock, flags); | |
458 | if (is_sysmmu_active(data)) | |
459 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
460 | spin_unlock_irqrestore(&data->lock, flags); | |
461 | ||
b398af21 | 462 | clk_disable(data->clk_master); |
66a7ed84 CK |
463 | } |
464 | ||
469acebe MS |
465 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
466 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
467 | { |
468 | unsigned long flags; | |
2a96536e | 469 | |
6b21a5db | 470 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 471 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 472 | unsigned int num_inv = 1; |
70605870 | 473 | |
b398af21 | 474 | clk_enable(data->clk_master); |
70605870 | 475 | |
3ad6b7f3 CK |
476 | /* |
477 | * L2TLB invalidation required | |
478 | * 4KB page: 1 invalidation | |
f171abab SK |
479 | * 64KB page: 16 invalidations |
480 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
481 | * because it is set-associative TLB |
482 | * with 8-way and 64 sets. | |
483 | * 1MB page can be cached in one of all sets. | |
484 | * 64KB page can be one of 16 consecutive sets. | |
485 | */ | |
512bd0c6 | 486 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
487 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
488 | ||
02cdc365 MS |
489 | if (sysmmu_block(data)) { |
490 | __sysmmu_tlb_invalidate_entry(data, iova, num_inv); | |
491 | sysmmu_unblock(data); | |
2a96536e | 492 | } |
b398af21 | 493 | clk_disable(data->clk_master); |
2a96536e | 494 | } else { |
469acebe MS |
495 | dev_dbg(data->master, |
496 | "disabled. Skipping TLB invalidation @ %#x\n", iova); | |
2a96536e | 497 | } |
9d4e7a24 | 498 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
499 | } |
500 | ||
6b21a5db | 501 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 502 | { |
46c16d1e | 503 | int irq, ret; |
7222e8db | 504 | struct device *dev = &pdev->dev; |
2a96536e | 505 | struct sysmmu_drvdata *data; |
7222e8db | 506 | struct resource *res; |
2a96536e | 507 | |
46c16d1e CK |
508 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
509 | if (!data) | |
510 | return -ENOMEM; | |
2a96536e | 511 | |
7222e8db | 512 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
513 | data->sfrbase = devm_ioremap_resource(dev, res); |
514 | if (IS_ERR(data->sfrbase)) | |
515 | return PTR_ERR(data->sfrbase); | |
2a96536e | 516 | |
46c16d1e CK |
517 | irq = platform_get_irq(pdev, 0); |
518 | if (irq <= 0) { | |
0bf4e54d | 519 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 520 | return irq; |
2a96536e KC |
521 | } |
522 | ||
46c16d1e | 523 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
524 | dev_name(dev), data); |
525 | if (ret) { | |
46c16d1e CK |
526 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
527 | return ret; | |
2a96536e KC |
528 | } |
529 | ||
46c16d1e CK |
530 | data->clk = devm_clk_get(dev, "sysmmu"); |
531 | if (IS_ERR(data->clk)) { | |
532 | dev_err(dev, "Failed to get clock!\n"); | |
533 | return PTR_ERR(data->clk); | |
534 | } else { | |
535 | ret = clk_prepare(data->clk); | |
536 | if (ret) { | |
537 | dev_err(dev, "Failed to prepare clk\n"); | |
538 | return ret; | |
539 | } | |
2a96536e KC |
540 | } |
541 | ||
70605870 CK |
542 | data->clk_master = devm_clk_get(dev, "master"); |
543 | if (!IS_ERR(data->clk_master)) { | |
544 | ret = clk_prepare(data->clk_master); | |
545 | if (ret) { | |
546 | clk_unprepare(data->clk); | |
547 | dev_err(dev, "Failed to prepare master's clk\n"); | |
548 | return ret; | |
549 | } | |
b398af21 MS |
550 | } else { |
551 | data->clk_master = NULL; | |
70605870 CK |
552 | } |
553 | ||
2a96536e | 554 | data->sysmmu = dev; |
9d4e7a24 | 555 | spin_lock_init(&data->lock); |
2a96536e | 556 | |
7222e8db CK |
557 | platform_set_drvdata(pdev, data); |
558 | ||
f4723ec1 | 559 | pm_runtime_enable(dev); |
2a96536e | 560 | |
2a96536e | 561 | return 0; |
2a96536e KC |
562 | } |
563 | ||
622015e4 MS |
564 | #ifdef CONFIG_PM_SLEEP |
565 | static int exynos_sysmmu_suspend(struct device *dev) | |
566 | { | |
567 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
568 | ||
569 | dev_dbg(dev, "suspend\n"); | |
570 | if (is_sysmmu_active(data)) { | |
571 | __sysmmu_disable_nocount(data); | |
572 | pm_runtime_put(dev); | |
573 | } | |
574 | return 0; | |
575 | } | |
576 | ||
577 | static int exynos_sysmmu_resume(struct device *dev) | |
578 | { | |
579 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
580 | ||
581 | dev_dbg(dev, "resume\n"); | |
582 | if (is_sysmmu_active(data)) { | |
583 | pm_runtime_get_sync(dev); | |
584 | __sysmmu_enable_nocount(data); | |
585 | } | |
586 | return 0; | |
587 | } | |
588 | #endif | |
589 | ||
590 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
591 | SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume) | |
592 | }; | |
593 | ||
6b21a5db CK |
594 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
595 | { .compatible = "samsung,exynos-sysmmu", }, | |
596 | { }, | |
597 | }; | |
598 | ||
599 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
600 | .probe = exynos_sysmmu_probe, | |
601 | .driver = { | |
2a96536e | 602 | .name = "exynos-sysmmu", |
6b21a5db | 603 | .of_match_table = sysmmu_of_match, |
622015e4 | 604 | .pm = &sysmmu_pm_ops, |
2a96536e KC |
605 | } |
606 | }; | |
607 | ||
5e3435eb | 608 | static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 609 | { |
5e3435eb MS |
610 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
611 | DMA_TO_DEVICE); | |
612 | *ent = val; | |
613 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), | |
614 | DMA_TO_DEVICE); | |
2a96536e KC |
615 | } |
616 | ||
e1fd1eaa | 617 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 618 | { |
bfa00489 | 619 | struct exynos_iommu_domain *domain; |
5e3435eb | 620 | dma_addr_t handle; |
66a7ed84 | 621 | int i; |
2a96536e | 622 | |
e1fd1eaa | 623 | |
bfa00489 MS |
624 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
625 | if (!domain) | |
e1fd1eaa | 626 | return NULL; |
2a96536e | 627 | |
58c6f6a3 MS |
628 | if (type == IOMMU_DOMAIN_DMA) { |
629 | if (iommu_get_dma_cookie(&domain->domain) != 0) | |
630 | goto err_pgtable; | |
631 | } else if (type != IOMMU_DOMAIN_UNMANAGED) { | |
632 | goto err_pgtable; | |
633 | } | |
634 | ||
bfa00489 MS |
635 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
636 | if (!domain->pgtable) | |
58c6f6a3 | 637 | goto err_dma_cookie; |
2a96536e | 638 | |
bfa00489 MS |
639 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
640 | if (!domain->lv2entcnt) | |
2a96536e KC |
641 | goto err_counter; |
642 | ||
f171abab | 643 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 644 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
645 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
646 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
647 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
648 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
649 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
650 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
651 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
652 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
653 | } |
654 | ||
5e3435eb MS |
655 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
656 | DMA_TO_DEVICE); | |
657 | /* For mapping page table entries we rely on dma == phys */ | |
658 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
2a96536e | 659 | |
bfa00489 MS |
660 | spin_lock_init(&domain->lock); |
661 | spin_lock_init(&domain->pgtablelock); | |
662 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 663 | |
bfa00489 MS |
664 | domain->domain.geometry.aperture_start = 0; |
665 | domain->domain.geometry.aperture_end = ~0UL; | |
666 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 667 | |
bfa00489 | 668 | return &domain->domain; |
2a96536e KC |
669 | |
670 | err_counter: | |
bfa00489 | 671 | free_pages((unsigned long)domain->pgtable, 2); |
58c6f6a3 MS |
672 | err_dma_cookie: |
673 | if (type == IOMMU_DOMAIN_DMA) | |
674 | iommu_put_dma_cookie(&domain->domain); | |
2a96536e | 675 | err_pgtable: |
bfa00489 | 676 | kfree(domain); |
e1fd1eaa | 677 | return NULL; |
2a96536e KC |
678 | } |
679 | ||
bfa00489 | 680 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 681 | { |
bfa00489 | 682 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 683 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
684 | unsigned long flags; |
685 | int i; | |
686 | ||
bfa00489 | 687 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 688 | |
bfa00489 | 689 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 690 | |
bfa00489 | 691 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
692 | if (__sysmmu_disable(data)) |
693 | data->master = NULL; | |
694 | list_del_init(&data->domain_node); | |
2a96536e KC |
695 | } |
696 | ||
bfa00489 | 697 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 698 | |
58c6f6a3 MS |
699 | if (iommu_domain->type == IOMMU_DOMAIN_DMA) |
700 | iommu_put_dma_cookie(iommu_domain); | |
701 | ||
5e3435eb MS |
702 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
703 | DMA_TO_DEVICE); | |
704 | ||
2a96536e | 705 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
706 | if (lv1ent_page(domain->pgtable + i)) { |
707 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
708 | ||
709 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
710 | DMA_TO_DEVICE); | |
734c3c73 | 711 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
712 | phys_to_virt(base)); |
713 | } | |
2a96536e | 714 | |
bfa00489 MS |
715 | free_pages((unsigned long)domain->pgtable, 2); |
716 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
717 | kfree(domain); | |
2a96536e KC |
718 | } |
719 | ||
bfa00489 | 720 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
721 | struct device *dev) |
722 | { | |
6b21a5db | 723 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 724 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 725 | struct sysmmu_drvdata *data; |
bfa00489 | 726 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 727 | unsigned long flags; |
469acebe | 728 | int ret = -ENODEV; |
2a96536e | 729 | |
469acebe MS |
730 | if (!has_sysmmu(dev)) |
731 | return -ENODEV; | |
2a96536e | 732 | |
1b092054 | 733 | list_for_each_entry(data, &owner->controllers, owner_node) { |
ce70ca56 | 734 | pm_runtime_get_sync(data->sysmmu); |
a9133b99 | 735 | ret = __sysmmu_enable(data, pagetable, domain); |
469acebe MS |
736 | if (ret >= 0) { |
737 | data->master = dev; | |
738 | ||
bfa00489 MS |
739 | spin_lock_irqsave(&domain->lock, flags); |
740 | list_add_tail(&data->domain_node, &domain->clients); | |
741 | spin_unlock_irqrestore(&domain->lock, flags); | |
469acebe MS |
742 | } |
743 | } | |
2a96536e KC |
744 | |
745 | if (ret < 0) { | |
7222e8db CK |
746 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
747 | __func__, &pagetable); | |
7222e8db | 748 | return ret; |
2a96536e KC |
749 | } |
750 | ||
7222e8db CK |
751 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
752 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
753 | ||
2a96536e KC |
754 | return ret; |
755 | } | |
756 | ||
bfa00489 | 757 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
758 | struct device *dev) |
759 | { | |
bfa00489 MS |
760 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
761 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
1b092054 | 762 | struct sysmmu_drvdata *data, *next; |
2a96536e | 763 | unsigned long flags; |
469acebe | 764 | bool found = false; |
2a96536e | 765 | |
469acebe MS |
766 | if (!has_sysmmu(dev)) |
767 | return; | |
2a96536e | 768 | |
bfa00489 | 769 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 770 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
771 | if (data->master == dev) { |
772 | if (__sysmmu_disable(data)) { | |
773 | data->master = NULL; | |
774 | list_del_init(&data->domain_node); | |
775 | } | |
ce70ca56 | 776 | pm_runtime_put(data->sysmmu); |
469acebe | 777 | found = true; |
2a96536e KC |
778 | } |
779 | } | |
bfa00489 | 780 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 781 | |
469acebe | 782 | if (found) |
7222e8db CK |
783 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
784 | __func__, &pagetable); | |
6b21a5db CK |
785 | else |
786 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
787 | } |
788 | ||
bfa00489 | 789 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 790 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 791 | { |
61128f08 | 792 | if (lv1ent_section(sent)) { |
d09d78fc | 793 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
794 | return ERR_PTR(-EADDRINUSE); |
795 | } | |
796 | ||
2a96536e | 797 | if (lv1ent_fault(sent)) { |
d09d78fc | 798 | sysmmu_pte_t *pent; |
66a7ed84 | 799 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 800 | |
734c3c73 | 801 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 802 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 803 | if (!pent) |
61128f08 | 804 | return ERR_PTR(-ENOMEM); |
2a96536e | 805 | |
5e3435eb | 806 | update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 807 | kmemleak_ignore(pent); |
2a96536e | 808 | *pgcounter = NUM_LV2ENTRIES; |
5e3435eb | 809 | dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE); |
66a7ed84 CK |
810 | |
811 | /* | |
f171abab SK |
812 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
813 | * FLPD cache may cache the address of zero_l2_table. This | |
814 | * function replaces the zero_l2_table with new L2 page table | |
815 | * to write valid mappings. | |
66a7ed84 | 816 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
817 | * cache may still cache zero_l2_table for the valid area |
818 | * instead of new L2 page table that has the mapping | |
819 | * information of the valid area. | |
66a7ed84 CK |
820 | * Thus any replacement of zero_l2_table with other valid L2 |
821 | * page table must involve FLPD cache invalidation for System | |
822 | * MMU v3.3. | |
823 | * FLPD cache invalidation is performed with TLB invalidation | |
824 | * by VPN without blocking. It is safe to invalidate TLB without | |
825 | * blocking because the target address of TLB invalidation is | |
826 | * not currently mapped. | |
827 | */ | |
828 | if (need_flush_flpd_cache) { | |
469acebe | 829 | struct sysmmu_drvdata *data; |
365409db | 830 | |
bfa00489 MS |
831 | spin_lock(&domain->lock); |
832 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 833 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 834 | spin_unlock(&domain->lock); |
66a7ed84 | 835 | } |
2a96536e KC |
836 | } |
837 | ||
838 | return page_entry(sent, iova); | |
839 | } | |
840 | ||
bfa00489 | 841 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 842 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 843 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 844 | { |
61128f08 | 845 | if (lv1ent_section(sent)) { |
d09d78fc | 846 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 847 | iova); |
2a96536e | 848 | return -EADDRINUSE; |
61128f08 | 849 | } |
2a96536e KC |
850 | |
851 | if (lv1ent_page(sent)) { | |
61128f08 | 852 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 853 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 854 | iova); |
2a96536e | 855 | return -EADDRINUSE; |
61128f08 | 856 | } |
2a96536e | 857 | |
734c3c73 | 858 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
859 | *pgcnt = 0; |
860 | } | |
861 | ||
5e3435eb | 862 | update_pte(sent, mk_lv1ent_sect(paddr)); |
2a96536e | 863 | |
bfa00489 | 864 | spin_lock(&domain->lock); |
66a7ed84 | 865 | if (lv1ent_page_zero(sent)) { |
469acebe | 866 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
867 | /* |
868 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
869 | * entry by speculative prefetch of SLPD which has no mapping. | |
870 | */ | |
bfa00489 | 871 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 872 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 873 | } |
bfa00489 | 874 | spin_unlock(&domain->lock); |
66a7ed84 | 875 | |
2a96536e KC |
876 | return 0; |
877 | } | |
878 | ||
d09d78fc | 879 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
880 | short *pgcnt) |
881 | { | |
882 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 883 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
884 | return -EADDRINUSE; |
885 | ||
5e3435eb | 886 | update_pte(pent, mk_lv2ent_spage(paddr)); |
2a96536e KC |
887 | *pgcnt -= 1; |
888 | } else { /* size == LPAGE_SIZE */ | |
889 | int i; | |
5e3435eb | 890 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 891 | |
5e3435eb MS |
892 | dma_sync_single_for_cpu(dma_dev, pent_base, |
893 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
894 | DMA_TO_DEVICE); | |
2a96536e | 895 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 896 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
897 | if (i > 0) |
898 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
899 | return -EADDRINUSE; |
900 | } | |
901 | ||
902 | *pent = mk_lv2ent_lpage(paddr); | |
903 | } | |
5e3435eb MS |
904 | dma_sync_single_for_device(dma_dev, pent_base, |
905 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
906 | DMA_TO_DEVICE); | |
2a96536e KC |
907 | *pgcnt -= SPAGES_PER_LPAGE; |
908 | } | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
66a7ed84 CK |
913 | /* |
914 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
915 | * | |
f171abab | 916 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 917 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
918 | * However, the logic has a bug that while caching faulty page table entries, |
919 | * System MMU reports page fault if the cached fault entry is hit even though | |
920 | * the fault entry is updated to a valid entry after the entry is cached. | |
921 | * To prevent caching faulty page table entries which may be updated to valid | |
922 | * entries later, the virtual memory manager should care about the workaround | |
923 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
924 | * |
925 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 926 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 927 | * |
f171abab | 928 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
929 | * the following sizes for System MMU v3.1 and v3.2. |
930 | * System MMU v3.1: 128KiB | |
931 | * System MMU v3.2: 256KiB | |
932 | * | |
933 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
934 | * more workarounds. |
935 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
936 | * than or equal to 128KiB. | |
66a7ed84 CK |
937 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
938 | */ | |
bfa00489 MS |
939 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
940 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
941 | int prot) | |
2a96536e | 942 | { |
bfa00489 | 943 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
944 | sysmmu_pte_t *entry; |
945 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
946 | unsigned long flags; |
947 | int ret = -ENOMEM; | |
948 | ||
bfa00489 | 949 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 950 | |
bfa00489 | 951 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 952 | |
bfa00489 | 953 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
954 | |
955 | if (size == SECT_SIZE) { | |
bfa00489 MS |
956 | ret = lv1set_section(domain, entry, iova, paddr, |
957 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 958 | } else { |
d09d78fc | 959 | sysmmu_pte_t *pent; |
2a96536e | 960 | |
bfa00489 MS |
961 | pent = alloc_lv2entry(domain, entry, iova, |
962 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 963 | |
61128f08 CK |
964 | if (IS_ERR(pent)) |
965 | ret = PTR_ERR(pent); | |
2a96536e KC |
966 | else |
967 | ret = lv2set_page(pent, paddr, size, | |
bfa00489 | 968 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
969 | } |
970 | ||
61128f08 | 971 | if (ret) |
0bf4e54d CK |
972 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
973 | __func__, ret, size, iova); | |
2a96536e | 974 | |
bfa00489 | 975 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
976 | |
977 | return ret; | |
978 | } | |
979 | ||
bfa00489 MS |
980 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
981 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 982 | { |
469acebe | 983 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
984 | unsigned long flags; |
985 | ||
bfa00489 | 986 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 987 | |
bfa00489 | 988 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 989 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 990 | |
bfa00489 | 991 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
992 | } |
993 | ||
bfa00489 MS |
994 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
995 | unsigned long l_iova, size_t size) | |
2a96536e | 996 | { |
bfa00489 | 997 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
998 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
999 | sysmmu_pte_t *ent; | |
61128f08 | 1000 | size_t err_pgsize; |
d09d78fc | 1001 | unsigned long flags; |
2a96536e | 1002 | |
bfa00489 | 1003 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1004 | |
bfa00489 | 1005 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1006 | |
bfa00489 | 1007 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1008 | |
1009 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1010 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1011 | err_pgsize = SECT_SIZE; |
1012 | goto err; | |
1013 | } | |
2a96536e | 1014 | |
f171abab | 1015 | /* workaround for h/w bug in System MMU v3.3 */ |
5e3435eb | 1016 | update_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1017 | size = SECT_SIZE; |
1018 | goto done; | |
1019 | } | |
1020 | ||
1021 | if (unlikely(lv1ent_fault(ent))) { | |
1022 | if (size > SECT_SIZE) | |
1023 | size = SECT_SIZE; | |
1024 | goto done; | |
1025 | } | |
1026 | ||
1027 | /* lv1ent_page(sent) == true here */ | |
1028 | ||
1029 | ent = page_entry(ent, iova); | |
1030 | ||
1031 | if (unlikely(lv2ent_fault(ent))) { | |
1032 | size = SPAGE_SIZE; | |
1033 | goto done; | |
1034 | } | |
1035 | ||
1036 | if (lv2ent_small(ent)) { | |
5e3435eb | 1037 | update_pte(ent, 0); |
2a96536e | 1038 | size = SPAGE_SIZE; |
bfa00489 | 1039 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1040 | goto done; |
1041 | } | |
1042 | ||
1043 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1044 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1045 | err_pgsize = LPAGE_SIZE; |
1046 | goto err; | |
1047 | } | |
2a96536e | 1048 | |
5e3435eb MS |
1049 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1050 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1051 | DMA_TO_DEVICE); | |
2a96536e | 1052 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1053 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1054 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1055 | DMA_TO_DEVICE); | |
2a96536e | 1056 | size = LPAGE_SIZE; |
bfa00489 | 1057 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1058 | done: |
bfa00489 | 1059 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1060 | |
bfa00489 | 1061 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1062 | |
2a96536e | 1063 | return size; |
61128f08 | 1064 | err: |
bfa00489 | 1065 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1066 | |
0bf4e54d CK |
1067 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1068 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1069 | |
1070 | return 0; | |
2a96536e KC |
1071 | } |
1072 | ||
bfa00489 | 1073 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1074 | dma_addr_t iova) |
2a96536e | 1075 | { |
bfa00489 | 1076 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1077 | sysmmu_pte_t *entry; |
2a96536e KC |
1078 | unsigned long flags; |
1079 | phys_addr_t phys = 0; | |
1080 | ||
bfa00489 | 1081 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1082 | |
bfa00489 | 1083 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1084 | |
1085 | if (lv1ent_section(entry)) { | |
1086 | phys = section_phys(entry) + section_offs(iova); | |
1087 | } else if (lv1ent_page(entry)) { | |
1088 | entry = page_entry(entry, iova); | |
1089 | ||
1090 | if (lv2ent_large(entry)) | |
1091 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1092 | else if (lv2ent_small(entry)) | |
1093 | phys = spage_phys(entry) + spage_offs(iova); | |
1094 | } | |
1095 | ||
bfa00489 | 1096 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1097 | |
1098 | return phys; | |
1099 | } | |
1100 | ||
6c2ae7e2 MS |
1101 | static struct iommu_group *get_device_iommu_group(struct device *dev) |
1102 | { | |
1103 | struct iommu_group *group; | |
1104 | ||
1105 | group = iommu_group_get(dev); | |
1106 | if (!group) | |
1107 | group = iommu_group_alloc(); | |
1108 | ||
1109 | return group; | |
1110 | } | |
1111 | ||
bf4a1c92 AM |
1112 | static int exynos_iommu_add_device(struct device *dev) |
1113 | { | |
1114 | struct iommu_group *group; | |
bf4a1c92 | 1115 | |
06801db0 MS |
1116 | if (!has_sysmmu(dev)) |
1117 | return -ENODEV; | |
1118 | ||
6c2ae7e2 | 1119 | group = iommu_group_get_for_dev(dev); |
bf4a1c92 | 1120 | |
6c2ae7e2 MS |
1121 | if (IS_ERR(group)) |
1122 | return PTR_ERR(group); | |
bf4a1c92 | 1123 | |
bf4a1c92 AM |
1124 | iommu_group_put(group); |
1125 | ||
6c2ae7e2 | 1126 | return 0; |
bf4a1c92 AM |
1127 | } |
1128 | ||
1129 | static void exynos_iommu_remove_device(struct device *dev) | |
1130 | { | |
06801db0 MS |
1131 | if (!has_sysmmu(dev)) |
1132 | return; | |
1133 | ||
bf4a1c92 AM |
1134 | iommu_group_remove_device(dev); |
1135 | } | |
1136 | ||
aa759fd3 MS |
1137 | static int exynos_iommu_of_xlate(struct device *dev, |
1138 | struct of_phandle_args *spec) | |
1139 | { | |
1140 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1141 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
1142 | struct sysmmu_drvdata *data; | |
1143 | ||
1144 | if (!sysmmu) | |
1145 | return -ENODEV; | |
1146 | ||
1147 | data = platform_get_drvdata(sysmmu); | |
1148 | if (!data) | |
1149 | return -ENODEV; | |
1150 | ||
1151 | if (!owner) { | |
1152 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1153 | if (!owner) | |
1154 | return -ENOMEM; | |
1155 | ||
1156 | INIT_LIST_HEAD(&owner->controllers); | |
1157 | dev->archdata.iommu = owner; | |
1158 | } | |
1159 | ||
1160 | list_add_tail(&data->owner_node, &owner->controllers); | |
1161 | return 0; | |
1162 | } | |
1163 | ||
8ed55c81 | 1164 | static struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1165 | .domain_alloc = exynos_iommu_domain_alloc, |
1166 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1167 | .attach_dev = exynos_iommu_attach_device, |
1168 | .detach_dev = exynos_iommu_detach_device, | |
1169 | .map = exynos_iommu_map, | |
1170 | .unmap = exynos_iommu_unmap, | |
315786eb | 1171 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 | 1172 | .iova_to_phys = exynos_iommu_iova_to_phys, |
6c2ae7e2 | 1173 | .device_group = get_device_iommu_group, |
ba5fa6f6 BH |
1174 | .add_device = exynos_iommu_add_device, |
1175 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1176 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1177 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1178 | }; |
1179 | ||
8ed55c81 MS |
1180 | static bool init_done; |
1181 | ||
2a96536e KC |
1182 | static int __init exynos_iommu_init(void) |
1183 | { | |
1184 | int ret; | |
1185 | ||
734c3c73 CK |
1186 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1187 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1188 | if (!lv2table_kmem_cache) { | |
1189 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1190 | return -ENOMEM; | |
1191 | } | |
1192 | ||
2a96536e | 1193 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1194 | if (ret) { |
1195 | pr_err("%s: Failed to register driver\n", __func__); | |
1196 | goto err_reg_driver; | |
1197 | } | |
2a96536e | 1198 | |
66a7ed84 CK |
1199 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1200 | if (zero_lv2_table == NULL) { | |
1201 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1202 | __func__); | |
1203 | ret = -ENOMEM; | |
1204 | goto err_zero_lv2; | |
1205 | } | |
1206 | ||
734c3c73 CK |
1207 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1208 | if (ret) { | |
1209 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1210 | __func__); | |
1211 | goto err_set_iommu; | |
1212 | } | |
2a96536e | 1213 | |
8ed55c81 MS |
1214 | init_done = true; |
1215 | ||
734c3c73 CK |
1216 | return 0; |
1217 | err_set_iommu: | |
66a7ed84 CK |
1218 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1219 | err_zero_lv2: | |
734c3c73 CK |
1220 | platform_driver_unregister(&exynos_sysmmu_driver); |
1221 | err_reg_driver: | |
1222 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1223 | return ret; |
1224 | } | |
8ed55c81 MS |
1225 | |
1226 | static int __init exynos_iommu_of_setup(struct device_node *np) | |
1227 | { | |
1228 | struct platform_device *pdev; | |
1229 | ||
1230 | if (!init_done) | |
1231 | exynos_iommu_init(); | |
1232 | ||
1233 | pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); | |
1234 | if (IS_ERR(pdev)) | |
1235 | return PTR_ERR(pdev); | |
1236 | ||
5e3435eb MS |
1237 | /* |
1238 | * use the first registered sysmmu device for performing | |
1239 | * dma mapping operations on iommu page tables (cpu cache flush) | |
1240 | */ | |
1241 | if (!dma_dev) | |
1242 | dma_dev = &pdev->dev; | |
1243 | ||
8ed55c81 MS |
1244 | of_iommu_set_ops(np, &exynos_iommu_ops); |
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", | |
1249 | exynos_iommu_of_setup); |