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2a96536e KC |
1 | /* linux/drivers/iommu/exynos_iommu.c |
2 | * | |
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | |
4 | * http://www.samsung.com | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #ifdef CONFIG_EXYNOS_IOMMU_DEBUG | |
12 | #define DEBUG | |
13 | #endif | |
14 | ||
2a96536e | 15 | #include <linux/clk.h> |
8ed55c81 | 16 | #include <linux/dma-mapping.h> |
2a96536e | 17 | #include <linux/err.h> |
312900c6 | 18 | #include <linux/io.h> |
2a96536e | 19 | #include <linux/iommu.h> |
312900c6 | 20 | #include <linux/interrupt.h> |
2a96536e | 21 | #include <linux/list.h> |
8ed55c81 MS |
22 | #include <linux/of.h> |
23 | #include <linux/of_iommu.h> | |
24 | #include <linux/of_platform.h> | |
312900c6 MS |
25 | #include <linux/platform_device.h> |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/slab.h> | |
58c6f6a3 | 28 | #include <linux/dma-iommu.h> |
2a96536e | 29 | |
d09d78fc CK |
30 | typedef u32 sysmmu_iova_t; |
31 | typedef u32 sysmmu_pte_t; | |
32 | ||
f171abab | 33 | /* We do not consider super section mapping (16MB) */ |
2a96536e KC |
34 | #define SECT_ORDER 20 |
35 | #define LPAGE_ORDER 16 | |
36 | #define SPAGE_ORDER 12 | |
37 | ||
38 | #define SECT_SIZE (1 << SECT_ORDER) | |
39 | #define LPAGE_SIZE (1 << LPAGE_ORDER) | |
40 | #define SPAGE_SIZE (1 << SPAGE_ORDER) | |
41 | ||
42 | #define SECT_MASK (~(SECT_SIZE - 1)) | |
43 | #define LPAGE_MASK (~(LPAGE_SIZE - 1)) | |
44 | #define SPAGE_MASK (~(SPAGE_SIZE - 1)) | |
45 | ||
66a7ed84 CK |
46 | #define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \ |
47 | ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3)) | |
48 | #define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK) | |
49 | #define lv1ent_page_zero(sent) ((*(sent) & 3) == 1) | |
50 | #define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \ | |
51 | ((*(sent) & 3) == 1)) | |
2a96536e KC |
52 | #define lv1ent_section(sent) ((*(sent) & 3) == 2) |
53 | ||
54 | #define lv2ent_fault(pent) ((*(pent) & 3) == 0) | |
55 | #define lv2ent_small(pent) ((*(pent) & 2) == 2) | |
56 | #define lv2ent_large(pent) ((*(pent) & 3) == 1) | |
57 | ||
d09d78fc CK |
58 | static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size) |
59 | { | |
60 | return iova & (size - 1); | |
61 | } | |
62 | ||
2a96536e | 63 | #define section_phys(sent) (*(sent) & SECT_MASK) |
d09d78fc | 64 | #define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE) |
2a96536e | 65 | #define lpage_phys(pent) (*(pent) & LPAGE_MASK) |
d09d78fc | 66 | #define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE) |
2a96536e | 67 | #define spage_phys(pent) (*(pent) & SPAGE_MASK) |
d09d78fc | 68 | #define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE) |
2a96536e KC |
69 | |
70 | #define NUM_LV1ENTRIES 4096 | |
d09d78fc | 71 | #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) |
2a96536e | 72 | |
d09d78fc CK |
73 | static u32 lv1ent_offset(sysmmu_iova_t iova) |
74 | { | |
75 | return iova >> SECT_ORDER; | |
76 | } | |
77 | ||
78 | static u32 lv2ent_offset(sysmmu_iova_t iova) | |
79 | { | |
80 | return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1); | |
81 | } | |
82 | ||
5e3435eb | 83 | #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) |
d09d78fc | 84 | #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) |
2a96536e KC |
85 | |
86 | #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) | |
87 | ||
88 | #define lv2table_base(sent) (*(sent) & 0xFFFFFC00) | |
89 | ||
90 | #define mk_lv1ent_sect(pa) ((pa) | 2) | |
91 | #define mk_lv1ent_page(pa) ((pa) | 1) | |
92 | #define mk_lv2ent_lpage(pa) ((pa) | 1) | |
93 | #define mk_lv2ent_spage(pa) ((pa) | 2) | |
94 | ||
95 | #define CTRL_ENABLE 0x5 | |
96 | #define CTRL_BLOCK 0x7 | |
97 | #define CTRL_DISABLE 0x0 | |
98 | ||
eeb5184b CK |
99 | #define CFG_LRU 0x1 |
100 | #define CFG_QOS(n) ((n & 0xF) << 7) | |
101 | #define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */ | |
102 | #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */ | |
103 | #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */ | |
104 | #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */ | |
105 | ||
2a96536e KC |
106 | #define REG_MMU_CTRL 0x000 |
107 | #define REG_MMU_CFG 0x004 | |
108 | #define REG_MMU_STATUS 0x008 | |
109 | #define REG_MMU_FLUSH 0x00C | |
110 | #define REG_MMU_FLUSH_ENTRY 0x010 | |
111 | #define REG_PT_BASE_ADDR 0x014 | |
112 | #define REG_INT_STATUS 0x018 | |
113 | #define REG_INT_CLEAR 0x01C | |
114 | ||
115 | #define REG_PAGE_FAULT_ADDR 0x024 | |
116 | #define REG_AW_FAULT_ADDR 0x028 | |
117 | #define REG_AR_FAULT_ADDR 0x02C | |
118 | #define REG_DEFAULT_SLAVE_ADDR 0x030 | |
119 | ||
120 | #define REG_MMU_VERSION 0x034 | |
121 | ||
eeb5184b CK |
122 | #define MMU_MAJ_VER(val) ((val) >> 7) |
123 | #define MMU_MIN_VER(val) ((val) & 0x7F) | |
124 | #define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */ | |
125 | ||
126 | #define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F)) | |
127 | ||
2a96536e KC |
128 | #define REG_PB0_SADDR 0x04C |
129 | #define REG_PB0_EADDR 0x050 | |
130 | #define REG_PB1_SADDR 0x054 | |
131 | #define REG_PB1_EADDR 0x058 | |
132 | ||
6b21a5db CK |
133 | #define has_sysmmu(dev) (dev->archdata.iommu != NULL) |
134 | ||
5e3435eb | 135 | static struct device *dma_dev; |
734c3c73 | 136 | static struct kmem_cache *lv2table_kmem_cache; |
66a7ed84 CK |
137 | static sysmmu_pte_t *zero_lv2_table; |
138 | #define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table)) | |
734c3c73 | 139 | |
d09d78fc | 140 | static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova) |
2a96536e KC |
141 | { |
142 | return pgtable + lv1ent_offset(iova); | |
143 | } | |
144 | ||
d09d78fc | 145 | static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) |
2a96536e | 146 | { |
d09d78fc | 147 | return (sysmmu_pte_t *)phys_to_virt( |
7222e8db | 148 | lv2table_base(sent)) + lv2ent_offset(iova); |
2a96536e KC |
149 | } |
150 | ||
151 | enum exynos_sysmmu_inttype { | |
152 | SYSMMU_PAGEFAULT, | |
153 | SYSMMU_AR_MULTIHIT, | |
154 | SYSMMU_AW_MULTIHIT, | |
155 | SYSMMU_BUSERROR, | |
156 | SYSMMU_AR_SECURITY, | |
157 | SYSMMU_AR_ACCESS, | |
158 | SYSMMU_AW_SECURITY, | |
159 | SYSMMU_AW_PROTECTION, /* 7 */ | |
160 | SYSMMU_FAULT_UNKNOWN, | |
161 | SYSMMU_FAULTS_NUM | |
162 | }; | |
163 | ||
2a96536e KC |
164 | static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = { |
165 | REG_PAGE_FAULT_ADDR, | |
166 | REG_AR_FAULT_ADDR, | |
167 | REG_AW_FAULT_ADDR, | |
168 | REG_DEFAULT_SLAVE_ADDR, | |
169 | REG_AR_FAULT_ADDR, | |
170 | REG_AR_FAULT_ADDR, | |
171 | REG_AW_FAULT_ADDR, | |
172 | REG_AW_FAULT_ADDR | |
173 | }; | |
174 | ||
175 | static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { | |
176 | "PAGE FAULT", | |
177 | "AR MULTI-HIT FAULT", | |
178 | "AW MULTI-HIT FAULT", | |
179 | "BUS ERROR", | |
180 | "AR SECURITY PROTECTION FAULT", | |
181 | "AR ACCESS PROTECTION FAULT", | |
182 | "AW SECURITY PROTECTION FAULT", | |
183 | "AW ACCESS PROTECTION FAULT", | |
184 | "UNKNOWN FAULT" | |
185 | }; | |
186 | ||
2860af3c MS |
187 | /* |
188 | * This structure is attached to dev.archdata.iommu of the master device | |
189 | * on device add, contains a list of SYSMMU controllers defined by device tree, | |
190 | * which are bound to given master device. It is usually referenced by 'owner' | |
191 | * pointer. | |
192 | */ | |
6b21a5db | 193 | struct exynos_iommu_owner { |
1b092054 | 194 | struct list_head controllers; /* list of sysmmu_drvdata.owner_node */ |
6b21a5db CK |
195 | }; |
196 | ||
2860af3c MS |
197 | /* |
198 | * This structure exynos specific generalization of struct iommu_domain. | |
199 | * It contains list of SYSMMU controllers from all master devices, which has | |
200 | * been attached to this domain and page tables of IO address space defined by | |
201 | * it. It is usually referenced by 'domain' pointer. | |
202 | */ | |
2a96536e | 203 | struct exynos_iommu_domain { |
2860af3c MS |
204 | struct list_head clients; /* list of sysmmu_drvdata.domain_node */ |
205 | sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ | |
206 | short *lv2entcnt; /* free lv2 entry counter for each section */ | |
207 | spinlock_t lock; /* lock for modyfying list of clients */ | |
208 | spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */ | |
e1fd1eaa | 209 | struct iommu_domain domain; /* generic domain data structure */ |
2a96536e KC |
210 | }; |
211 | ||
2860af3c MS |
212 | /* |
213 | * This structure hold all data of a single SYSMMU controller, this includes | |
214 | * hw resources like registers and clocks, pointers and list nodes to connect | |
215 | * it to all other structures, internal state and parameters read from device | |
216 | * tree. It is usually referenced by 'data' pointer. | |
217 | */ | |
2a96536e | 218 | struct sysmmu_drvdata { |
2860af3c MS |
219 | struct device *sysmmu; /* SYSMMU controller device */ |
220 | struct device *master; /* master device (owner) */ | |
221 | void __iomem *sfrbase; /* our registers */ | |
222 | struct clk *clk; /* SYSMMU's clock */ | |
223 | struct clk *clk_master; /* master's device clock */ | |
224 | int activations; /* number of calls to sysmmu_enable */ | |
225 | spinlock_t lock; /* lock for modyfying state */ | |
226 | struct exynos_iommu_domain *domain; /* domain we belong to */ | |
227 | struct list_head domain_node; /* node for domain clients list */ | |
1b092054 | 228 | struct list_head owner_node; /* node for owner controllers list */ |
2860af3c MS |
229 | phys_addr_t pgtable; /* assigned page table structure */ |
230 | unsigned int version; /* our version */ | |
2a96536e KC |
231 | }; |
232 | ||
e1fd1eaa JR |
233 | static struct exynos_iommu_domain *to_exynos_domain(struct iommu_domain *dom) |
234 | { | |
235 | return container_of(dom, struct exynos_iommu_domain, domain); | |
236 | } | |
237 | ||
2a96536e KC |
238 | static bool set_sysmmu_active(struct sysmmu_drvdata *data) |
239 | { | |
240 | /* return true if the System MMU was not active previously | |
241 | and it needs to be initialized */ | |
242 | return ++data->activations == 1; | |
243 | } | |
244 | ||
245 | static bool set_sysmmu_inactive(struct sysmmu_drvdata *data) | |
246 | { | |
247 | /* return true if the System MMU is needed to be disabled */ | |
248 | BUG_ON(data->activations < 1); | |
249 | return --data->activations == 0; | |
250 | } | |
251 | ||
252 | static bool is_sysmmu_active(struct sysmmu_drvdata *data) | |
253 | { | |
254 | return data->activations > 0; | |
255 | } | |
256 | ||
257 | static void sysmmu_unblock(void __iomem *sfrbase) | |
258 | { | |
259 | __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); | |
260 | } | |
261 | ||
262 | static bool sysmmu_block(void __iomem *sfrbase) | |
263 | { | |
264 | int i = 120; | |
265 | ||
266 | __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); | |
267 | while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) | |
268 | --i; | |
269 | ||
270 | if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { | |
271 | sysmmu_unblock(sfrbase); | |
272 | return false; | |
273 | } | |
274 | ||
275 | return true; | |
276 | } | |
277 | ||
278 | static void __sysmmu_tlb_invalidate(void __iomem *sfrbase) | |
279 | { | |
280 | __raw_writel(0x1, sfrbase + REG_MMU_FLUSH); | |
281 | } | |
282 | ||
283 | static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, | |
d09d78fc | 284 | sysmmu_iova_t iova, unsigned int num_inv) |
2a96536e | 285 | { |
3ad6b7f3 | 286 | unsigned int i; |
365409db | 287 | |
3ad6b7f3 CK |
288 | for (i = 0; i < num_inv; i++) { |
289 | __raw_writel((iova & SPAGE_MASK) | 1, | |
290 | sfrbase + REG_MMU_FLUSH_ENTRY); | |
291 | iova += SPAGE_SIZE; | |
292 | } | |
2a96536e KC |
293 | } |
294 | ||
295 | static void __sysmmu_set_ptbase(void __iomem *sfrbase, | |
d09d78fc | 296 | phys_addr_t pgd) |
2a96536e | 297 | { |
2a96536e KC |
298 | __raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR); |
299 | ||
300 | __sysmmu_tlb_invalidate(sfrbase); | |
301 | } | |
302 | ||
1fab7fa7 CK |
303 | static void show_fault_information(const char *name, |
304 | enum exynos_sysmmu_inttype itype, | |
d09d78fc | 305 | phys_addr_t pgtable_base, sysmmu_iova_t fault_addr) |
2a96536e | 306 | { |
d09d78fc | 307 | sysmmu_pte_t *ent; |
2a96536e KC |
308 | |
309 | if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT)) | |
310 | itype = SYSMMU_FAULT_UNKNOWN; | |
311 | ||
d09d78fc | 312 | pr_err("%s occurred at %#x by %s(Page table base: %pa)\n", |
1fab7fa7 | 313 | sysmmu_fault_name[itype], fault_addr, name, &pgtable_base); |
2a96536e | 314 | |
7222e8db | 315 | ent = section_entry(phys_to_virt(pgtable_base), fault_addr); |
d09d78fc | 316 | pr_err("\tLv1 entry: %#x\n", *ent); |
2a96536e KC |
317 | |
318 | if (lv1ent_page(ent)) { | |
319 | ent = page_entry(ent, fault_addr); | |
d09d78fc | 320 | pr_err("\t Lv2 entry: %#x\n", *ent); |
2a96536e | 321 | } |
2a96536e KC |
322 | } |
323 | ||
324 | static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) | |
325 | { | |
f171abab | 326 | /* SYSMMU is in blocked state when interrupt occurred. */ |
2a96536e | 327 | struct sysmmu_drvdata *data = dev_id; |
2a96536e | 328 | enum exynos_sysmmu_inttype itype; |
d09d78fc | 329 | sysmmu_iova_t addr = -1; |
7222e8db | 330 | int ret = -ENOSYS; |
2a96536e | 331 | |
2a96536e KC |
332 | WARN_ON(!is_sysmmu_active(data)); |
333 | ||
9d4e7a24 CK |
334 | spin_lock(&data->lock); |
335 | ||
b398af21 | 336 | clk_enable(data->clk_master); |
9d4e7a24 | 337 | |
7222e8db CK |
338 | itype = (enum exynos_sysmmu_inttype) |
339 | __ffs(__raw_readl(data->sfrbase + REG_INT_STATUS)); | |
340 | if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN)))) | |
2a96536e | 341 | itype = SYSMMU_FAULT_UNKNOWN; |
7222e8db CK |
342 | else |
343 | addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]); | |
2a96536e | 344 | |
1fab7fa7 CK |
345 | if (itype == SYSMMU_FAULT_UNKNOWN) { |
346 | pr_err("%s: Fault is not occurred by System MMU '%s'!\n", | |
347 | __func__, dev_name(data->sysmmu)); | |
348 | pr_err("%s: Please check if IRQ is correctly configured.\n", | |
349 | __func__); | |
350 | BUG(); | |
351 | } else { | |
d09d78fc | 352 | unsigned int base = |
1fab7fa7 CK |
353 | __raw_readl(data->sfrbase + REG_PT_BASE_ADDR); |
354 | show_fault_information(dev_name(data->sysmmu), | |
355 | itype, base, addr); | |
356 | if (data->domain) | |
a9133b99 | 357 | ret = report_iommu_fault(&data->domain->domain, |
6b21a5db | 358 | data->master, addr, itype); |
2a96536e KC |
359 | } |
360 | ||
1fab7fa7 CK |
361 | /* fault is not recovered by fault handler */ |
362 | BUG_ON(ret != 0); | |
2a96536e | 363 | |
1fab7fa7 CK |
364 | __raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR); |
365 | ||
366 | sysmmu_unblock(data->sfrbase); | |
2a96536e | 367 | |
b398af21 | 368 | clk_disable(data->clk_master); |
70605870 | 369 | |
9d4e7a24 | 370 | spin_unlock(&data->lock); |
2a96536e KC |
371 | |
372 | return IRQ_HANDLED; | |
373 | } | |
374 | ||
6b21a5db | 375 | static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data) |
2a96536e | 376 | { |
b398af21 | 377 | clk_enable(data->clk_master); |
70605870 | 378 | |
7222e8db | 379 | __raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL); |
6b21a5db | 380 | __raw_writel(0, data->sfrbase + REG_MMU_CFG); |
2a96536e | 381 | |
46c16d1e | 382 | clk_disable(data->clk); |
b398af21 | 383 | clk_disable(data->clk_master); |
2a96536e KC |
384 | } |
385 | ||
6b21a5db | 386 | static bool __sysmmu_disable(struct sysmmu_drvdata *data) |
2a96536e | 387 | { |
6b21a5db | 388 | bool disabled; |
2a96536e KC |
389 | unsigned long flags; |
390 | ||
9d4e7a24 | 391 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 392 | |
6b21a5db CK |
393 | disabled = set_sysmmu_inactive(data); |
394 | ||
395 | if (disabled) { | |
396 | data->pgtable = 0; | |
397 | data->domain = NULL; | |
398 | ||
399 | __sysmmu_disable_nocount(data); | |
2a96536e | 400 | |
6b21a5db CK |
401 | dev_dbg(data->sysmmu, "Disabled\n"); |
402 | } else { | |
403 | dev_dbg(data->sysmmu, "%d times left to disable\n", | |
404 | data->activations); | |
2a96536e KC |
405 | } |
406 | ||
6b21a5db CK |
407 | spin_unlock_irqrestore(&data->lock, flags); |
408 | ||
409 | return disabled; | |
410 | } | |
2a96536e | 411 | |
6b21a5db CK |
412 | static void __sysmmu_init_config(struct sysmmu_drvdata *data) |
413 | { | |
eeb5184b CK |
414 | unsigned int cfg = CFG_LRU | CFG_QOS(15); |
415 | unsigned int ver; | |
416 | ||
512bd0c6 | 417 | ver = MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION)); |
eeb5184b CK |
418 | if (MMU_MAJ_VER(ver) == 3) { |
419 | if (MMU_MIN_VER(ver) >= 2) { | |
420 | cfg |= CFG_FLPDCACHE; | |
421 | if (MMU_MIN_VER(ver) == 3) { | |
422 | cfg |= CFG_ACGEN; | |
423 | cfg &= ~CFG_LRU; | |
424 | } else { | |
425 | cfg |= CFG_SYSSEL; | |
426 | } | |
427 | } | |
428 | } | |
6b21a5db CK |
429 | |
430 | __raw_writel(cfg, data->sfrbase + REG_MMU_CFG); | |
512bd0c6 | 431 | data->version = ver; |
6b21a5db CK |
432 | } |
433 | ||
434 | static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data) | |
435 | { | |
b398af21 | 436 | clk_enable(data->clk_master); |
70605870 CK |
437 | clk_enable(data->clk); |
438 | ||
6b21a5db CK |
439 | __raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL); |
440 | ||
441 | __sysmmu_init_config(data); | |
442 | ||
443 | __sysmmu_set_ptbase(data->sfrbase, data->pgtable); | |
2a96536e | 444 | |
7222e8db CK |
445 | __raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL); |
446 | ||
b398af21 | 447 | clk_disable(data->clk_master); |
6b21a5db | 448 | } |
70605870 | 449 | |
bfa00489 | 450 | static int __sysmmu_enable(struct sysmmu_drvdata *data, phys_addr_t pgtable, |
a9133b99 | 451 | struct exynos_iommu_domain *domain) |
6b21a5db CK |
452 | { |
453 | int ret = 0; | |
454 | unsigned long flags; | |
455 | ||
456 | spin_lock_irqsave(&data->lock, flags); | |
457 | if (set_sysmmu_active(data)) { | |
458 | data->pgtable = pgtable; | |
a9133b99 | 459 | data->domain = domain; |
6b21a5db CK |
460 | |
461 | __sysmmu_enable_nocount(data); | |
462 | ||
463 | dev_dbg(data->sysmmu, "Enabled\n"); | |
464 | } else { | |
465 | ret = (pgtable == data->pgtable) ? 1 : -EBUSY; | |
466 | ||
467 | dev_dbg(data->sysmmu, "already enabled\n"); | |
468 | } | |
469 | ||
470 | if (WARN_ON(ret < 0)) | |
471 | set_sysmmu_inactive(data); /* decrement count */ | |
2a96536e | 472 | |
9d4e7a24 | 473 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
474 | |
475 | return ret; | |
476 | } | |
477 | ||
66a7ed84 CK |
478 | static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
479 | sysmmu_iova_t iova) | |
480 | { | |
512bd0c6 | 481 | if (data->version == MAKE_MMU_VER(3, 3)) |
66a7ed84 CK |
482 | __raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY); |
483 | } | |
484 | ||
469acebe | 485 | static void sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data, |
66a7ed84 CK |
486 | sysmmu_iova_t iova) |
487 | { | |
488 | unsigned long flags; | |
66a7ed84 | 489 | |
b398af21 | 490 | clk_enable(data->clk_master); |
66a7ed84 CK |
491 | |
492 | spin_lock_irqsave(&data->lock, flags); | |
493 | if (is_sysmmu_active(data)) | |
494 | __sysmmu_tlb_invalidate_flpdcache(data, iova); | |
495 | spin_unlock_irqrestore(&data->lock, flags); | |
496 | ||
b398af21 | 497 | clk_disable(data->clk_master); |
66a7ed84 CK |
498 | } |
499 | ||
469acebe MS |
500 | static void sysmmu_tlb_invalidate_entry(struct sysmmu_drvdata *data, |
501 | sysmmu_iova_t iova, size_t size) | |
2a96536e KC |
502 | { |
503 | unsigned long flags; | |
2a96536e | 504 | |
6b21a5db | 505 | spin_lock_irqsave(&data->lock, flags); |
2a96536e | 506 | if (is_sysmmu_active(data)) { |
3ad6b7f3 | 507 | unsigned int num_inv = 1; |
70605870 | 508 | |
b398af21 | 509 | clk_enable(data->clk_master); |
70605870 | 510 | |
3ad6b7f3 CK |
511 | /* |
512 | * L2TLB invalidation required | |
513 | * 4KB page: 1 invalidation | |
f171abab SK |
514 | * 64KB page: 16 invalidations |
515 | * 1MB page: 64 invalidations | |
3ad6b7f3 CK |
516 | * because it is set-associative TLB |
517 | * with 8-way and 64 sets. | |
518 | * 1MB page can be cached in one of all sets. | |
519 | * 64KB page can be one of 16 consecutive sets. | |
520 | */ | |
512bd0c6 | 521 | if (MMU_MAJ_VER(data->version) == 2) |
3ad6b7f3 CK |
522 | num_inv = min_t(unsigned int, size / PAGE_SIZE, 64); |
523 | ||
7222e8db CK |
524 | if (sysmmu_block(data->sfrbase)) { |
525 | __sysmmu_tlb_invalidate_entry( | |
3ad6b7f3 | 526 | data->sfrbase, iova, num_inv); |
7222e8db | 527 | sysmmu_unblock(data->sfrbase); |
2a96536e | 528 | } |
b398af21 | 529 | clk_disable(data->clk_master); |
2a96536e | 530 | } else { |
469acebe MS |
531 | dev_dbg(data->master, |
532 | "disabled. Skipping TLB invalidation @ %#x\n", iova); | |
2a96536e | 533 | } |
9d4e7a24 | 534 | spin_unlock_irqrestore(&data->lock, flags); |
2a96536e KC |
535 | } |
536 | ||
6b21a5db | 537 | static int __init exynos_sysmmu_probe(struct platform_device *pdev) |
2a96536e | 538 | { |
46c16d1e | 539 | int irq, ret; |
7222e8db | 540 | struct device *dev = &pdev->dev; |
2a96536e | 541 | struct sysmmu_drvdata *data; |
7222e8db | 542 | struct resource *res; |
2a96536e | 543 | |
46c16d1e CK |
544 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
545 | if (!data) | |
546 | return -ENOMEM; | |
2a96536e | 547 | |
7222e8db | 548 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
46c16d1e CK |
549 | data->sfrbase = devm_ioremap_resource(dev, res); |
550 | if (IS_ERR(data->sfrbase)) | |
551 | return PTR_ERR(data->sfrbase); | |
2a96536e | 552 | |
46c16d1e CK |
553 | irq = platform_get_irq(pdev, 0); |
554 | if (irq <= 0) { | |
0bf4e54d | 555 | dev_err(dev, "Unable to find IRQ resource\n"); |
46c16d1e | 556 | return irq; |
2a96536e KC |
557 | } |
558 | ||
46c16d1e | 559 | ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, |
7222e8db CK |
560 | dev_name(dev), data); |
561 | if (ret) { | |
46c16d1e CK |
562 | dev_err(dev, "Unabled to register handler of irq %d\n", irq); |
563 | return ret; | |
2a96536e KC |
564 | } |
565 | ||
46c16d1e CK |
566 | data->clk = devm_clk_get(dev, "sysmmu"); |
567 | if (IS_ERR(data->clk)) { | |
568 | dev_err(dev, "Failed to get clock!\n"); | |
569 | return PTR_ERR(data->clk); | |
570 | } else { | |
571 | ret = clk_prepare(data->clk); | |
572 | if (ret) { | |
573 | dev_err(dev, "Failed to prepare clk\n"); | |
574 | return ret; | |
575 | } | |
2a96536e KC |
576 | } |
577 | ||
70605870 CK |
578 | data->clk_master = devm_clk_get(dev, "master"); |
579 | if (!IS_ERR(data->clk_master)) { | |
580 | ret = clk_prepare(data->clk_master); | |
581 | if (ret) { | |
582 | clk_unprepare(data->clk); | |
583 | dev_err(dev, "Failed to prepare master's clk\n"); | |
584 | return ret; | |
585 | } | |
b398af21 MS |
586 | } else { |
587 | data->clk_master = NULL; | |
70605870 CK |
588 | } |
589 | ||
2a96536e | 590 | data->sysmmu = dev; |
9d4e7a24 | 591 | spin_lock_init(&data->lock); |
2a96536e | 592 | |
7222e8db CK |
593 | platform_set_drvdata(pdev, data); |
594 | ||
f4723ec1 | 595 | pm_runtime_enable(dev); |
2a96536e | 596 | |
2a96536e | 597 | return 0; |
2a96536e KC |
598 | } |
599 | ||
622015e4 MS |
600 | #ifdef CONFIG_PM_SLEEP |
601 | static int exynos_sysmmu_suspend(struct device *dev) | |
602 | { | |
603 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
604 | ||
605 | dev_dbg(dev, "suspend\n"); | |
606 | if (is_sysmmu_active(data)) { | |
607 | __sysmmu_disable_nocount(data); | |
608 | pm_runtime_put(dev); | |
609 | } | |
610 | return 0; | |
611 | } | |
612 | ||
613 | static int exynos_sysmmu_resume(struct device *dev) | |
614 | { | |
615 | struct sysmmu_drvdata *data = dev_get_drvdata(dev); | |
616 | ||
617 | dev_dbg(dev, "resume\n"); | |
618 | if (is_sysmmu_active(data)) { | |
619 | pm_runtime_get_sync(dev); | |
620 | __sysmmu_enable_nocount(data); | |
621 | } | |
622 | return 0; | |
623 | } | |
624 | #endif | |
625 | ||
626 | static const struct dev_pm_ops sysmmu_pm_ops = { | |
627 | SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, exynos_sysmmu_resume) | |
628 | }; | |
629 | ||
6b21a5db CK |
630 | static const struct of_device_id sysmmu_of_match[] __initconst = { |
631 | { .compatible = "samsung,exynos-sysmmu", }, | |
632 | { }, | |
633 | }; | |
634 | ||
635 | static struct platform_driver exynos_sysmmu_driver __refdata = { | |
636 | .probe = exynos_sysmmu_probe, | |
637 | .driver = { | |
2a96536e | 638 | .name = "exynos-sysmmu", |
6b21a5db | 639 | .of_match_table = sysmmu_of_match, |
622015e4 | 640 | .pm = &sysmmu_pm_ops, |
2a96536e KC |
641 | } |
642 | }; | |
643 | ||
5e3435eb | 644 | static inline void update_pte(sysmmu_pte_t *ent, sysmmu_pte_t val) |
2a96536e | 645 | { |
5e3435eb MS |
646 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), sizeof(*ent), |
647 | DMA_TO_DEVICE); | |
648 | *ent = val; | |
649 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), sizeof(*ent), | |
650 | DMA_TO_DEVICE); | |
2a96536e KC |
651 | } |
652 | ||
e1fd1eaa | 653 | static struct iommu_domain *exynos_iommu_domain_alloc(unsigned type) |
2a96536e | 654 | { |
bfa00489 | 655 | struct exynos_iommu_domain *domain; |
5e3435eb | 656 | dma_addr_t handle; |
66a7ed84 | 657 | int i; |
2a96536e | 658 | |
e1fd1eaa | 659 | |
bfa00489 MS |
660 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); |
661 | if (!domain) | |
e1fd1eaa | 662 | return NULL; |
2a96536e | 663 | |
58c6f6a3 MS |
664 | if (type == IOMMU_DOMAIN_DMA) { |
665 | if (iommu_get_dma_cookie(&domain->domain) != 0) | |
666 | goto err_pgtable; | |
667 | } else if (type != IOMMU_DOMAIN_UNMANAGED) { | |
668 | goto err_pgtable; | |
669 | } | |
670 | ||
bfa00489 MS |
671 | domain->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2); |
672 | if (!domain->pgtable) | |
58c6f6a3 | 673 | goto err_dma_cookie; |
2a96536e | 674 | |
bfa00489 MS |
675 | domain->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1); |
676 | if (!domain->lv2entcnt) | |
2a96536e KC |
677 | goto err_counter; |
678 | ||
f171abab | 679 | /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ |
66a7ed84 | 680 | for (i = 0; i < NUM_LV1ENTRIES; i += 8) { |
bfa00489 MS |
681 | domain->pgtable[i + 0] = ZERO_LV2LINK; |
682 | domain->pgtable[i + 1] = ZERO_LV2LINK; | |
683 | domain->pgtable[i + 2] = ZERO_LV2LINK; | |
684 | domain->pgtable[i + 3] = ZERO_LV2LINK; | |
685 | domain->pgtable[i + 4] = ZERO_LV2LINK; | |
686 | domain->pgtable[i + 5] = ZERO_LV2LINK; | |
687 | domain->pgtable[i + 6] = ZERO_LV2LINK; | |
688 | domain->pgtable[i + 7] = ZERO_LV2LINK; | |
66a7ed84 CK |
689 | } |
690 | ||
5e3435eb MS |
691 | handle = dma_map_single(dma_dev, domain->pgtable, LV1TABLE_SIZE, |
692 | DMA_TO_DEVICE); | |
693 | /* For mapping page table entries we rely on dma == phys */ | |
694 | BUG_ON(handle != virt_to_phys(domain->pgtable)); | |
2a96536e | 695 | |
bfa00489 MS |
696 | spin_lock_init(&domain->lock); |
697 | spin_lock_init(&domain->pgtablelock); | |
698 | INIT_LIST_HEAD(&domain->clients); | |
2a96536e | 699 | |
bfa00489 MS |
700 | domain->domain.geometry.aperture_start = 0; |
701 | domain->domain.geometry.aperture_end = ~0UL; | |
702 | domain->domain.geometry.force_aperture = true; | |
3177bb76 | 703 | |
bfa00489 | 704 | return &domain->domain; |
2a96536e KC |
705 | |
706 | err_counter: | |
bfa00489 | 707 | free_pages((unsigned long)domain->pgtable, 2); |
58c6f6a3 MS |
708 | err_dma_cookie: |
709 | if (type == IOMMU_DOMAIN_DMA) | |
710 | iommu_put_dma_cookie(&domain->domain); | |
2a96536e | 711 | err_pgtable: |
bfa00489 | 712 | kfree(domain); |
e1fd1eaa | 713 | return NULL; |
2a96536e KC |
714 | } |
715 | ||
bfa00489 | 716 | static void exynos_iommu_domain_free(struct iommu_domain *iommu_domain) |
2a96536e | 717 | { |
bfa00489 | 718 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 719 | struct sysmmu_drvdata *data, *next; |
2a96536e KC |
720 | unsigned long flags; |
721 | int i; | |
722 | ||
bfa00489 | 723 | WARN_ON(!list_empty(&domain->clients)); |
2a96536e | 724 | |
bfa00489 | 725 | spin_lock_irqsave(&domain->lock, flags); |
2a96536e | 726 | |
bfa00489 | 727 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
728 | if (__sysmmu_disable(data)) |
729 | data->master = NULL; | |
730 | list_del_init(&data->domain_node); | |
2a96536e KC |
731 | } |
732 | ||
bfa00489 | 733 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 734 | |
58c6f6a3 MS |
735 | if (iommu_domain->type == IOMMU_DOMAIN_DMA) |
736 | iommu_put_dma_cookie(iommu_domain); | |
737 | ||
5e3435eb MS |
738 | dma_unmap_single(dma_dev, virt_to_phys(domain->pgtable), LV1TABLE_SIZE, |
739 | DMA_TO_DEVICE); | |
740 | ||
2a96536e | 741 | for (i = 0; i < NUM_LV1ENTRIES; i++) |
5e3435eb MS |
742 | if (lv1ent_page(domain->pgtable + i)) { |
743 | phys_addr_t base = lv2table_base(domain->pgtable + i); | |
744 | ||
745 | dma_unmap_single(dma_dev, base, LV2TABLE_SIZE, | |
746 | DMA_TO_DEVICE); | |
734c3c73 | 747 | kmem_cache_free(lv2table_kmem_cache, |
5e3435eb MS |
748 | phys_to_virt(base)); |
749 | } | |
2a96536e | 750 | |
bfa00489 MS |
751 | free_pages((unsigned long)domain->pgtable, 2); |
752 | free_pages((unsigned long)domain->lv2entcnt, 1); | |
753 | kfree(domain); | |
2a96536e KC |
754 | } |
755 | ||
bfa00489 | 756 | static int exynos_iommu_attach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
757 | struct device *dev) |
758 | { | |
6b21a5db | 759 | struct exynos_iommu_owner *owner = dev->archdata.iommu; |
bfa00489 | 760 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
469acebe | 761 | struct sysmmu_drvdata *data; |
bfa00489 | 762 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); |
2a96536e | 763 | unsigned long flags; |
469acebe | 764 | int ret = -ENODEV; |
2a96536e | 765 | |
469acebe MS |
766 | if (!has_sysmmu(dev)) |
767 | return -ENODEV; | |
2a96536e | 768 | |
1b092054 | 769 | list_for_each_entry(data, &owner->controllers, owner_node) { |
ce70ca56 | 770 | pm_runtime_get_sync(data->sysmmu); |
a9133b99 | 771 | ret = __sysmmu_enable(data, pagetable, domain); |
469acebe MS |
772 | if (ret >= 0) { |
773 | data->master = dev; | |
774 | ||
bfa00489 MS |
775 | spin_lock_irqsave(&domain->lock, flags); |
776 | list_add_tail(&data->domain_node, &domain->clients); | |
777 | spin_unlock_irqrestore(&domain->lock, flags); | |
469acebe MS |
778 | } |
779 | } | |
2a96536e KC |
780 | |
781 | if (ret < 0) { | |
7222e8db CK |
782 | dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n", |
783 | __func__, &pagetable); | |
7222e8db | 784 | return ret; |
2a96536e KC |
785 | } |
786 | ||
7222e8db CK |
787 | dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n", |
788 | __func__, &pagetable, (ret == 0) ? "" : ", again"); | |
789 | ||
2a96536e KC |
790 | return ret; |
791 | } | |
792 | ||
bfa00489 | 793 | static void exynos_iommu_detach_device(struct iommu_domain *iommu_domain, |
2a96536e KC |
794 | struct device *dev) |
795 | { | |
bfa00489 MS |
796 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
797 | phys_addr_t pagetable = virt_to_phys(domain->pgtable); | |
1b092054 | 798 | struct sysmmu_drvdata *data, *next; |
2a96536e | 799 | unsigned long flags; |
469acebe | 800 | bool found = false; |
2a96536e | 801 | |
469acebe MS |
802 | if (!has_sysmmu(dev)) |
803 | return; | |
2a96536e | 804 | |
bfa00489 | 805 | spin_lock_irqsave(&domain->lock, flags); |
1b092054 | 806 | list_for_each_entry_safe(data, next, &domain->clients, domain_node) { |
469acebe MS |
807 | if (data->master == dev) { |
808 | if (__sysmmu_disable(data)) { | |
809 | data->master = NULL; | |
810 | list_del_init(&data->domain_node); | |
811 | } | |
ce70ca56 | 812 | pm_runtime_put(data->sysmmu); |
469acebe | 813 | found = true; |
2a96536e KC |
814 | } |
815 | } | |
bfa00489 | 816 | spin_unlock_irqrestore(&domain->lock, flags); |
2a96536e | 817 | |
469acebe | 818 | if (found) |
7222e8db CK |
819 | dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n", |
820 | __func__, &pagetable); | |
6b21a5db CK |
821 | else |
822 | dev_err(dev, "%s: No IOMMU is attached\n", __func__); | |
2a96536e KC |
823 | } |
824 | ||
bfa00489 | 825 | static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, |
66a7ed84 | 826 | sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter) |
2a96536e | 827 | { |
61128f08 | 828 | if (lv1ent_section(sent)) { |
d09d78fc | 829 | WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova); |
61128f08 CK |
830 | return ERR_PTR(-EADDRINUSE); |
831 | } | |
832 | ||
2a96536e | 833 | if (lv1ent_fault(sent)) { |
d09d78fc | 834 | sysmmu_pte_t *pent; |
66a7ed84 | 835 | bool need_flush_flpd_cache = lv1ent_zero(sent); |
2a96536e | 836 | |
734c3c73 | 837 | pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC); |
d09d78fc | 838 | BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1)); |
2a96536e | 839 | if (!pent) |
61128f08 | 840 | return ERR_PTR(-ENOMEM); |
2a96536e | 841 | |
5e3435eb | 842 | update_pte(sent, mk_lv1ent_page(virt_to_phys(pent))); |
dc3814f4 | 843 | kmemleak_ignore(pent); |
2a96536e | 844 | *pgcounter = NUM_LV2ENTRIES; |
5e3435eb | 845 | dma_map_single(dma_dev, pent, LV2TABLE_SIZE, DMA_TO_DEVICE); |
66a7ed84 CK |
846 | |
847 | /* | |
f171abab SK |
848 | * If pre-fetched SLPD is a faulty SLPD in zero_l2_table, |
849 | * FLPD cache may cache the address of zero_l2_table. This | |
850 | * function replaces the zero_l2_table with new L2 page table | |
851 | * to write valid mappings. | |
66a7ed84 | 852 | * Accessing the valid area may cause page fault since FLPD |
f171abab SK |
853 | * cache may still cache zero_l2_table for the valid area |
854 | * instead of new L2 page table that has the mapping | |
855 | * information of the valid area. | |
66a7ed84 CK |
856 | * Thus any replacement of zero_l2_table with other valid L2 |
857 | * page table must involve FLPD cache invalidation for System | |
858 | * MMU v3.3. | |
859 | * FLPD cache invalidation is performed with TLB invalidation | |
860 | * by VPN without blocking. It is safe to invalidate TLB without | |
861 | * blocking because the target address of TLB invalidation is | |
862 | * not currently mapped. | |
863 | */ | |
864 | if (need_flush_flpd_cache) { | |
469acebe | 865 | struct sysmmu_drvdata *data; |
365409db | 866 | |
bfa00489 MS |
867 | spin_lock(&domain->lock); |
868 | list_for_each_entry(data, &domain->clients, domain_node) | |
469acebe | 869 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
bfa00489 | 870 | spin_unlock(&domain->lock); |
66a7ed84 | 871 | } |
2a96536e KC |
872 | } |
873 | ||
874 | return page_entry(sent, iova); | |
875 | } | |
876 | ||
bfa00489 | 877 | static int lv1set_section(struct exynos_iommu_domain *domain, |
66a7ed84 | 878 | sysmmu_pte_t *sent, sysmmu_iova_t iova, |
61128f08 | 879 | phys_addr_t paddr, short *pgcnt) |
2a96536e | 880 | { |
61128f08 | 881 | if (lv1ent_section(sent)) { |
d09d78fc | 882 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 883 | iova); |
2a96536e | 884 | return -EADDRINUSE; |
61128f08 | 885 | } |
2a96536e KC |
886 | |
887 | if (lv1ent_page(sent)) { | |
61128f08 | 888 | if (*pgcnt != NUM_LV2ENTRIES) { |
d09d78fc | 889 | WARN(1, "Trying mapping on 1MiB@%#08x that is mapped", |
61128f08 | 890 | iova); |
2a96536e | 891 | return -EADDRINUSE; |
61128f08 | 892 | } |
2a96536e | 893 | |
734c3c73 | 894 | kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0)); |
2a96536e KC |
895 | *pgcnt = 0; |
896 | } | |
897 | ||
5e3435eb | 898 | update_pte(sent, mk_lv1ent_sect(paddr)); |
2a96536e | 899 | |
bfa00489 | 900 | spin_lock(&domain->lock); |
66a7ed84 | 901 | if (lv1ent_page_zero(sent)) { |
469acebe | 902 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
903 | /* |
904 | * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD | |
905 | * entry by speculative prefetch of SLPD which has no mapping. | |
906 | */ | |
bfa00489 | 907 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 908 | sysmmu_tlb_invalidate_flpdcache(data, iova); |
66a7ed84 | 909 | } |
bfa00489 | 910 | spin_unlock(&domain->lock); |
66a7ed84 | 911 | |
2a96536e KC |
912 | return 0; |
913 | } | |
914 | ||
d09d78fc | 915 | static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, |
2a96536e KC |
916 | short *pgcnt) |
917 | { | |
918 | if (size == SPAGE_SIZE) { | |
0bf4e54d | 919 | if (WARN_ON(!lv2ent_fault(pent))) |
2a96536e KC |
920 | return -EADDRINUSE; |
921 | ||
5e3435eb | 922 | update_pte(pent, mk_lv2ent_spage(paddr)); |
2a96536e KC |
923 | *pgcnt -= 1; |
924 | } else { /* size == LPAGE_SIZE */ | |
925 | int i; | |
5e3435eb | 926 | dma_addr_t pent_base = virt_to_phys(pent); |
365409db | 927 | |
5e3435eb MS |
928 | dma_sync_single_for_cpu(dma_dev, pent_base, |
929 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
930 | DMA_TO_DEVICE); | |
2a96536e | 931 | for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { |
0bf4e54d | 932 | if (WARN_ON(!lv2ent_fault(pent))) { |
61128f08 CK |
933 | if (i > 0) |
934 | memset(pent - i, 0, sizeof(*pent) * i); | |
2a96536e KC |
935 | return -EADDRINUSE; |
936 | } | |
937 | ||
938 | *pent = mk_lv2ent_lpage(paddr); | |
939 | } | |
5e3435eb MS |
940 | dma_sync_single_for_device(dma_dev, pent_base, |
941 | sizeof(*pent) * SPAGES_PER_LPAGE, | |
942 | DMA_TO_DEVICE); | |
2a96536e KC |
943 | *pgcnt -= SPAGES_PER_LPAGE; |
944 | } | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
66a7ed84 CK |
949 | /* |
950 | * *CAUTION* to the I/O virtual memory managers that support exynos-iommu: | |
951 | * | |
f171abab | 952 | * System MMU v3.x has advanced logic to improve address translation |
66a7ed84 | 953 | * performance with caching more page table entries by a page table walk. |
f171abab SK |
954 | * However, the logic has a bug that while caching faulty page table entries, |
955 | * System MMU reports page fault if the cached fault entry is hit even though | |
956 | * the fault entry is updated to a valid entry after the entry is cached. | |
957 | * To prevent caching faulty page table entries which may be updated to valid | |
958 | * entries later, the virtual memory manager should care about the workaround | |
959 | * for the problem. The following describes the workaround. | |
66a7ed84 CK |
960 | * |
961 | * Any two consecutive I/O virtual address regions must have a hole of 128KiB | |
f171abab | 962 | * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug). |
66a7ed84 | 963 | * |
f171abab | 964 | * Precisely, any start address of I/O virtual region must be aligned with |
66a7ed84 CK |
965 | * the following sizes for System MMU v3.1 and v3.2. |
966 | * System MMU v3.1: 128KiB | |
967 | * System MMU v3.2: 256KiB | |
968 | * | |
969 | * Because System MMU v3.3 caches page table entries more aggressively, it needs | |
f171abab SK |
970 | * more workarounds. |
971 | * - Any two consecutive I/O virtual regions must have a hole of size larger | |
972 | * than or equal to 128KiB. | |
66a7ed84 CK |
973 | * - Start address of an I/O virtual region must be aligned by 128KiB. |
974 | */ | |
bfa00489 MS |
975 | static int exynos_iommu_map(struct iommu_domain *iommu_domain, |
976 | unsigned long l_iova, phys_addr_t paddr, size_t size, | |
977 | int prot) | |
2a96536e | 978 | { |
bfa00489 | 979 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
980 | sysmmu_pte_t *entry; |
981 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; | |
2a96536e KC |
982 | unsigned long flags; |
983 | int ret = -ENOMEM; | |
984 | ||
bfa00489 | 985 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 986 | |
bfa00489 | 987 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 988 | |
bfa00489 | 989 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
990 | |
991 | if (size == SECT_SIZE) { | |
bfa00489 MS |
992 | ret = lv1set_section(domain, entry, iova, paddr, |
993 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 994 | } else { |
d09d78fc | 995 | sysmmu_pte_t *pent; |
2a96536e | 996 | |
bfa00489 MS |
997 | pent = alloc_lv2entry(domain, entry, iova, |
998 | &domain->lv2entcnt[lv1ent_offset(iova)]); | |
2a96536e | 999 | |
61128f08 CK |
1000 | if (IS_ERR(pent)) |
1001 | ret = PTR_ERR(pent); | |
2a96536e KC |
1002 | else |
1003 | ret = lv2set_page(pent, paddr, size, | |
bfa00489 | 1004 | &domain->lv2entcnt[lv1ent_offset(iova)]); |
2a96536e KC |
1005 | } |
1006 | ||
61128f08 | 1007 | if (ret) |
0bf4e54d CK |
1008 | pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n", |
1009 | __func__, ret, size, iova); | |
2a96536e | 1010 | |
bfa00489 | 1011 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1012 | |
1013 | return ret; | |
1014 | } | |
1015 | ||
bfa00489 MS |
1016 | static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *domain, |
1017 | sysmmu_iova_t iova, size_t size) | |
66a7ed84 | 1018 | { |
469acebe | 1019 | struct sysmmu_drvdata *data; |
66a7ed84 CK |
1020 | unsigned long flags; |
1021 | ||
bfa00489 | 1022 | spin_lock_irqsave(&domain->lock, flags); |
66a7ed84 | 1023 | |
bfa00489 | 1024 | list_for_each_entry(data, &domain->clients, domain_node) |
469acebe | 1025 | sysmmu_tlb_invalidate_entry(data, iova, size); |
66a7ed84 | 1026 | |
bfa00489 | 1027 | spin_unlock_irqrestore(&domain->lock, flags); |
66a7ed84 CK |
1028 | } |
1029 | ||
bfa00489 MS |
1030 | static size_t exynos_iommu_unmap(struct iommu_domain *iommu_domain, |
1031 | unsigned long l_iova, size_t size) | |
2a96536e | 1032 | { |
bfa00489 | 1033 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc CK |
1034 | sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; |
1035 | sysmmu_pte_t *ent; | |
61128f08 | 1036 | size_t err_pgsize; |
d09d78fc | 1037 | unsigned long flags; |
2a96536e | 1038 | |
bfa00489 | 1039 | BUG_ON(domain->pgtable == NULL); |
2a96536e | 1040 | |
bfa00489 | 1041 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1042 | |
bfa00489 | 1043 | ent = section_entry(domain->pgtable, iova); |
2a96536e KC |
1044 | |
1045 | if (lv1ent_section(ent)) { | |
0bf4e54d | 1046 | if (WARN_ON(size < SECT_SIZE)) { |
61128f08 CK |
1047 | err_pgsize = SECT_SIZE; |
1048 | goto err; | |
1049 | } | |
2a96536e | 1050 | |
f171abab | 1051 | /* workaround for h/w bug in System MMU v3.3 */ |
5e3435eb | 1052 | update_pte(ent, ZERO_LV2LINK); |
2a96536e KC |
1053 | size = SECT_SIZE; |
1054 | goto done; | |
1055 | } | |
1056 | ||
1057 | if (unlikely(lv1ent_fault(ent))) { | |
1058 | if (size > SECT_SIZE) | |
1059 | size = SECT_SIZE; | |
1060 | goto done; | |
1061 | } | |
1062 | ||
1063 | /* lv1ent_page(sent) == true here */ | |
1064 | ||
1065 | ent = page_entry(ent, iova); | |
1066 | ||
1067 | if (unlikely(lv2ent_fault(ent))) { | |
1068 | size = SPAGE_SIZE; | |
1069 | goto done; | |
1070 | } | |
1071 | ||
1072 | if (lv2ent_small(ent)) { | |
5e3435eb | 1073 | update_pte(ent, 0); |
2a96536e | 1074 | size = SPAGE_SIZE; |
bfa00489 | 1075 | domain->lv2entcnt[lv1ent_offset(iova)] += 1; |
2a96536e KC |
1076 | goto done; |
1077 | } | |
1078 | ||
1079 | /* lv1ent_large(ent) == true here */ | |
0bf4e54d | 1080 | if (WARN_ON(size < LPAGE_SIZE)) { |
61128f08 CK |
1081 | err_pgsize = LPAGE_SIZE; |
1082 | goto err; | |
1083 | } | |
2a96536e | 1084 | |
5e3435eb MS |
1085 | dma_sync_single_for_cpu(dma_dev, virt_to_phys(ent), |
1086 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1087 | DMA_TO_DEVICE); | |
2a96536e | 1088 | memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE); |
5e3435eb MS |
1089 | dma_sync_single_for_device(dma_dev, virt_to_phys(ent), |
1090 | sizeof(*ent) * SPAGES_PER_LPAGE, | |
1091 | DMA_TO_DEVICE); | |
2a96536e | 1092 | size = LPAGE_SIZE; |
bfa00489 | 1093 | domain->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE; |
2a96536e | 1094 | done: |
bfa00489 | 1095 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e | 1096 | |
bfa00489 | 1097 | exynos_iommu_tlb_invalidate_entry(domain, iova, size); |
2a96536e | 1098 | |
2a96536e | 1099 | return size; |
61128f08 | 1100 | err: |
bfa00489 | 1101 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
61128f08 | 1102 | |
0bf4e54d CK |
1103 | pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n", |
1104 | __func__, size, iova, err_pgsize); | |
61128f08 CK |
1105 | |
1106 | return 0; | |
2a96536e KC |
1107 | } |
1108 | ||
bfa00489 | 1109 | static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *iommu_domain, |
bb5547ac | 1110 | dma_addr_t iova) |
2a96536e | 1111 | { |
bfa00489 | 1112 | struct exynos_iommu_domain *domain = to_exynos_domain(iommu_domain); |
d09d78fc | 1113 | sysmmu_pte_t *entry; |
2a96536e KC |
1114 | unsigned long flags; |
1115 | phys_addr_t phys = 0; | |
1116 | ||
bfa00489 | 1117 | spin_lock_irqsave(&domain->pgtablelock, flags); |
2a96536e | 1118 | |
bfa00489 | 1119 | entry = section_entry(domain->pgtable, iova); |
2a96536e KC |
1120 | |
1121 | if (lv1ent_section(entry)) { | |
1122 | phys = section_phys(entry) + section_offs(iova); | |
1123 | } else if (lv1ent_page(entry)) { | |
1124 | entry = page_entry(entry, iova); | |
1125 | ||
1126 | if (lv2ent_large(entry)) | |
1127 | phys = lpage_phys(entry) + lpage_offs(iova); | |
1128 | else if (lv2ent_small(entry)) | |
1129 | phys = spage_phys(entry) + spage_offs(iova); | |
1130 | } | |
1131 | ||
bfa00489 | 1132 | spin_unlock_irqrestore(&domain->pgtablelock, flags); |
2a96536e KC |
1133 | |
1134 | return phys; | |
1135 | } | |
1136 | ||
6c2ae7e2 MS |
1137 | static struct iommu_group *get_device_iommu_group(struct device *dev) |
1138 | { | |
1139 | struct iommu_group *group; | |
1140 | ||
1141 | group = iommu_group_get(dev); | |
1142 | if (!group) | |
1143 | group = iommu_group_alloc(); | |
1144 | ||
1145 | return group; | |
1146 | } | |
1147 | ||
bf4a1c92 AM |
1148 | static int exynos_iommu_add_device(struct device *dev) |
1149 | { | |
1150 | struct iommu_group *group; | |
bf4a1c92 | 1151 | |
06801db0 MS |
1152 | if (!has_sysmmu(dev)) |
1153 | return -ENODEV; | |
1154 | ||
6c2ae7e2 | 1155 | group = iommu_group_get_for_dev(dev); |
bf4a1c92 | 1156 | |
6c2ae7e2 MS |
1157 | if (IS_ERR(group)) |
1158 | return PTR_ERR(group); | |
bf4a1c92 | 1159 | |
bf4a1c92 AM |
1160 | iommu_group_put(group); |
1161 | ||
6c2ae7e2 | 1162 | return 0; |
bf4a1c92 AM |
1163 | } |
1164 | ||
1165 | static void exynos_iommu_remove_device(struct device *dev) | |
1166 | { | |
06801db0 MS |
1167 | if (!has_sysmmu(dev)) |
1168 | return; | |
1169 | ||
bf4a1c92 AM |
1170 | iommu_group_remove_device(dev); |
1171 | } | |
1172 | ||
aa759fd3 MS |
1173 | static int exynos_iommu_of_xlate(struct device *dev, |
1174 | struct of_phandle_args *spec) | |
1175 | { | |
1176 | struct exynos_iommu_owner *owner = dev->archdata.iommu; | |
1177 | struct platform_device *sysmmu = of_find_device_by_node(spec->np); | |
1178 | struct sysmmu_drvdata *data; | |
1179 | ||
1180 | if (!sysmmu) | |
1181 | return -ENODEV; | |
1182 | ||
1183 | data = platform_get_drvdata(sysmmu); | |
1184 | if (!data) | |
1185 | return -ENODEV; | |
1186 | ||
1187 | if (!owner) { | |
1188 | owner = kzalloc(sizeof(*owner), GFP_KERNEL); | |
1189 | if (!owner) | |
1190 | return -ENOMEM; | |
1191 | ||
1192 | INIT_LIST_HEAD(&owner->controllers); | |
1193 | dev->archdata.iommu = owner; | |
1194 | } | |
1195 | ||
1196 | list_add_tail(&data->owner_node, &owner->controllers); | |
1197 | return 0; | |
1198 | } | |
1199 | ||
8ed55c81 | 1200 | static struct iommu_ops exynos_iommu_ops = { |
e1fd1eaa JR |
1201 | .domain_alloc = exynos_iommu_domain_alloc, |
1202 | .domain_free = exynos_iommu_domain_free, | |
ba5fa6f6 BH |
1203 | .attach_dev = exynos_iommu_attach_device, |
1204 | .detach_dev = exynos_iommu_detach_device, | |
1205 | .map = exynos_iommu_map, | |
1206 | .unmap = exynos_iommu_unmap, | |
315786eb | 1207 | .map_sg = default_iommu_map_sg, |
ba5fa6f6 | 1208 | .iova_to_phys = exynos_iommu_iova_to_phys, |
6c2ae7e2 | 1209 | .device_group = get_device_iommu_group, |
ba5fa6f6 BH |
1210 | .add_device = exynos_iommu_add_device, |
1211 | .remove_device = exynos_iommu_remove_device, | |
2a96536e | 1212 | .pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE, |
aa759fd3 | 1213 | .of_xlate = exynos_iommu_of_xlate, |
2a96536e KC |
1214 | }; |
1215 | ||
8ed55c81 MS |
1216 | static bool init_done; |
1217 | ||
2a96536e KC |
1218 | static int __init exynos_iommu_init(void) |
1219 | { | |
1220 | int ret; | |
1221 | ||
734c3c73 CK |
1222 | lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table", |
1223 | LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL); | |
1224 | if (!lv2table_kmem_cache) { | |
1225 | pr_err("%s: Failed to create kmem cache\n", __func__); | |
1226 | return -ENOMEM; | |
1227 | } | |
1228 | ||
2a96536e | 1229 | ret = platform_driver_register(&exynos_sysmmu_driver); |
734c3c73 CK |
1230 | if (ret) { |
1231 | pr_err("%s: Failed to register driver\n", __func__); | |
1232 | goto err_reg_driver; | |
1233 | } | |
2a96536e | 1234 | |
66a7ed84 CK |
1235 | zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL); |
1236 | if (zero_lv2_table == NULL) { | |
1237 | pr_err("%s: Failed to allocate zero level2 page table\n", | |
1238 | __func__); | |
1239 | ret = -ENOMEM; | |
1240 | goto err_zero_lv2; | |
1241 | } | |
1242 | ||
734c3c73 CK |
1243 | ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops); |
1244 | if (ret) { | |
1245 | pr_err("%s: Failed to register exynos-iommu driver.\n", | |
1246 | __func__); | |
1247 | goto err_set_iommu; | |
1248 | } | |
2a96536e | 1249 | |
8ed55c81 MS |
1250 | init_done = true; |
1251 | ||
734c3c73 CK |
1252 | return 0; |
1253 | err_set_iommu: | |
66a7ed84 CK |
1254 | kmem_cache_free(lv2table_kmem_cache, zero_lv2_table); |
1255 | err_zero_lv2: | |
734c3c73 CK |
1256 | platform_driver_unregister(&exynos_sysmmu_driver); |
1257 | err_reg_driver: | |
1258 | kmem_cache_destroy(lv2table_kmem_cache); | |
2a96536e KC |
1259 | return ret; |
1260 | } | |
8ed55c81 MS |
1261 | |
1262 | static int __init exynos_iommu_of_setup(struct device_node *np) | |
1263 | { | |
1264 | struct platform_device *pdev; | |
1265 | ||
1266 | if (!init_done) | |
1267 | exynos_iommu_init(); | |
1268 | ||
1269 | pdev = of_platform_device_create(np, NULL, platform_bus_type.dev_root); | |
1270 | if (IS_ERR(pdev)) | |
1271 | return PTR_ERR(pdev); | |
1272 | ||
5e3435eb MS |
1273 | /* |
1274 | * use the first registered sysmmu device for performing | |
1275 | * dma mapping operations on iommu page tables (cpu cache flush) | |
1276 | */ | |
1277 | if (!dma_dev) | |
1278 | dma_dev = &pdev->dev; | |
1279 | ||
8ed55c81 MS |
1280 | of_iommu_set_ops(np, &exynos_iommu_ops); |
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | IOMMU_OF_DECLARE(exynos_iommu_of, "samsung,exynos-sysmmu", | |
1285 | exynos_iommu_of_setup); |