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ba395927 | 1 | /* |
ea8ea460 | 2 | * Copyright © 2006-2014 Intel Corporation. |
ba395927 KA |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
ea8ea460 DW |
13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
14 | * Ashok Raj <ashok.raj@intel.com>, | |
15 | * Shaohua Li <shaohua.li@intel.com>, | |
16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, | |
17 | * Fenghua Yu <fenghua.yu@intel.com> | |
ba395927 KA |
18 | */ |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/bitmap.h> | |
5e0d2a6f | 22 | #include <linux/debugfs.h> |
54485c30 | 23 | #include <linux/export.h> |
ba395927 KA |
24 | #include <linux/slab.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/interrupt.h> | |
ba395927 KA |
27 | #include <linux/spinlock.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/dmar.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/mempool.h> | |
75f05569 | 32 | #include <linux/memory.h> |
5e0d2a6f | 33 | #include <linux/timer.h> |
38717946 | 34 | #include <linux/iova.h> |
5d450806 | 35 | #include <linux/iommu.h> |
38717946 | 36 | #include <linux/intel-iommu.h> |
134fac3f | 37 | #include <linux/syscore_ops.h> |
69575d38 | 38 | #include <linux/tboot.h> |
adb2fe02 | 39 | #include <linux/dmi.h> |
5cdede24 | 40 | #include <linux/pci-ats.h> |
0ee332c1 | 41 | #include <linux/memblock.h> |
8a8f422d | 42 | #include <asm/irq_remapping.h> |
ba395927 | 43 | #include <asm/cacheflush.h> |
46a7fa27 | 44 | #include <asm/iommu.h> |
ba395927 | 45 | |
078e1ee2 | 46 | #include "irq_remapping.h" |
61e015ac | 47 | #include "pci.h" |
078e1ee2 | 48 | |
5b6985ce FY |
49 | #define ROOT_SIZE VTD_PAGE_SIZE |
50 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
51 | ||
ba395927 KA |
52 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
53 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
e0fc7e0b | 54 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
ba395927 KA |
55 | |
56 | #define IOAPIC_RANGE_START (0xfee00000) | |
57 | #define IOAPIC_RANGE_END (0xfeefffff) | |
58 | #define IOVA_START_ADDR (0x1000) | |
59 | ||
60 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
61 | ||
4ed0d3e6 | 62 | #define MAX_AGAW_WIDTH 64 |
5c645b35 | 63 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
4ed0d3e6 | 64 | |
2ebe3151 DW |
65 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
66 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) | |
67 | ||
68 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR | |
69 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ | |
70 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ | |
71 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) | |
72 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) | |
ba395927 | 73 | |
f27be03b | 74 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 75 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 76 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 77 | |
df08cdc7 AM |
78 | /* page table handling */ |
79 | #define LEVEL_STRIDE (9) | |
80 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
81 | ||
6d1c56a9 OBC |
82 | /* |
83 | * This bitmap is used to advertise the page sizes our hardware support | |
84 | * to the IOMMU core, which will then use this information to split | |
85 | * physically contiguous memory regions it is mapping into page sizes | |
86 | * that we support. | |
87 | * | |
88 | * Traditionally the IOMMU core just handed us the mappings directly, | |
89 | * after making sure the size is an order of a 4KiB page and that the | |
90 | * mapping has natural alignment. | |
91 | * | |
92 | * To retain this behavior, we currently advertise that we support | |
93 | * all page sizes that are an order of 4KiB. | |
94 | * | |
95 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
96 | * we could change this to advertise the real page sizes we support. | |
97 | */ | |
98 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) | |
99 | ||
df08cdc7 AM |
100 | static inline int agaw_to_level(int agaw) |
101 | { | |
102 | return agaw + 2; | |
103 | } | |
104 | ||
105 | static inline int agaw_to_width(int agaw) | |
106 | { | |
5c645b35 | 107 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
df08cdc7 AM |
108 | } |
109 | ||
110 | static inline int width_to_agaw(int width) | |
111 | { | |
5c645b35 | 112 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
df08cdc7 AM |
113 | } |
114 | ||
115 | static inline unsigned int level_to_offset_bits(int level) | |
116 | { | |
117 | return (level - 1) * LEVEL_STRIDE; | |
118 | } | |
119 | ||
120 | static inline int pfn_level_offset(unsigned long pfn, int level) | |
121 | { | |
122 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; | |
123 | } | |
124 | ||
125 | static inline unsigned long level_mask(int level) | |
126 | { | |
127 | return -1UL << level_to_offset_bits(level); | |
128 | } | |
129 | ||
130 | static inline unsigned long level_size(int level) | |
131 | { | |
132 | return 1UL << level_to_offset_bits(level); | |
133 | } | |
134 | ||
135 | static inline unsigned long align_to_level(unsigned long pfn, int level) | |
136 | { | |
137 | return (pfn + level_size(level) - 1) & level_mask(level); | |
138 | } | |
fd18de50 | 139 | |
6dd9a7c7 YS |
140 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
141 | { | |
5c645b35 | 142 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
6dd9a7c7 YS |
143 | } |
144 | ||
dd4e8319 DW |
145 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
146 | are never going to work. */ | |
147 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
148 | { | |
149 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
150 | } | |
151 | ||
152 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
153 | { | |
154 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
155 | } | |
156 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
157 | { | |
158 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
159 | } | |
160 | static inline unsigned long virt_to_dma_pfn(void *p) | |
161 | { | |
162 | return page_to_dma_pfn(virt_to_page(p)); | |
163 | } | |
164 | ||
d9630fe9 WH |
165 | /* global iommu list, set NULL for ignored DMAR units */ |
166 | static struct intel_iommu **g_iommus; | |
167 | ||
e0fc7e0b | 168 | static void __init check_tylersburg_isoch(void); |
9af88143 DW |
169 | static int rwbf_quirk; |
170 | ||
b779260b JC |
171 | /* |
172 | * set to 1 to panic kernel if can't successfully enable VT-d | |
173 | * (used when kernel is launched w/ TXT) | |
174 | */ | |
175 | static int force_on = 0; | |
176 | ||
46b08e1a MM |
177 | /* |
178 | * 0: Present | |
179 | * 1-11: Reserved | |
180 | * 12-63: Context Ptr (12 - (haw-1)) | |
181 | * 64-127: Reserved | |
182 | */ | |
183 | struct root_entry { | |
184 | u64 val; | |
185 | u64 rsvd1; | |
186 | }; | |
187 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
188 | static inline bool root_present(struct root_entry *root) | |
189 | { | |
190 | return (root->val & 1); | |
191 | } | |
192 | static inline void set_root_present(struct root_entry *root) | |
193 | { | |
194 | root->val |= 1; | |
195 | } | |
196 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
197 | { | |
198 | root->val |= value & VTD_PAGE_MASK; | |
199 | } | |
200 | ||
201 | static inline struct context_entry * | |
202 | get_context_addr_from_root(struct root_entry *root) | |
203 | { | |
204 | return (struct context_entry *) | |
205 | (root_present(root)?phys_to_virt( | |
206 | root->val & VTD_PAGE_MASK) : | |
207 | NULL); | |
208 | } | |
209 | ||
7a8fc25e MM |
210 | /* |
211 | * low 64 bits: | |
212 | * 0: present | |
213 | * 1: fault processing disable | |
214 | * 2-3: translation type | |
215 | * 12-63: address space root | |
216 | * high 64 bits: | |
217 | * 0-2: address width | |
218 | * 3-6: aval | |
219 | * 8-23: domain id | |
220 | */ | |
221 | struct context_entry { | |
222 | u64 lo; | |
223 | u64 hi; | |
224 | }; | |
c07e7d21 MM |
225 | |
226 | static inline bool context_present(struct context_entry *context) | |
227 | { | |
228 | return (context->lo & 1); | |
229 | } | |
230 | static inline void context_set_present(struct context_entry *context) | |
231 | { | |
232 | context->lo |= 1; | |
233 | } | |
234 | ||
235 | static inline void context_set_fault_enable(struct context_entry *context) | |
236 | { | |
237 | context->lo &= (((u64)-1) << 2) | 1; | |
238 | } | |
239 | ||
c07e7d21 MM |
240 | static inline void context_set_translation_type(struct context_entry *context, |
241 | unsigned long value) | |
242 | { | |
243 | context->lo &= (((u64)-1) << 4) | 3; | |
244 | context->lo |= (value & 3) << 2; | |
245 | } | |
246 | ||
247 | static inline void context_set_address_root(struct context_entry *context, | |
248 | unsigned long value) | |
249 | { | |
250 | context->lo |= value & VTD_PAGE_MASK; | |
251 | } | |
252 | ||
253 | static inline void context_set_address_width(struct context_entry *context, | |
254 | unsigned long value) | |
255 | { | |
256 | context->hi |= value & 7; | |
257 | } | |
258 | ||
259 | static inline void context_set_domain_id(struct context_entry *context, | |
260 | unsigned long value) | |
261 | { | |
262 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
263 | } | |
264 | ||
265 | static inline void context_clear_entry(struct context_entry *context) | |
266 | { | |
267 | context->lo = 0; | |
268 | context->hi = 0; | |
269 | } | |
7a8fc25e | 270 | |
622ba12a MM |
271 | /* |
272 | * 0: readable | |
273 | * 1: writable | |
274 | * 2-6: reserved | |
275 | * 7: super page | |
9cf06697 SY |
276 | * 8-10: available |
277 | * 11: snoop behavior | |
622ba12a MM |
278 | * 12-63: Host physcial address |
279 | */ | |
280 | struct dma_pte { | |
281 | u64 val; | |
282 | }; | |
622ba12a | 283 | |
19c239ce MM |
284 | static inline void dma_clear_pte(struct dma_pte *pte) |
285 | { | |
286 | pte->val = 0; | |
287 | } | |
288 | ||
19c239ce MM |
289 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
290 | { | |
c85994e4 DW |
291 | #ifdef CONFIG_64BIT |
292 | return pte->val & VTD_PAGE_MASK; | |
293 | #else | |
294 | /* Must have a full atomic 64-bit read */ | |
1a8bd481 | 295 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
c85994e4 | 296 | #endif |
19c239ce MM |
297 | } |
298 | ||
19c239ce MM |
299 | static inline bool dma_pte_present(struct dma_pte *pte) |
300 | { | |
301 | return (pte->val & 3) != 0; | |
302 | } | |
622ba12a | 303 | |
4399c8bf AK |
304 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
305 | { | |
306 | return (pte->val & (1 << 7)); | |
307 | } | |
308 | ||
75e6bf96 DW |
309 | static inline int first_pte_in_page(struct dma_pte *pte) |
310 | { | |
311 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
312 | } | |
313 | ||
2c2e2c38 FY |
314 | /* |
315 | * This domain is a statically identity mapping domain. | |
316 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
317 | * 2. It maps to each iommu if successful. | |
318 | * 3. Each iommu mapps to this domain if successful. | |
319 | */ | |
19943b0e DW |
320 | static struct dmar_domain *si_domain; |
321 | static int hw_pass_through = 1; | |
2c2e2c38 | 322 | |
3b5410e7 | 323 | /* devices under the same p2p bridge are owned in one domain */ |
cdc7b837 | 324 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
3b5410e7 | 325 | |
1ce28feb WH |
326 | /* domain represents a virtual machine, more than one devices |
327 | * across iommus may be owned in one domain, e.g. kvm guest. | |
328 | */ | |
329 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) | |
330 | ||
2c2e2c38 FY |
331 | /* si_domain contains mulitple devices */ |
332 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) | |
333 | ||
1b198bb0 MT |
334 | /* define the limit of IOMMUs supported in each domain */ |
335 | #ifdef CONFIG_X86 | |
336 | # define IOMMU_UNITS_SUPPORTED MAX_IO_APICS | |
337 | #else | |
338 | # define IOMMU_UNITS_SUPPORTED 64 | |
339 | #endif | |
340 | ||
99126f7c MM |
341 | struct dmar_domain { |
342 | int id; /* domain id */ | |
4c923d47 | 343 | int nid; /* node id */ |
1b198bb0 MT |
344 | DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED); |
345 | /* bitmap of iommus this domain uses*/ | |
99126f7c MM |
346 | |
347 | struct list_head devices; /* all devices' list */ | |
348 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
349 | ||
350 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
351 | int gaw; /* max guest address width */ |
352 | ||
353 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
354 | int agaw; | |
355 | ||
3b5410e7 | 356 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
357 | |
358 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 359 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d | 360 | int iommu_count; /* reference count of iommu */ |
6dd9a7c7 YS |
361 | int iommu_superpage;/* Level of superpages supported: |
362 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
363 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
c7151a8d | 364 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
fe40f1e0 | 365 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
366 | }; |
367 | ||
a647dacb MM |
368 | /* PCI domain-device relationship */ |
369 | struct device_domain_info { | |
370 | struct list_head link; /* link to domain siblings */ | |
371 | struct list_head global; /* link to global list */ | |
276dbf99 | 372 | u8 bus; /* PCI bus number */ |
a647dacb | 373 | u8 devfn; /* PCI devfn number */ |
0bcb3e28 | 374 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
93a23a72 | 375 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
376 | struct dmar_domain *domain; /* pointer to domain */ |
377 | }; | |
378 | ||
b94e4117 JL |
379 | struct dmar_rmrr_unit { |
380 | struct list_head list; /* list of rmrr units */ | |
381 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
382 | u64 base_address; /* reserved base address*/ | |
383 | u64 end_address; /* reserved end address */ | |
832bd858 | 384 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
385 | int devices_cnt; /* target device count */ |
386 | }; | |
387 | ||
388 | struct dmar_atsr_unit { | |
389 | struct list_head list; /* list of ATSR units */ | |
390 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
832bd858 | 391 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
392 | int devices_cnt; /* target device count */ |
393 | u8 include_all:1; /* include all ports */ | |
394 | }; | |
395 | ||
396 | static LIST_HEAD(dmar_atsr_units); | |
397 | static LIST_HEAD(dmar_rmrr_units); | |
398 | ||
399 | #define for_each_rmrr_units(rmrr) \ | |
400 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
401 | ||
5e0d2a6f | 402 | static void flush_unmaps_timeout(unsigned long data); |
403 | ||
b707cb02 | 404 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
5e0d2a6f | 405 | |
80b20dd8 | 406 | #define HIGH_WATER_MARK 250 |
407 | struct deferred_flush_tables { | |
408 | int next; | |
409 | struct iova *iova[HIGH_WATER_MARK]; | |
410 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
ea8ea460 | 411 | struct page *freelist[HIGH_WATER_MARK]; |
80b20dd8 | 412 | }; |
413 | ||
414 | static struct deferred_flush_tables *deferred_flush; | |
415 | ||
5e0d2a6f | 416 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 417 | static int g_num_of_iommus; |
418 | ||
419 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
420 | static LIST_HEAD(unmaps_to_do); | |
421 | ||
422 | static int timer_on; | |
423 | static long list_size; | |
5e0d2a6f | 424 | |
92d03cc8 | 425 | static void domain_exit(struct dmar_domain *domain); |
ba395927 | 426 | static void domain_remove_dev_info(struct dmar_domain *domain); |
b94e4117 | 427 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
bf9c9eda | 428 | struct device *dev); |
92d03cc8 | 429 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 430 | struct device *dev); |
ba395927 | 431 | |
d3f13810 | 432 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
0cd5c3c8 KM |
433 | int dmar_disabled = 0; |
434 | #else | |
435 | int dmar_disabled = 1; | |
d3f13810 | 436 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
0cd5c3c8 | 437 | |
8bc1f85c ED |
438 | int intel_iommu_enabled = 0; |
439 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); | |
440 | ||
2d9e667e | 441 | static int dmar_map_gfx = 1; |
7d3b03ce | 442 | static int dmar_forcedac; |
5e0d2a6f | 443 | static int intel_iommu_strict; |
6dd9a7c7 | 444 | static int intel_iommu_superpage = 1; |
ba395927 | 445 | |
c0771df8 DW |
446 | int intel_iommu_gfx_mapped; |
447 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); | |
448 | ||
ba395927 KA |
449 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
450 | static DEFINE_SPINLOCK(device_domain_lock); | |
451 | static LIST_HEAD(device_domain_list); | |
452 | ||
a8bcbb0d JR |
453 | static struct iommu_ops intel_iommu_ops; |
454 | ||
ba395927 KA |
455 | static int __init intel_iommu_setup(char *str) |
456 | { | |
457 | if (!str) | |
458 | return -EINVAL; | |
459 | while (*str) { | |
0cd5c3c8 KM |
460 | if (!strncmp(str, "on", 2)) { |
461 | dmar_disabled = 0; | |
462 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
463 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 464 | dmar_disabled = 1; |
0cd5c3c8 | 465 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
466 | } else if (!strncmp(str, "igfx_off", 8)) { |
467 | dmar_map_gfx = 0; | |
468 | printk(KERN_INFO | |
469 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 470 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 471 | printk(KERN_INFO |
7d3b03ce KA |
472 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
473 | dmar_forcedac = 1; | |
5e0d2a6f | 474 | } else if (!strncmp(str, "strict", 6)) { |
475 | printk(KERN_INFO | |
476 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
477 | intel_iommu_strict = 1; | |
6dd9a7c7 YS |
478 | } else if (!strncmp(str, "sp_off", 6)) { |
479 | printk(KERN_INFO | |
480 | "Intel-IOMMU: disable supported super page\n"); | |
481 | intel_iommu_superpage = 0; | |
ba395927 KA |
482 | } |
483 | ||
484 | str += strcspn(str, ","); | |
485 | while (*str == ',') | |
486 | str++; | |
487 | } | |
488 | return 0; | |
489 | } | |
490 | __setup("intel_iommu=", intel_iommu_setup); | |
491 | ||
492 | static struct kmem_cache *iommu_domain_cache; | |
493 | static struct kmem_cache *iommu_devinfo_cache; | |
494 | static struct kmem_cache *iommu_iova_cache; | |
495 | ||
4c923d47 | 496 | static inline void *alloc_pgtable_page(int node) |
eb3fa7cb | 497 | { |
4c923d47 SS |
498 | struct page *page; |
499 | void *vaddr = NULL; | |
eb3fa7cb | 500 | |
4c923d47 SS |
501 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
502 | if (page) | |
503 | vaddr = page_address(page); | |
eb3fa7cb | 504 | return vaddr; |
ba395927 KA |
505 | } |
506 | ||
507 | static inline void free_pgtable_page(void *vaddr) | |
508 | { | |
509 | free_page((unsigned long)vaddr); | |
510 | } | |
511 | ||
512 | static inline void *alloc_domain_mem(void) | |
513 | { | |
354bb65e | 514 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
ba395927 KA |
515 | } |
516 | ||
38717946 | 517 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
518 | { |
519 | kmem_cache_free(iommu_domain_cache, vaddr); | |
520 | } | |
521 | ||
522 | static inline void * alloc_devinfo_mem(void) | |
523 | { | |
354bb65e | 524 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
ba395927 KA |
525 | } |
526 | ||
527 | static inline void free_devinfo_mem(void *vaddr) | |
528 | { | |
529 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
530 | } | |
531 | ||
532 | struct iova *alloc_iova_mem(void) | |
533 | { | |
354bb65e | 534 | return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC); |
ba395927 KA |
535 | } |
536 | ||
537 | void free_iova_mem(struct iova *iova) | |
538 | { | |
539 | kmem_cache_free(iommu_iova_cache, iova); | |
540 | } | |
541 | ||
1b573683 | 542 | |
4ed0d3e6 | 543 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
544 | { |
545 | unsigned long sagaw; | |
546 | int agaw = -1; | |
547 | ||
548 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 549 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
550 | agaw >= 0; agaw--) { |
551 | if (test_bit(agaw, &sagaw)) | |
552 | break; | |
553 | } | |
554 | ||
555 | return agaw; | |
556 | } | |
557 | ||
4ed0d3e6 FY |
558 | /* |
559 | * Calculate max SAGAW for each iommu. | |
560 | */ | |
561 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
562 | { | |
563 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
564 | } | |
565 | ||
566 | /* | |
567 | * calculate agaw for each iommu. | |
568 | * "SAGAW" may be different across iommus, use a default agaw, and | |
569 | * get a supported less agaw for iommus that don't support the default agaw. | |
570 | */ | |
571 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
572 | { | |
573 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
574 | } | |
575 | ||
2c2e2c38 | 576 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
577 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
578 | { | |
579 | int iommu_id; | |
580 | ||
2c2e2c38 | 581 | /* si_domain and vm domain should not get here. */ |
1ce28feb | 582 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
2c2e2c38 | 583 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
1ce28feb | 584 | |
1b198bb0 | 585 | iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus); |
8c11e798 WH |
586 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
587 | return NULL; | |
588 | ||
589 | return g_iommus[iommu_id]; | |
590 | } | |
591 | ||
8e604097 WH |
592 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
593 | { | |
d0501960 DW |
594 | struct dmar_drhd_unit *drhd; |
595 | struct intel_iommu *iommu; | |
596 | int i, found = 0; | |
2e12bc29 | 597 | |
d0501960 | 598 | domain->iommu_coherency = 1; |
8e604097 | 599 | |
1b198bb0 | 600 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
d0501960 | 601 | found = 1; |
8e604097 WH |
602 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
603 | domain->iommu_coherency = 0; | |
604 | break; | |
605 | } | |
8e604097 | 606 | } |
d0501960 DW |
607 | if (found) |
608 | return; | |
609 | ||
610 | /* No hardware attached; use lowest common denominator */ | |
611 | rcu_read_lock(); | |
612 | for_each_active_iommu(iommu, drhd) { | |
613 | if (!ecap_coherent(iommu->ecap)) { | |
614 | domain->iommu_coherency = 0; | |
615 | break; | |
616 | } | |
617 | } | |
618 | rcu_read_unlock(); | |
8e604097 WH |
619 | } |
620 | ||
58c610bd SY |
621 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
622 | { | |
623 | int i; | |
624 | ||
625 | domain->iommu_snooping = 1; | |
626 | ||
1b198bb0 | 627 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
58c610bd SY |
628 | if (!ecap_sc_support(g_iommus[i]->ecap)) { |
629 | domain->iommu_snooping = 0; | |
630 | break; | |
631 | } | |
58c610bd SY |
632 | } |
633 | } | |
634 | ||
6dd9a7c7 YS |
635 | static void domain_update_iommu_superpage(struct dmar_domain *domain) |
636 | { | |
8140a95d AK |
637 | struct dmar_drhd_unit *drhd; |
638 | struct intel_iommu *iommu = NULL; | |
639 | int mask = 0xf; | |
6dd9a7c7 YS |
640 | |
641 | if (!intel_iommu_superpage) { | |
642 | domain->iommu_superpage = 0; | |
643 | return; | |
644 | } | |
645 | ||
8140a95d | 646 | /* set iommu_superpage to the smallest common denominator */ |
0e242612 | 647 | rcu_read_lock(); |
8140a95d AK |
648 | for_each_active_iommu(iommu, drhd) { |
649 | mask &= cap_super_page_val(iommu->cap); | |
6dd9a7c7 YS |
650 | if (!mask) { |
651 | break; | |
652 | } | |
653 | } | |
0e242612 JL |
654 | rcu_read_unlock(); |
655 | ||
6dd9a7c7 YS |
656 | domain->iommu_superpage = fls(mask); |
657 | } | |
658 | ||
58c610bd SY |
659 | /* Some capabilities may be different across iommus */ |
660 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
661 | { | |
662 | domain_update_iommu_coherency(domain); | |
663 | domain_update_iommu_snooping(domain); | |
6dd9a7c7 | 664 | domain_update_iommu_superpage(domain); |
58c610bd SY |
665 | } |
666 | ||
156baca8 | 667 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
c7151a8d WH |
668 | { |
669 | struct dmar_drhd_unit *drhd = NULL; | |
b683b230 | 670 | struct intel_iommu *iommu; |
156baca8 DW |
671 | struct device *tmp; |
672 | struct pci_dev *ptmp, *pdev = NULL; | |
673 | u16 segment; | |
c7151a8d WH |
674 | int i; |
675 | ||
156baca8 DW |
676 | if (dev_is_pci(dev)) { |
677 | pdev = to_pci_dev(dev); | |
678 | segment = pci_domain_nr(pdev->bus); | |
679 | } else if (ACPI_COMPANION(dev)) | |
680 | dev = &ACPI_COMPANION(dev)->dev; | |
681 | ||
0e242612 | 682 | rcu_read_lock(); |
b683b230 | 683 | for_each_active_iommu(iommu, drhd) { |
156baca8 | 684 | if (pdev && segment != drhd->segment) |
276dbf99 | 685 | continue; |
c7151a8d | 686 | |
b683b230 | 687 | for_each_active_dev_scope(drhd->devices, |
156baca8 DW |
688 | drhd->devices_cnt, i, tmp) { |
689 | if (tmp == dev) { | |
690 | *bus = drhd->devices[i].bus; | |
691 | *devfn = drhd->devices[i].devfn; | |
b683b230 | 692 | goto out; |
156baca8 DW |
693 | } |
694 | ||
695 | if (!pdev || !dev_is_pci(tmp)) | |
696 | continue; | |
697 | ||
698 | ptmp = to_pci_dev(tmp); | |
699 | if (ptmp->subordinate && | |
700 | ptmp->subordinate->number <= pdev->bus->number && | |
701 | ptmp->subordinate->busn_res.end >= pdev->bus->number) | |
702 | goto got_pdev; | |
924b6231 | 703 | } |
c7151a8d | 704 | |
156baca8 DW |
705 | if (pdev && drhd->include_all) { |
706 | got_pdev: | |
707 | *bus = pdev->bus->number; | |
708 | *devfn = pdev->devfn; | |
b683b230 | 709 | goto out; |
156baca8 | 710 | } |
c7151a8d | 711 | } |
b683b230 | 712 | iommu = NULL; |
156baca8 | 713 | out: |
0e242612 | 714 | rcu_read_unlock(); |
c7151a8d | 715 | |
b683b230 | 716 | return iommu; |
c7151a8d WH |
717 | } |
718 | ||
5331fe6f WH |
719 | static void domain_flush_cache(struct dmar_domain *domain, |
720 | void *addr, int size) | |
721 | { | |
722 | if (!domain->iommu_coherency) | |
723 | clflush_cache_range(addr, size); | |
724 | } | |
725 | ||
ba395927 KA |
726 | /* Gets context entry for a given bus and devfn */ |
727 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
728 | u8 bus, u8 devfn) | |
729 | { | |
730 | struct root_entry *root; | |
731 | struct context_entry *context; | |
732 | unsigned long phy_addr; | |
733 | unsigned long flags; | |
734 | ||
735 | spin_lock_irqsave(&iommu->lock, flags); | |
736 | root = &iommu->root_entry[bus]; | |
737 | context = get_context_addr_from_root(root); | |
738 | if (!context) { | |
4c923d47 SS |
739 | context = (struct context_entry *) |
740 | alloc_pgtable_page(iommu->node); | |
ba395927 KA |
741 | if (!context) { |
742 | spin_unlock_irqrestore(&iommu->lock, flags); | |
743 | return NULL; | |
744 | } | |
5b6985ce | 745 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
746 | phy_addr = virt_to_phys((void *)context); |
747 | set_root_value(root, phy_addr); | |
748 | set_root_present(root); | |
749 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
750 | } | |
751 | spin_unlock_irqrestore(&iommu->lock, flags); | |
752 | return &context[devfn]; | |
753 | } | |
754 | ||
755 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
756 | { | |
757 | struct root_entry *root; | |
758 | struct context_entry *context; | |
759 | int ret; | |
760 | unsigned long flags; | |
761 | ||
762 | spin_lock_irqsave(&iommu->lock, flags); | |
763 | root = &iommu->root_entry[bus]; | |
764 | context = get_context_addr_from_root(root); | |
765 | if (!context) { | |
766 | ret = 0; | |
767 | goto out; | |
768 | } | |
c07e7d21 | 769 | ret = context_present(&context[devfn]); |
ba395927 KA |
770 | out: |
771 | spin_unlock_irqrestore(&iommu->lock, flags); | |
772 | return ret; | |
773 | } | |
774 | ||
775 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
776 | { | |
777 | struct root_entry *root; | |
778 | struct context_entry *context; | |
779 | unsigned long flags; | |
780 | ||
781 | spin_lock_irqsave(&iommu->lock, flags); | |
782 | root = &iommu->root_entry[bus]; | |
783 | context = get_context_addr_from_root(root); | |
784 | if (context) { | |
c07e7d21 | 785 | context_clear_entry(&context[devfn]); |
ba395927 KA |
786 | __iommu_flush_cache(iommu, &context[devfn], \ |
787 | sizeof(*context)); | |
788 | } | |
789 | spin_unlock_irqrestore(&iommu->lock, flags); | |
790 | } | |
791 | ||
792 | static void free_context_table(struct intel_iommu *iommu) | |
793 | { | |
794 | struct root_entry *root; | |
795 | int i; | |
796 | unsigned long flags; | |
797 | struct context_entry *context; | |
798 | ||
799 | spin_lock_irqsave(&iommu->lock, flags); | |
800 | if (!iommu->root_entry) { | |
801 | goto out; | |
802 | } | |
803 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
804 | root = &iommu->root_entry[i]; | |
805 | context = get_context_addr_from_root(root); | |
806 | if (context) | |
807 | free_pgtable_page(context); | |
808 | } | |
809 | free_pgtable_page(iommu->root_entry); | |
810 | iommu->root_entry = NULL; | |
811 | out: | |
812 | spin_unlock_irqrestore(&iommu->lock, flags); | |
813 | } | |
814 | ||
b026fd28 | 815 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
5cf0a76f | 816 | unsigned long pfn, int *target_level) |
ba395927 | 817 | { |
b026fd28 | 818 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 KA |
819 | struct dma_pte *parent, *pte = NULL; |
820 | int level = agaw_to_level(domain->agaw); | |
4399c8bf | 821 | int offset; |
ba395927 KA |
822 | |
823 | BUG_ON(!domain->pgd); | |
f9423606 JS |
824 | |
825 | if (addr_width < BITS_PER_LONG && pfn >> addr_width) | |
826 | /* Address beyond IOMMU's addressing capabilities. */ | |
827 | return NULL; | |
828 | ||
ba395927 KA |
829 | parent = domain->pgd; |
830 | ||
5cf0a76f | 831 | while (1) { |
ba395927 KA |
832 | void *tmp_page; |
833 | ||
b026fd28 | 834 | offset = pfn_level_offset(pfn, level); |
ba395927 | 835 | pte = &parent[offset]; |
5cf0a76f | 836 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
6dd9a7c7 | 837 | break; |
5cf0a76f | 838 | if (level == *target_level) |
ba395927 KA |
839 | break; |
840 | ||
19c239ce | 841 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
842 | uint64_t pteval; |
843 | ||
4c923d47 | 844 | tmp_page = alloc_pgtable_page(domain->nid); |
ba395927 | 845 | |
206a73c1 | 846 | if (!tmp_page) |
ba395927 | 847 | return NULL; |
206a73c1 | 848 | |
c85994e4 | 849 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
64de5af0 | 850 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
c85994e4 DW |
851 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { |
852 | /* Someone else set it while we were thinking; use theirs. */ | |
853 | free_pgtable_page(tmp_page); | |
854 | } else { | |
855 | dma_pte_addr(pte); | |
856 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
857 | } | |
ba395927 | 858 | } |
5cf0a76f DW |
859 | if (level == 1) |
860 | break; | |
861 | ||
19c239ce | 862 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
863 | level--; |
864 | } | |
865 | ||
5cf0a76f DW |
866 | if (!*target_level) |
867 | *target_level = level; | |
868 | ||
ba395927 KA |
869 | return pte; |
870 | } | |
871 | ||
6dd9a7c7 | 872 | |
ba395927 | 873 | /* return address's pte at specific level */ |
90dcfb5e DW |
874 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
875 | unsigned long pfn, | |
6dd9a7c7 | 876 | int level, int *large_page) |
ba395927 KA |
877 | { |
878 | struct dma_pte *parent, *pte = NULL; | |
879 | int total = agaw_to_level(domain->agaw); | |
880 | int offset; | |
881 | ||
882 | parent = domain->pgd; | |
883 | while (level <= total) { | |
90dcfb5e | 884 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
885 | pte = &parent[offset]; |
886 | if (level == total) | |
887 | return pte; | |
888 | ||
6dd9a7c7 YS |
889 | if (!dma_pte_present(pte)) { |
890 | *large_page = total; | |
ba395927 | 891 | break; |
6dd9a7c7 YS |
892 | } |
893 | ||
894 | if (pte->val & DMA_PTE_LARGE_PAGE) { | |
895 | *large_page = total; | |
896 | return pte; | |
897 | } | |
898 | ||
19c239ce | 899 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
900 | total--; |
901 | } | |
902 | return NULL; | |
903 | } | |
904 | ||
ba395927 | 905 | /* clear last level pte, a tlb flush should be followed */ |
5cf0a76f | 906 | static void dma_pte_clear_range(struct dmar_domain *domain, |
595badf5 DW |
907 | unsigned long start_pfn, |
908 | unsigned long last_pfn) | |
ba395927 | 909 | { |
04b18e65 | 910 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
6dd9a7c7 | 911 | unsigned int large_page = 1; |
310a5ab9 | 912 | struct dma_pte *first_pte, *pte; |
66eae846 | 913 | |
04b18e65 | 914 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
595badf5 | 915 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
59c36286 | 916 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 917 | |
04b18e65 | 918 | /* we don't need lock here; nobody else touches the iova range */ |
59c36286 | 919 | do { |
6dd9a7c7 YS |
920 | large_page = 1; |
921 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); | |
310a5ab9 | 922 | if (!pte) { |
6dd9a7c7 | 923 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
310a5ab9 DW |
924 | continue; |
925 | } | |
6dd9a7c7 | 926 | do { |
310a5ab9 | 927 | dma_clear_pte(pte); |
6dd9a7c7 | 928 | start_pfn += lvl_to_nr_pages(large_page); |
310a5ab9 | 929 | pte++; |
75e6bf96 DW |
930 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
931 | ||
310a5ab9 DW |
932 | domain_flush_cache(domain, first_pte, |
933 | (void *)pte - (void *)first_pte); | |
59c36286 DW |
934 | |
935 | } while (start_pfn && start_pfn <= last_pfn); | |
ba395927 KA |
936 | } |
937 | ||
3269ee0b AW |
938 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
939 | struct dma_pte *pte, unsigned long pfn, | |
940 | unsigned long start_pfn, unsigned long last_pfn) | |
941 | { | |
942 | pfn = max(start_pfn, pfn); | |
943 | pte = &pte[pfn_level_offset(pfn, level)]; | |
944 | ||
945 | do { | |
946 | unsigned long level_pfn; | |
947 | struct dma_pte *level_pte; | |
948 | ||
949 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) | |
950 | goto next; | |
951 | ||
952 | level_pfn = pfn & level_mask(level - 1); | |
953 | level_pte = phys_to_virt(dma_pte_addr(pte)); | |
954 | ||
955 | if (level > 2) | |
956 | dma_pte_free_level(domain, level - 1, level_pte, | |
957 | level_pfn, start_pfn, last_pfn); | |
958 | ||
959 | /* If range covers entire pagetable, free it */ | |
960 | if (!(start_pfn > level_pfn || | |
08336fd2 | 961 | last_pfn < level_pfn + level_size(level) - 1)) { |
3269ee0b AW |
962 | dma_clear_pte(pte); |
963 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
964 | free_pgtable_page(level_pte); | |
965 | } | |
966 | next: | |
967 | pfn += level_size(level); | |
968 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
969 | } | |
970 | ||
ba395927 KA |
971 | /* free page table pages. last level pte should already be cleared */ |
972 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
973 | unsigned long start_pfn, |
974 | unsigned long last_pfn) | |
ba395927 | 975 | { |
6660c63a | 976 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 | 977 | |
6660c63a DW |
978 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
979 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
59c36286 | 980 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 981 | |
f3a0a52f | 982 | /* We don't need lock here; nobody else touches the iova range */ |
3269ee0b AW |
983 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
984 | domain->pgd, 0, start_pfn, last_pfn); | |
6660c63a | 985 | |
ba395927 | 986 | /* free pgd */ |
d794dc9b | 987 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
988 | free_pgtable_page(domain->pgd); |
989 | domain->pgd = NULL; | |
990 | } | |
991 | } | |
992 | ||
ea8ea460 DW |
993 | /* When a page at a given level is being unlinked from its parent, we don't |
994 | need to *modify* it at all. All we need to do is make a list of all the | |
995 | pages which can be freed just as soon as we've flushed the IOTLB and we | |
996 | know the hardware page-walk will no longer touch them. | |
997 | The 'pte' argument is the *parent* PTE, pointing to the page that is to | |
998 | be freed. */ | |
999 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, | |
1000 | int level, struct dma_pte *pte, | |
1001 | struct page *freelist) | |
1002 | { | |
1003 | struct page *pg; | |
1004 | ||
1005 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); | |
1006 | pg->freelist = freelist; | |
1007 | freelist = pg; | |
1008 | ||
1009 | if (level == 1) | |
1010 | return freelist; | |
1011 | ||
adeb2590 JL |
1012 | pte = page_address(pg); |
1013 | do { | |
ea8ea460 DW |
1014 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
1015 | freelist = dma_pte_list_pagetables(domain, level - 1, | |
1016 | pte, freelist); | |
adeb2590 JL |
1017 | pte++; |
1018 | } while (!first_pte_in_page(pte)); | |
ea8ea460 DW |
1019 | |
1020 | return freelist; | |
1021 | } | |
1022 | ||
1023 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, | |
1024 | struct dma_pte *pte, unsigned long pfn, | |
1025 | unsigned long start_pfn, | |
1026 | unsigned long last_pfn, | |
1027 | struct page *freelist) | |
1028 | { | |
1029 | struct dma_pte *first_pte = NULL, *last_pte = NULL; | |
1030 | ||
1031 | pfn = max(start_pfn, pfn); | |
1032 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1033 | ||
1034 | do { | |
1035 | unsigned long level_pfn; | |
1036 | ||
1037 | if (!dma_pte_present(pte)) | |
1038 | goto next; | |
1039 | ||
1040 | level_pfn = pfn & level_mask(level); | |
1041 | ||
1042 | /* If range covers entire pagetable, free it */ | |
1043 | if (start_pfn <= level_pfn && | |
1044 | last_pfn >= level_pfn + level_size(level) - 1) { | |
1045 | /* These suborbinate page tables are going away entirely. Don't | |
1046 | bother to clear them; we're just going to *free* them. */ | |
1047 | if (level > 1 && !dma_pte_superpage(pte)) | |
1048 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); | |
1049 | ||
1050 | dma_clear_pte(pte); | |
1051 | if (!first_pte) | |
1052 | first_pte = pte; | |
1053 | last_pte = pte; | |
1054 | } else if (level > 1) { | |
1055 | /* Recurse down into a level that isn't *entirely* obsolete */ | |
1056 | freelist = dma_pte_clear_level(domain, level - 1, | |
1057 | phys_to_virt(dma_pte_addr(pte)), | |
1058 | level_pfn, start_pfn, last_pfn, | |
1059 | freelist); | |
1060 | } | |
1061 | next: | |
1062 | pfn += level_size(level); | |
1063 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1064 | ||
1065 | if (first_pte) | |
1066 | domain_flush_cache(domain, first_pte, | |
1067 | (void *)++last_pte - (void *)first_pte); | |
1068 | ||
1069 | return freelist; | |
1070 | } | |
1071 | ||
1072 | /* We can't just free the pages because the IOMMU may still be walking | |
1073 | the page tables, and may have cached the intermediate levels. The | |
1074 | pages can only be freed after the IOTLB flush has been done. */ | |
1075 | struct page *domain_unmap(struct dmar_domain *domain, | |
1076 | unsigned long start_pfn, | |
1077 | unsigned long last_pfn) | |
1078 | { | |
1079 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | |
1080 | struct page *freelist = NULL; | |
1081 | ||
1082 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); | |
1083 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
1084 | BUG_ON(start_pfn > last_pfn); | |
1085 | ||
1086 | /* we don't need lock here; nobody else touches the iova range */ | |
1087 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), | |
1088 | domain->pgd, 0, start_pfn, last_pfn, NULL); | |
1089 | ||
1090 | /* free pgd */ | |
1091 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { | |
1092 | struct page *pgd_page = virt_to_page(domain->pgd); | |
1093 | pgd_page->freelist = freelist; | |
1094 | freelist = pgd_page; | |
1095 | ||
1096 | domain->pgd = NULL; | |
1097 | } | |
1098 | ||
1099 | return freelist; | |
1100 | } | |
1101 | ||
1102 | void dma_free_pagelist(struct page *freelist) | |
1103 | { | |
1104 | struct page *pg; | |
1105 | ||
1106 | while ((pg = freelist)) { | |
1107 | freelist = pg->freelist; | |
1108 | free_pgtable_page(page_address(pg)); | |
1109 | } | |
1110 | } | |
1111 | ||
ba395927 KA |
1112 | /* iommu handling */ |
1113 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
1114 | { | |
1115 | struct root_entry *root; | |
1116 | unsigned long flags; | |
1117 | ||
4c923d47 | 1118 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
ba395927 KA |
1119 | if (!root) |
1120 | return -ENOMEM; | |
1121 | ||
5b6985ce | 1122 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
1123 | |
1124 | spin_lock_irqsave(&iommu->lock, flags); | |
1125 | iommu->root_entry = root; | |
1126 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1127 | ||
1128 | return 0; | |
1129 | } | |
1130 | ||
ba395927 KA |
1131 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
1132 | { | |
1133 | void *addr; | |
c416daa9 | 1134 | u32 sts; |
ba395927 KA |
1135 | unsigned long flag; |
1136 | ||
1137 | addr = iommu->root_entry; | |
1138 | ||
1f5b3c3f | 1139 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1140 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
1141 | ||
c416daa9 | 1142 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1143 | |
1144 | /* Make sure hardware complete it */ | |
1145 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1146 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 | 1147 | |
1f5b3c3f | 1148 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1149 | } |
1150 | ||
1151 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
1152 | { | |
1153 | u32 val; | |
1154 | unsigned long flag; | |
1155 | ||
9af88143 | 1156 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 1157 | return; |
ba395927 | 1158 | |
1f5b3c3f | 1159 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
462b60f6 | 1160 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1161 | |
1162 | /* Make sure hardware complete it */ | |
1163 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1164 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 | 1165 | |
1f5b3c3f | 1166 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1167 | } |
1168 | ||
1169 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
1170 | static void __iommu_flush_context(struct intel_iommu *iommu, |
1171 | u16 did, u16 source_id, u8 function_mask, | |
1172 | u64 type) | |
ba395927 KA |
1173 | { |
1174 | u64 val = 0; | |
1175 | unsigned long flag; | |
1176 | ||
ba395927 KA |
1177 | switch (type) { |
1178 | case DMA_CCMD_GLOBAL_INVL: | |
1179 | val = DMA_CCMD_GLOBAL_INVL; | |
1180 | break; | |
1181 | case DMA_CCMD_DOMAIN_INVL: | |
1182 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
1183 | break; | |
1184 | case DMA_CCMD_DEVICE_INVL: | |
1185 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
1186 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
1187 | break; | |
1188 | default: | |
1189 | BUG(); | |
1190 | } | |
1191 | val |= DMA_CCMD_ICC; | |
1192 | ||
1f5b3c3f | 1193 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1194 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
1195 | ||
1196 | /* Make sure hardware complete it */ | |
1197 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
1198 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
1199 | ||
1f5b3c3f | 1200 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1201 | } |
1202 | ||
ba395927 | 1203 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
1204 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
1205 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
1206 | { |
1207 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
1208 | u64 val = 0, val_iva = 0; | |
1209 | unsigned long flag; | |
1210 | ||
ba395927 KA |
1211 | switch (type) { |
1212 | case DMA_TLB_GLOBAL_FLUSH: | |
1213 | /* global flush doesn't need set IVA_REG */ | |
1214 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
1215 | break; | |
1216 | case DMA_TLB_DSI_FLUSH: | |
1217 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
1218 | break; | |
1219 | case DMA_TLB_PSI_FLUSH: | |
1220 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
ea8ea460 | 1221 | /* IH bit is passed in as part of address */ |
ba395927 KA |
1222 | val_iva = size_order | addr; |
1223 | break; | |
1224 | default: | |
1225 | BUG(); | |
1226 | } | |
1227 | /* Note: set drain read/write */ | |
1228 | #if 0 | |
1229 | /* | |
1230 | * This is probably to be super secure.. Looks like we can | |
1231 | * ignore it without any impact. | |
1232 | */ | |
1233 | if (cap_read_drain(iommu->cap)) | |
1234 | val |= DMA_TLB_READ_DRAIN; | |
1235 | #endif | |
1236 | if (cap_write_drain(iommu->cap)) | |
1237 | val |= DMA_TLB_WRITE_DRAIN; | |
1238 | ||
1f5b3c3f | 1239 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1240 | /* Note: Only uses first TLB reg currently */ |
1241 | if (val_iva) | |
1242 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
1243 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
1244 | ||
1245 | /* Make sure hardware complete it */ | |
1246 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
1247 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
1248 | ||
1f5b3c3f | 1249 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1250 | |
1251 | /* check IOTLB invalidation granularity */ | |
1252 | if (DMA_TLB_IAIG(val) == 0) | |
1253 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
1254 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
1255 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
1256 | (unsigned long long)DMA_TLB_IIRG(type), |
1257 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
1258 | } |
1259 | ||
64ae892b DW |
1260 | static struct device_domain_info * |
1261 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, | |
1262 | u8 bus, u8 devfn) | |
93a23a72 YZ |
1263 | { |
1264 | int found = 0; | |
1265 | unsigned long flags; | |
1266 | struct device_domain_info *info; | |
0bcb3e28 | 1267 | struct pci_dev *pdev; |
93a23a72 YZ |
1268 | |
1269 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
1270 | return NULL; | |
1271 | ||
1272 | if (!iommu->qi) | |
1273 | return NULL; | |
1274 | ||
1275 | spin_lock_irqsave(&device_domain_lock, flags); | |
1276 | list_for_each_entry(info, &domain->devices, link) | |
1277 | if (info->bus == bus && info->devfn == devfn) { | |
1278 | found = 1; | |
1279 | break; | |
1280 | } | |
1281 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1282 | ||
0bcb3e28 | 1283 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1284 | return NULL; |
1285 | ||
0bcb3e28 DW |
1286 | pdev = to_pci_dev(info->dev); |
1287 | ||
1288 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) | |
93a23a72 YZ |
1289 | return NULL; |
1290 | ||
0bcb3e28 | 1291 | if (!dmar_find_matched_atsr_unit(pdev)) |
93a23a72 YZ |
1292 | return NULL; |
1293 | ||
93a23a72 YZ |
1294 | return info; |
1295 | } | |
1296 | ||
1297 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1298 | { |
0bcb3e28 | 1299 | if (!info || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1300 | return; |
1301 | ||
0bcb3e28 | 1302 | pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT); |
93a23a72 YZ |
1303 | } |
1304 | ||
1305 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1306 | { | |
0bcb3e28 DW |
1307 | if (!info->dev || !dev_is_pci(info->dev) || |
1308 | !pci_ats_enabled(to_pci_dev(info->dev))) | |
93a23a72 YZ |
1309 | return; |
1310 | ||
0bcb3e28 | 1311 | pci_disable_ats(to_pci_dev(info->dev)); |
93a23a72 YZ |
1312 | } |
1313 | ||
1314 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1315 | u64 addr, unsigned mask) | |
1316 | { | |
1317 | u16 sid, qdep; | |
1318 | unsigned long flags; | |
1319 | struct device_domain_info *info; | |
1320 | ||
1321 | spin_lock_irqsave(&device_domain_lock, flags); | |
1322 | list_for_each_entry(info, &domain->devices, link) { | |
0bcb3e28 DW |
1323 | struct pci_dev *pdev; |
1324 | if (!info->dev || !dev_is_pci(info->dev)) | |
1325 | continue; | |
1326 | ||
1327 | pdev = to_pci_dev(info->dev); | |
1328 | if (!pci_ats_enabled(pdev)) | |
93a23a72 YZ |
1329 | continue; |
1330 | ||
1331 | sid = info->bus << 8 | info->devfn; | |
0bcb3e28 | 1332 | qdep = pci_ats_queue_depth(pdev); |
93a23a72 YZ |
1333 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
1334 | } | |
1335 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1336 | } | |
1337 | ||
1f0ef2aa | 1338 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
ea8ea460 | 1339 | unsigned long pfn, unsigned int pages, int ih, int map) |
ba395927 | 1340 | { |
9dd2fe89 | 1341 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1342 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
ba395927 | 1343 | |
ba395927 KA |
1344 | BUG_ON(pages == 0); |
1345 | ||
ea8ea460 DW |
1346 | if (ih) |
1347 | ih = 1 << 6; | |
ba395927 | 1348 | /* |
9dd2fe89 YZ |
1349 | * Fallback to domain selective flush if no PSI support or the size is |
1350 | * too big. | |
ba395927 KA |
1351 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1352 | * aligned to the size | |
1353 | */ | |
9dd2fe89 YZ |
1354 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1355 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1356 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 | 1357 | else |
ea8ea460 | 1358 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
9dd2fe89 | 1359 | DMA_TLB_PSI_FLUSH); |
bf92df30 YZ |
1360 | |
1361 | /* | |
82653633 NA |
1362 | * In caching mode, changes of pages from non-present to present require |
1363 | * flush. However, device IOTLB doesn't need to be flushed in this case. | |
bf92df30 | 1364 | */ |
82653633 | 1365 | if (!cap_caching_mode(iommu->cap) || !map) |
93a23a72 | 1366 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1367 | } |
1368 | ||
f8bab735 | 1369 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1370 | { | |
1371 | u32 pmen; | |
1372 | unsigned long flags; | |
1373 | ||
1f5b3c3f | 1374 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
f8bab735 | 1375 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
1376 | pmen &= ~DMA_PMEN_EPM; | |
1377 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1378 | ||
1379 | /* wait for the protected region status bit to clear */ | |
1380 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1381 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1382 | ||
1f5b3c3f | 1383 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
f8bab735 | 1384 | } |
1385 | ||
ba395927 KA |
1386 | static int iommu_enable_translation(struct intel_iommu *iommu) |
1387 | { | |
1388 | u32 sts; | |
1389 | unsigned long flags; | |
1390 | ||
1f5b3c3f | 1391 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
c416daa9 DW |
1392 | iommu->gcmd |= DMA_GCMD_TE; |
1393 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1394 | |
1395 | /* Make sure hardware complete it */ | |
1396 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1397 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1398 | |
1f5b3c3f | 1399 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
ba395927 KA |
1400 | return 0; |
1401 | } | |
1402 | ||
1403 | static int iommu_disable_translation(struct intel_iommu *iommu) | |
1404 | { | |
1405 | u32 sts; | |
1406 | unsigned long flag; | |
1407 | ||
1f5b3c3f | 1408 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1409 | iommu->gcmd &= ~DMA_GCMD_TE; |
1410 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1411 | ||
1412 | /* Make sure hardware complete it */ | |
1413 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1414 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 | 1415 | |
1f5b3c3f | 1416 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1417 | return 0; |
1418 | } | |
1419 | ||
3460a6d9 | 1420 | |
ba395927 KA |
1421 | static int iommu_init_domains(struct intel_iommu *iommu) |
1422 | { | |
1423 | unsigned long ndomains; | |
1424 | unsigned long nlongs; | |
1425 | ||
1426 | ndomains = cap_ndoms(iommu->cap); | |
852bdb04 JL |
1427 | pr_debug("IOMMU%d: Number of Domains supported <%ld>\n", |
1428 | iommu->seq_id, ndomains); | |
ba395927 KA |
1429 | nlongs = BITS_TO_LONGS(ndomains); |
1430 | ||
94a91b50 DD |
1431 | spin_lock_init(&iommu->lock); |
1432 | ||
ba395927 KA |
1433 | /* TBD: there might be 64K domains, |
1434 | * consider other allocation for future chip | |
1435 | */ | |
1436 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1437 | if (!iommu->domain_ids) { | |
852bdb04 JL |
1438 | pr_err("IOMMU%d: allocating domain id array failed\n", |
1439 | iommu->seq_id); | |
ba395927 KA |
1440 | return -ENOMEM; |
1441 | } | |
1442 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1443 | GFP_KERNEL); | |
1444 | if (!iommu->domains) { | |
852bdb04 JL |
1445 | pr_err("IOMMU%d: allocating domain array failed\n", |
1446 | iommu->seq_id); | |
1447 | kfree(iommu->domain_ids); | |
1448 | iommu->domain_ids = NULL; | |
ba395927 KA |
1449 | return -ENOMEM; |
1450 | } | |
1451 | ||
1452 | /* | |
1453 | * if Caching mode is set, then invalid translations are tagged | |
1454 | * with domainid 0. Hence we need to pre-allocate it. | |
1455 | */ | |
1456 | if (cap_caching_mode(iommu->cap)) | |
1457 | set_bit(0, iommu->domain_ids); | |
1458 | return 0; | |
1459 | } | |
ba395927 | 1460 | |
a868e6b7 | 1461 | static void free_dmar_iommu(struct intel_iommu *iommu) |
ba395927 KA |
1462 | { |
1463 | struct dmar_domain *domain; | |
5ced12af | 1464 | int i, count; |
c7151a8d | 1465 | unsigned long flags; |
ba395927 | 1466 | |
94a91b50 | 1467 | if ((iommu->domains) && (iommu->domain_ids)) { |
a45946ab | 1468 | for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) { |
a4eaa86c JL |
1469 | /* |
1470 | * Domain id 0 is reserved for invalid translation | |
1471 | * if hardware supports caching mode. | |
1472 | */ | |
1473 | if (cap_caching_mode(iommu->cap) && i == 0) | |
1474 | continue; | |
1475 | ||
94a91b50 DD |
1476 | domain = iommu->domains[i]; |
1477 | clear_bit(i, iommu->domain_ids); | |
1478 | ||
1479 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
5ced12af JL |
1480 | count = --domain->iommu_count; |
1481 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
92d03cc8 JL |
1482 | if (count == 0) |
1483 | domain_exit(domain); | |
5e98c4b1 | 1484 | } |
ba395927 KA |
1485 | } |
1486 | ||
1487 | if (iommu->gcmd & DMA_GCMD_TE) | |
1488 | iommu_disable_translation(iommu); | |
1489 | ||
ba395927 KA |
1490 | kfree(iommu->domains); |
1491 | kfree(iommu->domain_ids); | |
a868e6b7 JL |
1492 | iommu->domains = NULL; |
1493 | iommu->domain_ids = NULL; | |
ba395927 | 1494 | |
d9630fe9 WH |
1495 | g_iommus[iommu->seq_id] = NULL; |
1496 | ||
ba395927 KA |
1497 | /* free context mapping */ |
1498 | free_context_table(iommu); | |
ba395927 KA |
1499 | } |
1500 | ||
92d03cc8 | 1501 | static struct dmar_domain *alloc_domain(bool vm) |
ba395927 | 1502 | { |
92d03cc8 JL |
1503 | /* domain id for virtual machine, it won't be set in context */ |
1504 | static atomic_t vm_domid = ATOMIC_INIT(0); | |
ba395927 | 1505 | struct dmar_domain *domain; |
ba395927 KA |
1506 | |
1507 | domain = alloc_domain_mem(); | |
1508 | if (!domain) | |
1509 | return NULL; | |
1510 | ||
4c923d47 | 1511 | domain->nid = -1; |
92d03cc8 | 1512 | domain->iommu_count = 0; |
1b198bb0 | 1513 | memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp)); |
2c2e2c38 | 1514 | domain->flags = 0; |
92d03cc8 JL |
1515 | spin_lock_init(&domain->iommu_lock); |
1516 | INIT_LIST_HEAD(&domain->devices); | |
1517 | if (vm) { | |
1518 | domain->id = atomic_inc_return(&vm_domid); | |
1519 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; | |
1520 | } | |
2c2e2c38 FY |
1521 | |
1522 | return domain; | |
1523 | } | |
1524 | ||
1525 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1526 | struct intel_iommu *iommu) | |
1527 | { | |
1528 | int num; | |
1529 | unsigned long ndomains; | |
1530 | unsigned long flags; | |
1531 | ||
ba395927 KA |
1532 | ndomains = cap_ndoms(iommu->cap); |
1533 | ||
1534 | spin_lock_irqsave(&iommu->lock, flags); | |
2c2e2c38 | 1535 | |
ba395927 KA |
1536 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1537 | if (num >= ndomains) { | |
1538 | spin_unlock_irqrestore(&iommu->lock, flags); | |
ba395927 | 1539 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
2c2e2c38 | 1540 | return -ENOMEM; |
ba395927 KA |
1541 | } |
1542 | ||
ba395927 | 1543 | domain->id = num; |
9ebd682e | 1544 | domain->iommu_count++; |
2c2e2c38 | 1545 | set_bit(num, iommu->domain_ids); |
1b198bb0 | 1546 | set_bit(iommu->seq_id, domain->iommu_bmp); |
ba395927 KA |
1547 | iommu->domains[num] = domain; |
1548 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1549 | ||
2c2e2c38 | 1550 | return 0; |
ba395927 KA |
1551 | } |
1552 | ||
2c2e2c38 FY |
1553 | static void iommu_detach_domain(struct dmar_domain *domain, |
1554 | struct intel_iommu *iommu) | |
ba395927 KA |
1555 | { |
1556 | unsigned long flags; | |
2c2e2c38 | 1557 | int num, ndomains; |
ba395927 | 1558 | |
8c11e798 | 1559 | spin_lock_irqsave(&iommu->lock, flags); |
2c2e2c38 | 1560 | ndomains = cap_ndoms(iommu->cap); |
a45946ab | 1561 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
2c2e2c38 | 1562 | if (iommu->domains[num] == domain) { |
92d03cc8 JL |
1563 | clear_bit(num, iommu->domain_ids); |
1564 | iommu->domains[num] = NULL; | |
2c2e2c38 FY |
1565 | break; |
1566 | } | |
2c2e2c38 | 1567 | } |
8c11e798 | 1568 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1569 | } |
1570 | ||
1571 | static struct iova_domain reserved_iova_list; | |
8a443df4 | 1572 | static struct lock_class_key reserved_rbtree_key; |
ba395927 | 1573 | |
51a63e67 | 1574 | static int dmar_init_reserved_ranges(void) |
ba395927 KA |
1575 | { |
1576 | struct pci_dev *pdev = NULL; | |
1577 | struct iova *iova; | |
1578 | int i; | |
ba395927 | 1579 | |
f661197e | 1580 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1581 | |
8a443df4 MG |
1582 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
1583 | &reserved_rbtree_key); | |
1584 | ||
ba395927 KA |
1585 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1586 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1587 | IOVA_PFN(IOAPIC_RANGE_END)); | |
51a63e67 | 1588 | if (!iova) { |
ba395927 | 1589 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
51a63e67 JC |
1590 | return -ENODEV; |
1591 | } | |
ba395927 KA |
1592 | |
1593 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1594 | for_each_pci_dev(pdev) { | |
1595 | struct resource *r; | |
1596 | ||
1597 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1598 | r = &pdev->resource[i]; | |
1599 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1600 | continue; | |
1a4a4551 DW |
1601 | iova = reserve_iova(&reserved_iova_list, |
1602 | IOVA_PFN(r->start), | |
1603 | IOVA_PFN(r->end)); | |
51a63e67 | 1604 | if (!iova) { |
ba395927 | 1605 | printk(KERN_ERR "Reserve iova failed\n"); |
51a63e67 JC |
1606 | return -ENODEV; |
1607 | } | |
ba395927 KA |
1608 | } |
1609 | } | |
51a63e67 | 1610 | return 0; |
ba395927 KA |
1611 | } |
1612 | ||
1613 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1614 | { | |
1615 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1616 | } | |
1617 | ||
1618 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1619 | { | |
1620 | int agaw; | |
1621 | int r = (gaw - 12) % 9; | |
1622 | ||
1623 | if (r == 0) | |
1624 | agaw = gaw; | |
1625 | else | |
1626 | agaw = gaw + 9 - r; | |
1627 | if (agaw > 64) | |
1628 | agaw = 64; | |
1629 | return agaw; | |
1630 | } | |
1631 | ||
1632 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1633 | { | |
1634 | struct intel_iommu *iommu; | |
1635 | int adjust_width, agaw; | |
1636 | unsigned long sagaw; | |
1637 | ||
f661197e | 1638 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
ba395927 KA |
1639 | domain_reserve_special_ranges(domain); |
1640 | ||
1641 | /* calculate AGAW */ | |
8c11e798 | 1642 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1643 | if (guest_width > cap_mgaw(iommu->cap)) |
1644 | guest_width = cap_mgaw(iommu->cap); | |
1645 | domain->gaw = guest_width; | |
1646 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1647 | agaw = width_to_agaw(adjust_width); | |
1648 | sagaw = cap_sagaw(iommu->cap); | |
1649 | if (!test_bit(agaw, &sagaw)) { | |
1650 | /* hardware doesn't support it, choose a bigger one */ | |
1651 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1652 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1653 | if (agaw >= 5) | |
1654 | return -ENODEV; | |
1655 | } | |
1656 | domain->agaw = agaw; | |
ba395927 | 1657 | |
8e604097 WH |
1658 | if (ecap_coherent(iommu->ecap)) |
1659 | domain->iommu_coherency = 1; | |
1660 | else | |
1661 | domain->iommu_coherency = 0; | |
1662 | ||
58c610bd SY |
1663 | if (ecap_sc_support(iommu->ecap)) |
1664 | domain->iommu_snooping = 1; | |
1665 | else | |
1666 | domain->iommu_snooping = 0; | |
1667 | ||
214e39aa DW |
1668 | if (intel_iommu_superpage) |
1669 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); | |
1670 | else | |
1671 | domain->iommu_superpage = 0; | |
1672 | ||
4c923d47 | 1673 | domain->nid = iommu->node; |
c7151a8d | 1674 | |
ba395927 | 1675 | /* always allocate the top pgd */ |
4c923d47 | 1676 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
ba395927 KA |
1677 | if (!domain->pgd) |
1678 | return -ENOMEM; | |
5b6985ce | 1679 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1680 | return 0; |
1681 | } | |
1682 | ||
1683 | static void domain_exit(struct dmar_domain *domain) | |
1684 | { | |
2c2e2c38 FY |
1685 | struct dmar_drhd_unit *drhd; |
1686 | struct intel_iommu *iommu; | |
ea8ea460 | 1687 | struct page *freelist = NULL; |
ba395927 KA |
1688 | |
1689 | /* Domain 0 is reserved, so dont process it */ | |
1690 | if (!domain) | |
1691 | return; | |
1692 | ||
7b668357 AW |
1693 | /* Flush any lazy unmaps that may reference this domain */ |
1694 | if (!intel_iommu_strict) | |
1695 | flush_unmaps_timeout(0); | |
1696 | ||
92d03cc8 | 1697 | /* remove associated devices */ |
ba395927 | 1698 | domain_remove_dev_info(domain); |
92d03cc8 | 1699 | |
ba395927 KA |
1700 | /* destroy iovas */ |
1701 | put_iova_domain(&domain->iovad); | |
ba395927 | 1702 | |
ea8ea460 | 1703 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1704 | |
92d03cc8 | 1705 | /* clear attached or cached domains */ |
0e242612 | 1706 | rcu_read_lock(); |
2c2e2c38 | 1707 | for_each_active_iommu(iommu, drhd) |
92d03cc8 JL |
1708 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1709 | test_bit(iommu->seq_id, domain->iommu_bmp)) | |
2c2e2c38 | 1710 | iommu_detach_domain(domain, iommu); |
0e242612 | 1711 | rcu_read_unlock(); |
2c2e2c38 | 1712 | |
ea8ea460 DW |
1713 | dma_free_pagelist(freelist); |
1714 | ||
ba395927 KA |
1715 | free_domain_mem(domain); |
1716 | } | |
1717 | ||
64ae892b DW |
1718 | static int domain_context_mapping_one(struct dmar_domain *domain, |
1719 | struct intel_iommu *iommu, | |
1720 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1721 | { |
1722 | struct context_entry *context; | |
ba395927 | 1723 | unsigned long flags; |
ea6606b0 WH |
1724 | struct dma_pte *pgd; |
1725 | unsigned long num; | |
1726 | unsigned long ndomains; | |
1727 | int id; | |
1728 | int agaw; | |
93a23a72 | 1729 | struct device_domain_info *info = NULL; |
ba395927 KA |
1730 | |
1731 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1732 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1733 | |
ba395927 | 1734 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1735 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1736 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1737 | |
ba395927 KA |
1738 | context = device_to_context_entry(iommu, bus, devfn); |
1739 | if (!context) | |
1740 | return -ENOMEM; | |
1741 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1742 | if (context_present(context)) { |
ba395927 KA |
1743 | spin_unlock_irqrestore(&iommu->lock, flags); |
1744 | return 0; | |
1745 | } | |
1746 | ||
ea6606b0 WH |
1747 | id = domain->id; |
1748 | pgd = domain->pgd; | |
1749 | ||
2c2e2c38 FY |
1750 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1751 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { | |
ea6606b0 WH |
1752 | int found = 0; |
1753 | ||
1754 | /* find an available domain id for this device in iommu */ | |
1755 | ndomains = cap_ndoms(iommu->cap); | |
a45946ab | 1756 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
ea6606b0 WH |
1757 | if (iommu->domains[num] == domain) { |
1758 | id = num; | |
1759 | found = 1; | |
1760 | break; | |
1761 | } | |
ea6606b0 WH |
1762 | } |
1763 | ||
1764 | if (found == 0) { | |
1765 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1766 | if (num >= ndomains) { | |
1767 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1768 | printk(KERN_ERR "IOMMU: no free domain ids\n"); | |
1769 | return -EFAULT; | |
1770 | } | |
1771 | ||
1772 | set_bit(num, iommu->domain_ids); | |
1773 | iommu->domains[num] = domain; | |
1774 | id = num; | |
1775 | } | |
1776 | ||
1777 | /* Skip top levels of page tables for | |
1778 | * iommu which has less agaw than default. | |
1672af11 | 1779 | * Unnecessary for PT mode. |
ea6606b0 | 1780 | */ |
1672af11 CW |
1781 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1782 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1783 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1784 | if (!dma_pte_present(pgd)) { | |
1785 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1786 | return -ENOMEM; | |
1787 | } | |
ea6606b0 WH |
1788 | } |
1789 | } | |
1790 | } | |
1791 | ||
1792 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1793 | |
93a23a72 | 1794 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
64ae892b | 1795 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
93a23a72 YZ |
1796 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
1797 | CONTEXT_TT_MULTI_LEVEL; | |
1798 | } | |
4ed0d3e6 FY |
1799 | /* |
1800 | * In pass through mode, AW must be programmed to indicate the largest | |
1801 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1802 | */ | |
93a23a72 | 1803 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1804 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1805 | else { |
1806 | context_set_address_root(context, virt_to_phys(pgd)); | |
1807 | context_set_address_width(context, iommu->agaw); | |
1808 | } | |
4ed0d3e6 FY |
1809 | |
1810 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1811 | context_set_fault_enable(context); |
1812 | context_set_present(context); | |
5331fe6f | 1813 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1814 | |
4c25a2c1 DW |
1815 | /* |
1816 | * It's a non-present to present mapping. If hardware doesn't cache | |
1817 | * non-present entry we only need to flush the write-buffer. If the | |
1818 | * _does_ cache non-present entries, then it does so in the special | |
1819 | * domain #0, which we have to flush: | |
1820 | */ | |
1821 | if (cap_caching_mode(iommu->cap)) { | |
1822 | iommu->flush.flush_context(iommu, 0, | |
1823 | (((u16)bus) << 8) | devfn, | |
1824 | DMA_CCMD_MASK_NOBIT, | |
1825 | DMA_CCMD_DEVICE_INVL); | |
82653633 | 1826 | iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1827 | } else { |
ba395927 | 1828 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1829 | } |
93a23a72 | 1830 | iommu_enable_dev_iotlb(info); |
ba395927 | 1831 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d WH |
1832 | |
1833 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1b198bb0 | 1834 | if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) { |
c7151a8d | 1835 | domain->iommu_count++; |
4c923d47 SS |
1836 | if (domain->iommu_count == 1) |
1837 | domain->nid = iommu->node; | |
58c610bd | 1838 | domain_update_iommu_cap(domain); |
c7151a8d WH |
1839 | } |
1840 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
ba395927 KA |
1841 | return 0; |
1842 | } | |
1843 | ||
1844 | static int | |
e1f167f3 DW |
1845 | domain_context_mapping(struct dmar_domain *domain, struct device *dev, |
1846 | int translation) | |
ba395927 KA |
1847 | { |
1848 | int ret; | |
e1f167f3 | 1849 | struct pci_dev *pdev, *tmp, *parent; |
64ae892b | 1850 | struct intel_iommu *iommu; |
156baca8 | 1851 | u8 bus, devfn; |
64ae892b | 1852 | |
e1f167f3 | 1853 | iommu = device_to_iommu(dev, &bus, &devfn); |
64ae892b DW |
1854 | if (!iommu) |
1855 | return -ENODEV; | |
ba395927 | 1856 | |
156baca8 | 1857 | ret = domain_context_mapping_one(domain, iommu, bus, devfn, |
4ed0d3e6 | 1858 | translation); |
e1f167f3 | 1859 | if (ret || !dev_is_pci(dev)) |
ba395927 KA |
1860 | return ret; |
1861 | ||
1862 | /* dependent device mapping */ | |
e1f167f3 | 1863 | pdev = to_pci_dev(dev); |
ba395927 KA |
1864 | tmp = pci_find_upstream_pcie_bridge(pdev); |
1865 | if (!tmp) | |
1866 | return 0; | |
1867 | /* Secondary interface's bus number and devfn 0 */ | |
1868 | parent = pdev->bus->self; | |
1869 | while (parent != tmp) { | |
64ae892b | 1870 | ret = domain_context_mapping_one(domain, iommu, |
276dbf99 | 1871 | parent->bus->number, |
4ed0d3e6 | 1872 | parent->devfn, translation); |
ba395927 KA |
1873 | if (ret) |
1874 | return ret; | |
1875 | parent = parent->bus->self; | |
1876 | } | |
45e829ea | 1877 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
64ae892b | 1878 | return domain_context_mapping_one(domain, iommu, |
4ed0d3e6 FY |
1879 | tmp->subordinate->number, 0, |
1880 | translation); | |
ba395927 | 1881 | else /* this is a legacy PCI bridge */ |
64ae892b | 1882 | return domain_context_mapping_one(domain, iommu, |
276dbf99 | 1883 | tmp->bus->number, |
4ed0d3e6 FY |
1884 | tmp->devfn, |
1885 | translation); | |
ba395927 KA |
1886 | } |
1887 | ||
e1f167f3 | 1888 | static int domain_context_mapped(struct device *dev) |
ba395927 KA |
1889 | { |
1890 | int ret; | |
e1f167f3 | 1891 | struct pci_dev *pdev, *tmp, *parent; |
5331fe6f | 1892 | struct intel_iommu *iommu; |
156baca8 | 1893 | u8 bus, devfn; |
5331fe6f | 1894 | |
e1f167f3 | 1895 | iommu = device_to_iommu(dev, &bus, &devfn); |
5331fe6f WH |
1896 | if (!iommu) |
1897 | return -ENODEV; | |
ba395927 | 1898 | |
156baca8 | 1899 | ret = device_context_mapped(iommu, bus, devfn); |
e1f167f3 | 1900 | if (!ret || !dev_is_pci(dev)) |
ba395927 | 1901 | return ret; |
e1f167f3 | 1902 | |
ba395927 | 1903 | /* dependent device mapping */ |
e1f167f3 | 1904 | pdev = to_pci_dev(dev); |
ba395927 KA |
1905 | tmp = pci_find_upstream_pcie_bridge(pdev); |
1906 | if (!tmp) | |
1907 | return ret; | |
1908 | /* Secondary interface's bus number and devfn 0 */ | |
1909 | parent = pdev->bus->self; | |
1910 | while (parent != tmp) { | |
8c11e798 | 1911 | ret = device_context_mapped(iommu, parent->bus->number, |
276dbf99 | 1912 | parent->devfn); |
ba395927 KA |
1913 | if (!ret) |
1914 | return ret; | |
1915 | parent = parent->bus->self; | |
1916 | } | |
5f4d91a1 | 1917 | if (pci_is_pcie(tmp)) |
276dbf99 DW |
1918 | return device_context_mapped(iommu, tmp->subordinate->number, |
1919 | 0); | |
ba395927 | 1920 | else |
276dbf99 DW |
1921 | return device_context_mapped(iommu, tmp->bus->number, |
1922 | tmp->devfn); | |
ba395927 KA |
1923 | } |
1924 | ||
f532959b FY |
1925 | /* Returns a number of VTD pages, but aligned to MM page size */ |
1926 | static inline unsigned long aligned_nrpages(unsigned long host_addr, | |
1927 | size_t size) | |
1928 | { | |
1929 | host_addr &= ~PAGE_MASK; | |
1930 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; | |
1931 | } | |
1932 | ||
6dd9a7c7 YS |
1933 | /* Return largest possible superpage level for a given mapping */ |
1934 | static inline int hardware_largepage_caps(struct dmar_domain *domain, | |
1935 | unsigned long iov_pfn, | |
1936 | unsigned long phy_pfn, | |
1937 | unsigned long pages) | |
1938 | { | |
1939 | int support, level = 1; | |
1940 | unsigned long pfnmerge; | |
1941 | ||
1942 | support = domain->iommu_superpage; | |
1943 | ||
1944 | /* To use a large page, the virtual *and* physical addresses | |
1945 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either | |
1946 | of them will mean we have to use smaller pages. So just | |
1947 | merge them and check both at once. */ | |
1948 | pfnmerge = iov_pfn | phy_pfn; | |
1949 | ||
1950 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { | |
1951 | pages >>= VTD_STRIDE_SHIFT; | |
1952 | if (!pages) | |
1953 | break; | |
1954 | pfnmerge >>= VTD_STRIDE_SHIFT; | |
1955 | level++; | |
1956 | support--; | |
1957 | } | |
1958 | return level; | |
1959 | } | |
1960 | ||
9051aa02 DW |
1961 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1962 | struct scatterlist *sg, unsigned long phys_pfn, | |
1963 | unsigned long nr_pages, int prot) | |
e1605495 DW |
1964 | { |
1965 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 1966 | phys_addr_t uninitialized_var(pteval); |
e1605495 | 1967 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
9051aa02 | 1968 | unsigned long sg_res; |
6dd9a7c7 YS |
1969 | unsigned int largepage_lvl = 0; |
1970 | unsigned long lvl_pages = 0; | |
e1605495 DW |
1971 | |
1972 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); | |
1973 | ||
1974 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1975 | return -EINVAL; | |
1976 | ||
1977 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
1978 | ||
9051aa02 DW |
1979 | if (sg) |
1980 | sg_res = 0; | |
1981 | else { | |
1982 | sg_res = nr_pages + 1; | |
1983 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; | |
1984 | } | |
1985 | ||
6dd9a7c7 | 1986 | while (nr_pages > 0) { |
c85994e4 DW |
1987 | uint64_t tmp; |
1988 | ||
e1605495 | 1989 | if (!sg_res) { |
f532959b | 1990 | sg_res = aligned_nrpages(sg->offset, sg->length); |
e1605495 DW |
1991 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
1992 | sg->dma_length = sg->length; | |
1993 | pteval = page_to_phys(sg_page(sg)) | prot; | |
6dd9a7c7 | 1994 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
e1605495 | 1995 | } |
6dd9a7c7 | 1996 | |
e1605495 | 1997 | if (!pte) { |
6dd9a7c7 YS |
1998 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
1999 | ||
5cf0a76f | 2000 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
e1605495 DW |
2001 | if (!pte) |
2002 | return -ENOMEM; | |
6dd9a7c7 | 2003 | /* It is large page*/ |
6491d4d0 | 2004 | if (largepage_lvl > 1) { |
6dd9a7c7 | 2005 | pteval |= DMA_PTE_LARGE_PAGE; |
6491d4d0 WD |
2006 | /* Ensure that old small page tables are removed to make room |
2007 | for superpage, if they exist. */ | |
2008 | dma_pte_clear_range(domain, iov_pfn, | |
2009 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); | |
2010 | dma_pte_free_pagetable(domain, iov_pfn, | |
2011 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); | |
2012 | } else { | |
6dd9a7c7 | 2013 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
6491d4d0 | 2014 | } |
6dd9a7c7 | 2015 | |
e1605495 DW |
2016 | } |
2017 | /* We don't need lock here, nobody else | |
2018 | * touches the iova range | |
2019 | */ | |
7766a3fb | 2020 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 2021 | if (tmp) { |
1bf20f0d | 2022 | static int dumps = 5; |
c85994e4 DW |
2023 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
2024 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
2025 | if (dumps) { |
2026 | dumps--; | |
2027 | debug_dma_dump_mappings(NULL); | |
2028 | } | |
2029 | WARN_ON(1); | |
2030 | } | |
6dd9a7c7 YS |
2031 | |
2032 | lvl_pages = lvl_to_nr_pages(largepage_lvl); | |
2033 | ||
2034 | BUG_ON(nr_pages < lvl_pages); | |
2035 | BUG_ON(sg_res < lvl_pages); | |
2036 | ||
2037 | nr_pages -= lvl_pages; | |
2038 | iov_pfn += lvl_pages; | |
2039 | phys_pfn += lvl_pages; | |
2040 | pteval += lvl_pages * VTD_PAGE_SIZE; | |
2041 | sg_res -= lvl_pages; | |
2042 | ||
2043 | /* If the next PTE would be the first in a new page, then we | |
2044 | need to flush the cache on the entries we've just written. | |
2045 | And then we'll need to recalculate 'pte', so clear it and | |
2046 | let it get set again in the if (!pte) block above. | |
2047 | ||
2048 | If we're done (!nr_pages) we need to flush the cache too. | |
2049 | ||
2050 | Also if we've been setting superpages, we may need to | |
2051 | recalculate 'pte' and switch back to smaller pages for the | |
2052 | end of the mapping, if the trailing size is not enough to | |
2053 | use another superpage (i.e. sg_res < lvl_pages). */ | |
e1605495 | 2054 | pte++; |
6dd9a7c7 YS |
2055 | if (!nr_pages || first_pte_in_page(pte) || |
2056 | (largepage_lvl > 1 && sg_res < lvl_pages)) { | |
e1605495 DW |
2057 | domain_flush_cache(domain, first_pte, |
2058 | (void *)pte - (void *)first_pte); | |
2059 | pte = NULL; | |
2060 | } | |
6dd9a7c7 YS |
2061 | |
2062 | if (!sg_res && nr_pages) | |
e1605495 DW |
2063 | sg = sg_next(sg); |
2064 | } | |
2065 | return 0; | |
2066 | } | |
2067 | ||
9051aa02 DW |
2068 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2069 | struct scatterlist *sg, unsigned long nr_pages, | |
2070 | int prot) | |
ba395927 | 2071 | { |
9051aa02 DW |
2072 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
2073 | } | |
6f6a00e4 | 2074 | |
9051aa02 DW |
2075 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2076 | unsigned long phys_pfn, unsigned long nr_pages, | |
2077 | int prot) | |
2078 | { | |
2079 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
2080 | } |
2081 | ||
c7151a8d | 2082 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 2083 | { |
c7151a8d WH |
2084 | if (!iommu) |
2085 | return; | |
8c11e798 WH |
2086 | |
2087 | clear_context_table(iommu, bus, devfn); | |
2088 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 2089 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2090 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
2091 | } |
2092 | ||
109b9b04 DW |
2093 | static inline void unlink_domain_info(struct device_domain_info *info) |
2094 | { | |
2095 | assert_spin_locked(&device_domain_lock); | |
2096 | list_del(&info->link); | |
2097 | list_del(&info->global); | |
2098 | if (info->dev) | |
0bcb3e28 | 2099 | info->dev->archdata.iommu = NULL; |
109b9b04 DW |
2100 | } |
2101 | ||
ba395927 KA |
2102 | static void domain_remove_dev_info(struct dmar_domain *domain) |
2103 | { | |
2104 | struct device_domain_info *info; | |
92d03cc8 | 2105 | unsigned long flags, flags2; |
ba395927 KA |
2106 | |
2107 | spin_lock_irqsave(&device_domain_lock, flags); | |
2108 | while (!list_empty(&domain->devices)) { | |
2109 | info = list_entry(domain->devices.next, | |
2110 | struct device_domain_info, link); | |
109b9b04 | 2111 | unlink_domain_info(info); |
ba395927 KA |
2112 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2113 | ||
93a23a72 | 2114 | iommu_disable_dev_iotlb(info); |
7c7faa11 | 2115 | iommu_detach_dev(info->iommu, info->bus, info->devfn); |
ba395927 | 2116 | |
92d03cc8 | 2117 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) { |
7c7faa11 | 2118 | iommu_detach_dependent_devices(info->iommu, info->dev); |
92d03cc8 JL |
2119 | /* clear this iommu in iommu_bmp, update iommu count |
2120 | * and capabilities | |
2121 | */ | |
2122 | spin_lock_irqsave(&domain->iommu_lock, flags2); | |
7c7faa11 | 2123 | if (test_and_clear_bit(info->iommu->seq_id, |
92d03cc8 JL |
2124 | domain->iommu_bmp)) { |
2125 | domain->iommu_count--; | |
2126 | domain_update_iommu_cap(domain); | |
2127 | } | |
2128 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); | |
2129 | } | |
2130 | ||
2131 | free_devinfo_mem(info); | |
ba395927 KA |
2132 | spin_lock_irqsave(&device_domain_lock, flags); |
2133 | } | |
2134 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2135 | } | |
2136 | ||
2137 | /* | |
2138 | * find_domain | |
1525a29a | 2139 | * Note: we use struct device->archdata.iommu stores the info |
ba395927 | 2140 | */ |
1525a29a | 2141 | static struct dmar_domain *find_domain(struct device *dev) |
ba395927 KA |
2142 | { |
2143 | struct device_domain_info *info; | |
2144 | ||
2145 | /* No lock here, assumes no domain exit in normal case */ | |
1525a29a | 2146 | info = dev->archdata.iommu; |
ba395927 KA |
2147 | if (info) |
2148 | return info->domain; | |
2149 | return NULL; | |
2150 | } | |
2151 | ||
5a8f40e8 | 2152 | static inline struct device_domain_info * |
745f2586 JL |
2153 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
2154 | { | |
2155 | struct device_domain_info *info; | |
2156 | ||
2157 | list_for_each_entry(info, &device_domain_list, global) | |
41e80dca | 2158 | if (info->iommu->segment == segment && info->bus == bus && |
745f2586 | 2159 | info->devfn == devfn) |
5a8f40e8 | 2160 | return info; |
745f2586 JL |
2161 | |
2162 | return NULL; | |
2163 | } | |
2164 | ||
5a8f40e8 | 2165 | static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu, |
41e80dca | 2166 | int bus, int devfn, |
b718cd3d DW |
2167 | struct device *dev, |
2168 | struct dmar_domain *domain) | |
745f2586 | 2169 | { |
5a8f40e8 | 2170 | struct dmar_domain *found = NULL; |
745f2586 JL |
2171 | struct device_domain_info *info; |
2172 | unsigned long flags; | |
2173 | ||
2174 | info = alloc_devinfo_mem(); | |
2175 | if (!info) | |
b718cd3d | 2176 | return NULL; |
745f2586 | 2177 | |
745f2586 JL |
2178 | info->bus = bus; |
2179 | info->devfn = devfn; | |
2180 | info->dev = dev; | |
2181 | info->domain = domain; | |
5a8f40e8 | 2182 | info->iommu = iommu; |
745f2586 JL |
2183 | if (!dev) |
2184 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; | |
2185 | ||
2186 | spin_lock_irqsave(&device_domain_lock, flags); | |
2187 | if (dev) | |
0bcb3e28 | 2188 | found = find_domain(dev); |
5a8f40e8 DW |
2189 | else { |
2190 | struct device_domain_info *info2; | |
41e80dca | 2191 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
5a8f40e8 DW |
2192 | if (info2) |
2193 | found = info2->domain; | |
2194 | } | |
745f2586 JL |
2195 | if (found) { |
2196 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2197 | free_devinfo_mem(info); | |
b718cd3d DW |
2198 | /* Caller must free the original domain */ |
2199 | return found; | |
745f2586 JL |
2200 | } |
2201 | ||
b718cd3d DW |
2202 | list_add(&info->link, &domain->devices); |
2203 | list_add(&info->global, &device_domain_list); | |
2204 | if (dev) | |
2205 | dev->archdata.iommu = info; | |
2206 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2207 | ||
2208 | return domain; | |
745f2586 JL |
2209 | } |
2210 | ||
ba395927 | 2211 | /* domain is initialized */ |
146922ec | 2212 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
ba395927 | 2213 | { |
e85bb5d4 | 2214 | struct dmar_domain *domain, *free = NULL; |
5a8f40e8 DW |
2215 | struct intel_iommu *iommu = NULL; |
2216 | struct device_domain_info *info; | |
146922ec | 2217 | struct pci_dev *dev_tmp = NULL; |
ba395927 | 2218 | unsigned long flags; |
146922ec | 2219 | u8 bus, devfn, bridge_bus, bridge_devfn; |
ba395927 | 2220 | |
146922ec | 2221 | domain = find_domain(dev); |
ba395927 KA |
2222 | if (domain) |
2223 | return domain; | |
2224 | ||
146922ec DW |
2225 | if (dev_is_pci(dev)) { |
2226 | struct pci_dev *pdev = to_pci_dev(dev); | |
2227 | u16 segment; | |
276dbf99 | 2228 | |
146922ec DW |
2229 | segment = pci_domain_nr(pdev->bus); |
2230 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); | |
2231 | if (dev_tmp) { | |
2232 | if (pci_is_pcie(dev_tmp)) { | |
2233 | bridge_bus = dev_tmp->subordinate->number; | |
2234 | bridge_devfn = 0; | |
2235 | } else { | |
2236 | bridge_bus = dev_tmp->bus->number; | |
2237 | bridge_devfn = dev_tmp->devfn; | |
2238 | } | |
2239 | spin_lock_irqsave(&device_domain_lock, flags); | |
9f05d3fb DW |
2240 | info = dmar_search_domain_by_dev_info(segment, |
2241 | bridge_bus, | |
2242 | bridge_devfn); | |
146922ec DW |
2243 | if (info) { |
2244 | iommu = info->iommu; | |
2245 | domain = info->domain; | |
2246 | } | |
2247 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2248 | /* pcie-pci bridge already has a domain, uses it */ | |
2249 | if (info) | |
2250 | goto found_domain; | |
5a8f40e8 | 2251 | } |
ba395927 KA |
2252 | } |
2253 | ||
146922ec DW |
2254 | iommu = device_to_iommu(dev, &bus, &devfn); |
2255 | if (!iommu) | |
2256 | goto error; | |
ba395927 | 2257 | |
146922ec | 2258 | /* Allocate and initialize new domain for the device */ |
92d03cc8 | 2259 | domain = alloc_domain(false); |
745f2586 JL |
2260 | if (!domain) |
2261 | goto error; | |
2262 | if (iommu_attach_domain(domain, iommu)) { | |
2fe9723d | 2263 | free_domain_mem(domain); |
14d40569 | 2264 | domain = NULL; |
ba395927 | 2265 | goto error; |
2c2e2c38 | 2266 | } |
e85bb5d4 JL |
2267 | free = domain; |
2268 | if (domain_init(domain, gaw)) | |
ba395927 | 2269 | goto error; |
ba395927 KA |
2270 | |
2271 | /* register pcie-to-pci device */ | |
2272 | if (dev_tmp) { | |
146922ec DW |
2273 | domain = dmar_insert_dev_info(iommu, bridge_bus, bridge_devfn, |
2274 | NULL, domain); | |
b718cd3d | 2275 | if (!domain) |
ba395927 | 2276 | goto error; |
ba395927 KA |
2277 | } |
2278 | ||
2279 | found_domain: | |
146922ec | 2280 | domain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
ba395927 | 2281 | error: |
b718cd3d | 2282 | if (free != domain) |
e85bb5d4 | 2283 | domain_exit(free); |
b718cd3d DW |
2284 | |
2285 | return domain; | |
ba395927 KA |
2286 | } |
2287 | ||
2c2e2c38 | 2288 | static int iommu_identity_mapping; |
e0fc7e0b DW |
2289 | #define IDENTMAP_ALL 1 |
2290 | #define IDENTMAP_GFX 2 | |
2291 | #define IDENTMAP_AZALIA 4 | |
2c2e2c38 | 2292 | |
b213203e DW |
2293 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
2294 | unsigned long long start, | |
2295 | unsigned long long end) | |
ba395927 | 2296 | { |
c5395d5c DW |
2297 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
2298 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
2299 | ||
2300 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
2301 | dma_to_mm_pfn(last_vpfn))) { | |
ba395927 | 2302 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
b213203e | 2303 | return -ENOMEM; |
ba395927 KA |
2304 | } |
2305 | ||
c5395d5c DW |
2306 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
2307 | start, end, domain->id); | |
ba395927 KA |
2308 | /* |
2309 | * RMRR range might have overlap with physical memory range, | |
2310 | * clear it first | |
2311 | */ | |
c5395d5c | 2312 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 2313 | |
c5395d5c DW |
2314 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
2315 | last_vpfn - first_vpfn + 1, | |
61df7443 | 2316 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
2317 | } |
2318 | ||
0b9d9753 | 2319 | static int iommu_prepare_identity_map(struct device *dev, |
b213203e DW |
2320 | unsigned long long start, |
2321 | unsigned long long end) | |
2322 | { | |
2323 | struct dmar_domain *domain; | |
2324 | int ret; | |
2325 | ||
0b9d9753 | 2326 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
2327 | if (!domain) |
2328 | return -ENOMEM; | |
2329 | ||
19943b0e DW |
2330 | /* For _hardware_ passthrough, don't bother. But for software |
2331 | passthrough, we do it anyway -- it may indicate a memory | |
2332 | range which is reserved in E820, so which didn't get set | |
2333 | up to start with in si_domain */ | |
2334 | if (domain == si_domain && hw_pass_through) { | |
2335 | printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", | |
0b9d9753 | 2336 | dev_name(dev), start, end); |
19943b0e DW |
2337 | return 0; |
2338 | } | |
2339 | ||
2340 | printk(KERN_INFO | |
2341 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
0b9d9753 | 2342 | dev_name(dev), start, end); |
2ff729f5 | 2343 | |
5595b528 DW |
2344 | if (end < start) { |
2345 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" | |
2346 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2347 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2348 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2349 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2350 | ret = -EIO; | |
2351 | goto error; | |
2352 | } | |
2353 | ||
2ff729f5 DW |
2354 | if (end >> agaw_to_width(domain->agaw)) { |
2355 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" | |
2356 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2357 | agaw_to_width(domain->agaw), | |
2358 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2359 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2360 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2361 | ret = -EIO; | |
2362 | goto error; | |
2363 | } | |
19943b0e | 2364 | |
b213203e | 2365 | ret = iommu_domain_identity_map(domain, start, end); |
ba395927 KA |
2366 | if (ret) |
2367 | goto error; | |
2368 | ||
2369 | /* context entry init */ | |
0b9d9753 | 2370 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
2371 | if (ret) |
2372 | goto error; | |
2373 | ||
2374 | return 0; | |
2375 | ||
2376 | error: | |
ba395927 KA |
2377 | domain_exit(domain); |
2378 | return ret; | |
ba395927 KA |
2379 | } |
2380 | ||
2381 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
0b9d9753 | 2382 | struct device *dev) |
ba395927 | 2383 | { |
0b9d9753 | 2384 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 | 2385 | return 0; |
0b9d9753 DW |
2386 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
2387 | rmrr->end_address); | |
ba395927 KA |
2388 | } |
2389 | ||
d3f13810 | 2390 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
49a0429e KA |
2391 | static inline void iommu_prepare_isa(void) |
2392 | { | |
2393 | struct pci_dev *pdev; | |
2394 | int ret; | |
2395 | ||
2396 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
2397 | if (!pdev) | |
2398 | return; | |
2399 | ||
c7ab48d2 | 2400 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
0b9d9753 | 2401 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
49a0429e KA |
2402 | |
2403 | if (ret) | |
c7ab48d2 DW |
2404 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
2405 | "floppy might not work\n"); | |
49a0429e KA |
2406 | |
2407 | } | |
2408 | #else | |
2409 | static inline void iommu_prepare_isa(void) | |
2410 | { | |
2411 | return; | |
2412 | } | |
d3f13810 | 2413 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
49a0429e | 2414 | |
2c2e2c38 | 2415 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 | 2416 | |
071e1374 | 2417 | static int __init si_domain_init(int hw) |
2c2e2c38 FY |
2418 | { |
2419 | struct dmar_drhd_unit *drhd; | |
2420 | struct intel_iommu *iommu; | |
c7ab48d2 | 2421 | int nid, ret = 0; |
2c2e2c38 | 2422 | |
92d03cc8 | 2423 | si_domain = alloc_domain(false); |
2c2e2c38 FY |
2424 | if (!si_domain) |
2425 | return -EFAULT; | |
2426 | ||
92d03cc8 JL |
2427 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; |
2428 | ||
2c2e2c38 FY |
2429 | for_each_active_iommu(iommu, drhd) { |
2430 | ret = iommu_attach_domain(si_domain, iommu); | |
2431 | if (ret) { | |
2432 | domain_exit(si_domain); | |
2433 | return -EFAULT; | |
2434 | } | |
2435 | } | |
2436 | ||
2437 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2438 | domain_exit(si_domain); | |
2439 | return -EFAULT; | |
2440 | } | |
2441 | ||
9544c003 JL |
2442 | pr_debug("IOMMU: identity mapping domain is domain %d\n", |
2443 | si_domain->id); | |
2c2e2c38 | 2444 | |
19943b0e DW |
2445 | if (hw) |
2446 | return 0; | |
2447 | ||
c7ab48d2 | 2448 | for_each_online_node(nid) { |
5dfe8660 TH |
2449 | unsigned long start_pfn, end_pfn; |
2450 | int i; | |
2451 | ||
2452 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { | |
2453 | ret = iommu_domain_identity_map(si_domain, | |
2454 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); | |
2455 | if (ret) | |
2456 | return ret; | |
2457 | } | |
c7ab48d2 DW |
2458 | } |
2459 | ||
2c2e2c38 FY |
2460 | return 0; |
2461 | } | |
2462 | ||
9b226624 | 2463 | static int identity_mapping(struct device *dev) |
2c2e2c38 FY |
2464 | { |
2465 | struct device_domain_info *info; | |
2466 | ||
2467 | if (likely(!iommu_identity_mapping)) | |
2468 | return 0; | |
2469 | ||
9b226624 | 2470 | info = dev->archdata.iommu; |
cb452a40 MT |
2471 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
2472 | return (info->domain == si_domain); | |
2c2e2c38 | 2473 | |
2c2e2c38 FY |
2474 | return 0; |
2475 | } | |
2476 | ||
2477 | static int domain_add_dev_info(struct dmar_domain *domain, | |
5913c9bf | 2478 | struct device *dev, int translation) |
2c2e2c38 | 2479 | { |
0ac72664 | 2480 | struct dmar_domain *ndomain; |
5a8f40e8 | 2481 | struct intel_iommu *iommu; |
156baca8 | 2482 | u8 bus, devfn; |
5fe60f4e | 2483 | int ret; |
2c2e2c38 | 2484 | |
5913c9bf | 2485 | iommu = device_to_iommu(dev, &bus, &devfn); |
5a8f40e8 DW |
2486 | if (!iommu) |
2487 | return -ENODEV; | |
2488 | ||
5913c9bf | 2489 | ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
0ac72664 DW |
2490 | if (ndomain != domain) |
2491 | return -EBUSY; | |
2c2e2c38 | 2492 | |
5913c9bf | 2493 | ret = domain_context_mapping(domain, dev, translation); |
e2ad23d0 | 2494 | if (ret) { |
5913c9bf | 2495 | domain_remove_one_dev_info(domain, dev); |
e2ad23d0 DW |
2496 | return ret; |
2497 | } | |
2498 | ||
2c2e2c38 FY |
2499 | return 0; |
2500 | } | |
2501 | ||
0b9d9753 | 2502 | static bool device_has_rmrr(struct device *dev) |
ea2447f7 TM |
2503 | { |
2504 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2505 | struct device *tmp; |
ea2447f7 TM |
2506 | int i; |
2507 | ||
0e242612 | 2508 | rcu_read_lock(); |
ea2447f7 | 2509 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
2510 | /* |
2511 | * Return TRUE if this RMRR contains the device that | |
2512 | * is passed in. | |
2513 | */ | |
2514 | for_each_active_dev_scope(rmrr->devices, | |
2515 | rmrr->devices_cnt, i, tmp) | |
0b9d9753 | 2516 | if (tmp == dev) { |
0e242612 | 2517 | rcu_read_unlock(); |
ea2447f7 | 2518 | return true; |
b683b230 | 2519 | } |
ea2447f7 | 2520 | } |
0e242612 | 2521 | rcu_read_unlock(); |
ea2447f7 TM |
2522 | return false; |
2523 | } | |
2524 | ||
3bdb2591 | 2525 | static int iommu_should_identity_map(struct device *dev, int startup) |
6941af28 | 2526 | { |
ea2447f7 | 2527 | |
3bdb2591 DW |
2528 | if (dev_is_pci(dev)) { |
2529 | struct pci_dev *pdev = to_pci_dev(dev); | |
ea2447f7 | 2530 | |
3bdb2591 DW |
2531 | /* |
2532 | * We want to prevent any device associated with an RMRR from | |
2533 | * getting placed into the SI Domain. This is done because | |
2534 | * problems exist when devices are moved in and out of domains | |
2535 | * and their respective RMRR info is lost. We exempt USB devices | |
2536 | * from this process due to their usage of RMRRs that are known | |
2537 | * to not be needed after BIOS hand-off to OS. | |
2538 | */ | |
2539 | if (device_has_rmrr(dev) && | |
2540 | (pdev->class >> 8) != PCI_CLASS_SERIAL_USB) | |
2541 | return 0; | |
e0fc7e0b | 2542 | |
3bdb2591 DW |
2543 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
2544 | return 1; | |
e0fc7e0b | 2545 | |
3bdb2591 DW |
2546 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
2547 | return 1; | |
6941af28 | 2548 | |
3bdb2591 | 2549 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
3dfc813d | 2550 | return 0; |
3bdb2591 DW |
2551 | |
2552 | /* | |
2553 | * We want to start off with all devices in the 1:1 domain, and | |
2554 | * take them out later if we find they can't access all of memory. | |
2555 | * | |
2556 | * However, we can't do this for PCI devices behind bridges, | |
2557 | * because all PCI devices behind the same bridge will end up | |
2558 | * with the same source-id on their transactions. | |
2559 | * | |
2560 | * Practically speaking, we can't change things around for these | |
2561 | * devices at run-time, because we can't be sure there'll be no | |
2562 | * DMA transactions in flight for any of their siblings. | |
2563 | * | |
2564 | * So PCI devices (unless they're on the root bus) as well as | |
2565 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of | |
2566 | * the 1:1 domain, just in _case_ one of their siblings turns out | |
2567 | * not to be able to map all of memory. | |
2568 | */ | |
2569 | if (!pci_is_pcie(pdev)) { | |
2570 | if (!pci_is_root_bus(pdev->bus)) | |
2571 | return 0; | |
2572 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) | |
2573 | return 0; | |
2574 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
3dfc813d | 2575 | return 0; |
3bdb2591 DW |
2576 | } else { |
2577 | if (device_has_rmrr(dev)) | |
2578 | return 0; | |
2579 | } | |
3dfc813d | 2580 | |
3bdb2591 | 2581 | /* |
3dfc813d | 2582 | * At boot time, we don't yet know if devices will be 64-bit capable. |
3bdb2591 | 2583 | * Assume that they will — if they turn out not to be, then we can |
3dfc813d DW |
2584 | * take them out of the 1:1 domain later. |
2585 | */ | |
8fcc5372 CW |
2586 | if (!startup) { |
2587 | /* | |
2588 | * If the device's dma_mask is less than the system's memory | |
2589 | * size then this is not a candidate for identity mapping. | |
2590 | */ | |
3bdb2591 | 2591 | u64 dma_mask = *dev->dma_mask; |
8fcc5372 | 2592 | |
3bdb2591 DW |
2593 | if (dev->coherent_dma_mask && |
2594 | dev->coherent_dma_mask < dma_mask) | |
2595 | dma_mask = dev->coherent_dma_mask; | |
8fcc5372 | 2596 | |
3bdb2591 | 2597 | return dma_mask >= dma_get_required_mask(dev); |
8fcc5372 | 2598 | } |
6941af28 DW |
2599 | |
2600 | return 1; | |
2601 | } | |
2602 | ||
cf04eee8 DW |
2603 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
2604 | { | |
2605 | int ret; | |
2606 | ||
2607 | if (!iommu_should_identity_map(dev, 1)) | |
2608 | return 0; | |
2609 | ||
2610 | ret = domain_add_dev_info(si_domain, dev, | |
2611 | hw ? CONTEXT_TT_PASS_THROUGH : | |
2612 | CONTEXT_TT_MULTI_LEVEL); | |
2613 | if (!ret) | |
2614 | pr_info("IOMMU: %s identity mapping for device %s\n", | |
2615 | hw ? "hardware" : "software", dev_name(dev)); | |
2616 | else if (ret == -ENODEV) | |
2617 | /* device not associated with an iommu */ | |
2618 | ret = 0; | |
2619 | ||
2620 | return ret; | |
2621 | } | |
2622 | ||
2623 | ||
071e1374 | 2624 | static int __init iommu_prepare_static_identity_mapping(int hw) |
2c2e2c38 | 2625 | { |
2c2e2c38 | 2626 | struct pci_dev *pdev = NULL; |
cf04eee8 DW |
2627 | struct dmar_drhd_unit *drhd; |
2628 | struct intel_iommu *iommu; | |
2629 | struct device *dev; | |
2630 | int i; | |
2631 | int ret = 0; | |
2c2e2c38 | 2632 | |
19943b0e | 2633 | ret = si_domain_init(hw); |
2c2e2c38 FY |
2634 | if (ret) |
2635 | return -EFAULT; | |
2636 | ||
2c2e2c38 | 2637 | for_each_pci_dev(pdev) { |
cf04eee8 DW |
2638 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
2639 | if (ret) | |
2640 | return ret; | |
2641 | } | |
2642 | ||
2643 | for_each_active_iommu(iommu, drhd) | |
2644 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { | |
2645 | struct acpi_device_physical_node *pn; | |
2646 | struct acpi_device *adev; | |
2647 | ||
2648 | if (dev->bus != &acpi_bus_type) | |
2649 | continue; | |
2650 | ||
2651 | adev= to_acpi_device(dev); | |
2652 | mutex_lock(&adev->physical_node_lock); | |
2653 | list_for_each_entry(pn, &adev->physical_node_list, node) { | |
2654 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); | |
2655 | if (ret) | |
2656 | break; | |
eae460b6 | 2657 | } |
cf04eee8 DW |
2658 | mutex_unlock(&adev->physical_node_lock); |
2659 | if (ret) | |
2660 | return ret; | |
62edf5dc | 2661 | } |
2c2e2c38 FY |
2662 | |
2663 | return 0; | |
2664 | } | |
2665 | ||
b779260b | 2666 | static int __init init_dmars(void) |
ba395927 KA |
2667 | { |
2668 | struct dmar_drhd_unit *drhd; | |
2669 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2670 | struct device *dev; |
ba395927 | 2671 | struct intel_iommu *iommu; |
9d783ba0 | 2672 | int i, ret; |
2c2e2c38 | 2673 | |
ba395927 KA |
2674 | /* |
2675 | * for each drhd | |
2676 | * allocate root | |
2677 | * initialize and program root entry to not present | |
2678 | * endfor | |
2679 | */ | |
2680 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2681 | /* |
2682 | * lock not needed as this is only incremented in the single | |
2683 | * threaded kernel __init code path all other access are read | |
2684 | * only | |
2685 | */ | |
1b198bb0 MT |
2686 | if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) { |
2687 | g_num_of_iommus++; | |
2688 | continue; | |
2689 | } | |
2690 | printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n", | |
2691 | IOMMU_UNITS_SUPPORTED); | |
5e0d2a6f | 2692 | } |
2693 | ||
d9630fe9 WH |
2694 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2695 | GFP_KERNEL); | |
2696 | if (!g_iommus) { | |
2697 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2698 | ret = -ENOMEM; | |
2699 | goto error; | |
2700 | } | |
2701 | ||
80b20dd8 | 2702 | deferred_flush = kzalloc(g_num_of_iommus * |
2703 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2704 | if (!deferred_flush) { | |
5e0d2a6f | 2705 | ret = -ENOMEM; |
989d51fc | 2706 | goto free_g_iommus; |
5e0d2a6f | 2707 | } |
2708 | ||
7c919779 | 2709 | for_each_active_iommu(iommu, drhd) { |
d9630fe9 | 2710 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2711 | |
e61d98d8 SS |
2712 | ret = iommu_init_domains(iommu); |
2713 | if (ret) | |
989d51fc | 2714 | goto free_iommu; |
e61d98d8 | 2715 | |
ba395927 KA |
2716 | /* |
2717 | * TBD: | |
2718 | * we could share the same root & context tables | |
25985edc | 2719 | * among all IOMMU's. Need to Split it later. |
ba395927 KA |
2720 | */ |
2721 | ret = iommu_alloc_root_entry(iommu); | |
2722 | if (ret) { | |
2723 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
989d51fc | 2724 | goto free_iommu; |
ba395927 | 2725 | } |
4ed0d3e6 | 2726 | if (!ecap_pass_through(iommu->ecap)) |
19943b0e | 2727 | hw_pass_through = 0; |
ba395927 KA |
2728 | } |
2729 | ||
1531a6a6 SS |
2730 | /* |
2731 | * Start from the sane iommu hardware state. | |
2732 | */ | |
7c919779 | 2733 | for_each_active_iommu(iommu, drhd) { |
1531a6a6 SS |
2734 | /* |
2735 | * If the queued invalidation is already initialized by us | |
2736 | * (for example, while enabling interrupt-remapping) then | |
2737 | * we got the things already rolling from a sane state. | |
2738 | */ | |
2739 | if (iommu->qi) | |
2740 | continue; | |
2741 | ||
2742 | /* | |
2743 | * Clear any previous faults. | |
2744 | */ | |
2745 | dmar_fault(-1, iommu); | |
2746 | /* | |
2747 | * Disable queued invalidation if supported and already enabled | |
2748 | * before OS handover. | |
2749 | */ | |
2750 | dmar_disable_qi(iommu); | |
2751 | } | |
2752 | ||
7c919779 | 2753 | for_each_active_iommu(iommu, drhd) { |
a77b67d4 YS |
2754 | if (dmar_enable_qi(iommu)) { |
2755 | /* | |
2756 | * Queued Invalidate not enabled, use Register Based | |
2757 | * Invalidate | |
2758 | */ | |
2759 | iommu->flush.flush_context = __iommu_flush_context; | |
2760 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
680a7524 | 2761 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " |
b4e0f9eb | 2762 | "invalidation\n", |
680a7524 | 2763 | iommu->seq_id, |
b4e0f9eb | 2764 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2765 | } else { |
2766 | iommu->flush.flush_context = qi_flush_context; | |
2767 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
680a7524 | 2768 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " |
b4e0f9eb | 2769 | "invalidation\n", |
680a7524 | 2770 | iommu->seq_id, |
b4e0f9eb | 2771 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2772 | } |
2773 | } | |
2774 | ||
19943b0e | 2775 | if (iommu_pass_through) |
e0fc7e0b DW |
2776 | iommu_identity_mapping |= IDENTMAP_ALL; |
2777 | ||
d3f13810 | 2778 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
e0fc7e0b | 2779 | iommu_identity_mapping |= IDENTMAP_GFX; |
19943b0e | 2780 | #endif |
e0fc7e0b DW |
2781 | |
2782 | check_tylersburg_isoch(); | |
2783 | ||
ba395927 | 2784 | /* |
19943b0e DW |
2785 | * If pass through is not set or not enabled, setup context entries for |
2786 | * identity mappings for rmrr, gfx, and isa and may fall back to static | |
2787 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2788 | */ |
19943b0e DW |
2789 | if (iommu_identity_mapping) { |
2790 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); | |
4ed0d3e6 | 2791 | if (ret) { |
19943b0e | 2792 | printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); |
989d51fc | 2793 | goto free_iommu; |
ba395927 KA |
2794 | } |
2795 | } | |
ba395927 | 2796 | /* |
19943b0e DW |
2797 | * For each rmrr |
2798 | * for each dev attached to rmrr | |
2799 | * do | |
2800 | * locate drhd for dev, alloc domain for dev | |
2801 | * allocate free domain | |
2802 | * allocate page table entries for rmrr | |
2803 | * if context not allocated for bus | |
2804 | * allocate and init context | |
2805 | * set present in root table for this bus | |
2806 | * init context with domain, translation etc | |
2807 | * endfor | |
2808 | * endfor | |
ba395927 | 2809 | */ |
19943b0e DW |
2810 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
2811 | for_each_rmrr_units(rmrr) { | |
b683b230 JL |
2812 | /* some BIOS lists non-exist devices in DMAR table. */ |
2813 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, | |
832bd858 | 2814 | i, dev) { |
0b9d9753 | 2815 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
19943b0e DW |
2816 | if (ret) |
2817 | printk(KERN_ERR | |
2818 | "IOMMU: mapping reserved region failed\n"); | |
ba395927 | 2819 | } |
4ed0d3e6 | 2820 | } |
49a0429e | 2821 | |
19943b0e DW |
2822 | iommu_prepare_isa(); |
2823 | ||
ba395927 KA |
2824 | /* |
2825 | * for each drhd | |
2826 | * enable fault log | |
2827 | * global invalidate context cache | |
2828 | * global invalidate iotlb | |
2829 | * enable translation | |
2830 | */ | |
7c919779 | 2831 | for_each_iommu(iommu, drhd) { |
51a63e67 JC |
2832 | if (drhd->ignored) { |
2833 | /* | |
2834 | * we always have to disable PMRs or DMA may fail on | |
2835 | * this device | |
2836 | */ | |
2837 | if (force_on) | |
7c919779 | 2838 | iommu_disable_protect_mem_regions(iommu); |
ba395927 | 2839 | continue; |
51a63e67 | 2840 | } |
ba395927 KA |
2841 | |
2842 | iommu_flush_write_buffer(iommu); | |
2843 | ||
3460a6d9 KA |
2844 | ret = dmar_set_interrupt(iommu); |
2845 | if (ret) | |
989d51fc | 2846 | goto free_iommu; |
3460a6d9 | 2847 | |
ba395927 KA |
2848 | iommu_set_root_entry(iommu); |
2849 | ||
4c25a2c1 | 2850 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2851 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
f8bab735 | 2852 | |
ba395927 KA |
2853 | ret = iommu_enable_translation(iommu); |
2854 | if (ret) | |
989d51fc | 2855 | goto free_iommu; |
b94996c9 DW |
2856 | |
2857 | iommu_disable_protect_mem_regions(iommu); | |
ba395927 KA |
2858 | } |
2859 | ||
2860 | return 0; | |
989d51fc JL |
2861 | |
2862 | free_iommu: | |
7c919779 | 2863 | for_each_active_iommu(iommu, drhd) |
a868e6b7 | 2864 | free_dmar_iommu(iommu); |
9bdc531e | 2865 | kfree(deferred_flush); |
989d51fc | 2866 | free_g_iommus: |
d9630fe9 | 2867 | kfree(g_iommus); |
989d51fc | 2868 | error: |
ba395927 KA |
2869 | return ret; |
2870 | } | |
2871 | ||
5a5e02a6 | 2872 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
2873 | static struct iova *intel_alloc_iova(struct device *dev, |
2874 | struct dmar_domain *domain, | |
2875 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 2876 | { |
ba395927 | 2877 | struct iova *iova = NULL; |
ba395927 | 2878 | |
875764de DW |
2879 | /* Restrict dma_mask to the width that the iommu can handle */ |
2880 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
2881 | ||
2882 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
2883 | /* |
2884 | * First try to allocate an io virtual address in | |
284901a9 | 2885 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2886 | * from higher range |
ba395927 | 2887 | */ |
875764de DW |
2888 | iova = alloc_iova(&domain->iovad, nrpages, |
2889 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
2890 | if (iova) | |
2891 | return iova; | |
2892 | } | |
2893 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
2894 | if (unlikely(!iova)) { | |
2895 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", | |
207e3592 | 2896 | nrpages, dev_name(dev)); |
f76aec76 KA |
2897 | return NULL; |
2898 | } | |
2899 | ||
2900 | return iova; | |
2901 | } | |
2902 | ||
d4b709f4 | 2903 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
f76aec76 KA |
2904 | { |
2905 | struct dmar_domain *domain; | |
2906 | int ret; | |
2907 | ||
d4b709f4 | 2908 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
f76aec76 | 2909 | if (!domain) { |
d4b709f4 DW |
2910 | printk(KERN_ERR "Allocating domain for %s failed", |
2911 | dev_name(dev)); | |
4fe05bbc | 2912 | return NULL; |
ba395927 KA |
2913 | } |
2914 | ||
2915 | /* make sure context mapping is ok */ | |
d4b709f4 DW |
2916 | if (unlikely(!domain_context_mapped(dev))) { |
2917 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 | 2918 | if (ret) { |
d4b709f4 DW |
2919 | printk(KERN_ERR "Domain context map for %s failed", |
2920 | dev_name(dev)); | |
4fe05bbc | 2921 | return NULL; |
f76aec76 | 2922 | } |
ba395927 KA |
2923 | } |
2924 | ||
f76aec76 KA |
2925 | return domain; |
2926 | } | |
2927 | ||
d4b709f4 | 2928 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
147202aa DW |
2929 | { |
2930 | struct device_domain_info *info; | |
2931 | ||
2932 | /* No lock here, assumes no domain exit in normal case */ | |
d4b709f4 | 2933 | info = dev->archdata.iommu; |
147202aa DW |
2934 | if (likely(info)) |
2935 | return info->domain; | |
2936 | ||
2937 | return __get_valid_domain_for_dev(dev); | |
2938 | } | |
2939 | ||
3d89194a | 2940 | static int iommu_dummy(struct device *dev) |
2c2e2c38 | 2941 | { |
3d89194a | 2942 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
2c2e2c38 FY |
2943 | } |
2944 | ||
ecb509ec | 2945 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
73676832 | 2946 | static int iommu_no_mapping(struct device *dev) |
2c2e2c38 FY |
2947 | { |
2948 | int found; | |
2949 | ||
3d89194a | 2950 | if (iommu_dummy(dev)) |
1e4c64c4 DW |
2951 | return 1; |
2952 | ||
2c2e2c38 | 2953 | if (!iommu_identity_mapping) |
1e4c64c4 | 2954 | return 0; |
2c2e2c38 | 2955 | |
9b226624 | 2956 | found = identity_mapping(dev); |
2c2e2c38 | 2957 | if (found) { |
ecb509ec | 2958 | if (iommu_should_identity_map(dev, 0)) |
2c2e2c38 FY |
2959 | return 1; |
2960 | else { | |
2961 | /* | |
2962 | * 32 bit DMA is removed from si_domain and fall back | |
2963 | * to non-identity mapping. | |
2964 | */ | |
bf9c9eda | 2965 | domain_remove_one_dev_info(si_domain, dev); |
2c2e2c38 | 2966 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", |
ecb509ec | 2967 | dev_name(dev)); |
2c2e2c38 FY |
2968 | return 0; |
2969 | } | |
2970 | } else { | |
2971 | /* | |
2972 | * In case of a detached 64 bit DMA device from vm, the device | |
2973 | * is put into si_domain for identity mapping. | |
2974 | */ | |
ecb509ec | 2975 | if (iommu_should_identity_map(dev, 0)) { |
2c2e2c38 | 2976 | int ret; |
5913c9bf | 2977 | ret = domain_add_dev_info(si_domain, dev, |
5fe60f4e DW |
2978 | hw_pass_through ? |
2979 | CONTEXT_TT_PASS_THROUGH : | |
2980 | CONTEXT_TT_MULTI_LEVEL); | |
2c2e2c38 FY |
2981 | if (!ret) { |
2982 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
ecb509ec | 2983 | dev_name(dev)); |
2c2e2c38 FY |
2984 | return 1; |
2985 | } | |
2986 | } | |
2987 | } | |
2988 | ||
1e4c64c4 | 2989 | return 0; |
2c2e2c38 FY |
2990 | } |
2991 | ||
5040a918 | 2992 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
bb9e6d65 | 2993 | size_t size, int dir, u64 dma_mask) |
f76aec76 | 2994 | { |
f76aec76 | 2995 | struct dmar_domain *domain; |
5b6985ce | 2996 | phys_addr_t start_paddr; |
f76aec76 KA |
2997 | struct iova *iova; |
2998 | int prot = 0; | |
6865f0d1 | 2999 | int ret; |
8c11e798 | 3000 | struct intel_iommu *iommu; |
33041ec0 | 3001 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
f76aec76 KA |
3002 | |
3003 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 3004 | |
5040a918 | 3005 | if (iommu_no_mapping(dev)) |
6865f0d1 | 3006 | return paddr; |
f76aec76 | 3007 | |
5040a918 | 3008 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3009 | if (!domain) |
3010 | return 0; | |
3011 | ||
8c11e798 | 3012 | iommu = domain_get_iommu(domain); |
88cb6a74 | 3013 | size = aligned_nrpages(paddr, size); |
f76aec76 | 3014 | |
5040a918 | 3015 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
f76aec76 KA |
3016 | if (!iova) |
3017 | goto error; | |
3018 | ||
ba395927 KA |
3019 | /* |
3020 | * Check if DMAR supports zero-length reads on write only | |
3021 | * mappings.. | |
3022 | */ | |
3023 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3024 | !cap_zlr(iommu->cap)) |
ba395927 KA |
3025 | prot |= DMA_PTE_READ; |
3026 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3027 | prot |= DMA_PTE_WRITE; | |
3028 | /* | |
6865f0d1 | 3029 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 3030 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 3031 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
3032 | * is not a big problem |
3033 | */ | |
0ab36de2 | 3034 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
33041ec0 | 3035 | mm_to_dma_pfn(paddr_pfn), size, prot); |
ba395927 KA |
3036 | if (ret) |
3037 | goto error; | |
3038 | ||
1f0ef2aa DW |
3039 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3040 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 3041 | iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1); |
1f0ef2aa | 3042 | else |
8c11e798 | 3043 | iommu_flush_write_buffer(iommu); |
f76aec76 | 3044 | |
03d6a246 DW |
3045 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
3046 | start_paddr += paddr & ~PAGE_MASK; | |
3047 | return start_paddr; | |
ba395927 | 3048 | |
ba395927 | 3049 | error: |
f76aec76 KA |
3050 | if (iova) |
3051 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 3052 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5040a918 | 3053 | dev_name(dev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
3054 | return 0; |
3055 | } | |
3056 | ||
ffbbef5c FT |
3057 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
3058 | unsigned long offset, size_t size, | |
3059 | enum dma_data_direction dir, | |
3060 | struct dma_attrs *attrs) | |
bb9e6d65 | 3061 | { |
ffbbef5c | 3062 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
46333e37 | 3063 | dir, *dev->dma_mask); |
bb9e6d65 FT |
3064 | } |
3065 | ||
5e0d2a6f | 3066 | static void flush_unmaps(void) |
3067 | { | |
80b20dd8 | 3068 | int i, j; |
5e0d2a6f | 3069 | |
5e0d2a6f | 3070 | timer_on = 0; |
3071 | ||
3072 | /* just flush them all */ | |
3073 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
3074 | struct intel_iommu *iommu = g_iommus[i]; |
3075 | if (!iommu) | |
3076 | continue; | |
c42d9f32 | 3077 | |
9dd2fe89 YZ |
3078 | if (!deferred_flush[i].next) |
3079 | continue; | |
3080 | ||
78d5f0f5 NA |
3081 | /* In caching mode, global flushes turn emulation expensive */ |
3082 | if (!cap_caching_mode(iommu->cap)) | |
3083 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 3084 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 3085 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
3086 | unsigned long mask; |
3087 | struct iova *iova = deferred_flush[i].iova[j]; | |
78d5f0f5 NA |
3088 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
3089 | ||
3090 | /* On real hardware multiple invalidations are expensive */ | |
3091 | if (cap_caching_mode(iommu->cap)) | |
3092 | iommu_flush_iotlb_psi(iommu, domain->id, | |
ea8ea460 DW |
3093 | iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, |
3094 | !deferred_flush[i].freelist[j], 0); | |
78d5f0f5 NA |
3095 | else { |
3096 | mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1)); | |
3097 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], | |
3098 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); | |
3099 | } | |
93a23a72 | 3100 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
ea8ea460 DW |
3101 | if (deferred_flush[i].freelist[j]) |
3102 | dma_free_pagelist(deferred_flush[i].freelist[j]); | |
80b20dd8 | 3103 | } |
9dd2fe89 | 3104 | deferred_flush[i].next = 0; |
5e0d2a6f | 3105 | } |
3106 | ||
5e0d2a6f | 3107 | list_size = 0; |
5e0d2a6f | 3108 | } |
3109 | ||
3110 | static void flush_unmaps_timeout(unsigned long data) | |
3111 | { | |
80b20dd8 | 3112 | unsigned long flags; |
3113 | ||
3114 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 3115 | flush_unmaps(); |
80b20dd8 | 3116 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 3117 | } |
3118 | ||
ea8ea460 | 3119 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
5e0d2a6f | 3120 | { |
3121 | unsigned long flags; | |
80b20dd8 | 3122 | int next, iommu_id; |
8c11e798 | 3123 | struct intel_iommu *iommu; |
5e0d2a6f | 3124 | |
3125 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 3126 | if (list_size == HIGH_WATER_MARK) |
3127 | flush_unmaps(); | |
3128 | ||
8c11e798 WH |
3129 | iommu = domain_get_iommu(dom); |
3130 | iommu_id = iommu->seq_id; | |
c42d9f32 | 3131 | |
80b20dd8 | 3132 | next = deferred_flush[iommu_id].next; |
3133 | deferred_flush[iommu_id].domain[next] = dom; | |
3134 | deferred_flush[iommu_id].iova[next] = iova; | |
ea8ea460 | 3135 | deferred_flush[iommu_id].freelist[next] = freelist; |
80b20dd8 | 3136 | deferred_flush[iommu_id].next++; |
5e0d2a6f | 3137 | |
3138 | if (!timer_on) { | |
3139 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
3140 | timer_on = 1; | |
3141 | } | |
3142 | list_size++; | |
3143 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
3144 | } | |
3145 | ||
ffbbef5c FT |
3146 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
3147 | size_t size, enum dma_data_direction dir, | |
3148 | struct dma_attrs *attrs) | |
ba395927 | 3149 | { |
f76aec76 | 3150 | struct dmar_domain *domain; |
d794dc9b | 3151 | unsigned long start_pfn, last_pfn; |
ba395927 | 3152 | struct iova *iova; |
8c11e798 | 3153 | struct intel_iommu *iommu; |
ea8ea460 | 3154 | struct page *freelist; |
ba395927 | 3155 | |
73676832 | 3156 | if (iommu_no_mapping(dev)) |
f76aec76 | 3157 | return; |
2c2e2c38 | 3158 | |
1525a29a | 3159 | domain = find_domain(dev); |
ba395927 KA |
3160 | BUG_ON(!domain); |
3161 | ||
8c11e798 WH |
3162 | iommu = domain_get_iommu(domain); |
3163 | ||
ba395927 | 3164 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
3165 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
3166 | (unsigned long long)dev_addr)) | |
ba395927 | 3167 | return; |
ba395927 | 3168 | |
d794dc9b DW |
3169 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3170 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 3171 | |
d794dc9b | 3172 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
207e3592 | 3173 | dev_name(dev), start_pfn, last_pfn); |
ba395927 | 3174 | |
ea8ea460 | 3175 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
d794dc9b | 3176 | |
5e0d2a6f | 3177 | if (intel_iommu_strict) { |
03d6a246 | 3178 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
ea8ea460 | 3179 | last_pfn - start_pfn + 1, !freelist, 0); |
5e0d2a6f | 3180 | /* free iova */ |
3181 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3182 | dma_free_pagelist(freelist); |
5e0d2a6f | 3183 | } else { |
ea8ea460 | 3184 | add_unmap(domain, iova, freelist); |
5e0d2a6f | 3185 | /* |
3186 | * queue up the release of the unmap to save the 1/6th of the | |
3187 | * cpu used up by the iotlb flush operation... | |
3188 | */ | |
5e0d2a6f | 3189 | } |
ba395927 KA |
3190 | } |
3191 | ||
5040a918 | 3192 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
3193 | dma_addr_t *dma_handle, gfp_t flags, |
3194 | struct dma_attrs *attrs) | |
ba395927 KA |
3195 | { |
3196 | void *vaddr; | |
3197 | int order; | |
3198 | ||
5b6985ce | 3199 | size = PAGE_ALIGN(size); |
ba395927 | 3200 | order = get_order(size); |
e8bb910d | 3201 | |
5040a918 | 3202 | if (!iommu_no_mapping(dev)) |
e8bb910d | 3203 | flags &= ~(GFP_DMA | GFP_DMA32); |
5040a918 DW |
3204 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
3205 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) | |
e8bb910d AW |
3206 | flags |= GFP_DMA; |
3207 | else | |
3208 | flags |= GFP_DMA32; | |
3209 | } | |
ba395927 KA |
3210 | |
3211 | vaddr = (void *)__get_free_pages(flags, order); | |
3212 | if (!vaddr) | |
3213 | return NULL; | |
3214 | memset(vaddr, 0, size); | |
3215 | ||
5040a918 | 3216 | *dma_handle = __intel_map_single(dev, virt_to_bus(vaddr), size, |
bb9e6d65 | 3217 | DMA_BIDIRECTIONAL, |
5040a918 | 3218 | dev->coherent_dma_mask); |
ba395927 KA |
3219 | if (*dma_handle) |
3220 | return vaddr; | |
3221 | free_pages((unsigned long)vaddr, order); | |
3222 | return NULL; | |
3223 | } | |
3224 | ||
5040a918 | 3225 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
baa676fc | 3226 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
ba395927 KA |
3227 | { |
3228 | int order; | |
3229 | ||
5b6985ce | 3230 | size = PAGE_ALIGN(size); |
ba395927 KA |
3231 | order = get_order(size); |
3232 | ||
5040a918 | 3233 | intel_unmap_page(dev, dma_handle, size, DMA_BIDIRECTIONAL, NULL); |
ba395927 KA |
3234 | free_pages((unsigned long)vaddr, order); |
3235 | } | |
3236 | ||
5040a918 | 3237 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
d7ab5c46 FT |
3238 | int nelems, enum dma_data_direction dir, |
3239 | struct dma_attrs *attrs) | |
ba395927 | 3240 | { |
ba395927 | 3241 | struct dmar_domain *domain; |
d794dc9b | 3242 | unsigned long start_pfn, last_pfn; |
f76aec76 | 3243 | struct iova *iova; |
8c11e798 | 3244 | struct intel_iommu *iommu; |
ea8ea460 | 3245 | struct page *freelist; |
ba395927 | 3246 | |
5040a918 | 3247 | if (iommu_no_mapping(dev)) |
ba395927 KA |
3248 | return; |
3249 | ||
5040a918 | 3250 | domain = find_domain(dev); |
8c11e798 WH |
3251 | BUG_ON(!domain); |
3252 | ||
3253 | iommu = domain_get_iommu(domain); | |
ba395927 | 3254 | |
c03ab37c | 3255 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
85b98276 DW |
3256 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
3257 | (unsigned long long)sglist[0].dma_address)) | |
f76aec76 | 3258 | return; |
f76aec76 | 3259 | |
d794dc9b DW |
3260 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3261 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
f76aec76 | 3262 | |
ea8ea460 | 3263 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
f76aec76 | 3264 | |
acea0018 DW |
3265 | if (intel_iommu_strict) { |
3266 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, | |
ea8ea460 | 3267 | last_pfn - start_pfn + 1, !freelist, 0); |
acea0018 DW |
3268 | /* free iova */ |
3269 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3270 | dma_free_pagelist(freelist); |
acea0018 | 3271 | } else { |
ea8ea460 | 3272 | add_unmap(domain, iova, freelist); |
acea0018 DW |
3273 | /* |
3274 | * queue up the release of the unmap to save the 1/6th of the | |
3275 | * cpu used up by the iotlb flush operation... | |
3276 | */ | |
3277 | } | |
ba395927 KA |
3278 | } |
3279 | ||
ba395927 | 3280 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 3281 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
3282 | { |
3283 | int i; | |
c03ab37c | 3284 | struct scatterlist *sg; |
ba395927 | 3285 | |
c03ab37c | 3286 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 3287 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 3288 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 3289 | sg->dma_length = sg->length; |
ba395927 KA |
3290 | } |
3291 | return nelems; | |
3292 | } | |
3293 | ||
5040a918 | 3294 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
d7ab5c46 | 3295 | enum dma_data_direction dir, struct dma_attrs *attrs) |
ba395927 | 3296 | { |
ba395927 | 3297 | int i; |
ba395927 | 3298 | struct dmar_domain *domain; |
f76aec76 KA |
3299 | size_t size = 0; |
3300 | int prot = 0; | |
f76aec76 KA |
3301 | struct iova *iova = NULL; |
3302 | int ret; | |
c03ab37c | 3303 | struct scatterlist *sg; |
b536d24d | 3304 | unsigned long start_vpfn; |
8c11e798 | 3305 | struct intel_iommu *iommu; |
ba395927 KA |
3306 | |
3307 | BUG_ON(dir == DMA_NONE); | |
5040a918 DW |
3308 | if (iommu_no_mapping(dev)) |
3309 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); | |
ba395927 | 3310 | |
5040a918 | 3311 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3312 | if (!domain) |
3313 | return 0; | |
3314 | ||
8c11e798 WH |
3315 | iommu = domain_get_iommu(domain); |
3316 | ||
b536d24d | 3317 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 3318 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 3319 | |
5040a918 DW |
3320 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
3321 | *dev->dma_mask); | |
f76aec76 | 3322 | if (!iova) { |
c03ab37c | 3323 | sglist->dma_length = 0; |
f76aec76 KA |
3324 | return 0; |
3325 | } | |
3326 | ||
3327 | /* | |
3328 | * Check if DMAR supports zero-length reads on write only | |
3329 | * mappings.. | |
3330 | */ | |
3331 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3332 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
3333 | prot |= DMA_PTE_READ; |
3334 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3335 | prot |= DMA_PTE_WRITE; | |
3336 | ||
b536d24d | 3337 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 | 3338 | |
f532959b | 3339 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
e1605495 DW |
3340 | if (unlikely(ret)) { |
3341 | /* clear the page */ | |
3342 | dma_pte_clear_range(domain, start_vpfn, | |
3343 | start_vpfn + size - 1); | |
3344 | /* free page tables */ | |
3345 | dma_pte_free_pagetable(domain, start_vpfn, | |
3346 | start_vpfn + size - 1); | |
3347 | /* free iova */ | |
3348 | __free_iova(&domain->iovad, iova); | |
3349 | return 0; | |
ba395927 KA |
3350 | } |
3351 | ||
1f0ef2aa DW |
3352 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3353 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 3354 | iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1); |
1f0ef2aa | 3355 | else |
8c11e798 | 3356 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 3357 | |
ba395927 KA |
3358 | return nelems; |
3359 | } | |
3360 | ||
dfb805e8 FT |
3361 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
3362 | { | |
3363 | return !dma_addr; | |
3364 | } | |
3365 | ||
160c1d8e | 3366 | struct dma_map_ops intel_dma_ops = { |
baa676fc AP |
3367 | .alloc = intel_alloc_coherent, |
3368 | .free = intel_free_coherent, | |
ba395927 KA |
3369 | .map_sg = intel_map_sg, |
3370 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
3371 | .map_page = intel_map_page, |
3372 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 3373 | .mapping_error = intel_mapping_error, |
ba395927 KA |
3374 | }; |
3375 | ||
3376 | static inline int iommu_domain_cache_init(void) | |
3377 | { | |
3378 | int ret = 0; | |
3379 | ||
3380 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
3381 | sizeof(struct dmar_domain), | |
3382 | 0, | |
3383 | SLAB_HWCACHE_ALIGN, | |
3384 | ||
3385 | NULL); | |
3386 | if (!iommu_domain_cache) { | |
3387 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
3388 | ret = -ENOMEM; | |
3389 | } | |
3390 | ||
3391 | return ret; | |
3392 | } | |
3393 | ||
3394 | static inline int iommu_devinfo_cache_init(void) | |
3395 | { | |
3396 | int ret = 0; | |
3397 | ||
3398 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
3399 | sizeof(struct device_domain_info), | |
3400 | 0, | |
3401 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3402 | NULL); |
3403 | if (!iommu_devinfo_cache) { | |
3404 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
3405 | ret = -ENOMEM; | |
3406 | } | |
3407 | ||
3408 | return ret; | |
3409 | } | |
3410 | ||
3411 | static inline int iommu_iova_cache_init(void) | |
3412 | { | |
3413 | int ret = 0; | |
3414 | ||
3415 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
3416 | sizeof(struct iova), | |
3417 | 0, | |
3418 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3419 | NULL); |
3420 | if (!iommu_iova_cache) { | |
3421 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
3422 | ret = -ENOMEM; | |
3423 | } | |
3424 | ||
3425 | return ret; | |
3426 | } | |
3427 | ||
3428 | static int __init iommu_init_mempool(void) | |
3429 | { | |
3430 | int ret; | |
3431 | ret = iommu_iova_cache_init(); | |
3432 | if (ret) | |
3433 | return ret; | |
3434 | ||
3435 | ret = iommu_domain_cache_init(); | |
3436 | if (ret) | |
3437 | goto domain_error; | |
3438 | ||
3439 | ret = iommu_devinfo_cache_init(); | |
3440 | if (!ret) | |
3441 | return ret; | |
3442 | ||
3443 | kmem_cache_destroy(iommu_domain_cache); | |
3444 | domain_error: | |
3445 | kmem_cache_destroy(iommu_iova_cache); | |
3446 | ||
3447 | return -ENOMEM; | |
3448 | } | |
3449 | ||
3450 | static void __init iommu_exit_mempool(void) | |
3451 | { | |
3452 | kmem_cache_destroy(iommu_devinfo_cache); | |
3453 | kmem_cache_destroy(iommu_domain_cache); | |
3454 | kmem_cache_destroy(iommu_iova_cache); | |
3455 | ||
3456 | } | |
3457 | ||
556ab45f DW |
3458 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
3459 | { | |
3460 | struct dmar_drhd_unit *drhd; | |
3461 | u32 vtbar; | |
3462 | int rc; | |
3463 | ||
3464 | /* We know that this device on this chipset has its own IOMMU. | |
3465 | * If we find it under a different IOMMU, then the BIOS is lying | |
3466 | * to us. Hope that the IOMMU for this device is actually | |
3467 | * disabled, and it needs no translation... | |
3468 | */ | |
3469 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); | |
3470 | if (rc) { | |
3471 | /* "can't" happen */ | |
3472 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); | |
3473 | return; | |
3474 | } | |
3475 | vtbar &= 0xffff0000; | |
3476 | ||
3477 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ | |
3478 | drhd = dmar_find_matched_drhd_unit(pdev); | |
3479 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, | |
3480 | TAINT_FIRMWARE_WORKAROUND, | |
3481 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) | |
3482 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; | |
3483 | } | |
3484 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); | |
3485 | ||
ba395927 KA |
3486 | static void __init init_no_remapping_devices(void) |
3487 | { | |
3488 | struct dmar_drhd_unit *drhd; | |
832bd858 | 3489 | struct device *dev; |
b683b230 | 3490 | int i; |
ba395927 KA |
3491 | |
3492 | for_each_drhd_unit(drhd) { | |
3493 | if (!drhd->include_all) { | |
b683b230 JL |
3494 | for_each_active_dev_scope(drhd->devices, |
3495 | drhd->devices_cnt, i, dev) | |
3496 | break; | |
832bd858 | 3497 | /* ignore DMAR unit if no devices exist */ |
ba395927 KA |
3498 | if (i == drhd->devices_cnt) |
3499 | drhd->ignored = 1; | |
3500 | } | |
3501 | } | |
3502 | ||
7c919779 | 3503 | for_each_active_drhd_unit(drhd) { |
7c919779 | 3504 | if (drhd->include_all) |
ba395927 KA |
3505 | continue; |
3506 | ||
b683b230 JL |
3507 | for_each_active_dev_scope(drhd->devices, |
3508 | drhd->devices_cnt, i, dev) | |
832bd858 | 3509 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
ba395927 | 3510 | break; |
ba395927 KA |
3511 | if (i < drhd->devices_cnt) |
3512 | continue; | |
3513 | ||
c0771df8 DW |
3514 | /* This IOMMU has *only* gfx devices. Either bypass it or |
3515 | set the gfx_mapped flag, as appropriate */ | |
3516 | if (dmar_map_gfx) { | |
3517 | intel_iommu_gfx_mapped = 1; | |
3518 | } else { | |
3519 | drhd->ignored = 1; | |
b683b230 JL |
3520 | for_each_active_dev_scope(drhd->devices, |
3521 | drhd->devices_cnt, i, dev) | |
832bd858 | 3522 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
3523 | } |
3524 | } | |
3525 | } | |
3526 | ||
f59c7b69 FY |
3527 | #ifdef CONFIG_SUSPEND |
3528 | static int init_iommu_hw(void) | |
3529 | { | |
3530 | struct dmar_drhd_unit *drhd; | |
3531 | struct intel_iommu *iommu = NULL; | |
3532 | ||
3533 | for_each_active_iommu(iommu, drhd) | |
3534 | if (iommu->qi) | |
3535 | dmar_reenable_qi(iommu); | |
3536 | ||
b779260b JC |
3537 | for_each_iommu(iommu, drhd) { |
3538 | if (drhd->ignored) { | |
3539 | /* | |
3540 | * we always have to disable PMRs or DMA may fail on | |
3541 | * this device | |
3542 | */ | |
3543 | if (force_on) | |
3544 | iommu_disable_protect_mem_regions(iommu); | |
3545 | continue; | |
3546 | } | |
3547 | ||
f59c7b69 FY |
3548 | iommu_flush_write_buffer(iommu); |
3549 | ||
3550 | iommu_set_root_entry(iommu); | |
3551 | ||
3552 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3553 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3554 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3555 | DMA_TLB_GLOBAL_FLUSH); |
b779260b JC |
3556 | if (iommu_enable_translation(iommu)) |
3557 | return 1; | |
b94996c9 | 3558 | iommu_disable_protect_mem_regions(iommu); |
f59c7b69 FY |
3559 | } |
3560 | ||
3561 | return 0; | |
3562 | } | |
3563 | ||
3564 | static void iommu_flush_all(void) | |
3565 | { | |
3566 | struct dmar_drhd_unit *drhd; | |
3567 | struct intel_iommu *iommu; | |
3568 | ||
3569 | for_each_active_iommu(iommu, drhd) { | |
3570 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3571 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3572 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3573 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3574 | } |
3575 | } | |
3576 | ||
134fac3f | 3577 | static int iommu_suspend(void) |
f59c7b69 FY |
3578 | { |
3579 | struct dmar_drhd_unit *drhd; | |
3580 | struct intel_iommu *iommu = NULL; | |
3581 | unsigned long flag; | |
3582 | ||
3583 | for_each_active_iommu(iommu, drhd) { | |
3584 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3585 | GFP_ATOMIC); | |
3586 | if (!iommu->iommu_state) | |
3587 | goto nomem; | |
3588 | } | |
3589 | ||
3590 | iommu_flush_all(); | |
3591 | ||
3592 | for_each_active_iommu(iommu, drhd) { | |
3593 | iommu_disable_translation(iommu); | |
3594 | ||
1f5b3c3f | 3595 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3596 | |
3597 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3598 | readl(iommu->reg + DMAR_FECTL_REG); | |
3599 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3600 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3601 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3602 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3603 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3604 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3605 | ||
1f5b3c3f | 3606 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3607 | } |
3608 | return 0; | |
3609 | ||
3610 | nomem: | |
3611 | for_each_active_iommu(iommu, drhd) | |
3612 | kfree(iommu->iommu_state); | |
3613 | ||
3614 | return -ENOMEM; | |
3615 | } | |
3616 | ||
134fac3f | 3617 | static void iommu_resume(void) |
f59c7b69 FY |
3618 | { |
3619 | struct dmar_drhd_unit *drhd; | |
3620 | struct intel_iommu *iommu = NULL; | |
3621 | unsigned long flag; | |
3622 | ||
3623 | if (init_iommu_hw()) { | |
b779260b JC |
3624 | if (force_on) |
3625 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); | |
3626 | else | |
3627 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
134fac3f | 3628 | return; |
f59c7b69 FY |
3629 | } |
3630 | ||
3631 | for_each_active_iommu(iommu, drhd) { | |
3632 | ||
1f5b3c3f | 3633 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3634 | |
3635 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3636 | iommu->reg + DMAR_FECTL_REG); | |
3637 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3638 | iommu->reg + DMAR_FEDATA_REG); | |
3639 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3640 | iommu->reg + DMAR_FEADDR_REG); | |
3641 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3642 | iommu->reg + DMAR_FEUADDR_REG); | |
3643 | ||
1f5b3c3f | 3644 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3645 | } |
3646 | ||
3647 | for_each_active_iommu(iommu, drhd) | |
3648 | kfree(iommu->iommu_state); | |
f59c7b69 FY |
3649 | } |
3650 | ||
134fac3f | 3651 | static struct syscore_ops iommu_syscore_ops = { |
f59c7b69 FY |
3652 | .resume = iommu_resume, |
3653 | .suspend = iommu_suspend, | |
3654 | }; | |
3655 | ||
134fac3f | 3656 | static void __init init_iommu_pm_ops(void) |
f59c7b69 | 3657 | { |
134fac3f | 3658 | register_syscore_ops(&iommu_syscore_ops); |
f59c7b69 FY |
3659 | } |
3660 | ||
3661 | #else | |
99592ba4 | 3662 | static inline void init_iommu_pm_ops(void) {} |
f59c7b69 FY |
3663 | #endif /* CONFIG_PM */ |
3664 | ||
318fe7df SS |
3665 | |
3666 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header) | |
3667 | { | |
3668 | struct acpi_dmar_reserved_memory *rmrr; | |
3669 | struct dmar_rmrr_unit *rmrru; | |
3670 | ||
3671 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
3672 | if (!rmrru) | |
3673 | return -ENOMEM; | |
3674 | ||
3675 | rmrru->hdr = header; | |
3676 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
3677 | rmrru->base_address = rmrr->base_address; | |
3678 | rmrru->end_address = rmrr->end_address; | |
2e455289 JL |
3679 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
3680 | ((void *)rmrr) + rmrr->header.length, | |
3681 | &rmrru->devices_cnt); | |
3682 | if (rmrru->devices_cnt && rmrru->devices == NULL) { | |
3683 | kfree(rmrru); | |
3684 | return -ENOMEM; | |
3685 | } | |
318fe7df | 3686 | |
2e455289 | 3687 | list_add(&rmrru->list, &dmar_rmrr_units); |
318fe7df | 3688 | |
2e455289 | 3689 | return 0; |
318fe7df SS |
3690 | } |
3691 | ||
318fe7df SS |
3692 | int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr) |
3693 | { | |
3694 | struct acpi_dmar_atsr *atsr; | |
3695 | struct dmar_atsr_unit *atsru; | |
3696 | ||
3697 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
3698 | atsru = kzalloc(sizeof(*atsru), GFP_KERNEL); | |
3699 | if (!atsru) | |
3700 | return -ENOMEM; | |
3701 | ||
3702 | atsru->hdr = hdr; | |
3703 | atsru->include_all = atsr->flags & 0x1; | |
2e455289 JL |
3704 | if (!atsru->include_all) { |
3705 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), | |
3706 | (void *)atsr + atsr->header.length, | |
3707 | &atsru->devices_cnt); | |
3708 | if (atsru->devices_cnt && atsru->devices == NULL) { | |
3709 | kfree(atsru); | |
3710 | return -ENOMEM; | |
3711 | } | |
3712 | } | |
318fe7df | 3713 | |
0e242612 | 3714 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
318fe7df SS |
3715 | |
3716 | return 0; | |
3717 | } | |
3718 | ||
9bdc531e JL |
3719 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
3720 | { | |
3721 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); | |
3722 | kfree(atsru); | |
3723 | } | |
3724 | ||
3725 | static void intel_iommu_free_dmars(void) | |
3726 | { | |
3727 | struct dmar_rmrr_unit *rmrru, *rmrr_n; | |
3728 | struct dmar_atsr_unit *atsru, *atsr_n; | |
3729 | ||
3730 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { | |
3731 | list_del(&rmrru->list); | |
3732 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); | |
3733 | kfree(rmrru); | |
318fe7df SS |
3734 | } |
3735 | ||
9bdc531e JL |
3736 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
3737 | list_del(&atsru->list); | |
3738 | intel_iommu_free_atsr(atsru); | |
3739 | } | |
318fe7df SS |
3740 | } |
3741 | ||
3742 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) | |
3743 | { | |
b683b230 | 3744 | int i, ret = 1; |
318fe7df | 3745 | struct pci_bus *bus; |
832bd858 DW |
3746 | struct pci_dev *bridge = NULL; |
3747 | struct device *tmp; | |
318fe7df SS |
3748 | struct acpi_dmar_atsr *atsr; |
3749 | struct dmar_atsr_unit *atsru; | |
3750 | ||
3751 | dev = pci_physfn(dev); | |
318fe7df | 3752 | for (bus = dev->bus; bus; bus = bus->parent) { |
b5f82ddf | 3753 | bridge = bus->self; |
318fe7df | 3754 | if (!bridge || !pci_is_pcie(bridge) || |
62f87c0e | 3755 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
318fe7df | 3756 | return 0; |
b5f82ddf | 3757 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
318fe7df | 3758 | break; |
318fe7df | 3759 | } |
b5f82ddf JL |
3760 | if (!bridge) |
3761 | return 0; | |
318fe7df | 3762 | |
0e242612 | 3763 | rcu_read_lock(); |
b5f82ddf JL |
3764 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
3765 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3766 | if (atsr->segment != pci_domain_nr(dev->bus)) | |
3767 | continue; | |
3768 | ||
b683b230 | 3769 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
832bd858 | 3770 | if (tmp == &bridge->dev) |
b683b230 | 3771 | goto out; |
b5f82ddf JL |
3772 | |
3773 | if (atsru->include_all) | |
b683b230 | 3774 | goto out; |
b5f82ddf | 3775 | } |
b683b230 JL |
3776 | ret = 0; |
3777 | out: | |
0e242612 | 3778 | rcu_read_unlock(); |
318fe7df | 3779 | |
b683b230 | 3780 | return ret; |
318fe7df SS |
3781 | } |
3782 | ||
59ce0515 JL |
3783 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
3784 | { | |
3785 | int ret = 0; | |
3786 | struct dmar_rmrr_unit *rmrru; | |
3787 | struct dmar_atsr_unit *atsru; | |
3788 | struct acpi_dmar_atsr *atsr; | |
3789 | struct acpi_dmar_reserved_memory *rmrr; | |
3790 | ||
3791 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) | |
3792 | return 0; | |
3793 | ||
3794 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { | |
3795 | rmrr = container_of(rmrru->hdr, | |
3796 | struct acpi_dmar_reserved_memory, header); | |
3797 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3798 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), | |
3799 | ((void *)rmrr) + rmrr->header.length, | |
3800 | rmrr->segment, rmrru->devices, | |
3801 | rmrru->devices_cnt); | |
3802 | if (ret > 0) | |
3803 | break; | |
3804 | else if(ret < 0) | |
3805 | return ret; | |
3806 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
3807 | if (dmar_remove_dev_scope(info, rmrr->segment, | |
3808 | rmrru->devices, rmrru->devices_cnt)) | |
3809 | break; | |
3810 | } | |
3811 | } | |
3812 | ||
3813 | list_for_each_entry(atsru, &dmar_atsr_units, list) { | |
3814 | if (atsru->include_all) | |
3815 | continue; | |
3816 | ||
3817 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3818 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3819 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), | |
3820 | (void *)atsr + atsr->header.length, | |
3821 | atsr->segment, atsru->devices, | |
3822 | atsru->devices_cnt); | |
3823 | if (ret > 0) | |
3824 | break; | |
3825 | else if(ret < 0) | |
3826 | return ret; | |
3827 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
3828 | if (dmar_remove_dev_scope(info, atsr->segment, | |
3829 | atsru->devices, atsru->devices_cnt)) | |
3830 | break; | |
3831 | } | |
3832 | } | |
3833 | ||
3834 | return 0; | |
3835 | } | |
3836 | ||
99dcaded FY |
3837 | /* |
3838 | * Here we only respond to action of unbound device from driver. | |
3839 | * | |
3840 | * Added device is not attached to its DMAR domain here yet. That will happen | |
3841 | * when mapping the device to iova. | |
3842 | */ | |
3843 | static int device_notifier(struct notifier_block *nb, | |
3844 | unsigned long action, void *data) | |
3845 | { | |
3846 | struct device *dev = data; | |
99dcaded FY |
3847 | struct dmar_domain *domain; |
3848 | ||
3d89194a | 3849 | if (iommu_dummy(dev)) |
44cd613c DW |
3850 | return 0; |
3851 | ||
7e7dfab7 JL |
3852 | if (action != BUS_NOTIFY_UNBOUND_DRIVER && |
3853 | action != BUS_NOTIFY_DEL_DEVICE) | |
3854 | return 0; | |
3855 | ||
1525a29a | 3856 | domain = find_domain(dev); |
99dcaded FY |
3857 | if (!domain) |
3858 | return 0; | |
3859 | ||
3a5670e8 | 3860 | down_read(&dmar_global_lock); |
bf9c9eda | 3861 | domain_remove_one_dev_info(domain, dev); |
7e7dfab7 JL |
3862 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && |
3863 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) && | |
3864 | list_empty(&domain->devices)) | |
3865 | domain_exit(domain); | |
3a5670e8 | 3866 | up_read(&dmar_global_lock); |
a97590e5 | 3867 | |
99dcaded FY |
3868 | return 0; |
3869 | } | |
3870 | ||
3871 | static struct notifier_block device_nb = { | |
3872 | .notifier_call = device_notifier, | |
3873 | }; | |
3874 | ||
75f05569 JL |
3875 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
3876 | unsigned long val, void *v) | |
3877 | { | |
3878 | struct memory_notify *mhp = v; | |
3879 | unsigned long long start, end; | |
3880 | unsigned long start_vpfn, last_vpfn; | |
3881 | ||
3882 | switch (val) { | |
3883 | case MEM_GOING_ONLINE: | |
3884 | start = mhp->start_pfn << PAGE_SHIFT; | |
3885 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; | |
3886 | if (iommu_domain_identity_map(si_domain, start, end)) { | |
3887 | pr_warn("dmar: failed to build identity map for [%llx-%llx]\n", | |
3888 | start, end); | |
3889 | return NOTIFY_BAD; | |
3890 | } | |
3891 | break; | |
3892 | ||
3893 | case MEM_OFFLINE: | |
3894 | case MEM_CANCEL_ONLINE: | |
3895 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); | |
3896 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); | |
3897 | while (start_vpfn <= last_vpfn) { | |
3898 | struct iova *iova; | |
3899 | struct dmar_drhd_unit *drhd; | |
3900 | struct intel_iommu *iommu; | |
ea8ea460 | 3901 | struct page *freelist; |
75f05569 JL |
3902 | |
3903 | iova = find_iova(&si_domain->iovad, start_vpfn); | |
3904 | if (iova == NULL) { | |
3905 | pr_debug("dmar: failed get IOVA for PFN %lx\n", | |
3906 | start_vpfn); | |
3907 | break; | |
3908 | } | |
3909 | ||
3910 | iova = split_and_remove_iova(&si_domain->iovad, iova, | |
3911 | start_vpfn, last_vpfn); | |
3912 | if (iova == NULL) { | |
3913 | pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n", | |
3914 | start_vpfn, last_vpfn); | |
3915 | return NOTIFY_BAD; | |
3916 | } | |
3917 | ||
ea8ea460 DW |
3918 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
3919 | iova->pfn_hi); | |
3920 | ||
75f05569 JL |
3921 | rcu_read_lock(); |
3922 | for_each_active_iommu(iommu, drhd) | |
3923 | iommu_flush_iotlb_psi(iommu, si_domain->id, | |
3924 | iova->pfn_lo, | |
ea8ea460 DW |
3925 | iova->pfn_hi - iova->pfn_lo + 1, |
3926 | !freelist, 0); | |
75f05569 | 3927 | rcu_read_unlock(); |
ea8ea460 | 3928 | dma_free_pagelist(freelist); |
75f05569 JL |
3929 | |
3930 | start_vpfn = iova->pfn_hi + 1; | |
3931 | free_iova_mem(iova); | |
3932 | } | |
3933 | break; | |
3934 | } | |
3935 | ||
3936 | return NOTIFY_OK; | |
3937 | } | |
3938 | ||
3939 | static struct notifier_block intel_iommu_memory_nb = { | |
3940 | .notifier_call = intel_iommu_memory_notifier, | |
3941 | .priority = 0 | |
3942 | }; | |
3943 | ||
ba395927 KA |
3944 | int __init intel_iommu_init(void) |
3945 | { | |
9bdc531e | 3946 | int ret = -ENODEV; |
3a93c841 | 3947 | struct dmar_drhd_unit *drhd; |
7c919779 | 3948 | struct intel_iommu *iommu; |
ba395927 | 3949 | |
a59b50e9 JC |
3950 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
3951 | force_on = tboot_force_iommu(); | |
3952 | ||
3a5670e8 JL |
3953 | if (iommu_init_mempool()) { |
3954 | if (force_on) | |
3955 | panic("tboot: Failed to initialize iommu memory\n"); | |
3956 | return -ENOMEM; | |
3957 | } | |
3958 | ||
3959 | down_write(&dmar_global_lock); | |
a59b50e9 JC |
3960 | if (dmar_table_init()) { |
3961 | if (force_on) | |
3962 | panic("tboot: Failed to initialize DMAR table\n"); | |
9bdc531e | 3963 | goto out_free_dmar; |
a59b50e9 | 3964 | } |
ba395927 | 3965 | |
3a93c841 TI |
3966 | /* |
3967 | * Disable translation if already enabled prior to OS handover. | |
3968 | */ | |
7c919779 | 3969 | for_each_active_iommu(iommu, drhd) |
3a93c841 TI |
3970 | if (iommu->gcmd & DMA_GCMD_TE) |
3971 | iommu_disable_translation(iommu); | |
3a93c841 | 3972 | |
c2c7286a | 3973 | if (dmar_dev_scope_init() < 0) { |
a59b50e9 JC |
3974 | if (force_on) |
3975 | panic("tboot: Failed to initialize DMAR device scope\n"); | |
9bdc531e | 3976 | goto out_free_dmar; |
a59b50e9 | 3977 | } |
1886e8a9 | 3978 | |
75f1cdf1 | 3979 | if (no_iommu || dmar_disabled) |
9bdc531e | 3980 | goto out_free_dmar; |
2ae21010 | 3981 | |
318fe7df SS |
3982 | if (list_empty(&dmar_rmrr_units)) |
3983 | printk(KERN_INFO "DMAR: No RMRR found\n"); | |
3984 | ||
3985 | if (list_empty(&dmar_atsr_units)) | |
3986 | printk(KERN_INFO "DMAR: No ATSR found\n"); | |
3987 | ||
51a63e67 JC |
3988 | if (dmar_init_reserved_ranges()) { |
3989 | if (force_on) | |
3990 | panic("tboot: Failed to reserve iommu ranges\n"); | |
3a5670e8 | 3991 | goto out_free_reserved_range; |
51a63e67 | 3992 | } |
ba395927 KA |
3993 | |
3994 | init_no_remapping_devices(); | |
3995 | ||
b779260b | 3996 | ret = init_dmars(); |
ba395927 | 3997 | if (ret) { |
a59b50e9 JC |
3998 | if (force_on) |
3999 | panic("tboot: Failed to initialize DMARs\n"); | |
ba395927 | 4000 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
9bdc531e | 4001 | goto out_free_reserved_range; |
ba395927 | 4002 | } |
3a5670e8 | 4003 | up_write(&dmar_global_lock); |
ba395927 KA |
4004 | printk(KERN_INFO |
4005 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
4006 | ||
5e0d2a6f | 4007 | init_timer(&unmap_timer); |
75f1cdf1 FT |
4008 | #ifdef CONFIG_SWIOTLB |
4009 | swiotlb = 0; | |
4010 | #endif | |
19943b0e | 4011 | dma_ops = &intel_dma_ops; |
4ed0d3e6 | 4012 | |
134fac3f | 4013 | init_iommu_pm_ops(); |
a8bcbb0d | 4014 | |
4236d97d | 4015 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
99dcaded | 4016 | bus_register_notifier(&pci_bus_type, &device_nb); |
75f05569 JL |
4017 | if (si_domain && !hw_pass_through) |
4018 | register_memory_notifier(&intel_iommu_memory_nb); | |
99dcaded | 4019 | |
8bc1f85c ED |
4020 | intel_iommu_enabled = 1; |
4021 | ||
ba395927 | 4022 | return 0; |
9bdc531e JL |
4023 | |
4024 | out_free_reserved_range: | |
4025 | put_iova_domain(&reserved_iova_list); | |
9bdc531e JL |
4026 | out_free_dmar: |
4027 | intel_iommu_free_dmars(); | |
3a5670e8 JL |
4028 | up_write(&dmar_global_lock); |
4029 | iommu_exit_mempool(); | |
9bdc531e | 4030 | return ret; |
ba395927 | 4031 | } |
e820482c | 4032 | |
3199aa6b | 4033 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 4034 | struct device *dev) |
3199aa6b | 4035 | { |
0bcb3e28 | 4036 | struct pci_dev *tmp, *parent, *pdev; |
3199aa6b | 4037 | |
0bcb3e28 | 4038 | if (!iommu || !dev || !dev_is_pci(dev)) |
3199aa6b HW |
4039 | return; |
4040 | ||
0bcb3e28 DW |
4041 | pdev = to_pci_dev(dev); |
4042 | ||
3199aa6b HW |
4043 | /* dependent device detach */ |
4044 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
4045 | /* Secondary interface's bus number and devfn 0 */ | |
4046 | if (tmp) { | |
4047 | parent = pdev->bus->self; | |
4048 | while (parent != tmp) { | |
4049 | iommu_detach_dev(iommu, parent->bus->number, | |
276dbf99 | 4050 | parent->devfn); |
3199aa6b HW |
4051 | parent = parent->bus->self; |
4052 | } | |
45e829ea | 4053 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
3199aa6b HW |
4054 | iommu_detach_dev(iommu, |
4055 | tmp->subordinate->number, 0); | |
4056 | else /* this is a legacy PCI bridge */ | |
276dbf99 DW |
4057 | iommu_detach_dev(iommu, tmp->bus->number, |
4058 | tmp->devfn); | |
3199aa6b HW |
4059 | } |
4060 | } | |
4061 | ||
2c2e2c38 | 4062 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
bf9c9eda | 4063 | struct device *dev) |
c7151a8d | 4064 | { |
bca2b916 | 4065 | struct device_domain_info *info, *tmp; |
c7151a8d WH |
4066 | struct intel_iommu *iommu; |
4067 | unsigned long flags; | |
4068 | int found = 0; | |
156baca8 | 4069 | u8 bus, devfn; |
c7151a8d | 4070 | |
bf9c9eda | 4071 | iommu = device_to_iommu(dev, &bus, &devfn); |
c7151a8d WH |
4072 | if (!iommu) |
4073 | return; | |
4074 | ||
4075 | spin_lock_irqsave(&device_domain_lock, flags); | |
bca2b916 | 4076 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
bf9c9eda DW |
4077 | if (info->iommu == iommu && info->bus == bus && |
4078 | info->devfn == devfn) { | |
109b9b04 | 4079 | unlink_domain_info(info); |
c7151a8d WH |
4080 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4081 | ||
93a23a72 | 4082 | iommu_disable_dev_iotlb(info); |
c7151a8d | 4083 | iommu_detach_dev(iommu, info->bus, info->devfn); |
bf9c9eda | 4084 | iommu_detach_dependent_devices(iommu, dev); |
c7151a8d WH |
4085 | free_devinfo_mem(info); |
4086 | ||
4087 | spin_lock_irqsave(&device_domain_lock, flags); | |
4088 | ||
4089 | if (found) | |
4090 | break; | |
4091 | else | |
4092 | continue; | |
4093 | } | |
4094 | ||
4095 | /* if there is no other devices under the same iommu | |
4096 | * owned by this domain, clear this iommu in iommu_bmp | |
4097 | * update iommu count and coherency | |
4098 | */ | |
8bbc4410 | 4099 | if (info->iommu == iommu) |
c7151a8d WH |
4100 | found = 1; |
4101 | } | |
4102 | ||
3e7abe25 RD |
4103 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4104 | ||
c7151a8d WH |
4105 | if (found == 0) { |
4106 | unsigned long tmp_flags; | |
4107 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); | |
1b198bb0 | 4108 | clear_bit(iommu->seq_id, domain->iommu_bmp); |
c7151a8d | 4109 | domain->iommu_count--; |
58c610bd | 4110 | domain_update_iommu_cap(domain); |
c7151a8d | 4111 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
a97590e5 | 4112 | |
9b4554b2 AW |
4113 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && |
4114 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) { | |
4115 | spin_lock_irqsave(&iommu->lock, tmp_flags); | |
4116 | clear_bit(domain->id, iommu->domain_ids); | |
4117 | iommu->domains[domain->id] = NULL; | |
4118 | spin_unlock_irqrestore(&iommu->lock, tmp_flags); | |
4119 | } | |
c7151a8d | 4120 | } |
c7151a8d WH |
4121 | } |
4122 | ||
2c2e2c38 | 4123 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
4124 | { |
4125 | int adjust_width; | |
4126 | ||
4127 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
5e98c4b1 WH |
4128 | domain_reserve_special_ranges(domain); |
4129 | ||
4130 | /* calculate AGAW */ | |
4131 | domain->gaw = guest_width; | |
4132 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
4133 | domain->agaw = width_to_agaw(adjust_width); | |
4134 | ||
5e98c4b1 | 4135 | domain->iommu_coherency = 0; |
c5b15255 | 4136 | domain->iommu_snooping = 0; |
6dd9a7c7 | 4137 | domain->iommu_superpage = 0; |
fe40f1e0 | 4138 | domain->max_addr = 0; |
4c923d47 | 4139 | domain->nid = -1; |
5e98c4b1 WH |
4140 | |
4141 | /* always allocate the top pgd */ | |
4c923d47 | 4142 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
5e98c4b1 WH |
4143 | if (!domain->pgd) |
4144 | return -ENOMEM; | |
4145 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
4146 | return 0; | |
4147 | } | |
4148 | ||
5d450806 | 4149 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 4150 | { |
5d450806 | 4151 | struct dmar_domain *dmar_domain; |
38717946 | 4152 | |
92d03cc8 | 4153 | dmar_domain = alloc_domain(true); |
5d450806 | 4154 | if (!dmar_domain) { |
38717946 | 4155 | printk(KERN_ERR |
5d450806 JR |
4156 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
4157 | return -ENOMEM; | |
38717946 | 4158 | } |
2c2e2c38 | 4159 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 4160 | printk(KERN_ERR |
5d450806 | 4161 | "intel_iommu_domain_init() failed\n"); |
92d03cc8 | 4162 | domain_exit(dmar_domain); |
5d450806 | 4163 | return -ENOMEM; |
38717946 | 4164 | } |
8140a95d | 4165 | domain_update_iommu_cap(dmar_domain); |
5d450806 | 4166 | domain->priv = dmar_domain; |
faa3d6f5 | 4167 | |
8a0e715b JR |
4168 | domain->geometry.aperture_start = 0; |
4169 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); | |
4170 | domain->geometry.force_aperture = true; | |
4171 | ||
5d450806 | 4172 | return 0; |
38717946 | 4173 | } |
38717946 | 4174 | |
5d450806 | 4175 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 4176 | { |
5d450806 JR |
4177 | struct dmar_domain *dmar_domain = domain->priv; |
4178 | ||
4179 | domain->priv = NULL; | |
92d03cc8 | 4180 | domain_exit(dmar_domain); |
38717946 | 4181 | } |
38717946 | 4182 | |
4c5478c9 JR |
4183 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
4184 | struct device *dev) | |
38717946 | 4185 | { |
4c5478c9 | 4186 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 WH |
4187 | struct intel_iommu *iommu; |
4188 | int addr_width; | |
156baca8 | 4189 | u8 bus, devfn; |
faa3d6f5 | 4190 | |
7207d8f9 DW |
4191 | /* normally dev is not mapped */ |
4192 | if (unlikely(domain_context_mapped(dev))) { | |
faa3d6f5 WH |
4193 | struct dmar_domain *old_domain; |
4194 | ||
1525a29a | 4195 | old_domain = find_domain(dev); |
faa3d6f5 | 4196 | if (old_domain) { |
2c2e2c38 FY |
4197 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
4198 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) | |
bf9c9eda | 4199 | domain_remove_one_dev_info(old_domain, dev); |
faa3d6f5 WH |
4200 | else |
4201 | domain_remove_dev_info(old_domain); | |
4202 | } | |
4203 | } | |
4204 | ||
156baca8 | 4205 | iommu = device_to_iommu(dev, &bus, &devfn); |
fe40f1e0 WH |
4206 | if (!iommu) |
4207 | return -ENODEV; | |
4208 | ||
4209 | /* check if this iommu agaw is sufficient for max mapped address */ | |
4210 | addr_width = agaw_to_width(iommu->agaw); | |
a99c47a2 TL |
4211 | if (addr_width > cap_mgaw(iommu->cap)) |
4212 | addr_width = cap_mgaw(iommu->cap); | |
4213 | ||
4214 | if (dmar_domain->max_addr > (1LL << addr_width)) { | |
4215 | printk(KERN_ERR "%s: iommu width (%d) is not " | |
fe40f1e0 | 4216 | "sufficient for the mapped address (%llx)\n", |
a99c47a2 | 4217 | __func__, addr_width, dmar_domain->max_addr); |
fe40f1e0 WH |
4218 | return -EFAULT; |
4219 | } | |
a99c47a2 TL |
4220 | dmar_domain->gaw = addr_width; |
4221 | ||
4222 | /* | |
4223 | * Knock out extra levels of page tables if necessary | |
4224 | */ | |
4225 | while (iommu->agaw < dmar_domain->agaw) { | |
4226 | struct dma_pte *pte; | |
4227 | ||
4228 | pte = dmar_domain->pgd; | |
4229 | if (dma_pte_present(pte)) { | |
25cbff16 SY |
4230 | dmar_domain->pgd = (struct dma_pte *) |
4231 | phys_to_virt(dma_pte_addr(pte)); | |
7a661013 | 4232 | free_pgtable_page(pte); |
a99c47a2 TL |
4233 | } |
4234 | dmar_domain->agaw--; | |
4235 | } | |
fe40f1e0 | 4236 | |
5913c9bf | 4237 | return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL); |
38717946 | 4238 | } |
38717946 | 4239 | |
4c5478c9 JR |
4240 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
4241 | struct device *dev) | |
38717946 | 4242 | { |
4c5478c9 | 4243 | struct dmar_domain *dmar_domain = domain->priv; |
4c5478c9 | 4244 | |
bf9c9eda | 4245 | domain_remove_one_dev_info(dmar_domain, dev); |
faa3d6f5 | 4246 | } |
c7151a8d | 4247 | |
b146a1c9 JR |
4248 | static int intel_iommu_map(struct iommu_domain *domain, |
4249 | unsigned long iova, phys_addr_t hpa, | |
5009065d | 4250 | size_t size, int iommu_prot) |
faa3d6f5 | 4251 | { |
dde57a21 | 4252 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 | 4253 | u64 max_addr; |
dde57a21 | 4254 | int prot = 0; |
faa3d6f5 | 4255 | int ret; |
fe40f1e0 | 4256 | |
dde57a21 JR |
4257 | if (iommu_prot & IOMMU_READ) |
4258 | prot |= DMA_PTE_READ; | |
4259 | if (iommu_prot & IOMMU_WRITE) | |
4260 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
4261 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
4262 | prot |= DMA_PTE_SNP; | |
dde57a21 | 4263 | |
163cc52c | 4264 | max_addr = iova + size; |
dde57a21 | 4265 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
4266 | u64 end; |
4267 | ||
4268 | /* check if minimum agaw is sufficient for mapped address */ | |
8954da1f | 4269 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
fe40f1e0 | 4270 | if (end < max_addr) { |
8954da1f | 4271 | printk(KERN_ERR "%s: iommu width (%d) is not " |
fe40f1e0 | 4272 | "sufficient for the mapped address (%llx)\n", |
8954da1f | 4273 | __func__, dmar_domain->gaw, max_addr); |
fe40f1e0 WH |
4274 | return -EFAULT; |
4275 | } | |
dde57a21 | 4276 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 4277 | } |
ad051221 DW |
4278 | /* Round up size to next multiple of PAGE_SIZE, if it and |
4279 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 4280 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
4281 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
4282 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 4283 | return ret; |
38717946 | 4284 | } |
38717946 | 4285 | |
5009065d | 4286 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
ea8ea460 | 4287 | unsigned long iova, size_t size) |
38717946 | 4288 | { |
dde57a21 | 4289 | struct dmar_domain *dmar_domain = domain->priv; |
ea8ea460 DW |
4290 | struct page *freelist = NULL; |
4291 | struct intel_iommu *iommu; | |
4292 | unsigned long start_pfn, last_pfn; | |
4293 | unsigned int npages; | |
4294 | int iommu_id, num, ndomains, level = 0; | |
5cf0a76f DW |
4295 | |
4296 | /* Cope with horrid API which requires us to unmap more than the | |
4297 | size argument if it happens to be a large-page mapping. */ | |
4298 | if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)) | |
4299 | BUG(); | |
4300 | ||
4301 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) | |
4302 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); | |
4b99d352 | 4303 | |
ea8ea460 DW |
4304 | start_pfn = iova >> VTD_PAGE_SHIFT; |
4305 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; | |
4306 | ||
4307 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); | |
4308 | ||
4309 | npages = last_pfn - start_pfn + 1; | |
4310 | ||
4311 | for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) { | |
4312 | iommu = g_iommus[iommu_id]; | |
4313 | ||
4314 | /* | |
4315 | * find bit position of dmar_domain | |
4316 | */ | |
4317 | ndomains = cap_ndoms(iommu->cap); | |
4318 | for_each_set_bit(num, iommu->domain_ids, ndomains) { | |
4319 | if (iommu->domains[num] == dmar_domain) | |
4320 | iommu_flush_iotlb_psi(iommu, num, start_pfn, | |
4321 | npages, !freelist, 0); | |
4322 | } | |
4323 | ||
4324 | } | |
4325 | ||
4326 | dma_free_pagelist(freelist); | |
fe40f1e0 | 4327 | |
163cc52c DW |
4328 | if (dmar_domain->max_addr == iova + size) |
4329 | dmar_domain->max_addr = iova; | |
b146a1c9 | 4330 | |
5cf0a76f | 4331 | return size; |
38717946 | 4332 | } |
38717946 | 4333 | |
d14d6577 | 4334 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
bb5547ac | 4335 | dma_addr_t iova) |
38717946 | 4336 | { |
d14d6577 | 4337 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 4338 | struct dma_pte *pte; |
5cf0a76f | 4339 | int level = 0; |
faa3d6f5 | 4340 | u64 phys = 0; |
38717946 | 4341 | |
5cf0a76f | 4342 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
38717946 | 4343 | if (pte) |
faa3d6f5 | 4344 | phys = dma_pte_addr(pte); |
38717946 | 4345 | |
faa3d6f5 | 4346 | return phys; |
38717946 | 4347 | } |
a8bcbb0d | 4348 | |
dbb9fd86 SY |
4349 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
4350 | unsigned long cap) | |
4351 | { | |
4352 | struct dmar_domain *dmar_domain = domain->priv; | |
4353 | ||
4354 | if (cap == IOMMU_CAP_CACHE_COHERENCY) | |
4355 | return dmar_domain->iommu_snooping; | |
323f99cb | 4356 | if (cap == IOMMU_CAP_INTR_REMAP) |
95a02e97 | 4357 | return irq_remapping_enabled; |
dbb9fd86 SY |
4358 | |
4359 | return 0; | |
4360 | } | |
4361 | ||
783f157b | 4362 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
70ae6f0d | 4363 | |
abdfdde2 AW |
4364 | static int intel_iommu_add_device(struct device *dev) |
4365 | { | |
4366 | struct pci_dev *pdev = to_pci_dev(dev); | |
3da4af0a | 4367 | struct pci_dev *bridge, *dma_pdev = NULL; |
abdfdde2 AW |
4368 | struct iommu_group *group; |
4369 | int ret; | |
156baca8 | 4370 | u8 bus, devfn; |
70ae6f0d | 4371 | |
156baca8 | 4372 | if (!device_to_iommu(dev, &bus, &devfn)) |
70ae6f0d AW |
4373 | return -ENODEV; |
4374 | ||
4375 | bridge = pci_find_upstream_pcie_bridge(pdev); | |
4376 | if (bridge) { | |
abdfdde2 AW |
4377 | if (pci_is_pcie(bridge)) |
4378 | dma_pdev = pci_get_domain_bus_and_slot( | |
4379 | pci_domain_nr(pdev->bus), | |
4380 | bridge->subordinate->number, 0); | |
3da4af0a | 4381 | if (!dma_pdev) |
abdfdde2 AW |
4382 | dma_pdev = pci_dev_get(bridge); |
4383 | } else | |
4384 | dma_pdev = pci_dev_get(pdev); | |
4385 | ||
a4ff1fc2 | 4386 | /* Account for quirked devices */ |
783f157b AW |
4387 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
4388 | ||
a4ff1fc2 AW |
4389 | /* |
4390 | * If it's a multifunction device that does not support our | |
c14d2690 AW |
4391 | * required ACS flags, add to the same group as lowest numbered |
4392 | * function that also does not suport the required ACS flags. | |
a4ff1fc2 | 4393 | */ |
783f157b | 4394 | if (dma_pdev->multifunction && |
c14d2690 AW |
4395 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) { |
4396 | u8 i, slot = PCI_SLOT(dma_pdev->devfn); | |
4397 | ||
4398 | for (i = 0; i < 8; i++) { | |
4399 | struct pci_dev *tmp; | |
4400 | ||
4401 | tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i)); | |
4402 | if (!tmp) | |
4403 | continue; | |
4404 | ||
4405 | if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) { | |
4406 | swap_pci_ref(&dma_pdev, tmp); | |
4407 | break; | |
4408 | } | |
4409 | pci_dev_put(tmp); | |
4410 | } | |
4411 | } | |
783f157b | 4412 | |
a4ff1fc2 AW |
4413 | /* |
4414 | * Devices on the root bus go through the iommu. If that's not us, | |
4415 | * find the next upstream device and test ACS up to the root bus. | |
4416 | * Finding the next device may require skipping virtual buses. | |
4417 | */ | |
783f157b | 4418 | while (!pci_is_root_bus(dma_pdev->bus)) { |
a4ff1fc2 AW |
4419 | struct pci_bus *bus = dma_pdev->bus; |
4420 | ||
4421 | while (!bus->self) { | |
4422 | if (!pci_is_root_bus(bus)) | |
4423 | bus = bus->parent; | |
4424 | else | |
4425 | goto root_bus; | |
4426 | } | |
4427 | ||
4428 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
783f157b AW |
4429 | break; |
4430 | ||
a4ff1fc2 | 4431 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
783f157b AW |
4432 | } |
4433 | ||
a4ff1fc2 | 4434 | root_bus: |
abdfdde2 AW |
4435 | group = iommu_group_get(&dma_pdev->dev); |
4436 | pci_dev_put(dma_pdev); | |
4437 | if (!group) { | |
4438 | group = iommu_group_alloc(); | |
4439 | if (IS_ERR(group)) | |
4440 | return PTR_ERR(group); | |
70ae6f0d AW |
4441 | } |
4442 | ||
abdfdde2 | 4443 | ret = iommu_group_add_device(group, dev); |
bcb71abe | 4444 | |
abdfdde2 AW |
4445 | iommu_group_put(group); |
4446 | return ret; | |
4447 | } | |
70ae6f0d | 4448 | |
abdfdde2 AW |
4449 | static void intel_iommu_remove_device(struct device *dev) |
4450 | { | |
4451 | iommu_group_remove_device(dev); | |
70ae6f0d AW |
4452 | } |
4453 | ||
a8bcbb0d JR |
4454 | static struct iommu_ops intel_iommu_ops = { |
4455 | .domain_init = intel_iommu_domain_init, | |
4456 | .domain_destroy = intel_iommu_domain_destroy, | |
4457 | .attach_dev = intel_iommu_attach_device, | |
4458 | .detach_dev = intel_iommu_detach_device, | |
b146a1c9 JR |
4459 | .map = intel_iommu_map, |
4460 | .unmap = intel_iommu_unmap, | |
a8bcbb0d | 4461 | .iova_to_phys = intel_iommu_iova_to_phys, |
dbb9fd86 | 4462 | .domain_has_cap = intel_iommu_domain_has_cap, |
abdfdde2 AW |
4463 | .add_device = intel_iommu_add_device, |
4464 | .remove_device = intel_iommu_remove_device, | |
6d1c56a9 | 4465 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
a8bcbb0d | 4466 | }; |
9af88143 | 4467 | |
9452618e DV |
4468 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
4469 | { | |
4470 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ | |
4471 | printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); | |
4472 | dmar_map_gfx = 0; | |
4473 | } | |
4474 | ||
4475 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); | |
4476 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); | |
4477 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); | |
4478 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); | |
4479 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); | |
4480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); | |
4481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); | |
4482 | ||
d34d6517 | 4483 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
9af88143 DW |
4484 | { |
4485 | /* | |
4486 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
210561ff | 4487 | * but needs it. Same seems to hold for the desktop versions. |
9af88143 DW |
4488 | */ |
4489 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
4490 | rwbf_quirk = 1; | |
4491 | } | |
4492 | ||
4493 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | |
210561ff DV |
4494 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
4495 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | |
4496 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | |
4497 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | |
4498 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | |
4499 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | |
e0fc7e0b | 4500 | |
eecfd57f AJ |
4501 | #define GGC 0x52 |
4502 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | |
4503 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) | |
4504 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) | |
4505 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) | |
4506 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) | |
4507 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) | |
4508 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) | |
4509 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) | |
4510 | ||
d34d6517 | 4511 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
9eecabcb DW |
4512 | { |
4513 | unsigned short ggc; | |
4514 | ||
eecfd57f | 4515 | if (pci_read_config_word(dev, GGC, &ggc)) |
9eecabcb DW |
4516 | return; |
4517 | ||
eecfd57f | 4518 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
9eecabcb DW |
4519 | printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
4520 | dmar_map_gfx = 0; | |
6fbcfb3e DW |
4521 | } else if (dmar_map_gfx) { |
4522 | /* we have to ensure the gfx device is idle before we flush */ | |
4523 | printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); | |
4524 | intel_iommu_strict = 1; | |
4525 | } | |
9eecabcb DW |
4526 | } |
4527 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); | |
4528 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); | |
4529 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); | |
4530 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); | |
4531 | ||
e0fc7e0b DW |
4532 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
4533 | ISOCH DMAR unit for the Azalia sound device, but not give it any | |
4534 | TLB entries, which causes it to deadlock. Check for that. We do | |
4535 | this in a function called from init_dmars(), instead of in a PCI | |
4536 | quirk, because we don't want to print the obnoxious "BIOS broken" | |
4537 | message if VT-d is actually disabled. | |
4538 | */ | |
4539 | static void __init check_tylersburg_isoch(void) | |
4540 | { | |
4541 | struct pci_dev *pdev; | |
4542 | uint32_t vtisochctrl; | |
4543 | ||
4544 | /* If there's no Azalia in the system anyway, forget it. */ | |
4545 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); | |
4546 | if (!pdev) | |
4547 | return; | |
4548 | pci_dev_put(pdev); | |
4549 | ||
4550 | /* System Management Registers. Might be hidden, in which case | |
4551 | we can't do the sanity check. But that's OK, because the | |
4552 | known-broken BIOSes _don't_ actually hide it, so far. */ | |
4553 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); | |
4554 | if (!pdev) | |
4555 | return; | |
4556 | ||
4557 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { | |
4558 | pci_dev_put(pdev); | |
4559 | return; | |
4560 | } | |
4561 | ||
4562 | pci_dev_put(pdev); | |
4563 | ||
4564 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ | |
4565 | if (vtisochctrl & 1) | |
4566 | return; | |
4567 | ||
4568 | /* Drop all bits other than the number of TLB entries */ | |
4569 | vtisochctrl &= 0x1c; | |
4570 | ||
4571 | /* If we have the recommended number of TLB entries (16), fine. */ | |
4572 | if (vtisochctrl == 0x10) | |
4573 | return; | |
4574 | ||
4575 | /* Zero TLB entries? You get to ride the short bus to school. */ | |
4576 | if (!vtisochctrl) { | |
4577 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" | |
4578 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
4579 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
4580 | dmi_get_system_info(DMI_BIOS_VERSION), | |
4581 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
4582 | iommu_identity_mapping |= IDENTMAP_AZALIA; | |
4583 | return; | |
4584 | } | |
4585 | ||
4586 | printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", | |
4587 | vtisochctrl); | |
4588 | } |