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MAINTAINERS: Update VT-d entry for drivers/pci -> drivers/iommu move
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
ba395927
KA		 27#include <linux/slab.h>
28#include <linux/irq.h>
29#include <linux/interrupt.h>
ba395927
KA		 30#include <linux/spinlock.h>
31#include <linux/pci.h>
32#include <linux/dmar.h>
33#include <linux/dma-mapping.h>
34#include <linux/mempool.h>
5e0d2a6f 35#include <linux/timer.h>
38717946 36#include <linux/iova.h>
5d450806 37#include <linux/iommu.h>
38717946 38#include <linux/intel-iommu.h>
134fac3f 39#include <linux/syscore_ops.h>
69575d38 40#include <linux/tboot.h>
adb2fe02 41#include <linux/dmi.h>
5cdede24 42#include <linux/pci-ats.h>
ba395927 43#include <asm/cacheflush.h>
46a7fa27 44#include <asm/iommu.h>
ba395927 45
5b6985ce
FY		 46#define ROOT_SIZE VTD_PAGE_SIZE
47#define CONTEXT_SIZE VTD_PAGE_SIZE
48
825507d6
MT		 49#define IS_BRIDGE_HOST_DEVICE(pdev) \
50 ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
ba395927
KA		 51#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
52#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 53#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 54
55#define IOAPIC_RANGE_START (0xfee00000)
56#define IOAPIC_RANGE_END (0xfeefffff)
57#define IOVA_START_ADDR (0x1000)
58
59#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
60
4ed0d3e6
FY		 61#define MAX_AGAW_WIDTH 64
62
2ebe3151
DW		 63#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
64#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
65
66/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
67 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
68#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
69 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
70#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 71
f27be03b 72#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 73#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 74#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 75
df08cdc7
AM		 76/* page table handling */
77#define LEVEL_STRIDE (9)
78#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
79
80static inline int agaw_to_level(int agaw)
81{
82 return agaw + 2;
83}
84
85static inline int agaw_to_width(int agaw)
86{
87 return 30 + agaw * LEVEL_STRIDE;
88}
89
90static inline int width_to_agaw(int width)
91{
92 return (width - 30) / LEVEL_STRIDE;
93}
94
95static inline unsigned int level_to_offset_bits(int level)
96{
97 return (level - 1) * LEVEL_STRIDE;
98}
99
100static inline int pfn_level_offset(unsigned long pfn, int level)
101{
102 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
103}
104
105static inline unsigned long level_mask(int level)
106{
107 return -1UL << level_to_offset_bits(level);
108}
109
110static inline unsigned long level_size(int level)
111{
112 return 1UL << level_to_offset_bits(level);
113}
114
115static inline unsigned long align_to_level(unsigned long pfn, int level)
116{
117 return (pfn + level_size(level) - 1) & level_mask(level);
118}
fd18de50 119
6dd9a7c7
YS		 120static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
121{
122 return 1 << ((lvl - 1) * LEVEL_STRIDE);
123}
124
dd4e8319
DW		 125/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
126 are never going to work. */
127static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
128{
129 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
130}
131
132static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
133{
134 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
135}
136static inline unsigned long page_to_dma_pfn(struct page *pg)
137{
138 return mm_to_dma_pfn(page_to_pfn(pg));
139}
140static inline unsigned long virt_to_dma_pfn(void *p)
141{
142 return page_to_dma_pfn(virt_to_page(p));
143}
144
d9630fe9
WH		 145/* global iommu list, set NULL for ignored DMAR units */
146static struct intel_iommu **g_iommus;
147
e0fc7e0b 148static void __init check_tylersburg_isoch(void);
9af88143
DW		 149static int rwbf_quirk;
150
b779260b
JC		 151/*
152 * set to 1 to panic kernel if can't successfully enable VT-d
153 * (used when kernel is launched w/ TXT)
154 */
155static int force_on = 0;
156
46b08e1a
MM		 157/*
158 * 0: Present
159 * 1-11: Reserved
160 * 12-63: Context Ptr (12 - (haw-1))
161 * 64-127: Reserved
162 */
163struct root_entry {
164 u64 val;
165 u64 rsvd1;
166};
167#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
168static inline bool root_present(struct root_entry *root)
169{
170 return (root->val & 1);
171}
172static inline void set_root_present(struct root_entry *root)
173{
174 root->val |= 1;
175}
176static inline void set_root_value(struct root_entry *root, unsigned long value)
177{
178 root->val |= value & VTD_PAGE_MASK;
179}
180
181static inline struct context_entry *
182get_context_addr_from_root(struct root_entry *root)
183{
184 return (struct context_entry *)
185 (root_present(root)?phys_to_virt(
186 root->val & VTD_PAGE_MASK) :
187 NULL);
188}
189
7a8fc25e
MM		 190/*
191 * low 64 bits:
192 * 0: present
193 * 1: fault processing disable
194 * 2-3: translation type
195 * 12-63: address space root
196 * high 64 bits:
197 * 0-2: address width
198 * 3-6: aval
199 * 8-23: domain id
200 */
201struct context_entry {
202 u64 lo;
203 u64 hi;
204};
c07e7d21
MM		 205
206static inline bool context_present(struct context_entry *context)
207{
208 return (context->lo & 1);
209}
210static inline void context_set_present(struct context_entry *context)
211{
212 context->lo |= 1;
213}
214
215static inline void context_set_fault_enable(struct context_entry *context)
216{
217 context->lo &= (((u64)-1) << 2) | 1;
218}
219
c07e7d21
MM		 220static inline void context_set_translation_type(struct context_entry *context,
221 unsigned long value)
222{
223 context->lo &= (((u64)-1) << 4) | 3;
224 context->lo |= (value & 3) << 2;
225}
226
227static inline void context_set_address_root(struct context_entry *context,
228 unsigned long value)
229{
230 context->lo |= value & VTD_PAGE_MASK;
231}
232
233static inline void context_set_address_width(struct context_entry *context,
234 unsigned long value)
235{
236 context->hi |= value & 7;
237}
238
239static inline void context_set_domain_id(struct context_entry *context,
240 unsigned long value)
241{
242 context->hi |= (value & ((1 << 16) - 1)) << 8;
243}
244
245static inline void context_clear_entry(struct context_entry *context)
246{
247 context->lo = 0;
248 context->hi = 0;
249}
7a8fc25e 250
622ba12a
MM		 251/*
252 * 0: readable
253 * 1: writable
254 * 2-6: reserved
255 * 7: super page
9cf06697
SY		 256 * 8-10: available
257 * 11: snoop behavior
622ba12a
MM		 258 * 12-63: Host physcial address
259 */
260struct dma_pte {
261 u64 val;
262};
622ba12a 263
19c239ce
MM		 264static inline void dma_clear_pte(struct dma_pte *pte)
265{
266 pte->val = 0;
267}
268
269static inline void dma_set_pte_readable(struct dma_pte *pte)
270{
271 pte->val |= DMA_PTE_READ;
272}
273
274static inline void dma_set_pte_writable(struct dma_pte *pte)
275{
276 pte->val |= DMA_PTE_WRITE;
277}
278
9cf06697
SY		 279static inline void dma_set_pte_snp(struct dma_pte *pte)
280{
281 pte->val |= DMA_PTE_SNP;
282}
283
19c239ce
MM		 284static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
285{
286 pte->val = (pte->val & ~3) | (prot & 3);
287}
288
289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
dd4e8319 299static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
19c239ce 300{
dd4e8319 301 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
19c239ce
MM		 302}
303
304static inline bool dma_pte_present(struct dma_pte *pte)
305{
306 return (pte->val & 3) != 0;
307}
622ba12a 308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
3b5410e7 323/* devices under the same p2p bridge are owned in one domain */
cdc7b837 324#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 325
1ce28feb
WH		 326/* domain represents a virtual machine, more than one devices
327 * across iommus may be owned in one domain, e.g. kvm guest.
328 */
329#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
330
2c2e2c38
FY		 331/* si_domain contains mulitple devices */
332#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
333
99126f7c
MM		 334struct dmar_domain {
335 int id; /* domain id */
4c923d47 336 int nid; /* node id */
8c11e798 337 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
99126f7c
MM		 338
339 struct list_head devices; /* all devices' list */
340 struct iova_domain iovad; /* iova's that belong to this domain */
341
342 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 343 int gaw; /* max guest address width */
344
345 /* adjusted guest address width, 0 is level 2 30-bit */
346 int agaw;
347
3b5410e7 348 int flags; /* flags to find out type of domain */
8e604097
WH		 349
350 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 351 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 352 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 353 int iommu_superpage;/* Level of superpages supported:
354 0 == 4KiB (no superpages), 1 == 2MiB,
355 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 356 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 357 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 358};
359
a647dacb
MM		 360/* PCI domain-device relationship */
361struct device_domain_info {
362 struct list_head link; /* link to domain siblings */
363 struct list_head global; /* link to global list */
276dbf99
DW		 364 int segment; /* PCI domain */
365 u8 bus; /* PCI bus number */
a647dacb 366 u8 devfn; /* PCI devfn number */
45e829ea 367 struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 368 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 369 struct dmar_domain *domain; /* pointer to domain */
370};
371
5e0d2a6f 372static void flush_unmaps_timeout(unsigned long data);
373
374DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
375
80b20dd8 376#define HIGH_WATER_MARK 250
377struct deferred_flush_tables {
378 int next;
379 struct iova *iova[HIGH_WATER_MARK];
380 struct dmar_domain *domain[HIGH_WATER_MARK];
381};
382
383static struct deferred_flush_tables *deferred_flush;
384
5e0d2a6f 385/* bitmap for indexing intel_iommus */
5e0d2a6f 386static int g_num_of_iommus;
387
388static DEFINE_SPINLOCK(async_umap_flush_lock);
389static LIST_HEAD(unmaps_to_do);
390
391static int timer_on;
392static long list_size;
5e0d2a6f 393
ba395927
KA		 394static void domain_remove_dev_info(struct dmar_domain *domain);
395
0cd5c3c8
KM		 396#ifdef CONFIG_DMAR_DEFAULT_ON
397int dmar_disabled = 0;
398#else
399int dmar_disabled = 1;
400#endif /*CONFIG_DMAR_DEFAULT_ON*/
401
2d9e667e 402static int dmar_map_gfx = 1;
7d3b03ce 403static int dmar_forcedac;
5e0d2a6f 404static int intel_iommu_strict;
6dd9a7c7 405static int intel_iommu_superpage = 1;
ba395927 406
c0771df8
DW		 407int intel_iommu_gfx_mapped;
408EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
409
ba395927
KA		 410#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
411static DEFINE_SPINLOCK(device_domain_lock);
412static LIST_HEAD(device_domain_list);
413
a8bcbb0d
JR		 414static struct iommu_ops intel_iommu_ops;
415
ba395927
KA		 416static int __init intel_iommu_setup(char *str)
417{
418 if (!str)
419 return -EINVAL;
420 while (*str) {
0cd5c3c8
KM		 421 if (!strncmp(str, "on", 2)) {
422 dmar_disabled = 0;
423 printk(KERN_INFO "Intel-IOMMU: enabled\n");
424 } else if (!strncmp(str, "off", 3)) {
ba395927 425 dmar_disabled = 1;
0cd5c3c8 426 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 427 } else if (!strncmp(str, "igfx_off", 8)) {
428 dmar_map_gfx = 0;
429 printk(KERN_INFO
430 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 431 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 432 printk(KERN_INFO
7d3b03ce
KA		 433 "Intel-IOMMU: Forcing DAC for PCI devices\n");
434 dmar_forcedac = 1;
5e0d2a6f 435 } else if (!strncmp(str, "strict", 6)) {
436 printk(KERN_INFO
437 "Intel-IOMMU: disable batched IOTLB flush\n");
438 intel_iommu_strict = 1;
6dd9a7c7
YS		 439 } else if (!strncmp(str, "sp_off", 6)) {
440 printk(KERN_INFO
441 "Intel-IOMMU: disable supported super page\n");
442 intel_iommu_superpage = 0;
ba395927
KA		 443 }
444
445 str += strcspn(str, ",");
446 while (*str == ',')
447 str++;
448 }
449 return 0;
450}
451__setup("intel_iommu=", intel_iommu_setup);
452
453static struct kmem_cache *iommu_domain_cache;
454static struct kmem_cache *iommu_devinfo_cache;
455static struct kmem_cache *iommu_iova_cache;
456
4c923d47 457static inline void *alloc_pgtable_page(int node)
eb3fa7cb 458{
4c923d47
SS		 459 struct page *page;
460 void *vaddr = NULL;
eb3fa7cb 461
4c923d47
SS		 462 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
463 if (page)
464 vaddr = page_address(page);
eb3fa7cb 465 return vaddr;
ba395927
KA		 466}
467
468static inline void free_pgtable_page(void *vaddr)
469{
470 free_page((unsigned long)vaddr);
471}
472
473static inline void *alloc_domain_mem(void)
474{
354bb65e 475 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 476}
477
38717946 478static void free_domain_mem(void *vaddr)
ba395927
KA		 479{
480 kmem_cache_free(iommu_domain_cache, vaddr);
481}
482
483static inline void * alloc_devinfo_mem(void)
484{
354bb65e 485 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 486}
487
488static inline void free_devinfo_mem(void *vaddr)
489{
490 kmem_cache_free(iommu_devinfo_cache, vaddr);
491}
492
493struct iova *alloc_iova_mem(void)
494{
354bb65e 495 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 496}
497
498void free_iova_mem(struct iova *iova)
499{
500 kmem_cache_free(iommu_iova_cache, iova);
501}
502
1b573683 503
4ed0d3e6 504static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 505{
506 unsigned long sagaw;
507 int agaw = -1;
508
509 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 510 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 511 agaw >= 0; agaw--) {
512 if (test_bit(agaw, &sagaw))
513 break;
514 }
515
516 return agaw;
517}
518
4ed0d3e6
FY		 519/*
520 * Calculate max SAGAW for each iommu.
521 */
522int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
523{
524 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
525}
526
527/*
528 * calculate agaw for each iommu.
529 * "SAGAW" may be different across iommus, use a default agaw, and
530 * get a supported less agaw for iommus that don't support the default agaw.
531 */
532int iommu_calculate_agaw(struct intel_iommu *iommu)
533{
534 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
535}
536
2c2e2c38 537/* This functionin only returns single iommu in a domain */
8c11e798
WH		 538static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
539{
540 int iommu_id;
541
2c2e2c38 542 /* si_domain and vm domain should not get here. */
1ce28feb 543 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 544 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 545
8c11e798
WH		 546 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
547 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
548 return NULL;
549
550 return g_iommus[iommu_id];
551}
552
8e604097
WH		 553static void domain_update_iommu_coherency(struct dmar_domain *domain)
554{
555 int i;
556
557 domain->iommu_coherency = 1;
558
a45946ab 559 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
8e604097
WH		 560 if (!ecap_coherent(g_iommus[i]->ecap)) {
561 domain->iommu_coherency = 0;
562 break;
563 }
8e604097
WH		 564 }
565}
566
58c610bd
SY		 567static void domain_update_iommu_snooping(struct dmar_domain *domain)
568{
569 int i;
570
571 domain->iommu_snooping = 1;
572
a45946ab 573 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 574 if (!ecap_sc_support(g_iommus[i]->ecap)) {
575 domain->iommu_snooping = 0;
576 break;
577 }
58c610bd
SY		 578 }
579}
580
6dd9a7c7
YS		 581static void domain_update_iommu_superpage(struct dmar_domain *domain)
582{
583 int i, mask = 0xf;
584
585 if (!intel_iommu_superpage) {
586 domain->iommu_superpage = 0;
587 return;
588 }
589
590 domain->iommu_superpage = 4; /* 1TiB */
591
592 for_each_set_bit(i, &domain->iommu_bmp, g_num_of_iommus) {
593 mask |= cap_super_page_val(g_iommus[i]->cap);
594 if (!mask) {
595 break;
596 }
597 }
598 domain->iommu_superpage = fls(mask);
599}
600
58c610bd
SY		 601/* Some capabilities may be different across iommus */
602static void domain_update_iommu_cap(struct dmar_domain *domain)
603{
604 domain_update_iommu_coherency(domain);
605 domain_update_iommu_snooping(domain);
6dd9a7c7 606 domain_update_iommu_superpage(domain);
58c610bd
SY		 607}
608
276dbf99 609static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 610{
611 struct dmar_drhd_unit *drhd = NULL;
612 int i;
613
614 for_each_drhd_unit(drhd) {
615 if (drhd->ignored)
616 continue;
276dbf99
DW		 617 if (segment != drhd->segment)
618 continue;
c7151a8d 619
924b6231 620 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 621 if (drhd->devices[i] &&
622 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 623 drhd->devices[i]->devfn == devfn)
624 return drhd->iommu;
4958c5dc
DW		 625 if (drhd->devices[i] &&
626 drhd->devices[i]->subordinate &&
924b6231
DW		 627 drhd->devices[i]->subordinate->number <= bus &&
628 drhd->devices[i]->subordinate->subordinate >= bus)
629 return drhd->iommu;
630 }
c7151a8d
WH		 631
632 if (drhd->include_all)
633 return drhd->iommu;
634 }
635
636 return NULL;
637}
638
5331fe6f
WH		 639static void domain_flush_cache(struct dmar_domain *domain,
640 void *addr, int size)
641{
642 if (!domain->iommu_coherency)
643 clflush_cache_range(addr, size);
644}
645
ba395927
KA		 646/* Gets context entry for a given bus and devfn */
647static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
648 u8 bus, u8 devfn)
649{
650 struct root_entry *root;
651 struct context_entry *context;
652 unsigned long phy_addr;
653 unsigned long flags;
654
655 spin_lock_irqsave(&iommu->lock, flags);
656 root = &iommu->root_entry[bus];
657 context = get_context_addr_from_root(root);
658 if (!context) {
4c923d47
SS		 659 context = (struct context_entry *)
660 alloc_pgtable_page(iommu->node);
ba395927
KA		 661 if (!context) {
662 spin_unlock_irqrestore(&iommu->lock, flags);
663 return NULL;
664 }
5b6985ce 665 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 666 phy_addr = virt_to_phys((void *)context);
667 set_root_value(root, phy_addr);
668 set_root_present(root);
669 __iommu_flush_cache(iommu, root, sizeof(*root));
670 }
671 spin_unlock_irqrestore(&iommu->lock, flags);
672 return &context[devfn];
673}
674
675static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
676{
677 struct root_entry *root;
678 struct context_entry *context;
679 int ret;
680 unsigned long flags;
681
682 spin_lock_irqsave(&iommu->lock, flags);
683 root = &iommu->root_entry[bus];
684 context = get_context_addr_from_root(root);
685 if (!context) {
686 ret = 0;
687 goto out;
688 }
c07e7d21 689 ret = context_present(&context[devfn]);
ba395927
KA		 690out:
691 spin_unlock_irqrestore(&iommu->lock, flags);
692 return ret;
693}
694
695static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
696{
697 struct root_entry *root;
698 struct context_entry *context;
699 unsigned long flags;
700
701 spin_lock_irqsave(&iommu->lock, flags);
702 root = &iommu->root_entry[bus];
703 context = get_context_addr_from_root(root);
704 if (context) {
c07e7d21 705 context_clear_entry(&context[devfn]);
ba395927
KA		 706 __iommu_flush_cache(iommu, &context[devfn], \
707 sizeof(*context));
708 }
709 spin_unlock_irqrestore(&iommu->lock, flags);
710}
711
712static void free_context_table(struct intel_iommu *iommu)
713{
714 struct root_entry *root;
715 int i;
716 unsigned long flags;
717 struct context_entry *context;
718
719 spin_lock_irqsave(&iommu->lock, flags);
720 if (!iommu->root_entry) {
721 goto out;
722 }
723 for (i = 0; i < ROOT_ENTRY_NR; i++) {
724 root = &iommu->root_entry[i];
725 context = get_context_addr_from_root(root);
726 if (context)
727 free_pgtable_page(context);
728 }
729 free_pgtable_page(iommu->root_entry);
730 iommu->root_entry = NULL;
731out:
732 spin_unlock_irqrestore(&iommu->lock, flags);
733}
734
b026fd28 735static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
6dd9a7c7 736 unsigned long pfn, int large_level)
ba395927 737{
b026fd28 738 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 739 struct dma_pte *parent, *pte = NULL;
740 int level = agaw_to_level(domain->agaw);
6dd9a7c7 741 int offset, target_level;
ba395927
KA		 742
743 BUG_ON(!domain->pgd);
b026fd28 744 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
ba395927
KA		 745 parent = domain->pgd;
746
6dd9a7c7
YS		 747 /* Search pte */
748 if (!large_level)
749 target_level = 1;
750 else
751 target_level = large_level;
752
ba395927
KA		 753 while (level > 0) {
754 void *tmp_page;
755
b026fd28 756 offset = pfn_level_offset(pfn, level);
ba395927 757 pte = &parent[offset];
6dd9a7c7
YS		 758 if (!large_level && (pte->val & DMA_PTE_LARGE_PAGE))
759 break;
760 if (level == target_level)
ba395927
KA		 761 break;
762
19c239ce 763 if (!dma_pte_present(pte)) {
c85994e4
DW		 764 uint64_t pteval;
765
4c923d47 766 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 767
206a73c1 768 if (!tmp_page)
ba395927 769 return NULL;
206a73c1 770
c85994e4 771 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 772 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 773 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
774 /* Someone else set it while we were thinking; use theirs. */
775 free_pgtable_page(tmp_page);
776 } else {
777 dma_pte_addr(pte);
778 domain_flush_cache(domain, pte, sizeof(*pte));
779 }
ba395927 780 }
19c239ce 781 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 782 level--;
783 }
784
ba395927
KA		 785 return pte;
786}
787
6dd9a7c7 788
ba395927 789/* return address's pte at specific level */
90dcfb5e
DW		 790static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
791 unsigned long pfn,
6dd9a7c7 792 int level, int *large_page)
ba395927
KA		 793{
794 struct dma_pte *parent, *pte = NULL;
795 int total = agaw_to_level(domain->agaw);
796 int offset;
797
798 parent = domain->pgd;
799 while (level <= total) {
90dcfb5e 800 offset = pfn_level_offset(pfn, total);
ba395927
KA		 801 pte = &parent[offset];
802 if (level == total)
803 return pte;
804
6dd9a7c7
YS		 805 if (!dma_pte_present(pte)) {
806 *large_page = total;
ba395927 807 break;
6dd9a7c7
YS		 808 }
809
810 if (pte->val & DMA_PTE_LARGE_PAGE) {
811 *large_page = total;
812 return pte;
813 }
814
19c239ce 815 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 816 total--;
817 }
818 return NULL;
819}
820
ba395927 821/* clear last level pte, a tlb flush should be followed */
595badf5
DW		 822static void dma_pte_clear_range(struct dmar_domain *domain,
823 unsigned long start_pfn,
824 unsigned long last_pfn)
ba395927 825{
04b18e65 826 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 827 unsigned int large_page = 1;
310a5ab9 828 struct dma_pte *first_pte, *pte;
66eae846 829
04b18e65 830 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 831 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 832 BUG_ON(start_pfn > last_pfn);
ba395927 833
04b18e65 834 /* we don't need lock here; nobody else touches the iova range */
59c36286 835 do {
6dd9a7c7
YS		 836 large_page = 1;
837 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 838 if (!pte) {
6dd9a7c7 839 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 840 continue;
841 }
6dd9a7c7 842 do {
310a5ab9 843 dma_clear_pte(pte);
6dd9a7c7 844 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 845 pte++;
75e6bf96
DW		 846 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
847
310a5ab9
DW		 848 domain_flush_cache(domain, first_pte,
849 (void *)pte - (void *)first_pte);
59c36286
DW		 850
851 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 852}
853
854/* free page table pages. last level pte should already be cleared */
855static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 856 unsigned long start_pfn,
857 unsigned long last_pfn)
ba395927 858{
6660c63a 859 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
f3a0a52f 860 struct dma_pte *first_pte, *pte;
ba395927
KA		 861 int total = agaw_to_level(domain->agaw);
862 int level;
6660c63a 863 unsigned long tmp;
6dd9a7c7 864 int large_page = 2;
ba395927 865
6660c63a
DW		 866 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
867 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 868 BUG_ON(start_pfn > last_pfn);
ba395927 869
f3a0a52f 870 /* We don't need lock here; nobody else touches the iova range */
ba395927
KA		 871 level = 2;
872 while (level <= total) {
6660c63a
DW		 873 tmp = align_to_level(start_pfn, level);
874
f3a0a52f 875 /* If we can't even clear one PTE at this level, we're done */
6660c63a 876 if (tmp + level_size(level) - 1 > last_pfn)
ba395927
KA		 877 return;
878
59c36286 879 do {
6dd9a7c7
YS		 880 large_page = level;
881 first_pte = pte = dma_pfn_level_pte(domain, tmp, level, &large_page);
882 if (large_page > level)
883 level = large_page + 1;
f3a0a52f
DW		 884 if (!pte) {
885 tmp = align_to_level(tmp + 1, level + 1);
886 continue;
887 }
75e6bf96 888 do {
6a43e574
DW		 889 if (dma_pte_present(pte)) {
890 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
891 dma_clear_pte(pte);
892 }
f3a0a52f
DW		 893 pte++;
894 tmp += level_size(level);
75e6bf96
DW		 895 } while (!first_pte_in_page(pte) &&
896 tmp + level_size(level) - 1 <= last_pfn);
897
f3a0a52f
DW		 898 domain_flush_cache(domain, first_pte,
899 (void *)pte - (void *)first_pte);
900
59c36286 901 } while (tmp && tmp + level_size(level) - 1 <= last_pfn);
ba395927
KA		 902 level++;
903 }
904 /* free pgd */
d794dc9b 905 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 906 free_pgtable_page(domain->pgd);
907 domain->pgd = NULL;
908 }
909}
910
911/* iommu handling */
912static int iommu_alloc_root_entry(struct intel_iommu *iommu)
913{
914 struct root_entry *root;
915 unsigned long flags;
916
4c923d47 917 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 918 if (!root)
919 return -ENOMEM;
920
5b6985ce 921 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 922
923 spin_lock_irqsave(&iommu->lock, flags);
924 iommu->root_entry = root;
925 spin_unlock_irqrestore(&iommu->lock, flags);
926
927 return 0;
928}
929
ba395927
KA		 930static void iommu_set_root_entry(struct intel_iommu *iommu)
931{
932 void *addr;
c416daa9 933 u32 sts;
ba395927
KA		 934 unsigned long flag;
935
936 addr = iommu->root_entry;
937
938 spin_lock_irqsave(&iommu->register_lock, flag);
939 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
940
c416daa9 941 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 942
943 /* Make sure hardware complete it */
944 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 945 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927
KA		 946
947 spin_unlock_irqrestore(&iommu->register_lock, flag);
948}
949
950static void iommu_flush_write_buffer(struct intel_iommu *iommu)
951{
952 u32 val;
953 unsigned long flag;
954
9af88143 955 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 956 return;
ba395927
KA		 957
958 spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 959 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 960
961 /* Make sure hardware complete it */
962 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 963 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927
KA		 964
965 spin_unlock_irqrestore(&iommu->register_lock, flag);
966}
967
968/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 969static void __iommu_flush_context(struct intel_iommu *iommu,
970 u16 did, u16 source_id, u8 function_mask,
971 u64 type)
ba395927
KA		 972{
973 u64 val = 0;
974 unsigned long flag;
975
ba395927
KA		 976 switch (type) {
977 case DMA_CCMD_GLOBAL_INVL:
978 val = DMA_CCMD_GLOBAL_INVL;
979 break;
980 case DMA_CCMD_DOMAIN_INVL:
981 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
982 break;
983 case DMA_CCMD_DEVICE_INVL:
984 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
985 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
986 break;
987 default:
988 BUG();
989 }
990 val |= DMA_CCMD_ICC;
991
992 spin_lock_irqsave(&iommu->register_lock, flag);
993 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
994
995 /* Make sure hardware complete it */
996 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
997 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
998
999 spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1000}
1001
ba395927 1002/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1003static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1004 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1005{
1006 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1007 u64 val = 0, val_iva = 0;
1008 unsigned long flag;
1009
ba395927
KA		 1010 switch (type) {
1011 case DMA_TLB_GLOBAL_FLUSH:
1012 /* global flush doesn't need set IVA_REG */
1013 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1014 break;
1015 case DMA_TLB_DSI_FLUSH:
1016 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1017 break;
1018 case DMA_TLB_PSI_FLUSH:
1019 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1020 /* Note: always flush non-leaf currently */
1021 val_iva = size_order | addr;
1022 break;
1023 default:
1024 BUG();
1025 }
1026 /* Note: set drain read/write */
1027#if 0
1028 /*
1029 * This is probably to be super secure.. Looks like we can
1030 * ignore it without any impact.
1031 */
1032 if (cap_read_drain(iommu->cap))
1033 val |= DMA_TLB_READ_DRAIN;
1034#endif
1035 if (cap_write_drain(iommu->cap))
1036 val |= DMA_TLB_WRITE_DRAIN;
1037
1038 spin_lock_irqsave(&iommu->register_lock, flag);
1039 /* Note: Only uses first TLB reg currently */
1040 if (val_iva)
1041 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1042 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1043
1044 /* Make sure hardware complete it */
1045 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1046 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1047
1048 spin_unlock_irqrestore(&iommu->register_lock, flag);
1049
1050 /* check IOTLB invalidation granularity */
1051 if (DMA_TLB_IAIG(val) == 0)
1052 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1053 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1054 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1055 (unsigned long long)DMA_TLB_IIRG(type),
1056 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1057}
1058
93a23a72
YZ		 1059static struct device_domain_info *iommu_support_dev_iotlb(
1060 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1061{
1062 int found = 0;
1063 unsigned long flags;
1064 struct device_domain_info *info;
1065 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1066
1067 if (!ecap_dev_iotlb_support(iommu->ecap))
1068 return NULL;
1069
1070 if (!iommu->qi)
1071 return NULL;
1072
1073 spin_lock_irqsave(&device_domain_lock, flags);
1074 list_for_each_entry(info, &domain->devices, link)
1075 if (info->bus == bus && info->devfn == devfn) {
1076 found = 1;
1077 break;
1078 }
1079 spin_unlock_irqrestore(&device_domain_lock, flags);
1080
1081 if (!found || !info->dev)
1082 return NULL;
1083
1084 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1085 return NULL;
1086
1087 if (!dmar_find_matched_atsr_unit(info->dev))
1088 return NULL;
1089
1090 info->iommu = iommu;
1091
1092 return info;
1093}
1094
1095static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1096{
93a23a72
YZ		 1097 if (!info)
1098 return;
1099
1100 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1101}
1102
1103static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1104{
1105 if (!info->dev || !pci_ats_enabled(info->dev))
1106 return;
1107
1108 pci_disable_ats(info->dev);
1109}
1110
1111static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1112 u64 addr, unsigned mask)
1113{
1114 u16 sid, qdep;
1115 unsigned long flags;
1116 struct device_domain_info *info;
1117
1118 spin_lock_irqsave(&device_domain_lock, flags);
1119 list_for_each_entry(info, &domain->devices, link) {
1120 if (!info->dev || !pci_ats_enabled(info->dev))
1121 continue;
1122
1123 sid = info->bus << 8 | info->devfn;
1124 qdep = pci_ats_queue_depth(info->dev);
1125 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1126 }
1127 spin_unlock_irqrestore(&device_domain_lock, flags);
1128}
1129
1f0ef2aa 1130static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
82653633 1131 unsigned long pfn, unsigned int pages, int map)
ba395927 1132{
9dd2fe89 1133 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1134 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1135
ba395927
KA		 1136 BUG_ON(pages == 0);
1137
ba395927 1138 /*
9dd2fe89
YZ		 1139 * Fallback to domain selective flush if no PSI support or the size is
1140 * too big.
ba395927
KA		 1141 * PSI requires page size to be 2 ^ x, and the base address is naturally
1142 * aligned to the size
1143 */
9dd2fe89
YZ		 1144 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1145 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1146 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1147 else
1148 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1149 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1150
1151 /*
82653633
NA		 1152 * In caching mode, changes of pages from non-present to present require
1153 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1154 */
82653633 1155 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1156 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1157}
1158
f8bab735 1159static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1160{
1161 u32 pmen;
1162 unsigned long flags;
1163
1164 spin_lock_irqsave(&iommu->register_lock, flags);
1165 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1166 pmen &= ~DMA_PMEN_EPM;
1167 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1168
1169 /* wait for the protected region status bit to clear */
1170 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1171 readl, !(pmen & DMA_PMEN_PRS), pmen);
1172
1173 spin_unlock_irqrestore(&iommu->register_lock, flags);
1174}
1175
ba395927
KA		 1176static int iommu_enable_translation(struct intel_iommu *iommu)
1177{
1178 u32 sts;
1179 unsigned long flags;
1180
1181 spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1182 iommu->gcmd |= DMA_GCMD_TE;
1183 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1184
1185 /* Make sure hardware complete it */
1186 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1187 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1188
ba395927
KA		 1189 spin_unlock_irqrestore(&iommu->register_lock, flags);
1190 return 0;
1191}
1192
1193static int iommu_disable_translation(struct intel_iommu *iommu)
1194{
1195 u32 sts;
1196 unsigned long flag;
1197
1198 spin_lock_irqsave(&iommu->register_lock, flag);
1199 iommu->gcmd &= ~DMA_GCMD_TE;
1200 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1201
1202 /* Make sure hardware complete it */
1203 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1204 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927
KA		 1205
1206 spin_unlock_irqrestore(&iommu->register_lock, flag);
1207 return 0;
1208}
1209
3460a6d9 1210
ba395927
KA		 1211static int iommu_init_domains(struct intel_iommu *iommu)
1212{
1213 unsigned long ndomains;
1214 unsigned long nlongs;
1215
1216 ndomains = cap_ndoms(iommu->cap);
680a7524
YL		 1217 pr_debug("IOMMU %d: Number of Domains supportd <%ld>\n", iommu->seq_id,
1218 ndomains);
ba395927
KA		 1219 nlongs = BITS_TO_LONGS(ndomains);
1220
94a91b50
DD		 1221 spin_lock_init(&iommu->lock);
1222
ba395927
KA		 1223 /* TBD: there might be 64K domains,
1224 * consider other allocation for future chip
1225 */
1226 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1227 if (!iommu->domain_ids) {
1228 printk(KERN_ERR "Allocating domain id array failed\n");
1229 return -ENOMEM;
1230 }
1231 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1232 GFP_KERNEL);
1233 if (!iommu->domains) {
1234 printk(KERN_ERR "Allocating domain array failed\n");
ba395927
KA		 1235 return -ENOMEM;
1236 }
1237
1238 /*
1239 * if Caching mode is set, then invalid translations are tagged
1240 * with domainid 0. Hence we need to pre-allocate it.
1241 */
1242 if (cap_caching_mode(iommu->cap))
1243 set_bit(0, iommu->domain_ids);
1244 return 0;
1245}
ba395927 1246
ba395927
KA		 1247
1248static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1249static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8
SS		 1250
1251void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1252{
1253 struct dmar_domain *domain;
1254 int i;
c7151a8d 1255 unsigned long flags;
ba395927 1256
94a91b50 1257 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1258 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
94a91b50
DD		 1259 domain = iommu->domains[i];
1260 clear_bit(i, iommu->domain_ids);
1261
1262 spin_lock_irqsave(&domain->iommu_lock, flags);
1263 if (--domain->iommu_count == 0) {
1264 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1265 vm_domain_exit(domain);
1266 else
1267 domain_exit(domain);
1268 }
1269 spin_unlock_irqrestore(&domain->iommu_lock, flags);
5e98c4b1 1270 }
ba395927
KA		 1271 }
1272
1273 if (iommu->gcmd & DMA_GCMD_TE)
1274 iommu_disable_translation(iommu);
1275
1276 if (iommu->irq) {
dced35ae 1277 irq_set_handler_data(iommu->irq, NULL);
ba395927
KA		 1278 /* This will mask the irq */
1279 free_irq(iommu->irq, iommu);
1280 destroy_irq(iommu->irq);
1281 }
1282
1283 kfree(iommu->domains);
1284 kfree(iommu->domain_ids);
1285
d9630fe9
WH		 1286 g_iommus[iommu->seq_id] = NULL;
1287
1288 /* if all iommus are freed, free g_iommus */
1289 for (i = 0; i < g_num_of_iommus; i++) {
1290 if (g_iommus[i])
1291 break;
1292 }
1293
1294 if (i == g_num_of_iommus)
1295 kfree(g_iommus);
1296
ba395927
KA		 1297 /* free context mapping */
1298 free_context_table(iommu);
ba395927
KA		 1299}
1300
2c2e2c38 1301static struct dmar_domain *alloc_domain(void)
ba395927 1302{
ba395927 1303 struct dmar_domain *domain;
ba395927
KA		 1304
1305 domain = alloc_domain_mem();
1306 if (!domain)
1307 return NULL;
1308
4c923d47 1309 domain->nid = -1;
2c2e2c38
FY		 1310 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1311 domain->flags = 0;
1312
1313 return domain;
1314}
1315
1316static int iommu_attach_domain(struct dmar_domain *domain,
1317 struct intel_iommu *iommu)
1318{
1319 int num;
1320 unsigned long ndomains;
1321 unsigned long flags;
1322
ba395927
KA		 1323 ndomains = cap_ndoms(iommu->cap);
1324
1325 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1326
ba395927
KA		 1327 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1328 if (num >= ndomains) {
1329 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1330 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1331 return -ENOMEM;
ba395927
KA		 1332 }
1333
ba395927 1334 domain->id = num;
2c2e2c38 1335 set_bit(num, iommu->domain_ids);
8c11e798 1336 set_bit(iommu->seq_id, &domain->iommu_bmp);
ba395927
KA		 1337 iommu->domains[num] = domain;
1338 spin_unlock_irqrestore(&iommu->lock, flags);
1339
2c2e2c38 1340 return 0;
ba395927
KA		 1341}
1342
2c2e2c38
FY		 1343static void iommu_detach_domain(struct dmar_domain *domain,
1344 struct intel_iommu *iommu)
ba395927
KA		 1345{
1346 unsigned long flags;
2c2e2c38
FY		 1347 int num, ndomains;
1348 int found = 0;
ba395927 1349
8c11e798 1350 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1351 ndomains = cap_ndoms(iommu->cap);
a45946ab 1352 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38
FY		 1353 if (iommu->domains[num] == domain) {
1354 found = 1;
1355 break;
1356 }
2c2e2c38
FY		 1357 }
1358
1359 if (found) {
1360 clear_bit(num, iommu->domain_ids);
1361 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1362 iommu->domains[num] = NULL;
1363 }
8c11e798 1364 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1365}
1366
1367static struct iova_domain reserved_iova_list;
8a443df4 1368static struct lock_class_key reserved_rbtree_key;
ba395927 1369
51a63e67 1370static int dmar_init_reserved_ranges(void)
ba395927
KA		 1371{
1372 struct pci_dev *pdev = NULL;
1373 struct iova *iova;
1374 int i;
ba395927 1375
f661197e 1376 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1377
8a443df4
MG		 1378 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1379 &reserved_rbtree_key);
1380
ba395927
KA		 1381 /* IOAPIC ranges shouldn't be accessed by DMA */
1382 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1383 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1384 if (!iova) {
ba395927 1385 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1386 return -ENODEV;
1387 }
ba395927
KA		 1388
1389 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1390 for_each_pci_dev(pdev) {
1391 struct resource *r;
1392
1393 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1394 r = &pdev->resource[i];
1395 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1396 continue;
1a4a4551
DW		 1397 iova = reserve_iova(&reserved_iova_list,
1398 IOVA_PFN(r->start),
1399 IOVA_PFN(r->end));
51a63e67 1400 if (!iova) {
ba395927 1401 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1402 return -ENODEV;
1403 }
ba395927
KA		 1404 }
1405 }
51a63e67 1406 return 0;
ba395927
KA		 1407}
1408
1409static void domain_reserve_special_ranges(struct dmar_domain *domain)
1410{
1411 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1412}
1413
1414static inline int guestwidth_to_adjustwidth(int gaw)
1415{
1416 int agaw;
1417 int r = (gaw - 12) % 9;
1418
1419 if (r == 0)
1420 agaw = gaw;
1421 else
1422 agaw = gaw + 9 - r;
1423 if (agaw > 64)
1424 agaw = 64;
1425 return agaw;
1426}
1427
1428static int domain_init(struct dmar_domain *domain, int guest_width)
1429{
1430 struct intel_iommu *iommu;
1431 int adjust_width, agaw;
1432 unsigned long sagaw;
1433
f661197e 1434 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1435 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1436
1437 domain_reserve_special_ranges(domain);
1438
1439 /* calculate AGAW */
8c11e798 1440 iommu = domain_get_iommu(domain);
ba395927
KA		 1441 if (guest_width > cap_mgaw(iommu->cap))
1442 guest_width = cap_mgaw(iommu->cap);
1443 domain->gaw = guest_width;
1444 adjust_width = guestwidth_to_adjustwidth(guest_width);
1445 agaw = width_to_agaw(adjust_width);
1446 sagaw = cap_sagaw(iommu->cap);
1447 if (!test_bit(agaw, &sagaw)) {
1448 /* hardware doesn't support it, choose a bigger one */
1449 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1450 agaw = find_next_bit(&sagaw, 5, agaw);
1451 if (agaw >= 5)
1452 return -ENODEV;
1453 }
1454 domain->agaw = agaw;
1455 INIT_LIST_HEAD(&domain->devices);
1456
8e604097
WH		 1457 if (ecap_coherent(iommu->ecap))
1458 domain->iommu_coherency = 1;
1459 else
1460 domain->iommu_coherency = 0;
1461
58c610bd
SY		 1462 if (ecap_sc_support(iommu->ecap))
1463 domain->iommu_snooping = 1;
1464 else
1465 domain->iommu_snooping = 0;
1466
6dd9a7c7 1467 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
c7151a8d 1468 domain->iommu_count = 1;
4c923d47 1469 domain->nid = iommu->node;
c7151a8d 1470
ba395927 1471 /* always allocate the top pgd */
4c923d47 1472 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1473 if (!domain->pgd)
1474 return -ENOMEM;
5b6985ce 1475 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1476 return 0;
1477}
1478
1479static void domain_exit(struct dmar_domain *domain)
1480{
2c2e2c38
FY		 1481 struct dmar_drhd_unit *drhd;
1482 struct intel_iommu *iommu;
ba395927
KA		 1483
1484 /* Domain 0 is reserved, so dont process it */
1485 if (!domain)
1486 return;
1487
7b668357
AW		 1488 /* Flush any lazy unmaps that may reference this domain */
1489 if (!intel_iommu_strict)
1490 flush_unmaps_timeout(0);
1491
ba395927
KA		 1492 domain_remove_dev_info(domain);
1493 /* destroy iovas */
1494 put_iova_domain(&domain->iovad);
ba395927
KA		 1495
1496 /* clear ptes */
595badf5 1497 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1498
1499 /* free page tables */
d794dc9b 1500 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1501
2c2e2c38
FY		 1502 for_each_active_iommu(iommu, drhd)
1503 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1504 iommu_detach_domain(domain, iommu);
1505
ba395927
KA		 1506 free_domain_mem(domain);
1507}
1508
4ed0d3e6
FY		 1509static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1510 u8 bus, u8 devfn, int translation)
ba395927
KA		 1511{
1512 struct context_entry *context;
ba395927 1513 unsigned long flags;
5331fe6f 1514 struct intel_iommu *iommu;
ea6606b0
WH		 1515 struct dma_pte *pgd;
1516 unsigned long num;
1517 unsigned long ndomains;
1518 int id;
1519 int agaw;
93a23a72 1520 struct device_domain_info *info = NULL;
ba395927
KA		 1521
1522 pr_debug("Set context mapping for %02x:%02x.%d\n",
1523 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1524
ba395927 1525 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1526 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1527 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1528
276dbf99 1529 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1530 if (!iommu)
1531 return -ENODEV;
1532
ba395927
KA		 1533 context = device_to_context_entry(iommu, bus, devfn);
1534 if (!context)
1535 return -ENOMEM;
1536 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1537 if (context_present(context)) {
ba395927
KA		 1538 spin_unlock_irqrestore(&iommu->lock, flags);
1539 return 0;
1540 }
1541
ea6606b0
WH		 1542 id = domain->id;
1543 pgd = domain->pgd;
1544
2c2e2c38
FY		 1545 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1546 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1547 int found = 0;
1548
1549 /* find an available domain id for this device in iommu */
1550 ndomains = cap_ndoms(iommu->cap);
a45946ab 1551 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1552 if (iommu->domains[num] == domain) {
1553 id = num;
1554 found = 1;
1555 break;
1556 }
ea6606b0
WH		 1557 }
1558
1559 if (found == 0) {
1560 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1561 if (num >= ndomains) {
1562 spin_unlock_irqrestore(&iommu->lock, flags);
1563 printk(KERN_ERR "IOMMU: no free domain ids\n");
1564 return -EFAULT;
1565 }
1566
1567 set_bit(num, iommu->domain_ids);
1568 iommu->domains[num] = domain;
1569 id = num;
1570 }
1571
1572 /* Skip top levels of page tables for
1573 * iommu which has less agaw than default.
1672af11 1574 * Unnecessary for PT mode.
ea6606b0 1575 */
1672af11
CW		 1576 if (translation != CONTEXT_TT_PASS_THROUGH) {
1577 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1578 pgd = phys_to_virt(dma_pte_addr(pgd));
1579 if (!dma_pte_present(pgd)) {
1580 spin_unlock_irqrestore(&iommu->lock, flags);
1581 return -ENOMEM;
1582 }
ea6606b0
WH		 1583 }
1584 }
1585 }
1586
1587 context_set_domain_id(context, id);
4ed0d3e6 1588
93a23a72
YZ		 1589 if (translation != CONTEXT_TT_PASS_THROUGH) {
1590 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1591 translation = info ? CONTEXT_TT_DEV_IOTLB :
1592 CONTEXT_TT_MULTI_LEVEL;
1593 }
4ed0d3e6
FY		 1594 /*
1595 * In pass through mode, AW must be programmed to indicate the largest
1596 * AGAW value supported by hardware. And ASR is ignored by hardware.
1597 */
93a23a72 1598 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1599 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1600 else {
1601 context_set_address_root(context, virt_to_phys(pgd));
1602 context_set_address_width(context, iommu->agaw);
1603 }
4ed0d3e6
FY		 1604
1605 context_set_translation_type(context, translation);
c07e7d21
MM		 1606 context_set_fault_enable(context);
1607 context_set_present(context);
5331fe6f 1608 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1609
4c25a2c1
DW		 1610 /*
1611 * It's a non-present to present mapping. If hardware doesn't cache
1612 * non-present entry we only need to flush the write-buffer. If the
1613 * _does_ cache non-present entries, then it does so in the special
1614 * domain #0, which we have to flush:
1615 */
1616 if (cap_caching_mode(iommu->cap)) {
1617 iommu->flush.flush_context(iommu, 0,
1618 (((u16)bus) << 8) | devfn,
1619 DMA_CCMD_MASK_NOBIT,
1620 DMA_CCMD_DEVICE_INVL);
82653633 1621 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1622 } else {
ba395927 1623 iommu_flush_write_buffer(iommu);
4c25a2c1 1624 }
93a23a72 1625 iommu_enable_dev_iotlb(info);
ba395927 1626 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1627
1628 spin_lock_irqsave(&domain->iommu_lock, flags);
1629 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1630 domain->iommu_count++;
4c923d47
SS		 1631 if (domain->iommu_count == 1)
1632 domain->nid = iommu->node;
58c610bd 1633 domain_update_iommu_cap(domain);
c7151a8d
WH		 1634 }
1635 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1636 return 0;
1637}
1638
1639static int
4ed0d3e6
FY		 1640domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1641 int translation)
ba395927
KA		 1642{
1643 int ret;
1644 struct pci_dev *tmp, *parent;
1645
276dbf99 1646 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1647 pdev->bus->number, pdev->devfn,
1648 translation);
ba395927
KA		 1649 if (ret)
1650 return ret;
1651
1652 /* dependent device mapping */
1653 tmp = pci_find_upstream_pcie_bridge(pdev);
1654 if (!tmp)
1655 return 0;
1656 /* Secondary interface's bus number and devfn 0 */
1657 parent = pdev->bus->self;
1658 while (parent != tmp) {
276dbf99
DW		 1659 ret = domain_context_mapping_one(domain,
1660 pci_domain_nr(parent->bus),
1661 parent->bus->number,
4ed0d3e6 1662 parent->devfn, translation);
ba395927
KA		 1663 if (ret)
1664 return ret;
1665 parent = parent->bus->self;
1666 }
45e829ea 1667 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
ba395927 1668 return domain_context_mapping_one(domain,
276dbf99 1669 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1670 tmp->subordinate->number, 0,
1671 translation);
ba395927
KA		 1672 else /* this is a legacy PCI bridge */
1673 return domain_context_mapping_one(domain,
276dbf99
DW		 1674 pci_domain_nr(tmp->bus),
1675 tmp->bus->number,
4ed0d3e6
FY		 1676 tmp->devfn,
1677 translation);
ba395927
KA		 1678}
1679
5331fe6f 1680static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1681{
1682 int ret;
1683 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1684 struct intel_iommu *iommu;
1685
276dbf99
DW		 1686 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1687 pdev->devfn);
5331fe6f
WH		 1688 if (!iommu)
1689 return -ENODEV;
ba395927 1690
276dbf99 1691 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1692 if (!ret)
1693 return ret;
1694 /* dependent device mapping */
1695 tmp = pci_find_upstream_pcie_bridge(pdev);
1696 if (!tmp)
1697 return ret;
1698 /* Secondary interface's bus number and devfn 0 */
1699 parent = pdev->bus->self;
1700 while (parent != tmp) {
8c11e798 1701 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1702 parent->devfn);
ba395927
KA		 1703 if (!ret)
1704 return ret;
1705 parent = parent->bus->self;
1706 }
5f4d91a1 1707 if (pci_is_pcie(tmp))
276dbf99
DW		 1708 return device_context_mapped(iommu, tmp->subordinate->number,
1709 0);
ba395927 1710 else
276dbf99
DW		 1711 return device_context_mapped(iommu, tmp->bus->number,
1712 tmp->devfn);
ba395927
KA		 1713}
1714
f532959b
FY		 1715/* Returns a number of VTD pages, but aligned to MM page size */
1716static inline unsigned long aligned_nrpages(unsigned long host_addr,
1717 size_t size)
1718{
1719 host_addr &= ~PAGE_MASK;
1720 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1721}
1722
6dd9a7c7
YS		 1723/* Return largest possible superpage level for a given mapping */
1724static inline int hardware_largepage_caps(struct dmar_domain *domain,
1725 unsigned long iov_pfn,
1726 unsigned long phy_pfn,
1727 unsigned long pages)
1728{
1729 int support, level = 1;
1730 unsigned long pfnmerge;
1731
1732 support = domain->iommu_superpage;
1733
1734 /* To use a large page, the virtual *and* physical addresses
1735 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1736 of them will mean we have to use smaller pages. So just
1737 merge them and check both at once. */
1738 pfnmerge = iov_pfn | phy_pfn;
1739
1740 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1741 pages >>= VTD_STRIDE_SHIFT;
1742 if (!pages)
1743 break;
1744 pfnmerge >>= VTD_STRIDE_SHIFT;
1745 level++;
1746 support--;
1747 }
1748 return level;
1749}
1750
9051aa02
DW		 1751static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1752 struct scatterlist *sg, unsigned long phys_pfn,
1753 unsigned long nr_pages, int prot)
e1605495
DW		 1754{
1755 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1756 phys_addr_t uninitialized_var(pteval);
e1605495 1757 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1758 unsigned long sg_res;
6dd9a7c7
YS		 1759 unsigned int largepage_lvl = 0;
1760 unsigned long lvl_pages = 0;
e1605495
DW		 1761
1762 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1763
1764 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1765 return -EINVAL;
1766
1767 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1768
9051aa02
DW		 1769 if (sg)
1770 sg_res = 0;
1771 else {
1772 sg_res = nr_pages + 1;
1773 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1774 }
1775
6dd9a7c7 1776 while (nr_pages > 0) {
c85994e4
DW		 1777 uint64_t tmp;
1778
e1605495 1779 if (!sg_res) {
f532959b 1780 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1781 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1782 sg->dma_length = sg->length;
1783 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1784 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1785 }
6dd9a7c7 1786
e1605495 1787 if (!pte) {
6dd9a7c7
YS		 1788 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1789
1790 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
e1605495
DW		 1791 if (!pte)
1792 return -ENOMEM;
6dd9a7c7
YS		 1793 /* It is large page*/
1794 if (largepage_lvl > 1)
1795 pteval |= DMA_PTE_LARGE_PAGE;
1796 else
1797 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
1798
e1605495
DW		 1799 }
1800 /* We don't need lock here, nobody else
1801 * touches the iova range
1802 */
7766a3fb 1803 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1804 if (tmp) {
1bf20f0d 1805 static int dumps = 5;
c85994e4
DW		 1806 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1807 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1808 if (dumps) {
1809 dumps--;
1810 debug_dma_dump_mappings(NULL);
1811 }
1812 WARN_ON(1);
1813 }
6dd9a7c7
YS		 1814
1815 lvl_pages = lvl_to_nr_pages(largepage_lvl);
1816
1817 BUG_ON(nr_pages < lvl_pages);
1818 BUG_ON(sg_res < lvl_pages);
1819
1820 nr_pages -= lvl_pages;
1821 iov_pfn += lvl_pages;
1822 phys_pfn += lvl_pages;
1823 pteval += lvl_pages * VTD_PAGE_SIZE;
1824 sg_res -= lvl_pages;
1825
1826 /* If the next PTE would be the first in a new page, then we
1827 need to flush the cache on the entries we've just written.
1828 And then we'll need to recalculate 'pte', so clear it and
1829 let it get set again in the if (!pte) block above.
1830
1831 If we're done (!nr_pages) we need to flush the cache too.
1832
1833 Also if we've been setting superpages, we may need to
1834 recalculate 'pte' and switch back to smaller pages for the
1835 end of the mapping, if the trailing size is not enough to
1836 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 1837 pte++;
6dd9a7c7
YS		 1838 if (!nr_pages || first_pte_in_page(pte) ||
1839 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 1840 domain_flush_cache(domain, first_pte,
1841 (void *)pte - (void *)first_pte);
1842 pte = NULL;
1843 }
6dd9a7c7
YS		 1844
1845 if (!sg_res && nr_pages)
e1605495
DW		 1846 sg = sg_next(sg);
1847 }
1848 return 0;
1849}
1850
9051aa02
DW		 1851static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1852 struct scatterlist *sg, unsigned long nr_pages,
1853 int prot)
ba395927 1854{
9051aa02
DW		 1855 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1856}
6f6a00e4 1857
9051aa02
DW		 1858static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1859 unsigned long phys_pfn, unsigned long nr_pages,
1860 int prot)
1861{
1862 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1863}
1864
c7151a8d 1865static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1866{
c7151a8d
WH		 1867 if (!iommu)
1868 return;
8c11e798
WH		 1869
1870 clear_context_table(iommu, bus, devfn);
1871 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1872 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1873 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1874}
1875
1876static void domain_remove_dev_info(struct dmar_domain *domain)
1877{
1878 struct device_domain_info *info;
1879 unsigned long flags;
c7151a8d 1880 struct intel_iommu *iommu;
ba395927
KA		 1881
1882 spin_lock_irqsave(&device_domain_lock, flags);
1883 while (!list_empty(&domain->devices)) {
1884 info = list_entry(domain->devices.next,
1885 struct device_domain_info, link);
1886 list_del(&info->link);
1887 list_del(&info->global);
1888 if (info->dev)
358dd8ac 1889 info->dev->dev.archdata.iommu = NULL;
ba395927
KA		 1890 spin_unlock_irqrestore(&device_domain_lock, flags);
1891
93a23a72 1892 iommu_disable_dev_iotlb(info);
276dbf99 1893 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1894 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1895 free_devinfo_mem(info);
1896
1897 spin_lock_irqsave(&device_domain_lock, flags);
1898 }
1899 spin_unlock_irqrestore(&device_domain_lock, flags);
1900}
1901
1902/*
1903 * find_domain
358dd8ac 1904 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1905 */
38717946 1906static struct dmar_domain *
ba395927
KA		 1907find_domain(struct pci_dev *pdev)
1908{
1909 struct device_domain_info *info;
1910
1911 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1912 info = pdev->dev.archdata.iommu;
ba395927
KA		 1913 if (info)
1914 return info->domain;
1915 return NULL;
1916}
1917
ba395927
KA		 1918/* domain is initialized */
1919static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1920{
1921 struct dmar_domain *domain, *found = NULL;
1922 struct intel_iommu *iommu;
1923 struct dmar_drhd_unit *drhd;
1924 struct device_domain_info *info, *tmp;
1925 struct pci_dev *dev_tmp;
1926 unsigned long flags;
1927 int bus = 0, devfn = 0;
276dbf99 1928 int segment;
2c2e2c38 1929 int ret;
ba395927
KA		 1930
1931 domain = find_domain(pdev);
1932 if (domain)
1933 return domain;
1934
276dbf99
DW		 1935 segment = pci_domain_nr(pdev->bus);
1936
ba395927
KA		 1937 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1938 if (dev_tmp) {
5f4d91a1 1939 if (pci_is_pcie(dev_tmp)) {
ba395927
KA		 1940 bus = dev_tmp->subordinate->number;
1941 devfn = 0;
1942 } else {
1943 bus = dev_tmp->bus->number;
1944 devfn = dev_tmp->devfn;
1945 }
1946 spin_lock_irqsave(&device_domain_lock, flags);
1947 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1948 if (info->segment == segment &&
1949 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1950 found = info->domain;
1951 break;
1952 }
1953 }
1954 spin_unlock_irqrestore(&device_domain_lock, flags);
1955 /* pcie-pci bridge already has a domain, uses it */
1956 if (found) {
1957 domain = found;
1958 goto found_domain;
1959 }
1960 }
1961
2c2e2c38
FY		 1962 domain = alloc_domain();
1963 if (!domain)
1964 goto error;
1965
ba395927
KA		 1966 /* Allocate new domain for the device */
1967 drhd = dmar_find_matched_drhd_unit(pdev);
1968 if (!drhd) {
1969 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1970 pci_name(pdev));
1971 return NULL;
1972 }
1973 iommu = drhd->iommu;
1974
2c2e2c38
FY		 1975 ret = iommu_attach_domain(domain, iommu);
1976 if (ret) {
2fe9723d 1977 free_domain_mem(domain);
ba395927 1978 goto error;
2c2e2c38 1979 }
ba395927
KA		 1980
1981 if (domain_init(domain, gaw)) {
1982 domain_exit(domain);
1983 goto error;
1984 }
1985
1986 /* register pcie-to-pci device */
1987 if (dev_tmp) {
1988 info = alloc_devinfo_mem();
1989 if (!info) {
1990 domain_exit(domain);
1991 goto error;
1992 }
276dbf99 1993 info->segment = segment;
ba395927
KA		 1994 info->bus = bus;
1995 info->devfn = devfn;
1996 info->dev = NULL;
1997 info->domain = domain;
1998 /* This domain is shared by devices under p2p bridge */
3b5410e7 1999 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 2000
2001 /* pcie-to-pci bridge already has a domain, uses it */
2002 found = NULL;
2003 spin_lock_irqsave(&device_domain_lock, flags);
2004 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 2005 if (tmp->segment == segment &&
2006 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 2007 found = tmp->domain;
2008 break;
2009 }
2010 }
2011 if (found) {
00dfff77 2012 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927
KA		 2013 free_devinfo_mem(info);
2014 domain_exit(domain);
2015 domain = found;
2016 } else {
2017 list_add(&info->link, &domain->devices);
2018 list_add(&info->global, &device_domain_list);
00dfff77 2019 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2020 }
ba395927
KA		 2021 }
2022
2023found_domain:
2024 info = alloc_devinfo_mem();
2025 if (!info)
2026 goto error;
276dbf99 2027 info->segment = segment;
ba395927
KA		 2028 info->bus = pdev->bus->number;
2029 info->devfn = pdev->devfn;
2030 info->dev = pdev;
2031 info->domain = domain;
2032 spin_lock_irqsave(&device_domain_lock, flags);
2033 /* somebody is fast */
2034 found = find_domain(pdev);
2035 if (found != NULL) {
2036 spin_unlock_irqrestore(&device_domain_lock, flags);
2037 if (found != domain) {
2038 domain_exit(domain);
2039 domain = found;
2040 }
2041 free_devinfo_mem(info);
2042 return domain;
2043 }
2044 list_add(&info->link, &domain->devices);
2045 list_add(&info->global, &device_domain_list);
358dd8ac 2046 pdev->dev.archdata.iommu = info;
ba395927
KA		 2047 spin_unlock_irqrestore(&device_domain_lock, flags);
2048 return domain;
2049error:
2050 /* recheck it here, maybe others set it */
2051 return find_domain(pdev);
2052}
2053
2c2e2c38 2054static int iommu_identity_mapping;
e0fc7e0b
DW		 2055#define IDENTMAP_ALL 1
2056#define IDENTMAP_GFX 2
2057#define IDENTMAP_AZALIA 4
2c2e2c38 2058
b213203e
DW		 2059static int iommu_domain_identity_map(struct dmar_domain *domain,
2060 unsigned long long start,
2061 unsigned long long end)
ba395927 2062{
c5395d5c
DW		 2063 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2064 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2065
2066 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2067 dma_to_mm_pfn(last_vpfn))) {
ba395927 2068 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2069 return -ENOMEM;
ba395927
KA		 2070 }
2071
c5395d5c
DW		 2072 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2073 start, end, domain->id);
ba395927
KA		 2074 /*
2075 * RMRR range might have overlap with physical memory range,
2076 * clear it first
2077 */
c5395d5c 2078 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2079
c5395d5c
DW		 2080 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2081 last_vpfn - first_vpfn + 1,
61df7443 2082 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2083}
2084
2085static int iommu_prepare_identity_map(struct pci_dev *pdev,
2086 unsigned long long start,
2087 unsigned long long end)
2088{
2089 struct dmar_domain *domain;
2090 int ret;
2091
c7ab48d2 2092 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2093 if (!domain)
2094 return -ENOMEM;
2095
19943b0e
DW		 2096 /* For _hardware_ passthrough, don't bother. But for software
2097 passthrough, we do it anyway -- it may indicate a memory
2098 range which is reserved in E820, so which didn't get set
2099 up to start with in si_domain */
2100 if (domain == si_domain && hw_pass_through) {
2101 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2102 pci_name(pdev), start, end);
2103 return 0;
2104 }
2105
2106 printk(KERN_INFO
2107 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2108 pci_name(pdev), start, end);
2ff729f5 2109
5595b528
DW		 2110 if (end < start) {
2111 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2112 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2113 dmi_get_system_info(DMI_BIOS_VENDOR),
2114 dmi_get_system_info(DMI_BIOS_VERSION),
2115 dmi_get_system_info(DMI_PRODUCT_VERSION));
2116 ret = -EIO;
2117 goto error;
2118 }
2119
2ff729f5
DW		 2120 if (end >> agaw_to_width(domain->agaw)) {
2121 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2122 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2123 agaw_to_width(domain->agaw),
2124 dmi_get_system_info(DMI_BIOS_VENDOR),
2125 dmi_get_system_info(DMI_BIOS_VERSION),
2126 dmi_get_system_info(DMI_PRODUCT_VERSION));
2127 ret = -EIO;
2128 goto error;
2129 }
19943b0e 2130
b213203e 2131 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2132 if (ret)
2133 goto error;
2134
2135 /* context entry init */
4ed0d3e6 2136 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2137 if (ret)
2138 goto error;
2139
2140 return 0;
2141
2142 error:
ba395927
KA		 2143 domain_exit(domain);
2144 return ret;
ba395927
KA		 2145}
2146
2147static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2148 struct pci_dev *pdev)
2149{
358dd8ac 2150 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2151 return 0;
2152 return iommu_prepare_identity_map(pdev, rmrr->base_address,
70e535d1 2153 rmrr->end_address);
ba395927
KA		 2154}
2155
49a0429e
KA		 2156#ifdef CONFIG_DMAR_FLOPPY_WA
2157static inline void iommu_prepare_isa(void)
2158{
2159 struct pci_dev *pdev;
2160 int ret;
2161
2162 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2163 if (!pdev)
2164 return;
2165
c7ab48d2 2166 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
70e535d1 2167 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2168
2169 if (ret)
c7ab48d2
DW		 2170 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2171 "floppy might not work\n");
49a0429e
KA		 2172
2173}
2174#else
2175static inline void iommu_prepare_isa(void)
2176{
2177 return;
2178}
2179#endif /* !CONFIG_DMAR_FLPY_WA */
2180
2c2e2c38 2181static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2
DW		 2182
2183static int __init si_domain_work_fn(unsigned long start_pfn,
2184 unsigned long end_pfn, void *datax)
2185{
2186 int *ret = datax;
2187
2188 *ret = iommu_domain_identity_map(si_domain,
2189 (uint64_t)start_pfn << PAGE_SHIFT,
2190 (uint64_t)end_pfn << PAGE_SHIFT);
2191 return *ret;
2192
2193}
2194
071e1374 2195static int __init si_domain_init(int hw)
2c2e2c38
FY		 2196{
2197 struct dmar_drhd_unit *drhd;
2198 struct intel_iommu *iommu;
c7ab48d2 2199 int nid, ret = 0;
2c2e2c38
FY		 2200
2201 si_domain = alloc_domain();
2202 if (!si_domain)
2203 return -EFAULT;
2204
c7ab48d2 2205 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2c2e2c38
FY		 2206
2207 for_each_active_iommu(iommu, drhd) {
2208 ret = iommu_attach_domain(si_domain, iommu);
2209 if (ret) {
2210 domain_exit(si_domain);
2211 return -EFAULT;
2212 }
2213 }
2214
2215 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2216 domain_exit(si_domain);
2217 return -EFAULT;
2218 }
2219
2220 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2221
19943b0e
DW		 2222 if (hw)
2223 return 0;
2224
c7ab48d2
DW		 2225 for_each_online_node(nid) {
2226 work_with_active_regions(nid, si_domain_work_fn, &ret);
2227 if (ret)
2228 return ret;
2229 }
2230
2c2e2c38
FY		 2231 return 0;
2232}
2233
2234static void domain_remove_one_dev_info(struct dmar_domain *domain,
2235 struct pci_dev *pdev);
2236static int identity_mapping(struct pci_dev *pdev)
2237{
2238 struct device_domain_info *info;
2239
2240 if (likely(!iommu_identity_mapping))
2241 return 0;
2242
cb452a40
MT		 2243 info = pdev->dev.archdata.iommu;
2244 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2245 return (info->domain == si_domain);
2c2e2c38 2246
2c2e2c38
FY		 2247 return 0;
2248}
2249
2250static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2251 struct pci_dev *pdev,
2252 int translation)
2c2e2c38
FY		 2253{
2254 struct device_domain_info *info;
2255 unsigned long flags;
5fe60f4e 2256 int ret;
2c2e2c38
FY		 2257
2258 info = alloc_devinfo_mem();
2259 if (!info)
2260 return -ENOMEM;
2261
5fe60f4e
DW		 2262 ret = domain_context_mapping(domain, pdev, translation);
2263 if (ret) {
2264 free_devinfo_mem(info);
2265 return ret;
2266 }
2267
2c2e2c38
FY		 2268 info->segment = pci_domain_nr(pdev->bus);
2269 info->bus = pdev->bus->number;
2270 info->devfn = pdev->devfn;
2271 info->dev = pdev;
2272 info->domain = domain;
2273
2274 spin_lock_irqsave(&device_domain_lock, flags);
2275 list_add(&info->link, &domain->devices);
2276 list_add(&info->global, &device_domain_list);
2277 pdev->dev.archdata.iommu = info;
2278 spin_unlock_irqrestore(&device_domain_lock, flags);
2279
2280 return 0;
2281}
2282
6941af28
DW		 2283static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2284{
e0fc7e0b
DW		 2285 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2286 return 1;
2287
2288 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2289 return 1;
2290
2291 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2292 return 0;
6941af28 2293
3dfc813d
DW		 2294 /*
2295 * We want to start off with all devices in the 1:1 domain, and
2296 * take them out later if we find they can't access all of memory.
2297 *
2298 * However, we can't do this for PCI devices behind bridges,
2299 * because all PCI devices behind the same bridge will end up
2300 * with the same source-id on their transactions.
2301 *
2302 * Practically speaking, we can't change things around for these
2303 * devices at run-time, because we can't be sure there'll be no
2304 * DMA transactions in flight for any of their siblings.
2305 *
2306 * So PCI devices (unless they're on the root bus) as well as
2307 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2308 * the 1:1 domain, just in _case_ one of their siblings turns out
2309 * not to be able to map all of memory.
2310 */
5f4d91a1 2311 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2312 if (!pci_is_root_bus(pdev->bus))
2313 return 0;
2314 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2315 return 0;
2316 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2317 return 0;
2318
2319 /*
2320 * At boot time, we don't yet know if devices will be 64-bit capable.
2321 * Assume that they will -- if they turn out not to be, then we can
2322 * take them out of the 1:1 domain later.
2323 */
8fcc5372
CW		 2324 if (!startup) {
2325 /*
2326 * If the device's dma_mask is less than the system's memory
2327 * size then this is not a candidate for identity mapping.
2328 */
2329 u64 dma_mask = pdev->dma_mask;
2330
2331 if (pdev->dev.coherent_dma_mask &&
2332 pdev->dev.coherent_dma_mask < dma_mask)
2333 dma_mask = pdev->dev.coherent_dma_mask;
2334
2335 return dma_mask >= dma_get_required_mask(&pdev->dev);
2336 }
6941af28
DW		 2337
2338 return 1;
2339}
2340
071e1374 2341static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2342{
2c2e2c38
FY		 2343 struct pci_dev *pdev = NULL;
2344 int ret;
2345
19943b0e 2346 ret = si_domain_init(hw);
2c2e2c38
FY		 2347 if (ret)
2348 return -EFAULT;
2349
2c2e2c38 2350 for_each_pci_dev(pdev) {
825507d6
MT		 2351 /* Skip Host/PCI Bridge devices */
2352 if (IS_BRIDGE_HOST_DEVICE(pdev))
2353 continue;
6941af28 2354 if (iommu_should_identity_map(pdev, 1)) {
19943b0e
DW		 2355 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2356 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2357
5fe60f4e 2358 ret = domain_add_dev_info(si_domain, pdev,
19943b0e 2359 hw ? CONTEXT_TT_PASS_THROUGH :
62edf5dc
DW		 2360 CONTEXT_TT_MULTI_LEVEL);
2361 if (ret)
2362 return ret;
62edf5dc 2363 }
2c2e2c38
FY		 2364 }
2365
2366 return 0;
2367}
2368
b779260b 2369static int __init init_dmars(void)
ba395927
KA		 2370{
2371 struct dmar_drhd_unit *drhd;
2372 struct dmar_rmrr_unit *rmrr;
2373 struct pci_dev *pdev;
2374 struct intel_iommu *iommu;
9d783ba0 2375 int i, ret;
2c2e2c38 2376
ba395927
KA		 2377 /*
2378 * for each drhd
2379 * allocate root
2380 * initialize and program root entry to not present
2381 * endfor
2382 */
2383 for_each_drhd_unit(drhd) {
5e0d2a6f 2384 g_num_of_iommus++;
2385 /*
2386 * lock not needed as this is only incremented in the single
2387 * threaded kernel __init code path all other access are read
2388 * only
2389 */
2390 }
2391
d9630fe9
WH		 2392 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2393 GFP_KERNEL);
2394 if (!g_iommus) {
2395 printk(KERN_ERR "Allocating global iommu array failed\n");
2396 ret = -ENOMEM;
2397 goto error;
2398 }
2399
80b20dd8 2400 deferred_flush = kzalloc(g_num_of_iommus *
2401 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2402 if (!deferred_flush) {
5e0d2a6f 2403 ret = -ENOMEM;
2404 goto error;
2405 }
2406
5e0d2a6f 2407 for_each_drhd_unit(drhd) {
2408 if (drhd->ignored)
2409 continue;
1886e8a9
SS		 2410
2411 iommu = drhd->iommu;
d9630fe9 2412 g_iommus[iommu->seq_id] = iommu;
ba395927 2413
e61d98d8
SS		 2414 ret = iommu_init_domains(iommu);
2415 if (ret)
2416 goto error;
2417
ba395927
KA		 2418 /*
2419 * TBD:
2420 * we could share the same root & context tables
25985edc 2421 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2422 */
2423 ret = iommu_alloc_root_entry(iommu);
2424 if (ret) {
2425 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2426 goto error;
2427 }
4ed0d3e6 2428 if (!ecap_pass_through(iommu->ecap))
19943b0e 2429 hw_pass_through = 0;
ba395927
KA		 2430 }
2431
1531a6a6
SS		 2432 /*
2433 * Start from the sane iommu hardware state.
2434 */
a77b67d4
YS		 2435 for_each_drhd_unit(drhd) {
2436 if (drhd->ignored)
2437 continue;
2438
2439 iommu = drhd->iommu;
1531a6a6
SS		 2440
2441 /*
2442 * If the queued invalidation is already initialized by us
2443 * (for example, while enabling interrupt-remapping) then
2444 * we got the things already rolling from a sane state.
2445 */
2446 if (iommu->qi)
2447 continue;
2448
2449 /*
2450 * Clear any previous faults.
2451 */
2452 dmar_fault(-1, iommu);
2453 /*
2454 * Disable queued invalidation if supported and already enabled
2455 * before OS handover.
2456 */
2457 dmar_disable_qi(iommu);
2458 }
2459
2460 for_each_drhd_unit(drhd) {
2461 if (drhd->ignored)
2462 continue;
2463
2464 iommu = drhd->iommu;
2465
a77b67d4
YS		 2466 if (dmar_enable_qi(iommu)) {
2467 /*
2468 * Queued Invalidate not enabled, use Register Based
2469 * Invalidate
2470 */
2471 iommu->flush.flush_context = __iommu_flush_context;
2472 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2473 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2474 "invalidation\n",
680a7524 2475 iommu->seq_id,
b4e0f9eb 2476 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2477 } else {
2478 iommu->flush.flush_context = qi_flush_context;
2479 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2480 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2481 "invalidation\n",
680a7524 2482 iommu->seq_id,
b4e0f9eb 2483 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2484 }
2485 }
2486
19943b0e 2487 if (iommu_pass_through)
e0fc7e0b
DW		 2488 iommu_identity_mapping |= IDENTMAP_ALL;
2489
19943b0e 2490#ifdef CONFIG_DMAR_BROKEN_GFX_WA
e0fc7e0b 2491 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2492#endif
e0fc7e0b
DW		 2493
2494 check_tylersburg_isoch();
2495
ba395927 2496 /*
19943b0e
DW		 2497 * If pass through is not set or not enabled, setup context entries for
2498 * identity mappings for rmrr, gfx, and isa and may fall back to static
2499 * identity mapping if iommu_identity_mapping is set.
ba395927 2500 */
19943b0e
DW		 2501 if (iommu_identity_mapping) {
2502 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2503 if (ret) {
19943b0e
DW		 2504 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2505 goto error;
ba395927
KA		 2506 }
2507 }
ba395927 2508 /*
19943b0e
DW		 2509 * For each rmrr
2510 * for each dev attached to rmrr
2511 * do
2512 * locate drhd for dev, alloc domain for dev
2513 * allocate free domain
2514 * allocate page table entries for rmrr
2515 * if context not allocated for bus
2516 * allocate and init context
2517 * set present in root table for this bus
2518 * init context with domain, translation etc
2519 * endfor
2520 * endfor
ba395927 2521 */
19943b0e
DW		 2522 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2523 for_each_rmrr_units(rmrr) {
2524 for (i = 0; i < rmrr->devices_cnt; i++) {
2525 pdev = rmrr->devices[i];
2526 /*
2527 * some BIOS lists non-exist devices in DMAR
2528 * table.
2529 */
2530 if (!pdev)
2531 continue;
2532 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2533 if (ret)
2534 printk(KERN_ERR
2535 "IOMMU: mapping reserved region failed\n");
ba395927 2536 }
4ed0d3e6 2537 }
49a0429e 2538
19943b0e
DW		 2539 iommu_prepare_isa();
2540
ba395927
KA		 2541 /*
2542 * for each drhd
2543 * enable fault log
2544 * global invalidate context cache
2545 * global invalidate iotlb
2546 * enable translation
2547 */
2548 for_each_drhd_unit(drhd) {
51a63e67
JC		 2549 if (drhd->ignored) {
2550 /*
2551 * we always have to disable PMRs or DMA may fail on
2552 * this device
2553 */
2554 if (force_on)
2555 iommu_disable_protect_mem_regions(drhd->iommu);
ba395927 2556 continue;
51a63e67 2557 }
ba395927 2558 iommu = drhd->iommu;
ba395927
KA		 2559
2560 iommu_flush_write_buffer(iommu);
2561
3460a6d9
KA		 2562 ret = dmar_set_interrupt(iommu);
2563 if (ret)
2564 goto error;
2565
ba395927
KA		 2566 iommu_set_root_entry(iommu);
2567
4c25a2c1 2568 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2569 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2570
ba395927
KA		 2571 ret = iommu_enable_translation(iommu);
2572 if (ret)
2573 goto error;
b94996c9
DW		 2574
2575 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2576 }
2577
2578 return 0;
2579error:
2580 for_each_drhd_unit(drhd) {
2581 if (drhd->ignored)
2582 continue;
2583 iommu = drhd->iommu;
2584 free_iommu(iommu);
2585 }
d9630fe9 2586 kfree(g_iommus);
ba395927
KA		 2587 return ret;
2588}
2589
5a5e02a6 2590/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2591static struct iova *intel_alloc_iova(struct device *dev,
2592 struct dmar_domain *domain,
2593 unsigned long nrpages, uint64_t dma_mask)
ba395927 2594{
ba395927 2595 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2596 struct iova *iova = NULL;
ba395927 2597
875764de
DW		 2598 /* Restrict dma_mask to the width that the iommu can handle */
2599 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2600
2601 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2602 /*
2603 * First try to allocate an io virtual address in
284901a9 2604 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2605 * from higher range
ba395927 2606 */
875764de
DW		 2607 iova = alloc_iova(&domain->iovad, nrpages,
2608 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2609 if (iova)
2610 return iova;
2611 }
2612 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2613 if (unlikely(!iova)) {
2614 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2615 nrpages, pci_name(pdev));
f76aec76
KA		 2616 return NULL;
2617 }
2618
2619 return iova;
2620}
2621
147202aa 2622static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2623{
2624 struct dmar_domain *domain;
2625 int ret;
2626
2627 domain = get_domain_for_dev(pdev,
2628 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2629 if (!domain) {
2630 printk(KERN_ERR
2631 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2632 return NULL;
ba395927
KA		 2633 }
2634
2635 /* make sure context mapping is ok */
5331fe6f 2636 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2637 ret = domain_context_mapping(domain, pdev,
2638 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2639 if (ret) {
2640 printk(KERN_ERR
2641 "Domain context map for %s failed",
2642 pci_name(pdev));
4fe05bbc 2643 return NULL;
f76aec76 2644 }
ba395927
KA		 2645 }
2646
f76aec76
KA		 2647 return domain;
2648}
2649
147202aa
DW		 2650static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2651{
2652 struct device_domain_info *info;
2653
2654 /* No lock here, assumes no domain exit in normal case */
2655 info = dev->dev.archdata.iommu;
2656 if (likely(info))
2657 return info->domain;
2658
2659 return __get_valid_domain_for_dev(dev);
2660}
2661
2c2e2c38
FY		 2662static int iommu_dummy(struct pci_dev *pdev)
2663{
2664 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2665}
2666
2667/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2668static int iommu_no_mapping(struct device *dev)
2c2e2c38 2669{
73676832 2670 struct pci_dev *pdev;
2c2e2c38
FY		 2671 int found;
2672
73676832
DW		 2673 if (unlikely(dev->bus != &pci_bus_type))
2674 return 1;
2675
2676 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2677 if (iommu_dummy(pdev))
2678 return 1;
2679
2c2e2c38 2680 if (!iommu_identity_mapping)
1e4c64c4 2681 return 0;
2c2e2c38
FY		 2682
2683 found = identity_mapping(pdev);
2684 if (found) {
6941af28 2685 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2686 return 1;
2687 else {
2688 /*
2689 * 32 bit DMA is removed from si_domain and fall back
2690 * to non-identity mapping.
2691 */
2692 domain_remove_one_dev_info(si_domain, pdev);
2693 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2694 pci_name(pdev));
2695 return 0;
2696 }
2697 } else {
2698 /*
2699 * In case of a detached 64 bit DMA device from vm, the device
2700 * is put into si_domain for identity mapping.
2701 */
6941af28 2702 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2703 int ret;
5fe60f4e
DW		 2704 ret = domain_add_dev_info(si_domain, pdev,
2705 hw_pass_through ?
2706 CONTEXT_TT_PASS_THROUGH :
2707 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2708 if (!ret) {
2709 printk(KERN_INFO "64bit %s uses identity mapping\n",
2710 pci_name(pdev));
2711 return 1;
2712 }
2713 }
2714 }
2715
1e4c64c4 2716 return 0;
2c2e2c38
FY		 2717}
2718
bb9e6d65
FT		 2719static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2720 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2721{
2722 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2723 struct dmar_domain *domain;
5b6985ce 2724 phys_addr_t start_paddr;
f76aec76
KA		 2725 struct iova *iova;
2726 int prot = 0;
6865f0d1 2727 int ret;
8c11e798 2728 struct intel_iommu *iommu;
33041ec0 2729 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2730
2731 BUG_ON(dir == DMA_NONE);
2c2e2c38 2732
73676832 2733 if (iommu_no_mapping(hwdev))
6865f0d1 2734 return paddr;
f76aec76
KA		 2735
2736 domain = get_valid_domain_for_dev(pdev);
2737 if (!domain)
2738 return 0;
2739
8c11e798 2740 iommu = domain_get_iommu(domain);
88cb6a74 2741 size = aligned_nrpages(paddr, size);
f76aec76 2742
c681d0ba 2743 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2744 if (!iova)
2745 goto error;
2746
ba395927
KA		 2747 /*
2748 * Check if DMAR supports zero-length reads on write only
2749 * mappings..
2750 */
2751 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2752 !cap_zlr(iommu->cap))
ba395927
KA		 2753 prot |= DMA_PTE_READ;
2754 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2755 prot |= DMA_PTE_WRITE;
2756 /*
6865f0d1 2757 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2758 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2759 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2760 * is not a big problem
2761 */
0ab36de2 2762 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2763 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2764 if (ret)
2765 goto error;
2766
1f0ef2aa
DW		 2767 /* it's a non-present to present mapping. Only flush if caching mode */
2768 if (cap_caching_mode(iommu->cap))
82653633 2769 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
1f0ef2aa 2770 else
8c11e798 2771 iommu_flush_write_buffer(iommu);
f76aec76 2772
03d6a246
DW		 2773 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2774 start_paddr += paddr & ~PAGE_MASK;
2775 return start_paddr;
ba395927 2776
ba395927 2777error:
f76aec76
KA		 2778 if (iova)
2779 __free_iova(&domain->iovad, iova);
4cf2e75d 2780 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2781 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2782 return 0;
2783}
2784
ffbbef5c
FT		 2785static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2786 unsigned long offset, size_t size,
2787 enum dma_data_direction dir,
2788 struct dma_attrs *attrs)
bb9e6d65 2789{
ffbbef5c
FT		 2790 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2791 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2792}
2793
5e0d2a6f 2794static void flush_unmaps(void)
2795{
80b20dd8 2796 int i, j;
5e0d2a6f 2797
5e0d2a6f 2798 timer_on = 0;
2799
2800 /* just flush them all */
2801 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2802 struct intel_iommu *iommu = g_iommus[i];
2803 if (!iommu)
2804 continue;
c42d9f32 2805
9dd2fe89
YZ		 2806 if (!deferred_flush[i].next)
2807 continue;
2808
78d5f0f5
NA		 2809 /* In caching mode, global flushes turn emulation expensive */
2810 if (!cap_caching_mode(iommu->cap))
2811 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2812 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2813 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2814 unsigned long mask;
2815 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 2816 struct dmar_domain *domain = deferred_flush[i].domain[j];
2817
2818 /* On real hardware multiple invalidations are expensive */
2819 if (cap_caching_mode(iommu->cap))
2820 iommu_flush_iotlb_psi(iommu, domain->id,
2821 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
2822 else {
2823 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
2824 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2825 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
2826 }
93a23a72 2827 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2828 }
9dd2fe89 2829 deferred_flush[i].next = 0;
5e0d2a6f 2830 }
2831
5e0d2a6f 2832 list_size = 0;
5e0d2a6f 2833}
2834
2835static void flush_unmaps_timeout(unsigned long data)
2836{
80b20dd8 2837 unsigned long flags;
2838
2839 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2840 flush_unmaps();
80b20dd8 2841 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2842}
2843
2844static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2845{
2846 unsigned long flags;
80b20dd8 2847 int next, iommu_id;
8c11e798 2848 struct intel_iommu *iommu;
5e0d2a6f 2849
2850 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2851 if (list_size == HIGH_WATER_MARK)
2852 flush_unmaps();
2853
8c11e798
WH		 2854 iommu = domain_get_iommu(dom);
2855 iommu_id = iommu->seq_id;
c42d9f32 2856
80b20dd8 2857 next = deferred_flush[iommu_id].next;
2858 deferred_flush[iommu_id].domain[next] = dom;
2859 deferred_flush[iommu_id].iova[next] = iova;
2860 deferred_flush[iommu_id].next++;
5e0d2a6f 2861
2862 if (!timer_on) {
2863 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2864 timer_on = 1;
2865 }
2866 list_size++;
2867 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2868}
2869
ffbbef5c
FT		 2870static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2871 size_t size, enum dma_data_direction dir,
2872 struct dma_attrs *attrs)
ba395927 2873{
ba395927 2874 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2875 struct dmar_domain *domain;
d794dc9b 2876 unsigned long start_pfn, last_pfn;
ba395927 2877 struct iova *iova;
8c11e798 2878 struct intel_iommu *iommu;
ba395927 2879
73676832 2880 if (iommu_no_mapping(dev))
f76aec76 2881 return;
2c2e2c38 2882
ba395927
KA		 2883 domain = find_domain(pdev);
2884 BUG_ON(!domain);
2885
8c11e798
WH		 2886 iommu = domain_get_iommu(domain);
2887
ba395927 2888 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2889 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2890 (unsigned long long)dev_addr))
ba395927 2891 return;
ba395927 2892
d794dc9b
DW		 2893 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2894 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2895
d794dc9b
DW		 2896 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2897 pci_name(pdev), start_pfn, last_pfn);
ba395927 2898
f76aec76 2899 /* clear the whole page */
d794dc9b
DW		 2900 dma_pte_clear_range(domain, start_pfn, last_pfn);
2901
f76aec76 2902 /* free page tables */
d794dc9b
DW		 2903 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2904
5e0d2a6f 2905 if (intel_iommu_strict) {
03d6a246 2906 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 2907 last_pfn - start_pfn + 1, 0);
5e0d2a6f 2908 /* free iova */
2909 __free_iova(&domain->iovad, iova);
2910 } else {
2911 add_unmap(domain, iova);
2912 /*
2913 * queue up the release of the unmap to save the 1/6th of the
2914 * cpu used up by the iotlb flush operation...
2915 */
5e0d2a6f 2916 }
ba395927
KA		 2917}
2918
d7ab5c46
FT		 2919static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2920 dma_addr_t *dma_handle, gfp_t flags)
ba395927
KA		 2921{
2922 void *vaddr;
2923 int order;
2924
5b6985ce 2925 size = PAGE_ALIGN(size);
ba395927 2926 order = get_order(size);
e8bb910d
AW		 2927
2928 if (!iommu_no_mapping(hwdev))
2929 flags &= ~(GFP_DMA | GFP_DMA32);
2930 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
2931 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
2932 flags |= GFP_DMA;
2933 else
2934 flags |= GFP_DMA32;
2935 }
ba395927
KA		 2936
2937 vaddr = (void *)__get_free_pages(flags, order);
2938 if (!vaddr)
2939 return NULL;
2940 memset(vaddr, 0, size);
2941
bb9e6d65
FT		 2942 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2943 DMA_BIDIRECTIONAL,
2944 hwdev->coherent_dma_mask);
ba395927
KA		 2945 if (*dma_handle)
2946 return vaddr;
2947 free_pages((unsigned long)vaddr, order);
2948 return NULL;
2949}
2950
d7ab5c46
FT		 2951static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2952 dma_addr_t dma_handle)
ba395927
KA		 2953{
2954 int order;
2955
5b6985ce 2956 size = PAGE_ALIGN(size);
ba395927
KA		 2957 order = get_order(size);
2958
0db9b7ae 2959 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 2960 free_pages((unsigned long)vaddr, order);
2961}
2962
d7ab5c46
FT		 2963static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2964 int nelems, enum dma_data_direction dir,
2965 struct dma_attrs *attrs)
ba395927 2966{
ba395927
KA		 2967 struct pci_dev *pdev = to_pci_dev(hwdev);
2968 struct dmar_domain *domain;
d794dc9b 2969 unsigned long start_pfn, last_pfn;
f76aec76 2970 struct iova *iova;
8c11e798 2971 struct intel_iommu *iommu;
ba395927 2972
73676832 2973 if (iommu_no_mapping(hwdev))
ba395927
KA		 2974 return;
2975
2976 domain = find_domain(pdev);
8c11e798
WH		 2977 BUG_ON(!domain);
2978
2979 iommu = domain_get_iommu(domain);
ba395927 2980
c03ab37c 2981 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 2982 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2983 (unsigned long long)sglist[0].dma_address))
f76aec76 2984 return;
f76aec76 2985
d794dc9b
DW		 2986 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2987 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 2988
2989 /* clear the whole page */
d794dc9b
DW		 2990 dma_pte_clear_range(domain, start_pfn, last_pfn);
2991
f76aec76 2992 /* free page tables */
d794dc9b 2993 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 2994
acea0018
DW		 2995 if (intel_iommu_strict) {
2996 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 2997 last_pfn - start_pfn + 1, 0);
acea0018
DW		 2998 /* free iova */
2999 __free_iova(&domain->iovad, iova);
3000 } else {
3001 add_unmap(domain, iova);
3002 /*
3003 * queue up the release of the unmap to save the 1/6th of the
3004 * cpu used up by the iotlb flush operation...
3005 */
3006 }
ba395927
KA		 3007}
3008
ba395927 3009static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3010 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3011{
3012 int i;
c03ab37c 3013 struct scatterlist *sg;
ba395927 3014
c03ab37c 3015 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3016 BUG_ON(!sg_page(sg));
4cf2e75d 3017 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3018 sg->dma_length = sg->length;
ba395927
KA		 3019 }
3020 return nelems;
3021}
3022
d7ab5c46
FT		 3023static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3024 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3025{
ba395927 3026 int i;
ba395927
KA		 3027 struct pci_dev *pdev = to_pci_dev(hwdev);
3028 struct dmar_domain *domain;
f76aec76
KA		 3029 size_t size = 0;
3030 int prot = 0;
f76aec76
KA		 3031 struct iova *iova = NULL;
3032 int ret;
c03ab37c 3033 struct scatterlist *sg;
b536d24d 3034 unsigned long start_vpfn;
8c11e798 3035 struct intel_iommu *iommu;
ba395927
KA		 3036
3037 BUG_ON(dir == DMA_NONE);
73676832 3038 if (iommu_no_mapping(hwdev))
c03ab37c 3039 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3040
f76aec76
KA		 3041 domain = get_valid_domain_for_dev(pdev);
3042 if (!domain)
3043 return 0;
3044
8c11e798
WH		 3045 iommu = domain_get_iommu(domain);
3046
b536d24d 3047 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3048 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3049
5a5e02a6
DW		 3050 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3051 pdev->dma_mask);
f76aec76 3052 if (!iova) {
c03ab37c 3053 sglist->dma_length = 0;
f76aec76
KA		 3054 return 0;
3055 }
3056
3057 /*
3058 * Check if DMAR supports zero-length reads on write only
3059 * mappings..
3060 */
3061 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3062 !cap_zlr(iommu->cap))
f76aec76
KA		 3063 prot |= DMA_PTE_READ;
3064 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3065 prot |= DMA_PTE_WRITE;
3066
b536d24d 3067 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3068
f532959b 3069 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3070 if (unlikely(ret)) {
3071 /* clear the page */
3072 dma_pte_clear_range(domain, start_vpfn,
3073 start_vpfn + size - 1);
3074 /* free page tables */
3075 dma_pte_free_pagetable(domain, start_vpfn,
3076 start_vpfn + size - 1);
3077 /* free iova */
3078 __free_iova(&domain->iovad, iova);
3079 return 0;
ba395927
KA		 3080 }
3081
1f0ef2aa
DW		 3082 /* it's a non-present to present mapping. Only flush if caching mode */
3083 if (cap_caching_mode(iommu->cap))
82653633 3084 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
1f0ef2aa 3085 else
8c11e798 3086 iommu_flush_write_buffer(iommu);
1f0ef2aa 3087
ba395927
KA		 3088 return nelems;
3089}
3090
dfb805e8
FT		 3091static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3092{
3093 return !dma_addr;
3094}
3095
160c1d8e 3096struct dma_map_ops intel_dma_ops = {
ba395927
KA		 3097 .alloc_coherent = intel_alloc_coherent,
3098 .free_coherent = intel_free_coherent,
ba395927
KA		 3099 .map_sg = intel_map_sg,
3100 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3101 .map_page = intel_map_page,
3102 .unmap_page = intel_unmap_page,
dfb805e8 3103 .mapping_error = intel_mapping_error,
ba395927
KA		 3104};
3105
3106static inline int iommu_domain_cache_init(void)
3107{
3108 int ret = 0;
3109
3110 iommu_domain_cache = kmem_cache_create("iommu_domain",
3111 sizeof(struct dmar_domain),
3112 0,
3113 SLAB_HWCACHE_ALIGN,
3114
3115 NULL);
3116 if (!iommu_domain_cache) {
3117 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3118 ret = -ENOMEM;
3119 }
3120
3121 return ret;
3122}
3123
3124static inline int iommu_devinfo_cache_init(void)
3125{
3126 int ret = 0;
3127
3128 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3129 sizeof(struct device_domain_info),
3130 0,
3131 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3132 NULL);
3133 if (!iommu_devinfo_cache) {
3134 printk(KERN_ERR "Couldn't create devinfo cache\n");
3135 ret = -ENOMEM;
3136 }
3137
3138 return ret;
3139}
3140
3141static inline int iommu_iova_cache_init(void)
3142{
3143 int ret = 0;
3144
3145 iommu_iova_cache = kmem_cache_create("iommu_iova",
3146 sizeof(struct iova),
3147 0,
3148 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3149 NULL);
3150 if (!iommu_iova_cache) {
3151 printk(KERN_ERR "Couldn't create iova cache\n");
3152 ret = -ENOMEM;
3153 }
3154
3155 return ret;
3156}
3157
3158static int __init iommu_init_mempool(void)
3159{
3160 int ret;
3161 ret = iommu_iova_cache_init();
3162 if (ret)
3163 return ret;
3164
3165 ret = iommu_domain_cache_init();
3166 if (ret)
3167 goto domain_error;
3168
3169 ret = iommu_devinfo_cache_init();
3170 if (!ret)
3171 return ret;
3172
3173 kmem_cache_destroy(iommu_domain_cache);
3174domain_error:
3175 kmem_cache_destroy(iommu_iova_cache);
3176
3177 return -ENOMEM;
3178}
3179
3180static void __init iommu_exit_mempool(void)
3181{
3182 kmem_cache_destroy(iommu_devinfo_cache);
3183 kmem_cache_destroy(iommu_domain_cache);
3184 kmem_cache_destroy(iommu_iova_cache);
3185
3186}
3187
556ab45f
DW		 3188static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3189{
3190 struct dmar_drhd_unit *drhd;
3191 u32 vtbar;
3192 int rc;
3193
3194 /* We know that this device on this chipset has its own IOMMU.
3195 * If we find it under a different IOMMU, then the BIOS is lying
3196 * to us. Hope that the IOMMU for this device is actually
3197 * disabled, and it needs no translation...
3198 */
3199 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3200 if (rc) {
3201 /* "can't" happen */
3202 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3203 return;
3204 }
3205 vtbar &= 0xffff0000;
3206
3207 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3208 drhd = dmar_find_matched_drhd_unit(pdev);
3209 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3210 TAINT_FIRMWARE_WORKAROUND,
3211 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3212 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3213}
3214DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3215
ba395927
KA		 3216static void __init init_no_remapping_devices(void)
3217{
3218 struct dmar_drhd_unit *drhd;
3219
3220 for_each_drhd_unit(drhd) {
3221 if (!drhd->include_all) {
3222 int i;
3223 for (i = 0; i < drhd->devices_cnt; i++)
3224 if (drhd->devices[i] != NULL)
3225 break;
3226 /* ignore DMAR unit if no pci devices exist */
3227 if (i == drhd->devices_cnt)
3228 drhd->ignored = 1;
3229 }
3230 }
3231
ba395927
KA		 3232 for_each_drhd_unit(drhd) {
3233 int i;
3234 if (drhd->ignored || drhd->include_all)
3235 continue;
3236
3237 for (i = 0; i < drhd->devices_cnt; i++)
3238 if (drhd->devices[i] &&
c0771df8 3239 !IS_GFX_DEVICE(drhd->devices[i]))
ba395927
KA		 3240 break;
3241
3242 if (i < drhd->devices_cnt)
3243 continue;
3244
c0771df8
DW		 3245 /* This IOMMU has *only* gfx devices. Either bypass it or
3246 set the gfx_mapped flag, as appropriate */
3247 if (dmar_map_gfx) {
3248 intel_iommu_gfx_mapped = 1;
3249 } else {
3250 drhd->ignored = 1;
3251 for (i = 0; i < drhd->devices_cnt; i++) {
3252 if (!drhd->devices[i])
3253 continue;
3254 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3255 }
ba395927
KA		 3256 }
3257 }
3258}
3259
f59c7b69
FY		 3260#ifdef CONFIG_SUSPEND
3261static int init_iommu_hw(void)
3262{
3263 struct dmar_drhd_unit *drhd;
3264 struct intel_iommu *iommu = NULL;
3265
3266 for_each_active_iommu(iommu, drhd)
3267 if (iommu->qi)
3268 dmar_reenable_qi(iommu);
3269
b779260b
JC		 3270 for_each_iommu(iommu, drhd) {
3271 if (drhd->ignored) {
3272 /*
3273 * we always have to disable PMRs or DMA may fail on
3274 * this device
3275 */
3276 if (force_on)
3277 iommu_disable_protect_mem_regions(iommu);
3278 continue;
3279 }
3280
f59c7b69
FY		 3281 iommu_flush_write_buffer(iommu);
3282
3283 iommu_set_root_entry(iommu);
3284
3285 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3286 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3287 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3288 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3289 if (iommu_enable_translation(iommu))
3290 return 1;
b94996c9 3291 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3292 }
3293
3294 return 0;
3295}
3296
3297static void iommu_flush_all(void)
3298{
3299 struct dmar_drhd_unit *drhd;
3300 struct intel_iommu *iommu;
3301
3302 for_each_active_iommu(iommu, drhd) {
3303 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3304 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3305 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3306 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3307 }
3308}
3309
134fac3f 3310static int iommu_suspend(void)
f59c7b69
FY		 3311{
3312 struct dmar_drhd_unit *drhd;
3313 struct intel_iommu *iommu = NULL;
3314 unsigned long flag;
3315
3316 for_each_active_iommu(iommu, drhd) {
3317 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3318 GFP_ATOMIC);
3319 if (!iommu->iommu_state)
3320 goto nomem;
3321 }
3322
3323 iommu_flush_all();
3324
3325 for_each_active_iommu(iommu, drhd) {
3326 iommu_disable_translation(iommu);
3327
3328 spin_lock_irqsave(&iommu->register_lock, flag);
3329
3330 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3331 readl(iommu->reg + DMAR_FECTL_REG);
3332 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3333 readl(iommu->reg + DMAR_FEDATA_REG);
3334 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3335 readl(iommu->reg + DMAR_FEADDR_REG);
3336 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3337 readl(iommu->reg + DMAR_FEUADDR_REG);
3338
3339 spin_unlock_irqrestore(&iommu->register_lock, flag);
3340 }
3341 return 0;
3342
3343nomem:
3344 for_each_active_iommu(iommu, drhd)
3345 kfree(iommu->iommu_state);
3346
3347 return -ENOMEM;
3348}
3349
134fac3f 3350static void iommu_resume(void)
f59c7b69
FY		 3351{
3352 struct dmar_drhd_unit *drhd;
3353 struct intel_iommu *iommu = NULL;
3354 unsigned long flag;
3355
3356 if (init_iommu_hw()) {
b779260b
JC		 3357 if (force_on)
3358 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3359 else
3360 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3361 return;
f59c7b69
FY		 3362 }
3363
3364 for_each_active_iommu(iommu, drhd) {
3365
3366 spin_lock_irqsave(&iommu->register_lock, flag);
3367
3368 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3369 iommu->reg + DMAR_FECTL_REG);
3370 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3371 iommu->reg + DMAR_FEDATA_REG);
3372 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3373 iommu->reg + DMAR_FEADDR_REG);
3374 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3375 iommu->reg + DMAR_FEUADDR_REG);
3376
3377 spin_unlock_irqrestore(&iommu->register_lock, flag);
3378 }
3379
3380 for_each_active_iommu(iommu, drhd)
3381 kfree(iommu->iommu_state);
f59c7b69
FY		 3382}
3383
134fac3f 3384static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3385 .resume = iommu_resume,
3386 .suspend = iommu_suspend,
3387};
3388
134fac3f 3389static void __init init_iommu_pm_ops(void)
f59c7b69 3390{
134fac3f 3391 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3392}
3393
3394#else
99592ba4 3395static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3396#endif /* CONFIG_PM */
3397
99dcaded
FY		 3398/*
3399 * Here we only respond to action of unbound device from driver.
3400 *
3401 * Added device is not attached to its DMAR domain here yet. That will happen
3402 * when mapping the device to iova.
3403 */
3404static int device_notifier(struct notifier_block *nb,
3405 unsigned long action, void *data)
3406{
3407 struct device *dev = data;
3408 struct pci_dev *pdev = to_pci_dev(dev);
3409 struct dmar_domain *domain;
3410
44cd613c
DW		 3411 if (iommu_no_mapping(dev))
3412 return 0;
3413
99dcaded
FY		 3414 domain = find_domain(pdev);
3415 if (!domain)
3416 return 0;
3417
a97590e5 3418 if (action == BUS_NOTIFY_UNBOUND_DRIVER && !iommu_pass_through) {
99dcaded
FY		 3419 domain_remove_one_dev_info(domain, pdev);
3420
a97590e5
AW		 3421 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3422 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3423 list_empty(&domain->devices))
3424 domain_exit(domain);
3425 }
3426
99dcaded
FY		 3427 return 0;
3428}
3429
3430static struct notifier_block device_nb = {
3431 .notifier_call = device_notifier,
3432};
3433
ba395927
KA		 3434int __init intel_iommu_init(void)
3435{
3436 int ret = 0;
3437
a59b50e9
JC		 3438 /* VT-d is required for a TXT/tboot launch, so enforce that */
3439 force_on = tboot_force_iommu();
3440
3441 if (dmar_table_init()) {
3442 if (force_on)
3443 panic("tboot: Failed to initialize DMAR table\n");
ba395927 3444 return -ENODEV;
a59b50e9 3445 }
ba395927 3446
a59b50e9
JC		 3447 if (dmar_dev_scope_init()) {
3448 if (force_on)
3449 panic("tboot: Failed to initialize DMAR device scope\n");
1886e8a9 3450 return -ENODEV;
a59b50e9 3451 }
1886e8a9 3452
2ae21010
SS		 3453 /*
3454 * Check the need for DMA-remapping initialization now.
3455 * Above initialization will also be used by Interrupt-remapping.
3456 */
75f1cdf1 3457 if (no_iommu || dmar_disabled)
2ae21010
SS		 3458 return -ENODEV;
3459
51a63e67
JC		 3460 if (iommu_init_mempool()) {
3461 if (force_on)
3462 panic("tboot: Failed to initialize iommu memory\n");
3463 return -ENODEV;
3464 }
3465
3466 if (dmar_init_reserved_ranges()) {
3467 if (force_on)
3468 panic("tboot: Failed to reserve iommu ranges\n");
3469 return -ENODEV;
3470 }
ba395927
KA		 3471
3472 init_no_remapping_devices();
3473
b779260b 3474 ret = init_dmars();
ba395927 3475 if (ret) {
a59b50e9
JC		 3476 if (force_on)
3477 panic("tboot: Failed to initialize DMARs\n");
ba395927
KA		 3478 printk(KERN_ERR "IOMMU: dmar init failed\n");
3479 put_iova_domain(&reserved_iova_list);
3480 iommu_exit_mempool();
3481 return ret;
3482 }
3483 printk(KERN_INFO
3484 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3485
5e0d2a6f 3486 init_timer(&unmap_timer);
75f1cdf1
FT		 3487#ifdef CONFIG_SWIOTLB
3488 swiotlb = 0;
3489#endif
19943b0e 3490 dma_ops = &intel_dma_ops;
4ed0d3e6 3491
134fac3f 3492 init_iommu_pm_ops();
a8bcbb0d
JR		 3493
3494 register_iommu(&intel_iommu_ops);
3495
99dcaded
FY		 3496 bus_register_notifier(&pci_bus_type, &device_nb);
3497
ba395927
KA		 3498 return 0;
3499}
e820482c 3500
3199aa6b
HW		 3501static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3502 struct pci_dev *pdev)
3503{
3504 struct pci_dev *tmp, *parent;
3505
3506 if (!iommu || !pdev)
3507 return;
3508
3509 /* dependent device detach */
3510 tmp = pci_find_upstream_pcie_bridge(pdev);
3511 /* Secondary interface's bus number and devfn 0 */
3512 if (tmp) {
3513 parent = pdev->bus->self;
3514 while (parent != tmp) {
3515 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3516 parent->devfn);
3199aa6b
HW		 3517 parent = parent->bus->self;
3518 }
45e829ea 3519 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 3520 iommu_detach_dev(iommu,
3521 tmp->subordinate->number, 0);
3522 else /* this is a legacy PCI bridge */
276dbf99
DW		 3523 iommu_detach_dev(iommu, tmp->bus->number,
3524 tmp->devfn);
3199aa6b
HW		 3525 }
3526}
3527
2c2e2c38 3528static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3529 struct pci_dev *pdev)
3530{
3531 struct device_domain_info *info;
3532 struct intel_iommu *iommu;
3533 unsigned long flags;
3534 int found = 0;
3535 struct list_head *entry, *tmp;
3536
276dbf99
DW		 3537 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3538 pdev->devfn);
c7151a8d
WH		 3539 if (!iommu)
3540 return;
3541
3542 spin_lock_irqsave(&device_domain_lock, flags);
3543 list_for_each_safe(entry, tmp, &domain->devices) {
3544 info = list_entry(entry, struct device_domain_info, link);
8519dc44
MH		 3545 if (info->segment == pci_domain_nr(pdev->bus) &&
3546 info->bus == pdev->bus->number &&
c7151a8d
WH		 3547 info->devfn == pdev->devfn) {
3548 list_del(&info->link);
3549 list_del(&info->global);
3550 if (info->dev)
3551 info->dev->dev.archdata.iommu = NULL;
3552 spin_unlock_irqrestore(&device_domain_lock, flags);
3553
93a23a72 3554 iommu_disable_dev_iotlb(info);
c7151a8d 3555 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3556 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3557 free_devinfo_mem(info);
3558
3559 spin_lock_irqsave(&device_domain_lock, flags);
3560
3561 if (found)
3562 break;
3563 else
3564 continue;
3565 }
3566
3567 /* if there is no other devices under the same iommu
3568 * owned by this domain, clear this iommu in iommu_bmp
3569 * update iommu count and coherency
3570 */
276dbf99
DW		 3571 if (iommu == device_to_iommu(info->segment, info->bus,
3572 info->devfn))
c7151a8d
WH		 3573 found = 1;
3574 }
3575
3e7abe25
RD		 3576 spin_unlock_irqrestore(&device_domain_lock, flags);
3577
c7151a8d
WH		 3578 if (found == 0) {
3579 unsigned long tmp_flags;
3580 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3581 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3582 domain->iommu_count--;
58c610bd 3583 domain_update_iommu_cap(domain);
c7151a8d 3584 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 3585
9b4554b2
AW		 3586 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3587 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
3588 spin_lock_irqsave(&iommu->lock, tmp_flags);
3589 clear_bit(domain->id, iommu->domain_ids);
3590 iommu->domains[domain->id] = NULL;
3591 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
3592 }
c7151a8d 3593 }
c7151a8d
WH		 3594}
3595
3596static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3597{
3598 struct device_domain_info *info;
3599 struct intel_iommu *iommu;
3600 unsigned long flags1, flags2;
3601
3602 spin_lock_irqsave(&device_domain_lock, flags1);
3603 while (!list_empty(&domain->devices)) {
3604 info = list_entry(domain->devices.next,
3605 struct device_domain_info, link);
3606 list_del(&info->link);
3607 list_del(&info->global);
3608 if (info->dev)
3609 info->dev->dev.archdata.iommu = NULL;
3610
3611 spin_unlock_irqrestore(&device_domain_lock, flags1);
3612
93a23a72 3613 iommu_disable_dev_iotlb(info);
276dbf99 3614 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3615 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3616 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3617
3618 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3619 * and capabilities
c7151a8d
WH		 3620 */
3621 spin_lock_irqsave(&domain->iommu_lock, flags2);
3622 if (test_and_clear_bit(iommu->seq_id,
3623 &domain->iommu_bmp)) {
3624 domain->iommu_count--;
58c610bd 3625 domain_update_iommu_cap(domain);
c7151a8d
WH		 3626 }
3627 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3628
3629 free_devinfo_mem(info);
3630 spin_lock_irqsave(&device_domain_lock, flags1);
3631 }
3632 spin_unlock_irqrestore(&device_domain_lock, flags1);
3633}
3634
5e98c4b1
WH		 3635/* domain id for virtual machine, it won't be set in context */
3636static unsigned long vm_domid;
3637
3638static struct dmar_domain *iommu_alloc_vm_domain(void)
3639{
3640 struct dmar_domain *domain;
3641
3642 domain = alloc_domain_mem();
3643 if (!domain)
3644 return NULL;
3645
3646 domain->id = vm_domid++;
4c923d47 3647 domain->nid = -1;
5e98c4b1
WH		 3648 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3649 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3650
3651 return domain;
3652}
3653
2c2e2c38 3654static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3655{
3656 int adjust_width;
3657
3658 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3659 spin_lock_init(&domain->iommu_lock);
3660
3661 domain_reserve_special_ranges(domain);
3662
3663 /* calculate AGAW */
3664 domain->gaw = guest_width;
3665 adjust_width = guestwidth_to_adjustwidth(guest_width);
3666 domain->agaw = width_to_agaw(adjust_width);
3667
3668 INIT_LIST_HEAD(&domain->devices);
3669
3670 domain->iommu_count = 0;
3671 domain->iommu_coherency = 0;
c5b15255 3672 domain->iommu_snooping = 0;
6dd9a7c7 3673 domain->iommu_superpage = 0;
fe40f1e0 3674 domain->max_addr = 0;
4c923d47 3675 domain->nid = -1;
5e98c4b1
WH		 3676
3677 /* always allocate the top pgd */
4c923d47 3678 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 3679 if (!domain->pgd)
3680 return -ENOMEM;
3681 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3682 return 0;
3683}
3684
3685static void iommu_free_vm_domain(struct dmar_domain *domain)
3686{
3687 unsigned long flags;
3688 struct dmar_drhd_unit *drhd;
3689 struct intel_iommu *iommu;
3690 unsigned long i;
3691 unsigned long ndomains;
3692
3693 for_each_drhd_unit(drhd) {
3694 if (drhd->ignored)
3695 continue;
3696 iommu = drhd->iommu;
3697
3698 ndomains = cap_ndoms(iommu->cap);
a45946ab 3699 for_each_set_bit(i, iommu->domain_ids, ndomains) {
5e98c4b1
WH		 3700 if (iommu->domains[i] == domain) {
3701 spin_lock_irqsave(&iommu->lock, flags);
3702 clear_bit(i, iommu->domain_ids);
3703 iommu->domains[i] = NULL;
3704 spin_unlock_irqrestore(&iommu->lock, flags);
3705 break;
3706 }
5e98c4b1
WH		 3707 }
3708 }
3709}
3710
3711static void vm_domain_exit(struct dmar_domain *domain)
3712{
5e98c4b1
WH		 3713 /* Domain 0 is reserved, so dont process it */
3714 if (!domain)
3715 return;
3716
3717 vm_domain_remove_all_dev_info(domain);
3718 /* destroy iovas */
3719 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3720
3721 /* clear ptes */
595badf5 3722 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3723
3724 /* free page tables */
d794dc9b 3725 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3726
3727 iommu_free_vm_domain(domain);
3728 free_domain_mem(domain);
3729}
3730
5d450806 3731static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3732{
5d450806 3733 struct dmar_domain *dmar_domain;
38717946 3734
5d450806
JR		 3735 dmar_domain = iommu_alloc_vm_domain();
3736 if (!dmar_domain) {
38717946 3737 printk(KERN_ERR
5d450806
JR		 3738 "intel_iommu_domain_init: dmar_domain == NULL\n");
3739 return -ENOMEM;
38717946 3740 }
2c2e2c38 3741 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3742 printk(KERN_ERR
5d450806
JR		 3743 "intel_iommu_domain_init() failed\n");
3744 vm_domain_exit(dmar_domain);
3745 return -ENOMEM;
38717946 3746 }
5d450806 3747 domain->priv = dmar_domain;
faa3d6f5 3748
5d450806 3749 return 0;
38717946 3750}
38717946 3751
5d450806 3752static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3753{
5d450806
JR		 3754 struct dmar_domain *dmar_domain = domain->priv;
3755
3756 domain->priv = NULL;
3757 vm_domain_exit(dmar_domain);
38717946 3758}
38717946 3759
4c5478c9
JR		 3760static int intel_iommu_attach_device(struct iommu_domain *domain,
3761 struct device *dev)
38717946 3762{
4c5478c9
JR		 3763 struct dmar_domain *dmar_domain = domain->priv;
3764 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3765 struct intel_iommu *iommu;
3766 int addr_width;
faa3d6f5
WH		 3767
3768 /* normally pdev is not mapped */
3769 if (unlikely(domain_context_mapped(pdev))) {
3770 struct dmar_domain *old_domain;
3771
3772 old_domain = find_domain(pdev);
3773 if (old_domain) {
2c2e2c38
FY		 3774 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3775 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3776 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 3777 else
3778 domain_remove_dev_info(old_domain);
3779 }
3780 }
3781
276dbf99
DW		 3782 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3783 pdev->devfn);
fe40f1e0
WH		 3784 if (!iommu)
3785 return -ENODEV;
3786
3787 /* check if this iommu agaw is sufficient for max mapped address */
3788 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 3789 if (addr_width > cap_mgaw(iommu->cap))
3790 addr_width = cap_mgaw(iommu->cap);
3791
3792 if (dmar_domain->max_addr > (1LL << addr_width)) {
3793 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 3794 "sufficient for the mapped address (%llx)\n",
a99c47a2 3795 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 3796 return -EFAULT;
3797 }
a99c47a2
TL		 3798 dmar_domain->gaw = addr_width;
3799
3800 /*
3801 * Knock out extra levels of page tables if necessary
3802 */
3803 while (iommu->agaw < dmar_domain->agaw) {
3804 struct dma_pte *pte;
3805
3806 pte = dmar_domain->pgd;
3807 if (dma_pte_present(pte)) {
25cbff16
SY		 3808 dmar_domain->pgd = (struct dma_pte *)
3809 phys_to_virt(dma_pte_addr(pte));
7a661013 3810 free_pgtable_page(pte);
a99c47a2
TL		 3811 }
3812 dmar_domain->agaw--;
3813 }
fe40f1e0 3814
5fe60f4e 3815 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 3816}
38717946 3817
4c5478c9
JR		 3818static void intel_iommu_detach_device(struct iommu_domain *domain,
3819 struct device *dev)
38717946 3820{
4c5478c9
JR		 3821 struct dmar_domain *dmar_domain = domain->priv;
3822 struct pci_dev *pdev = to_pci_dev(dev);
3823
2c2e2c38 3824 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 3825}
c7151a8d 3826
b146a1c9
JR		 3827static int intel_iommu_map(struct iommu_domain *domain,
3828 unsigned long iova, phys_addr_t hpa,
3829 int gfp_order, int iommu_prot)
faa3d6f5 3830{
dde57a21 3831 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 3832 u64 max_addr;
dde57a21 3833 int prot = 0;
b146a1c9 3834 size_t size;
faa3d6f5 3835 int ret;
fe40f1e0 3836
dde57a21
JR		 3837 if (iommu_prot & IOMMU_READ)
3838 prot |= DMA_PTE_READ;
3839 if (iommu_prot & IOMMU_WRITE)
3840 prot |= DMA_PTE_WRITE;
9cf06697
SY		 3841 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3842 prot |= DMA_PTE_SNP;
dde57a21 3843
b146a1c9 3844 size = PAGE_SIZE << gfp_order;
163cc52c 3845 max_addr = iova + size;
dde57a21 3846 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 3847 u64 end;
3848
3849 /* check if minimum agaw is sufficient for mapped address */
8954da1f 3850 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 3851 if (end < max_addr) {
8954da1f 3852 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 3853 "sufficient for the mapped address (%llx)\n",
8954da1f 3854 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 3855 return -EFAULT;
3856 }
dde57a21 3857 dmar_domain->max_addr = max_addr;
fe40f1e0 3858 }
ad051221
DW		 3859 /* Round up size to next multiple of PAGE_SIZE, if it and
3860 the low bits of hpa would take us onto the next page */
88cb6a74 3861 size = aligned_nrpages(hpa, size);
ad051221
DW		 3862 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3863 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 3864 return ret;
38717946 3865}
38717946 3866
b146a1c9
JR		 3867static int intel_iommu_unmap(struct iommu_domain *domain,
3868 unsigned long iova, int gfp_order)
38717946 3869{
dde57a21 3870 struct dmar_domain *dmar_domain = domain->priv;
b146a1c9 3871 size_t size = PAGE_SIZE << gfp_order;
4b99d352 3872
163cc52c
DW		 3873 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3874 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 3875
163cc52c
DW		 3876 if (dmar_domain->max_addr == iova + size)
3877 dmar_domain->max_addr = iova;
b146a1c9
JR		 3878
3879 return gfp_order;
38717946 3880}
38717946 3881
d14d6577
JR		 3882static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3883 unsigned long iova)
38717946 3884{
d14d6577 3885 struct dmar_domain *dmar_domain = domain->priv;
38717946 3886 struct dma_pte *pte;
faa3d6f5 3887 u64 phys = 0;
38717946 3888
6dd9a7c7 3889 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
38717946 3890 if (pte)
faa3d6f5 3891 phys = dma_pte_addr(pte);
38717946 3892
faa3d6f5 3893 return phys;
38717946 3894}
a8bcbb0d 3895
dbb9fd86
SY		 3896static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3897 unsigned long cap)
3898{
3899 struct dmar_domain *dmar_domain = domain->priv;
3900
3901 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3902 return dmar_domain->iommu_snooping;
323f99cb
TL		 3903 if (cap == IOMMU_CAP_INTR_REMAP)
3904 return intr_remapping_enabled;
dbb9fd86
SY		 3905
3906 return 0;
3907}
3908
a8bcbb0d
JR		 3909static struct iommu_ops intel_iommu_ops = {
3910 .domain_init = intel_iommu_domain_init,
3911 .domain_destroy = intel_iommu_domain_destroy,
3912 .attach_dev = intel_iommu_attach_device,
3913 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 3914 .map = intel_iommu_map,
3915 .unmap = intel_iommu_unmap,
a8bcbb0d 3916 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 3917 .domain_has_cap = intel_iommu_domain_has_cap,
a8bcbb0d 3918};
9af88143
DW		 3919
3920static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3921{
3922 /*
3923 * Mobile 4 Series Chipset neglects to set RWBF capability,
3924 * but needs it:
3925 */
3926 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3927 rwbf_quirk = 1;
2d9e667e
DW		 3928
3929 /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
3930 if (dev->revision == 0x07) {
3931 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
3932 dmar_map_gfx = 0;
3933 }
9af88143
DW		 3934}
3935
3936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
e0fc7e0b 3937
eecfd57f
AJ		 3938#define GGC 0x52
3939#define GGC_MEMORY_SIZE_MASK (0xf << 8)
3940#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
3941#define GGC_MEMORY_SIZE_1M (0x1 << 8)
3942#define GGC_MEMORY_SIZE_2M (0x3 << 8)
3943#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
3944#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
3945#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
3946#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
3947
9eecabcb
DW		 3948static void __devinit quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
3949{
3950 unsigned short ggc;
3951
eecfd57f 3952 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 3953 return;
3954
eecfd57f 3955 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 3956 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
3957 dmar_map_gfx = 0;
6fbcfb3e
DW		 3958 } else if (dmar_map_gfx) {
3959 /* we have to ensure the gfx device is idle before we flush */
3960 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
3961 intel_iommu_strict = 1;
3962 }
9eecabcb
DW		 3963}
3964DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
3965DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
3966DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
3967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
3968
e0fc7e0b
DW		 3969/* On Tylersburg chipsets, some BIOSes have been known to enable the
3970 ISOCH DMAR unit for the Azalia sound device, but not give it any
3971 TLB entries, which causes it to deadlock. Check for that. We do
3972 this in a function called from init_dmars(), instead of in a PCI
3973 quirk, because we don't want to print the obnoxious "BIOS broken"
3974 message if VT-d is actually disabled.
3975*/
3976static void __init check_tylersburg_isoch(void)
3977{
3978 struct pci_dev *pdev;
3979 uint32_t vtisochctrl;
3980
3981 /* If there's no Azalia in the system anyway, forget it. */
3982 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
3983 if (!pdev)
3984 return;
3985 pci_dev_put(pdev);
3986
3987 /* System Management Registers. Might be hidden, in which case
3988 we can't do the sanity check. But that's OK, because the
3989 known-broken BIOSes _don't_ actually hide it, so far. */
3990 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
3991 if (!pdev)
3992 return;
3993
3994 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
3995 pci_dev_put(pdev);
3996 return;
3997 }
3998
3999 pci_dev_put(pdev);
4000
4001 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4002 if (vtisochctrl & 1)
4003 return;
4004
4005 /* Drop all bits other than the number of TLB entries */
4006 vtisochctrl &= 0x1c;
4007
4008 /* If we have the recommended number of TLB entries (16), fine. */
4009 if (vtisochctrl == 0x10)
4010 return;
4011
4012 /* Zero TLB entries? You get to ride the short bus to school. */
4013 if (!vtisochctrl) {
4014 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4015 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4016 dmi_get_system_info(DMI_BIOS_VENDOR),
4017 dmi_get_system_info(DMI_BIOS_VERSION),
4018 dmi_get_system_info(DMI_PRODUCT_VERSION));
4019 iommu_identity_mapping |= IDENTMAP_AZALIA;
4020 return;
4021 }
4022
4023 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4024 vtisochctrl);
4025}
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