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ba395927 | 1 | /* |
ea8ea460 | 2 | * Copyright © 2006-2014 Intel Corporation. |
ba395927 KA |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
ea8ea460 DW |
13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
14 | * Ashok Raj <ashok.raj@intel.com>, | |
15 | * Shaohua Li <shaohua.li@intel.com>, | |
16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, | |
17 | * Fenghua Yu <fenghua.yu@intel.com> | |
9f10e5bf | 18 | * Joerg Roedel <jroedel@suse.de> |
ba395927 KA |
19 | */ |
20 | ||
9f10e5bf JR |
21 | #define pr_fmt(fmt) "DMAR: " fmt |
22 | ||
ba395927 KA |
23 | #include <linux/init.h> |
24 | #include <linux/bitmap.h> | |
5e0d2a6f | 25 | #include <linux/debugfs.h> |
54485c30 | 26 | #include <linux/export.h> |
ba395927 KA |
27 | #include <linux/slab.h> |
28 | #include <linux/irq.h> | |
29 | #include <linux/interrupt.h> | |
ba395927 KA |
30 | #include <linux/spinlock.h> |
31 | #include <linux/pci.h> | |
32 | #include <linux/dmar.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/mempool.h> | |
75f05569 | 35 | #include <linux/memory.h> |
5e0d2a6f | 36 | #include <linux/timer.h> |
38717946 | 37 | #include <linux/iova.h> |
5d450806 | 38 | #include <linux/iommu.h> |
38717946 | 39 | #include <linux/intel-iommu.h> |
134fac3f | 40 | #include <linux/syscore_ops.h> |
69575d38 | 41 | #include <linux/tboot.h> |
adb2fe02 | 42 | #include <linux/dmi.h> |
5cdede24 | 43 | #include <linux/pci-ats.h> |
0ee332c1 | 44 | #include <linux/memblock.h> |
36746436 | 45 | #include <linux/dma-contiguous.h> |
091d42e4 | 46 | #include <linux/crash_dump.h> |
8a8f422d | 47 | #include <asm/irq_remapping.h> |
ba395927 | 48 | #include <asm/cacheflush.h> |
46a7fa27 | 49 | #include <asm/iommu.h> |
ba395927 | 50 | |
078e1ee2 JR |
51 | #include "irq_remapping.h" |
52 | ||
5b6985ce FY |
53 | #define ROOT_SIZE VTD_PAGE_SIZE |
54 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
55 | ||
ba395927 | 56 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
18436afd | 57 | #define IS_USB_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) |
ba395927 | 58 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
e0fc7e0b | 59 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
ba395927 KA |
60 | |
61 | #define IOAPIC_RANGE_START (0xfee00000) | |
62 | #define IOAPIC_RANGE_END (0xfeefffff) | |
63 | #define IOVA_START_ADDR (0x1000) | |
64 | ||
65 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
66 | ||
4ed0d3e6 | 67 | #define MAX_AGAW_WIDTH 64 |
5c645b35 | 68 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
4ed0d3e6 | 69 | |
2ebe3151 DW |
70 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
71 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) | |
72 | ||
73 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR | |
74 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ | |
75 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ | |
76 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) | |
77 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) | |
ba395927 | 78 | |
1b722500 RM |
79 | /* IO virtual address start page frame number */ |
80 | #define IOVA_START_PFN (1) | |
81 | ||
f27be03b | 82 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 83 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 84 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 85 | |
df08cdc7 AM |
86 | /* page table handling */ |
87 | #define LEVEL_STRIDE (9) | |
88 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
89 | ||
6d1c56a9 OBC |
90 | /* |
91 | * This bitmap is used to advertise the page sizes our hardware support | |
92 | * to the IOMMU core, which will then use this information to split | |
93 | * physically contiguous memory regions it is mapping into page sizes | |
94 | * that we support. | |
95 | * | |
96 | * Traditionally the IOMMU core just handed us the mappings directly, | |
97 | * after making sure the size is an order of a 4KiB page and that the | |
98 | * mapping has natural alignment. | |
99 | * | |
100 | * To retain this behavior, we currently advertise that we support | |
101 | * all page sizes that are an order of 4KiB. | |
102 | * | |
103 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
104 | * we could change this to advertise the real page sizes we support. | |
105 | */ | |
106 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) | |
107 | ||
df08cdc7 AM |
108 | static inline int agaw_to_level(int agaw) |
109 | { | |
110 | return agaw + 2; | |
111 | } | |
112 | ||
113 | static inline int agaw_to_width(int agaw) | |
114 | { | |
5c645b35 | 115 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
df08cdc7 AM |
116 | } |
117 | ||
118 | static inline int width_to_agaw(int width) | |
119 | { | |
5c645b35 | 120 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
df08cdc7 AM |
121 | } |
122 | ||
123 | static inline unsigned int level_to_offset_bits(int level) | |
124 | { | |
125 | return (level - 1) * LEVEL_STRIDE; | |
126 | } | |
127 | ||
128 | static inline int pfn_level_offset(unsigned long pfn, int level) | |
129 | { | |
130 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; | |
131 | } | |
132 | ||
133 | static inline unsigned long level_mask(int level) | |
134 | { | |
135 | return -1UL << level_to_offset_bits(level); | |
136 | } | |
137 | ||
138 | static inline unsigned long level_size(int level) | |
139 | { | |
140 | return 1UL << level_to_offset_bits(level); | |
141 | } | |
142 | ||
143 | static inline unsigned long align_to_level(unsigned long pfn, int level) | |
144 | { | |
145 | return (pfn + level_size(level) - 1) & level_mask(level); | |
146 | } | |
fd18de50 | 147 | |
6dd9a7c7 YS |
148 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
149 | { | |
5c645b35 | 150 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
6dd9a7c7 YS |
151 | } |
152 | ||
dd4e8319 DW |
153 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
154 | are never going to work. */ | |
155 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
156 | { | |
157 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
158 | } | |
159 | ||
160 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
161 | { | |
162 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
163 | } | |
164 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
165 | { | |
166 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
167 | } | |
168 | static inline unsigned long virt_to_dma_pfn(void *p) | |
169 | { | |
170 | return page_to_dma_pfn(virt_to_page(p)); | |
171 | } | |
172 | ||
d9630fe9 WH |
173 | /* global iommu list, set NULL for ignored DMAR units */ |
174 | static struct intel_iommu **g_iommus; | |
175 | ||
e0fc7e0b | 176 | static void __init check_tylersburg_isoch(void); |
9af88143 DW |
177 | static int rwbf_quirk; |
178 | ||
b779260b JC |
179 | /* |
180 | * set to 1 to panic kernel if can't successfully enable VT-d | |
181 | * (used when kernel is launched w/ TXT) | |
182 | */ | |
183 | static int force_on = 0; | |
184 | ||
46b08e1a MM |
185 | /* |
186 | * 0: Present | |
187 | * 1-11: Reserved | |
188 | * 12-63: Context Ptr (12 - (haw-1)) | |
189 | * 64-127: Reserved | |
190 | */ | |
191 | struct root_entry { | |
03ecc32c DW |
192 | u64 lo; |
193 | u64 hi; | |
46b08e1a MM |
194 | }; |
195 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
46b08e1a | 196 | |
091d42e4 JR |
197 | /* |
198 | * Take a root_entry and return the Lower Context Table Pointer (LCTP) | |
199 | * if marked present. | |
200 | */ | |
201 | static phys_addr_t root_entry_lctp(struct root_entry *re) | |
202 | { | |
203 | if (!(re->lo & 1)) | |
204 | return 0; | |
205 | ||
206 | return re->lo & VTD_PAGE_MASK; | |
207 | } | |
208 | ||
209 | /* | |
210 | * Take a root_entry and return the Upper Context Table Pointer (UCTP) | |
211 | * if marked present. | |
212 | */ | |
213 | static phys_addr_t root_entry_uctp(struct root_entry *re) | |
214 | { | |
215 | if (!(re->hi & 1)) | |
216 | return 0; | |
46b08e1a | 217 | |
091d42e4 JR |
218 | return re->hi & VTD_PAGE_MASK; |
219 | } | |
7a8fc25e MM |
220 | /* |
221 | * low 64 bits: | |
222 | * 0: present | |
223 | * 1: fault processing disable | |
224 | * 2-3: translation type | |
225 | * 12-63: address space root | |
226 | * high 64 bits: | |
227 | * 0-2: address width | |
228 | * 3-6: aval | |
229 | * 8-23: domain id | |
230 | */ | |
231 | struct context_entry { | |
232 | u64 lo; | |
233 | u64 hi; | |
234 | }; | |
c07e7d21 | 235 | |
cf484d0e JR |
236 | static inline void context_clear_pasid_enable(struct context_entry *context) |
237 | { | |
238 | context->lo &= ~(1ULL << 11); | |
239 | } | |
240 | ||
241 | static inline bool context_pasid_enabled(struct context_entry *context) | |
242 | { | |
243 | return !!(context->lo & (1ULL << 11)); | |
244 | } | |
245 | ||
246 | static inline void context_set_copied(struct context_entry *context) | |
247 | { | |
248 | context->hi |= (1ull << 3); | |
249 | } | |
250 | ||
251 | static inline bool context_copied(struct context_entry *context) | |
252 | { | |
253 | return !!(context->hi & (1ULL << 3)); | |
254 | } | |
255 | ||
256 | static inline bool __context_present(struct context_entry *context) | |
c07e7d21 MM |
257 | { |
258 | return (context->lo & 1); | |
259 | } | |
cf484d0e JR |
260 | |
261 | static inline bool context_present(struct context_entry *context) | |
262 | { | |
263 | return context_pasid_enabled(context) ? | |
264 | __context_present(context) : | |
265 | __context_present(context) && !context_copied(context); | |
266 | } | |
267 | ||
c07e7d21 MM |
268 | static inline void context_set_present(struct context_entry *context) |
269 | { | |
270 | context->lo |= 1; | |
271 | } | |
272 | ||
273 | static inline void context_set_fault_enable(struct context_entry *context) | |
274 | { | |
275 | context->lo &= (((u64)-1) << 2) | 1; | |
276 | } | |
277 | ||
c07e7d21 MM |
278 | static inline void context_set_translation_type(struct context_entry *context, |
279 | unsigned long value) | |
280 | { | |
281 | context->lo &= (((u64)-1) << 4) | 3; | |
282 | context->lo |= (value & 3) << 2; | |
283 | } | |
284 | ||
285 | static inline void context_set_address_root(struct context_entry *context, | |
286 | unsigned long value) | |
287 | { | |
1a2262f9 | 288 | context->lo &= ~VTD_PAGE_MASK; |
c07e7d21 MM |
289 | context->lo |= value & VTD_PAGE_MASK; |
290 | } | |
291 | ||
292 | static inline void context_set_address_width(struct context_entry *context, | |
293 | unsigned long value) | |
294 | { | |
295 | context->hi |= value & 7; | |
296 | } | |
297 | ||
298 | static inline void context_set_domain_id(struct context_entry *context, | |
299 | unsigned long value) | |
300 | { | |
301 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
302 | } | |
303 | ||
dbcd861f JR |
304 | static inline int context_domain_id(struct context_entry *c) |
305 | { | |
306 | return((c->hi >> 8) & 0xffff); | |
307 | } | |
308 | ||
c07e7d21 MM |
309 | static inline void context_clear_entry(struct context_entry *context) |
310 | { | |
311 | context->lo = 0; | |
312 | context->hi = 0; | |
313 | } | |
7a8fc25e | 314 | |
622ba12a MM |
315 | /* |
316 | * 0: readable | |
317 | * 1: writable | |
318 | * 2-6: reserved | |
319 | * 7: super page | |
9cf06697 SY |
320 | * 8-10: available |
321 | * 11: snoop behavior | |
622ba12a MM |
322 | * 12-63: Host physcial address |
323 | */ | |
324 | struct dma_pte { | |
325 | u64 val; | |
326 | }; | |
622ba12a | 327 | |
19c239ce MM |
328 | static inline void dma_clear_pte(struct dma_pte *pte) |
329 | { | |
330 | pte->val = 0; | |
331 | } | |
332 | ||
19c239ce MM |
333 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
334 | { | |
c85994e4 DW |
335 | #ifdef CONFIG_64BIT |
336 | return pte->val & VTD_PAGE_MASK; | |
337 | #else | |
338 | /* Must have a full atomic 64-bit read */ | |
1a8bd481 | 339 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
c85994e4 | 340 | #endif |
19c239ce MM |
341 | } |
342 | ||
19c239ce MM |
343 | static inline bool dma_pte_present(struct dma_pte *pte) |
344 | { | |
345 | return (pte->val & 3) != 0; | |
346 | } | |
622ba12a | 347 | |
4399c8bf AK |
348 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
349 | { | |
c3c75eb7 | 350 | return (pte->val & DMA_PTE_LARGE_PAGE); |
4399c8bf AK |
351 | } |
352 | ||
75e6bf96 DW |
353 | static inline int first_pte_in_page(struct dma_pte *pte) |
354 | { | |
355 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
356 | } | |
357 | ||
2c2e2c38 FY |
358 | /* |
359 | * This domain is a statically identity mapping domain. | |
360 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
361 | * 2. It maps to each iommu if successful. | |
362 | * 3. Each iommu mapps to this domain if successful. | |
363 | */ | |
19943b0e DW |
364 | static struct dmar_domain *si_domain; |
365 | static int hw_pass_through = 1; | |
2c2e2c38 | 366 | |
28ccce0d JR |
367 | /* |
368 | * Domain represents a virtual machine, more than one devices | |
1ce28feb WH |
369 | * across iommus may be owned in one domain, e.g. kvm guest. |
370 | */ | |
ab8dfe25 | 371 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0) |
1ce28feb | 372 | |
2c2e2c38 | 373 | /* si_domain contains mulitple devices */ |
ab8dfe25 | 374 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1) |
2c2e2c38 | 375 | |
29a27719 JR |
376 | #define for_each_domain_iommu(idx, domain) \ |
377 | for (idx = 0; idx < g_num_of_iommus; idx++) \ | |
378 | if (domain->iommu_refcnt[idx]) | |
379 | ||
99126f7c | 380 | struct dmar_domain { |
4c923d47 | 381 | int nid; /* node id */ |
29a27719 JR |
382 | |
383 | unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED]; | |
384 | /* Refcount of devices per iommu */ | |
385 | ||
99126f7c | 386 | |
c0e8a6c8 JR |
387 | u16 iommu_did[DMAR_UNITS_SUPPORTED]; |
388 | /* Domain ids per IOMMU. Use u16 since | |
389 | * domain ids are 16 bit wide according | |
390 | * to VT-d spec, section 9.3 */ | |
99126f7c | 391 | |
00a77deb | 392 | struct list_head devices; /* all devices' list */ |
99126f7c MM |
393 | struct iova_domain iovad; /* iova's that belong to this domain */ |
394 | ||
395 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
396 | int gaw; /* max guest address width */ |
397 | ||
398 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
399 | int agaw; | |
400 | ||
3b5410e7 | 401 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
402 | |
403 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 404 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d | 405 | int iommu_count; /* reference count of iommu */ |
6dd9a7c7 YS |
406 | int iommu_superpage;/* Level of superpages supported: |
407 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
408 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
fe40f1e0 | 409 | u64 max_addr; /* maximum mapped address */ |
00a77deb JR |
410 | |
411 | struct iommu_domain domain; /* generic domain data structure for | |
412 | iommu core */ | |
99126f7c MM |
413 | }; |
414 | ||
a647dacb MM |
415 | /* PCI domain-device relationship */ |
416 | struct device_domain_info { | |
417 | struct list_head link; /* link to domain siblings */ | |
418 | struct list_head global; /* link to global list */ | |
276dbf99 | 419 | u8 bus; /* PCI bus number */ |
a647dacb | 420 | u8 devfn; /* PCI devfn number */ |
fb0cc3aa BH |
421 | struct { |
422 | u8 enabled:1; | |
423 | u8 qdep; | |
424 | } ats; /* ATS state */ | |
0bcb3e28 | 425 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
93a23a72 | 426 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
427 | struct dmar_domain *domain; /* pointer to domain */ |
428 | }; | |
429 | ||
b94e4117 JL |
430 | struct dmar_rmrr_unit { |
431 | struct list_head list; /* list of rmrr units */ | |
432 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
433 | u64 base_address; /* reserved base address*/ | |
434 | u64 end_address; /* reserved end address */ | |
832bd858 | 435 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
436 | int devices_cnt; /* target device count */ |
437 | }; | |
438 | ||
439 | struct dmar_atsr_unit { | |
440 | struct list_head list; /* list of ATSR units */ | |
441 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
832bd858 | 442 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
443 | int devices_cnt; /* target device count */ |
444 | u8 include_all:1; /* include all ports */ | |
445 | }; | |
446 | ||
447 | static LIST_HEAD(dmar_atsr_units); | |
448 | static LIST_HEAD(dmar_rmrr_units); | |
449 | ||
450 | #define for_each_rmrr_units(rmrr) \ | |
451 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
452 | ||
5e0d2a6f | 453 | static void flush_unmaps_timeout(unsigned long data); |
454 | ||
b707cb02 | 455 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
5e0d2a6f | 456 | |
80b20dd8 | 457 | #define HIGH_WATER_MARK 250 |
458 | struct deferred_flush_tables { | |
459 | int next; | |
460 | struct iova *iova[HIGH_WATER_MARK]; | |
461 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
ea8ea460 | 462 | struct page *freelist[HIGH_WATER_MARK]; |
80b20dd8 | 463 | }; |
464 | ||
465 | static struct deferred_flush_tables *deferred_flush; | |
466 | ||
5e0d2a6f | 467 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 468 | static int g_num_of_iommus; |
469 | ||
470 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
471 | static LIST_HEAD(unmaps_to_do); | |
472 | ||
473 | static int timer_on; | |
474 | static long list_size; | |
5e0d2a6f | 475 | |
92d03cc8 | 476 | static void domain_exit(struct dmar_domain *domain); |
ba395927 | 477 | static void domain_remove_dev_info(struct dmar_domain *domain); |
e6de0f8d JR |
478 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
479 | struct device *dev); | |
127c7615 | 480 | static void __dmar_remove_one_dev_info(struct device_domain_info *info); |
2452d9db JR |
481 | static void domain_context_clear(struct intel_iommu *iommu, |
482 | struct device *dev); | |
2a46ddf7 JL |
483 | static int domain_detach_iommu(struct dmar_domain *domain, |
484 | struct intel_iommu *iommu); | |
ba395927 | 485 | |
d3f13810 | 486 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
0cd5c3c8 KM |
487 | int dmar_disabled = 0; |
488 | #else | |
489 | int dmar_disabled = 1; | |
d3f13810 | 490 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
0cd5c3c8 | 491 | |
8bc1f85c ED |
492 | int intel_iommu_enabled = 0; |
493 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); | |
494 | ||
2d9e667e | 495 | static int dmar_map_gfx = 1; |
7d3b03ce | 496 | static int dmar_forcedac; |
5e0d2a6f | 497 | static int intel_iommu_strict; |
6dd9a7c7 | 498 | static int intel_iommu_superpage = 1; |
c83b2f20 | 499 | static int intel_iommu_ecs = 1; |
ae853ddb DW |
500 | static int intel_iommu_pasid28; |
501 | static int iommu_identity_mapping; | |
502 | ||
503 | #define IDENTMAP_ALL 1 | |
504 | #define IDENTMAP_GFX 2 | |
505 | #define IDENTMAP_AZALIA 4 | |
c83b2f20 DW |
506 | |
507 | /* We only actually use ECS when PASID support (on the new bit 40) | |
508 | * is also advertised. Some early implementations — the ones with | |
509 | * PASID support on bit 28 — have issues even when we *only* use | |
510 | * extended root/context tables. */ | |
ae853ddb DW |
511 | #define pasid_enabled(iommu) (ecap_pasid(iommu->ecap) || \ |
512 | (intel_iommu_pasid28 && ecap_broken_pasid(iommu->ecap))) | |
c83b2f20 | 513 | #define ecs_enabled(iommu) (intel_iommu_ecs && ecap_ecs(iommu->ecap) && \ |
ae853ddb | 514 | pasid_enabled(iommu)) |
ba395927 | 515 | |
c0771df8 DW |
516 | int intel_iommu_gfx_mapped; |
517 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); | |
518 | ||
ba395927 KA |
519 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
520 | static DEFINE_SPINLOCK(device_domain_lock); | |
521 | static LIST_HEAD(device_domain_list); | |
522 | ||
b22f6434 | 523 | static const struct iommu_ops intel_iommu_ops; |
a8bcbb0d | 524 | |
4158c2ec JR |
525 | static bool translation_pre_enabled(struct intel_iommu *iommu) |
526 | { | |
527 | return (iommu->flags & VTD_FLAG_TRANS_PRE_ENABLED); | |
528 | } | |
529 | ||
091d42e4 JR |
530 | static void clear_translation_pre_enabled(struct intel_iommu *iommu) |
531 | { | |
532 | iommu->flags &= ~VTD_FLAG_TRANS_PRE_ENABLED; | |
533 | } | |
534 | ||
4158c2ec JR |
535 | static void init_translation_status(struct intel_iommu *iommu) |
536 | { | |
537 | u32 gsts; | |
538 | ||
539 | gsts = readl(iommu->reg + DMAR_GSTS_REG); | |
540 | if (gsts & DMA_GSTS_TES) | |
541 | iommu->flags |= VTD_FLAG_TRANS_PRE_ENABLED; | |
542 | } | |
543 | ||
00a77deb JR |
544 | /* Convert generic 'struct iommu_domain to private struct dmar_domain */ |
545 | static struct dmar_domain *to_dmar_domain(struct iommu_domain *dom) | |
546 | { | |
547 | return container_of(dom, struct dmar_domain, domain); | |
548 | } | |
549 | ||
ba395927 KA |
550 | static int __init intel_iommu_setup(char *str) |
551 | { | |
552 | if (!str) | |
553 | return -EINVAL; | |
554 | while (*str) { | |
0cd5c3c8 KM |
555 | if (!strncmp(str, "on", 2)) { |
556 | dmar_disabled = 0; | |
9f10e5bf | 557 | pr_info("IOMMU enabled\n"); |
0cd5c3c8 | 558 | } else if (!strncmp(str, "off", 3)) { |
ba395927 | 559 | dmar_disabled = 1; |
9f10e5bf | 560 | pr_info("IOMMU disabled\n"); |
ba395927 KA |
561 | } else if (!strncmp(str, "igfx_off", 8)) { |
562 | dmar_map_gfx = 0; | |
9f10e5bf | 563 | pr_info("Disable GFX device mapping\n"); |
7d3b03ce | 564 | } else if (!strncmp(str, "forcedac", 8)) { |
9f10e5bf | 565 | pr_info("Forcing DAC for PCI devices\n"); |
7d3b03ce | 566 | dmar_forcedac = 1; |
5e0d2a6f | 567 | } else if (!strncmp(str, "strict", 6)) { |
9f10e5bf | 568 | pr_info("Disable batched IOTLB flush\n"); |
5e0d2a6f | 569 | intel_iommu_strict = 1; |
6dd9a7c7 | 570 | } else if (!strncmp(str, "sp_off", 6)) { |
9f10e5bf | 571 | pr_info("Disable supported super page\n"); |
6dd9a7c7 | 572 | intel_iommu_superpage = 0; |
c83b2f20 DW |
573 | } else if (!strncmp(str, "ecs_off", 7)) { |
574 | printk(KERN_INFO | |
575 | "Intel-IOMMU: disable extended context table support\n"); | |
576 | intel_iommu_ecs = 0; | |
ae853ddb DW |
577 | } else if (!strncmp(str, "pasid28", 7)) { |
578 | printk(KERN_INFO | |
579 | "Intel-IOMMU: enable pre-production PASID support\n"); | |
580 | intel_iommu_pasid28 = 1; | |
581 | iommu_identity_mapping |= IDENTMAP_GFX; | |
ba395927 KA |
582 | } |
583 | ||
584 | str += strcspn(str, ","); | |
585 | while (*str == ',') | |
586 | str++; | |
587 | } | |
588 | return 0; | |
589 | } | |
590 | __setup("intel_iommu=", intel_iommu_setup); | |
591 | ||
592 | static struct kmem_cache *iommu_domain_cache; | |
593 | static struct kmem_cache *iommu_devinfo_cache; | |
ba395927 | 594 | |
9452d5bf JR |
595 | static struct dmar_domain* get_iommu_domain(struct intel_iommu *iommu, u16 did) |
596 | { | |
8bf47816 JR |
597 | struct dmar_domain **domains; |
598 | int idx = did >> 8; | |
599 | ||
600 | domains = iommu->domains[idx]; | |
601 | if (!domains) | |
602 | return NULL; | |
603 | ||
604 | return domains[did & 0xff]; | |
9452d5bf JR |
605 | } |
606 | ||
607 | static void set_iommu_domain(struct intel_iommu *iommu, u16 did, | |
608 | struct dmar_domain *domain) | |
609 | { | |
8bf47816 JR |
610 | struct dmar_domain **domains; |
611 | int idx = did >> 8; | |
612 | ||
613 | if (!iommu->domains[idx]) { | |
614 | size_t size = 256 * sizeof(struct dmar_domain *); | |
615 | iommu->domains[idx] = kzalloc(size, GFP_ATOMIC); | |
616 | } | |
617 | ||
618 | domains = iommu->domains[idx]; | |
619 | if (WARN_ON(!domains)) | |
620 | return; | |
621 | else | |
622 | domains[did & 0xff] = domain; | |
9452d5bf JR |
623 | } |
624 | ||
4c923d47 | 625 | static inline void *alloc_pgtable_page(int node) |
eb3fa7cb | 626 | { |
4c923d47 SS |
627 | struct page *page; |
628 | void *vaddr = NULL; | |
eb3fa7cb | 629 | |
4c923d47 SS |
630 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
631 | if (page) | |
632 | vaddr = page_address(page); | |
eb3fa7cb | 633 | return vaddr; |
ba395927 KA |
634 | } |
635 | ||
636 | static inline void free_pgtable_page(void *vaddr) | |
637 | { | |
638 | free_page((unsigned long)vaddr); | |
639 | } | |
640 | ||
641 | static inline void *alloc_domain_mem(void) | |
642 | { | |
354bb65e | 643 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
ba395927 KA |
644 | } |
645 | ||
38717946 | 646 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
647 | { |
648 | kmem_cache_free(iommu_domain_cache, vaddr); | |
649 | } | |
650 | ||
651 | static inline void * alloc_devinfo_mem(void) | |
652 | { | |
354bb65e | 653 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
ba395927 KA |
654 | } |
655 | ||
656 | static inline void free_devinfo_mem(void *vaddr) | |
657 | { | |
658 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
659 | } | |
660 | ||
ab8dfe25 JL |
661 | static inline int domain_type_is_vm(struct dmar_domain *domain) |
662 | { | |
663 | return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE; | |
664 | } | |
665 | ||
28ccce0d JR |
666 | static inline int domain_type_is_si(struct dmar_domain *domain) |
667 | { | |
668 | return domain->flags & DOMAIN_FLAG_STATIC_IDENTITY; | |
669 | } | |
670 | ||
ab8dfe25 JL |
671 | static inline int domain_type_is_vm_or_si(struct dmar_domain *domain) |
672 | { | |
673 | return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE | | |
674 | DOMAIN_FLAG_STATIC_IDENTITY); | |
675 | } | |
1b573683 | 676 | |
162d1b10 JL |
677 | static inline int domain_pfn_supported(struct dmar_domain *domain, |
678 | unsigned long pfn) | |
679 | { | |
680 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | |
681 | ||
682 | return !(addr_width < BITS_PER_LONG && pfn >> addr_width); | |
683 | } | |
684 | ||
4ed0d3e6 | 685 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
686 | { |
687 | unsigned long sagaw; | |
688 | int agaw = -1; | |
689 | ||
690 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 691 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
692 | agaw >= 0; agaw--) { |
693 | if (test_bit(agaw, &sagaw)) | |
694 | break; | |
695 | } | |
696 | ||
697 | return agaw; | |
698 | } | |
699 | ||
4ed0d3e6 FY |
700 | /* |
701 | * Calculate max SAGAW for each iommu. | |
702 | */ | |
703 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
704 | { | |
705 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
706 | } | |
707 | ||
708 | /* | |
709 | * calculate agaw for each iommu. | |
710 | * "SAGAW" may be different across iommus, use a default agaw, and | |
711 | * get a supported less agaw for iommus that don't support the default agaw. | |
712 | */ | |
713 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
714 | { | |
715 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
716 | } | |
717 | ||
2c2e2c38 | 718 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
719 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
720 | { | |
721 | int iommu_id; | |
722 | ||
2c2e2c38 | 723 | /* si_domain and vm domain should not get here. */ |
ab8dfe25 | 724 | BUG_ON(domain_type_is_vm_or_si(domain)); |
29a27719 JR |
725 | for_each_domain_iommu(iommu_id, domain) |
726 | break; | |
727 | ||
8c11e798 WH |
728 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
729 | return NULL; | |
730 | ||
731 | return g_iommus[iommu_id]; | |
732 | } | |
733 | ||
8e604097 WH |
734 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
735 | { | |
d0501960 DW |
736 | struct dmar_drhd_unit *drhd; |
737 | struct intel_iommu *iommu; | |
2f119c78 QL |
738 | bool found = false; |
739 | int i; | |
2e12bc29 | 740 | |
d0501960 | 741 | domain->iommu_coherency = 1; |
8e604097 | 742 | |
29a27719 | 743 | for_each_domain_iommu(i, domain) { |
2f119c78 | 744 | found = true; |
8e604097 WH |
745 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
746 | domain->iommu_coherency = 0; | |
747 | break; | |
748 | } | |
8e604097 | 749 | } |
d0501960 DW |
750 | if (found) |
751 | return; | |
752 | ||
753 | /* No hardware attached; use lowest common denominator */ | |
754 | rcu_read_lock(); | |
755 | for_each_active_iommu(iommu, drhd) { | |
756 | if (!ecap_coherent(iommu->ecap)) { | |
757 | domain->iommu_coherency = 0; | |
758 | break; | |
759 | } | |
760 | } | |
761 | rcu_read_unlock(); | |
8e604097 WH |
762 | } |
763 | ||
161f6934 | 764 | static int domain_update_iommu_snooping(struct intel_iommu *skip) |
58c610bd | 765 | { |
161f6934 JL |
766 | struct dmar_drhd_unit *drhd; |
767 | struct intel_iommu *iommu; | |
768 | int ret = 1; | |
58c610bd | 769 | |
161f6934 JL |
770 | rcu_read_lock(); |
771 | for_each_active_iommu(iommu, drhd) { | |
772 | if (iommu != skip) { | |
773 | if (!ecap_sc_support(iommu->ecap)) { | |
774 | ret = 0; | |
775 | break; | |
776 | } | |
58c610bd | 777 | } |
58c610bd | 778 | } |
161f6934 JL |
779 | rcu_read_unlock(); |
780 | ||
781 | return ret; | |
58c610bd SY |
782 | } |
783 | ||
161f6934 | 784 | static int domain_update_iommu_superpage(struct intel_iommu *skip) |
6dd9a7c7 | 785 | { |
8140a95d | 786 | struct dmar_drhd_unit *drhd; |
161f6934 | 787 | struct intel_iommu *iommu; |
8140a95d | 788 | int mask = 0xf; |
6dd9a7c7 YS |
789 | |
790 | if (!intel_iommu_superpage) { | |
161f6934 | 791 | return 0; |
6dd9a7c7 YS |
792 | } |
793 | ||
8140a95d | 794 | /* set iommu_superpage to the smallest common denominator */ |
0e242612 | 795 | rcu_read_lock(); |
8140a95d | 796 | for_each_active_iommu(iommu, drhd) { |
161f6934 JL |
797 | if (iommu != skip) { |
798 | mask &= cap_super_page_val(iommu->cap); | |
799 | if (!mask) | |
800 | break; | |
6dd9a7c7 YS |
801 | } |
802 | } | |
0e242612 JL |
803 | rcu_read_unlock(); |
804 | ||
161f6934 | 805 | return fls(mask); |
6dd9a7c7 YS |
806 | } |
807 | ||
58c610bd SY |
808 | /* Some capabilities may be different across iommus */ |
809 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
810 | { | |
811 | domain_update_iommu_coherency(domain); | |
161f6934 JL |
812 | domain->iommu_snooping = domain_update_iommu_snooping(NULL); |
813 | domain->iommu_superpage = domain_update_iommu_superpage(NULL); | |
58c610bd SY |
814 | } |
815 | ||
03ecc32c DW |
816 | static inline struct context_entry *iommu_context_addr(struct intel_iommu *iommu, |
817 | u8 bus, u8 devfn, int alloc) | |
818 | { | |
819 | struct root_entry *root = &iommu->root_entry[bus]; | |
820 | struct context_entry *context; | |
821 | u64 *entry; | |
822 | ||
4df4eab1 | 823 | entry = &root->lo; |
c83b2f20 | 824 | if (ecs_enabled(iommu)) { |
03ecc32c DW |
825 | if (devfn >= 0x80) { |
826 | devfn -= 0x80; | |
827 | entry = &root->hi; | |
828 | } | |
829 | devfn *= 2; | |
830 | } | |
03ecc32c DW |
831 | if (*entry & 1) |
832 | context = phys_to_virt(*entry & VTD_PAGE_MASK); | |
833 | else { | |
834 | unsigned long phy_addr; | |
835 | if (!alloc) | |
836 | return NULL; | |
837 | ||
838 | context = alloc_pgtable_page(iommu->node); | |
839 | if (!context) | |
840 | return NULL; | |
841 | ||
842 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); | |
843 | phy_addr = virt_to_phys((void *)context); | |
844 | *entry = phy_addr | 1; | |
845 | __iommu_flush_cache(iommu, entry, sizeof(*entry)); | |
846 | } | |
847 | return &context[devfn]; | |
848 | } | |
849 | ||
4ed6a540 DW |
850 | static int iommu_dummy(struct device *dev) |
851 | { | |
852 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; | |
853 | } | |
854 | ||
156baca8 | 855 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
c7151a8d WH |
856 | { |
857 | struct dmar_drhd_unit *drhd = NULL; | |
b683b230 | 858 | struct intel_iommu *iommu; |
156baca8 DW |
859 | struct device *tmp; |
860 | struct pci_dev *ptmp, *pdev = NULL; | |
aa4d066a | 861 | u16 segment = 0; |
c7151a8d WH |
862 | int i; |
863 | ||
4ed6a540 DW |
864 | if (iommu_dummy(dev)) |
865 | return NULL; | |
866 | ||
156baca8 DW |
867 | if (dev_is_pci(dev)) { |
868 | pdev = to_pci_dev(dev); | |
869 | segment = pci_domain_nr(pdev->bus); | |
ca5b74d2 | 870 | } else if (has_acpi_companion(dev)) |
156baca8 DW |
871 | dev = &ACPI_COMPANION(dev)->dev; |
872 | ||
0e242612 | 873 | rcu_read_lock(); |
b683b230 | 874 | for_each_active_iommu(iommu, drhd) { |
156baca8 | 875 | if (pdev && segment != drhd->segment) |
276dbf99 | 876 | continue; |
c7151a8d | 877 | |
b683b230 | 878 | for_each_active_dev_scope(drhd->devices, |
156baca8 DW |
879 | drhd->devices_cnt, i, tmp) { |
880 | if (tmp == dev) { | |
881 | *bus = drhd->devices[i].bus; | |
882 | *devfn = drhd->devices[i].devfn; | |
b683b230 | 883 | goto out; |
156baca8 DW |
884 | } |
885 | ||
886 | if (!pdev || !dev_is_pci(tmp)) | |
887 | continue; | |
888 | ||
889 | ptmp = to_pci_dev(tmp); | |
890 | if (ptmp->subordinate && | |
891 | ptmp->subordinate->number <= pdev->bus->number && | |
892 | ptmp->subordinate->busn_res.end >= pdev->bus->number) | |
893 | goto got_pdev; | |
924b6231 | 894 | } |
c7151a8d | 895 | |
156baca8 DW |
896 | if (pdev && drhd->include_all) { |
897 | got_pdev: | |
898 | *bus = pdev->bus->number; | |
899 | *devfn = pdev->devfn; | |
b683b230 | 900 | goto out; |
156baca8 | 901 | } |
c7151a8d | 902 | } |
b683b230 | 903 | iommu = NULL; |
156baca8 | 904 | out: |
0e242612 | 905 | rcu_read_unlock(); |
c7151a8d | 906 | |
b683b230 | 907 | return iommu; |
c7151a8d WH |
908 | } |
909 | ||
5331fe6f WH |
910 | static void domain_flush_cache(struct dmar_domain *domain, |
911 | void *addr, int size) | |
912 | { | |
913 | if (!domain->iommu_coherency) | |
914 | clflush_cache_range(addr, size); | |
915 | } | |
916 | ||
ba395927 KA |
917 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
918 | { | |
ba395927 | 919 | struct context_entry *context; |
03ecc32c | 920 | int ret = 0; |
ba395927 KA |
921 | unsigned long flags; |
922 | ||
923 | spin_lock_irqsave(&iommu->lock, flags); | |
03ecc32c DW |
924 | context = iommu_context_addr(iommu, bus, devfn, 0); |
925 | if (context) | |
926 | ret = context_present(context); | |
ba395927 KA |
927 | spin_unlock_irqrestore(&iommu->lock, flags); |
928 | return ret; | |
929 | } | |
930 | ||
931 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
932 | { | |
ba395927 KA |
933 | struct context_entry *context; |
934 | unsigned long flags; | |
935 | ||
936 | spin_lock_irqsave(&iommu->lock, flags); | |
03ecc32c | 937 | context = iommu_context_addr(iommu, bus, devfn, 0); |
ba395927 | 938 | if (context) { |
03ecc32c DW |
939 | context_clear_entry(context); |
940 | __iommu_flush_cache(iommu, context, sizeof(*context)); | |
ba395927 KA |
941 | } |
942 | spin_unlock_irqrestore(&iommu->lock, flags); | |
943 | } | |
944 | ||
945 | static void free_context_table(struct intel_iommu *iommu) | |
946 | { | |
ba395927 KA |
947 | int i; |
948 | unsigned long flags; | |
949 | struct context_entry *context; | |
950 | ||
951 | spin_lock_irqsave(&iommu->lock, flags); | |
952 | if (!iommu->root_entry) { | |
953 | goto out; | |
954 | } | |
955 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
03ecc32c | 956 | context = iommu_context_addr(iommu, i, 0, 0); |
ba395927 KA |
957 | if (context) |
958 | free_pgtable_page(context); | |
03ecc32c | 959 | |
c83b2f20 | 960 | if (!ecs_enabled(iommu)) |
03ecc32c DW |
961 | continue; |
962 | ||
963 | context = iommu_context_addr(iommu, i, 0x80, 0); | |
964 | if (context) | |
965 | free_pgtable_page(context); | |
966 | ||
ba395927 KA |
967 | } |
968 | free_pgtable_page(iommu->root_entry); | |
969 | iommu->root_entry = NULL; | |
970 | out: | |
971 | spin_unlock_irqrestore(&iommu->lock, flags); | |
972 | } | |
973 | ||
b026fd28 | 974 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
5cf0a76f | 975 | unsigned long pfn, int *target_level) |
ba395927 | 976 | { |
ba395927 KA |
977 | struct dma_pte *parent, *pte = NULL; |
978 | int level = agaw_to_level(domain->agaw); | |
4399c8bf | 979 | int offset; |
ba395927 KA |
980 | |
981 | BUG_ON(!domain->pgd); | |
f9423606 | 982 | |
162d1b10 | 983 | if (!domain_pfn_supported(domain, pfn)) |
f9423606 JS |
984 | /* Address beyond IOMMU's addressing capabilities. */ |
985 | return NULL; | |
986 | ||
ba395927 KA |
987 | parent = domain->pgd; |
988 | ||
5cf0a76f | 989 | while (1) { |
ba395927 KA |
990 | void *tmp_page; |
991 | ||
b026fd28 | 992 | offset = pfn_level_offset(pfn, level); |
ba395927 | 993 | pte = &parent[offset]; |
5cf0a76f | 994 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
6dd9a7c7 | 995 | break; |
5cf0a76f | 996 | if (level == *target_level) |
ba395927 KA |
997 | break; |
998 | ||
19c239ce | 999 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
1000 | uint64_t pteval; |
1001 | ||
4c923d47 | 1002 | tmp_page = alloc_pgtable_page(domain->nid); |
ba395927 | 1003 | |
206a73c1 | 1004 | if (!tmp_page) |
ba395927 | 1005 | return NULL; |
206a73c1 | 1006 | |
c85994e4 | 1007 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
64de5af0 | 1008 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
effad4b5 | 1009 | if (cmpxchg64(&pte->val, 0ULL, pteval)) |
c85994e4 DW |
1010 | /* Someone else set it while we were thinking; use theirs. */ |
1011 | free_pgtable_page(tmp_page); | |
effad4b5 | 1012 | else |
c85994e4 | 1013 | domain_flush_cache(domain, pte, sizeof(*pte)); |
ba395927 | 1014 | } |
5cf0a76f DW |
1015 | if (level == 1) |
1016 | break; | |
1017 | ||
19c239ce | 1018 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
1019 | level--; |
1020 | } | |
1021 | ||
5cf0a76f DW |
1022 | if (!*target_level) |
1023 | *target_level = level; | |
1024 | ||
ba395927 KA |
1025 | return pte; |
1026 | } | |
1027 | ||
6dd9a7c7 | 1028 | |
ba395927 | 1029 | /* return address's pte at specific level */ |
90dcfb5e DW |
1030 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
1031 | unsigned long pfn, | |
6dd9a7c7 | 1032 | int level, int *large_page) |
ba395927 KA |
1033 | { |
1034 | struct dma_pte *parent, *pte = NULL; | |
1035 | int total = agaw_to_level(domain->agaw); | |
1036 | int offset; | |
1037 | ||
1038 | parent = domain->pgd; | |
1039 | while (level <= total) { | |
90dcfb5e | 1040 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
1041 | pte = &parent[offset]; |
1042 | if (level == total) | |
1043 | return pte; | |
1044 | ||
6dd9a7c7 YS |
1045 | if (!dma_pte_present(pte)) { |
1046 | *large_page = total; | |
ba395927 | 1047 | break; |
6dd9a7c7 YS |
1048 | } |
1049 | ||
e16922af | 1050 | if (dma_pte_superpage(pte)) { |
6dd9a7c7 YS |
1051 | *large_page = total; |
1052 | return pte; | |
1053 | } | |
1054 | ||
19c239ce | 1055 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
1056 | total--; |
1057 | } | |
1058 | return NULL; | |
1059 | } | |
1060 | ||
ba395927 | 1061 | /* clear last level pte, a tlb flush should be followed */ |
5cf0a76f | 1062 | static void dma_pte_clear_range(struct dmar_domain *domain, |
595badf5 DW |
1063 | unsigned long start_pfn, |
1064 | unsigned long last_pfn) | |
ba395927 | 1065 | { |
6dd9a7c7 | 1066 | unsigned int large_page = 1; |
310a5ab9 | 1067 | struct dma_pte *first_pte, *pte; |
66eae846 | 1068 | |
162d1b10 JL |
1069 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1070 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 1071 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 1072 | |
04b18e65 | 1073 | /* we don't need lock here; nobody else touches the iova range */ |
59c36286 | 1074 | do { |
6dd9a7c7 YS |
1075 | large_page = 1; |
1076 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); | |
310a5ab9 | 1077 | if (!pte) { |
6dd9a7c7 | 1078 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
310a5ab9 DW |
1079 | continue; |
1080 | } | |
6dd9a7c7 | 1081 | do { |
310a5ab9 | 1082 | dma_clear_pte(pte); |
6dd9a7c7 | 1083 | start_pfn += lvl_to_nr_pages(large_page); |
310a5ab9 | 1084 | pte++; |
75e6bf96 DW |
1085 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
1086 | ||
310a5ab9 DW |
1087 | domain_flush_cache(domain, first_pte, |
1088 | (void *)pte - (void *)first_pte); | |
59c36286 DW |
1089 | |
1090 | } while (start_pfn && start_pfn <= last_pfn); | |
ba395927 KA |
1091 | } |
1092 | ||
3269ee0b AW |
1093 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
1094 | struct dma_pte *pte, unsigned long pfn, | |
1095 | unsigned long start_pfn, unsigned long last_pfn) | |
1096 | { | |
1097 | pfn = max(start_pfn, pfn); | |
1098 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1099 | ||
1100 | do { | |
1101 | unsigned long level_pfn; | |
1102 | struct dma_pte *level_pte; | |
1103 | ||
1104 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) | |
1105 | goto next; | |
1106 | ||
1107 | level_pfn = pfn & level_mask(level - 1); | |
1108 | level_pte = phys_to_virt(dma_pte_addr(pte)); | |
1109 | ||
1110 | if (level > 2) | |
1111 | dma_pte_free_level(domain, level - 1, level_pte, | |
1112 | level_pfn, start_pfn, last_pfn); | |
1113 | ||
1114 | /* If range covers entire pagetable, free it */ | |
1115 | if (!(start_pfn > level_pfn || | |
08336fd2 | 1116 | last_pfn < level_pfn + level_size(level) - 1)) { |
3269ee0b AW |
1117 | dma_clear_pte(pte); |
1118 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
1119 | free_pgtable_page(level_pte); | |
1120 | } | |
1121 | next: | |
1122 | pfn += level_size(level); | |
1123 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1124 | } | |
1125 | ||
ba395927 KA |
1126 | /* free page table pages. last level pte should already be cleared */ |
1127 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
1128 | unsigned long start_pfn, |
1129 | unsigned long last_pfn) | |
ba395927 | 1130 | { |
162d1b10 JL |
1131 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1132 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
59c36286 | 1133 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 1134 | |
d41a4adb JL |
1135 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
1136 | ||
f3a0a52f | 1137 | /* We don't need lock here; nobody else touches the iova range */ |
3269ee0b AW |
1138 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
1139 | domain->pgd, 0, start_pfn, last_pfn); | |
6660c63a | 1140 | |
ba395927 | 1141 | /* free pgd */ |
d794dc9b | 1142 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
1143 | free_pgtable_page(domain->pgd); |
1144 | domain->pgd = NULL; | |
1145 | } | |
1146 | } | |
1147 | ||
ea8ea460 DW |
1148 | /* When a page at a given level is being unlinked from its parent, we don't |
1149 | need to *modify* it at all. All we need to do is make a list of all the | |
1150 | pages which can be freed just as soon as we've flushed the IOTLB and we | |
1151 | know the hardware page-walk will no longer touch them. | |
1152 | The 'pte' argument is the *parent* PTE, pointing to the page that is to | |
1153 | be freed. */ | |
1154 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, | |
1155 | int level, struct dma_pte *pte, | |
1156 | struct page *freelist) | |
1157 | { | |
1158 | struct page *pg; | |
1159 | ||
1160 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); | |
1161 | pg->freelist = freelist; | |
1162 | freelist = pg; | |
1163 | ||
1164 | if (level == 1) | |
1165 | return freelist; | |
1166 | ||
adeb2590 JL |
1167 | pte = page_address(pg); |
1168 | do { | |
ea8ea460 DW |
1169 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
1170 | freelist = dma_pte_list_pagetables(domain, level - 1, | |
1171 | pte, freelist); | |
adeb2590 JL |
1172 | pte++; |
1173 | } while (!first_pte_in_page(pte)); | |
ea8ea460 DW |
1174 | |
1175 | return freelist; | |
1176 | } | |
1177 | ||
1178 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, | |
1179 | struct dma_pte *pte, unsigned long pfn, | |
1180 | unsigned long start_pfn, | |
1181 | unsigned long last_pfn, | |
1182 | struct page *freelist) | |
1183 | { | |
1184 | struct dma_pte *first_pte = NULL, *last_pte = NULL; | |
1185 | ||
1186 | pfn = max(start_pfn, pfn); | |
1187 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1188 | ||
1189 | do { | |
1190 | unsigned long level_pfn; | |
1191 | ||
1192 | if (!dma_pte_present(pte)) | |
1193 | goto next; | |
1194 | ||
1195 | level_pfn = pfn & level_mask(level); | |
1196 | ||
1197 | /* If range covers entire pagetable, free it */ | |
1198 | if (start_pfn <= level_pfn && | |
1199 | last_pfn >= level_pfn + level_size(level) - 1) { | |
1200 | /* These suborbinate page tables are going away entirely. Don't | |
1201 | bother to clear them; we're just going to *free* them. */ | |
1202 | if (level > 1 && !dma_pte_superpage(pte)) | |
1203 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); | |
1204 | ||
1205 | dma_clear_pte(pte); | |
1206 | if (!first_pte) | |
1207 | first_pte = pte; | |
1208 | last_pte = pte; | |
1209 | } else if (level > 1) { | |
1210 | /* Recurse down into a level that isn't *entirely* obsolete */ | |
1211 | freelist = dma_pte_clear_level(domain, level - 1, | |
1212 | phys_to_virt(dma_pte_addr(pte)), | |
1213 | level_pfn, start_pfn, last_pfn, | |
1214 | freelist); | |
1215 | } | |
1216 | next: | |
1217 | pfn += level_size(level); | |
1218 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1219 | ||
1220 | if (first_pte) | |
1221 | domain_flush_cache(domain, first_pte, | |
1222 | (void *)++last_pte - (void *)first_pte); | |
1223 | ||
1224 | return freelist; | |
1225 | } | |
1226 | ||
1227 | /* We can't just free the pages because the IOMMU may still be walking | |
1228 | the page tables, and may have cached the intermediate levels. The | |
1229 | pages can only be freed after the IOTLB flush has been done. */ | |
b690420a JR |
1230 | static struct page *domain_unmap(struct dmar_domain *domain, |
1231 | unsigned long start_pfn, | |
1232 | unsigned long last_pfn) | |
ea8ea460 | 1233 | { |
ea8ea460 DW |
1234 | struct page *freelist = NULL; |
1235 | ||
162d1b10 JL |
1236 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
1237 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); | |
ea8ea460 DW |
1238 | BUG_ON(start_pfn > last_pfn); |
1239 | ||
1240 | /* we don't need lock here; nobody else touches the iova range */ | |
1241 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), | |
1242 | domain->pgd, 0, start_pfn, last_pfn, NULL); | |
1243 | ||
1244 | /* free pgd */ | |
1245 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { | |
1246 | struct page *pgd_page = virt_to_page(domain->pgd); | |
1247 | pgd_page->freelist = freelist; | |
1248 | freelist = pgd_page; | |
1249 | ||
1250 | domain->pgd = NULL; | |
1251 | } | |
1252 | ||
1253 | return freelist; | |
1254 | } | |
1255 | ||
b690420a | 1256 | static void dma_free_pagelist(struct page *freelist) |
ea8ea460 DW |
1257 | { |
1258 | struct page *pg; | |
1259 | ||
1260 | while ((pg = freelist)) { | |
1261 | freelist = pg->freelist; | |
1262 | free_pgtable_page(page_address(pg)); | |
1263 | } | |
1264 | } | |
1265 | ||
ba395927 KA |
1266 | /* iommu handling */ |
1267 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
1268 | { | |
1269 | struct root_entry *root; | |
1270 | unsigned long flags; | |
1271 | ||
4c923d47 | 1272 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
ffebeb46 | 1273 | if (!root) { |
9f10e5bf | 1274 | pr_err("Allocating root entry for %s failed\n", |
ffebeb46 | 1275 | iommu->name); |
ba395927 | 1276 | return -ENOMEM; |
ffebeb46 | 1277 | } |
ba395927 | 1278 | |
5b6985ce | 1279 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
1280 | |
1281 | spin_lock_irqsave(&iommu->lock, flags); | |
1282 | iommu->root_entry = root; | |
1283 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1284 | ||
1285 | return 0; | |
1286 | } | |
1287 | ||
ba395927 KA |
1288 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
1289 | { | |
03ecc32c | 1290 | u64 addr; |
c416daa9 | 1291 | u32 sts; |
ba395927 KA |
1292 | unsigned long flag; |
1293 | ||
03ecc32c | 1294 | addr = virt_to_phys(iommu->root_entry); |
c83b2f20 | 1295 | if (ecs_enabled(iommu)) |
03ecc32c | 1296 | addr |= DMA_RTADDR_RTT; |
ba395927 | 1297 | |
1f5b3c3f | 1298 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
03ecc32c | 1299 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr); |
ba395927 | 1300 | |
c416daa9 | 1301 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1302 | |
1303 | /* Make sure hardware complete it */ | |
1304 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1305 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 | 1306 | |
1f5b3c3f | 1307 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1308 | } |
1309 | ||
1310 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
1311 | { | |
1312 | u32 val; | |
1313 | unsigned long flag; | |
1314 | ||
9af88143 | 1315 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 1316 | return; |
ba395927 | 1317 | |
1f5b3c3f | 1318 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
462b60f6 | 1319 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1320 | |
1321 | /* Make sure hardware complete it */ | |
1322 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1323 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 | 1324 | |
1f5b3c3f | 1325 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1326 | } |
1327 | ||
1328 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
1329 | static void __iommu_flush_context(struct intel_iommu *iommu, |
1330 | u16 did, u16 source_id, u8 function_mask, | |
1331 | u64 type) | |
ba395927 KA |
1332 | { |
1333 | u64 val = 0; | |
1334 | unsigned long flag; | |
1335 | ||
ba395927 KA |
1336 | switch (type) { |
1337 | case DMA_CCMD_GLOBAL_INVL: | |
1338 | val = DMA_CCMD_GLOBAL_INVL; | |
1339 | break; | |
1340 | case DMA_CCMD_DOMAIN_INVL: | |
1341 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
1342 | break; | |
1343 | case DMA_CCMD_DEVICE_INVL: | |
1344 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
1345 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
1346 | break; | |
1347 | default: | |
1348 | BUG(); | |
1349 | } | |
1350 | val |= DMA_CCMD_ICC; | |
1351 | ||
1f5b3c3f | 1352 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1353 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
1354 | ||
1355 | /* Make sure hardware complete it */ | |
1356 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
1357 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
1358 | ||
1f5b3c3f | 1359 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1360 | } |
1361 | ||
ba395927 | 1362 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
1363 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
1364 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
1365 | { |
1366 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
1367 | u64 val = 0, val_iva = 0; | |
1368 | unsigned long flag; | |
1369 | ||
ba395927 KA |
1370 | switch (type) { |
1371 | case DMA_TLB_GLOBAL_FLUSH: | |
1372 | /* global flush doesn't need set IVA_REG */ | |
1373 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
1374 | break; | |
1375 | case DMA_TLB_DSI_FLUSH: | |
1376 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
1377 | break; | |
1378 | case DMA_TLB_PSI_FLUSH: | |
1379 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
ea8ea460 | 1380 | /* IH bit is passed in as part of address */ |
ba395927 KA |
1381 | val_iva = size_order | addr; |
1382 | break; | |
1383 | default: | |
1384 | BUG(); | |
1385 | } | |
1386 | /* Note: set drain read/write */ | |
1387 | #if 0 | |
1388 | /* | |
1389 | * This is probably to be super secure.. Looks like we can | |
1390 | * ignore it without any impact. | |
1391 | */ | |
1392 | if (cap_read_drain(iommu->cap)) | |
1393 | val |= DMA_TLB_READ_DRAIN; | |
1394 | #endif | |
1395 | if (cap_write_drain(iommu->cap)) | |
1396 | val |= DMA_TLB_WRITE_DRAIN; | |
1397 | ||
1f5b3c3f | 1398 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1399 | /* Note: Only uses first TLB reg currently */ |
1400 | if (val_iva) | |
1401 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
1402 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
1403 | ||
1404 | /* Make sure hardware complete it */ | |
1405 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
1406 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
1407 | ||
1f5b3c3f | 1408 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1409 | |
1410 | /* check IOTLB invalidation granularity */ | |
1411 | if (DMA_TLB_IAIG(val) == 0) | |
9f10e5bf | 1412 | pr_err("Flush IOTLB failed\n"); |
ba395927 | 1413 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
9f10e5bf | 1414 | pr_debug("TLB flush request %Lx, actual %Lx\n", |
5b6985ce FY |
1415 | (unsigned long long)DMA_TLB_IIRG(type), |
1416 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
1417 | } |
1418 | ||
64ae892b DW |
1419 | static struct device_domain_info * |
1420 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, | |
1421 | u8 bus, u8 devfn) | |
93a23a72 | 1422 | { |
2f119c78 | 1423 | bool found = false; |
93a23a72 | 1424 | struct device_domain_info *info; |
0bcb3e28 | 1425 | struct pci_dev *pdev; |
93a23a72 | 1426 | |
55d94043 JR |
1427 | assert_spin_locked(&device_domain_lock); |
1428 | ||
93a23a72 YZ |
1429 | if (!ecap_dev_iotlb_support(iommu->ecap)) |
1430 | return NULL; | |
1431 | ||
1432 | if (!iommu->qi) | |
1433 | return NULL; | |
1434 | ||
93a23a72 | 1435 | list_for_each_entry(info, &domain->devices, link) |
c3b497c6 JL |
1436 | if (info->iommu == iommu && info->bus == bus && |
1437 | info->devfn == devfn) { | |
2f119c78 | 1438 | found = true; |
93a23a72 YZ |
1439 | break; |
1440 | } | |
93a23a72 | 1441 | |
0bcb3e28 | 1442 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1443 | return NULL; |
1444 | ||
0bcb3e28 DW |
1445 | pdev = to_pci_dev(info->dev); |
1446 | ||
1447 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) | |
93a23a72 YZ |
1448 | return NULL; |
1449 | ||
0bcb3e28 | 1450 | if (!dmar_find_matched_atsr_unit(pdev)) |
93a23a72 YZ |
1451 | return NULL; |
1452 | ||
93a23a72 YZ |
1453 | return info; |
1454 | } | |
1455 | ||
1456 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1457 | { |
fb0cc3aa BH |
1458 | struct pci_dev *pdev; |
1459 | ||
0bcb3e28 | 1460 | if (!info || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1461 | return; |
1462 | ||
fb0cc3aa BH |
1463 | pdev = to_pci_dev(info->dev); |
1464 | if (pci_enable_ats(pdev, VTD_PAGE_SHIFT)) | |
1465 | return; | |
1466 | ||
1467 | info->ats.enabled = 1; | |
1468 | info->ats.qdep = pci_ats_queue_depth(pdev); | |
93a23a72 YZ |
1469 | } |
1470 | ||
1471 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1472 | { | |
fb0cc3aa | 1473 | if (!info->ats.enabled) |
93a23a72 YZ |
1474 | return; |
1475 | ||
0bcb3e28 | 1476 | pci_disable_ats(to_pci_dev(info->dev)); |
fb0cc3aa | 1477 | info->ats.enabled = 0; |
93a23a72 YZ |
1478 | } |
1479 | ||
1480 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1481 | u64 addr, unsigned mask) | |
1482 | { | |
1483 | u16 sid, qdep; | |
1484 | unsigned long flags; | |
1485 | struct device_domain_info *info; | |
1486 | ||
1487 | spin_lock_irqsave(&device_domain_lock, flags); | |
1488 | list_for_each_entry(info, &domain->devices, link) { | |
fb0cc3aa | 1489 | if (!info->ats.enabled) |
93a23a72 YZ |
1490 | continue; |
1491 | ||
1492 | sid = info->bus << 8 | info->devfn; | |
fb0cc3aa | 1493 | qdep = info->ats.qdep; |
93a23a72 YZ |
1494 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
1495 | } | |
1496 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1497 | } | |
1498 | ||
a1ddcbe9 JR |
1499 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, |
1500 | struct dmar_domain *domain, | |
1501 | unsigned long pfn, unsigned int pages, | |
1502 | int ih, int map) | |
ba395927 | 1503 | { |
9dd2fe89 | 1504 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1505 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
a1ddcbe9 | 1506 | u16 did = domain->iommu_did[iommu->seq_id]; |
ba395927 | 1507 | |
ba395927 KA |
1508 | BUG_ON(pages == 0); |
1509 | ||
ea8ea460 DW |
1510 | if (ih) |
1511 | ih = 1 << 6; | |
ba395927 | 1512 | /* |
9dd2fe89 YZ |
1513 | * Fallback to domain selective flush if no PSI support or the size is |
1514 | * too big. | |
ba395927 KA |
1515 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1516 | * aligned to the size | |
1517 | */ | |
9dd2fe89 YZ |
1518 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1519 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1520 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 | 1521 | else |
ea8ea460 | 1522 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
9dd2fe89 | 1523 | DMA_TLB_PSI_FLUSH); |
bf92df30 YZ |
1524 | |
1525 | /* | |
82653633 NA |
1526 | * In caching mode, changes of pages from non-present to present require |
1527 | * flush. However, device IOTLB doesn't need to be flushed in this case. | |
bf92df30 | 1528 | */ |
82653633 | 1529 | if (!cap_caching_mode(iommu->cap) || !map) |
9452d5bf JR |
1530 | iommu_flush_dev_iotlb(get_iommu_domain(iommu, did), |
1531 | addr, mask); | |
ba395927 KA |
1532 | } |
1533 | ||
f8bab735 | 1534 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1535 | { | |
1536 | u32 pmen; | |
1537 | unsigned long flags; | |
1538 | ||
1f5b3c3f | 1539 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
f8bab735 | 1540 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
1541 | pmen &= ~DMA_PMEN_EPM; | |
1542 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1543 | ||
1544 | /* wait for the protected region status bit to clear */ | |
1545 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1546 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1547 | ||
1f5b3c3f | 1548 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
f8bab735 | 1549 | } |
1550 | ||
2a41ccee | 1551 | static void iommu_enable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1552 | { |
1553 | u32 sts; | |
1554 | unsigned long flags; | |
1555 | ||
1f5b3c3f | 1556 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
c416daa9 DW |
1557 | iommu->gcmd |= DMA_GCMD_TE; |
1558 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1559 | |
1560 | /* Make sure hardware complete it */ | |
1561 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1562 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1563 | |
1f5b3c3f | 1564 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
ba395927 KA |
1565 | } |
1566 | ||
2a41ccee | 1567 | static void iommu_disable_translation(struct intel_iommu *iommu) |
ba395927 KA |
1568 | { |
1569 | u32 sts; | |
1570 | unsigned long flag; | |
1571 | ||
1f5b3c3f | 1572 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1573 | iommu->gcmd &= ~DMA_GCMD_TE; |
1574 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1575 | ||
1576 | /* Make sure hardware complete it */ | |
1577 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1578 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 | 1579 | |
1f5b3c3f | 1580 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1581 | } |
1582 | ||
3460a6d9 | 1583 | |
ba395927 KA |
1584 | static int iommu_init_domains(struct intel_iommu *iommu) |
1585 | { | |
8bf47816 JR |
1586 | u32 ndomains, nlongs; |
1587 | size_t size; | |
ba395927 KA |
1588 | |
1589 | ndomains = cap_ndoms(iommu->cap); | |
8bf47816 | 1590 | pr_debug("%s: Number of Domains supported <%d>\n", |
9f10e5bf | 1591 | iommu->name, ndomains); |
ba395927 KA |
1592 | nlongs = BITS_TO_LONGS(ndomains); |
1593 | ||
94a91b50 DD |
1594 | spin_lock_init(&iommu->lock); |
1595 | ||
ba395927 KA |
1596 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
1597 | if (!iommu->domain_ids) { | |
9f10e5bf JR |
1598 | pr_err("%s: Allocating domain id array failed\n", |
1599 | iommu->name); | |
ba395927 KA |
1600 | return -ENOMEM; |
1601 | } | |
8bf47816 JR |
1602 | |
1603 | size = ((ndomains >> 8) + 1) * sizeof(struct dmar_domain **); | |
1604 | iommu->domains = kzalloc(size, GFP_KERNEL); | |
1605 | ||
1606 | if (iommu->domains) { | |
1607 | size = 256 * sizeof(struct dmar_domain *); | |
1608 | iommu->domains[0] = kzalloc(size, GFP_KERNEL); | |
1609 | } | |
1610 | ||
1611 | if (!iommu->domains || !iommu->domains[0]) { | |
9f10e5bf JR |
1612 | pr_err("%s: Allocating domain array failed\n", |
1613 | iommu->name); | |
852bdb04 | 1614 | kfree(iommu->domain_ids); |
8bf47816 | 1615 | kfree(iommu->domains); |
852bdb04 | 1616 | iommu->domain_ids = NULL; |
8bf47816 | 1617 | iommu->domains = NULL; |
ba395927 KA |
1618 | return -ENOMEM; |
1619 | } | |
1620 | ||
8bf47816 JR |
1621 | |
1622 | ||
ba395927 | 1623 | /* |
c0e8a6c8 JR |
1624 | * If Caching mode is set, then invalid translations are tagged |
1625 | * with domain-id 0, hence we need to pre-allocate it. We also | |
1626 | * use domain-id 0 as a marker for non-allocated domain-id, so | |
1627 | * make sure it is not used for a real domain. | |
ba395927 | 1628 | */ |
c0e8a6c8 JR |
1629 | set_bit(0, iommu->domain_ids); |
1630 | ||
ba395927 KA |
1631 | return 0; |
1632 | } | |
ba395927 | 1633 | |
ffebeb46 | 1634 | static void disable_dmar_iommu(struct intel_iommu *iommu) |
ba395927 | 1635 | { |
29a27719 | 1636 | struct device_domain_info *info, *tmp; |
55d94043 | 1637 | unsigned long flags; |
ba395927 | 1638 | |
29a27719 JR |
1639 | if (!iommu->domains || !iommu->domain_ids) |
1640 | return; | |
a4eaa86c | 1641 | |
55d94043 | 1642 | spin_lock_irqsave(&device_domain_lock, flags); |
29a27719 JR |
1643 | list_for_each_entry_safe(info, tmp, &device_domain_list, global) { |
1644 | struct dmar_domain *domain; | |
1645 | ||
1646 | if (info->iommu != iommu) | |
1647 | continue; | |
1648 | ||
1649 | if (!info->dev || !info->domain) | |
1650 | continue; | |
1651 | ||
1652 | domain = info->domain; | |
1653 | ||
e6de0f8d | 1654 | dmar_remove_one_dev_info(domain, info->dev); |
29a27719 JR |
1655 | |
1656 | if (!domain_type_is_vm_or_si(domain)) | |
1657 | domain_exit(domain); | |
ba395927 | 1658 | } |
55d94043 | 1659 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 KA |
1660 | |
1661 | if (iommu->gcmd & DMA_GCMD_TE) | |
1662 | iommu_disable_translation(iommu); | |
ffebeb46 | 1663 | } |
ba395927 | 1664 | |
ffebeb46 JL |
1665 | static void free_dmar_iommu(struct intel_iommu *iommu) |
1666 | { | |
1667 | if ((iommu->domains) && (iommu->domain_ids)) { | |
8bf47816 JR |
1668 | int elems = (cap_ndoms(iommu->cap) >> 8) + 1; |
1669 | int i; | |
1670 | ||
1671 | for (i = 0; i < elems; i++) | |
1672 | kfree(iommu->domains[i]); | |
ffebeb46 JL |
1673 | kfree(iommu->domains); |
1674 | kfree(iommu->domain_ids); | |
1675 | iommu->domains = NULL; | |
1676 | iommu->domain_ids = NULL; | |
1677 | } | |
ba395927 | 1678 | |
d9630fe9 WH |
1679 | g_iommus[iommu->seq_id] = NULL; |
1680 | ||
ba395927 KA |
1681 | /* free context mapping */ |
1682 | free_context_table(iommu); | |
ba395927 KA |
1683 | } |
1684 | ||
ab8dfe25 | 1685 | static struct dmar_domain *alloc_domain(int flags) |
ba395927 | 1686 | { |
ba395927 | 1687 | struct dmar_domain *domain; |
ba395927 KA |
1688 | |
1689 | domain = alloc_domain_mem(); | |
1690 | if (!domain) | |
1691 | return NULL; | |
1692 | ||
ab8dfe25 | 1693 | memset(domain, 0, sizeof(*domain)); |
4c923d47 | 1694 | domain->nid = -1; |
ab8dfe25 | 1695 | domain->flags = flags; |
92d03cc8 | 1696 | INIT_LIST_HEAD(&domain->devices); |
2c2e2c38 FY |
1697 | |
1698 | return domain; | |
1699 | } | |
1700 | ||
d160aca5 JR |
1701 | /* Must be called with iommu->lock */ |
1702 | static int domain_attach_iommu(struct dmar_domain *domain, | |
fb170fb4 JL |
1703 | struct intel_iommu *iommu) |
1704 | { | |
44bde614 | 1705 | unsigned long ndomains; |
55d94043 | 1706 | int num; |
44bde614 | 1707 | |
55d94043 | 1708 | assert_spin_locked(&device_domain_lock); |
d160aca5 | 1709 | assert_spin_locked(&iommu->lock); |
ba395927 | 1710 | |
29a27719 JR |
1711 | domain->iommu_refcnt[iommu->seq_id] += 1; |
1712 | domain->iommu_count += 1; | |
1713 | if (domain->iommu_refcnt[iommu->seq_id] == 1) { | |
fb170fb4 | 1714 | ndomains = cap_ndoms(iommu->cap); |
d160aca5 JR |
1715 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1716 | ||
1717 | if (num >= ndomains) { | |
1718 | pr_err("%s: No free domain ids\n", iommu->name); | |
1719 | domain->iommu_refcnt[iommu->seq_id] -= 1; | |
1720 | domain->iommu_count -= 1; | |
55d94043 | 1721 | return -ENOSPC; |
2c2e2c38 | 1722 | } |
ba395927 | 1723 | |
d160aca5 JR |
1724 | set_bit(num, iommu->domain_ids); |
1725 | set_iommu_domain(iommu, num, domain); | |
1726 | ||
1727 | domain->iommu_did[iommu->seq_id] = num; | |
1728 | domain->nid = iommu->node; | |
fb170fb4 | 1729 | |
fb170fb4 JL |
1730 | domain_update_iommu_cap(domain); |
1731 | } | |
d160aca5 | 1732 | |
55d94043 | 1733 | return 0; |
fb170fb4 JL |
1734 | } |
1735 | ||
1736 | static int domain_detach_iommu(struct dmar_domain *domain, | |
1737 | struct intel_iommu *iommu) | |
1738 | { | |
d160aca5 | 1739 | int num, count = INT_MAX; |
d160aca5 | 1740 | |
55d94043 | 1741 | assert_spin_locked(&device_domain_lock); |
d160aca5 | 1742 | assert_spin_locked(&iommu->lock); |
fb170fb4 | 1743 | |
29a27719 JR |
1744 | domain->iommu_refcnt[iommu->seq_id] -= 1; |
1745 | count = --domain->iommu_count; | |
1746 | if (domain->iommu_refcnt[iommu->seq_id] == 0) { | |
d160aca5 JR |
1747 | num = domain->iommu_did[iommu->seq_id]; |
1748 | clear_bit(num, iommu->domain_ids); | |
1749 | set_iommu_domain(iommu, num, NULL); | |
fb170fb4 | 1750 | |
fb170fb4 | 1751 | domain_update_iommu_cap(domain); |
c0e8a6c8 | 1752 | domain->iommu_did[iommu->seq_id] = 0; |
fb170fb4 | 1753 | } |
fb170fb4 JL |
1754 | |
1755 | return count; | |
1756 | } | |
1757 | ||
ba395927 | 1758 | static struct iova_domain reserved_iova_list; |
8a443df4 | 1759 | static struct lock_class_key reserved_rbtree_key; |
ba395927 | 1760 | |
51a63e67 | 1761 | static int dmar_init_reserved_ranges(void) |
ba395927 KA |
1762 | { |
1763 | struct pci_dev *pdev = NULL; | |
1764 | struct iova *iova; | |
1765 | int i; | |
ba395927 | 1766 | |
0fb5fe87 RM |
1767 | init_iova_domain(&reserved_iova_list, VTD_PAGE_SIZE, IOVA_START_PFN, |
1768 | DMA_32BIT_PFN); | |
ba395927 | 1769 | |
8a443df4 MG |
1770 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
1771 | &reserved_rbtree_key); | |
1772 | ||
ba395927 KA |
1773 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1774 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1775 | IOVA_PFN(IOAPIC_RANGE_END)); | |
51a63e67 | 1776 | if (!iova) { |
9f10e5bf | 1777 | pr_err("Reserve IOAPIC range failed\n"); |
51a63e67 JC |
1778 | return -ENODEV; |
1779 | } | |
ba395927 KA |
1780 | |
1781 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1782 | for_each_pci_dev(pdev) { | |
1783 | struct resource *r; | |
1784 | ||
1785 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1786 | r = &pdev->resource[i]; | |
1787 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1788 | continue; | |
1a4a4551 DW |
1789 | iova = reserve_iova(&reserved_iova_list, |
1790 | IOVA_PFN(r->start), | |
1791 | IOVA_PFN(r->end)); | |
51a63e67 | 1792 | if (!iova) { |
9f10e5bf | 1793 | pr_err("Reserve iova failed\n"); |
51a63e67 JC |
1794 | return -ENODEV; |
1795 | } | |
ba395927 KA |
1796 | } |
1797 | } | |
51a63e67 | 1798 | return 0; |
ba395927 KA |
1799 | } |
1800 | ||
1801 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1802 | { | |
1803 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1804 | } | |
1805 | ||
1806 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1807 | { | |
1808 | int agaw; | |
1809 | int r = (gaw - 12) % 9; | |
1810 | ||
1811 | if (r == 0) | |
1812 | agaw = gaw; | |
1813 | else | |
1814 | agaw = gaw + 9 - r; | |
1815 | if (agaw > 64) | |
1816 | agaw = 64; | |
1817 | return agaw; | |
1818 | } | |
1819 | ||
dc534b25 JR |
1820 | static int domain_init(struct dmar_domain *domain, struct intel_iommu *iommu, |
1821 | int guest_width) | |
ba395927 | 1822 | { |
ba395927 KA |
1823 | int adjust_width, agaw; |
1824 | unsigned long sagaw; | |
1825 | ||
0fb5fe87 RM |
1826 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
1827 | DMA_32BIT_PFN); | |
ba395927 KA |
1828 | domain_reserve_special_ranges(domain); |
1829 | ||
1830 | /* calculate AGAW */ | |
ba395927 KA |
1831 | if (guest_width > cap_mgaw(iommu->cap)) |
1832 | guest_width = cap_mgaw(iommu->cap); | |
1833 | domain->gaw = guest_width; | |
1834 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1835 | agaw = width_to_agaw(adjust_width); | |
1836 | sagaw = cap_sagaw(iommu->cap); | |
1837 | if (!test_bit(agaw, &sagaw)) { | |
1838 | /* hardware doesn't support it, choose a bigger one */ | |
9f10e5bf | 1839 | pr_debug("Hardware doesn't support agaw %d\n", agaw); |
ba395927 KA |
1840 | agaw = find_next_bit(&sagaw, 5, agaw); |
1841 | if (agaw >= 5) | |
1842 | return -ENODEV; | |
1843 | } | |
1844 | domain->agaw = agaw; | |
ba395927 | 1845 | |
8e604097 WH |
1846 | if (ecap_coherent(iommu->ecap)) |
1847 | domain->iommu_coherency = 1; | |
1848 | else | |
1849 | domain->iommu_coherency = 0; | |
1850 | ||
58c610bd SY |
1851 | if (ecap_sc_support(iommu->ecap)) |
1852 | domain->iommu_snooping = 1; | |
1853 | else | |
1854 | domain->iommu_snooping = 0; | |
1855 | ||
214e39aa DW |
1856 | if (intel_iommu_superpage) |
1857 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); | |
1858 | else | |
1859 | domain->iommu_superpage = 0; | |
1860 | ||
4c923d47 | 1861 | domain->nid = iommu->node; |
c7151a8d | 1862 | |
ba395927 | 1863 | /* always allocate the top pgd */ |
4c923d47 | 1864 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
ba395927 KA |
1865 | if (!domain->pgd) |
1866 | return -ENOMEM; | |
5b6985ce | 1867 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1868 | return 0; |
1869 | } | |
1870 | ||
1871 | static void domain_exit(struct dmar_domain *domain) | |
1872 | { | |
ea8ea460 | 1873 | struct page *freelist = NULL; |
ba395927 KA |
1874 | |
1875 | /* Domain 0 is reserved, so dont process it */ | |
1876 | if (!domain) | |
1877 | return; | |
1878 | ||
7b668357 AW |
1879 | /* Flush any lazy unmaps that may reference this domain */ |
1880 | if (!intel_iommu_strict) | |
1881 | flush_unmaps_timeout(0); | |
1882 | ||
d160aca5 JR |
1883 | /* Remove associated devices and clear attached or cached domains */ |
1884 | rcu_read_lock(); | |
ba395927 | 1885 | domain_remove_dev_info(domain); |
d160aca5 | 1886 | rcu_read_unlock(); |
92d03cc8 | 1887 | |
ba395927 KA |
1888 | /* destroy iovas */ |
1889 | put_iova_domain(&domain->iovad); | |
ba395927 | 1890 | |
ea8ea460 | 1891 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1892 | |
ea8ea460 DW |
1893 | dma_free_pagelist(freelist); |
1894 | ||
ba395927 KA |
1895 | free_domain_mem(domain); |
1896 | } | |
1897 | ||
64ae892b DW |
1898 | static int domain_context_mapping_one(struct dmar_domain *domain, |
1899 | struct intel_iommu *iommu, | |
28ccce0d | 1900 | u8 bus, u8 devfn) |
ba395927 | 1901 | { |
c6c2cebd | 1902 | u16 did = domain->iommu_did[iommu->seq_id]; |
28ccce0d JR |
1903 | int translation = CONTEXT_TT_MULTI_LEVEL; |
1904 | struct device_domain_info *info = NULL; | |
ba395927 | 1905 | struct context_entry *context; |
ba395927 | 1906 | unsigned long flags; |
ea6606b0 | 1907 | struct dma_pte *pgd; |
55d94043 | 1908 | int ret, agaw; |
28ccce0d | 1909 | |
c6c2cebd JR |
1910 | WARN_ON(did == 0); |
1911 | ||
28ccce0d JR |
1912 | if (hw_pass_through && domain_type_is_si(domain)) |
1913 | translation = CONTEXT_TT_PASS_THROUGH; | |
ba395927 KA |
1914 | |
1915 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1916 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1917 | |
ba395927 | 1918 | BUG_ON(!domain->pgd); |
5331fe6f | 1919 | |
55d94043 JR |
1920 | spin_lock_irqsave(&device_domain_lock, flags); |
1921 | spin_lock(&iommu->lock); | |
1922 | ||
1923 | ret = -ENOMEM; | |
03ecc32c | 1924 | context = iommu_context_addr(iommu, bus, devfn, 1); |
ba395927 | 1925 | if (!context) |
55d94043 | 1926 | goto out_unlock; |
ba395927 | 1927 | |
55d94043 JR |
1928 | ret = 0; |
1929 | if (context_present(context)) | |
1930 | goto out_unlock; | |
cf484d0e | 1931 | |
ea6606b0 WH |
1932 | pgd = domain->pgd; |
1933 | ||
de24e553 | 1934 | context_clear_entry(context); |
c6c2cebd | 1935 | context_set_domain_id(context, did); |
ea6606b0 | 1936 | |
de24e553 JR |
1937 | /* |
1938 | * Skip top levels of page tables for iommu which has less agaw | |
1939 | * than default. Unnecessary for PT mode. | |
1940 | */ | |
93a23a72 | 1941 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
de24e553 | 1942 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
55d94043 | 1943 | ret = -ENOMEM; |
de24e553 | 1944 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
55d94043 JR |
1945 | if (!dma_pte_present(pgd)) |
1946 | goto out_unlock; | |
ea6606b0 | 1947 | } |
4ed0d3e6 | 1948 | |
64ae892b | 1949 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
93a23a72 YZ |
1950 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
1951 | CONTEXT_TT_MULTI_LEVEL; | |
de24e553 | 1952 | |
93a23a72 YZ |
1953 | context_set_address_root(context, virt_to_phys(pgd)); |
1954 | context_set_address_width(context, iommu->agaw); | |
de24e553 JR |
1955 | } else { |
1956 | /* | |
1957 | * In pass through mode, AW must be programmed to | |
1958 | * indicate the largest AGAW value supported by | |
1959 | * hardware. And ASR is ignored by hardware. | |
1960 | */ | |
1961 | context_set_address_width(context, iommu->msagaw); | |
93a23a72 | 1962 | } |
4ed0d3e6 FY |
1963 | |
1964 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1965 | context_set_fault_enable(context); |
1966 | context_set_present(context); | |
5331fe6f | 1967 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1968 | |
4c25a2c1 DW |
1969 | /* |
1970 | * It's a non-present to present mapping. If hardware doesn't cache | |
1971 | * non-present entry we only need to flush the write-buffer. If the | |
1972 | * _does_ cache non-present entries, then it does so in the special | |
1973 | * domain #0, which we have to flush: | |
1974 | */ | |
1975 | if (cap_caching_mode(iommu->cap)) { | |
1976 | iommu->flush.flush_context(iommu, 0, | |
1977 | (((u16)bus) << 8) | devfn, | |
1978 | DMA_CCMD_MASK_NOBIT, | |
1979 | DMA_CCMD_DEVICE_INVL); | |
c6c2cebd | 1980 | iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1981 | } else { |
ba395927 | 1982 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1983 | } |
93a23a72 | 1984 | iommu_enable_dev_iotlb(info); |
c7151a8d | 1985 | |
55d94043 JR |
1986 | ret = 0; |
1987 | ||
1988 | out_unlock: | |
1989 | spin_unlock(&iommu->lock); | |
1990 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
fb170fb4 | 1991 | |
ba395927 KA |
1992 | return 0; |
1993 | } | |
1994 | ||
579305f7 AW |
1995 | struct domain_context_mapping_data { |
1996 | struct dmar_domain *domain; | |
1997 | struct intel_iommu *iommu; | |
579305f7 AW |
1998 | }; |
1999 | ||
2000 | static int domain_context_mapping_cb(struct pci_dev *pdev, | |
2001 | u16 alias, void *opaque) | |
2002 | { | |
2003 | struct domain_context_mapping_data *data = opaque; | |
2004 | ||
2005 | return domain_context_mapping_one(data->domain, data->iommu, | |
28ccce0d | 2006 | PCI_BUS_NUM(alias), alias & 0xff); |
579305f7 AW |
2007 | } |
2008 | ||
ba395927 | 2009 | static int |
28ccce0d | 2010 | domain_context_mapping(struct dmar_domain *domain, struct device *dev) |
ba395927 | 2011 | { |
64ae892b | 2012 | struct intel_iommu *iommu; |
156baca8 | 2013 | u8 bus, devfn; |
579305f7 | 2014 | struct domain_context_mapping_data data; |
64ae892b | 2015 | |
e1f167f3 | 2016 | iommu = device_to_iommu(dev, &bus, &devfn); |
64ae892b DW |
2017 | if (!iommu) |
2018 | return -ENODEV; | |
ba395927 | 2019 | |
579305f7 | 2020 | if (!dev_is_pci(dev)) |
28ccce0d | 2021 | return domain_context_mapping_one(domain, iommu, bus, devfn); |
579305f7 AW |
2022 | |
2023 | data.domain = domain; | |
2024 | data.iommu = iommu; | |
579305f7 AW |
2025 | |
2026 | return pci_for_each_dma_alias(to_pci_dev(dev), | |
2027 | &domain_context_mapping_cb, &data); | |
2028 | } | |
2029 | ||
2030 | static int domain_context_mapped_cb(struct pci_dev *pdev, | |
2031 | u16 alias, void *opaque) | |
2032 | { | |
2033 | struct intel_iommu *iommu = opaque; | |
2034 | ||
2035 | return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); | |
ba395927 KA |
2036 | } |
2037 | ||
e1f167f3 | 2038 | static int domain_context_mapped(struct device *dev) |
ba395927 | 2039 | { |
5331fe6f | 2040 | struct intel_iommu *iommu; |
156baca8 | 2041 | u8 bus, devfn; |
5331fe6f | 2042 | |
e1f167f3 | 2043 | iommu = device_to_iommu(dev, &bus, &devfn); |
5331fe6f WH |
2044 | if (!iommu) |
2045 | return -ENODEV; | |
ba395927 | 2046 | |
579305f7 AW |
2047 | if (!dev_is_pci(dev)) |
2048 | return device_context_mapped(iommu, bus, devfn); | |
e1f167f3 | 2049 | |
579305f7 AW |
2050 | return !pci_for_each_dma_alias(to_pci_dev(dev), |
2051 | domain_context_mapped_cb, iommu); | |
ba395927 KA |
2052 | } |
2053 | ||
f532959b FY |
2054 | /* Returns a number of VTD pages, but aligned to MM page size */ |
2055 | static inline unsigned long aligned_nrpages(unsigned long host_addr, | |
2056 | size_t size) | |
2057 | { | |
2058 | host_addr &= ~PAGE_MASK; | |
2059 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; | |
2060 | } | |
2061 | ||
6dd9a7c7 YS |
2062 | /* Return largest possible superpage level for a given mapping */ |
2063 | static inline int hardware_largepage_caps(struct dmar_domain *domain, | |
2064 | unsigned long iov_pfn, | |
2065 | unsigned long phy_pfn, | |
2066 | unsigned long pages) | |
2067 | { | |
2068 | int support, level = 1; | |
2069 | unsigned long pfnmerge; | |
2070 | ||
2071 | support = domain->iommu_superpage; | |
2072 | ||
2073 | /* To use a large page, the virtual *and* physical addresses | |
2074 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either | |
2075 | of them will mean we have to use smaller pages. So just | |
2076 | merge them and check both at once. */ | |
2077 | pfnmerge = iov_pfn | phy_pfn; | |
2078 | ||
2079 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { | |
2080 | pages >>= VTD_STRIDE_SHIFT; | |
2081 | if (!pages) | |
2082 | break; | |
2083 | pfnmerge >>= VTD_STRIDE_SHIFT; | |
2084 | level++; | |
2085 | support--; | |
2086 | } | |
2087 | return level; | |
2088 | } | |
2089 | ||
9051aa02 DW |
2090 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2091 | struct scatterlist *sg, unsigned long phys_pfn, | |
2092 | unsigned long nr_pages, int prot) | |
e1605495 DW |
2093 | { |
2094 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 2095 | phys_addr_t uninitialized_var(pteval); |
cc4f14aa | 2096 | unsigned long sg_res = 0; |
6dd9a7c7 YS |
2097 | unsigned int largepage_lvl = 0; |
2098 | unsigned long lvl_pages = 0; | |
e1605495 | 2099 | |
162d1b10 | 2100 | BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1)); |
e1605495 DW |
2101 | |
2102 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
2103 | return -EINVAL; | |
2104 | ||
2105 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
2106 | ||
cc4f14aa JL |
2107 | if (!sg) { |
2108 | sg_res = nr_pages; | |
9051aa02 DW |
2109 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
2110 | } | |
2111 | ||
6dd9a7c7 | 2112 | while (nr_pages > 0) { |
c85994e4 DW |
2113 | uint64_t tmp; |
2114 | ||
e1605495 | 2115 | if (!sg_res) { |
f532959b | 2116 | sg_res = aligned_nrpages(sg->offset, sg->length); |
e1605495 DW |
2117 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
2118 | sg->dma_length = sg->length; | |
db0fa0cb | 2119 | pteval = (sg_phys(sg) & PAGE_MASK) | prot; |
6dd9a7c7 | 2120 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
e1605495 | 2121 | } |
6dd9a7c7 | 2122 | |
e1605495 | 2123 | if (!pte) { |
6dd9a7c7 YS |
2124 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
2125 | ||
5cf0a76f | 2126 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
e1605495 DW |
2127 | if (!pte) |
2128 | return -ENOMEM; | |
6dd9a7c7 | 2129 | /* It is large page*/ |
6491d4d0 | 2130 | if (largepage_lvl > 1) { |
ba2374fd CZ |
2131 | unsigned long nr_superpages, end_pfn; |
2132 | ||
6dd9a7c7 | 2133 | pteval |= DMA_PTE_LARGE_PAGE; |
d41a4adb | 2134 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
ba2374fd CZ |
2135 | |
2136 | nr_superpages = sg_res / lvl_pages; | |
2137 | end_pfn = iov_pfn + nr_superpages * lvl_pages - 1; | |
2138 | ||
d41a4adb JL |
2139 | /* |
2140 | * Ensure that old small page tables are | |
ba2374fd | 2141 | * removed to make room for superpage(s). |
d41a4adb | 2142 | */ |
ba2374fd | 2143 | dma_pte_free_pagetable(domain, iov_pfn, end_pfn); |
6491d4d0 | 2144 | } else { |
6dd9a7c7 | 2145 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
6491d4d0 | 2146 | } |
6dd9a7c7 | 2147 | |
e1605495 DW |
2148 | } |
2149 | /* We don't need lock here, nobody else | |
2150 | * touches the iova range | |
2151 | */ | |
7766a3fb | 2152 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 2153 | if (tmp) { |
1bf20f0d | 2154 | static int dumps = 5; |
9f10e5bf JR |
2155 | pr_crit("ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
2156 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
2157 | if (dumps) { |
2158 | dumps--; | |
2159 | debug_dma_dump_mappings(NULL); | |
2160 | } | |
2161 | WARN_ON(1); | |
2162 | } | |
6dd9a7c7 YS |
2163 | |
2164 | lvl_pages = lvl_to_nr_pages(largepage_lvl); | |
2165 | ||
2166 | BUG_ON(nr_pages < lvl_pages); | |
2167 | BUG_ON(sg_res < lvl_pages); | |
2168 | ||
2169 | nr_pages -= lvl_pages; | |
2170 | iov_pfn += lvl_pages; | |
2171 | phys_pfn += lvl_pages; | |
2172 | pteval += lvl_pages * VTD_PAGE_SIZE; | |
2173 | sg_res -= lvl_pages; | |
2174 | ||
2175 | /* If the next PTE would be the first in a new page, then we | |
2176 | need to flush the cache on the entries we've just written. | |
2177 | And then we'll need to recalculate 'pte', so clear it and | |
2178 | let it get set again in the if (!pte) block above. | |
2179 | ||
2180 | If we're done (!nr_pages) we need to flush the cache too. | |
2181 | ||
2182 | Also if we've been setting superpages, we may need to | |
2183 | recalculate 'pte' and switch back to smaller pages for the | |
2184 | end of the mapping, if the trailing size is not enough to | |
2185 | use another superpage (i.e. sg_res < lvl_pages). */ | |
e1605495 | 2186 | pte++; |
6dd9a7c7 YS |
2187 | if (!nr_pages || first_pte_in_page(pte) || |
2188 | (largepage_lvl > 1 && sg_res < lvl_pages)) { | |
e1605495 DW |
2189 | domain_flush_cache(domain, first_pte, |
2190 | (void *)pte - (void *)first_pte); | |
2191 | pte = NULL; | |
2192 | } | |
6dd9a7c7 YS |
2193 | |
2194 | if (!sg_res && nr_pages) | |
e1605495 DW |
2195 | sg = sg_next(sg); |
2196 | } | |
2197 | return 0; | |
2198 | } | |
2199 | ||
9051aa02 DW |
2200 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2201 | struct scatterlist *sg, unsigned long nr_pages, | |
2202 | int prot) | |
ba395927 | 2203 | { |
9051aa02 DW |
2204 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
2205 | } | |
6f6a00e4 | 2206 | |
9051aa02 DW |
2207 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2208 | unsigned long phys_pfn, unsigned long nr_pages, | |
2209 | int prot) | |
2210 | { | |
2211 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
2212 | } |
2213 | ||
2452d9db | 2214 | static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 2215 | { |
c7151a8d WH |
2216 | if (!iommu) |
2217 | return; | |
8c11e798 WH |
2218 | |
2219 | clear_context_table(iommu, bus, devfn); | |
2220 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 2221 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2222 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
2223 | } |
2224 | ||
109b9b04 DW |
2225 | static inline void unlink_domain_info(struct device_domain_info *info) |
2226 | { | |
2227 | assert_spin_locked(&device_domain_lock); | |
2228 | list_del(&info->link); | |
2229 | list_del(&info->global); | |
2230 | if (info->dev) | |
0bcb3e28 | 2231 | info->dev->archdata.iommu = NULL; |
109b9b04 DW |
2232 | } |
2233 | ||
ba395927 KA |
2234 | static void domain_remove_dev_info(struct dmar_domain *domain) |
2235 | { | |
3a74ca01 | 2236 | struct device_domain_info *info, *tmp; |
fb170fb4 | 2237 | unsigned long flags; |
ba395927 KA |
2238 | |
2239 | spin_lock_irqsave(&device_domain_lock, flags); | |
76f45fe3 | 2240 | list_for_each_entry_safe(info, tmp, &domain->devices, link) |
127c7615 | 2241 | __dmar_remove_one_dev_info(info); |
ba395927 KA |
2242 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2243 | } | |
2244 | ||
2245 | /* | |
2246 | * find_domain | |
1525a29a | 2247 | * Note: we use struct device->archdata.iommu stores the info |
ba395927 | 2248 | */ |
1525a29a | 2249 | static struct dmar_domain *find_domain(struct device *dev) |
ba395927 KA |
2250 | { |
2251 | struct device_domain_info *info; | |
2252 | ||
2253 | /* No lock here, assumes no domain exit in normal case */ | |
1525a29a | 2254 | info = dev->archdata.iommu; |
ba395927 KA |
2255 | if (info) |
2256 | return info->domain; | |
2257 | return NULL; | |
2258 | } | |
2259 | ||
5a8f40e8 | 2260 | static inline struct device_domain_info * |
745f2586 JL |
2261 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
2262 | { | |
2263 | struct device_domain_info *info; | |
2264 | ||
2265 | list_for_each_entry(info, &device_domain_list, global) | |
41e80dca | 2266 | if (info->iommu->segment == segment && info->bus == bus && |
745f2586 | 2267 | info->devfn == devfn) |
5a8f40e8 | 2268 | return info; |
745f2586 JL |
2269 | |
2270 | return NULL; | |
2271 | } | |
2272 | ||
5db31569 JR |
2273 | static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, |
2274 | int bus, int devfn, | |
2275 | struct device *dev, | |
2276 | struct dmar_domain *domain) | |
745f2586 | 2277 | { |
5a8f40e8 | 2278 | struct dmar_domain *found = NULL; |
745f2586 JL |
2279 | struct device_domain_info *info; |
2280 | unsigned long flags; | |
d160aca5 | 2281 | int ret; |
745f2586 JL |
2282 | |
2283 | info = alloc_devinfo_mem(); | |
2284 | if (!info) | |
b718cd3d | 2285 | return NULL; |
745f2586 | 2286 | |
745f2586 JL |
2287 | info->bus = bus; |
2288 | info->devfn = devfn; | |
fb0cc3aa BH |
2289 | info->ats.enabled = 0; |
2290 | info->ats.qdep = 0; | |
745f2586 JL |
2291 | info->dev = dev; |
2292 | info->domain = domain; | |
5a8f40e8 | 2293 | info->iommu = iommu; |
745f2586 JL |
2294 | |
2295 | spin_lock_irqsave(&device_domain_lock, flags); | |
2296 | if (dev) | |
0bcb3e28 | 2297 | found = find_domain(dev); |
f303e507 JR |
2298 | |
2299 | if (!found) { | |
5a8f40e8 | 2300 | struct device_domain_info *info2; |
41e80dca | 2301 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
f303e507 JR |
2302 | if (info2) { |
2303 | found = info2->domain; | |
2304 | info2->dev = dev; | |
2305 | } | |
5a8f40e8 | 2306 | } |
f303e507 | 2307 | |
745f2586 JL |
2308 | if (found) { |
2309 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2310 | free_devinfo_mem(info); | |
b718cd3d DW |
2311 | /* Caller must free the original domain */ |
2312 | return found; | |
745f2586 JL |
2313 | } |
2314 | ||
d160aca5 JR |
2315 | spin_lock(&iommu->lock); |
2316 | ret = domain_attach_iommu(domain, iommu); | |
2317 | spin_unlock(&iommu->lock); | |
2318 | ||
2319 | if (ret) { | |
c6c2cebd JR |
2320 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2321 | return NULL; | |
2322 | } | |
c6c2cebd | 2323 | |
b718cd3d DW |
2324 | list_add(&info->link, &domain->devices); |
2325 | list_add(&info->global, &device_domain_list); | |
2326 | if (dev) | |
2327 | dev->archdata.iommu = info; | |
2328 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2329 | ||
cc4e2575 JR |
2330 | if (dev && domain_context_mapping(domain, dev)) { |
2331 | pr_err("Domain context map for %s failed\n", dev_name(dev)); | |
e6de0f8d | 2332 | dmar_remove_one_dev_info(domain, dev); |
cc4e2575 JR |
2333 | return NULL; |
2334 | } | |
2335 | ||
b718cd3d | 2336 | return domain; |
745f2586 JL |
2337 | } |
2338 | ||
579305f7 AW |
2339 | static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque) |
2340 | { | |
2341 | *(u16 *)opaque = alias; | |
2342 | return 0; | |
2343 | } | |
2344 | ||
ba395927 | 2345 | /* domain is initialized */ |
146922ec | 2346 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
ba395927 | 2347 | { |
cc4e2575 | 2348 | struct device_domain_info *info = NULL; |
579305f7 AW |
2349 | struct dmar_domain *domain, *tmp; |
2350 | struct intel_iommu *iommu; | |
08a7f456 | 2351 | u16 req_id, dma_alias; |
ba395927 | 2352 | unsigned long flags; |
aa4d066a | 2353 | u8 bus, devfn; |
ba395927 | 2354 | |
146922ec | 2355 | domain = find_domain(dev); |
ba395927 KA |
2356 | if (domain) |
2357 | return domain; | |
2358 | ||
579305f7 AW |
2359 | iommu = device_to_iommu(dev, &bus, &devfn); |
2360 | if (!iommu) | |
2361 | return NULL; | |
2362 | ||
08a7f456 JR |
2363 | req_id = ((u16)bus << 8) | devfn; |
2364 | ||
146922ec DW |
2365 | if (dev_is_pci(dev)) { |
2366 | struct pci_dev *pdev = to_pci_dev(dev); | |
276dbf99 | 2367 | |
579305f7 AW |
2368 | pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias); |
2369 | ||
2370 | spin_lock_irqsave(&device_domain_lock, flags); | |
2371 | info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus), | |
2372 | PCI_BUS_NUM(dma_alias), | |
2373 | dma_alias & 0xff); | |
2374 | if (info) { | |
2375 | iommu = info->iommu; | |
2376 | domain = info->domain; | |
5a8f40e8 | 2377 | } |
579305f7 | 2378 | spin_unlock_irqrestore(&device_domain_lock, flags); |
ba395927 | 2379 | |
579305f7 AW |
2380 | /* DMA alias already has a domain, uses it */ |
2381 | if (info) | |
2382 | goto found_domain; | |
2383 | } | |
ba395927 | 2384 | |
146922ec | 2385 | /* Allocate and initialize new domain for the device */ |
ab8dfe25 | 2386 | domain = alloc_domain(0); |
745f2586 | 2387 | if (!domain) |
579305f7 | 2388 | return NULL; |
dc534b25 | 2389 | if (domain_init(domain, iommu, gaw)) { |
579305f7 AW |
2390 | domain_exit(domain); |
2391 | return NULL; | |
2c2e2c38 | 2392 | } |
ba395927 | 2393 | |
579305f7 | 2394 | /* register PCI DMA alias device */ |
08a7f456 | 2395 | if (req_id != dma_alias && dev_is_pci(dev)) { |
5db31569 JR |
2396 | tmp = dmar_insert_one_dev_info(iommu, PCI_BUS_NUM(dma_alias), |
2397 | dma_alias & 0xff, NULL, domain); | |
579305f7 AW |
2398 | |
2399 | if (!tmp || tmp != domain) { | |
2400 | domain_exit(domain); | |
2401 | domain = tmp; | |
2402 | } | |
2403 | ||
b718cd3d | 2404 | if (!domain) |
579305f7 | 2405 | return NULL; |
ba395927 KA |
2406 | } |
2407 | ||
2408 | found_domain: | |
5db31569 | 2409 | tmp = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
579305f7 AW |
2410 | |
2411 | if (!tmp || tmp != domain) { | |
2412 | domain_exit(domain); | |
2413 | domain = tmp; | |
2414 | } | |
b718cd3d DW |
2415 | |
2416 | return domain; | |
ba395927 KA |
2417 | } |
2418 | ||
b213203e DW |
2419 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
2420 | unsigned long long start, | |
2421 | unsigned long long end) | |
ba395927 | 2422 | { |
c5395d5c DW |
2423 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
2424 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
2425 | ||
2426 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
2427 | dma_to_mm_pfn(last_vpfn))) { | |
9f10e5bf | 2428 | pr_err("Reserving iova failed\n"); |
b213203e | 2429 | return -ENOMEM; |
ba395927 KA |
2430 | } |
2431 | ||
af1089ce | 2432 | pr_debug("Mapping reserved region %llx-%llx\n", start, end); |
ba395927 KA |
2433 | /* |
2434 | * RMRR range might have overlap with physical memory range, | |
2435 | * clear it first | |
2436 | */ | |
c5395d5c | 2437 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 2438 | |
c5395d5c DW |
2439 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
2440 | last_vpfn - first_vpfn + 1, | |
61df7443 | 2441 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
2442 | } |
2443 | ||
0b9d9753 | 2444 | static int iommu_prepare_identity_map(struct device *dev, |
b213203e DW |
2445 | unsigned long long start, |
2446 | unsigned long long end) | |
2447 | { | |
2448 | struct dmar_domain *domain; | |
2449 | int ret; | |
2450 | ||
0b9d9753 | 2451 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
2452 | if (!domain) |
2453 | return -ENOMEM; | |
2454 | ||
19943b0e DW |
2455 | /* For _hardware_ passthrough, don't bother. But for software |
2456 | passthrough, we do it anyway -- it may indicate a memory | |
2457 | range which is reserved in E820, so which didn't get set | |
2458 | up to start with in si_domain */ | |
2459 | if (domain == si_domain && hw_pass_through) { | |
9f10e5bf JR |
2460 | pr_warn("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", |
2461 | dev_name(dev), start, end); | |
19943b0e DW |
2462 | return 0; |
2463 | } | |
2464 | ||
9f10e5bf JR |
2465 | pr_info("Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
2466 | dev_name(dev), start, end); | |
2467 | ||
5595b528 DW |
2468 | if (end < start) { |
2469 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" | |
2470 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2471 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2472 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2473 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2474 | ret = -EIO; | |
2475 | goto error; | |
2476 | } | |
2477 | ||
2ff729f5 DW |
2478 | if (end >> agaw_to_width(domain->agaw)) { |
2479 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" | |
2480 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2481 | agaw_to_width(domain->agaw), | |
2482 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2483 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2484 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2485 | ret = -EIO; | |
2486 | goto error; | |
2487 | } | |
19943b0e | 2488 | |
b213203e | 2489 | ret = iommu_domain_identity_map(domain, start, end); |
ba395927 KA |
2490 | if (ret) |
2491 | goto error; | |
2492 | ||
b213203e DW |
2493 | return 0; |
2494 | ||
2495 | error: | |
ba395927 KA |
2496 | domain_exit(domain); |
2497 | return ret; | |
ba395927 KA |
2498 | } |
2499 | ||
2500 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
0b9d9753 | 2501 | struct device *dev) |
ba395927 | 2502 | { |
0b9d9753 | 2503 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 | 2504 | return 0; |
0b9d9753 DW |
2505 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
2506 | rmrr->end_address); | |
ba395927 KA |
2507 | } |
2508 | ||
d3f13810 | 2509 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
49a0429e KA |
2510 | static inline void iommu_prepare_isa(void) |
2511 | { | |
2512 | struct pci_dev *pdev; | |
2513 | int ret; | |
2514 | ||
2515 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
2516 | if (!pdev) | |
2517 | return; | |
2518 | ||
9f10e5bf | 2519 | pr_info("Prepare 0-16MiB unity mapping for LPC\n"); |
0b9d9753 | 2520 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
49a0429e KA |
2521 | |
2522 | if (ret) | |
9f10e5bf | 2523 | pr_err("Failed to create 0-16MiB identity map - floppy might not work\n"); |
49a0429e | 2524 | |
9b27e82d | 2525 | pci_dev_put(pdev); |
49a0429e KA |
2526 | } |
2527 | #else | |
2528 | static inline void iommu_prepare_isa(void) | |
2529 | { | |
2530 | return; | |
2531 | } | |
d3f13810 | 2532 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
49a0429e | 2533 | |
2c2e2c38 | 2534 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 | 2535 | |
071e1374 | 2536 | static int __init si_domain_init(int hw) |
2c2e2c38 | 2537 | { |
c7ab48d2 | 2538 | int nid, ret = 0; |
2c2e2c38 | 2539 | |
ab8dfe25 | 2540 | si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY); |
2c2e2c38 FY |
2541 | if (!si_domain) |
2542 | return -EFAULT; | |
2543 | ||
2c2e2c38 FY |
2544 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
2545 | domain_exit(si_domain); | |
2546 | return -EFAULT; | |
2547 | } | |
2548 | ||
0dc79715 | 2549 | pr_debug("Identity mapping domain allocated\n"); |
2c2e2c38 | 2550 | |
19943b0e DW |
2551 | if (hw) |
2552 | return 0; | |
2553 | ||
c7ab48d2 | 2554 | for_each_online_node(nid) { |
5dfe8660 TH |
2555 | unsigned long start_pfn, end_pfn; |
2556 | int i; | |
2557 | ||
2558 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { | |
2559 | ret = iommu_domain_identity_map(si_domain, | |
2560 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); | |
2561 | if (ret) | |
2562 | return ret; | |
2563 | } | |
c7ab48d2 DW |
2564 | } |
2565 | ||
2c2e2c38 FY |
2566 | return 0; |
2567 | } | |
2568 | ||
9b226624 | 2569 | static int identity_mapping(struct device *dev) |
2c2e2c38 FY |
2570 | { |
2571 | struct device_domain_info *info; | |
2572 | ||
2573 | if (likely(!iommu_identity_mapping)) | |
2574 | return 0; | |
2575 | ||
9b226624 | 2576 | info = dev->archdata.iommu; |
cb452a40 MT |
2577 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
2578 | return (info->domain == si_domain); | |
2c2e2c38 | 2579 | |
2c2e2c38 FY |
2580 | return 0; |
2581 | } | |
2582 | ||
28ccce0d | 2583 | static int domain_add_dev_info(struct dmar_domain *domain, struct device *dev) |
2c2e2c38 | 2584 | { |
0ac72664 | 2585 | struct dmar_domain *ndomain; |
5a8f40e8 | 2586 | struct intel_iommu *iommu; |
156baca8 | 2587 | u8 bus, devfn; |
2c2e2c38 | 2588 | |
5913c9bf | 2589 | iommu = device_to_iommu(dev, &bus, &devfn); |
5a8f40e8 DW |
2590 | if (!iommu) |
2591 | return -ENODEV; | |
2592 | ||
5db31569 | 2593 | ndomain = dmar_insert_one_dev_info(iommu, bus, devfn, dev, domain); |
0ac72664 DW |
2594 | if (ndomain != domain) |
2595 | return -EBUSY; | |
2c2e2c38 FY |
2596 | |
2597 | return 0; | |
2598 | } | |
2599 | ||
0b9d9753 | 2600 | static bool device_has_rmrr(struct device *dev) |
ea2447f7 TM |
2601 | { |
2602 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2603 | struct device *tmp; |
ea2447f7 TM |
2604 | int i; |
2605 | ||
0e242612 | 2606 | rcu_read_lock(); |
ea2447f7 | 2607 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
2608 | /* |
2609 | * Return TRUE if this RMRR contains the device that | |
2610 | * is passed in. | |
2611 | */ | |
2612 | for_each_active_dev_scope(rmrr->devices, | |
2613 | rmrr->devices_cnt, i, tmp) | |
0b9d9753 | 2614 | if (tmp == dev) { |
0e242612 | 2615 | rcu_read_unlock(); |
ea2447f7 | 2616 | return true; |
b683b230 | 2617 | } |
ea2447f7 | 2618 | } |
0e242612 | 2619 | rcu_read_unlock(); |
ea2447f7 TM |
2620 | return false; |
2621 | } | |
2622 | ||
c875d2c1 AW |
2623 | /* |
2624 | * There are a couple cases where we need to restrict the functionality of | |
2625 | * devices associated with RMRRs. The first is when evaluating a device for | |
2626 | * identity mapping because problems exist when devices are moved in and out | |
2627 | * of domains and their respective RMRR information is lost. This means that | |
2628 | * a device with associated RMRRs will never be in a "passthrough" domain. | |
2629 | * The second is use of the device through the IOMMU API. This interface | |
2630 | * expects to have full control of the IOVA space for the device. We cannot | |
2631 | * satisfy both the requirement that RMRR access is maintained and have an | |
2632 | * unencumbered IOVA space. We also have no ability to quiesce the device's | |
2633 | * use of the RMRR space or even inform the IOMMU API user of the restriction. | |
2634 | * We therefore prevent devices associated with an RMRR from participating in | |
2635 | * the IOMMU API, which eliminates them from device assignment. | |
2636 | * | |
2637 | * In both cases we assume that PCI USB devices with RMRRs have them largely | |
2638 | * for historical reasons and that the RMRR space is not actively used post | |
2639 | * boot. This exclusion may change if vendors begin to abuse it. | |
18436afd DW |
2640 | * |
2641 | * The same exception is made for graphics devices, with the requirement that | |
2642 | * any use of the RMRR regions will be torn down before assigning the device | |
2643 | * to a guest. | |
c875d2c1 AW |
2644 | */ |
2645 | static bool device_is_rmrr_locked(struct device *dev) | |
2646 | { | |
2647 | if (!device_has_rmrr(dev)) | |
2648 | return false; | |
2649 | ||
2650 | if (dev_is_pci(dev)) { | |
2651 | struct pci_dev *pdev = to_pci_dev(dev); | |
2652 | ||
18436afd | 2653 | if (IS_USB_DEVICE(pdev) || IS_GFX_DEVICE(pdev)) |
c875d2c1 AW |
2654 | return false; |
2655 | } | |
2656 | ||
2657 | return true; | |
2658 | } | |
2659 | ||
3bdb2591 | 2660 | static int iommu_should_identity_map(struct device *dev, int startup) |
6941af28 | 2661 | { |
ea2447f7 | 2662 | |
3bdb2591 DW |
2663 | if (dev_is_pci(dev)) { |
2664 | struct pci_dev *pdev = to_pci_dev(dev); | |
ea2447f7 | 2665 | |
c875d2c1 | 2666 | if (device_is_rmrr_locked(dev)) |
3bdb2591 | 2667 | return 0; |
e0fc7e0b | 2668 | |
3bdb2591 DW |
2669 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
2670 | return 1; | |
e0fc7e0b | 2671 | |
3bdb2591 DW |
2672 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
2673 | return 1; | |
6941af28 | 2674 | |
3bdb2591 | 2675 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
3dfc813d | 2676 | return 0; |
3bdb2591 DW |
2677 | |
2678 | /* | |
2679 | * We want to start off with all devices in the 1:1 domain, and | |
2680 | * take them out later if we find they can't access all of memory. | |
2681 | * | |
2682 | * However, we can't do this for PCI devices behind bridges, | |
2683 | * because all PCI devices behind the same bridge will end up | |
2684 | * with the same source-id on their transactions. | |
2685 | * | |
2686 | * Practically speaking, we can't change things around for these | |
2687 | * devices at run-time, because we can't be sure there'll be no | |
2688 | * DMA transactions in flight for any of their siblings. | |
2689 | * | |
2690 | * So PCI devices (unless they're on the root bus) as well as | |
2691 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of | |
2692 | * the 1:1 domain, just in _case_ one of their siblings turns out | |
2693 | * not to be able to map all of memory. | |
2694 | */ | |
2695 | if (!pci_is_pcie(pdev)) { | |
2696 | if (!pci_is_root_bus(pdev->bus)) | |
2697 | return 0; | |
2698 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) | |
2699 | return 0; | |
2700 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) | |
3dfc813d | 2701 | return 0; |
3bdb2591 DW |
2702 | } else { |
2703 | if (device_has_rmrr(dev)) | |
2704 | return 0; | |
2705 | } | |
3dfc813d | 2706 | |
3bdb2591 | 2707 | /* |
3dfc813d | 2708 | * At boot time, we don't yet know if devices will be 64-bit capable. |
3bdb2591 | 2709 | * Assume that they will — if they turn out not to be, then we can |
3dfc813d DW |
2710 | * take them out of the 1:1 domain later. |
2711 | */ | |
8fcc5372 CW |
2712 | if (!startup) { |
2713 | /* | |
2714 | * If the device's dma_mask is less than the system's memory | |
2715 | * size then this is not a candidate for identity mapping. | |
2716 | */ | |
3bdb2591 | 2717 | u64 dma_mask = *dev->dma_mask; |
8fcc5372 | 2718 | |
3bdb2591 DW |
2719 | if (dev->coherent_dma_mask && |
2720 | dev->coherent_dma_mask < dma_mask) | |
2721 | dma_mask = dev->coherent_dma_mask; | |
8fcc5372 | 2722 | |
3bdb2591 | 2723 | return dma_mask >= dma_get_required_mask(dev); |
8fcc5372 | 2724 | } |
6941af28 DW |
2725 | |
2726 | return 1; | |
2727 | } | |
2728 | ||
cf04eee8 DW |
2729 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
2730 | { | |
2731 | int ret; | |
2732 | ||
2733 | if (!iommu_should_identity_map(dev, 1)) | |
2734 | return 0; | |
2735 | ||
28ccce0d | 2736 | ret = domain_add_dev_info(si_domain, dev); |
cf04eee8 | 2737 | if (!ret) |
9f10e5bf JR |
2738 | pr_info("%s identity mapping for device %s\n", |
2739 | hw ? "Hardware" : "Software", dev_name(dev)); | |
cf04eee8 DW |
2740 | else if (ret == -ENODEV) |
2741 | /* device not associated with an iommu */ | |
2742 | ret = 0; | |
2743 | ||
2744 | return ret; | |
2745 | } | |
2746 | ||
2747 | ||
071e1374 | 2748 | static int __init iommu_prepare_static_identity_mapping(int hw) |
2c2e2c38 | 2749 | { |
2c2e2c38 | 2750 | struct pci_dev *pdev = NULL; |
cf04eee8 DW |
2751 | struct dmar_drhd_unit *drhd; |
2752 | struct intel_iommu *iommu; | |
2753 | struct device *dev; | |
2754 | int i; | |
2755 | int ret = 0; | |
2c2e2c38 | 2756 | |
2c2e2c38 | 2757 | for_each_pci_dev(pdev) { |
cf04eee8 DW |
2758 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
2759 | if (ret) | |
2760 | return ret; | |
2761 | } | |
2762 | ||
2763 | for_each_active_iommu(iommu, drhd) | |
2764 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { | |
2765 | struct acpi_device_physical_node *pn; | |
2766 | struct acpi_device *adev; | |
2767 | ||
2768 | if (dev->bus != &acpi_bus_type) | |
2769 | continue; | |
86080ccc | 2770 | |
cf04eee8 DW |
2771 | adev= to_acpi_device(dev); |
2772 | mutex_lock(&adev->physical_node_lock); | |
2773 | list_for_each_entry(pn, &adev->physical_node_list, node) { | |
2774 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); | |
2775 | if (ret) | |
2776 | break; | |
eae460b6 | 2777 | } |
cf04eee8 DW |
2778 | mutex_unlock(&adev->physical_node_lock); |
2779 | if (ret) | |
2780 | return ret; | |
62edf5dc | 2781 | } |
2c2e2c38 FY |
2782 | |
2783 | return 0; | |
2784 | } | |
2785 | ||
ffebeb46 JL |
2786 | static void intel_iommu_init_qi(struct intel_iommu *iommu) |
2787 | { | |
2788 | /* | |
2789 | * Start from the sane iommu hardware state. | |
2790 | * If the queued invalidation is already initialized by us | |
2791 | * (for example, while enabling interrupt-remapping) then | |
2792 | * we got the things already rolling from a sane state. | |
2793 | */ | |
2794 | if (!iommu->qi) { | |
2795 | /* | |
2796 | * Clear any previous faults. | |
2797 | */ | |
2798 | dmar_fault(-1, iommu); | |
2799 | /* | |
2800 | * Disable queued invalidation if supported and already enabled | |
2801 | * before OS handover. | |
2802 | */ | |
2803 | dmar_disable_qi(iommu); | |
2804 | } | |
2805 | ||
2806 | if (dmar_enable_qi(iommu)) { | |
2807 | /* | |
2808 | * Queued Invalidate not enabled, use Register Based Invalidate | |
2809 | */ | |
2810 | iommu->flush.flush_context = __iommu_flush_context; | |
2811 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
9f10e5bf | 2812 | pr_info("%s: Using Register based invalidation\n", |
ffebeb46 JL |
2813 | iommu->name); |
2814 | } else { | |
2815 | iommu->flush.flush_context = qi_flush_context; | |
2816 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
9f10e5bf | 2817 | pr_info("%s: Using Queued invalidation\n", iommu->name); |
ffebeb46 JL |
2818 | } |
2819 | } | |
2820 | ||
091d42e4 | 2821 | static int copy_context_table(struct intel_iommu *iommu, |
543c8dcf | 2822 | struct root_entry __iomem *old_re, |
091d42e4 JR |
2823 | struct context_entry **tbl, |
2824 | int bus, bool ext) | |
2825 | { | |
dbcd861f | 2826 | int tbl_idx, pos = 0, idx, devfn, ret = 0, did; |
543c8dcf JR |
2827 | struct context_entry __iomem *old_ce = NULL; |
2828 | struct context_entry *new_ce = NULL, ce; | |
2829 | struct root_entry re; | |
091d42e4 JR |
2830 | phys_addr_t old_ce_phys; |
2831 | ||
2832 | tbl_idx = ext ? bus * 2 : bus; | |
543c8dcf | 2833 | memcpy_fromio(&re, old_re, sizeof(re)); |
091d42e4 JR |
2834 | |
2835 | for (devfn = 0; devfn < 256; devfn++) { | |
2836 | /* First calculate the correct index */ | |
2837 | idx = (ext ? devfn * 2 : devfn) % 256; | |
2838 | ||
2839 | if (idx == 0) { | |
2840 | /* First save what we may have and clean up */ | |
2841 | if (new_ce) { | |
2842 | tbl[tbl_idx] = new_ce; | |
2843 | __iommu_flush_cache(iommu, new_ce, | |
2844 | VTD_PAGE_SIZE); | |
2845 | pos = 1; | |
2846 | } | |
2847 | ||
2848 | if (old_ce) | |
2849 | iounmap(old_ce); | |
2850 | ||
2851 | ret = 0; | |
2852 | if (devfn < 0x80) | |
543c8dcf | 2853 | old_ce_phys = root_entry_lctp(&re); |
091d42e4 | 2854 | else |
543c8dcf | 2855 | old_ce_phys = root_entry_uctp(&re); |
091d42e4 JR |
2856 | |
2857 | if (!old_ce_phys) { | |
2858 | if (ext && devfn == 0) { | |
2859 | /* No LCTP, try UCTP */ | |
2860 | devfn = 0x7f; | |
2861 | continue; | |
2862 | } else { | |
2863 | goto out; | |
2864 | } | |
2865 | } | |
2866 | ||
2867 | ret = -ENOMEM; | |
2868 | old_ce = ioremap_cache(old_ce_phys, PAGE_SIZE); | |
2869 | if (!old_ce) | |
2870 | goto out; | |
2871 | ||
2872 | new_ce = alloc_pgtable_page(iommu->node); | |
2873 | if (!new_ce) | |
2874 | goto out_unmap; | |
2875 | ||
2876 | ret = 0; | |
2877 | } | |
2878 | ||
2879 | /* Now copy the context entry */ | |
543c8dcf | 2880 | memcpy_fromio(&ce, old_ce + idx, sizeof(ce)); |
091d42e4 | 2881 | |
cf484d0e | 2882 | if (!__context_present(&ce)) |
091d42e4 JR |
2883 | continue; |
2884 | ||
dbcd861f JR |
2885 | did = context_domain_id(&ce); |
2886 | if (did >= 0 && did < cap_ndoms(iommu->cap)) | |
2887 | set_bit(did, iommu->domain_ids); | |
2888 | ||
cf484d0e JR |
2889 | /* |
2890 | * We need a marker for copied context entries. This | |
2891 | * marker needs to work for the old format as well as | |
2892 | * for extended context entries. | |
2893 | * | |
2894 | * Bit 67 of the context entry is used. In the old | |
2895 | * format this bit is available to software, in the | |
2896 | * extended format it is the PGE bit, but PGE is ignored | |
2897 | * by HW if PASIDs are disabled (and thus still | |
2898 | * available). | |
2899 | * | |
2900 | * So disable PASIDs first and then mark the entry | |
2901 | * copied. This means that we don't copy PASID | |
2902 | * translations from the old kernel, but this is fine as | |
2903 | * faults there are not fatal. | |
2904 | */ | |
2905 | context_clear_pasid_enable(&ce); | |
2906 | context_set_copied(&ce); | |
2907 | ||
091d42e4 JR |
2908 | new_ce[idx] = ce; |
2909 | } | |
2910 | ||
2911 | tbl[tbl_idx + pos] = new_ce; | |
2912 | ||
2913 | __iommu_flush_cache(iommu, new_ce, VTD_PAGE_SIZE); | |
2914 | ||
2915 | out_unmap: | |
2916 | iounmap(old_ce); | |
2917 | ||
2918 | out: | |
2919 | return ret; | |
2920 | } | |
2921 | ||
2922 | static int copy_translation_tables(struct intel_iommu *iommu) | |
2923 | { | |
543c8dcf | 2924 | struct root_entry __iomem *old_rt; |
091d42e4 | 2925 | struct context_entry **ctxt_tbls; |
091d42e4 JR |
2926 | phys_addr_t old_rt_phys; |
2927 | int ctxt_table_entries; | |
2928 | unsigned long flags; | |
2929 | u64 rtaddr_reg; | |
2930 | int bus, ret; | |
c3361f2f | 2931 | bool new_ext, ext; |
091d42e4 JR |
2932 | |
2933 | rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG); | |
2934 | ext = !!(rtaddr_reg & DMA_RTADDR_RTT); | |
c3361f2f JR |
2935 | new_ext = !!ecap_ecs(iommu->ecap); |
2936 | ||
2937 | /* | |
2938 | * The RTT bit can only be changed when translation is disabled, | |
2939 | * but disabling translation means to open a window for data | |
2940 | * corruption. So bail out and don't copy anything if we would | |
2941 | * have to change the bit. | |
2942 | */ | |
2943 | if (new_ext != ext) | |
2944 | return -EINVAL; | |
091d42e4 JR |
2945 | |
2946 | old_rt_phys = rtaddr_reg & VTD_PAGE_MASK; | |
2947 | if (!old_rt_phys) | |
2948 | return -EINVAL; | |
2949 | ||
2950 | old_rt = ioremap_cache(old_rt_phys, PAGE_SIZE); | |
2951 | if (!old_rt) | |
2952 | return -ENOMEM; | |
2953 | ||
2954 | /* This is too big for the stack - allocate it from slab */ | |
2955 | ctxt_table_entries = ext ? 512 : 256; | |
2956 | ret = -ENOMEM; | |
2957 | ctxt_tbls = kzalloc(ctxt_table_entries * sizeof(void *), GFP_KERNEL); | |
2958 | if (!ctxt_tbls) | |
2959 | goto out_unmap; | |
2960 | ||
2961 | for (bus = 0; bus < 256; bus++) { | |
2962 | ret = copy_context_table(iommu, &old_rt[bus], | |
2963 | ctxt_tbls, bus, ext); | |
2964 | if (ret) { | |
2965 | pr_err("%s: Failed to copy context table for bus %d\n", | |
2966 | iommu->name, bus); | |
2967 | continue; | |
2968 | } | |
2969 | } | |
2970 | ||
2971 | spin_lock_irqsave(&iommu->lock, flags); | |
2972 | ||
2973 | /* Context tables are copied, now write them to the root_entry table */ | |
2974 | for (bus = 0; bus < 256; bus++) { | |
2975 | int idx = ext ? bus * 2 : bus; | |
2976 | u64 val; | |
2977 | ||
2978 | if (ctxt_tbls[idx]) { | |
2979 | val = virt_to_phys(ctxt_tbls[idx]) | 1; | |
2980 | iommu->root_entry[bus].lo = val; | |
2981 | } | |
2982 | ||
2983 | if (!ext || !ctxt_tbls[idx + 1]) | |
2984 | continue; | |
2985 | ||
2986 | val = virt_to_phys(ctxt_tbls[idx + 1]) | 1; | |
2987 | iommu->root_entry[bus].hi = val; | |
2988 | } | |
2989 | ||
2990 | spin_unlock_irqrestore(&iommu->lock, flags); | |
2991 | ||
2992 | kfree(ctxt_tbls); | |
2993 | ||
2994 | __iommu_flush_cache(iommu, iommu->root_entry, PAGE_SIZE); | |
2995 | ||
2996 | ret = 0; | |
2997 | ||
2998 | out_unmap: | |
2999 | iounmap(old_rt); | |
3000 | ||
3001 | return ret; | |
3002 | } | |
3003 | ||
b779260b | 3004 | static int __init init_dmars(void) |
ba395927 KA |
3005 | { |
3006 | struct dmar_drhd_unit *drhd; | |
3007 | struct dmar_rmrr_unit *rmrr; | |
a87f4918 | 3008 | bool copied_tables = false; |
832bd858 | 3009 | struct device *dev; |
ba395927 | 3010 | struct intel_iommu *iommu; |
9d783ba0 | 3011 | int i, ret; |
2c2e2c38 | 3012 | |
ba395927 KA |
3013 | /* |
3014 | * for each drhd | |
3015 | * allocate root | |
3016 | * initialize and program root entry to not present | |
3017 | * endfor | |
3018 | */ | |
3019 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 3020 | /* |
3021 | * lock not needed as this is only incremented in the single | |
3022 | * threaded kernel __init code path all other access are read | |
3023 | * only | |
3024 | */ | |
78d8e704 | 3025 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { |
1b198bb0 MT |
3026 | g_num_of_iommus++; |
3027 | continue; | |
3028 | } | |
9f10e5bf | 3029 | pr_err_once("Exceeded %d IOMMUs\n", DMAR_UNITS_SUPPORTED); |
5e0d2a6f | 3030 | } |
3031 | ||
ffebeb46 JL |
3032 | /* Preallocate enough resources for IOMMU hot-addition */ |
3033 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) | |
3034 | g_num_of_iommus = DMAR_UNITS_SUPPORTED; | |
3035 | ||
d9630fe9 WH |
3036 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
3037 | GFP_KERNEL); | |
3038 | if (!g_iommus) { | |
9f10e5bf | 3039 | pr_err("Allocating global iommu array failed\n"); |
d9630fe9 WH |
3040 | ret = -ENOMEM; |
3041 | goto error; | |
3042 | } | |
3043 | ||
80b20dd8 | 3044 | deferred_flush = kzalloc(g_num_of_iommus * |
3045 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
3046 | if (!deferred_flush) { | |
5e0d2a6f | 3047 | ret = -ENOMEM; |
989d51fc | 3048 | goto free_g_iommus; |
5e0d2a6f | 3049 | } |
3050 | ||
7c919779 | 3051 | for_each_active_iommu(iommu, drhd) { |
d9630fe9 | 3052 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 3053 | |
b63d80d1 JR |
3054 | intel_iommu_init_qi(iommu); |
3055 | ||
e61d98d8 SS |
3056 | ret = iommu_init_domains(iommu); |
3057 | if (ret) | |
989d51fc | 3058 | goto free_iommu; |
e61d98d8 | 3059 | |
4158c2ec JR |
3060 | init_translation_status(iommu); |
3061 | ||
091d42e4 JR |
3062 | if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { |
3063 | iommu_disable_translation(iommu); | |
3064 | clear_translation_pre_enabled(iommu); | |
3065 | pr_warn("Translation was enabled for %s but we are not in kdump mode\n", | |
3066 | iommu->name); | |
3067 | } | |
4158c2ec | 3068 | |
ba395927 KA |
3069 | /* |
3070 | * TBD: | |
3071 | * we could share the same root & context tables | |
25985edc | 3072 | * among all IOMMU's. Need to Split it later. |
ba395927 KA |
3073 | */ |
3074 | ret = iommu_alloc_root_entry(iommu); | |
ffebeb46 | 3075 | if (ret) |
989d51fc | 3076 | goto free_iommu; |
5f0a7f76 | 3077 | |
091d42e4 JR |
3078 | if (translation_pre_enabled(iommu)) { |
3079 | pr_info("Translation already enabled - trying to copy translation structures\n"); | |
3080 | ||
3081 | ret = copy_translation_tables(iommu); | |
3082 | if (ret) { | |
3083 | /* | |
3084 | * We found the IOMMU with translation | |
3085 | * enabled - but failed to copy over the | |
3086 | * old root-entry table. Try to proceed | |
3087 | * by disabling translation now and | |
3088 | * allocating a clean root-entry table. | |
3089 | * This might cause DMAR faults, but | |
3090 | * probably the dump will still succeed. | |
3091 | */ | |
3092 | pr_err("Failed to copy translation tables from previous kernel for %s\n", | |
3093 | iommu->name); | |
3094 | iommu_disable_translation(iommu); | |
3095 | clear_translation_pre_enabled(iommu); | |
3096 | } else { | |
3097 | pr_info("Copied translation tables from previous kernel for %s\n", | |
3098 | iommu->name); | |
a87f4918 | 3099 | copied_tables = true; |
091d42e4 JR |
3100 | } |
3101 | } | |
3102 | ||
5f0a7f76 JR |
3103 | iommu_flush_write_buffer(iommu); |
3104 | iommu_set_root_entry(iommu); | |
3105 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); | |
3106 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); | |
3107 | ||
4ed0d3e6 | 3108 | if (!ecap_pass_through(iommu->ecap)) |
19943b0e | 3109 | hw_pass_through = 0; |
ba395927 KA |
3110 | } |
3111 | ||
19943b0e | 3112 | if (iommu_pass_through) |
e0fc7e0b DW |
3113 | iommu_identity_mapping |= IDENTMAP_ALL; |
3114 | ||
d3f13810 | 3115 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
e0fc7e0b | 3116 | iommu_identity_mapping |= IDENTMAP_GFX; |
19943b0e | 3117 | #endif |
e0fc7e0b | 3118 | |
86080ccc JR |
3119 | if (iommu_identity_mapping) { |
3120 | ret = si_domain_init(hw_pass_through); | |
3121 | if (ret) | |
3122 | goto free_iommu; | |
3123 | } | |
3124 | ||
e0fc7e0b DW |
3125 | check_tylersburg_isoch(); |
3126 | ||
a87f4918 JR |
3127 | /* |
3128 | * If we copied translations from a previous kernel in the kdump | |
3129 | * case, we can not assign the devices to domains now, as that | |
3130 | * would eliminate the old mappings. So skip this part and defer | |
3131 | * the assignment to device driver initialization time. | |
3132 | */ | |
3133 | if (copied_tables) | |
3134 | goto domains_done; | |
3135 | ||
ba395927 | 3136 | /* |
19943b0e DW |
3137 | * If pass through is not set or not enabled, setup context entries for |
3138 | * identity mappings for rmrr, gfx, and isa and may fall back to static | |
3139 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 3140 | */ |
19943b0e DW |
3141 | if (iommu_identity_mapping) { |
3142 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); | |
4ed0d3e6 | 3143 | if (ret) { |
9f10e5bf | 3144 | pr_crit("Failed to setup IOMMU pass-through\n"); |
989d51fc | 3145 | goto free_iommu; |
ba395927 KA |
3146 | } |
3147 | } | |
ba395927 | 3148 | /* |
19943b0e DW |
3149 | * For each rmrr |
3150 | * for each dev attached to rmrr | |
3151 | * do | |
3152 | * locate drhd for dev, alloc domain for dev | |
3153 | * allocate free domain | |
3154 | * allocate page table entries for rmrr | |
3155 | * if context not allocated for bus | |
3156 | * allocate and init context | |
3157 | * set present in root table for this bus | |
3158 | * init context with domain, translation etc | |
3159 | * endfor | |
3160 | * endfor | |
ba395927 | 3161 | */ |
9f10e5bf | 3162 | pr_info("Setting RMRR:\n"); |
19943b0e | 3163 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
3164 | /* some BIOS lists non-exist devices in DMAR table. */ |
3165 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, | |
832bd858 | 3166 | i, dev) { |
0b9d9753 | 3167 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
19943b0e | 3168 | if (ret) |
9f10e5bf | 3169 | pr_err("Mapping reserved region failed\n"); |
ba395927 | 3170 | } |
4ed0d3e6 | 3171 | } |
49a0429e | 3172 | |
19943b0e DW |
3173 | iommu_prepare_isa(); |
3174 | ||
a87f4918 JR |
3175 | domains_done: |
3176 | ||
ba395927 KA |
3177 | /* |
3178 | * for each drhd | |
3179 | * enable fault log | |
3180 | * global invalidate context cache | |
3181 | * global invalidate iotlb | |
3182 | * enable translation | |
3183 | */ | |
7c919779 | 3184 | for_each_iommu(iommu, drhd) { |
51a63e67 JC |
3185 | if (drhd->ignored) { |
3186 | /* | |
3187 | * we always have to disable PMRs or DMA may fail on | |
3188 | * this device | |
3189 | */ | |
3190 | if (force_on) | |
7c919779 | 3191 | iommu_disable_protect_mem_regions(iommu); |
ba395927 | 3192 | continue; |
51a63e67 | 3193 | } |
ba395927 KA |
3194 | |
3195 | iommu_flush_write_buffer(iommu); | |
3196 | ||
3460a6d9 KA |
3197 | ret = dmar_set_interrupt(iommu); |
3198 | if (ret) | |
989d51fc | 3199 | goto free_iommu; |
3460a6d9 | 3200 | |
8939ddf6 JR |
3201 | if (!translation_pre_enabled(iommu)) |
3202 | iommu_enable_translation(iommu); | |
3203 | ||
b94996c9 | 3204 | iommu_disable_protect_mem_regions(iommu); |
ba395927 KA |
3205 | } |
3206 | ||
3207 | return 0; | |
989d51fc JL |
3208 | |
3209 | free_iommu: | |
ffebeb46 JL |
3210 | for_each_active_iommu(iommu, drhd) { |
3211 | disable_dmar_iommu(iommu); | |
a868e6b7 | 3212 | free_dmar_iommu(iommu); |
ffebeb46 | 3213 | } |
9bdc531e | 3214 | kfree(deferred_flush); |
989d51fc | 3215 | free_g_iommus: |
d9630fe9 | 3216 | kfree(g_iommus); |
989d51fc | 3217 | error: |
ba395927 KA |
3218 | return ret; |
3219 | } | |
3220 | ||
5a5e02a6 | 3221 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
3222 | static struct iova *intel_alloc_iova(struct device *dev, |
3223 | struct dmar_domain *domain, | |
3224 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 3225 | { |
ba395927 | 3226 | struct iova *iova = NULL; |
ba395927 | 3227 | |
875764de DW |
3228 | /* Restrict dma_mask to the width that the iommu can handle */ |
3229 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
8f6429c7 RM |
3230 | /* Ensure we reserve the whole size-aligned region */ |
3231 | nrpages = __roundup_pow_of_two(nrpages); | |
875764de DW |
3232 | |
3233 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
3234 | /* |
3235 | * First try to allocate an io virtual address in | |
284901a9 | 3236 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 3237 | * from higher range |
ba395927 | 3238 | */ |
875764de DW |
3239 | iova = alloc_iova(&domain->iovad, nrpages, |
3240 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
3241 | if (iova) | |
3242 | return iova; | |
3243 | } | |
3244 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
3245 | if (unlikely(!iova)) { | |
9f10e5bf | 3246 | pr_err("Allocating %ld-page iova for %s failed", |
207e3592 | 3247 | nrpages, dev_name(dev)); |
f76aec76 KA |
3248 | return NULL; |
3249 | } | |
3250 | ||
3251 | return iova; | |
3252 | } | |
3253 | ||
d4b709f4 | 3254 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
f76aec76 KA |
3255 | { |
3256 | struct dmar_domain *domain; | |
f76aec76 | 3257 | |
d4b709f4 | 3258 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
f76aec76 | 3259 | if (!domain) { |
9f10e5bf | 3260 | pr_err("Allocating domain for %s failed\n", |
d4b709f4 | 3261 | dev_name(dev)); |
4fe05bbc | 3262 | return NULL; |
ba395927 KA |
3263 | } |
3264 | ||
f76aec76 KA |
3265 | return domain; |
3266 | } | |
3267 | ||
d4b709f4 | 3268 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
147202aa DW |
3269 | { |
3270 | struct device_domain_info *info; | |
3271 | ||
3272 | /* No lock here, assumes no domain exit in normal case */ | |
d4b709f4 | 3273 | info = dev->archdata.iommu; |
147202aa DW |
3274 | if (likely(info)) |
3275 | return info->domain; | |
3276 | ||
3277 | return __get_valid_domain_for_dev(dev); | |
3278 | } | |
3279 | ||
ecb509ec | 3280 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
73676832 | 3281 | static int iommu_no_mapping(struct device *dev) |
2c2e2c38 FY |
3282 | { |
3283 | int found; | |
3284 | ||
3d89194a | 3285 | if (iommu_dummy(dev)) |
1e4c64c4 DW |
3286 | return 1; |
3287 | ||
2c2e2c38 | 3288 | if (!iommu_identity_mapping) |
1e4c64c4 | 3289 | return 0; |
2c2e2c38 | 3290 | |
9b226624 | 3291 | found = identity_mapping(dev); |
2c2e2c38 | 3292 | if (found) { |
ecb509ec | 3293 | if (iommu_should_identity_map(dev, 0)) |
2c2e2c38 FY |
3294 | return 1; |
3295 | else { | |
3296 | /* | |
3297 | * 32 bit DMA is removed from si_domain and fall back | |
3298 | * to non-identity mapping. | |
3299 | */ | |
e6de0f8d | 3300 | dmar_remove_one_dev_info(si_domain, dev); |
9f10e5bf JR |
3301 | pr_info("32bit %s uses non-identity mapping\n", |
3302 | dev_name(dev)); | |
2c2e2c38 FY |
3303 | return 0; |
3304 | } | |
3305 | } else { | |
3306 | /* | |
3307 | * In case of a detached 64 bit DMA device from vm, the device | |
3308 | * is put into si_domain for identity mapping. | |
3309 | */ | |
ecb509ec | 3310 | if (iommu_should_identity_map(dev, 0)) { |
2c2e2c38 | 3311 | int ret; |
28ccce0d | 3312 | ret = domain_add_dev_info(si_domain, dev); |
2c2e2c38 | 3313 | if (!ret) { |
9f10e5bf JR |
3314 | pr_info("64bit %s uses identity mapping\n", |
3315 | dev_name(dev)); | |
2c2e2c38 FY |
3316 | return 1; |
3317 | } | |
3318 | } | |
3319 | } | |
3320 | ||
1e4c64c4 | 3321 | return 0; |
2c2e2c38 FY |
3322 | } |
3323 | ||
5040a918 | 3324 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
bb9e6d65 | 3325 | size_t size, int dir, u64 dma_mask) |
f76aec76 | 3326 | { |
f76aec76 | 3327 | struct dmar_domain *domain; |
5b6985ce | 3328 | phys_addr_t start_paddr; |
f76aec76 KA |
3329 | struct iova *iova; |
3330 | int prot = 0; | |
6865f0d1 | 3331 | int ret; |
8c11e798 | 3332 | struct intel_iommu *iommu; |
33041ec0 | 3333 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
f76aec76 KA |
3334 | |
3335 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 3336 | |
5040a918 | 3337 | if (iommu_no_mapping(dev)) |
6865f0d1 | 3338 | return paddr; |
f76aec76 | 3339 | |
5040a918 | 3340 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3341 | if (!domain) |
3342 | return 0; | |
3343 | ||
8c11e798 | 3344 | iommu = domain_get_iommu(domain); |
88cb6a74 | 3345 | size = aligned_nrpages(paddr, size); |
f76aec76 | 3346 | |
5040a918 | 3347 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
f76aec76 KA |
3348 | if (!iova) |
3349 | goto error; | |
3350 | ||
ba395927 KA |
3351 | /* |
3352 | * Check if DMAR supports zero-length reads on write only | |
3353 | * mappings.. | |
3354 | */ | |
3355 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3356 | !cap_zlr(iommu->cap)) |
ba395927 KA |
3357 | prot |= DMA_PTE_READ; |
3358 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3359 | prot |= DMA_PTE_WRITE; | |
3360 | /* | |
6865f0d1 | 3361 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 3362 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 3363 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
3364 | * is not a big problem |
3365 | */ | |
0ab36de2 | 3366 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
33041ec0 | 3367 | mm_to_dma_pfn(paddr_pfn), size, prot); |
ba395927 KA |
3368 | if (ret) |
3369 | goto error; | |
3370 | ||
1f0ef2aa DW |
3371 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3372 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 JR |
3373 | iommu_flush_iotlb_psi(iommu, domain, |
3374 | mm_to_dma_pfn(iova->pfn_lo), | |
3375 | size, 0, 1); | |
1f0ef2aa | 3376 | else |
8c11e798 | 3377 | iommu_flush_write_buffer(iommu); |
f76aec76 | 3378 | |
03d6a246 DW |
3379 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
3380 | start_paddr += paddr & ~PAGE_MASK; | |
3381 | return start_paddr; | |
ba395927 | 3382 | |
ba395927 | 3383 | error: |
f76aec76 KA |
3384 | if (iova) |
3385 | __free_iova(&domain->iovad, iova); | |
9f10e5bf | 3386 | pr_err("Device %s request: %zx@%llx dir %d --- failed\n", |
5040a918 | 3387 | dev_name(dev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
3388 | return 0; |
3389 | } | |
3390 | ||
ffbbef5c FT |
3391 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
3392 | unsigned long offset, size_t size, | |
3393 | enum dma_data_direction dir, | |
3394 | struct dma_attrs *attrs) | |
bb9e6d65 | 3395 | { |
ffbbef5c | 3396 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
46333e37 | 3397 | dir, *dev->dma_mask); |
bb9e6d65 FT |
3398 | } |
3399 | ||
5e0d2a6f | 3400 | static void flush_unmaps(void) |
3401 | { | |
80b20dd8 | 3402 | int i, j; |
5e0d2a6f | 3403 | |
5e0d2a6f | 3404 | timer_on = 0; |
3405 | ||
3406 | /* just flush them all */ | |
3407 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
3408 | struct intel_iommu *iommu = g_iommus[i]; |
3409 | if (!iommu) | |
3410 | continue; | |
c42d9f32 | 3411 | |
9dd2fe89 YZ |
3412 | if (!deferred_flush[i].next) |
3413 | continue; | |
3414 | ||
78d5f0f5 NA |
3415 | /* In caching mode, global flushes turn emulation expensive */ |
3416 | if (!cap_caching_mode(iommu->cap)) | |
3417 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 3418 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 3419 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
3420 | unsigned long mask; |
3421 | struct iova *iova = deferred_flush[i].iova[j]; | |
78d5f0f5 NA |
3422 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
3423 | ||
3424 | /* On real hardware multiple invalidations are expensive */ | |
3425 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 | 3426 | iommu_flush_iotlb_psi(iommu, domain, |
a156ef99 | 3427 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 3428 | !deferred_flush[i].freelist[j], 0); |
78d5f0f5 | 3429 | else { |
a156ef99 | 3430 | mask = ilog2(mm_to_dma_pfn(iova_size(iova))); |
78d5f0f5 NA |
3431 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
3432 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); | |
3433 | } | |
93a23a72 | 3434 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
ea8ea460 DW |
3435 | if (deferred_flush[i].freelist[j]) |
3436 | dma_free_pagelist(deferred_flush[i].freelist[j]); | |
80b20dd8 | 3437 | } |
9dd2fe89 | 3438 | deferred_flush[i].next = 0; |
5e0d2a6f | 3439 | } |
3440 | ||
5e0d2a6f | 3441 | list_size = 0; |
5e0d2a6f | 3442 | } |
3443 | ||
3444 | static void flush_unmaps_timeout(unsigned long data) | |
3445 | { | |
80b20dd8 | 3446 | unsigned long flags; |
3447 | ||
3448 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 3449 | flush_unmaps(); |
80b20dd8 | 3450 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 3451 | } |
3452 | ||
ea8ea460 | 3453 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
5e0d2a6f | 3454 | { |
3455 | unsigned long flags; | |
80b20dd8 | 3456 | int next, iommu_id; |
8c11e798 | 3457 | struct intel_iommu *iommu; |
5e0d2a6f | 3458 | |
3459 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 3460 | if (list_size == HIGH_WATER_MARK) |
3461 | flush_unmaps(); | |
3462 | ||
8c11e798 WH |
3463 | iommu = domain_get_iommu(dom); |
3464 | iommu_id = iommu->seq_id; | |
c42d9f32 | 3465 | |
80b20dd8 | 3466 | next = deferred_flush[iommu_id].next; |
3467 | deferred_flush[iommu_id].domain[next] = dom; | |
3468 | deferred_flush[iommu_id].iova[next] = iova; | |
ea8ea460 | 3469 | deferred_flush[iommu_id].freelist[next] = freelist; |
80b20dd8 | 3470 | deferred_flush[iommu_id].next++; |
5e0d2a6f | 3471 | |
3472 | if (!timer_on) { | |
3473 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
3474 | timer_on = 1; | |
3475 | } | |
3476 | list_size++; | |
3477 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
3478 | } | |
3479 | ||
d41a4adb | 3480 | static void intel_unmap(struct device *dev, dma_addr_t dev_addr) |
ba395927 | 3481 | { |
f76aec76 | 3482 | struct dmar_domain *domain; |
d794dc9b | 3483 | unsigned long start_pfn, last_pfn; |
ba395927 | 3484 | struct iova *iova; |
8c11e798 | 3485 | struct intel_iommu *iommu; |
ea8ea460 | 3486 | struct page *freelist; |
ba395927 | 3487 | |
73676832 | 3488 | if (iommu_no_mapping(dev)) |
f76aec76 | 3489 | return; |
2c2e2c38 | 3490 | |
1525a29a | 3491 | domain = find_domain(dev); |
ba395927 KA |
3492 | BUG_ON(!domain); |
3493 | ||
8c11e798 WH |
3494 | iommu = domain_get_iommu(domain); |
3495 | ||
ba395927 | 3496 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
3497 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
3498 | (unsigned long long)dev_addr)) | |
ba395927 | 3499 | return; |
ba395927 | 3500 | |
d794dc9b DW |
3501 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3502 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 3503 | |
d794dc9b | 3504 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
207e3592 | 3505 | dev_name(dev), start_pfn, last_pfn); |
ba395927 | 3506 | |
ea8ea460 | 3507 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
d794dc9b | 3508 | |
5e0d2a6f | 3509 | if (intel_iommu_strict) { |
a1ddcbe9 | 3510 | iommu_flush_iotlb_psi(iommu, domain, start_pfn, |
ea8ea460 | 3511 | last_pfn - start_pfn + 1, !freelist, 0); |
5e0d2a6f | 3512 | /* free iova */ |
3513 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3514 | dma_free_pagelist(freelist); |
5e0d2a6f | 3515 | } else { |
ea8ea460 | 3516 | add_unmap(domain, iova, freelist); |
5e0d2a6f | 3517 | /* |
3518 | * queue up the release of the unmap to save the 1/6th of the | |
3519 | * cpu used up by the iotlb flush operation... | |
3520 | */ | |
5e0d2a6f | 3521 | } |
ba395927 KA |
3522 | } |
3523 | ||
d41a4adb JL |
3524 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
3525 | size_t size, enum dma_data_direction dir, | |
3526 | struct dma_attrs *attrs) | |
3527 | { | |
3528 | intel_unmap(dev, dev_addr); | |
3529 | } | |
3530 | ||
5040a918 | 3531 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
baa676fc AP |
3532 | dma_addr_t *dma_handle, gfp_t flags, |
3533 | struct dma_attrs *attrs) | |
ba395927 | 3534 | { |
36746436 | 3535 | struct page *page = NULL; |
ba395927 KA |
3536 | int order; |
3537 | ||
5b6985ce | 3538 | size = PAGE_ALIGN(size); |
ba395927 | 3539 | order = get_order(size); |
e8bb910d | 3540 | |
5040a918 | 3541 | if (!iommu_no_mapping(dev)) |
e8bb910d | 3542 | flags &= ~(GFP_DMA | GFP_DMA32); |
5040a918 DW |
3543 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
3544 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) | |
e8bb910d AW |
3545 | flags |= GFP_DMA; |
3546 | else | |
3547 | flags |= GFP_DMA32; | |
3548 | } | |
ba395927 | 3549 | |
36746436 AM |
3550 | if (flags & __GFP_WAIT) { |
3551 | unsigned int count = size >> PAGE_SHIFT; | |
3552 | ||
3553 | page = dma_alloc_from_contiguous(dev, count, order); | |
3554 | if (page && iommu_no_mapping(dev) && | |
3555 | page_to_phys(page) + size > dev->coherent_dma_mask) { | |
3556 | dma_release_from_contiguous(dev, page, count); | |
3557 | page = NULL; | |
3558 | } | |
3559 | } | |
3560 | ||
3561 | if (!page) | |
3562 | page = alloc_pages(flags, order); | |
3563 | if (!page) | |
ba395927 | 3564 | return NULL; |
36746436 | 3565 | memset(page_address(page), 0, size); |
ba395927 | 3566 | |
36746436 | 3567 | *dma_handle = __intel_map_single(dev, page_to_phys(page), size, |
bb9e6d65 | 3568 | DMA_BIDIRECTIONAL, |
5040a918 | 3569 | dev->coherent_dma_mask); |
ba395927 | 3570 | if (*dma_handle) |
36746436 AM |
3571 | return page_address(page); |
3572 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) | |
3573 | __free_pages(page, order); | |
3574 | ||
ba395927 KA |
3575 | return NULL; |
3576 | } | |
3577 | ||
5040a918 | 3578 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
baa676fc | 3579 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
ba395927 KA |
3580 | { |
3581 | int order; | |
36746436 | 3582 | struct page *page = virt_to_page(vaddr); |
ba395927 | 3583 | |
5b6985ce | 3584 | size = PAGE_ALIGN(size); |
ba395927 KA |
3585 | order = get_order(size); |
3586 | ||
d41a4adb | 3587 | intel_unmap(dev, dma_handle); |
36746436 AM |
3588 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
3589 | __free_pages(page, order); | |
ba395927 KA |
3590 | } |
3591 | ||
5040a918 | 3592 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
d7ab5c46 FT |
3593 | int nelems, enum dma_data_direction dir, |
3594 | struct dma_attrs *attrs) | |
ba395927 | 3595 | { |
d41a4adb | 3596 | intel_unmap(dev, sglist[0].dma_address); |
ba395927 KA |
3597 | } |
3598 | ||
ba395927 | 3599 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 3600 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
3601 | { |
3602 | int i; | |
c03ab37c | 3603 | struct scatterlist *sg; |
ba395927 | 3604 | |
c03ab37c | 3605 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 3606 | BUG_ON(!sg_page(sg)); |
db0fa0cb | 3607 | sg->dma_address = sg_phys(sg); |
c03ab37c | 3608 | sg->dma_length = sg->length; |
ba395927 KA |
3609 | } |
3610 | return nelems; | |
3611 | } | |
3612 | ||
5040a918 | 3613 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
d7ab5c46 | 3614 | enum dma_data_direction dir, struct dma_attrs *attrs) |
ba395927 | 3615 | { |
ba395927 | 3616 | int i; |
ba395927 | 3617 | struct dmar_domain *domain; |
f76aec76 KA |
3618 | size_t size = 0; |
3619 | int prot = 0; | |
f76aec76 KA |
3620 | struct iova *iova = NULL; |
3621 | int ret; | |
c03ab37c | 3622 | struct scatterlist *sg; |
b536d24d | 3623 | unsigned long start_vpfn; |
8c11e798 | 3624 | struct intel_iommu *iommu; |
ba395927 KA |
3625 | |
3626 | BUG_ON(dir == DMA_NONE); | |
5040a918 DW |
3627 | if (iommu_no_mapping(dev)) |
3628 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); | |
ba395927 | 3629 | |
5040a918 | 3630 | domain = get_valid_domain_for_dev(dev); |
f76aec76 KA |
3631 | if (!domain) |
3632 | return 0; | |
3633 | ||
8c11e798 WH |
3634 | iommu = domain_get_iommu(domain); |
3635 | ||
b536d24d | 3636 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 3637 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 3638 | |
5040a918 DW |
3639 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
3640 | *dev->dma_mask); | |
f76aec76 | 3641 | if (!iova) { |
c03ab37c | 3642 | sglist->dma_length = 0; |
f76aec76 KA |
3643 | return 0; |
3644 | } | |
3645 | ||
3646 | /* | |
3647 | * Check if DMAR supports zero-length reads on write only | |
3648 | * mappings.. | |
3649 | */ | |
3650 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3651 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
3652 | prot |= DMA_PTE_READ; |
3653 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3654 | prot |= DMA_PTE_WRITE; | |
3655 | ||
b536d24d | 3656 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 | 3657 | |
f532959b | 3658 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
e1605495 | 3659 | if (unlikely(ret)) { |
e1605495 DW |
3660 | dma_pte_free_pagetable(domain, start_vpfn, |
3661 | start_vpfn + size - 1); | |
e1605495 DW |
3662 | __free_iova(&domain->iovad, iova); |
3663 | return 0; | |
ba395927 KA |
3664 | } |
3665 | ||
1f0ef2aa DW |
3666 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3667 | if (cap_caching_mode(iommu->cap)) | |
a1ddcbe9 | 3668 | iommu_flush_iotlb_psi(iommu, domain, start_vpfn, size, 0, 1); |
1f0ef2aa | 3669 | else |
8c11e798 | 3670 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 3671 | |
ba395927 KA |
3672 | return nelems; |
3673 | } | |
3674 | ||
dfb805e8 FT |
3675 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
3676 | { | |
3677 | return !dma_addr; | |
3678 | } | |
3679 | ||
160c1d8e | 3680 | struct dma_map_ops intel_dma_ops = { |
baa676fc AP |
3681 | .alloc = intel_alloc_coherent, |
3682 | .free = intel_free_coherent, | |
ba395927 KA |
3683 | .map_sg = intel_map_sg, |
3684 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
3685 | .map_page = intel_map_page, |
3686 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 3687 | .mapping_error = intel_mapping_error, |
ba395927 KA |
3688 | }; |
3689 | ||
3690 | static inline int iommu_domain_cache_init(void) | |
3691 | { | |
3692 | int ret = 0; | |
3693 | ||
3694 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
3695 | sizeof(struct dmar_domain), | |
3696 | 0, | |
3697 | SLAB_HWCACHE_ALIGN, | |
3698 | ||
3699 | NULL); | |
3700 | if (!iommu_domain_cache) { | |
9f10e5bf | 3701 | pr_err("Couldn't create iommu_domain cache\n"); |
ba395927 KA |
3702 | ret = -ENOMEM; |
3703 | } | |
3704 | ||
3705 | return ret; | |
3706 | } | |
3707 | ||
3708 | static inline int iommu_devinfo_cache_init(void) | |
3709 | { | |
3710 | int ret = 0; | |
3711 | ||
3712 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
3713 | sizeof(struct device_domain_info), | |
3714 | 0, | |
3715 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3716 | NULL); |
3717 | if (!iommu_devinfo_cache) { | |
9f10e5bf | 3718 | pr_err("Couldn't create devinfo cache\n"); |
ba395927 KA |
3719 | ret = -ENOMEM; |
3720 | } | |
3721 | ||
3722 | return ret; | |
3723 | } | |
3724 | ||
ba395927 KA |
3725 | static int __init iommu_init_mempool(void) |
3726 | { | |
3727 | int ret; | |
ae1ff3d6 | 3728 | ret = iova_cache_get(); |
ba395927 KA |
3729 | if (ret) |
3730 | return ret; | |
3731 | ||
3732 | ret = iommu_domain_cache_init(); | |
3733 | if (ret) | |
3734 | goto domain_error; | |
3735 | ||
3736 | ret = iommu_devinfo_cache_init(); | |
3737 | if (!ret) | |
3738 | return ret; | |
3739 | ||
3740 | kmem_cache_destroy(iommu_domain_cache); | |
3741 | domain_error: | |
ae1ff3d6 | 3742 | iova_cache_put(); |
ba395927 KA |
3743 | |
3744 | return -ENOMEM; | |
3745 | } | |
3746 | ||
3747 | static void __init iommu_exit_mempool(void) | |
3748 | { | |
3749 | kmem_cache_destroy(iommu_devinfo_cache); | |
3750 | kmem_cache_destroy(iommu_domain_cache); | |
ae1ff3d6 | 3751 | iova_cache_put(); |
ba395927 KA |
3752 | } |
3753 | ||
556ab45f DW |
3754 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
3755 | { | |
3756 | struct dmar_drhd_unit *drhd; | |
3757 | u32 vtbar; | |
3758 | int rc; | |
3759 | ||
3760 | /* We know that this device on this chipset has its own IOMMU. | |
3761 | * If we find it under a different IOMMU, then the BIOS is lying | |
3762 | * to us. Hope that the IOMMU for this device is actually | |
3763 | * disabled, and it needs no translation... | |
3764 | */ | |
3765 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); | |
3766 | if (rc) { | |
3767 | /* "can't" happen */ | |
3768 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); | |
3769 | return; | |
3770 | } | |
3771 | vtbar &= 0xffff0000; | |
3772 | ||
3773 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ | |
3774 | drhd = dmar_find_matched_drhd_unit(pdev); | |
3775 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, | |
3776 | TAINT_FIRMWARE_WORKAROUND, | |
3777 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) | |
3778 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; | |
3779 | } | |
3780 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); | |
3781 | ||
ba395927 KA |
3782 | static void __init init_no_remapping_devices(void) |
3783 | { | |
3784 | struct dmar_drhd_unit *drhd; | |
832bd858 | 3785 | struct device *dev; |
b683b230 | 3786 | int i; |
ba395927 KA |
3787 | |
3788 | for_each_drhd_unit(drhd) { | |
3789 | if (!drhd->include_all) { | |
b683b230 JL |
3790 | for_each_active_dev_scope(drhd->devices, |
3791 | drhd->devices_cnt, i, dev) | |
3792 | break; | |
832bd858 | 3793 | /* ignore DMAR unit if no devices exist */ |
ba395927 KA |
3794 | if (i == drhd->devices_cnt) |
3795 | drhd->ignored = 1; | |
3796 | } | |
3797 | } | |
3798 | ||
7c919779 | 3799 | for_each_active_drhd_unit(drhd) { |
7c919779 | 3800 | if (drhd->include_all) |
ba395927 KA |
3801 | continue; |
3802 | ||
b683b230 JL |
3803 | for_each_active_dev_scope(drhd->devices, |
3804 | drhd->devices_cnt, i, dev) | |
832bd858 | 3805 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
ba395927 | 3806 | break; |
ba395927 KA |
3807 | if (i < drhd->devices_cnt) |
3808 | continue; | |
3809 | ||
c0771df8 DW |
3810 | /* This IOMMU has *only* gfx devices. Either bypass it or |
3811 | set the gfx_mapped flag, as appropriate */ | |
3812 | if (dmar_map_gfx) { | |
3813 | intel_iommu_gfx_mapped = 1; | |
3814 | } else { | |
3815 | drhd->ignored = 1; | |
b683b230 JL |
3816 | for_each_active_dev_scope(drhd->devices, |
3817 | drhd->devices_cnt, i, dev) | |
832bd858 | 3818 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
3819 | } |
3820 | } | |
3821 | } | |
3822 | ||
f59c7b69 FY |
3823 | #ifdef CONFIG_SUSPEND |
3824 | static int init_iommu_hw(void) | |
3825 | { | |
3826 | struct dmar_drhd_unit *drhd; | |
3827 | struct intel_iommu *iommu = NULL; | |
3828 | ||
3829 | for_each_active_iommu(iommu, drhd) | |
3830 | if (iommu->qi) | |
3831 | dmar_reenable_qi(iommu); | |
3832 | ||
b779260b JC |
3833 | for_each_iommu(iommu, drhd) { |
3834 | if (drhd->ignored) { | |
3835 | /* | |
3836 | * we always have to disable PMRs or DMA may fail on | |
3837 | * this device | |
3838 | */ | |
3839 | if (force_on) | |
3840 | iommu_disable_protect_mem_regions(iommu); | |
3841 | continue; | |
3842 | } | |
3843 | ||
f59c7b69 FY |
3844 | iommu_flush_write_buffer(iommu); |
3845 | ||
3846 | iommu_set_root_entry(iommu); | |
3847 | ||
3848 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3849 | DMA_CCMD_GLOBAL_INVL); |
2a41ccee JL |
3850 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
3851 | iommu_enable_translation(iommu); | |
b94996c9 | 3852 | iommu_disable_protect_mem_regions(iommu); |
f59c7b69 FY |
3853 | } |
3854 | ||
3855 | return 0; | |
3856 | } | |
3857 | ||
3858 | static void iommu_flush_all(void) | |
3859 | { | |
3860 | struct dmar_drhd_unit *drhd; | |
3861 | struct intel_iommu *iommu; | |
3862 | ||
3863 | for_each_active_iommu(iommu, drhd) { | |
3864 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3865 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3866 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3867 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3868 | } |
3869 | } | |
3870 | ||
134fac3f | 3871 | static int iommu_suspend(void) |
f59c7b69 FY |
3872 | { |
3873 | struct dmar_drhd_unit *drhd; | |
3874 | struct intel_iommu *iommu = NULL; | |
3875 | unsigned long flag; | |
3876 | ||
3877 | for_each_active_iommu(iommu, drhd) { | |
3878 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3879 | GFP_ATOMIC); | |
3880 | if (!iommu->iommu_state) | |
3881 | goto nomem; | |
3882 | } | |
3883 | ||
3884 | iommu_flush_all(); | |
3885 | ||
3886 | for_each_active_iommu(iommu, drhd) { | |
3887 | iommu_disable_translation(iommu); | |
3888 | ||
1f5b3c3f | 3889 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3890 | |
3891 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3892 | readl(iommu->reg + DMAR_FECTL_REG); | |
3893 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3894 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3895 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3896 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3897 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3898 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3899 | ||
1f5b3c3f | 3900 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3901 | } |
3902 | return 0; | |
3903 | ||
3904 | nomem: | |
3905 | for_each_active_iommu(iommu, drhd) | |
3906 | kfree(iommu->iommu_state); | |
3907 | ||
3908 | return -ENOMEM; | |
3909 | } | |
3910 | ||
134fac3f | 3911 | static void iommu_resume(void) |
f59c7b69 FY |
3912 | { |
3913 | struct dmar_drhd_unit *drhd; | |
3914 | struct intel_iommu *iommu = NULL; | |
3915 | unsigned long flag; | |
3916 | ||
3917 | if (init_iommu_hw()) { | |
b779260b JC |
3918 | if (force_on) |
3919 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); | |
3920 | else | |
3921 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
134fac3f | 3922 | return; |
f59c7b69 FY |
3923 | } |
3924 | ||
3925 | for_each_active_iommu(iommu, drhd) { | |
3926 | ||
1f5b3c3f | 3927 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3928 | |
3929 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3930 | iommu->reg + DMAR_FECTL_REG); | |
3931 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3932 | iommu->reg + DMAR_FEDATA_REG); | |
3933 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3934 | iommu->reg + DMAR_FEADDR_REG); | |
3935 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3936 | iommu->reg + DMAR_FEUADDR_REG); | |
3937 | ||
1f5b3c3f | 3938 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3939 | } |
3940 | ||
3941 | for_each_active_iommu(iommu, drhd) | |
3942 | kfree(iommu->iommu_state); | |
f59c7b69 FY |
3943 | } |
3944 | ||
134fac3f | 3945 | static struct syscore_ops iommu_syscore_ops = { |
f59c7b69 FY |
3946 | .resume = iommu_resume, |
3947 | .suspend = iommu_suspend, | |
3948 | }; | |
3949 | ||
134fac3f | 3950 | static void __init init_iommu_pm_ops(void) |
f59c7b69 | 3951 | { |
134fac3f | 3952 | register_syscore_ops(&iommu_syscore_ops); |
f59c7b69 FY |
3953 | } |
3954 | ||
3955 | #else | |
99592ba4 | 3956 | static inline void init_iommu_pm_ops(void) {} |
f59c7b69 FY |
3957 | #endif /* CONFIG_PM */ |
3958 | ||
318fe7df | 3959 | |
c2a0b538 | 3960 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg) |
318fe7df SS |
3961 | { |
3962 | struct acpi_dmar_reserved_memory *rmrr; | |
3963 | struct dmar_rmrr_unit *rmrru; | |
3964 | ||
3965 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
3966 | if (!rmrru) | |
3967 | return -ENOMEM; | |
3968 | ||
3969 | rmrru->hdr = header; | |
3970 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
3971 | rmrru->base_address = rmrr->base_address; | |
3972 | rmrru->end_address = rmrr->end_address; | |
2e455289 JL |
3973 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
3974 | ((void *)rmrr) + rmrr->header.length, | |
3975 | &rmrru->devices_cnt); | |
3976 | if (rmrru->devices_cnt && rmrru->devices == NULL) { | |
3977 | kfree(rmrru); | |
3978 | return -ENOMEM; | |
3979 | } | |
318fe7df | 3980 | |
2e455289 | 3981 | list_add(&rmrru->list, &dmar_rmrr_units); |
318fe7df | 3982 | |
2e455289 | 3983 | return 0; |
318fe7df SS |
3984 | } |
3985 | ||
6b197249 JL |
3986 | static struct dmar_atsr_unit *dmar_find_atsr(struct acpi_dmar_atsr *atsr) |
3987 | { | |
3988 | struct dmar_atsr_unit *atsru; | |
3989 | struct acpi_dmar_atsr *tmp; | |
3990 | ||
3991 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { | |
3992 | tmp = (struct acpi_dmar_atsr *)atsru->hdr; | |
3993 | if (atsr->segment != tmp->segment) | |
3994 | continue; | |
3995 | if (atsr->header.length != tmp->header.length) | |
3996 | continue; | |
3997 | if (memcmp(atsr, tmp, atsr->header.length) == 0) | |
3998 | return atsru; | |
3999 | } | |
4000 | ||
4001 | return NULL; | |
4002 | } | |
4003 | ||
4004 | int dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg) | |
318fe7df SS |
4005 | { |
4006 | struct acpi_dmar_atsr *atsr; | |
4007 | struct dmar_atsr_unit *atsru; | |
4008 | ||
6b197249 JL |
4009 | if (system_state != SYSTEM_BOOTING && !intel_iommu_enabled) |
4010 | return 0; | |
4011 | ||
318fe7df | 4012 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
6b197249 JL |
4013 | atsru = dmar_find_atsr(atsr); |
4014 | if (atsru) | |
4015 | return 0; | |
4016 | ||
4017 | atsru = kzalloc(sizeof(*atsru) + hdr->length, GFP_KERNEL); | |
318fe7df SS |
4018 | if (!atsru) |
4019 | return -ENOMEM; | |
4020 | ||
6b197249 JL |
4021 | /* |
4022 | * If memory is allocated from slab by ACPI _DSM method, we need to | |
4023 | * copy the memory content because the memory buffer will be freed | |
4024 | * on return. | |
4025 | */ | |
4026 | atsru->hdr = (void *)(atsru + 1); | |
4027 | memcpy(atsru->hdr, hdr, hdr->length); | |
318fe7df | 4028 | atsru->include_all = atsr->flags & 0x1; |
2e455289 JL |
4029 | if (!atsru->include_all) { |
4030 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), | |
4031 | (void *)atsr + atsr->header.length, | |
4032 | &atsru->devices_cnt); | |
4033 | if (atsru->devices_cnt && atsru->devices == NULL) { | |
4034 | kfree(atsru); | |
4035 | return -ENOMEM; | |
4036 | } | |
4037 | } | |
318fe7df | 4038 | |
0e242612 | 4039 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
318fe7df SS |
4040 | |
4041 | return 0; | |
4042 | } | |
4043 | ||
9bdc531e JL |
4044 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
4045 | { | |
4046 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); | |
4047 | kfree(atsru); | |
4048 | } | |
4049 | ||
6b197249 JL |
4050 | int dmar_release_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
4051 | { | |
4052 | struct acpi_dmar_atsr *atsr; | |
4053 | struct dmar_atsr_unit *atsru; | |
4054 | ||
4055 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
4056 | atsru = dmar_find_atsr(atsr); | |
4057 | if (atsru) { | |
4058 | list_del_rcu(&atsru->list); | |
4059 | synchronize_rcu(); | |
4060 | intel_iommu_free_atsr(atsru); | |
4061 | } | |
4062 | ||
4063 | return 0; | |
4064 | } | |
4065 | ||
4066 | int dmar_check_one_atsr(struct acpi_dmar_header *hdr, void *arg) | |
4067 | { | |
4068 | int i; | |
4069 | struct device *dev; | |
4070 | struct acpi_dmar_atsr *atsr; | |
4071 | struct dmar_atsr_unit *atsru; | |
4072 | ||
4073 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
4074 | atsru = dmar_find_atsr(atsr); | |
4075 | if (!atsru) | |
4076 | return 0; | |
4077 | ||
4078 | if (!atsru->include_all && atsru->devices && atsru->devices_cnt) | |
4079 | for_each_active_dev_scope(atsru->devices, atsru->devices_cnt, | |
4080 | i, dev) | |
4081 | return -EBUSY; | |
4082 | ||
4083 | return 0; | |
4084 | } | |
4085 | ||
ffebeb46 JL |
4086 | static int intel_iommu_add(struct dmar_drhd_unit *dmaru) |
4087 | { | |
4088 | int sp, ret = 0; | |
4089 | struct intel_iommu *iommu = dmaru->iommu; | |
4090 | ||
4091 | if (g_iommus[iommu->seq_id]) | |
4092 | return 0; | |
4093 | ||
4094 | if (hw_pass_through && !ecap_pass_through(iommu->ecap)) { | |
9f10e5bf | 4095 | pr_warn("%s: Doesn't support hardware pass through.\n", |
ffebeb46 JL |
4096 | iommu->name); |
4097 | return -ENXIO; | |
4098 | } | |
4099 | if (!ecap_sc_support(iommu->ecap) && | |
4100 | domain_update_iommu_snooping(iommu)) { | |
9f10e5bf | 4101 | pr_warn("%s: Doesn't support snooping.\n", |
ffebeb46 JL |
4102 | iommu->name); |
4103 | return -ENXIO; | |
4104 | } | |
4105 | sp = domain_update_iommu_superpage(iommu) - 1; | |
4106 | if (sp >= 0 && !(cap_super_page_val(iommu->cap) & (1 << sp))) { | |
9f10e5bf | 4107 | pr_warn("%s: Doesn't support large page.\n", |
ffebeb46 JL |
4108 | iommu->name); |
4109 | return -ENXIO; | |
4110 | } | |
4111 | ||
4112 | /* | |
4113 | * Disable translation if already enabled prior to OS handover. | |
4114 | */ | |
4115 | if (iommu->gcmd & DMA_GCMD_TE) | |
4116 | iommu_disable_translation(iommu); | |
4117 | ||
4118 | g_iommus[iommu->seq_id] = iommu; | |
4119 | ret = iommu_init_domains(iommu); | |
4120 | if (ret == 0) | |
4121 | ret = iommu_alloc_root_entry(iommu); | |
4122 | if (ret) | |
4123 | goto out; | |
4124 | ||
4125 | if (dmaru->ignored) { | |
4126 | /* | |
4127 | * we always have to disable PMRs or DMA may fail on this device | |
4128 | */ | |
4129 | if (force_on) | |
4130 | iommu_disable_protect_mem_regions(iommu); | |
4131 | return 0; | |
4132 | } | |
4133 | ||
4134 | intel_iommu_init_qi(iommu); | |
4135 | iommu_flush_write_buffer(iommu); | |
4136 | ret = dmar_set_interrupt(iommu); | |
4137 | if (ret) | |
4138 | goto disable_iommu; | |
4139 | ||
4140 | iommu_set_root_entry(iommu); | |
4141 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); | |
4142 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); | |
4143 | iommu_enable_translation(iommu); | |
4144 | ||
ffebeb46 JL |
4145 | iommu_disable_protect_mem_regions(iommu); |
4146 | return 0; | |
4147 | ||
4148 | disable_iommu: | |
4149 | disable_dmar_iommu(iommu); | |
4150 | out: | |
4151 | free_dmar_iommu(iommu); | |
4152 | return ret; | |
4153 | } | |
4154 | ||
6b197249 JL |
4155 | int dmar_iommu_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
4156 | { | |
ffebeb46 JL |
4157 | int ret = 0; |
4158 | struct intel_iommu *iommu = dmaru->iommu; | |
4159 | ||
4160 | if (!intel_iommu_enabled) | |
4161 | return 0; | |
4162 | if (iommu == NULL) | |
4163 | return -EINVAL; | |
4164 | ||
4165 | if (insert) { | |
4166 | ret = intel_iommu_add(dmaru); | |
4167 | } else { | |
4168 | disable_dmar_iommu(iommu); | |
4169 | free_dmar_iommu(iommu); | |
4170 | } | |
4171 | ||
4172 | return ret; | |
6b197249 JL |
4173 | } |
4174 | ||
9bdc531e JL |
4175 | static void intel_iommu_free_dmars(void) |
4176 | { | |
4177 | struct dmar_rmrr_unit *rmrru, *rmrr_n; | |
4178 | struct dmar_atsr_unit *atsru, *atsr_n; | |
4179 | ||
4180 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { | |
4181 | list_del(&rmrru->list); | |
4182 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); | |
4183 | kfree(rmrru); | |
318fe7df SS |
4184 | } |
4185 | ||
9bdc531e JL |
4186 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
4187 | list_del(&atsru->list); | |
4188 | intel_iommu_free_atsr(atsru); | |
4189 | } | |
318fe7df SS |
4190 | } |
4191 | ||
4192 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) | |
4193 | { | |
b683b230 | 4194 | int i, ret = 1; |
318fe7df | 4195 | struct pci_bus *bus; |
832bd858 DW |
4196 | struct pci_dev *bridge = NULL; |
4197 | struct device *tmp; | |
318fe7df SS |
4198 | struct acpi_dmar_atsr *atsr; |
4199 | struct dmar_atsr_unit *atsru; | |
4200 | ||
4201 | dev = pci_physfn(dev); | |
318fe7df | 4202 | for (bus = dev->bus; bus; bus = bus->parent) { |
b5f82ddf | 4203 | bridge = bus->self; |
d14053b3 DW |
4204 | /* If it's an integrated device, allow ATS */ |
4205 | if (!bridge) | |
4206 | return 1; | |
4207 | /* Connected via non-PCIe: no ATS */ | |
4208 | if (!pci_is_pcie(bridge) || | |
62f87c0e | 4209 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
318fe7df | 4210 | return 0; |
d14053b3 | 4211 | /* If we found the root port, look it up in the ATSR */ |
b5f82ddf | 4212 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
318fe7df | 4213 | break; |
318fe7df SS |
4214 | } |
4215 | ||
0e242612 | 4216 | rcu_read_lock(); |
b5f82ddf JL |
4217 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
4218 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
4219 | if (atsr->segment != pci_domain_nr(dev->bus)) | |
4220 | continue; | |
4221 | ||
b683b230 | 4222 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
832bd858 | 4223 | if (tmp == &bridge->dev) |
b683b230 | 4224 | goto out; |
b5f82ddf JL |
4225 | |
4226 | if (atsru->include_all) | |
b683b230 | 4227 | goto out; |
b5f82ddf | 4228 | } |
b683b230 JL |
4229 | ret = 0; |
4230 | out: | |
0e242612 | 4231 | rcu_read_unlock(); |
318fe7df | 4232 | |
b683b230 | 4233 | return ret; |
318fe7df SS |
4234 | } |
4235 | ||
59ce0515 JL |
4236 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
4237 | { | |
4238 | int ret = 0; | |
4239 | struct dmar_rmrr_unit *rmrru; | |
4240 | struct dmar_atsr_unit *atsru; | |
4241 | struct acpi_dmar_atsr *atsr; | |
4242 | struct acpi_dmar_reserved_memory *rmrr; | |
4243 | ||
4244 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) | |
4245 | return 0; | |
4246 | ||
4247 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { | |
4248 | rmrr = container_of(rmrru->hdr, | |
4249 | struct acpi_dmar_reserved_memory, header); | |
4250 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
4251 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), | |
4252 | ((void *)rmrr) + rmrr->header.length, | |
4253 | rmrr->segment, rmrru->devices, | |
4254 | rmrru->devices_cnt); | |
27e24950 | 4255 | if(ret < 0) |
59ce0515 JL |
4256 | return ret; |
4257 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
27e24950 JL |
4258 | dmar_remove_dev_scope(info, rmrr->segment, |
4259 | rmrru->devices, rmrru->devices_cnt); | |
59ce0515 JL |
4260 | } |
4261 | } | |
4262 | ||
4263 | list_for_each_entry(atsru, &dmar_atsr_units, list) { | |
4264 | if (atsru->include_all) | |
4265 | continue; | |
4266 | ||
4267 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
4268 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
4269 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), | |
4270 | (void *)atsr + atsr->header.length, | |
4271 | atsr->segment, atsru->devices, | |
4272 | atsru->devices_cnt); | |
4273 | if (ret > 0) | |
4274 | break; | |
4275 | else if(ret < 0) | |
4276 | return ret; | |
4277 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
4278 | if (dmar_remove_dev_scope(info, atsr->segment, | |
4279 | atsru->devices, atsru->devices_cnt)) | |
4280 | break; | |
4281 | } | |
4282 | } | |
4283 | ||
4284 | return 0; | |
4285 | } | |
4286 | ||
99dcaded FY |
4287 | /* |
4288 | * Here we only respond to action of unbound device from driver. | |
4289 | * | |
4290 | * Added device is not attached to its DMAR domain here yet. That will happen | |
4291 | * when mapping the device to iova. | |
4292 | */ | |
4293 | static int device_notifier(struct notifier_block *nb, | |
4294 | unsigned long action, void *data) | |
4295 | { | |
4296 | struct device *dev = data; | |
99dcaded FY |
4297 | struct dmar_domain *domain; |
4298 | ||
3d89194a | 4299 | if (iommu_dummy(dev)) |
44cd613c DW |
4300 | return 0; |
4301 | ||
1196c2fb | 4302 | if (action != BUS_NOTIFY_REMOVED_DEVICE) |
7e7dfab7 JL |
4303 | return 0; |
4304 | ||
1525a29a | 4305 | domain = find_domain(dev); |
99dcaded FY |
4306 | if (!domain) |
4307 | return 0; | |
4308 | ||
e6de0f8d | 4309 | dmar_remove_one_dev_info(domain, dev); |
ab8dfe25 | 4310 | if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices)) |
7e7dfab7 | 4311 | domain_exit(domain); |
a97590e5 | 4312 | |
99dcaded FY |
4313 | return 0; |
4314 | } | |
4315 | ||
4316 | static struct notifier_block device_nb = { | |
4317 | .notifier_call = device_notifier, | |
4318 | }; | |
4319 | ||
75f05569 JL |
4320 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
4321 | unsigned long val, void *v) | |
4322 | { | |
4323 | struct memory_notify *mhp = v; | |
4324 | unsigned long long start, end; | |
4325 | unsigned long start_vpfn, last_vpfn; | |
4326 | ||
4327 | switch (val) { | |
4328 | case MEM_GOING_ONLINE: | |
4329 | start = mhp->start_pfn << PAGE_SHIFT; | |
4330 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; | |
4331 | if (iommu_domain_identity_map(si_domain, start, end)) { | |
9f10e5bf | 4332 | pr_warn("Failed to build identity map for [%llx-%llx]\n", |
75f05569 JL |
4333 | start, end); |
4334 | return NOTIFY_BAD; | |
4335 | } | |
4336 | break; | |
4337 | ||
4338 | case MEM_OFFLINE: | |
4339 | case MEM_CANCEL_ONLINE: | |
4340 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); | |
4341 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); | |
4342 | while (start_vpfn <= last_vpfn) { | |
4343 | struct iova *iova; | |
4344 | struct dmar_drhd_unit *drhd; | |
4345 | struct intel_iommu *iommu; | |
ea8ea460 | 4346 | struct page *freelist; |
75f05569 JL |
4347 | |
4348 | iova = find_iova(&si_domain->iovad, start_vpfn); | |
4349 | if (iova == NULL) { | |
9f10e5bf | 4350 | pr_debug("Failed get IOVA for PFN %lx\n", |
75f05569 JL |
4351 | start_vpfn); |
4352 | break; | |
4353 | } | |
4354 | ||
4355 | iova = split_and_remove_iova(&si_domain->iovad, iova, | |
4356 | start_vpfn, last_vpfn); | |
4357 | if (iova == NULL) { | |
9f10e5bf | 4358 | pr_warn("Failed to split IOVA PFN [%lx-%lx]\n", |
75f05569 JL |
4359 | start_vpfn, last_vpfn); |
4360 | return NOTIFY_BAD; | |
4361 | } | |
4362 | ||
ea8ea460 DW |
4363 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
4364 | iova->pfn_hi); | |
4365 | ||
75f05569 JL |
4366 | rcu_read_lock(); |
4367 | for_each_active_iommu(iommu, drhd) | |
a1ddcbe9 | 4368 | iommu_flush_iotlb_psi(iommu, si_domain, |
a156ef99 | 4369 | iova->pfn_lo, iova_size(iova), |
ea8ea460 | 4370 | !freelist, 0); |
75f05569 | 4371 | rcu_read_unlock(); |
ea8ea460 | 4372 | dma_free_pagelist(freelist); |
75f05569 JL |
4373 | |
4374 | start_vpfn = iova->pfn_hi + 1; | |
4375 | free_iova_mem(iova); | |
4376 | } | |
4377 | break; | |
4378 | } | |
4379 | ||
4380 | return NOTIFY_OK; | |
4381 | } | |
4382 | ||
4383 | static struct notifier_block intel_iommu_memory_nb = { | |
4384 | .notifier_call = intel_iommu_memory_notifier, | |
4385 | .priority = 0 | |
4386 | }; | |
4387 | ||
a5459cfe AW |
4388 | |
4389 | static ssize_t intel_iommu_show_version(struct device *dev, | |
4390 | struct device_attribute *attr, | |
4391 | char *buf) | |
4392 | { | |
4393 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4394 | u32 ver = readl(iommu->reg + DMAR_VER_REG); | |
4395 | return sprintf(buf, "%d:%d\n", | |
4396 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver)); | |
4397 | } | |
4398 | static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL); | |
4399 | ||
4400 | static ssize_t intel_iommu_show_address(struct device *dev, | |
4401 | struct device_attribute *attr, | |
4402 | char *buf) | |
4403 | { | |
4404 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4405 | return sprintf(buf, "%llx\n", iommu->reg_phys); | |
4406 | } | |
4407 | static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL); | |
4408 | ||
4409 | static ssize_t intel_iommu_show_cap(struct device *dev, | |
4410 | struct device_attribute *attr, | |
4411 | char *buf) | |
4412 | { | |
4413 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4414 | return sprintf(buf, "%llx\n", iommu->cap); | |
4415 | } | |
4416 | static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL); | |
4417 | ||
4418 | static ssize_t intel_iommu_show_ecap(struct device *dev, | |
4419 | struct device_attribute *attr, | |
4420 | char *buf) | |
4421 | { | |
4422 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4423 | return sprintf(buf, "%llx\n", iommu->ecap); | |
4424 | } | |
4425 | static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL); | |
4426 | ||
2238c082 AW |
4427 | static ssize_t intel_iommu_show_ndoms(struct device *dev, |
4428 | struct device_attribute *attr, | |
4429 | char *buf) | |
4430 | { | |
4431 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4432 | return sprintf(buf, "%ld\n", cap_ndoms(iommu->cap)); | |
4433 | } | |
4434 | static DEVICE_ATTR(domains_supported, S_IRUGO, intel_iommu_show_ndoms, NULL); | |
4435 | ||
4436 | static ssize_t intel_iommu_show_ndoms_used(struct device *dev, | |
4437 | struct device_attribute *attr, | |
4438 | char *buf) | |
4439 | { | |
4440 | struct intel_iommu *iommu = dev_get_drvdata(dev); | |
4441 | return sprintf(buf, "%d\n", bitmap_weight(iommu->domain_ids, | |
4442 | cap_ndoms(iommu->cap))); | |
4443 | } | |
4444 | static DEVICE_ATTR(domains_used, S_IRUGO, intel_iommu_show_ndoms_used, NULL); | |
4445 | ||
a5459cfe AW |
4446 | static struct attribute *intel_iommu_attrs[] = { |
4447 | &dev_attr_version.attr, | |
4448 | &dev_attr_address.attr, | |
4449 | &dev_attr_cap.attr, | |
4450 | &dev_attr_ecap.attr, | |
2238c082 AW |
4451 | &dev_attr_domains_supported.attr, |
4452 | &dev_attr_domains_used.attr, | |
a5459cfe AW |
4453 | NULL, |
4454 | }; | |
4455 | ||
4456 | static struct attribute_group intel_iommu_group = { | |
4457 | .name = "intel-iommu", | |
4458 | .attrs = intel_iommu_attrs, | |
4459 | }; | |
4460 | ||
4461 | const struct attribute_group *intel_iommu_groups[] = { | |
4462 | &intel_iommu_group, | |
4463 | NULL, | |
4464 | }; | |
4465 | ||
ba395927 KA |
4466 | int __init intel_iommu_init(void) |
4467 | { | |
9bdc531e | 4468 | int ret = -ENODEV; |
3a93c841 | 4469 | struct dmar_drhd_unit *drhd; |
7c919779 | 4470 | struct intel_iommu *iommu; |
ba395927 | 4471 | |
a59b50e9 JC |
4472 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
4473 | force_on = tboot_force_iommu(); | |
4474 | ||
3a5670e8 JL |
4475 | if (iommu_init_mempool()) { |
4476 | if (force_on) | |
4477 | panic("tboot: Failed to initialize iommu memory\n"); | |
4478 | return -ENOMEM; | |
4479 | } | |
4480 | ||
4481 | down_write(&dmar_global_lock); | |
a59b50e9 JC |
4482 | if (dmar_table_init()) { |
4483 | if (force_on) | |
4484 | panic("tboot: Failed to initialize DMAR table\n"); | |
9bdc531e | 4485 | goto out_free_dmar; |
a59b50e9 | 4486 | } |
ba395927 | 4487 | |
c2c7286a | 4488 | if (dmar_dev_scope_init() < 0) { |
a59b50e9 JC |
4489 | if (force_on) |
4490 | panic("tboot: Failed to initialize DMAR device scope\n"); | |
9bdc531e | 4491 | goto out_free_dmar; |
a59b50e9 | 4492 | } |
1886e8a9 | 4493 | |
75f1cdf1 | 4494 | if (no_iommu || dmar_disabled) |
9bdc531e | 4495 | goto out_free_dmar; |
2ae21010 | 4496 | |
318fe7df | 4497 | if (list_empty(&dmar_rmrr_units)) |
9f10e5bf | 4498 | pr_info("No RMRR found\n"); |
318fe7df SS |
4499 | |
4500 | if (list_empty(&dmar_atsr_units)) | |
9f10e5bf | 4501 | pr_info("No ATSR found\n"); |
318fe7df | 4502 | |
51a63e67 JC |
4503 | if (dmar_init_reserved_ranges()) { |
4504 | if (force_on) | |
4505 | panic("tboot: Failed to reserve iommu ranges\n"); | |
3a5670e8 | 4506 | goto out_free_reserved_range; |
51a63e67 | 4507 | } |
ba395927 KA |
4508 | |
4509 | init_no_remapping_devices(); | |
4510 | ||
b779260b | 4511 | ret = init_dmars(); |
ba395927 | 4512 | if (ret) { |
a59b50e9 JC |
4513 | if (force_on) |
4514 | panic("tboot: Failed to initialize DMARs\n"); | |
9f10e5bf | 4515 | pr_err("Initialization failed\n"); |
9bdc531e | 4516 | goto out_free_reserved_range; |
ba395927 | 4517 | } |
3a5670e8 | 4518 | up_write(&dmar_global_lock); |
9f10e5bf | 4519 | pr_info("Intel(R) Virtualization Technology for Directed I/O\n"); |
ba395927 | 4520 | |
5e0d2a6f | 4521 | init_timer(&unmap_timer); |
75f1cdf1 FT |
4522 | #ifdef CONFIG_SWIOTLB |
4523 | swiotlb = 0; | |
4524 | #endif | |
19943b0e | 4525 | dma_ops = &intel_dma_ops; |
4ed0d3e6 | 4526 | |
134fac3f | 4527 | init_iommu_pm_ops(); |
a8bcbb0d | 4528 | |
a5459cfe AW |
4529 | for_each_active_iommu(iommu, drhd) |
4530 | iommu->iommu_dev = iommu_device_create(NULL, iommu, | |
4531 | intel_iommu_groups, | |
2439d4aa | 4532 | "%s", iommu->name); |
a5459cfe | 4533 | |
4236d97d | 4534 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
99dcaded | 4535 | bus_register_notifier(&pci_bus_type, &device_nb); |
75f05569 JL |
4536 | if (si_domain && !hw_pass_through) |
4537 | register_memory_notifier(&intel_iommu_memory_nb); | |
99dcaded | 4538 | |
8bc1f85c ED |
4539 | intel_iommu_enabled = 1; |
4540 | ||
ba395927 | 4541 | return 0; |
9bdc531e JL |
4542 | |
4543 | out_free_reserved_range: | |
4544 | put_iova_domain(&reserved_iova_list); | |
9bdc531e JL |
4545 | out_free_dmar: |
4546 | intel_iommu_free_dmars(); | |
3a5670e8 JL |
4547 | up_write(&dmar_global_lock); |
4548 | iommu_exit_mempool(); | |
9bdc531e | 4549 | return ret; |
ba395927 | 4550 | } |
e820482c | 4551 | |
2452d9db | 4552 | static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
579305f7 AW |
4553 | { |
4554 | struct intel_iommu *iommu = opaque; | |
4555 | ||
2452d9db | 4556 | domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
579305f7 AW |
4557 | return 0; |
4558 | } | |
4559 | ||
4560 | /* | |
4561 | * NB - intel-iommu lacks any sort of reference counting for the users of | |
4562 | * dependent devices. If multiple endpoints have intersecting dependent | |
4563 | * devices, unbinding the driver from any one of them will possibly leave | |
4564 | * the others unable to operate. | |
4565 | */ | |
2452d9db | 4566 | static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) |
3199aa6b | 4567 | { |
0bcb3e28 | 4568 | if (!iommu || !dev || !dev_is_pci(dev)) |
3199aa6b HW |
4569 | return; |
4570 | ||
2452d9db | 4571 | pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); |
3199aa6b HW |
4572 | } |
4573 | ||
127c7615 | 4574 | static void __dmar_remove_one_dev_info(struct device_domain_info *info) |
c7151a8d | 4575 | { |
c7151a8d WH |
4576 | struct intel_iommu *iommu; |
4577 | unsigned long flags; | |
c7151a8d | 4578 | |
55d94043 JR |
4579 | assert_spin_locked(&device_domain_lock); |
4580 | ||
127c7615 | 4581 | if (WARN_ON(!info)) |
c7151a8d WH |
4582 | return; |
4583 | ||
127c7615 | 4584 | iommu = info->iommu; |
c7151a8d | 4585 | |
127c7615 JR |
4586 | if (info->dev) { |
4587 | iommu_disable_dev_iotlb(info); | |
4588 | domain_context_clear(iommu, info->dev); | |
4589 | } | |
c7151a8d | 4590 | |
b608ac3b | 4591 | unlink_domain_info(info); |
c7151a8d | 4592 | |
d160aca5 | 4593 | spin_lock_irqsave(&iommu->lock, flags); |
127c7615 | 4594 | domain_detach_iommu(info->domain, iommu); |
d160aca5 | 4595 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d | 4596 | |
127c7615 | 4597 | free_devinfo_mem(info); |
c7151a8d | 4598 | } |
c7151a8d | 4599 | |
55d94043 JR |
4600 | static void dmar_remove_one_dev_info(struct dmar_domain *domain, |
4601 | struct device *dev) | |
4602 | { | |
127c7615 | 4603 | struct device_domain_info *info; |
55d94043 | 4604 | unsigned long flags; |
3e7abe25 | 4605 | |
55d94043 | 4606 | spin_lock_irqsave(&device_domain_lock, flags); |
127c7615 JR |
4607 | info = dev->archdata.iommu; |
4608 | __dmar_remove_one_dev_info(info); | |
55d94043 | 4609 | spin_unlock_irqrestore(&device_domain_lock, flags); |
c7151a8d WH |
4610 | } |
4611 | ||
2c2e2c38 | 4612 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
4613 | { |
4614 | int adjust_width; | |
4615 | ||
0fb5fe87 RM |
4616 | init_iova_domain(&domain->iovad, VTD_PAGE_SIZE, IOVA_START_PFN, |
4617 | DMA_32BIT_PFN); | |
5e98c4b1 WH |
4618 | domain_reserve_special_ranges(domain); |
4619 | ||
4620 | /* calculate AGAW */ | |
4621 | domain->gaw = guest_width; | |
4622 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
4623 | domain->agaw = width_to_agaw(adjust_width); | |
4624 | ||
5e98c4b1 | 4625 | domain->iommu_coherency = 0; |
c5b15255 | 4626 | domain->iommu_snooping = 0; |
6dd9a7c7 | 4627 | domain->iommu_superpage = 0; |
fe40f1e0 | 4628 | domain->max_addr = 0; |
5e98c4b1 WH |
4629 | |
4630 | /* always allocate the top pgd */ | |
4c923d47 | 4631 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
5e98c4b1 WH |
4632 | if (!domain->pgd) |
4633 | return -ENOMEM; | |
4634 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
4635 | return 0; | |
4636 | } | |
4637 | ||
00a77deb | 4638 | static struct iommu_domain *intel_iommu_domain_alloc(unsigned type) |
38717946 | 4639 | { |
5d450806 | 4640 | struct dmar_domain *dmar_domain; |
00a77deb JR |
4641 | struct iommu_domain *domain; |
4642 | ||
4643 | if (type != IOMMU_DOMAIN_UNMANAGED) | |
4644 | return NULL; | |
38717946 | 4645 | |
ab8dfe25 | 4646 | dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE); |
5d450806 | 4647 | if (!dmar_domain) { |
9f10e5bf | 4648 | pr_err("Can't allocate dmar_domain\n"); |
00a77deb | 4649 | return NULL; |
38717946 | 4650 | } |
2c2e2c38 | 4651 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
9f10e5bf | 4652 | pr_err("Domain initialization failed\n"); |
92d03cc8 | 4653 | domain_exit(dmar_domain); |
00a77deb | 4654 | return NULL; |
38717946 | 4655 | } |
8140a95d | 4656 | domain_update_iommu_cap(dmar_domain); |
faa3d6f5 | 4657 | |
00a77deb | 4658 | domain = &dmar_domain->domain; |
8a0e715b JR |
4659 | domain->geometry.aperture_start = 0; |
4660 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); | |
4661 | domain->geometry.force_aperture = true; | |
4662 | ||
00a77deb | 4663 | return domain; |
38717946 | 4664 | } |
38717946 | 4665 | |
00a77deb | 4666 | static void intel_iommu_domain_free(struct iommu_domain *domain) |
38717946 | 4667 | { |
00a77deb | 4668 | domain_exit(to_dmar_domain(domain)); |
38717946 | 4669 | } |
38717946 | 4670 | |
4c5478c9 JR |
4671 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
4672 | struct device *dev) | |
38717946 | 4673 | { |
00a77deb | 4674 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
fe40f1e0 WH |
4675 | struct intel_iommu *iommu; |
4676 | int addr_width; | |
156baca8 | 4677 | u8 bus, devfn; |
faa3d6f5 | 4678 | |
c875d2c1 AW |
4679 | if (device_is_rmrr_locked(dev)) { |
4680 | dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n"); | |
4681 | return -EPERM; | |
4682 | } | |
4683 | ||
7207d8f9 DW |
4684 | /* normally dev is not mapped */ |
4685 | if (unlikely(domain_context_mapped(dev))) { | |
faa3d6f5 WH |
4686 | struct dmar_domain *old_domain; |
4687 | ||
1525a29a | 4688 | old_domain = find_domain(dev); |
faa3d6f5 | 4689 | if (old_domain) { |
d160aca5 | 4690 | rcu_read_lock(); |
de7e8886 | 4691 | dmar_remove_one_dev_info(old_domain, dev); |
d160aca5 | 4692 | rcu_read_unlock(); |
62c22167 JR |
4693 | |
4694 | if (!domain_type_is_vm_or_si(old_domain) && | |
4695 | list_empty(&old_domain->devices)) | |
4696 | domain_exit(old_domain); | |
faa3d6f5 WH |
4697 | } |
4698 | } | |
4699 | ||
156baca8 | 4700 | iommu = device_to_iommu(dev, &bus, &devfn); |
fe40f1e0 WH |
4701 | if (!iommu) |
4702 | return -ENODEV; | |
4703 | ||
4704 | /* check if this iommu agaw is sufficient for max mapped address */ | |
4705 | addr_width = agaw_to_width(iommu->agaw); | |
a99c47a2 TL |
4706 | if (addr_width > cap_mgaw(iommu->cap)) |
4707 | addr_width = cap_mgaw(iommu->cap); | |
4708 | ||
4709 | if (dmar_domain->max_addr > (1LL << addr_width)) { | |
9f10e5bf | 4710 | pr_err("%s: iommu width (%d) is not " |
fe40f1e0 | 4711 | "sufficient for the mapped address (%llx)\n", |
a99c47a2 | 4712 | __func__, addr_width, dmar_domain->max_addr); |
fe40f1e0 WH |
4713 | return -EFAULT; |
4714 | } | |
a99c47a2 TL |
4715 | dmar_domain->gaw = addr_width; |
4716 | ||
4717 | /* | |
4718 | * Knock out extra levels of page tables if necessary | |
4719 | */ | |
4720 | while (iommu->agaw < dmar_domain->agaw) { | |
4721 | struct dma_pte *pte; | |
4722 | ||
4723 | pte = dmar_domain->pgd; | |
4724 | if (dma_pte_present(pte)) { | |
25cbff16 SY |
4725 | dmar_domain->pgd = (struct dma_pte *) |
4726 | phys_to_virt(dma_pte_addr(pte)); | |
7a661013 | 4727 | free_pgtable_page(pte); |
a99c47a2 TL |
4728 | } |
4729 | dmar_domain->agaw--; | |
4730 | } | |
fe40f1e0 | 4731 | |
28ccce0d | 4732 | return domain_add_dev_info(dmar_domain, dev); |
38717946 | 4733 | } |
38717946 | 4734 | |
4c5478c9 JR |
4735 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
4736 | struct device *dev) | |
38717946 | 4737 | { |
e6de0f8d | 4738 | dmar_remove_one_dev_info(to_dmar_domain(domain), dev); |
faa3d6f5 | 4739 | } |
c7151a8d | 4740 | |
b146a1c9 JR |
4741 | static int intel_iommu_map(struct iommu_domain *domain, |
4742 | unsigned long iova, phys_addr_t hpa, | |
5009065d | 4743 | size_t size, int iommu_prot) |
faa3d6f5 | 4744 | { |
00a77deb | 4745 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
fe40f1e0 | 4746 | u64 max_addr; |
dde57a21 | 4747 | int prot = 0; |
faa3d6f5 | 4748 | int ret; |
fe40f1e0 | 4749 | |
dde57a21 JR |
4750 | if (iommu_prot & IOMMU_READ) |
4751 | prot |= DMA_PTE_READ; | |
4752 | if (iommu_prot & IOMMU_WRITE) | |
4753 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
4754 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
4755 | prot |= DMA_PTE_SNP; | |
dde57a21 | 4756 | |
163cc52c | 4757 | max_addr = iova + size; |
dde57a21 | 4758 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
4759 | u64 end; |
4760 | ||
4761 | /* check if minimum agaw is sufficient for mapped address */ | |
8954da1f | 4762 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
fe40f1e0 | 4763 | if (end < max_addr) { |
9f10e5bf | 4764 | pr_err("%s: iommu width (%d) is not " |
fe40f1e0 | 4765 | "sufficient for the mapped address (%llx)\n", |
8954da1f | 4766 | __func__, dmar_domain->gaw, max_addr); |
fe40f1e0 WH |
4767 | return -EFAULT; |
4768 | } | |
dde57a21 | 4769 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 4770 | } |
ad051221 DW |
4771 | /* Round up size to next multiple of PAGE_SIZE, if it and |
4772 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 4773 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
4774 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
4775 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 4776 | return ret; |
38717946 | 4777 | } |
38717946 | 4778 | |
5009065d | 4779 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
ea8ea460 | 4780 | unsigned long iova, size_t size) |
38717946 | 4781 | { |
00a77deb | 4782 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
ea8ea460 DW |
4783 | struct page *freelist = NULL; |
4784 | struct intel_iommu *iommu; | |
4785 | unsigned long start_pfn, last_pfn; | |
4786 | unsigned int npages; | |
42e8c186 | 4787 | int iommu_id, level = 0; |
5cf0a76f DW |
4788 | |
4789 | /* Cope with horrid API which requires us to unmap more than the | |
4790 | size argument if it happens to be a large-page mapping. */ | |
dc02e46e | 4791 | BUG_ON(!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)); |
5cf0a76f DW |
4792 | |
4793 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) | |
4794 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); | |
4b99d352 | 4795 | |
ea8ea460 DW |
4796 | start_pfn = iova >> VTD_PAGE_SHIFT; |
4797 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; | |
4798 | ||
4799 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); | |
4800 | ||
4801 | npages = last_pfn - start_pfn + 1; | |
4802 | ||
29a27719 | 4803 | for_each_domain_iommu(iommu_id, dmar_domain) { |
a1ddcbe9 | 4804 | iommu = g_iommus[iommu_id]; |
ea8ea460 | 4805 | |
42e8c186 JR |
4806 | iommu_flush_iotlb_psi(g_iommus[iommu_id], dmar_domain, |
4807 | start_pfn, npages, !freelist, 0); | |
ea8ea460 DW |
4808 | } |
4809 | ||
4810 | dma_free_pagelist(freelist); | |
fe40f1e0 | 4811 | |
163cc52c DW |
4812 | if (dmar_domain->max_addr == iova + size) |
4813 | dmar_domain->max_addr = iova; | |
b146a1c9 | 4814 | |
5cf0a76f | 4815 | return size; |
38717946 | 4816 | } |
38717946 | 4817 | |
d14d6577 | 4818 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
bb5547ac | 4819 | dma_addr_t iova) |
38717946 | 4820 | { |
00a77deb | 4821 | struct dmar_domain *dmar_domain = to_dmar_domain(domain); |
38717946 | 4822 | struct dma_pte *pte; |
5cf0a76f | 4823 | int level = 0; |
faa3d6f5 | 4824 | u64 phys = 0; |
38717946 | 4825 | |
5cf0a76f | 4826 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
38717946 | 4827 | if (pte) |
faa3d6f5 | 4828 | phys = dma_pte_addr(pte); |
38717946 | 4829 | |
faa3d6f5 | 4830 | return phys; |
38717946 | 4831 | } |
a8bcbb0d | 4832 | |
5d587b8d | 4833 | static bool intel_iommu_capable(enum iommu_cap cap) |
dbb9fd86 | 4834 | { |
dbb9fd86 | 4835 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
5d587b8d | 4836 | return domain_update_iommu_snooping(NULL) == 1; |
323f99cb | 4837 | if (cap == IOMMU_CAP_INTR_REMAP) |
5d587b8d | 4838 | return irq_remapping_enabled == 1; |
dbb9fd86 | 4839 | |
5d587b8d | 4840 | return false; |
dbb9fd86 SY |
4841 | } |
4842 | ||
abdfdde2 AW |
4843 | static int intel_iommu_add_device(struct device *dev) |
4844 | { | |
a5459cfe | 4845 | struct intel_iommu *iommu; |
abdfdde2 | 4846 | struct iommu_group *group; |
156baca8 | 4847 | u8 bus, devfn; |
70ae6f0d | 4848 | |
a5459cfe AW |
4849 | iommu = device_to_iommu(dev, &bus, &devfn); |
4850 | if (!iommu) | |
70ae6f0d AW |
4851 | return -ENODEV; |
4852 | ||
a5459cfe | 4853 | iommu_device_link(iommu->iommu_dev, dev); |
a4ff1fc2 | 4854 | |
e17f9ff4 | 4855 | group = iommu_group_get_for_dev(dev); |
783f157b | 4856 | |
e17f9ff4 AW |
4857 | if (IS_ERR(group)) |
4858 | return PTR_ERR(group); | |
bcb71abe | 4859 | |
abdfdde2 | 4860 | iommu_group_put(group); |
e17f9ff4 | 4861 | return 0; |
abdfdde2 | 4862 | } |
70ae6f0d | 4863 | |
abdfdde2 AW |
4864 | static void intel_iommu_remove_device(struct device *dev) |
4865 | { | |
a5459cfe AW |
4866 | struct intel_iommu *iommu; |
4867 | u8 bus, devfn; | |
4868 | ||
4869 | iommu = device_to_iommu(dev, &bus, &devfn); | |
4870 | if (!iommu) | |
4871 | return; | |
4872 | ||
abdfdde2 | 4873 | iommu_group_remove_device(dev); |
a5459cfe AW |
4874 | |
4875 | iommu_device_unlink(iommu->iommu_dev, dev); | |
70ae6f0d AW |
4876 | } |
4877 | ||
b22f6434 | 4878 | static const struct iommu_ops intel_iommu_ops = { |
5d587b8d | 4879 | .capable = intel_iommu_capable, |
00a77deb JR |
4880 | .domain_alloc = intel_iommu_domain_alloc, |
4881 | .domain_free = intel_iommu_domain_free, | |
a8bcbb0d JR |
4882 | .attach_dev = intel_iommu_attach_device, |
4883 | .detach_dev = intel_iommu_detach_device, | |
b146a1c9 JR |
4884 | .map = intel_iommu_map, |
4885 | .unmap = intel_iommu_unmap, | |
315786eb | 4886 | .map_sg = default_iommu_map_sg, |
a8bcbb0d | 4887 | .iova_to_phys = intel_iommu_iova_to_phys, |
abdfdde2 AW |
4888 | .add_device = intel_iommu_add_device, |
4889 | .remove_device = intel_iommu_remove_device, | |
6d1c56a9 | 4890 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
a8bcbb0d | 4891 | }; |
9af88143 | 4892 | |
9452618e DV |
4893 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
4894 | { | |
4895 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ | |
9f10e5bf | 4896 | pr_info("Disabling IOMMU for graphics on this chipset\n"); |
9452618e DV |
4897 | dmar_map_gfx = 0; |
4898 | } | |
4899 | ||
4900 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); | |
4901 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); | |
4902 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); | |
4903 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); | |
4904 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); | |
4905 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); | |
4906 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); | |
4907 | ||
d34d6517 | 4908 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
9af88143 DW |
4909 | { |
4910 | /* | |
4911 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
210561ff | 4912 | * but needs it. Same seems to hold for the desktop versions. |
9af88143 | 4913 | */ |
9f10e5bf | 4914 | pr_info("Forcing write-buffer flush capability\n"); |
9af88143 DW |
4915 | rwbf_quirk = 1; |
4916 | } | |
4917 | ||
4918 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | |
210561ff DV |
4919 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
4920 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | |
4921 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | |
4922 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | |
4923 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | |
4924 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | |
e0fc7e0b | 4925 | |
eecfd57f AJ |
4926 | #define GGC 0x52 |
4927 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | |
4928 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) | |
4929 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) | |
4930 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) | |
4931 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) | |
4932 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) | |
4933 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) | |
4934 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) | |
4935 | ||
d34d6517 | 4936 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
9eecabcb DW |
4937 | { |
4938 | unsigned short ggc; | |
4939 | ||
eecfd57f | 4940 | if (pci_read_config_word(dev, GGC, &ggc)) |
9eecabcb DW |
4941 | return; |
4942 | ||
eecfd57f | 4943 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
9f10e5bf | 4944 | pr_info("BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
9eecabcb | 4945 | dmar_map_gfx = 0; |
6fbcfb3e DW |
4946 | } else if (dmar_map_gfx) { |
4947 | /* we have to ensure the gfx device is idle before we flush */ | |
9f10e5bf | 4948 | pr_info("Disabling batched IOTLB flush on Ironlake\n"); |
6fbcfb3e DW |
4949 | intel_iommu_strict = 1; |
4950 | } | |
9eecabcb DW |
4951 | } |
4952 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); | |
4953 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); | |
4954 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); | |
4955 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); | |
4956 | ||
e0fc7e0b DW |
4957 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
4958 | ISOCH DMAR unit for the Azalia sound device, but not give it any | |
4959 | TLB entries, which causes it to deadlock. Check for that. We do | |
4960 | this in a function called from init_dmars(), instead of in a PCI | |
4961 | quirk, because we don't want to print the obnoxious "BIOS broken" | |
4962 | message if VT-d is actually disabled. | |
4963 | */ | |
4964 | static void __init check_tylersburg_isoch(void) | |
4965 | { | |
4966 | struct pci_dev *pdev; | |
4967 | uint32_t vtisochctrl; | |
4968 | ||
4969 | /* If there's no Azalia in the system anyway, forget it. */ | |
4970 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); | |
4971 | if (!pdev) | |
4972 | return; | |
4973 | pci_dev_put(pdev); | |
4974 | ||
4975 | /* System Management Registers. Might be hidden, in which case | |
4976 | we can't do the sanity check. But that's OK, because the | |
4977 | known-broken BIOSes _don't_ actually hide it, so far. */ | |
4978 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); | |
4979 | if (!pdev) | |
4980 | return; | |
4981 | ||
4982 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { | |
4983 | pci_dev_put(pdev); | |
4984 | return; | |
4985 | } | |
4986 | ||
4987 | pci_dev_put(pdev); | |
4988 | ||
4989 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ | |
4990 | if (vtisochctrl & 1) | |
4991 | return; | |
4992 | ||
4993 | /* Drop all bits other than the number of TLB entries */ | |
4994 | vtisochctrl &= 0x1c; | |
4995 | ||
4996 | /* If we have the recommended number of TLB entries (16), fine. */ | |
4997 | if (vtisochctrl == 0x10) | |
4998 | return; | |
4999 | ||
5000 | /* Zero TLB entries? You get to ride the short bus to school. */ | |
5001 | if (!vtisochctrl) { | |
5002 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" | |
5003 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
5004 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
5005 | dmi_get_system_info(DMI_BIOS_VERSION), | |
5006 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
5007 | iommu_identity_mapping |= IDENTMAP_AZALIA; | |
5008 | return; | |
5009 | } | |
9f10e5bf JR |
5010 | |
5011 | pr_warn("Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", | |
e0fc7e0b DW |
5012 | vtisochctrl); |
5013 | } |