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iommu/vt-d: Move private structures and variables into intel-iommu.c
[mirror_ubuntu-zesty-kernel.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927
KA		 1/*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
98bcef56 17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
5b6985ce 21 * Author: Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 22 */
23
24#include <linux/init.h>
25#include <linux/bitmap.h>
5e0d2a6f 26#include <linux/debugfs.h>
54485c30 27#include <linux/export.h>
ba395927
KA		 28#include <linux/slab.h>
29#include <linux/irq.h>
30#include <linux/interrupt.h>
ba395927
KA		 31#include <linux/spinlock.h>
32#include <linux/pci.h>
33#include <linux/dmar.h>
34#include <linux/dma-mapping.h>
35#include <linux/mempool.h>
5e0d2a6f 36#include <linux/timer.h>
38717946 37#include <linux/iova.h>
5d450806 38#include <linux/iommu.h>
38717946 39#include <linux/intel-iommu.h>
134fac3f 40#include <linux/syscore_ops.h>
69575d38 41#include <linux/tboot.h>
adb2fe02 42#include <linux/dmi.h>
5cdede24 43#include <linux/pci-ats.h>
0ee332c1 44#include <linux/memblock.h>
8a8f422d 45#include <asm/irq_remapping.h>
ba395927 46#include <asm/cacheflush.h>
46a7fa27 47#include <asm/iommu.h>
ba395927 48
078e1ee2 49#include "irq_remapping.h"
61e015ac 50#include "pci.h"
078e1ee2 51
5b6985ce
FY		 52#define ROOT_SIZE VTD_PAGE_SIZE
53#define CONTEXT_SIZE VTD_PAGE_SIZE
54
ba395927
KA		 55#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
56#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 57#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 58
59#define IOAPIC_RANGE_START (0xfee00000)
60#define IOAPIC_RANGE_END (0xfeefffff)
61#define IOVA_START_ADDR (0x1000)
62
63#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
64
4ed0d3e6 65#define MAX_AGAW_WIDTH 64
5c645b35 66#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 67
2ebe3151
DW		 68#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
69#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
70
71/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
72 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
73#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
74 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
75#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 76
f27be03b 77#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 78#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 79#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 80
df08cdc7
AM		 81/* page table handling */
82#define LEVEL_STRIDE (9)
83#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
84
6d1c56a9
OBC		 85/*
86 * This bitmap is used to advertise the page sizes our hardware support
87 * to the IOMMU core, which will then use this information to split
88 * physically contiguous memory regions it is mapping into page sizes
89 * that we support.
90 *
91 * Traditionally the IOMMU core just handed us the mappings directly,
92 * after making sure the size is an order of a 4KiB page and that the
93 * mapping has natural alignment.
94 *
95 * To retain this behavior, we currently advertise that we support
96 * all page sizes that are an order of 4KiB.
97 *
98 * If at some point we'd like to utilize the IOMMU core's new behavior,
99 * we could change this to advertise the real page sizes we support.
100 */
101#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
102
df08cdc7
AM		 103static inline int agaw_to_level(int agaw)
104{
105 return agaw + 2;
106}
107
108static inline int agaw_to_width(int agaw)
109{
5c645b35 110 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 111}
112
113static inline int width_to_agaw(int width)
114{
5c645b35 115 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 116}
117
118static inline unsigned int level_to_offset_bits(int level)
119{
120 return (level - 1) * LEVEL_STRIDE;
121}
122
123static inline int pfn_level_offset(unsigned long pfn, int level)
124{
125 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
126}
127
128static inline unsigned long level_mask(int level)
129{
130 return -1UL << level_to_offset_bits(level);
131}
132
133static inline unsigned long level_size(int level)
134{
135 return 1UL << level_to_offset_bits(level);
136}
137
138static inline unsigned long align_to_level(unsigned long pfn, int level)
139{
140 return (pfn + level_size(level) - 1) & level_mask(level);
141}
fd18de50 142
6dd9a7c7
YS		 143static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
144{
5c645b35 145 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 146}
147
dd4e8319
DW		 148/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
149 are never going to work. */
150static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
151{
152 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
153}
154
155static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
156{
157 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
158}
159static inline unsigned long page_to_dma_pfn(struct page *pg)
160{
161 return mm_to_dma_pfn(page_to_pfn(pg));
162}
163static inline unsigned long virt_to_dma_pfn(void *p)
164{
165 return page_to_dma_pfn(virt_to_page(p));
166}
167
d9630fe9
WH		 168/* global iommu list, set NULL for ignored DMAR units */
169static struct intel_iommu **g_iommus;
170
e0fc7e0b 171static void __init check_tylersburg_isoch(void);
9af88143
DW		 172static int rwbf_quirk;
173
b779260b
JC		 174/*
175 * set to 1 to panic kernel if can't successfully enable VT-d
176 * (used when kernel is launched w/ TXT)
177 */
178static int force_on = 0;
179
46b08e1a
MM		 180/*
181 * 0: Present
182 * 1-11: Reserved
183 * 12-63: Context Ptr (12 - (haw-1))
184 * 64-127: Reserved
185 */
186struct root_entry {
187 u64 val;
188 u64 rsvd1;
189};
190#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
191static inline bool root_present(struct root_entry *root)
192{
193 return (root->val & 1);
194}
195static inline void set_root_present(struct root_entry *root)
196{
197 root->val |= 1;
198}
199static inline void set_root_value(struct root_entry *root, unsigned long value)
200{
201 root->val |= value & VTD_PAGE_MASK;
202}
203
204static inline struct context_entry *
205get_context_addr_from_root(struct root_entry *root)
206{
207 return (struct context_entry *)
208 (root_present(root)?phys_to_virt(
209 root->val & VTD_PAGE_MASK) :
210 NULL);
211}
212
7a8fc25e
MM		 213/*
214 * low 64 bits:
215 * 0: present
216 * 1: fault processing disable
217 * 2-3: translation type
218 * 12-63: address space root
219 * high 64 bits:
220 * 0-2: address width
221 * 3-6: aval
222 * 8-23: domain id
223 */
224struct context_entry {
225 u64 lo;
226 u64 hi;
227};
c07e7d21
MM		 228
229static inline bool context_present(struct context_entry *context)
230{
231 return (context->lo & 1);
232}
233static inline void context_set_present(struct context_entry *context)
234{
235 context->lo |= 1;
236}
237
238static inline void context_set_fault_enable(struct context_entry *context)
239{
240 context->lo &= (((u64)-1) << 2) | 1;
241}
242
c07e7d21
MM		 243static inline void context_set_translation_type(struct context_entry *context,
244 unsigned long value)
245{
246 context->lo &= (((u64)-1) << 4) | 3;
247 context->lo |= (value & 3) << 2;
248}
249
250static inline void context_set_address_root(struct context_entry *context,
251 unsigned long value)
252{
253 context->lo |= value & VTD_PAGE_MASK;
254}
255
256static inline void context_set_address_width(struct context_entry *context,
257 unsigned long value)
258{
259 context->hi |= value & 7;
260}
261
262static inline void context_set_domain_id(struct context_entry *context,
263 unsigned long value)
264{
265 context->hi |= (value & ((1 << 16) - 1)) << 8;
266}
267
268static inline void context_clear_entry(struct context_entry *context)
269{
270 context->lo = 0;
271 context->hi = 0;
272}
7a8fc25e 273
622ba12a
MM		 274/*
275 * 0: readable
276 * 1: writable
277 * 2-6: reserved
278 * 7: super page
9cf06697
SY		 279 * 8-10: available
280 * 11: snoop behavior
622ba12a
MM		 281 * 12-63: Host physcial address
282 */
283struct dma_pte {
284 u64 val;
285};
622ba12a 286
19c239ce
MM		 287static inline void dma_clear_pte(struct dma_pte *pte)
288{
289 pte->val = 0;
290}
291
19c239ce
MM		 292static inline u64 dma_pte_addr(struct dma_pte *pte)
293{
c85994e4
DW		 294#ifdef CONFIG_64BIT
295 return pte->val & VTD_PAGE_MASK;
296#else
297 /* Must have a full atomic 64-bit read */
1a8bd481 298 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 299#endif
19c239ce
MM		 300}
301
19c239ce
MM		 302static inline bool dma_pte_present(struct dma_pte *pte)
303{
304 return (pte->val & 3) != 0;
305}
622ba12a 306
4399c8bf
AK		 307static inline bool dma_pte_superpage(struct dma_pte *pte)
308{
309 return (pte->val & (1 << 7));
310}
311
75e6bf96
DW		 312static inline int first_pte_in_page(struct dma_pte *pte)
313{
314 return !((unsigned long)pte & ~VTD_PAGE_MASK);
315}
316
2c2e2c38
FY		 317/*
318 * This domain is a statically identity mapping domain.
319 * 1. This domain creats a static 1:1 mapping to all usable memory.
320 * 2. It maps to each iommu if successful.
321 * 3. Each iommu mapps to this domain if successful.
322 */
19943b0e
DW		 323static struct dmar_domain *si_domain;
324static int hw_pass_through = 1;
2c2e2c38 325
3b5410e7 326/* devices under the same p2p bridge are owned in one domain */
cdc7b837 327#define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
3b5410e7 328
1ce28feb
WH		 329/* domain represents a virtual machine, more than one devices
330 * across iommus may be owned in one domain, e.g. kvm guest.
331 */
332#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
333
2c2e2c38
FY		 334/* si_domain contains mulitple devices */
335#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
336
1b198bb0
MT		 337/* define the limit of IOMMUs supported in each domain */
338#ifdef CONFIG_X86
339# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
340#else
341# define IOMMU_UNITS_SUPPORTED 64
342#endif
343
99126f7c
MM		 344struct dmar_domain {
345 int id; /* domain id */
4c923d47 346 int nid; /* node id */
1b198bb0
MT		 347 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
348 /* bitmap of iommus this domain uses*/
99126f7c
MM		 349
350 struct list_head devices; /* all devices' list */
351 struct iova_domain iovad; /* iova's that belong to this domain */
352
353 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 354 int gaw; /* max guest address width */
355
356 /* adjusted guest address width, 0 is level 2 30-bit */
357 int agaw;
358
3b5410e7 359 int flags; /* flags to find out type of domain */
8e604097
WH		 360
361 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 362 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 363 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 364 int iommu_superpage;/* Level of superpages supported:
365 0 == 4KiB (no superpages), 1 == 2MiB,
366 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 367 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 368 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 369};
370
a647dacb
MM		 371/* PCI domain-device relationship */
372struct device_domain_info {
373 struct list_head link; /* link to domain siblings */
374 struct list_head global; /* link to global list */
276dbf99
DW		 375 int segment; /* PCI domain */
376 u8 bus; /* PCI bus number */
a647dacb 377 u8 devfn; /* PCI devfn number */
45e829ea 378 struct pci_dev *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 379 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 380 struct dmar_domain *domain; /* pointer to domain */
381};
382
b94e4117
JL		 383struct dmar_rmrr_unit {
384 struct list_head list; /* list of rmrr units */
385 struct acpi_dmar_header *hdr; /* ACPI header */
386 u64 base_address; /* reserved base address*/
387 u64 end_address; /* reserved end address */
388 struct pci_dev **devices; /* target devices */
389 int devices_cnt; /* target device count */
390};
391
392struct dmar_atsr_unit {
393 struct list_head list; /* list of ATSR units */
394 struct acpi_dmar_header *hdr; /* ACPI header */
395 struct pci_dev **devices; /* target devices */
396 int devices_cnt; /* target device count */
397 u8 include_all:1; /* include all ports */
398};
399
400static LIST_HEAD(dmar_atsr_units);
401static LIST_HEAD(dmar_rmrr_units);
402
403#define for_each_rmrr_units(rmrr) \
404 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
405
5e0d2a6f 406static void flush_unmaps_timeout(unsigned long data);
407
b707cb02 408static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 409
80b20dd8 410#define HIGH_WATER_MARK 250
411struct deferred_flush_tables {
412 int next;
413 struct iova *iova[HIGH_WATER_MARK];
414 struct dmar_domain *domain[HIGH_WATER_MARK];
415};
416
417static struct deferred_flush_tables *deferred_flush;
418
5e0d2a6f 419/* bitmap for indexing intel_iommus */
5e0d2a6f 420static int g_num_of_iommus;
421
422static DEFINE_SPINLOCK(async_umap_flush_lock);
423static LIST_HEAD(unmaps_to_do);
424
425static int timer_on;
426static long list_size;
5e0d2a6f 427
ba395927 428static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117
JL		 429static void domain_remove_one_dev_info(struct dmar_domain *domain,
430 struct pci_dev *pdev);
ba395927 431
d3f13810 432#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 433int dmar_disabled = 0;
434#else
435int dmar_disabled = 1;
d3f13810 436#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 437
8bc1f85c
ED		 438int intel_iommu_enabled = 0;
439EXPORT_SYMBOL_GPL(intel_iommu_enabled);
440
2d9e667e 441static int dmar_map_gfx = 1;
7d3b03ce 442static int dmar_forcedac;
5e0d2a6f 443static int intel_iommu_strict;
6dd9a7c7 444static int intel_iommu_superpage = 1;
ba395927 445
c0771df8
DW		 446int intel_iommu_gfx_mapped;
447EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
448
ba395927
KA		 449#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
450static DEFINE_SPINLOCK(device_domain_lock);
451static LIST_HEAD(device_domain_list);
452
a8bcbb0d
JR		 453static struct iommu_ops intel_iommu_ops;
454
ba395927
KA		 455static int __init intel_iommu_setup(char *str)
456{
457 if (!str)
458 return -EINVAL;
459 while (*str) {
0cd5c3c8
KM		 460 if (!strncmp(str, "on", 2)) {
461 dmar_disabled = 0;
462 printk(KERN_INFO "Intel-IOMMU: enabled\n");
463 } else if (!strncmp(str, "off", 3)) {
ba395927 464 dmar_disabled = 1;
0cd5c3c8 465 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 466 } else if (!strncmp(str, "igfx_off", 8)) {
467 dmar_map_gfx = 0;
468 printk(KERN_INFO
469 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 470 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 471 printk(KERN_INFO
7d3b03ce
KA		 472 "Intel-IOMMU: Forcing DAC for PCI devices\n");
473 dmar_forcedac = 1;
5e0d2a6f 474 } else if (!strncmp(str, "strict", 6)) {
475 printk(KERN_INFO
476 "Intel-IOMMU: disable batched IOTLB flush\n");
477 intel_iommu_strict = 1;
6dd9a7c7
YS		 478 } else if (!strncmp(str, "sp_off", 6)) {
479 printk(KERN_INFO
480 "Intel-IOMMU: disable supported super page\n");
481 intel_iommu_superpage = 0;
ba395927
KA		 482 }
483
484 str += strcspn(str, ",");
485 while (*str == ',')
486 str++;
487 }
488 return 0;
489}
490__setup("intel_iommu=", intel_iommu_setup);
491
492static struct kmem_cache *iommu_domain_cache;
493static struct kmem_cache *iommu_devinfo_cache;
494static struct kmem_cache *iommu_iova_cache;
495
4c923d47 496static inline void *alloc_pgtable_page(int node)
eb3fa7cb 497{
4c923d47
SS		 498 struct page *page;
499 void *vaddr = NULL;
eb3fa7cb 500
4c923d47
SS		 501 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
502 if (page)
503 vaddr = page_address(page);
eb3fa7cb 504 return vaddr;
ba395927
KA		 505}
506
507static inline void free_pgtable_page(void *vaddr)
508{
509 free_page((unsigned long)vaddr);
510}
511
512static inline void *alloc_domain_mem(void)
513{
354bb65e 514 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 515}
516
38717946 517static void free_domain_mem(void *vaddr)
ba395927
KA		 518{
519 kmem_cache_free(iommu_domain_cache, vaddr);
520}
521
522static inline void * alloc_devinfo_mem(void)
523{
354bb65e 524 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 525}
526
527static inline void free_devinfo_mem(void *vaddr)
528{
529 kmem_cache_free(iommu_devinfo_cache, vaddr);
530}
531
532struct iova *alloc_iova_mem(void)
533{
354bb65e 534 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 535}
536
537void free_iova_mem(struct iova *iova)
538{
539 kmem_cache_free(iommu_iova_cache, iova);
540}
541
1b573683 542
4ed0d3e6 543static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 544{
545 unsigned long sagaw;
546 int agaw = -1;
547
548 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 549 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 550 agaw >= 0; agaw--) {
551 if (test_bit(agaw, &sagaw))
552 break;
553 }
554
555 return agaw;
556}
557
4ed0d3e6
FY		 558/*
559 * Calculate max SAGAW for each iommu.
560 */
561int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
562{
563 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
564}
565
566/*
567 * calculate agaw for each iommu.
568 * "SAGAW" may be different across iommus, use a default agaw, and
569 * get a supported less agaw for iommus that don't support the default agaw.
570 */
571int iommu_calculate_agaw(struct intel_iommu *iommu)
572{
573 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
574}
575
2c2e2c38 576/* This functionin only returns single iommu in a domain */
8c11e798
WH		 577static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
578{
579 int iommu_id;
580
2c2e2c38 581 /* si_domain and vm domain should not get here. */
1ce28feb 582 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
2c2e2c38 583 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
1ce28feb 584
1b198bb0 585 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 586 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
587 return NULL;
588
589 return g_iommus[iommu_id];
590}
591
8e604097
WH		 592static void domain_update_iommu_coherency(struct dmar_domain *domain)
593{
594 int i;
595
2e12bc29
AW		 596 i = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
597
598 domain->iommu_coherency = i < g_num_of_iommus ? 1 : 0;
8e604097 599
1b198bb0 600 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
8e604097
WH		 601 if (!ecap_coherent(g_iommus[i]->ecap)) {
602 domain->iommu_coherency = 0;
603 break;
604 }
8e604097
WH		 605 }
606}
607
58c610bd
SY		 608static void domain_update_iommu_snooping(struct dmar_domain *domain)
609{
610 int i;
611
612 domain->iommu_snooping = 1;
613
1b198bb0 614 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 615 if (!ecap_sc_support(g_iommus[i]->ecap)) {
616 domain->iommu_snooping = 0;
617 break;
618 }
58c610bd
SY		 619 }
620}
621
6dd9a7c7
YS		 622static void domain_update_iommu_superpage(struct dmar_domain *domain)
623{
8140a95d
AK		 624 struct dmar_drhd_unit *drhd;
625 struct intel_iommu *iommu = NULL;
626 int mask = 0xf;
6dd9a7c7
YS		 627
628 if (!intel_iommu_superpage) {
629 domain->iommu_superpage = 0;
630 return;
631 }
632
8140a95d
AK		 633 /* set iommu_superpage to the smallest common denominator */
634 for_each_active_iommu(iommu, drhd) {
635 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 636 if (!mask) {
637 break;
638 }
639 }
640 domain->iommu_superpage = fls(mask);
641}
642
58c610bd
SY		 643/* Some capabilities may be different across iommus */
644static void domain_update_iommu_cap(struct dmar_domain *domain)
645{
646 domain_update_iommu_coherency(domain);
647 domain_update_iommu_snooping(domain);
6dd9a7c7 648 domain_update_iommu_superpage(domain);
58c610bd
SY		 649}
650
276dbf99 651static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
c7151a8d
WH		 652{
653 struct dmar_drhd_unit *drhd = NULL;
654 int i;
655
7c919779 656 for_each_active_drhd_unit(drhd) {
276dbf99
DW		 657 if (segment != drhd->segment)
658 continue;
c7151a8d 659
924b6231 660 for (i = 0; i < drhd->devices_cnt; i++) {
288e4877
DH		 661 if (drhd->devices[i] &&
662 drhd->devices[i]->bus->number == bus &&
c7151a8d
WH		 663 drhd->devices[i]->devfn == devfn)
664 return drhd->iommu;
4958c5dc
DW		 665 if (drhd->devices[i] &&
666 drhd->devices[i]->subordinate &&
924b6231 667 drhd->devices[i]->subordinate->number <= bus &&
b918c62e 668 drhd->devices[i]->subordinate->busn_res.end >= bus)
924b6231
DW		 669 return drhd->iommu;
670 }
c7151a8d
WH		 671
672 if (drhd->include_all)
673 return drhd->iommu;
674 }
675
676 return NULL;
677}
678
5331fe6f
WH		 679static void domain_flush_cache(struct dmar_domain *domain,
680 void *addr, int size)
681{
682 if (!domain->iommu_coherency)
683 clflush_cache_range(addr, size);
684}
685
ba395927
KA		 686/* Gets context entry for a given bus and devfn */
687static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
688 u8 bus, u8 devfn)
689{
690 struct root_entry *root;
691 struct context_entry *context;
692 unsigned long phy_addr;
693 unsigned long flags;
694
695 spin_lock_irqsave(&iommu->lock, flags);
696 root = &iommu->root_entry[bus];
697 context = get_context_addr_from_root(root);
698 if (!context) {
4c923d47
SS		 699 context = (struct context_entry *)
700 alloc_pgtable_page(iommu->node);
ba395927
KA		 701 if (!context) {
702 spin_unlock_irqrestore(&iommu->lock, flags);
703 return NULL;
704 }
5b6985ce 705 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 706 phy_addr = virt_to_phys((void *)context);
707 set_root_value(root, phy_addr);
708 set_root_present(root);
709 __iommu_flush_cache(iommu, root, sizeof(*root));
710 }
711 spin_unlock_irqrestore(&iommu->lock, flags);
712 return &context[devfn];
713}
714
715static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
716{
717 struct root_entry *root;
718 struct context_entry *context;
719 int ret;
720 unsigned long flags;
721
722 spin_lock_irqsave(&iommu->lock, flags);
723 root = &iommu->root_entry[bus];
724 context = get_context_addr_from_root(root);
725 if (!context) {
726 ret = 0;
727 goto out;
728 }
c07e7d21 729 ret = context_present(&context[devfn]);
ba395927
KA		 730out:
731 spin_unlock_irqrestore(&iommu->lock, flags);
732 return ret;
733}
734
735static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
736{
737 struct root_entry *root;
738 struct context_entry *context;
739 unsigned long flags;
740
741 spin_lock_irqsave(&iommu->lock, flags);
742 root = &iommu->root_entry[bus];
743 context = get_context_addr_from_root(root);
744 if (context) {
c07e7d21 745 context_clear_entry(&context[devfn]);
ba395927
KA		 746 __iommu_flush_cache(iommu, &context[devfn], \
747 sizeof(*context));
748 }
749 spin_unlock_irqrestore(&iommu->lock, flags);
750}
751
752static void free_context_table(struct intel_iommu *iommu)
753{
754 struct root_entry *root;
755 int i;
756 unsigned long flags;
757 struct context_entry *context;
758
759 spin_lock_irqsave(&iommu->lock, flags);
760 if (!iommu->root_entry) {
761 goto out;
762 }
763 for (i = 0; i < ROOT_ENTRY_NR; i++) {
764 root = &iommu->root_entry[i];
765 context = get_context_addr_from_root(root);
766 if (context)
767 free_pgtable_page(context);
768 }
769 free_pgtable_page(iommu->root_entry);
770 iommu->root_entry = NULL;
771out:
772 spin_unlock_irqrestore(&iommu->lock, flags);
773}
774
b026fd28 775static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
4399c8bf 776 unsigned long pfn, int target_level)
ba395927 777{
b026fd28 778 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 779 struct dma_pte *parent, *pte = NULL;
780 int level = agaw_to_level(domain->agaw);
4399c8bf 781 int offset;
ba395927
KA		 782
783 BUG_ON(!domain->pgd);
f9423606
JS		 784
785 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
786 /* Address beyond IOMMU's addressing capabilities. */
787 return NULL;
788
ba395927
KA		 789 parent = domain->pgd;
790
ba395927
KA		 791 while (level > 0) {
792 void *tmp_page;
793
b026fd28 794 offset = pfn_level_offset(pfn, level);
ba395927 795 pte = &parent[offset];
4399c8bf 796 if (!target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7
YS		 797 break;
798 if (level == target_level)
ba395927
KA		 799 break;
800
19c239ce 801 if (!dma_pte_present(pte)) {
c85994e4
DW		 802 uint64_t pteval;
803
4c923d47 804 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 805
206a73c1 806 if (!tmp_page)
ba395927 807 return NULL;
206a73c1 808
c85994e4 809 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 810 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
c85994e4
DW		 811 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
812 /* Someone else set it while we were thinking; use theirs. */
813 free_pgtable_page(tmp_page);
814 } else {
815 dma_pte_addr(pte);
816 domain_flush_cache(domain, pte, sizeof(*pte));
817 }
ba395927 818 }
19c239ce 819 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 820 level--;
821 }
822
ba395927
KA		 823 return pte;
824}
825
6dd9a7c7 826
ba395927 827/* return address's pte at specific level */
90dcfb5e
DW		 828static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
829 unsigned long pfn,
6dd9a7c7 830 int level, int *large_page)
ba395927
KA		 831{
832 struct dma_pte *parent, *pte = NULL;
833 int total = agaw_to_level(domain->agaw);
834 int offset;
835
836 parent = domain->pgd;
837 while (level <= total) {
90dcfb5e 838 offset = pfn_level_offset(pfn, total);
ba395927
KA		 839 pte = &parent[offset];
840 if (level == total)
841 return pte;
842
6dd9a7c7
YS		 843 if (!dma_pte_present(pte)) {
844 *large_page = total;
ba395927 845 break;
6dd9a7c7
YS		 846 }
847
848 if (pte->val & DMA_PTE_LARGE_PAGE) {
849 *large_page = total;
850 return pte;
851 }
852
19c239ce 853 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 854 total--;
855 }
856 return NULL;
857}
858
ba395927 859/* clear last level pte, a tlb flush should be followed */
292827cb 860static int dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 861 unsigned long start_pfn,
862 unsigned long last_pfn)
ba395927 863{
04b18e65 864 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 865 unsigned int large_page = 1;
310a5ab9 866 struct dma_pte *first_pte, *pte;
66eae846 867
04b18e65 868 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 869 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 870 BUG_ON(start_pfn > last_pfn);
ba395927 871
04b18e65 872 /* we don't need lock here; nobody else touches the iova range */
59c36286 873 do {
6dd9a7c7
YS		 874 large_page = 1;
875 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 876 if (!pte) {
6dd9a7c7 877 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 878 continue;
879 }
6dd9a7c7 880 do {
310a5ab9 881 dma_clear_pte(pte);
6dd9a7c7 882 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 883 pte++;
75e6bf96
DW		 884 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
885
310a5ab9
DW		 886 domain_flush_cache(domain, first_pte,
887 (void *)pte - (void *)first_pte);
59c36286
DW		 888
889 } while (start_pfn && start_pfn <= last_pfn);
292827cb 890
5c645b35 891 return min_t(int, (large_page - 1) * 9, MAX_AGAW_PFN_WIDTH);
ba395927
KA		 892}
893
3269ee0b
AW		 894static void dma_pte_free_level(struct dmar_domain *domain, int level,
895 struct dma_pte *pte, unsigned long pfn,
896 unsigned long start_pfn, unsigned long last_pfn)
897{
898 pfn = max(start_pfn, pfn);
899 pte = &pte[pfn_level_offset(pfn, level)];
900
901 do {
902 unsigned long level_pfn;
903 struct dma_pte *level_pte;
904
905 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
906 goto next;
907
908 level_pfn = pfn & level_mask(level - 1);
909 level_pte = phys_to_virt(dma_pte_addr(pte));
910
911 if (level > 2)
912 dma_pte_free_level(domain, level - 1, level_pte,
913 level_pfn, start_pfn, last_pfn);
914
915 /* If range covers entire pagetable, free it */
916 if (!(start_pfn > level_pfn ||
08336fd2 917 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 918 dma_clear_pte(pte);
919 domain_flush_cache(domain, pte, sizeof(*pte));
920 free_pgtable_page(level_pte);
921 }
922next:
923 pfn += level_size(level);
924 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
925}
926
ba395927
KA		 927/* free page table pages. last level pte should already be cleared */
928static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 929 unsigned long start_pfn,
930 unsigned long last_pfn)
ba395927 931{
6660c63a 932 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 933
6660c63a
DW		 934 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
935 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 936 BUG_ON(start_pfn > last_pfn);
ba395927 937
f3a0a52f 938 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 939 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
940 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 941
ba395927 942 /* free pgd */
d794dc9b 943 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 944 free_pgtable_page(domain->pgd);
945 domain->pgd = NULL;
946 }
947}
948
949/* iommu handling */
950static int iommu_alloc_root_entry(struct intel_iommu *iommu)
951{
952 struct root_entry *root;
953 unsigned long flags;
954
4c923d47 955 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 956 if (!root)
957 return -ENOMEM;
958
5b6985ce 959 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 960
961 spin_lock_irqsave(&iommu->lock, flags);
962 iommu->root_entry = root;
963 spin_unlock_irqrestore(&iommu->lock, flags);
964
965 return 0;
966}
967
ba395927
KA		 968static void iommu_set_root_entry(struct intel_iommu *iommu)
969{
970 void *addr;
c416daa9 971 u32 sts;
ba395927
KA		 972 unsigned long flag;
973
974 addr = iommu->root_entry;
975
1f5b3c3f 976 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 977 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
978
c416daa9 979 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 980
981 /* Make sure hardware complete it */
982 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 983 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 984
1f5b3c3f 985 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 986}
987
988static void iommu_flush_write_buffer(struct intel_iommu *iommu)
989{
990 u32 val;
991 unsigned long flag;
992
9af88143 993 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 994 return;
ba395927 995
1f5b3c3f 996 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 997 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 998
999 /* Make sure hardware complete it */
1000 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1001 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1002
1f5b3c3f 1003 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1004}
1005
1006/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1007static void __iommu_flush_context(struct intel_iommu *iommu,
1008 u16 did, u16 source_id, u8 function_mask,
1009 u64 type)
ba395927
KA		 1010{
1011 u64 val = 0;
1012 unsigned long flag;
1013
ba395927
KA		 1014 switch (type) {
1015 case DMA_CCMD_GLOBAL_INVL:
1016 val = DMA_CCMD_GLOBAL_INVL;
1017 break;
1018 case DMA_CCMD_DOMAIN_INVL:
1019 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1020 break;
1021 case DMA_CCMD_DEVICE_INVL:
1022 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1023 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1024 break;
1025 default:
1026 BUG();
1027 }
1028 val |= DMA_CCMD_ICC;
1029
1f5b3c3f 1030 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1031 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1032
1033 /* Make sure hardware complete it */
1034 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1035 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1036
1f5b3c3f 1037 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1038}
1039
ba395927 1040/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1041static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1042 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1043{
1044 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1045 u64 val = 0, val_iva = 0;
1046 unsigned long flag;
1047
ba395927
KA		 1048 switch (type) {
1049 case DMA_TLB_GLOBAL_FLUSH:
1050 /* global flush doesn't need set IVA_REG */
1051 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1052 break;
1053 case DMA_TLB_DSI_FLUSH:
1054 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1055 break;
1056 case DMA_TLB_PSI_FLUSH:
1057 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1058 /* Note: always flush non-leaf currently */
1059 val_iva = size_order | addr;
1060 break;
1061 default:
1062 BUG();
1063 }
1064 /* Note: set drain read/write */
1065#if 0
1066 /*
1067 * This is probably to be super secure.. Looks like we can
1068 * ignore it without any impact.
1069 */
1070 if (cap_read_drain(iommu->cap))
1071 val |= DMA_TLB_READ_DRAIN;
1072#endif
1073 if (cap_write_drain(iommu->cap))
1074 val |= DMA_TLB_WRITE_DRAIN;
1075
1f5b3c3f 1076 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1077 /* Note: Only uses first TLB reg currently */
1078 if (val_iva)
1079 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1080 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1081
1082 /* Make sure hardware complete it */
1083 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1084 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1085
1f5b3c3f 1086 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1087
1088 /* check IOTLB invalidation granularity */
1089 if (DMA_TLB_IAIG(val) == 0)
1090 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1091 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1092 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1093 (unsigned long long)DMA_TLB_IIRG(type),
1094 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1095}
1096
93a23a72
YZ		 1097static struct device_domain_info *iommu_support_dev_iotlb(
1098 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1099{
1100 int found = 0;
1101 unsigned long flags;
1102 struct device_domain_info *info;
1103 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1104
1105 if (!ecap_dev_iotlb_support(iommu->ecap))
1106 return NULL;
1107
1108 if (!iommu->qi)
1109 return NULL;
1110
1111 spin_lock_irqsave(&device_domain_lock, flags);
1112 list_for_each_entry(info, &domain->devices, link)
1113 if (info->bus == bus && info->devfn == devfn) {
1114 found = 1;
1115 break;
1116 }
1117 spin_unlock_irqrestore(&device_domain_lock, flags);
1118
1119 if (!found || !info->dev)
1120 return NULL;
1121
1122 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1123 return NULL;
1124
1125 if (!dmar_find_matched_atsr_unit(info->dev))
1126 return NULL;
1127
1128 info->iommu = iommu;
1129
1130 return info;
1131}
1132
1133static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1134{
93a23a72
YZ		 1135 if (!info)
1136 return;
1137
1138 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1139}
1140
1141static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1142{
1143 if (!info->dev || !pci_ats_enabled(info->dev))
1144 return;
1145
1146 pci_disable_ats(info->dev);
1147}
1148
1149static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1150 u64 addr, unsigned mask)
1151{
1152 u16 sid, qdep;
1153 unsigned long flags;
1154 struct device_domain_info *info;
1155
1156 spin_lock_irqsave(&device_domain_lock, flags);
1157 list_for_each_entry(info, &domain->devices, link) {
1158 if (!info->dev || !pci_ats_enabled(info->dev))
1159 continue;
1160
1161 sid = info->bus << 8 | info->devfn;
1162 qdep = pci_ats_queue_depth(info->dev);
1163 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1164 }
1165 spin_unlock_irqrestore(&device_domain_lock, flags);
1166}
1167
1f0ef2aa 1168static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
82653633 1169 unsigned long pfn, unsigned int pages, int map)
ba395927 1170{
9dd2fe89 1171 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1172 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1173
ba395927
KA		 1174 BUG_ON(pages == 0);
1175
ba395927 1176 /*
9dd2fe89
YZ		 1177 * Fallback to domain selective flush if no PSI support or the size is
1178 * too big.
ba395927
KA		 1179 * PSI requires page size to be 2 ^ x, and the base address is naturally
1180 * aligned to the size
1181 */
9dd2fe89
YZ		 1182 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1183 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1184 DMA_TLB_DSI_FLUSH);
9dd2fe89
YZ		 1185 else
1186 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1187 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1188
1189 /*
82653633
NA		 1190 * In caching mode, changes of pages from non-present to present require
1191 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1192 */
82653633 1193 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1194 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1195}
1196
f8bab735 1197static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1198{
1199 u32 pmen;
1200 unsigned long flags;
1201
1f5b3c3f 1202 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1203 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1204 pmen &= ~DMA_PMEN_EPM;
1205 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1206
1207 /* wait for the protected region status bit to clear */
1208 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1209 readl, !(pmen & DMA_PMEN_PRS), pmen);
1210
1f5b3c3f 1211 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1212}
1213
ba395927
KA		 1214static int iommu_enable_translation(struct intel_iommu *iommu)
1215{
1216 u32 sts;
1217 unsigned long flags;
1218
1f5b3c3f 1219 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1220 iommu->gcmd |= DMA_GCMD_TE;
1221 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1222
1223 /* Make sure hardware complete it */
1224 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1225 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1226
1f5b3c3f 1227 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1228 return 0;
1229}
1230
1231static int iommu_disable_translation(struct intel_iommu *iommu)
1232{
1233 u32 sts;
1234 unsigned long flag;
1235
1f5b3c3f 1236 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1237 iommu->gcmd &= ~DMA_GCMD_TE;
1238 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1239
1240 /* Make sure hardware complete it */
1241 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1242 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1243
1f5b3c3f 1244 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1245 return 0;
1246}
1247
3460a6d9 1248
ba395927
KA		 1249static int iommu_init_domains(struct intel_iommu *iommu)
1250{
1251 unsigned long ndomains;
1252 unsigned long nlongs;
1253
1254 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1255 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1256 iommu->seq_id, ndomains);
ba395927
KA		 1257 nlongs = BITS_TO_LONGS(ndomains);
1258
94a91b50
DD		 1259 spin_lock_init(&iommu->lock);
1260
ba395927
KA		 1261 /* TBD: there might be 64K domains,
1262 * consider other allocation for future chip
1263 */
1264 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1265 if (!iommu->domain_ids) {
852bdb04
JL		 1266 pr_err("IOMMU%d: allocating domain id array failed\n",
1267 iommu->seq_id);
ba395927
KA		 1268 return -ENOMEM;
1269 }
1270 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1271 GFP_KERNEL);
1272 if (!iommu->domains) {
852bdb04
JL		 1273 pr_err("IOMMU%d: allocating domain array failed\n",
1274 iommu->seq_id);
1275 kfree(iommu->domain_ids);
1276 iommu->domain_ids = NULL;
ba395927
KA		 1277 return -ENOMEM;
1278 }
1279
1280 /*
1281 * if Caching mode is set, then invalid translations are tagged
1282 * with domainid 0. Hence we need to pre-allocate it.
1283 */
1284 if (cap_caching_mode(iommu->cap))
1285 set_bit(0, iommu->domain_ids);
1286 return 0;
1287}
ba395927 1288
ba395927
KA		 1289
1290static void domain_exit(struct dmar_domain *domain);
5e98c4b1 1291static void vm_domain_exit(struct dmar_domain *domain);
e61d98d8 1292
a868e6b7 1293static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1294{
1295 struct dmar_domain *domain;
5ced12af 1296 int i, count;
c7151a8d 1297 unsigned long flags;
ba395927 1298
94a91b50 1299 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1300 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
94a91b50
DD		 1301 domain = iommu->domains[i];
1302 clear_bit(i, iommu->domain_ids);
1303
1304 spin_lock_irqsave(&domain->iommu_lock, flags);
5ced12af
JL		 1305 count = --domain->iommu_count;
1306 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1307 if (count == 0) {
94a91b50
DD		 1308 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1309 vm_domain_exit(domain);
1310 else
1311 domain_exit(domain);
1312 }
5e98c4b1 1313 }
ba395927
KA		 1314 }
1315
1316 if (iommu->gcmd & DMA_GCMD_TE)
1317 iommu_disable_translation(iommu);
1318
ba395927
KA		 1319 kfree(iommu->domains);
1320 kfree(iommu->domain_ids);
a868e6b7
JL		 1321 iommu->domains = NULL;
1322 iommu->domain_ids = NULL;
ba395927 1323
d9630fe9
WH		 1324 g_iommus[iommu->seq_id] = NULL;
1325
ba395927
KA		 1326 /* free context mapping */
1327 free_context_table(iommu);
ba395927
KA		 1328}
1329
2c2e2c38 1330static struct dmar_domain *alloc_domain(void)
ba395927 1331{
ba395927 1332 struct dmar_domain *domain;
ba395927
KA		 1333
1334 domain = alloc_domain_mem();
1335 if (!domain)
1336 return NULL;
1337
4c923d47 1338 domain->nid = -1;
1b198bb0 1339 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
2c2e2c38
FY		 1340 domain->flags = 0;
1341
1342 return domain;
1343}
1344
1345static int iommu_attach_domain(struct dmar_domain *domain,
1346 struct intel_iommu *iommu)
1347{
1348 int num;
1349 unsigned long ndomains;
1350 unsigned long flags;
1351
ba395927
KA		 1352 ndomains = cap_ndoms(iommu->cap);
1353
1354 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1355
ba395927
KA		 1356 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1357 if (num >= ndomains) {
1358 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927 1359 printk(KERN_ERR "IOMMU: no free domain ids\n");
2c2e2c38 1360 return -ENOMEM;
ba395927
KA		 1361 }
1362
ba395927 1363 domain->id = num;
2c2e2c38 1364 set_bit(num, iommu->domain_ids);
1b198bb0 1365 set_bit(iommu->seq_id, domain->iommu_bmp);
ba395927
KA		 1366 iommu->domains[num] = domain;
1367 spin_unlock_irqrestore(&iommu->lock, flags);
1368
2c2e2c38 1369 return 0;
ba395927
KA		 1370}
1371
2c2e2c38
FY		 1372static void iommu_detach_domain(struct dmar_domain *domain,
1373 struct intel_iommu *iommu)
ba395927
KA		 1374{
1375 unsigned long flags;
2c2e2c38
FY		 1376 int num, ndomains;
1377 int found = 0;
ba395927 1378
8c11e798 1379 spin_lock_irqsave(&iommu->lock, flags);
2c2e2c38 1380 ndomains = cap_ndoms(iommu->cap);
a45946ab 1381 for_each_set_bit(num, iommu->domain_ids, ndomains) {
2c2e2c38
FY		 1382 if (iommu->domains[num] == domain) {
1383 found = 1;
1384 break;
1385 }
2c2e2c38
FY		 1386 }
1387
1388 if (found) {
1389 clear_bit(num, iommu->domain_ids);
1b198bb0 1390 clear_bit(iommu->seq_id, domain->iommu_bmp);
2c2e2c38
FY		 1391 iommu->domains[num] = NULL;
1392 }
8c11e798 1393 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1394}
1395
1396static struct iova_domain reserved_iova_list;
8a443df4 1397static struct lock_class_key reserved_rbtree_key;
ba395927 1398
51a63e67 1399static int dmar_init_reserved_ranges(void)
ba395927
KA		 1400{
1401 struct pci_dev *pdev = NULL;
1402 struct iova *iova;
1403 int i;
ba395927 1404
f661197e 1405 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1406
8a443df4
MG		 1407 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1408 &reserved_rbtree_key);
1409
ba395927
KA		 1410 /* IOAPIC ranges shouldn't be accessed by DMA */
1411 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1412 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1413 if (!iova) {
ba395927 1414 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1415 return -ENODEV;
1416 }
ba395927
KA		 1417
1418 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1419 for_each_pci_dev(pdev) {
1420 struct resource *r;
1421
1422 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1423 r = &pdev->resource[i];
1424 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1425 continue;
1a4a4551
DW		 1426 iova = reserve_iova(&reserved_iova_list,
1427 IOVA_PFN(r->start),
1428 IOVA_PFN(r->end));
51a63e67 1429 if (!iova) {
ba395927 1430 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1431 return -ENODEV;
1432 }
ba395927
KA		 1433 }
1434 }
51a63e67 1435 return 0;
ba395927
KA		 1436}
1437
1438static void domain_reserve_special_ranges(struct dmar_domain *domain)
1439{
1440 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1441}
1442
1443static inline int guestwidth_to_adjustwidth(int gaw)
1444{
1445 int agaw;
1446 int r = (gaw - 12) % 9;
1447
1448 if (r == 0)
1449 agaw = gaw;
1450 else
1451 agaw = gaw + 9 - r;
1452 if (agaw > 64)
1453 agaw = 64;
1454 return agaw;
1455}
1456
1457static int domain_init(struct dmar_domain *domain, int guest_width)
1458{
1459 struct intel_iommu *iommu;
1460 int adjust_width, agaw;
1461 unsigned long sagaw;
1462
f661197e 1463 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
c7151a8d 1464 spin_lock_init(&domain->iommu_lock);
ba395927
KA		 1465
1466 domain_reserve_special_ranges(domain);
1467
1468 /* calculate AGAW */
8c11e798 1469 iommu = domain_get_iommu(domain);
ba395927
KA		 1470 if (guest_width > cap_mgaw(iommu->cap))
1471 guest_width = cap_mgaw(iommu->cap);
1472 domain->gaw = guest_width;
1473 adjust_width = guestwidth_to_adjustwidth(guest_width);
1474 agaw = width_to_agaw(adjust_width);
1475 sagaw = cap_sagaw(iommu->cap);
1476 if (!test_bit(agaw, &sagaw)) {
1477 /* hardware doesn't support it, choose a bigger one */
1478 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1479 agaw = find_next_bit(&sagaw, 5, agaw);
1480 if (agaw >= 5)
1481 return -ENODEV;
1482 }
1483 domain->agaw = agaw;
1484 INIT_LIST_HEAD(&domain->devices);
1485
8e604097
WH		 1486 if (ecap_coherent(iommu->ecap))
1487 domain->iommu_coherency = 1;
1488 else
1489 domain->iommu_coherency = 0;
1490
58c610bd
SY		 1491 if (ecap_sc_support(iommu->ecap))
1492 domain->iommu_snooping = 1;
1493 else
1494 domain->iommu_snooping = 0;
1495
6dd9a7c7 1496 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
c7151a8d 1497 domain->iommu_count = 1;
4c923d47 1498 domain->nid = iommu->node;
c7151a8d 1499
ba395927 1500 /* always allocate the top pgd */
4c923d47 1501 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1502 if (!domain->pgd)
1503 return -ENOMEM;
5b6985ce 1504 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1505 return 0;
1506}
1507
1508static void domain_exit(struct dmar_domain *domain)
1509{
2c2e2c38
FY		 1510 struct dmar_drhd_unit *drhd;
1511 struct intel_iommu *iommu;
ba395927
KA		 1512
1513 /* Domain 0 is reserved, so dont process it */
1514 if (!domain)
1515 return;
1516
7b668357
AW		 1517 /* Flush any lazy unmaps that may reference this domain */
1518 if (!intel_iommu_strict)
1519 flush_unmaps_timeout(0);
1520
ba395927
KA		 1521 domain_remove_dev_info(domain);
1522 /* destroy iovas */
1523 put_iova_domain(&domain->iovad);
ba395927
KA		 1524
1525 /* clear ptes */
595badf5 1526 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927
KA		 1527
1528 /* free page tables */
d794dc9b 1529 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1530
2c2e2c38 1531 for_each_active_iommu(iommu, drhd)
1b198bb0 1532 if (test_bit(iommu->seq_id, domain->iommu_bmp))
2c2e2c38
FY		 1533 iommu_detach_domain(domain, iommu);
1534
ba395927
KA		 1535 free_domain_mem(domain);
1536}
1537
4ed0d3e6
FY		 1538static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1539 u8 bus, u8 devfn, int translation)
ba395927
KA		 1540{
1541 struct context_entry *context;
ba395927 1542 unsigned long flags;
5331fe6f 1543 struct intel_iommu *iommu;
ea6606b0
WH		 1544 struct dma_pte *pgd;
1545 unsigned long num;
1546 unsigned long ndomains;
1547 int id;
1548 int agaw;
93a23a72 1549 struct device_domain_info *info = NULL;
ba395927
KA		 1550
1551 pr_debug("Set context mapping for %02x:%02x.%d\n",
1552 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1553
ba395927 1554 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1555 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1556 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1557
276dbf99 1558 iommu = device_to_iommu(segment, bus, devfn);
5331fe6f
WH		 1559 if (!iommu)
1560 return -ENODEV;
1561
ba395927
KA		 1562 context = device_to_context_entry(iommu, bus, devfn);
1563 if (!context)
1564 return -ENOMEM;
1565 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1566 if (context_present(context)) {
ba395927
KA		 1567 spin_unlock_irqrestore(&iommu->lock, flags);
1568 return 0;
1569 }
1570
ea6606b0
WH		 1571 id = domain->id;
1572 pgd = domain->pgd;
1573
2c2e2c38
FY		 1574 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1575 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
ea6606b0
WH		 1576 int found = 0;
1577
1578 /* find an available domain id for this device in iommu */
1579 ndomains = cap_ndoms(iommu->cap);
a45946ab 1580 for_each_set_bit(num, iommu->domain_ids, ndomains) {
ea6606b0
WH		 1581 if (iommu->domains[num] == domain) {
1582 id = num;
1583 found = 1;
1584 break;
1585 }
ea6606b0
WH		 1586 }
1587
1588 if (found == 0) {
1589 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1590 if (num >= ndomains) {
1591 spin_unlock_irqrestore(&iommu->lock, flags);
1592 printk(KERN_ERR "IOMMU: no free domain ids\n");
1593 return -EFAULT;
1594 }
1595
1596 set_bit(num, iommu->domain_ids);
1597 iommu->domains[num] = domain;
1598 id = num;
1599 }
1600
1601 /* Skip top levels of page tables for
1602 * iommu which has less agaw than default.
1672af11 1603 * Unnecessary for PT mode.
ea6606b0 1604 */
1672af11
CW		 1605 if (translation != CONTEXT_TT_PASS_THROUGH) {
1606 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1607 pgd = phys_to_virt(dma_pte_addr(pgd));
1608 if (!dma_pte_present(pgd)) {
1609 spin_unlock_irqrestore(&iommu->lock, flags);
1610 return -ENOMEM;
1611 }
ea6606b0
WH		 1612 }
1613 }
1614 }
1615
1616 context_set_domain_id(context, id);
4ed0d3e6 1617
93a23a72
YZ		 1618 if (translation != CONTEXT_TT_PASS_THROUGH) {
1619 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1620 translation = info ? CONTEXT_TT_DEV_IOTLB :
1621 CONTEXT_TT_MULTI_LEVEL;
1622 }
4ed0d3e6
FY		 1623 /*
1624 * In pass through mode, AW must be programmed to indicate the largest
1625 * AGAW value supported by hardware. And ASR is ignored by hardware.
1626 */
93a23a72 1627 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1628 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1629 else {
1630 context_set_address_root(context, virt_to_phys(pgd));
1631 context_set_address_width(context, iommu->agaw);
1632 }
4ed0d3e6
FY		 1633
1634 context_set_translation_type(context, translation);
c07e7d21
MM		 1635 context_set_fault_enable(context);
1636 context_set_present(context);
5331fe6f 1637 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1638
4c25a2c1
DW		 1639 /*
1640 * It's a non-present to present mapping. If hardware doesn't cache
1641 * non-present entry we only need to flush the write-buffer. If the
1642 * _does_ cache non-present entries, then it does so in the special
1643 * domain #0, which we have to flush:
1644 */
1645 if (cap_caching_mode(iommu->cap)) {
1646 iommu->flush.flush_context(iommu, 0,
1647 (((u16)bus) << 8) | devfn,
1648 DMA_CCMD_MASK_NOBIT,
1649 DMA_CCMD_DEVICE_INVL);
82653633 1650 iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1651 } else {
ba395927 1652 iommu_flush_write_buffer(iommu);
4c25a2c1 1653 }
93a23a72 1654 iommu_enable_dev_iotlb(info);
ba395927 1655 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d
WH		 1656
1657 spin_lock_irqsave(&domain->iommu_lock, flags);
1b198bb0 1658 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
c7151a8d 1659 domain->iommu_count++;
4c923d47
SS		 1660 if (domain->iommu_count == 1)
1661 domain->nid = iommu->node;
58c610bd 1662 domain_update_iommu_cap(domain);
c7151a8d
WH		 1663 }
1664 spin_unlock_irqrestore(&domain->iommu_lock, flags);
ba395927
KA		 1665 return 0;
1666}
1667
1668static int
4ed0d3e6
FY		 1669domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1670 int translation)
ba395927
KA		 1671{
1672 int ret;
1673 struct pci_dev *tmp, *parent;
1674
276dbf99 1675 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
4ed0d3e6
FY		 1676 pdev->bus->number, pdev->devfn,
1677 translation);
ba395927
KA		 1678 if (ret)
1679 return ret;
1680
1681 /* dependent device mapping */
1682 tmp = pci_find_upstream_pcie_bridge(pdev);
1683 if (!tmp)
1684 return 0;
1685 /* Secondary interface's bus number and devfn 0 */
1686 parent = pdev->bus->self;
1687 while (parent != tmp) {
276dbf99
DW		 1688 ret = domain_context_mapping_one(domain,
1689 pci_domain_nr(parent->bus),
1690 parent->bus->number,
4ed0d3e6 1691 parent->devfn, translation);
ba395927
KA		 1692 if (ret)
1693 return ret;
1694 parent = parent->bus->self;
1695 }
45e829ea 1696 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
ba395927 1697 return domain_context_mapping_one(domain,
276dbf99 1698 pci_domain_nr(tmp->subordinate),
4ed0d3e6
FY		 1699 tmp->subordinate->number, 0,
1700 translation);
ba395927
KA		 1701 else /* this is a legacy PCI bridge */
1702 return domain_context_mapping_one(domain,
276dbf99
DW		 1703 pci_domain_nr(tmp->bus),
1704 tmp->bus->number,
4ed0d3e6
FY		 1705 tmp->devfn,
1706 translation);
ba395927
KA		 1707}
1708
5331fe6f 1709static int domain_context_mapped(struct pci_dev *pdev)
ba395927
KA		 1710{
1711 int ret;
1712 struct pci_dev *tmp, *parent;
5331fe6f
WH		 1713 struct intel_iommu *iommu;
1714
276dbf99
DW		 1715 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1716 pdev->devfn);
5331fe6f
WH		 1717 if (!iommu)
1718 return -ENODEV;
ba395927 1719
276dbf99 1720 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
ba395927
KA		 1721 if (!ret)
1722 return ret;
1723 /* dependent device mapping */
1724 tmp = pci_find_upstream_pcie_bridge(pdev);
1725 if (!tmp)
1726 return ret;
1727 /* Secondary interface's bus number and devfn 0 */
1728 parent = pdev->bus->self;
1729 while (parent != tmp) {
8c11e798 1730 ret = device_context_mapped(iommu, parent->bus->number,
276dbf99 1731 parent->devfn);
ba395927
KA		 1732 if (!ret)
1733 return ret;
1734 parent = parent->bus->self;
1735 }
5f4d91a1 1736 if (pci_is_pcie(tmp))
276dbf99
DW		 1737 return device_context_mapped(iommu, tmp->subordinate->number,
1738 0);
ba395927 1739 else
276dbf99
DW		 1740 return device_context_mapped(iommu, tmp->bus->number,
1741 tmp->devfn);
ba395927
KA		 1742}
1743
f532959b
FY		 1744/* Returns a number of VTD pages, but aligned to MM page size */
1745static inline unsigned long aligned_nrpages(unsigned long host_addr,
1746 size_t size)
1747{
1748 host_addr &= ~PAGE_MASK;
1749 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1750}
1751
6dd9a7c7
YS		 1752/* Return largest possible superpage level for a given mapping */
1753static inline int hardware_largepage_caps(struct dmar_domain *domain,
1754 unsigned long iov_pfn,
1755 unsigned long phy_pfn,
1756 unsigned long pages)
1757{
1758 int support, level = 1;
1759 unsigned long pfnmerge;
1760
1761 support = domain->iommu_superpage;
1762
1763 /* To use a large page, the virtual *and* physical addresses
1764 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1765 of them will mean we have to use smaller pages. So just
1766 merge them and check both at once. */
1767 pfnmerge = iov_pfn | phy_pfn;
1768
1769 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1770 pages >>= VTD_STRIDE_SHIFT;
1771 if (!pages)
1772 break;
1773 pfnmerge >>= VTD_STRIDE_SHIFT;
1774 level++;
1775 support--;
1776 }
1777 return level;
1778}
1779
9051aa02
DW		 1780static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1781 struct scatterlist *sg, unsigned long phys_pfn,
1782 unsigned long nr_pages, int prot)
e1605495
DW		 1783{
1784 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1785 phys_addr_t uninitialized_var(pteval);
e1605495 1786 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1787 unsigned long sg_res;
6dd9a7c7
YS		 1788 unsigned int largepage_lvl = 0;
1789 unsigned long lvl_pages = 0;
e1605495
DW		 1790
1791 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1792
1793 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1794 return -EINVAL;
1795
1796 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1797
9051aa02
DW		 1798 if (sg)
1799 sg_res = 0;
1800 else {
1801 sg_res = nr_pages + 1;
1802 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1803 }
1804
6dd9a7c7 1805 while (nr_pages > 0) {
c85994e4
DW		 1806 uint64_t tmp;
1807
e1605495 1808 if (!sg_res) {
f532959b 1809 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 1810 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1811 sg->dma_length = sg->length;
1812 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 1813 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 1814 }
6dd9a7c7 1815
e1605495 1816 if (!pte) {
6dd9a7c7
YS		 1817 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
1818
1819 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, largepage_lvl);
e1605495
DW		 1820 if (!pte)
1821 return -ENOMEM;
6dd9a7c7 1822 /* It is large page*/
6491d4d0 1823 if (largepage_lvl > 1) {
6dd9a7c7 1824 pteval |= DMA_PTE_LARGE_PAGE;
6491d4d0
WD		 1825 /* Ensure that old small page tables are removed to make room
1826 for superpage, if they exist. */
1827 dma_pte_clear_range(domain, iov_pfn,
1828 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1829 dma_pte_free_pagetable(domain, iov_pfn,
1830 iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1);
1831 } else {
6dd9a7c7 1832 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 1833 }
6dd9a7c7 1834
e1605495
DW		 1835 }
1836 /* We don't need lock here, nobody else
1837 * touches the iova range
1838 */
7766a3fb 1839 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 1840 if (tmp) {
1bf20f0d 1841 static int dumps = 5;
c85994e4
DW		 1842 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1843 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 1844 if (dumps) {
1845 dumps--;
1846 debug_dma_dump_mappings(NULL);
1847 }
1848 WARN_ON(1);
1849 }
6dd9a7c7
YS		 1850
1851 lvl_pages = lvl_to_nr_pages(largepage_lvl);
1852
1853 BUG_ON(nr_pages < lvl_pages);
1854 BUG_ON(sg_res < lvl_pages);
1855
1856 nr_pages -= lvl_pages;
1857 iov_pfn += lvl_pages;
1858 phys_pfn += lvl_pages;
1859 pteval += lvl_pages * VTD_PAGE_SIZE;
1860 sg_res -= lvl_pages;
1861
1862 /* If the next PTE would be the first in a new page, then we
1863 need to flush the cache on the entries we've just written.
1864 And then we'll need to recalculate 'pte', so clear it and
1865 let it get set again in the if (!pte) block above.
1866
1867 If we're done (!nr_pages) we need to flush the cache too.
1868
1869 Also if we've been setting superpages, we may need to
1870 recalculate 'pte' and switch back to smaller pages for the
1871 end of the mapping, if the trailing size is not enough to
1872 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 1873 pte++;
6dd9a7c7
YS		 1874 if (!nr_pages || first_pte_in_page(pte) ||
1875 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 1876 domain_flush_cache(domain, first_pte,
1877 (void *)pte - (void *)first_pte);
1878 pte = NULL;
1879 }
6dd9a7c7
YS		 1880
1881 if (!sg_res && nr_pages)
e1605495
DW		 1882 sg = sg_next(sg);
1883 }
1884 return 0;
1885}
1886
9051aa02
DW		 1887static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1888 struct scatterlist *sg, unsigned long nr_pages,
1889 int prot)
ba395927 1890{
9051aa02
DW		 1891 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1892}
6f6a00e4 1893
9051aa02
DW		 1894static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1895 unsigned long phys_pfn, unsigned long nr_pages,
1896 int prot)
1897{
1898 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 1899}
1900
c7151a8d 1901static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 1902{
c7151a8d
WH		 1903 if (!iommu)
1904 return;
8c11e798
WH		 1905
1906 clear_context_table(iommu, bus, devfn);
1907 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 1908 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 1909 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 1910}
1911
109b9b04
DW		 1912static inline void unlink_domain_info(struct device_domain_info *info)
1913{
1914 assert_spin_locked(&device_domain_lock);
1915 list_del(&info->link);
1916 list_del(&info->global);
1917 if (info->dev)
1918 info->dev->dev.archdata.iommu = NULL;
1919}
1920
ba395927
KA		 1921static void domain_remove_dev_info(struct dmar_domain *domain)
1922{
1923 struct device_domain_info *info;
1924 unsigned long flags;
c7151a8d 1925 struct intel_iommu *iommu;
ba395927
KA		 1926
1927 spin_lock_irqsave(&device_domain_lock, flags);
1928 while (!list_empty(&domain->devices)) {
1929 info = list_entry(domain->devices.next,
1930 struct device_domain_info, link);
109b9b04 1931 unlink_domain_info(info);
ba395927
KA		 1932 spin_unlock_irqrestore(&device_domain_lock, flags);
1933
93a23a72 1934 iommu_disable_dev_iotlb(info);
276dbf99 1935 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 1936 iommu_detach_dev(iommu, info->bus, info->devfn);
ba395927
KA		 1937 free_devinfo_mem(info);
1938
1939 spin_lock_irqsave(&device_domain_lock, flags);
1940 }
1941 spin_unlock_irqrestore(&device_domain_lock, flags);
1942}
1943
1944/*
1945 * find_domain
358dd8ac 1946 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
ba395927 1947 */
38717946 1948static struct dmar_domain *
ba395927
KA		 1949find_domain(struct pci_dev *pdev)
1950{
1951 struct device_domain_info *info;
1952
1953 /* No lock here, assumes no domain exit in normal case */
358dd8ac 1954 info = pdev->dev.archdata.iommu;
ba395927
KA		 1955 if (info)
1956 return info->domain;
1957 return NULL;
1958}
1959
ba395927
KA		 1960/* domain is initialized */
1961static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1962{
1963 struct dmar_domain *domain, *found = NULL;
1964 struct intel_iommu *iommu;
1965 struct dmar_drhd_unit *drhd;
1966 struct device_domain_info *info, *tmp;
1967 struct pci_dev *dev_tmp;
1968 unsigned long flags;
1969 int bus = 0, devfn = 0;
276dbf99 1970 int segment;
2c2e2c38 1971 int ret;
ba395927
KA		 1972
1973 domain = find_domain(pdev);
1974 if (domain)
1975 return domain;
1976
276dbf99
DW		 1977 segment = pci_domain_nr(pdev->bus);
1978
ba395927
KA		 1979 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1980 if (dev_tmp) {
5f4d91a1 1981 if (pci_is_pcie(dev_tmp)) {
ba395927
KA		 1982 bus = dev_tmp->subordinate->number;
1983 devfn = 0;
1984 } else {
1985 bus = dev_tmp->bus->number;
1986 devfn = dev_tmp->devfn;
1987 }
1988 spin_lock_irqsave(&device_domain_lock, flags);
1989 list_for_each_entry(info, &device_domain_list, global) {
276dbf99
DW		 1990 if (info->segment == segment &&
1991 info->bus == bus && info->devfn == devfn) {
ba395927
KA		 1992 found = info->domain;
1993 break;
1994 }
1995 }
1996 spin_unlock_irqrestore(&device_domain_lock, flags);
1997 /* pcie-pci bridge already has a domain, uses it */
1998 if (found) {
1999 domain = found;
2000 goto found_domain;
2001 }
2002 }
2003
2c2e2c38
FY		 2004 domain = alloc_domain();
2005 if (!domain)
2006 goto error;
2007
ba395927
KA		 2008 /* Allocate new domain for the device */
2009 drhd = dmar_find_matched_drhd_unit(pdev);
2010 if (!drhd) {
2011 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
2012 pci_name(pdev));
d2900bd6 2013 free_domain_mem(domain);
ba395927
KA		 2014 return NULL;
2015 }
2016 iommu = drhd->iommu;
2017
2c2e2c38
FY		 2018 ret = iommu_attach_domain(domain, iommu);
2019 if (ret) {
2fe9723d 2020 free_domain_mem(domain);
ba395927 2021 goto error;
2c2e2c38 2022 }
ba395927
KA		 2023
2024 if (domain_init(domain, gaw)) {
2025 domain_exit(domain);
2026 goto error;
2027 }
2028
2029 /* register pcie-to-pci device */
2030 if (dev_tmp) {
2031 info = alloc_devinfo_mem();
2032 if (!info) {
2033 domain_exit(domain);
2034 goto error;
2035 }
276dbf99 2036 info->segment = segment;
ba395927
KA		 2037 info->bus = bus;
2038 info->devfn = devfn;
2039 info->dev = NULL;
2040 info->domain = domain;
2041 /* This domain is shared by devices under p2p bridge */
3b5410e7 2042 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
ba395927
KA		 2043
2044 /* pcie-to-pci bridge already has a domain, uses it */
2045 found = NULL;
2046 spin_lock_irqsave(&device_domain_lock, flags);
2047 list_for_each_entry(tmp, &device_domain_list, global) {
276dbf99
DW		 2048 if (tmp->segment == segment &&
2049 tmp->bus == bus && tmp->devfn == devfn) {
ba395927
KA		 2050 found = tmp->domain;
2051 break;
2052 }
2053 }
2054 if (found) {
00dfff77 2055 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927
KA		 2056 free_devinfo_mem(info);
2057 domain_exit(domain);
2058 domain = found;
2059 } else {
2060 list_add(&info->link, &domain->devices);
2061 list_add(&info->global, &device_domain_list);
00dfff77 2062 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2063 }
ba395927
KA		 2064 }
2065
2066found_domain:
2067 info = alloc_devinfo_mem();
2068 if (!info)
2069 goto error;
276dbf99 2070 info->segment = segment;
ba395927
KA		 2071 info->bus = pdev->bus->number;
2072 info->devfn = pdev->devfn;
2073 info->dev = pdev;
2074 info->domain = domain;
2075 spin_lock_irqsave(&device_domain_lock, flags);
2076 /* somebody is fast */
2077 found = find_domain(pdev);
2078 if (found != NULL) {
2079 spin_unlock_irqrestore(&device_domain_lock, flags);
2080 if (found != domain) {
2081 domain_exit(domain);
2082 domain = found;
2083 }
2084 free_devinfo_mem(info);
2085 return domain;
2086 }
2087 list_add(&info->link, &domain->devices);
2088 list_add(&info->global, &device_domain_list);
358dd8ac 2089 pdev->dev.archdata.iommu = info;
ba395927
KA		 2090 spin_unlock_irqrestore(&device_domain_lock, flags);
2091 return domain;
2092error:
2093 /* recheck it here, maybe others set it */
2094 return find_domain(pdev);
2095}
2096
2c2e2c38 2097static int iommu_identity_mapping;
e0fc7e0b
DW		 2098#define IDENTMAP_ALL 1
2099#define IDENTMAP_GFX 2
2100#define IDENTMAP_AZALIA 4
2c2e2c38 2101
b213203e
DW		 2102static int iommu_domain_identity_map(struct dmar_domain *domain,
2103 unsigned long long start,
2104 unsigned long long end)
ba395927 2105{
c5395d5c
DW		 2106 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2107 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2108
2109 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2110 dma_to_mm_pfn(last_vpfn))) {
ba395927 2111 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2112 return -ENOMEM;
ba395927
KA		 2113 }
2114
c5395d5c
DW		 2115 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2116 start, end, domain->id);
ba395927
KA		 2117 /*
2118 * RMRR range might have overlap with physical memory range,
2119 * clear it first
2120 */
c5395d5c 2121 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2122
c5395d5c
DW		 2123 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2124 last_vpfn - first_vpfn + 1,
61df7443 2125 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2126}
2127
2128static int iommu_prepare_identity_map(struct pci_dev *pdev,
2129 unsigned long long start,
2130 unsigned long long end)
2131{
2132 struct dmar_domain *domain;
2133 int ret;
2134
c7ab48d2 2135 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2136 if (!domain)
2137 return -ENOMEM;
2138
19943b0e
DW		 2139 /* For _hardware_ passthrough, don't bother. But for software
2140 passthrough, we do it anyway -- it may indicate a memory
2141 range which is reserved in E820, so which didn't get set
2142 up to start with in si_domain */
2143 if (domain == si_domain && hw_pass_through) {
2144 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
2145 pci_name(pdev), start, end);
2146 return 0;
2147 }
2148
2149 printk(KERN_INFO
2150 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
2151 pci_name(pdev), start, end);
2ff729f5 2152
5595b528
DW		 2153 if (end < start) {
2154 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2155 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2156 dmi_get_system_info(DMI_BIOS_VENDOR),
2157 dmi_get_system_info(DMI_BIOS_VERSION),
2158 dmi_get_system_info(DMI_PRODUCT_VERSION));
2159 ret = -EIO;
2160 goto error;
2161 }
2162
2ff729f5
DW		 2163 if (end >> agaw_to_width(domain->agaw)) {
2164 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2165 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2166 agaw_to_width(domain->agaw),
2167 dmi_get_system_info(DMI_BIOS_VENDOR),
2168 dmi_get_system_info(DMI_BIOS_VERSION),
2169 dmi_get_system_info(DMI_PRODUCT_VERSION));
2170 ret = -EIO;
2171 goto error;
2172 }
19943b0e 2173
b213203e 2174 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2175 if (ret)
2176 goto error;
2177
2178 /* context entry init */
4ed0d3e6 2179 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2180 if (ret)
2181 goto error;
2182
2183 return 0;
2184
2185 error:
ba395927
KA		 2186 domain_exit(domain);
2187 return ret;
ba395927
KA		 2188}
2189
2190static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2191 struct pci_dev *pdev)
2192{
358dd8ac 2193 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927
KA		 2194 return 0;
2195 return iommu_prepare_identity_map(pdev, rmrr->base_address,
70e535d1 2196 rmrr->end_address);
ba395927
KA		 2197}
2198
d3f13810 2199#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2200static inline void iommu_prepare_isa(void)
2201{
2202 struct pci_dev *pdev;
2203 int ret;
2204
2205 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2206 if (!pdev)
2207 return;
2208
c7ab48d2 2209 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
70e535d1 2210 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2211
2212 if (ret)
c7ab48d2
DW		 2213 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2214 "floppy might not work\n");
49a0429e
KA		 2215
2216}
2217#else
2218static inline void iommu_prepare_isa(void)
2219{
2220 return;
2221}
d3f13810 2222#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2223
2c2e2c38 2224static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2225
071e1374 2226static int __init si_domain_init(int hw)
2c2e2c38
FY		 2227{
2228 struct dmar_drhd_unit *drhd;
2229 struct intel_iommu *iommu;
c7ab48d2 2230 int nid, ret = 0;
2c2e2c38
FY		 2231
2232 si_domain = alloc_domain();
2233 if (!si_domain)
2234 return -EFAULT;
2235
2c2e2c38
FY		 2236 for_each_active_iommu(iommu, drhd) {
2237 ret = iommu_attach_domain(si_domain, iommu);
2238 if (ret) {
2239 domain_exit(si_domain);
2240 return -EFAULT;
2241 }
2242 }
2243
2244 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2245 domain_exit(si_domain);
2246 return -EFAULT;
2247 }
2248
2249 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
9544c003
JL		 2250 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2251 si_domain->id);
2c2e2c38 2252
19943b0e
DW		 2253 if (hw)
2254 return 0;
2255
c7ab48d2 2256 for_each_online_node(nid) {
5dfe8660
TH		 2257 unsigned long start_pfn, end_pfn;
2258 int i;
2259
2260 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2261 ret = iommu_domain_identity_map(si_domain,
2262 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2263 if (ret)
2264 return ret;
2265 }
c7ab48d2
DW		 2266 }
2267
2c2e2c38
FY		 2268 return 0;
2269}
2270
2c2e2c38
FY		 2271static int identity_mapping(struct pci_dev *pdev)
2272{
2273 struct device_domain_info *info;
2274
2275 if (likely(!iommu_identity_mapping))
2276 return 0;
2277
cb452a40
MT		 2278 info = pdev->dev.archdata.iommu;
2279 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2280 return (info->domain == si_domain);
2c2e2c38 2281
2c2e2c38
FY		 2282 return 0;
2283}
2284
2285static int domain_add_dev_info(struct dmar_domain *domain,
5fe60f4e
DW		 2286 struct pci_dev *pdev,
2287 int translation)
2c2e2c38
FY		 2288{
2289 struct device_domain_info *info;
2290 unsigned long flags;
5fe60f4e 2291 int ret;
2c2e2c38
FY		 2292
2293 info = alloc_devinfo_mem();
2294 if (!info)
2295 return -ENOMEM;
2296
2297 info->segment = pci_domain_nr(pdev->bus);
2298 info->bus = pdev->bus->number;
2299 info->devfn = pdev->devfn;
2300 info->dev = pdev;
2301 info->domain = domain;
2302
2303 spin_lock_irqsave(&device_domain_lock, flags);
2304 list_add(&info->link, &domain->devices);
2305 list_add(&info->global, &device_domain_list);
2306 pdev->dev.archdata.iommu = info;
2307 spin_unlock_irqrestore(&device_domain_lock, flags);
2308
e2ad23d0
DW		 2309 ret = domain_context_mapping(domain, pdev, translation);
2310 if (ret) {
2311 spin_lock_irqsave(&device_domain_lock, flags);
109b9b04 2312 unlink_domain_info(info);
e2ad23d0
DW		 2313 spin_unlock_irqrestore(&device_domain_lock, flags);
2314 free_devinfo_mem(info);
2315 return ret;
2316 }
2317
2c2e2c38
FY		 2318 return 0;
2319}
2320
ea2447f7
TM		 2321static bool device_has_rmrr(struct pci_dev *dev)
2322{
2323 struct dmar_rmrr_unit *rmrr;
2324 int i;
2325
2326 for_each_rmrr_units(rmrr) {
2327 for (i = 0; i < rmrr->devices_cnt; i++) {
2328 /*
2329 * Return TRUE if this RMRR contains the device that
2330 * is passed in.
2331 */
2332 if (rmrr->devices[i] == dev)
2333 return true;
2334 }
2335 }
2336 return false;
2337}
2338
6941af28
DW		 2339static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2340{
ea2447f7
TM		 2341
2342 /*
2343 * We want to prevent any device associated with an RMRR from
2344 * getting placed into the SI Domain. This is done because
2345 * problems exist when devices are moved in and out of domains
2346 * and their respective RMRR info is lost. We exempt USB devices
2347 * from this process due to their usage of RMRRs that are known
2348 * to not be needed after BIOS hand-off to OS.
2349 */
2350 if (device_has_rmrr(pdev) &&
2351 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2352 return 0;
2353
e0fc7e0b
DW		 2354 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2355 return 1;
2356
2357 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2358 return 1;
2359
2360 if (!(iommu_identity_mapping & IDENTMAP_ALL))
2361 return 0;
6941af28 2362
3dfc813d
DW		 2363 /*
2364 * We want to start off with all devices in the 1:1 domain, and
2365 * take them out later if we find they can't access all of memory.
2366 *
2367 * However, we can't do this for PCI devices behind bridges,
2368 * because all PCI devices behind the same bridge will end up
2369 * with the same source-id on their transactions.
2370 *
2371 * Practically speaking, we can't change things around for these
2372 * devices at run-time, because we can't be sure there'll be no
2373 * DMA transactions in flight for any of their siblings.
2374 *
2375 * So PCI devices (unless they're on the root bus) as well as
2376 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2377 * the 1:1 domain, just in _case_ one of their siblings turns out
2378 * not to be able to map all of memory.
2379 */
5f4d91a1 2380 if (!pci_is_pcie(pdev)) {
3dfc813d
DW		 2381 if (!pci_is_root_bus(pdev->bus))
2382 return 0;
2383 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2384 return 0;
62f87c0e 2385 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d
DW		 2386 return 0;
2387
2388 /*
2389 * At boot time, we don't yet know if devices will be 64-bit capable.
2390 * Assume that they will -- if they turn out not to be, then we can
2391 * take them out of the 1:1 domain later.
2392 */
8fcc5372
CW		 2393 if (!startup) {
2394 /*
2395 * If the device's dma_mask is less than the system's memory
2396 * size then this is not a candidate for identity mapping.
2397 */
2398 u64 dma_mask = pdev->dma_mask;
2399
2400 if (pdev->dev.coherent_dma_mask &&
2401 pdev->dev.coherent_dma_mask < dma_mask)
2402 dma_mask = pdev->dev.coherent_dma_mask;
2403
2404 return dma_mask >= dma_get_required_mask(&pdev->dev);
2405 }
6941af28
DW		 2406
2407 return 1;
2408}
2409
071e1374 2410static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2411{
2c2e2c38
FY		 2412 struct pci_dev *pdev = NULL;
2413 int ret;
2414
19943b0e 2415 ret = si_domain_init(hw);
2c2e2c38
FY		 2416 if (ret)
2417 return -EFAULT;
2418
2c2e2c38 2419 for_each_pci_dev(pdev) {
6941af28 2420 if (iommu_should_identity_map(pdev, 1)) {
5fe60f4e 2421 ret = domain_add_dev_info(si_domain, pdev,
eae460b6
MT		 2422 hw ? CONTEXT_TT_PASS_THROUGH :
2423 CONTEXT_TT_MULTI_LEVEL);
2424 if (ret) {
2425 /* device not associated with an iommu */
2426 if (ret == -ENODEV)
2427 continue;
62edf5dc 2428 return ret;
eae460b6
MT		 2429 }
2430 pr_info("IOMMU: %s identity mapping for device %s\n",
2431 hw ? "hardware" : "software", pci_name(pdev));
62edf5dc 2432 }
2c2e2c38
FY		 2433 }
2434
2435 return 0;
2436}
2437
b779260b 2438static int __init init_dmars(void)
ba395927
KA		 2439{
2440 struct dmar_drhd_unit *drhd;
2441 struct dmar_rmrr_unit *rmrr;
2442 struct pci_dev *pdev;
2443 struct intel_iommu *iommu;
9d783ba0 2444 int i, ret;
2c2e2c38 2445
ba395927
KA		 2446 /*
2447 * for each drhd
2448 * allocate root
2449 * initialize and program root entry to not present
2450 * endfor
2451 */
2452 for_each_drhd_unit(drhd) {
5e0d2a6f 2453 /*
2454 * lock not needed as this is only incremented in the single
2455 * threaded kernel __init code path all other access are read
2456 * only
2457 */
1b198bb0
MT		 2458 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2459 g_num_of_iommus++;
2460 continue;
2461 }
2462 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2463 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2464 }
2465
d9630fe9
WH		 2466 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2467 GFP_KERNEL);
2468 if (!g_iommus) {
2469 printk(KERN_ERR "Allocating global iommu array failed\n");
2470 ret = -ENOMEM;
2471 goto error;
2472 }
2473
80b20dd8 2474 deferred_flush = kzalloc(g_num_of_iommus *
2475 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2476 if (!deferred_flush) {
5e0d2a6f 2477 ret = -ENOMEM;
989d51fc 2478 goto free_g_iommus;
5e0d2a6f 2479 }
2480
7c919779 2481 for_each_active_iommu(iommu, drhd) {
d9630fe9 2482 g_iommus[iommu->seq_id] = iommu;
ba395927 2483
e61d98d8
SS		 2484 ret = iommu_init_domains(iommu);
2485 if (ret)
989d51fc 2486 goto free_iommu;
e61d98d8 2487
ba395927
KA		 2488 /*
2489 * TBD:
2490 * we could share the same root & context tables
25985edc 2491 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2492 */
2493 ret = iommu_alloc_root_entry(iommu);
2494 if (ret) {
2495 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2496 goto free_iommu;
ba395927 2497 }
4ed0d3e6 2498 if (!ecap_pass_through(iommu->ecap))
19943b0e 2499 hw_pass_through = 0;
ba395927
KA		 2500 }
2501
1531a6a6
SS		 2502 /*
2503 * Start from the sane iommu hardware state.
2504 */
7c919779 2505 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2506 /*
2507 * If the queued invalidation is already initialized by us
2508 * (for example, while enabling interrupt-remapping) then
2509 * we got the things already rolling from a sane state.
2510 */
2511 if (iommu->qi)
2512 continue;
2513
2514 /*
2515 * Clear any previous faults.
2516 */
2517 dmar_fault(-1, iommu);
2518 /*
2519 * Disable queued invalidation if supported and already enabled
2520 * before OS handover.
2521 */
2522 dmar_disable_qi(iommu);
2523 }
2524
7c919779 2525 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2526 if (dmar_enable_qi(iommu)) {
2527 /*
2528 * Queued Invalidate not enabled, use Register Based
2529 * Invalidate
2530 */
2531 iommu->flush.flush_context = __iommu_flush_context;
2532 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2533 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2534 "invalidation\n",
680a7524 2535 iommu->seq_id,
b4e0f9eb 2536 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2537 } else {
2538 iommu->flush.flush_context = qi_flush_context;
2539 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2540 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2541 "invalidation\n",
680a7524 2542 iommu->seq_id,
b4e0f9eb 2543 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2544 }
2545 }
2546
19943b0e 2547 if (iommu_pass_through)
e0fc7e0b
DW		 2548 iommu_identity_mapping |= IDENTMAP_ALL;
2549
d3f13810 2550#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2551 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2552#endif
e0fc7e0b
DW		 2553
2554 check_tylersburg_isoch();
2555
ba395927 2556 /*
19943b0e
DW		 2557 * If pass through is not set or not enabled, setup context entries for
2558 * identity mappings for rmrr, gfx, and isa and may fall back to static
2559 * identity mapping if iommu_identity_mapping is set.
ba395927 2560 */
19943b0e
DW		 2561 if (iommu_identity_mapping) {
2562 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2563 if (ret) {
19943b0e 2564 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2565 goto free_iommu;
ba395927
KA		 2566 }
2567 }
ba395927 2568 /*
19943b0e
DW		 2569 * For each rmrr
2570 * for each dev attached to rmrr
2571 * do
2572 * locate drhd for dev, alloc domain for dev
2573 * allocate free domain
2574 * allocate page table entries for rmrr
2575 * if context not allocated for bus
2576 * allocate and init context
2577 * set present in root table for this bus
2578 * init context with domain, translation etc
2579 * endfor
2580 * endfor
ba395927 2581 */
19943b0e
DW		 2582 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2583 for_each_rmrr_units(rmrr) {
2584 for (i = 0; i < rmrr->devices_cnt; i++) {
2585 pdev = rmrr->devices[i];
2586 /*
2587 * some BIOS lists non-exist devices in DMAR
2588 * table.
2589 */
2590 if (!pdev)
2591 continue;
2592 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2593 if (ret)
2594 printk(KERN_ERR
2595 "IOMMU: mapping reserved region failed\n");
ba395927 2596 }
4ed0d3e6 2597 }
49a0429e 2598
19943b0e
DW		 2599 iommu_prepare_isa();
2600
ba395927
KA		 2601 /*
2602 * for each drhd
2603 * enable fault log
2604 * global invalidate context cache
2605 * global invalidate iotlb
2606 * enable translation
2607 */
7c919779 2608 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2609 if (drhd->ignored) {
2610 /*
2611 * we always have to disable PMRs or DMA may fail on
2612 * this device
2613 */
2614 if (force_on)
7c919779 2615 iommu_disable_protect_mem_regions(iommu);
ba395927 2616 continue;
51a63e67 2617 }
ba395927
KA		 2618
2619 iommu_flush_write_buffer(iommu);
2620
3460a6d9
KA		 2621 ret = dmar_set_interrupt(iommu);
2622 if (ret)
989d51fc 2623 goto free_iommu;
3460a6d9 2624
ba395927
KA		 2625 iommu_set_root_entry(iommu);
2626
4c25a2c1 2627 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2628 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
f8bab735 2629
ba395927
KA		 2630 ret = iommu_enable_translation(iommu);
2631 if (ret)
989d51fc 2632 goto free_iommu;
b94996c9
DW		 2633
2634 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2635 }
2636
2637 return 0;
989d51fc
JL		 2638
2639free_iommu:
7c919779 2640 for_each_active_iommu(iommu, drhd)
a868e6b7 2641 free_dmar_iommu(iommu);
9bdc531e 2642 kfree(deferred_flush);
989d51fc 2643free_g_iommus:
d9630fe9 2644 kfree(g_iommus);
989d51fc 2645error:
ba395927
KA		 2646 return ret;
2647}
2648
5a5e02a6 2649/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2650static struct iova *intel_alloc_iova(struct device *dev,
2651 struct dmar_domain *domain,
2652 unsigned long nrpages, uint64_t dma_mask)
ba395927 2653{
ba395927 2654 struct pci_dev *pdev = to_pci_dev(dev);
ba395927 2655 struct iova *iova = NULL;
ba395927 2656
875764de
DW		 2657 /* Restrict dma_mask to the width that the iommu can handle */
2658 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2659
2660 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2661 /*
2662 * First try to allocate an io virtual address in
284901a9 2663 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2664 * from higher range
ba395927 2665 */
875764de
DW		 2666 iova = alloc_iova(&domain->iovad, nrpages,
2667 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2668 if (iova)
2669 return iova;
2670 }
2671 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2672 if (unlikely(!iova)) {
2673 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2674 nrpages, pci_name(pdev));
f76aec76
KA		 2675 return NULL;
2676 }
2677
2678 return iova;
2679}
2680
147202aa 2681static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
f76aec76
KA		 2682{
2683 struct dmar_domain *domain;
2684 int ret;
2685
2686 domain = get_domain_for_dev(pdev,
2687 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2688 if (!domain) {
2689 printk(KERN_ERR
2690 "Allocating domain for %s failed", pci_name(pdev));
4fe05bbc 2691 return NULL;
ba395927
KA		 2692 }
2693
2694 /* make sure context mapping is ok */
5331fe6f 2695 if (unlikely(!domain_context_mapped(pdev))) {
4ed0d3e6
FY		 2696 ret = domain_context_mapping(domain, pdev,
2697 CONTEXT_TT_MULTI_LEVEL);
f76aec76
KA		 2698 if (ret) {
2699 printk(KERN_ERR
2700 "Domain context map for %s failed",
2701 pci_name(pdev));
4fe05bbc 2702 return NULL;
f76aec76 2703 }
ba395927
KA		 2704 }
2705
f76aec76
KA		 2706 return domain;
2707}
2708
147202aa
DW		 2709static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2710{
2711 struct device_domain_info *info;
2712
2713 /* No lock here, assumes no domain exit in normal case */
2714 info = dev->dev.archdata.iommu;
2715 if (likely(info))
2716 return info->domain;
2717
2718 return __get_valid_domain_for_dev(dev);
2719}
2720
2c2e2c38
FY		 2721static int iommu_dummy(struct pci_dev *pdev)
2722{
2723 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2724}
2725
2726/* Check if the pdev needs to go through non-identity map and unmap process.*/
73676832 2727static int iommu_no_mapping(struct device *dev)
2c2e2c38 2728{
73676832 2729 struct pci_dev *pdev;
2c2e2c38
FY		 2730 int found;
2731
dbad0864 2732 if (unlikely(!dev_is_pci(dev)))
73676832
DW		 2733 return 1;
2734
2735 pdev = to_pci_dev(dev);
1e4c64c4
DW		 2736 if (iommu_dummy(pdev))
2737 return 1;
2738
2c2e2c38 2739 if (!iommu_identity_mapping)
1e4c64c4 2740 return 0;
2c2e2c38
FY		 2741
2742 found = identity_mapping(pdev);
2743 if (found) {
6941af28 2744 if (iommu_should_identity_map(pdev, 0))
2c2e2c38
FY		 2745 return 1;
2746 else {
2747 /*
2748 * 32 bit DMA is removed from si_domain and fall back
2749 * to non-identity mapping.
2750 */
2751 domain_remove_one_dev_info(si_domain, pdev);
2752 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2753 pci_name(pdev));
2754 return 0;
2755 }
2756 } else {
2757 /*
2758 * In case of a detached 64 bit DMA device from vm, the device
2759 * is put into si_domain for identity mapping.
2760 */
6941af28 2761 if (iommu_should_identity_map(pdev, 0)) {
2c2e2c38 2762 int ret;
5fe60f4e
DW		 2763 ret = domain_add_dev_info(si_domain, pdev,
2764 hw_pass_through ?
2765 CONTEXT_TT_PASS_THROUGH :
2766 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2767 if (!ret) {
2768 printk(KERN_INFO "64bit %s uses identity mapping\n",
2769 pci_name(pdev));
2770 return 1;
2771 }
2772 }
2773 }
2774
1e4c64c4 2775 return 0;
2c2e2c38
FY		 2776}
2777
bb9e6d65
FT		 2778static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2779 size_t size, int dir, u64 dma_mask)
f76aec76
KA		 2780{
2781 struct pci_dev *pdev = to_pci_dev(hwdev);
f76aec76 2782 struct dmar_domain *domain;
5b6985ce 2783 phys_addr_t start_paddr;
f76aec76
KA		 2784 struct iova *iova;
2785 int prot = 0;
6865f0d1 2786 int ret;
8c11e798 2787 struct intel_iommu *iommu;
33041ec0 2788 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 2789
2790 BUG_ON(dir == DMA_NONE);
2c2e2c38 2791
73676832 2792 if (iommu_no_mapping(hwdev))
6865f0d1 2793 return paddr;
f76aec76
KA		 2794
2795 domain = get_valid_domain_for_dev(pdev);
2796 if (!domain)
2797 return 0;
2798
8c11e798 2799 iommu = domain_get_iommu(domain);
88cb6a74 2800 size = aligned_nrpages(paddr, size);
f76aec76 2801
c681d0ba 2802 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 2803 if (!iova)
2804 goto error;
2805
ba395927
KA		 2806 /*
2807 * Check if DMAR supports zero-length reads on write only
2808 * mappings..
2809 */
2810 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 2811 !cap_zlr(iommu->cap))
ba395927
KA		 2812 prot |= DMA_PTE_READ;
2813 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2814 prot |= DMA_PTE_WRITE;
2815 /*
6865f0d1 2816 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 2817 * page. Note: if two part of one page are separately mapped, we
6865f0d1 2818 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 2819 * is not a big problem
2820 */
0ab36de2 2821 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 2822 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 2823 if (ret)
2824 goto error;
2825
1f0ef2aa
DW		 2826 /* it's a non-present to present mapping. Only flush if caching mode */
2827 if (cap_caching_mode(iommu->cap))
82653633 2828 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 1);
1f0ef2aa 2829 else
8c11e798 2830 iommu_flush_write_buffer(iommu);
f76aec76 2831
03d6a246
DW		 2832 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2833 start_paddr += paddr & ~PAGE_MASK;
2834 return start_paddr;
ba395927 2835
ba395927 2836error:
f76aec76
KA		 2837 if (iova)
2838 __free_iova(&domain->iovad, iova);
4cf2e75d 2839 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5b6985ce 2840 pci_name(pdev), size, (unsigned long long)paddr, dir);
ba395927
KA		 2841 return 0;
2842}
2843
ffbbef5c
FT		 2844static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2845 unsigned long offset, size_t size,
2846 enum dma_data_direction dir,
2847 struct dma_attrs *attrs)
bb9e6d65 2848{
ffbbef5c
FT		 2849 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2850 dir, to_pci_dev(dev)->dma_mask);
bb9e6d65
FT		 2851}
2852
5e0d2a6f 2853static void flush_unmaps(void)
2854{
80b20dd8 2855 int i, j;
5e0d2a6f 2856
5e0d2a6f 2857 timer_on = 0;
2858
2859 /* just flush them all */
2860 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 2861 struct intel_iommu *iommu = g_iommus[i];
2862 if (!iommu)
2863 continue;
c42d9f32 2864
9dd2fe89
YZ		 2865 if (!deferred_flush[i].next)
2866 continue;
2867
78d5f0f5
NA		 2868 /* In caching mode, global flushes turn emulation expensive */
2869 if (!cap_caching_mode(iommu->cap))
2870 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 2871 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 2872 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 2873 unsigned long mask;
2874 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 2875 struct dmar_domain *domain = deferred_flush[i].domain[j];
2876
2877 /* On real hardware multiple invalidations are expensive */
2878 if (cap_caching_mode(iommu->cap))
2879 iommu_flush_iotlb_psi(iommu, domain->id,
2880 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, 0);
2881 else {
2882 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
2883 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2884 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
2885 }
93a23a72 2886 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
80b20dd8 2887 }
9dd2fe89 2888 deferred_flush[i].next = 0;
5e0d2a6f 2889 }
2890
5e0d2a6f 2891 list_size = 0;
5e0d2a6f 2892}
2893
2894static void flush_unmaps_timeout(unsigned long data)
2895{
80b20dd8 2896 unsigned long flags;
2897
2898 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 2899 flush_unmaps();
80b20dd8 2900 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 2901}
2902
2903static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2904{
2905 unsigned long flags;
80b20dd8 2906 int next, iommu_id;
8c11e798 2907 struct intel_iommu *iommu;
5e0d2a6f 2908
2909 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 2910 if (list_size == HIGH_WATER_MARK)
2911 flush_unmaps();
2912
8c11e798
WH		 2913 iommu = domain_get_iommu(dom);
2914 iommu_id = iommu->seq_id;
c42d9f32 2915
80b20dd8 2916 next = deferred_flush[iommu_id].next;
2917 deferred_flush[iommu_id].domain[next] = dom;
2918 deferred_flush[iommu_id].iova[next] = iova;
2919 deferred_flush[iommu_id].next++;
5e0d2a6f 2920
2921 if (!timer_on) {
2922 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2923 timer_on = 1;
2924 }
2925 list_size++;
2926 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2927}
2928
ffbbef5c
FT		 2929static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2930 size_t size, enum dma_data_direction dir,
2931 struct dma_attrs *attrs)
ba395927 2932{
ba395927 2933 struct pci_dev *pdev = to_pci_dev(dev);
f76aec76 2934 struct dmar_domain *domain;
d794dc9b 2935 unsigned long start_pfn, last_pfn;
ba395927 2936 struct iova *iova;
8c11e798 2937 struct intel_iommu *iommu;
ba395927 2938
73676832 2939 if (iommu_no_mapping(dev))
f76aec76 2940 return;
2c2e2c38 2941
ba395927
KA		 2942 domain = find_domain(pdev);
2943 BUG_ON(!domain);
2944
8c11e798
WH		 2945 iommu = domain_get_iommu(domain);
2946
ba395927 2947 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 2948 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2949 (unsigned long long)dev_addr))
ba395927 2950 return;
ba395927 2951
d794dc9b
DW		 2952 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2953 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 2954
d794dc9b
DW		 2955 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2956 pci_name(pdev), start_pfn, last_pfn);
ba395927 2957
f76aec76 2958 /* clear the whole page */
d794dc9b
DW		 2959 dma_pte_clear_range(domain, start_pfn, last_pfn);
2960
f76aec76 2961 /* free page tables */
d794dc9b
DW		 2962 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2963
5e0d2a6f 2964 if (intel_iommu_strict) {
03d6a246 2965 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 2966 last_pfn - start_pfn + 1, 0);
5e0d2a6f 2967 /* free iova */
2968 __free_iova(&domain->iovad, iova);
2969 } else {
2970 add_unmap(domain, iova);
2971 /*
2972 * queue up the release of the unmap to save the 1/6th of the
2973 * cpu used up by the iotlb flush operation...
2974 */
5e0d2a6f 2975 }
ba395927
KA		 2976}
2977
d7ab5c46 2978static void *intel_alloc_coherent(struct device *hwdev, size_t size,
baa676fc
AP		 2979 dma_addr_t *dma_handle, gfp_t flags,
2980 struct dma_attrs *attrs)
ba395927
KA		 2981{
2982 void *vaddr;
2983 int order;
2984
5b6985ce 2985 size = PAGE_ALIGN(size);
ba395927 2986 order = get_order(size);
e8bb910d
AW		 2987
2988 if (!iommu_no_mapping(hwdev))
2989 flags &= ~(GFP_DMA | GFP_DMA32);
2990 else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) {
2991 if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32))
2992 flags |= GFP_DMA;
2993 else
2994 flags |= GFP_DMA32;
2995 }
ba395927
KA		 2996
2997 vaddr = (void *)__get_free_pages(flags, order);
2998 if (!vaddr)
2999 return NULL;
3000 memset(vaddr, 0, size);
3001
bb9e6d65
FT		 3002 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
3003 DMA_BIDIRECTIONAL,
3004 hwdev->coherent_dma_mask);
ba395927
KA		 3005 if (*dma_handle)
3006 return vaddr;
3007 free_pages((unsigned long)vaddr, order);
3008 return NULL;
3009}
3010
d7ab5c46 3011static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
baa676fc 3012 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3013{
3014 int order;
3015
5b6985ce 3016 size = PAGE_ALIGN(size);
ba395927
KA		 3017 order = get_order(size);
3018
0db9b7ae 3019 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
ba395927
KA		 3020 free_pages((unsigned long)vaddr, order);
3021}
3022
d7ab5c46
FT		 3023static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
3024 int nelems, enum dma_data_direction dir,
3025 struct dma_attrs *attrs)
ba395927 3026{
ba395927
KA		 3027 struct pci_dev *pdev = to_pci_dev(hwdev);
3028 struct dmar_domain *domain;
d794dc9b 3029 unsigned long start_pfn, last_pfn;
f76aec76 3030 struct iova *iova;
8c11e798 3031 struct intel_iommu *iommu;
ba395927 3032
73676832 3033 if (iommu_no_mapping(hwdev))
ba395927
KA		 3034 return;
3035
3036 domain = find_domain(pdev);
8c11e798
WH		 3037 BUG_ON(!domain);
3038
3039 iommu = domain_get_iommu(domain);
ba395927 3040
c03ab37c 3041 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
85b98276
DW		 3042 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
3043 (unsigned long long)sglist[0].dma_address))
f76aec76 3044 return;
f76aec76 3045
d794dc9b
DW		 3046 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3047 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
f76aec76
KA		 3048
3049 /* clear the whole page */
d794dc9b
DW		 3050 dma_pte_clear_range(domain, start_pfn, last_pfn);
3051
f76aec76 3052 /* free page tables */
d794dc9b 3053 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
f76aec76 3054
acea0018
DW		 3055 if (intel_iommu_strict) {
3056 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
82653633 3057 last_pfn - start_pfn + 1, 0);
acea0018
DW		 3058 /* free iova */
3059 __free_iova(&domain->iovad, iova);
3060 } else {
3061 add_unmap(domain, iova);
3062 /*
3063 * queue up the release of the unmap to save the 1/6th of the
3064 * cpu used up by the iotlb flush operation...
3065 */
3066 }
ba395927
KA		 3067}
3068
ba395927 3069static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3070 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3071{
3072 int i;
c03ab37c 3073 struct scatterlist *sg;
ba395927 3074
c03ab37c 3075 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3076 BUG_ON(!sg_page(sg));
4cf2e75d 3077 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3078 sg->dma_length = sg->length;
ba395927
KA		 3079 }
3080 return nelems;
3081}
3082
d7ab5c46
FT		 3083static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
3084 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3085{
ba395927 3086 int i;
ba395927
KA		 3087 struct pci_dev *pdev = to_pci_dev(hwdev);
3088 struct dmar_domain *domain;
f76aec76
KA		 3089 size_t size = 0;
3090 int prot = 0;
f76aec76
KA		 3091 struct iova *iova = NULL;
3092 int ret;
c03ab37c 3093 struct scatterlist *sg;
b536d24d 3094 unsigned long start_vpfn;
8c11e798 3095 struct intel_iommu *iommu;
ba395927
KA		 3096
3097 BUG_ON(dir == DMA_NONE);
73676832 3098 if (iommu_no_mapping(hwdev))
c03ab37c 3099 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
ba395927 3100
f76aec76
KA		 3101 domain = get_valid_domain_for_dev(pdev);
3102 if (!domain)
3103 return 0;
3104
8c11e798
WH		 3105 iommu = domain_get_iommu(domain);
3106
b536d24d 3107 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3108 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3109
5a5e02a6
DW		 3110 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
3111 pdev->dma_mask);
f76aec76 3112 if (!iova) {
c03ab37c 3113 sglist->dma_length = 0;
f76aec76
KA		 3114 return 0;
3115 }
3116
3117 /*
3118 * Check if DMAR supports zero-length reads on write only
3119 * mappings..
3120 */
3121 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3122 !cap_zlr(iommu->cap))
f76aec76
KA		 3123 prot |= DMA_PTE_READ;
3124 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3125 prot |= DMA_PTE_WRITE;
3126
b536d24d 3127 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3128
f532959b 3129 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495
DW		 3130 if (unlikely(ret)) {
3131 /* clear the page */
3132 dma_pte_clear_range(domain, start_vpfn,
3133 start_vpfn + size - 1);
3134 /* free page tables */
3135 dma_pte_free_pagetable(domain, start_vpfn,
3136 start_vpfn + size - 1);
3137 /* free iova */
3138 __free_iova(&domain->iovad, iova);
3139 return 0;
ba395927
KA		 3140 }
3141
1f0ef2aa
DW		 3142 /* it's a non-present to present mapping. Only flush if caching mode */
3143 if (cap_caching_mode(iommu->cap))
82653633 3144 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 1);
1f0ef2aa 3145 else
8c11e798 3146 iommu_flush_write_buffer(iommu);
1f0ef2aa 3147
ba395927
KA		 3148 return nelems;
3149}
3150
dfb805e8
FT		 3151static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3152{
3153 return !dma_addr;
3154}
3155
160c1d8e 3156struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3157 .alloc = intel_alloc_coherent,
3158 .free = intel_free_coherent,
ba395927
KA		 3159 .map_sg = intel_map_sg,
3160 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3161 .map_page = intel_map_page,
3162 .unmap_page = intel_unmap_page,
dfb805e8 3163 .mapping_error = intel_mapping_error,
ba395927
KA		 3164};
3165
3166static inline int iommu_domain_cache_init(void)
3167{
3168 int ret = 0;
3169
3170 iommu_domain_cache = kmem_cache_create("iommu_domain",
3171 sizeof(struct dmar_domain),
3172 0,
3173 SLAB_HWCACHE_ALIGN,
3174
3175 NULL);
3176 if (!iommu_domain_cache) {
3177 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3178 ret = -ENOMEM;
3179 }
3180
3181 return ret;
3182}
3183
3184static inline int iommu_devinfo_cache_init(void)
3185{
3186 int ret = 0;
3187
3188 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3189 sizeof(struct device_domain_info),
3190 0,
3191 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3192 NULL);
3193 if (!iommu_devinfo_cache) {
3194 printk(KERN_ERR "Couldn't create devinfo cache\n");
3195 ret = -ENOMEM;
3196 }
3197
3198 return ret;
3199}
3200
3201static inline int iommu_iova_cache_init(void)
3202{
3203 int ret = 0;
3204
3205 iommu_iova_cache = kmem_cache_create("iommu_iova",
3206 sizeof(struct iova),
3207 0,
3208 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3209 NULL);
3210 if (!iommu_iova_cache) {
3211 printk(KERN_ERR "Couldn't create iova cache\n");
3212 ret = -ENOMEM;
3213 }
3214
3215 return ret;
3216}
3217
3218static int __init iommu_init_mempool(void)
3219{
3220 int ret;
3221 ret = iommu_iova_cache_init();
3222 if (ret)
3223 return ret;
3224
3225 ret = iommu_domain_cache_init();
3226 if (ret)
3227 goto domain_error;
3228
3229 ret = iommu_devinfo_cache_init();
3230 if (!ret)
3231 return ret;
3232
3233 kmem_cache_destroy(iommu_domain_cache);
3234domain_error:
3235 kmem_cache_destroy(iommu_iova_cache);
3236
3237 return -ENOMEM;
3238}
3239
3240static void __init iommu_exit_mempool(void)
3241{
3242 kmem_cache_destroy(iommu_devinfo_cache);
3243 kmem_cache_destroy(iommu_domain_cache);
3244 kmem_cache_destroy(iommu_iova_cache);
3245
3246}
3247
556ab45f
DW		 3248static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3249{
3250 struct dmar_drhd_unit *drhd;
3251 u32 vtbar;
3252 int rc;
3253
3254 /* We know that this device on this chipset has its own IOMMU.
3255 * If we find it under a different IOMMU, then the BIOS is lying
3256 * to us. Hope that the IOMMU for this device is actually
3257 * disabled, and it needs no translation...
3258 */
3259 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3260 if (rc) {
3261 /* "can't" happen */
3262 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3263 return;
3264 }
3265 vtbar &= 0xffff0000;
3266
3267 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3268 drhd = dmar_find_matched_drhd_unit(pdev);
3269 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3270 TAINT_FIRMWARE_WORKAROUND,
3271 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3272 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3273}
3274DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3275
ba395927
KA		 3276static void __init init_no_remapping_devices(void)
3277{
3278 struct dmar_drhd_unit *drhd;
3279
3280 for_each_drhd_unit(drhd) {
3281 if (!drhd->include_all) {
3282 int i;
3283 for (i = 0; i < drhd->devices_cnt; i++)
3284 if (drhd->devices[i] != NULL)
3285 break;
3286 /* ignore DMAR unit if no pci devices exist */
3287 if (i == drhd->devices_cnt)
3288 drhd->ignored = 1;
3289 }
3290 }
3291
7c919779 3292 for_each_active_drhd_unit(drhd) {
ba395927 3293 int i;
7c919779 3294 if (drhd->include_all)
ba395927
KA		 3295 continue;
3296
3297 for (i = 0; i < drhd->devices_cnt; i++)
3298 if (drhd->devices[i] &&
c0771df8 3299 !IS_GFX_DEVICE(drhd->devices[i]))
ba395927
KA		 3300 break;
3301
3302 if (i < drhd->devices_cnt)
3303 continue;
3304
c0771df8
DW		 3305 /* This IOMMU has *only* gfx devices. Either bypass it or
3306 set the gfx_mapped flag, as appropriate */
3307 if (dmar_map_gfx) {
3308 intel_iommu_gfx_mapped = 1;
3309 } else {
3310 drhd->ignored = 1;
3311 for (i = 0; i < drhd->devices_cnt; i++) {
3312 if (!drhd->devices[i])
3313 continue;
3314 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3315 }
ba395927
KA		 3316 }
3317 }
3318}
3319
f59c7b69
FY		 3320#ifdef CONFIG_SUSPEND
3321static int init_iommu_hw(void)
3322{
3323 struct dmar_drhd_unit *drhd;
3324 struct intel_iommu *iommu = NULL;
3325
3326 for_each_active_iommu(iommu, drhd)
3327 if (iommu->qi)
3328 dmar_reenable_qi(iommu);
3329
b779260b
JC		 3330 for_each_iommu(iommu, drhd) {
3331 if (drhd->ignored) {
3332 /*
3333 * we always have to disable PMRs or DMA may fail on
3334 * this device
3335 */
3336 if (force_on)
3337 iommu_disable_protect_mem_regions(iommu);
3338 continue;
3339 }
3340
f59c7b69
FY		 3341 iommu_flush_write_buffer(iommu);
3342
3343 iommu_set_root_entry(iommu);
3344
3345 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3346 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3347 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3348 DMA_TLB_GLOBAL_FLUSH);
b779260b
JC		 3349 if (iommu_enable_translation(iommu))
3350 return 1;
b94996c9 3351 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3352 }
3353
3354 return 0;
3355}
3356
3357static void iommu_flush_all(void)
3358{
3359 struct dmar_drhd_unit *drhd;
3360 struct intel_iommu *iommu;
3361
3362 for_each_active_iommu(iommu, drhd) {
3363 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3364 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3365 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3366 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3367 }
3368}
3369
134fac3f 3370static int iommu_suspend(void)
f59c7b69
FY		 3371{
3372 struct dmar_drhd_unit *drhd;
3373 struct intel_iommu *iommu = NULL;
3374 unsigned long flag;
3375
3376 for_each_active_iommu(iommu, drhd) {
3377 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3378 GFP_ATOMIC);
3379 if (!iommu->iommu_state)
3380 goto nomem;
3381 }
3382
3383 iommu_flush_all();
3384
3385 for_each_active_iommu(iommu, drhd) {
3386 iommu_disable_translation(iommu);
3387
1f5b3c3f 3388 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3389
3390 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3391 readl(iommu->reg + DMAR_FECTL_REG);
3392 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3393 readl(iommu->reg + DMAR_FEDATA_REG);
3394 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3395 readl(iommu->reg + DMAR_FEADDR_REG);
3396 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3397 readl(iommu->reg + DMAR_FEUADDR_REG);
3398
1f5b3c3f 3399 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3400 }
3401 return 0;
3402
3403nomem:
3404 for_each_active_iommu(iommu, drhd)
3405 kfree(iommu->iommu_state);
3406
3407 return -ENOMEM;
3408}
3409
134fac3f 3410static void iommu_resume(void)
f59c7b69
FY		 3411{
3412 struct dmar_drhd_unit *drhd;
3413 struct intel_iommu *iommu = NULL;
3414 unsigned long flag;
3415
3416 if (init_iommu_hw()) {
b779260b
JC		 3417 if (force_on)
3418 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3419 else
3420 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3421 return;
f59c7b69
FY		 3422 }
3423
3424 for_each_active_iommu(iommu, drhd) {
3425
1f5b3c3f 3426 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3427
3428 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3429 iommu->reg + DMAR_FECTL_REG);
3430 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3431 iommu->reg + DMAR_FEDATA_REG);
3432 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3433 iommu->reg + DMAR_FEADDR_REG);
3434 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3435 iommu->reg + DMAR_FEUADDR_REG);
3436
1f5b3c3f 3437 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3438 }
3439
3440 for_each_active_iommu(iommu, drhd)
3441 kfree(iommu->iommu_state);
f59c7b69
FY		 3442}
3443
134fac3f 3444static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3445 .resume = iommu_resume,
3446 .suspend = iommu_suspend,
3447};
3448
134fac3f 3449static void __init init_iommu_pm_ops(void)
f59c7b69 3450{
134fac3f 3451 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3452}
3453
3454#else
99592ba4 3455static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3456#endif /* CONFIG_PM */
3457
318fe7df
SS		 3458static void __init dmar_register_rmrr_unit(struct dmar_rmrr_unit *rmrr)
3459{
3460 list_add(&rmrr->list, &dmar_rmrr_units);
3461}
3462
3463
3464int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3465{
3466 struct acpi_dmar_reserved_memory *rmrr;
3467 struct dmar_rmrr_unit *rmrru;
3468
3469 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3470 if (!rmrru)
3471 return -ENOMEM;
3472
3473 rmrru->hdr = header;
3474 rmrr = (struct acpi_dmar_reserved_memory *)header;
3475 rmrru->base_address = rmrr->base_address;
3476 rmrru->end_address = rmrr->end_address;
3477
3478 dmar_register_rmrr_unit(rmrru);
3479 return 0;
3480}
3481
3482static int __init
3483rmrr_parse_dev(struct dmar_rmrr_unit *rmrru)
3484{
3485 struct acpi_dmar_reserved_memory *rmrr;
318fe7df
SS		 3486
3487 rmrr = (struct acpi_dmar_reserved_memory *) rmrru->hdr;
9bdc531e
JL		 3488 return dmar_parse_dev_scope((void *)(rmrr + 1),
3489 ((void *)rmrr) + rmrr->header.length,
3490 &rmrru->devices_cnt, &rmrru->devices,
3491 rmrr->segment);
318fe7df
SS		 3492}
3493
318fe7df
SS		 3494int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3495{
3496 struct acpi_dmar_atsr *atsr;
3497 struct dmar_atsr_unit *atsru;
3498
3499 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3500 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3501 if (!atsru)
3502 return -ENOMEM;
3503
3504 atsru->hdr = hdr;
3505 atsru->include_all = atsr->flags & 0x1;
3506
3507 list_add(&atsru->list, &dmar_atsr_units);
3508
3509 return 0;
3510}
3511
3512static int __init atsr_parse_dev(struct dmar_atsr_unit *atsru)
3513{
318fe7df
SS		 3514 struct acpi_dmar_atsr *atsr;
3515
3516 if (atsru->include_all)
3517 return 0;
3518
3519 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
9bdc531e
JL		 3520 return dmar_parse_dev_scope((void *)(atsr + 1),
3521 (void *)atsr + atsr->header.length,
3522 &atsru->devices_cnt, &atsru->devices,
3523 atsr->segment);
3524}
3525
3526static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3527{
3528 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3529 kfree(atsru);
3530}
3531
3532static void intel_iommu_free_dmars(void)
3533{
3534 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3535 struct dmar_atsr_unit *atsru, *atsr_n;
3536
3537 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3538 list_del(&rmrru->list);
3539 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3540 kfree(rmrru);
318fe7df
SS		 3541 }
3542
9bdc531e
JL		 3543 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3544 list_del(&atsru->list);
3545 intel_iommu_free_atsr(atsru);
3546 }
318fe7df
SS		 3547}
3548
3549int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3550{
3551 int i;
3552 struct pci_bus *bus;
3553 struct acpi_dmar_atsr *atsr;
3554 struct dmar_atsr_unit *atsru;
3555
3556 dev = pci_physfn(dev);
3557
3558 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3559 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3560 if (atsr->segment == pci_domain_nr(dev->bus))
3561 goto found;
3562 }
3563
3564 return 0;
3565
3566found:
3567 for (bus = dev->bus; bus; bus = bus->parent) {
3568 struct pci_dev *bridge = bus->self;
3569
3570 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3571 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df
SS		 3572 return 0;
3573
62f87c0e 3574 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
318fe7df
SS		 3575 for (i = 0; i < atsru->devices_cnt; i++)
3576 if (atsru->devices[i] == bridge)
3577 return 1;
3578 break;
3579 }
3580 }
3581
3582 if (atsru->include_all)
3583 return 1;
3584
3585 return 0;
3586}
3587
c8f369ab 3588int __init dmar_parse_rmrr_atsr_dev(void)
318fe7df 3589{
9bdc531e
JL		 3590 struct dmar_rmrr_unit *rmrr;
3591 struct dmar_atsr_unit *atsr;
318fe7df
SS		 3592 int ret = 0;
3593
9bdc531e 3594 list_for_each_entry(rmrr, &dmar_rmrr_units, list) {
318fe7df
SS		 3595 ret = rmrr_parse_dev(rmrr);
3596 if (ret)
3597 return ret;
3598 }
3599
9bdc531e 3600 list_for_each_entry(atsr, &dmar_atsr_units, list) {
318fe7df
SS		 3601 ret = atsr_parse_dev(atsr);
3602 if (ret)
3603 return ret;
3604 }
3605
3606 return ret;
3607}
3608
99dcaded
FY		 3609/*
3610 * Here we only respond to action of unbound device from driver.
3611 *
3612 * Added device is not attached to its DMAR domain here yet. That will happen
3613 * when mapping the device to iova.
3614 */
3615static int device_notifier(struct notifier_block *nb,
3616 unsigned long action, void *data)
3617{
3618 struct device *dev = data;
3619 struct pci_dev *pdev = to_pci_dev(dev);
3620 struct dmar_domain *domain;
3621
816997d0 3622 if (iommu_dummy(pdev))
44cd613c
DW		 3623 return 0;
3624
7e7dfab7
JL		 3625 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3626 action != BUS_NOTIFY_DEL_DEVICE)
3627 return 0;
3628
99dcaded
FY		 3629 domain = find_domain(pdev);
3630 if (!domain)
3631 return 0;
3632
7e7dfab7
JL		 3633 domain_remove_one_dev_info(domain, pdev);
3634 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3635 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) &&
3636 list_empty(&domain->devices))
3637 domain_exit(domain);
a97590e5 3638
99dcaded
FY		 3639 return 0;
3640}
3641
3642static struct notifier_block device_nb = {
3643 .notifier_call = device_notifier,
3644};
3645
ba395927
KA		 3646int __init intel_iommu_init(void)
3647{
9bdc531e 3648 int ret = -ENODEV;
3a93c841 3649 struct dmar_drhd_unit *drhd;
7c919779 3650 struct intel_iommu *iommu;
ba395927 3651
a59b50e9
JC		 3652 /* VT-d is required for a TXT/tboot launch, so enforce that */
3653 force_on = tboot_force_iommu();
3654
3655 if (dmar_table_init()) {
3656 if (force_on)
3657 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 3658 goto out_free_dmar;
a59b50e9 3659 }
ba395927 3660
3a93c841
TI		 3661 /*
3662 * Disable translation if already enabled prior to OS handover.
3663 */
7c919779 3664 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 3665 if (iommu->gcmd & DMA_GCMD_TE)
3666 iommu_disable_translation(iommu);
3a93c841 3667
c2c7286a 3668 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 3669 if (force_on)
3670 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 3671 goto out_free_dmar;
a59b50e9 3672 }
1886e8a9 3673
75f1cdf1 3674 if (no_iommu || dmar_disabled)
9bdc531e 3675 goto out_free_dmar;
2ae21010 3676
51a63e67
JC		 3677 if (iommu_init_mempool()) {
3678 if (force_on)
3679 panic("tboot: Failed to initialize iommu memory\n");
9bdc531e 3680 goto out_free_dmar;
51a63e67
JC		 3681 }
3682
318fe7df
SS		 3683 if (list_empty(&dmar_rmrr_units))
3684 printk(KERN_INFO "DMAR: No RMRR found\n");
3685
3686 if (list_empty(&dmar_atsr_units))
3687 printk(KERN_INFO "DMAR: No ATSR found\n");
3688
51a63e67
JC		 3689 if (dmar_init_reserved_ranges()) {
3690 if (force_on)
3691 panic("tboot: Failed to reserve iommu ranges\n");
9bdc531e 3692 goto out_free_mempool;
51a63e67 3693 }
ba395927
KA		 3694
3695 init_no_remapping_devices();
3696
b779260b 3697 ret = init_dmars();
ba395927 3698 if (ret) {
a59b50e9
JC		 3699 if (force_on)
3700 panic("tboot: Failed to initialize DMARs\n");
ba395927 3701 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 3702 goto out_free_reserved_range;
ba395927
KA		 3703 }
3704 printk(KERN_INFO
3705 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3706
5e0d2a6f 3707 init_timer(&unmap_timer);
75f1cdf1
FT		 3708#ifdef CONFIG_SWIOTLB
3709 swiotlb = 0;
3710#endif
19943b0e 3711 dma_ops = &intel_dma_ops;
4ed0d3e6 3712
134fac3f 3713 init_iommu_pm_ops();
a8bcbb0d 3714
4236d97d 3715 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
a8bcbb0d 3716
99dcaded
FY		 3717 bus_register_notifier(&pci_bus_type, &device_nb);
3718
8bc1f85c
ED		 3719 intel_iommu_enabled = 1;
3720
ba395927 3721 return 0;
9bdc531e
JL		 3722
3723out_free_reserved_range:
3724 put_iova_domain(&reserved_iova_list);
3725out_free_mempool:
3726 iommu_exit_mempool();
3727out_free_dmar:
3728 intel_iommu_free_dmars();
3729 return ret;
ba395927 3730}
e820482c 3731
3199aa6b
HW		 3732static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3733 struct pci_dev *pdev)
3734{
3735 struct pci_dev *tmp, *parent;
3736
3737 if (!iommu || !pdev)
3738 return;
3739
3740 /* dependent device detach */
3741 tmp = pci_find_upstream_pcie_bridge(pdev);
3742 /* Secondary interface's bus number and devfn 0 */
3743 if (tmp) {
3744 parent = pdev->bus->self;
3745 while (parent != tmp) {
3746 iommu_detach_dev(iommu, parent->bus->number,
276dbf99 3747 parent->devfn);
3199aa6b
HW		 3748 parent = parent->bus->self;
3749 }
45e829ea 3750 if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */
3199aa6b
HW		 3751 iommu_detach_dev(iommu,
3752 tmp->subordinate->number, 0);
3753 else /* this is a legacy PCI bridge */
276dbf99
DW		 3754 iommu_detach_dev(iommu, tmp->bus->number,
3755 tmp->devfn);
3199aa6b
HW		 3756 }
3757}
3758
2c2e2c38 3759static void domain_remove_one_dev_info(struct dmar_domain *domain,
c7151a8d
WH		 3760 struct pci_dev *pdev)
3761{
bca2b916 3762 struct device_domain_info *info, *tmp;
c7151a8d
WH		 3763 struct intel_iommu *iommu;
3764 unsigned long flags;
3765 int found = 0;
c7151a8d 3766
276dbf99
DW		 3767 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3768 pdev->devfn);
c7151a8d
WH		 3769 if (!iommu)
3770 return;
3771
3772 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 3773 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
8519dc44
MH		 3774 if (info->segment == pci_domain_nr(pdev->bus) &&
3775 info->bus == pdev->bus->number &&
c7151a8d 3776 info->devfn == pdev->devfn) {
109b9b04 3777 unlink_domain_info(info);
c7151a8d
WH		 3778 spin_unlock_irqrestore(&device_domain_lock, flags);
3779
93a23a72 3780 iommu_disable_dev_iotlb(info);
c7151a8d 3781 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3782 iommu_detach_dependent_devices(iommu, pdev);
c7151a8d
WH		 3783 free_devinfo_mem(info);
3784
3785 spin_lock_irqsave(&device_domain_lock, flags);
3786
3787 if (found)
3788 break;
3789 else
3790 continue;
3791 }
3792
3793 /* if there is no other devices under the same iommu
3794 * owned by this domain, clear this iommu in iommu_bmp
3795 * update iommu count and coherency
3796 */
276dbf99
DW		 3797 if (iommu == device_to_iommu(info->segment, info->bus,
3798 info->devfn))
c7151a8d
WH		 3799 found = 1;
3800 }
3801
3e7abe25
RD		 3802 spin_unlock_irqrestore(&device_domain_lock, flags);
3803
c7151a8d
WH		 3804 if (found == 0) {
3805 unsigned long tmp_flags;
3806 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
1b198bb0 3807 clear_bit(iommu->seq_id, domain->iommu_bmp);
c7151a8d 3808 domain->iommu_count--;
58c610bd 3809 domain_update_iommu_cap(domain);
c7151a8d 3810 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
a97590e5 3811
9b4554b2
AW		 3812 if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) &&
3813 !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) {
3814 spin_lock_irqsave(&iommu->lock, tmp_flags);
3815 clear_bit(domain->id, iommu->domain_ids);
3816 iommu->domains[domain->id] = NULL;
3817 spin_unlock_irqrestore(&iommu->lock, tmp_flags);
3818 }
c7151a8d 3819 }
c7151a8d
WH		 3820}
3821
3822static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3823{
3824 struct device_domain_info *info;
3825 struct intel_iommu *iommu;
3826 unsigned long flags1, flags2;
3827
3828 spin_lock_irqsave(&device_domain_lock, flags1);
3829 while (!list_empty(&domain->devices)) {
3830 info = list_entry(domain->devices.next,
3831 struct device_domain_info, link);
109b9b04 3832 unlink_domain_info(info);
c7151a8d
WH		 3833 spin_unlock_irqrestore(&device_domain_lock, flags1);
3834
93a23a72 3835 iommu_disable_dev_iotlb(info);
276dbf99 3836 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
c7151a8d 3837 iommu_detach_dev(iommu, info->bus, info->devfn);
3199aa6b 3838 iommu_detach_dependent_devices(iommu, info->dev);
c7151a8d
WH		 3839
3840 /* clear this iommu in iommu_bmp, update iommu count
58c610bd 3841 * and capabilities
c7151a8d
WH		 3842 */
3843 spin_lock_irqsave(&domain->iommu_lock, flags2);
3844 if (test_and_clear_bit(iommu->seq_id,
1b198bb0 3845 domain->iommu_bmp)) {
c7151a8d 3846 domain->iommu_count--;
58c610bd 3847 domain_update_iommu_cap(domain);
c7151a8d
WH		 3848 }
3849 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3850
3851 free_devinfo_mem(info);
3852 spin_lock_irqsave(&device_domain_lock, flags1);
3853 }
3854 spin_unlock_irqrestore(&device_domain_lock, flags1);
3855}
3856
5e98c4b1 3857/* domain id for virtual machine, it won't be set in context */
18d99165 3858static atomic_t vm_domid = ATOMIC_INIT(0);
5e98c4b1
WH		 3859
3860static struct dmar_domain *iommu_alloc_vm_domain(void)
3861{
3862 struct dmar_domain *domain;
3863
3864 domain = alloc_domain_mem();
3865 if (!domain)
3866 return NULL;
3867
18d99165 3868 domain->id = atomic_inc_return(&vm_domid);
4c923d47 3869 domain->nid = -1;
1b198bb0 3870 memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp));
5e98c4b1
WH		 3871 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3872
3873 return domain;
3874}
3875
2c2e2c38 3876static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 3877{
3878 int adjust_width;
3879
3880 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 3881 spin_lock_init(&domain->iommu_lock);
3882
3883 domain_reserve_special_ranges(domain);
3884
3885 /* calculate AGAW */
3886 domain->gaw = guest_width;
3887 adjust_width = guestwidth_to_adjustwidth(guest_width);
3888 domain->agaw = width_to_agaw(adjust_width);
3889
3890 INIT_LIST_HEAD(&domain->devices);
3891
3892 domain->iommu_count = 0;
3893 domain->iommu_coherency = 0;
c5b15255 3894 domain->iommu_snooping = 0;
6dd9a7c7 3895 domain->iommu_superpage = 0;
fe40f1e0 3896 domain->max_addr = 0;
4c923d47 3897 domain->nid = -1;
5e98c4b1
WH		 3898
3899 /* always allocate the top pgd */
4c923d47 3900 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 3901 if (!domain->pgd)
3902 return -ENOMEM;
3903 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3904 return 0;
3905}
3906
3907static void iommu_free_vm_domain(struct dmar_domain *domain)
3908{
3909 unsigned long flags;
3910 struct dmar_drhd_unit *drhd;
3911 struct intel_iommu *iommu;
3912 unsigned long i;
3913 unsigned long ndomains;
3914
7c919779 3915 for_each_active_iommu(iommu, drhd) {
5e98c4b1 3916 ndomains = cap_ndoms(iommu->cap);
a45946ab 3917 for_each_set_bit(i, iommu->domain_ids, ndomains) {
5e98c4b1
WH		 3918 if (iommu->domains[i] == domain) {
3919 spin_lock_irqsave(&iommu->lock, flags);
3920 clear_bit(i, iommu->domain_ids);
3921 iommu->domains[i] = NULL;
3922 spin_unlock_irqrestore(&iommu->lock, flags);
3923 break;
3924 }
5e98c4b1
WH		 3925 }
3926 }
3927}
3928
3929static void vm_domain_exit(struct dmar_domain *domain)
3930{
5e98c4b1
WH		 3931 /* Domain 0 is reserved, so dont process it */
3932 if (!domain)
3933 return;
3934
3935 vm_domain_remove_all_dev_info(domain);
3936 /* destroy iovas */
3937 put_iova_domain(&domain->iovad);
5e98c4b1
WH		 3938
3939 /* clear ptes */
595badf5 3940 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3941
3942 /* free page tables */
d794dc9b 3943 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
5e98c4b1
WH		 3944
3945 iommu_free_vm_domain(domain);
3946 free_domain_mem(domain);
3947}
3948
5d450806 3949static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 3950{
5d450806 3951 struct dmar_domain *dmar_domain;
38717946 3952
5d450806
JR		 3953 dmar_domain = iommu_alloc_vm_domain();
3954 if (!dmar_domain) {
38717946 3955 printk(KERN_ERR
5d450806
JR		 3956 "intel_iommu_domain_init: dmar_domain == NULL\n");
3957 return -ENOMEM;
38717946 3958 }
2c2e2c38 3959 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 3960 printk(KERN_ERR
5d450806
JR		 3961 "intel_iommu_domain_init() failed\n");
3962 vm_domain_exit(dmar_domain);
3963 return -ENOMEM;
38717946 3964 }
8140a95d 3965 domain_update_iommu_cap(dmar_domain);
5d450806 3966 domain->priv = dmar_domain;
faa3d6f5 3967
8a0e715b
JR		 3968 domain->geometry.aperture_start = 0;
3969 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
3970 domain->geometry.force_aperture = true;
3971
5d450806 3972 return 0;
38717946 3973}
38717946 3974
5d450806 3975static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 3976{
5d450806
JR		 3977 struct dmar_domain *dmar_domain = domain->priv;
3978
3979 domain->priv = NULL;
3980 vm_domain_exit(dmar_domain);
38717946 3981}
38717946 3982
4c5478c9
JR		 3983static int intel_iommu_attach_device(struct iommu_domain *domain,
3984 struct device *dev)
38717946 3985{
4c5478c9
JR		 3986 struct dmar_domain *dmar_domain = domain->priv;
3987 struct pci_dev *pdev = to_pci_dev(dev);
fe40f1e0
WH		 3988 struct intel_iommu *iommu;
3989 int addr_width;
faa3d6f5
WH		 3990
3991 /* normally pdev is not mapped */
3992 if (unlikely(domain_context_mapped(pdev))) {
3993 struct dmar_domain *old_domain;
3994
3995 old_domain = find_domain(pdev);
3996 if (old_domain) {
2c2e2c38
FY		 3997 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3998 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3999 domain_remove_one_dev_info(old_domain, pdev);
faa3d6f5
WH		 4000 else
4001 domain_remove_dev_info(old_domain);
4002 }
4003 }
4004
276dbf99
DW		 4005 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
4006 pdev->devfn);
fe40f1e0
WH		 4007 if (!iommu)
4008 return -ENODEV;
4009
4010 /* check if this iommu agaw is sufficient for max mapped address */
4011 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4012 if (addr_width > cap_mgaw(iommu->cap))
4013 addr_width = cap_mgaw(iommu->cap);
4014
4015 if (dmar_domain->max_addr > (1LL << addr_width)) {
4016 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4017 "sufficient for the mapped address (%llx)\n",
a99c47a2 4018 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4019 return -EFAULT;
4020 }
a99c47a2
TL		 4021 dmar_domain->gaw = addr_width;
4022
4023 /*
4024 * Knock out extra levels of page tables if necessary
4025 */
4026 while (iommu->agaw < dmar_domain->agaw) {
4027 struct dma_pte *pte;
4028
4029 pte = dmar_domain->pgd;
4030 if (dma_pte_present(pte)) {
25cbff16
SY		 4031 dmar_domain->pgd = (struct dma_pte *)
4032 phys_to_virt(dma_pte_addr(pte));
7a661013 4033 free_pgtable_page(pte);
a99c47a2
TL		 4034 }
4035 dmar_domain->agaw--;
4036 }
fe40f1e0 4037
5fe60f4e 4038 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
38717946 4039}
38717946 4040
4c5478c9
JR		 4041static void intel_iommu_detach_device(struct iommu_domain *domain,
4042 struct device *dev)
38717946 4043{
4c5478c9
JR		 4044 struct dmar_domain *dmar_domain = domain->priv;
4045 struct pci_dev *pdev = to_pci_dev(dev);
4046
2c2e2c38 4047 domain_remove_one_dev_info(dmar_domain, pdev);
faa3d6f5 4048}
c7151a8d 4049
b146a1c9
JR		 4050static int intel_iommu_map(struct iommu_domain *domain,
4051 unsigned long iova, phys_addr_t hpa,
5009065d 4052 size_t size, int iommu_prot)
faa3d6f5 4053{
dde57a21 4054 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4055 u64 max_addr;
dde57a21 4056 int prot = 0;
faa3d6f5 4057 int ret;
fe40f1e0 4058
dde57a21
JR		 4059 if (iommu_prot & IOMMU_READ)
4060 prot |= DMA_PTE_READ;
4061 if (iommu_prot & IOMMU_WRITE)
4062 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4063 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4064 prot |= DMA_PTE_SNP;
dde57a21 4065
163cc52c 4066 max_addr = iova + size;
dde57a21 4067 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4068 u64 end;
4069
4070 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4071 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4072 if (end < max_addr) {
8954da1f 4073 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4074 "sufficient for the mapped address (%llx)\n",
8954da1f 4075 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4076 return -EFAULT;
4077 }
dde57a21 4078 dmar_domain->max_addr = max_addr;
fe40f1e0 4079 }
ad051221
DW		 4080 /* Round up size to next multiple of PAGE_SIZE, if it and
4081 the low bits of hpa would take us onto the next page */
88cb6a74 4082 size = aligned_nrpages(hpa, size);
ad051221
DW		 4083 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4084 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4085 return ret;
38717946 4086}
38717946 4087
5009065d
OBC		 4088static size_t intel_iommu_unmap(struct iommu_domain *domain,
4089 unsigned long iova, size_t size)
38717946 4090{
dde57a21 4091 struct dmar_domain *dmar_domain = domain->priv;
292827cb 4092 int order;
4b99d352 4093
292827cb 4094 order = dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
163cc52c 4095 (iova + size - 1) >> VTD_PAGE_SHIFT);
fe40f1e0 4096
163cc52c
DW		 4097 if (dmar_domain->max_addr == iova + size)
4098 dmar_domain->max_addr = iova;
b146a1c9 4099
5009065d 4100 return PAGE_SIZE << order;
38717946 4101}
38717946 4102
d14d6577 4103static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4104 dma_addr_t iova)
38717946 4105{
d14d6577 4106 struct dmar_domain *dmar_domain = domain->priv;
38717946 4107 struct dma_pte *pte;
faa3d6f5 4108 u64 phys = 0;
38717946 4109
6dd9a7c7 4110 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, 0);
38717946 4111 if (pte)
faa3d6f5 4112 phys = dma_pte_addr(pte);
38717946 4113
faa3d6f5 4114 return phys;
38717946 4115}
a8bcbb0d 4116
dbb9fd86
SY		 4117static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4118 unsigned long cap)
4119{
4120 struct dmar_domain *dmar_domain = domain->priv;
4121
4122 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4123 return dmar_domain->iommu_snooping;
323f99cb 4124 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4125 return irq_remapping_enabled;
dbb9fd86
SY		 4126
4127 return 0;
4128}
4129
783f157b 4130#define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF)
70ae6f0d 4131
abdfdde2
AW		 4132static int intel_iommu_add_device(struct device *dev)
4133{
4134 struct pci_dev *pdev = to_pci_dev(dev);
3da4af0a 4135 struct pci_dev *bridge, *dma_pdev = NULL;
abdfdde2
AW		 4136 struct iommu_group *group;
4137 int ret;
70ae6f0d 4138
abdfdde2
AW		 4139 if (!device_to_iommu(pci_domain_nr(pdev->bus),
4140 pdev->bus->number, pdev->devfn))
70ae6f0d
AW		 4141 return -ENODEV;
4142
4143 bridge = pci_find_upstream_pcie_bridge(pdev);
4144 if (bridge) {
abdfdde2
AW		 4145 if (pci_is_pcie(bridge))
4146 dma_pdev = pci_get_domain_bus_and_slot(
4147 pci_domain_nr(pdev->bus),
4148 bridge->subordinate->number, 0);
3da4af0a 4149 if (!dma_pdev)
abdfdde2
AW		 4150 dma_pdev = pci_dev_get(bridge);
4151 } else
4152 dma_pdev = pci_dev_get(pdev);
4153
a4ff1fc2 4154 /* Account for quirked devices */
783f157b
AW		 4155 swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev));
4156
a4ff1fc2
AW		 4157 /*
4158 * If it's a multifunction device that does not support our
c14d2690
AW		 4159 * required ACS flags, add to the same group as lowest numbered
4160 * function that also does not suport the required ACS flags.
a4ff1fc2 4161 */
783f157b 4162 if (dma_pdev->multifunction &&
c14d2690
AW		 4163 !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) {
4164 u8 i, slot = PCI_SLOT(dma_pdev->devfn);
4165
4166 for (i = 0; i < 8; i++) {
4167 struct pci_dev *tmp;
4168
4169 tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i));
4170 if (!tmp)
4171 continue;
4172
4173 if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) {
4174 swap_pci_ref(&dma_pdev, tmp);
4175 break;
4176 }
4177 pci_dev_put(tmp);
4178 }
4179 }
783f157b 4180
a4ff1fc2
AW		 4181 /*
4182 * Devices on the root bus go through the iommu. If that's not us,
4183 * find the next upstream device and test ACS up to the root bus.
4184 * Finding the next device may require skipping virtual buses.
4185 */
783f157b 4186 while (!pci_is_root_bus(dma_pdev->bus)) {
a4ff1fc2
AW		 4187 struct pci_bus *bus = dma_pdev->bus;
4188
4189 while (!bus->self) {
4190 if (!pci_is_root_bus(bus))
4191 bus = bus->parent;
4192 else
4193 goto root_bus;
4194 }
4195
4196 if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS))
783f157b
AW		 4197 break;
4198
a4ff1fc2 4199 swap_pci_ref(&dma_pdev, pci_dev_get(bus->self));
783f157b
AW		 4200 }
4201
a4ff1fc2 4202root_bus:
abdfdde2
AW		 4203 group = iommu_group_get(&dma_pdev->dev);
4204 pci_dev_put(dma_pdev);
4205 if (!group) {
4206 group = iommu_group_alloc();
4207 if (IS_ERR(group))
4208 return PTR_ERR(group);
70ae6f0d
AW		 4209 }
4210
abdfdde2 4211 ret = iommu_group_add_device(group, dev);
bcb71abe 4212
abdfdde2
AW		 4213 iommu_group_put(group);
4214 return ret;
4215}
70ae6f0d 4216
abdfdde2
AW		 4217static void intel_iommu_remove_device(struct device *dev)
4218{
4219 iommu_group_remove_device(dev);
70ae6f0d
AW		 4220}
4221
a8bcbb0d
JR		 4222static struct iommu_ops intel_iommu_ops = {
4223 .domain_init = intel_iommu_domain_init,
4224 .domain_destroy = intel_iommu_domain_destroy,
4225 .attach_dev = intel_iommu_attach_device,
4226 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4227 .map = intel_iommu_map,
4228 .unmap = intel_iommu_unmap,
a8bcbb0d 4229 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4230 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4231 .add_device = intel_iommu_add_device,
4232 .remove_device = intel_iommu_remove_device,
6d1c56a9 4233 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4234};
9af88143 4235
9452618e
DV		 4236static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4237{
4238 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4239 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4240 dmar_map_gfx = 0;
4241}
4242
4243DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4244DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4245DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4247DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4248DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4249DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4250
d34d6517 4251static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4252{
4253 /*
4254 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4255 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4256 */
4257 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4258 rwbf_quirk = 1;
4259}
4260
4261DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4262DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4263DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4266DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4268
eecfd57f
AJ		 4269#define GGC 0x52
4270#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4271#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4272#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4273#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4274#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4275#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4276#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4277#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4278
d34d6517 4279static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4280{
4281 unsigned short ggc;
4282
eecfd57f 4283 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4284 return;
4285
eecfd57f 4286 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4287 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4288 dmar_map_gfx = 0;
6fbcfb3e
DW		 4289 } else if (dmar_map_gfx) {
4290 /* we have to ensure the gfx device is idle before we flush */
4291 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4292 intel_iommu_strict = 1;
4293 }
9eecabcb
DW		 4294}
4295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4296DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4299
e0fc7e0b
DW		 4300/* On Tylersburg chipsets, some BIOSes have been known to enable the
4301 ISOCH DMAR unit for the Azalia sound device, but not give it any
4302 TLB entries, which causes it to deadlock. Check for that. We do
4303 this in a function called from init_dmars(), instead of in a PCI
4304 quirk, because we don't want to print the obnoxious "BIOS broken"
4305 message if VT-d is actually disabled.
4306*/
4307static void __init check_tylersburg_isoch(void)
4308{
4309 struct pci_dev *pdev;
4310 uint32_t vtisochctrl;
4311
4312 /* If there's no Azalia in the system anyway, forget it. */
4313 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4314 if (!pdev)
4315 return;
4316 pci_dev_put(pdev);
4317
4318 /* System Management Registers. Might be hidden, in which case
4319 we can't do the sanity check. But that's OK, because the
4320 known-broken BIOSes _don't_ actually hide it, so far. */
4321 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4322 if (!pdev)
4323 return;
4324
4325 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4326 pci_dev_put(pdev);
4327 return;
4328 }
4329
4330 pci_dev_put(pdev);
4331
4332 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4333 if (vtisochctrl & 1)
4334 return;
4335
4336 /* Drop all bits other than the number of TLB entries */
4337 vtisochctrl &= 0x1c;
4338
4339 /* If we have the recommended number of TLB entries (16), fine. */
4340 if (vtisochctrl == 0x10)
4341 return;
4342
4343 /* Zero TLB entries? You get to ride the short bus to school. */
4344 if (!vtisochctrl) {
4345 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4346 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4347 dmi_get_system_info(DMI_BIOS_VENDOR),
4348 dmi_get_system_info(DMI_BIOS_VERSION),
4349 dmi_get_system_info(DMI_PRODUCT_VERSION));
4350 iommu_identity_mapping |= IDENTMAP_AZALIA;
4351 return;
4352 }
4353
4354 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4355 vtisochctrl);
4356}
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