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iommu/vt-d: Simplify intel_unmap_sg() and kill duplicated code
[mirror_ubuntu-jammy-kernel.git] / drivers / iommu / intel-iommu.c
CommitLineData
ba395927 1/*
ea8ea460 2 * Copyright © 2006-2014 Intel Corporation.
ba395927
KA		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
ea8ea460
DW		 13 * Authors: David Woodhouse <dwmw2@infradead.org>,
14 * Ashok Raj <ashok.raj@intel.com>,
15 * Shaohua Li <shaohua.li@intel.com>,
16 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>,
17 * Fenghua Yu <fenghua.yu@intel.com>
ba395927
KA		 18 */
19
20#include <linux/init.h>
21#include <linux/bitmap.h>
5e0d2a6f 22#include <linux/debugfs.h>
54485c30 23#include <linux/export.h>
ba395927
KA		 24#include <linux/slab.h>
25#include <linux/irq.h>
26#include <linux/interrupt.h>
ba395927
KA		 27#include <linux/spinlock.h>
28#include <linux/pci.h>
29#include <linux/dmar.h>
30#include <linux/dma-mapping.h>
31#include <linux/mempool.h>
75f05569 32#include <linux/memory.h>
5e0d2a6f 33#include <linux/timer.h>
38717946 34#include <linux/iova.h>
5d450806 35#include <linux/iommu.h>
38717946 36#include <linux/intel-iommu.h>
134fac3f 37#include <linux/syscore_ops.h>
69575d38 38#include <linux/tboot.h>
adb2fe02 39#include <linux/dmi.h>
5cdede24 40#include <linux/pci-ats.h>
0ee332c1 41#include <linux/memblock.h>
36746436 42#include <linux/dma-contiguous.h>
8a8f422d 43#include <asm/irq_remapping.h>
ba395927 44#include <asm/cacheflush.h>
46a7fa27 45#include <asm/iommu.h>
ba395927 46
078e1ee2
JR		 47#include "irq_remapping.h"
48
5b6985ce
FY		 49#define ROOT_SIZE VTD_PAGE_SIZE
50#define CONTEXT_SIZE VTD_PAGE_SIZE
51
ba395927
KA		 52#define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
53#define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
e0fc7e0b 54#define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e)
ba395927
KA		 55
56#define IOAPIC_RANGE_START (0xfee00000)
57#define IOAPIC_RANGE_END (0xfeefffff)
58#define IOVA_START_ADDR (0x1000)
59
60#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
61
4ed0d3e6 62#define MAX_AGAW_WIDTH 64
5c645b35 63#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
4ed0d3e6 64
2ebe3151
DW		 65#define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
66#define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
67
68/* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
69 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
70#define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
71 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
72#define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
ba395927 73
f27be03b 74#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
284901a9 75#define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
6a35528a 76#define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
5e0d2a6f 77
df08cdc7
AM		 78/* page table handling */
79#define LEVEL_STRIDE (9)
80#define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
81
6d1c56a9
OBC		 82/*
83 * This bitmap is used to advertise the page sizes our hardware support
84 * to the IOMMU core, which will then use this information to split
85 * physically contiguous memory regions it is mapping into page sizes
86 * that we support.
87 *
88 * Traditionally the IOMMU core just handed us the mappings directly,
89 * after making sure the size is an order of a 4KiB page and that the
90 * mapping has natural alignment.
91 *
92 * To retain this behavior, we currently advertise that we support
93 * all page sizes that are an order of 4KiB.
94 *
95 * If at some point we'd like to utilize the IOMMU core's new behavior,
96 * we could change this to advertise the real page sizes we support.
97 */
98#define INTEL_IOMMU_PGSIZES (~0xFFFUL)
99
df08cdc7
AM		 100static inline int agaw_to_level(int agaw)
101{
102 return agaw + 2;
103}
104
105static inline int agaw_to_width(int agaw)
106{
5c645b35 107 return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH);
df08cdc7
AM		 108}
109
110static inline int width_to_agaw(int width)
111{
5c645b35 112 return DIV_ROUND_UP(width - 30, LEVEL_STRIDE);
df08cdc7
AM		 113}
114
115static inline unsigned int level_to_offset_bits(int level)
116{
117 return (level - 1) * LEVEL_STRIDE;
118}
119
120static inline int pfn_level_offset(unsigned long pfn, int level)
121{
122 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
123}
124
125static inline unsigned long level_mask(int level)
126{
127 return -1UL << level_to_offset_bits(level);
128}
129
130static inline unsigned long level_size(int level)
131{
132 return 1UL << level_to_offset_bits(level);
133}
134
135static inline unsigned long align_to_level(unsigned long pfn, int level)
136{
137 return (pfn + level_size(level) - 1) & level_mask(level);
138}
fd18de50 139
6dd9a7c7
YS		 140static inline unsigned long lvl_to_nr_pages(unsigned int lvl)
141{
5c645b35 142 return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH);
6dd9a7c7
YS		 143}
144
dd4e8319
DW		 145/* VT-d pages must always be _smaller_ than MM pages. Otherwise things
146 are never going to work. */
147static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
148{
149 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
150}
151
152static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
153{
154 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
155}
156static inline unsigned long page_to_dma_pfn(struct page *pg)
157{
158 return mm_to_dma_pfn(page_to_pfn(pg));
159}
160static inline unsigned long virt_to_dma_pfn(void *p)
161{
162 return page_to_dma_pfn(virt_to_page(p));
163}
164
d9630fe9
WH		 165/* global iommu list, set NULL for ignored DMAR units */
166static struct intel_iommu **g_iommus;
167
e0fc7e0b 168static void __init check_tylersburg_isoch(void);
9af88143
DW		 169static int rwbf_quirk;
170
b779260b
JC		 171/*
172 * set to 1 to panic kernel if can't successfully enable VT-d
173 * (used when kernel is launched w/ TXT)
174 */
175static int force_on = 0;
176
46b08e1a
MM		 177/*
178 * 0: Present
179 * 1-11: Reserved
180 * 12-63: Context Ptr (12 - (haw-1))
181 * 64-127: Reserved
182 */
183struct root_entry {
184 u64 val;
185 u64 rsvd1;
186};
187#define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
188static inline bool root_present(struct root_entry *root)
189{
190 return (root->val & 1);
191}
192static inline void set_root_present(struct root_entry *root)
193{
194 root->val |= 1;
195}
196static inline void set_root_value(struct root_entry *root, unsigned long value)
197{
198 root->val |= value & VTD_PAGE_MASK;
199}
200
201static inline struct context_entry *
202get_context_addr_from_root(struct root_entry *root)
203{
204 return (struct context_entry *)
205 (root_present(root)?phys_to_virt(
206 root->val & VTD_PAGE_MASK) :
207 NULL);
208}
209
7a8fc25e
MM		 210/*
211 * low 64 bits:
212 * 0: present
213 * 1: fault processing disable
214 * 2-3: translation type
215 * 12-63: address space root
216 * high 64 bits:
217 * 0-2: address width
218 * 3-6: aval
219 * 8-23: domain id
220 */
221struct context_entry {
222 u64 lo;
223 u64 hi;
224};
c07e7d21
MM		 225
226static inline bool context_present(struct context_entry *context)
227{
228 return (context->lo & 1);
229}
230static inline void context_set_present(struct context_entry *context)
231{
232 context->lo |= 1;
233}
234
235static inline void context_set_fault_enable(struct context_entry *context)
236{
237 context->lo &= (((u64)-1) << 2) | 1;
238}
239
c07e7d21
MM		 240static inline void context_set_translation_type(struct context_entry *context,
241 unsigned long value)
242{
243 context->lo &= (((u64)-1) << 4) | 3;
244 context->lo |= (value & 3) << 2;
245}
246
247static inline void context_set_address_root(struct context_entry *context,
248 unsigned long value)
249{
250 context->lo |= value & VTD_PAGE_MASK;
251}
252
253static inline void context_set_address_width(struct context_entry *context,
254 unsigned long value)
255{
256 context->hi |= value & 7;
257}
258
259static inline void context_set_domain_id(struct context_entry *context,
260 unsigned long value)
261{
262 context->hi |= (value & ((1 << 16) - 1)) << 8;
263}
264
265static inline void context_clear_entry(struct context_entry *context)
266{
267 context->lo = 0;
268 context->hi = 0;
269}
7a8fc25e 270
622ba12a
MM		 271/*
272 * 0: readable
273 * 1: writable
274 * 2-6: reserved
275 * 7: super page
9cf06697
SY		 276 * 8-10: available
277 * 11: snoop behavior
622ba12a
MM		 278 * 12-63: Host physcial address
279 */
280struct dma_pte {
281 u64 val;
282};
622ba12a 283
19c239ce
MM		 284static inline void dma_clear_pte(struct dma_pte *pte)
285{
286 pte->val = 0;
287}
288
19c239ce
MM		 289static inline u64 dma_pte_addr(struct dma_pte *pte)
290{
c85994e4
DW		 291#ifdef CONFIG_64BIT
292 return pte->val & VTD_PAGE_MASK;
293#else
294 /* Must have a full atomic 64-bit read */
1a8bd481 295 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
c85994e4 296#endif
19c239ce
MM		 297}
298
19c239ce
MM		 299static inline bool dma_pte_present(struct dma_pte *pte)
300{
301 return (pte->val & 3) != 0;
302}
622ba12a 303
4399c8bf
AK		 304static inline bool dma_pte_superpage(struct dma_pte *pte)
305{
c3c75eb7 306 return (pte->val & DMA_PTE_LARGE_PAGE);
4399c8bf
AK		 307}
308
75e6bf96
DW		 309static inline int first_pte_in_page(struct dma_pte *pte)
310{
311 return !((unsigned long)pte & ~VTD_PAGE_MASK);
312}
313
2c2e2c38
FY		 314/*
315 * This domain is a statically identity mapping domain.
316 * 1. This domain creats a static 1:1 mapping to all usable memory.
317 * 2. It maps to each iommu if successful.
318 * 3. Each iommu mapps to this domain if successful.
319 */
19943b0e
DW		 320static struct dmar_domain *si_domain;
321static int hw_pass_through = 1;
2c2e2c38 322
1ce28feb
WH		 323/* domain represents a virtual machine, more than one devices
324 * across iommus may be owned in one domain, e.g. kvm guest.
325 */
ab8dfe25 326#define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0)
1ce28feb 327
2c2e2c38 328/* si_domain contains mulitple devices */
ab8dfe25 329#define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1)
2c2e2c38 330
1b198bb0
MT		 331/* define the limit of IOMMUs supported in each domain */
332#ifdef CONFIG_X86
333# define IOMMU_UNITS_SUPPORTED MAX_IO_APICS
334#else
335# define IOMMU_UNITS_SUPPORTED 64
336#endif
337
99126f7c
MM		 338struct dmar_domain {
339 int id; /* domain id */
4c923d47 340 int nid; /* node id */
1b198bb0
MT		 341 DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED);
342 /* bitmap of iommus this domain uses*/
99126f7c
MM		 343
344 struct list_head devices; /* all devices' list */
345 struct iova_domain iovad; /* iova's that belong to this domain */
346
347 struct dma_pte *pgd; /* virtual address */
99126f7c
MM		 348 int gaw; /* max guest address width */
349
350 /* adjusted guest address width, 0 is level 2 30-bit */
351 int agaw;
352
3b5410e7 353 int flags; /* flags to find out type of domain */
8e604097
WH		 354
355 int iommu_coherency;/* indicate coherency of iommu access */
58c610bd 356 int iommu_snooping; /* indicate snooping control feature*/
c7151a8d 357 int iommu_count; /* reference count of iommu */
6dd9a7c7
YS		 358 int iommu_superpage;/* Level of superpages supported:
359 0 == 4KiB (no superpages), 1 == 2MiB,
360 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
c7151a8d 361 spinlock_t iommu_lock; /* protect iommu set in domain */
fe40f1e0 362 u64 max_addr; /* maximum mapped address */
99126f7c
MM		 363};
364
a647dacb
MM		 365/* PCI domain-device relationship */
366struct device_domain_info {
367 struct list_head link; /* link to domain siblings */
368 struct list_head global; /* link to global list */
276dbf99 369 u8 bus; /* PCI bus number */
a647dacb 370 u8 devfn; /* PCI devfn number */
0bcb3e28 371 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
93a23a72 372 struct intel_iommu *iommu; /* IOMMU used by this device */
a647dacb
MM		 373 struct dmar_domain *domain; /* pointer to domain */
374};
375
b94e4117
JL		 376struct dmar_rmrr_unit {
377 struct list_head list; /* list of rmrr units */
378 struct acpi_dmar_header *hdr; /* ACPI header */
379 u64 base_address; /* reserved base address*/
380 u64 end_address; /* reserved end address */
832bd858 381 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 382 int devices_cnt; /* target device count */
383};
384
385struct dmar_atsr_unit {
386 struct list_head list; /* list of ATSR units */
387 struct acpi_dmar_header *hdr; /* ACPI header */
832bd858 388 struct dmar_dev_scope *devices; /* target devices */
b94e4117
JL		 389 int devices_cnt; /* target device count */
390 u8 include_all:1; /* include all ports */
391};
392
393static LIST_HEAD(dmar_atsr_units);
394static LIST_HEAD(dmar_rmrr_units);
395
396#define for_each_rmrr_units(rmrr) \
397 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
398
5e0d2a6f 399static void flush_unmaps_timeout(unsigned long data);
400
b707cb02 401static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
5e0d2a6f 402
80b20dd8 403#define HIGH_WATER_MARK 250
404struct deferred_flush_tables {
405 int next;
406 struct iova *iova[HIGH_WATER_MARK];
407 struct dmar_domain *domain[HIGH_WATER_MARK];
ea8ea460 408 struct page *freelist[HIGH_WATER_MARK];
80b20dd8 409};
410
411static struct deferred_flush_tables *deferred_flush;
412
5e0d2a6f 413/* bitmap for indexing intel_iommus */
5e0d2a6f 414static int g_num_of_iommus;
415
416static DEFINE_SPINLOCK(async_umap_flush_lock);
417static LIST_HEAD(unmaps_to_do);
418
419static int timer_on;
420static long list_size;
5e0d2a6f 421
92d03cc8 422static void domain_exit(struct dmar_domain *domain);
ba395927 423static void domain_remove_dev_info(struct dmar_domain *domain);
b94e4117 424static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 425 struct device *dev);
92d03cc8 426static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 427 struct device *dev);
2a46ddf7
JL		 428static int domain_detach_iommu(struct dmar_domain *domain,
429 struct intel_iommu *iommu);
ba395927 430
d3f13810 431#ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON
0cd5c3c8
KM		 432int dmar_disabled = 0;
433#else
434int dmar_disabled = 1;
d3f13810 435#endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/
0cd5c3c8 436
8bc1f85c
ED		 437int intel_iommu_enabled = 0;
438EXPORT_SYMBOL_GPL(intel_iommu_enabled);
439
2d9e667e 440static int dmar_map_gfx = 1;
7d3b03ce 441static int dmar_forcedac;
5e0d2a6f 442static int intel_iommu_strict;
6dd9a7c7 443static int intel_iommu_superpage = 1;
ba395927 444
c0771df8
DW		 445int intel_iommu_gfx_mapped;
446EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped);
447
ba395927
KA		 448#define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
449static DEFINE_SPINLOCK(device_domain_lock);
450static LIST_HEAD(device_domain_list);
451
b22f6434 452static const struct iommu_ops intel_iommu_ops;
a8bcbb0d 453
ba395927
KA		 454static int __init intel_iommu_setup(char *str)
455{
456 if (!str)
457 return -EINVAL;
458 while (*str) {
0cd5c3c8
KM		 459 if (!strncmp(str, "on", 2)) {
460 dmar_disabled = 0;
461 printk(KERN_INFO "Intel-IOMMU: enabled\n");
462 } else if (!strncmp(str, "off", 3)) {
ba395927 463 dmar_disabled = 1;
0cd5c3c8 464 printk(KERN_INFO "Intel-IOMMU: disabled\n");
ba395927
KA		 465 } else if (!strncmp(str, "igfx_off", 8)) {
466 dmar_map_gfx = 0;
467 printk(KERN_INFO
468 "Intel-IOMMU: disable GFX device mapping\n");
7d3b03ce 469 } else if (!strncmp(str, "forcedac", 8)) {
5e0d2a6f 470 printk(KERN_INFO
7d3b03ce
KA		 471 "Intel-IOMMU: Forcing DAC for PCI devices\n");
472 dmar_forcedac = 1;
5e0d2a6f 473 } else if (!strncmp(str, "strict", 6)) {
474 printk(KERN_INFO
475 "Intel-IOMMU: disable batched IOTLB flush\n");
476 intel_iommu_strict = 1;
6dd9a7c7
YS		 477 } else if (!strncmp(str, "sp_off", 6)) {
478 printk(KERN_INFO
479 "Intel-IOMMU: disable supported super page\n");
480 intel_iommu_superpage = 0;
ba395927
KA		 481 }
482
483 str += strcspn(str, ",");
484 while (*str == ',')
485 str++;
486 }
487 return 0;
488}
489__setup("intel_iommu=", intel_iommu_setup);
490
491static struct kmem_cache *iommu_domain_cache;
492static struct kmem_cache *iommu_devinfo_cache;
493static struct kmem_cache *iommu_iova_cache;
494
4c923d47 495static inline void *alloc_pgtable_page(int node)
eb3fa7cb 496{
4c923d47
SS		 497 struct page *page;
498 void *vaddr = NULL;
eb3fa7cb 499
4c923d47
SS		 500 page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0);
501 if (page)
502 vaddr = page_address(page);
eb3fa7cb 503 return vaddr;
ba395927
KA		 504}
505
506static inline void free_pgtable_page(void *vaddr)
507{
508 free_page((unsigned long)vaddr);
509}
510
511static inline void *alloc_domain_mem(void)
512{
354bb65e 513 return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC);
ba395927
KA		 514}
515
38717946 516static void free_domain_mem(void *vaddr)
ba395927
KA		 517{
518 kmem_cache_free(iommu_domain_cache, vaddr);
519}
520
521static inline void * alloc_devinfo_mem(void)
522{
354bb65e 523 return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC);
ba395927
KA		 524}
525
526static inline void free_devinfo_mem(void *vaddr)
527{
528 kmem_cache_free(iommu_devinfo_cache, vaddr);
529}
530
531struct iova *alloc_iova_mem(void)
532{
354bb65e 533 return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC);
ba395927
KA		 534}
535
536void free_iova_mem(struct iova *iova)
537{
538 kmem_cache_free(iommu_iova_cache, iova);
539}
540
ab8dfe25
JL		 541static inline int domain_type_is_vm(struct dmar_domain *domain)
542{
543 return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE;
544}
545
546static inline int domain_type_is_vm_or_si(struct dmar_domain *domain)
547{
548 return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE |
549 DOMAIN_FLAG_STATIC_IDENTITY);
550}
1b573683 551
4ed0d3e6 552static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
1b573683
WH		 553{
554 unsigned long sagaw;
555 int agaw = -1;
556
557 sagaw = cap_sagaw(iommu->cap);
4ed0d3e6 558 for (agaw = width_to_agaw(max_gaw);
1b573683
WH		 559 agaw >= 0; agaw--) {
560 if (test_bit(agaw, &sagaw))
561 break;
562 }
563
564 return agaw;
565}
566
4ed0d3e6
FY		 567/*
568 * Calculate max SAGAW for each iommu.
569 */
570int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
571{
572 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
573}
574
575/*
576 * calculate agaw for each iommu.
577 * "SAGAW" may be different across iommus, use a default agaw, and
578 * get a supported less agaw for iommus that don't support the default agaw.
579 */
580int iommu_calculate_agaw(struct intel_iommu *iommu)
581{
582 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
583}
584
2c2e2c38 585/* This functionin only returns single iommu in a domain */
8c11e798
WH		 586static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
587{
588 int iommu_id;
589
2c2e2c38 590 /* si_domain and vm domain should not get here. */
ab8dfe25 591 BUG_ON(domain_type_is_vm_or_si(domain));
1b198bb0 592 iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus);
8c11e798
WH		 593 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
594 return NULL;
595
596 return g_iommus[iommu_id];
597}
598
8e604097
WH		 599static void domain_update_iommu_coherency(struct dmar_domain *domain)
600{
d0501960
DW		 601 struct dmar_drhd_unit *drhd;
602 struct intel_iommu *iommu;
603 int i, found = 0;
2e12bc29 604
d0501960 605 domain->iommu_coherency = 1;
8e604097 606
1b198bb0 607 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
d0501960 608 found = 1;
8e604097
WH		 609 if (!ecap_coherent(g_iommus[i]->ecap)) {
610 domain->iommu_coherency = 0;
611 break;
612 }
8e604097 613 }
d0501960
DW		 614 if (found)
615 return;
616
617 /* No hardware attached; use lowest common denominator */
618 rcu_read_lock();
619 for_each_active_iommu(iommu, drhd) {
620 if (!ecap_coherent(iommu->ecap)) {
621 domain->iommu_coherency = 0;
622 break;
623 }
624 }
625 rcu_read_unlock();
8e604097
WH		 626}
627
58c610bd
SY		 628static void domain_update_iommu_snooping(struct dmar_domain *domain)
629{
630 int i;
631
632 domain->iommu_snooping = 1;
633
1b198bb0 634 for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) {
58c610bd
SY		 635 if (!ecap_sc_support(g_iommus[i]->ecap)) {
636 domain->iommu_snooping = 0;
637 break;
638 }
58c610bd
SY		 639 }
640}
641
6dd9a7c7
YS		 642static void domain_update_iommu_superpage(struct dmar_domain *domain)
643{
8140a95d
AK		 644 struct dmar_drhd_unit *drhd;
645 struct intel_iommu *iommu = NULL;
646 int mask = 0xf;
6dd9a7c7
YS		 647
648 if (!intel_iommu_superpage) {
649 domain->iommu_superpage = 0;
650 return;
651 }
652
8140a95d 653 /* set iommu_superpage to the smallest common denominator */
0e242612 654 rcu_read_lock();
8140a95d
AK		 655 for_each_active_iommu(iommu, drhd) {
656 mask &= cap_super_page_val(iommu->cap);
6dd9a7c7
YS		 657 if (!mask) {
658 break;
659 }
660 }
0e242612
JL		 661 rcu_read_unlock();
662
6dd9a7c7
YS		 663 domain->iommu_superpage = fls(mask);
664}
665
58c610bd
SY		 666/* Some capabilities may be different across iommus */
667static void domain_update_iommu_cap(struct dmar_domain *domain)
668{
669 domain_update_iommu_coherency(domain);
670 domain_update_iommu_snooping(domain);
6dd9a7c7 671 domain_update_iommu_superpage(domain);
58c610bd
SY		 672}
673
156baca8 674static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn)
c7151a8d
WH		 675{
676 struct dmar_drhd_unit *drhd = NULL;
b683b230 677 struct intel_iommu *iommu;
156baca8
DW		 678 struct device *tmp;
679 struct pci_dev *ptmp, *pdev = NULL;
aa4d066a 680 u16 segment = 0;
c7151a8d
WH		 681 int i;
682
156baca8
DW		 683 if (dev_is_pci(dev)) {
684 pdev = to_pci_dev(dev);
685 segment = pci_domain_nr(pdev->bus);
686 } else if (ACPI_COMPANION(dev))
687 dev = &ACPI_COMPANION(dev)->dev;
688
0e242612 689 rcu_read_lock();
b683b230 690 for_each_active_iommu(iommu, drhd) {
156baca8 691 if (pdev && segment != drhd->segment)
276dbf99 692 continue;
c7151a8d 693
b683b230 694 for_each_active_dev_scope(drhd->devices,
156baca8
DW		 695 drhd->devices_cnt, i, tmp) {
696 if (tmp == dev) {
697 *bus = drhd->devices[i].bus;
698 *devfn = drhd->devices[i].devfn;
b683b230 699 goto out;
156baca8
DW		 700 }
701
702 if (!pdev || !dev_is_pci(tmp))
703 continue;
704
705 ptmp = to_pci_dev(tmp);
706 if (ptmp->subordinate &&
707 ptmp->subordinate->number <= pdev->bus->number &&
708 ptmp->subordinate->busn_res.end >= pdev->bus->number)
709 goto got_pdev;
924b6231 710 }
c7151a8d 711
156baca8
DW		 712 if (pdev && drhd->include_all) {
713 got_pdev:
714 *bus = pdev->bus->number;
715 *devfn = pdev->devfn;
b683b230 716 goto out;
156baca8 717 }
c7151a8d 718 }
b683b230 719 iommu = NULL;
156baca8 720 out:
0e242612 721 rcu_read_unlock();
c7151a8d 722
b683b230 723 return iommu;
c7151a8d
WH		 724}
725
5331fe6f
WH		 726static void domain_flush_cache(struct dmar_domain *domain,
727 void *addr, int size)
728{
729 if (!domain->iommu_coherency)
730 clflush_cache_range(addr, size);
731}
732
ba395927
KA		 733/* Gets context entry for a given bus and devfn */
734static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
735 u8 bus, u8 devfn)
736{
737 struct root_entry *root;
738 struct context_entry *context;
739 unsigned long phy_addr;
740 unsigned long flags;
741
742 spin_lock_irqsave(&iommu->lock, flags);
743 root = &iommu->root_entry[bus];
744 context = get_context_addr_from_root(root);
745 if (!context) {
4c923d47
SS		 746 context = (struct context_entry *)
747 alloc_pgtable_page(iommu->node);
ba395927
KA		 748 if (!context) {
749 spin_unlock_irqrestore(&iommu->lock, flags);
750 return NULL;
751 }
5b6985ce 752 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
ba395927
KA		 753 phy_addr = virt_to_phys((void *)context);
754 set_root_value(root, phy_addr);
755 set_root_present(root);
756 __iommu_flush_cache(iommu, root, sizeof(*root));
757 }
758 spin_unlock_irqrestore(&iommu->lock, flags);
759 return &context[devfn];
760}
761
762static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
763{
764 struct root_entry *root;
765 struct context_entry *context;
766 int ret;
767 unsigned long flags;
768
769 spin_lock_irqsave(&iommu->lock, flags);
770 root = &iommu->root_entry[bus];
771 context = get_context_addr_from_root(root);
772 if (!context) {
773 ret = 0;
774 goto out;
775 }
c07e7d21 776 ret = context_present(&context[devfn]);
ba395927
KA		 777out:
778 spin_unlock_irqrestore(&iommu->lock, flags);
779 return ret;
780}
781
782static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
783{
784 struct root_entry *root;
785 struct context_entry *context;
786 unsigned long flags;
787
788 spin_lock_irqsave(&iommu->lock, flags);
789 root = &iommu->root_entry[bus];
790 context = get_context_addr_from_root(root);
791 if (context) {
c07e7d21 792 context_clear_entry(&context[devfn]);
ba395927
KA		 793 __iommu_flush_cache(iommu, &context[devfn], \
794 sizeof(*context));
795 }
796 spin_unlock_irqrestore(&iommu->lock, flags);
797}
798
799static void free_context_table(struct intel_iommu *iommu)
800{
801 struct root_entry *root;
802 int i;
803 unsigned long flags;
804 struct context_entry *context;
805
806 spin_lock_irqsave(&iommu->lock, flags);
807 if (!iommu->root_entry) {
808 goto out;
809 }
810 for (i = 0; i < ROOT_ENTRY_NR; i++) {
811 root = &iommu->root_entry[i];
812 context = get_context_addr_from_root(root);
813 if (context)
814 free_pgtable_page(context);
815 }
816 free_pgtable_page(iommu->root_entry);
817 iommu->root_entry = NULL;
818out:
819 spin_unlock_irqrestore(&iommu->lock, flags);
820}
821
b026fd28 822static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
5cf0a76f 823 unsigned long pfn, int *target_level)
ba395927 824{
b026fd28 825 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927
KA		 826 struct dma_pte *parent, *pte = NULL;
827 int level = agaw_to_level(domain->agaw);
4399c8bf 828 int offset;
ba395927
KA		 829
830 BUG_ON(!domain->pgd);
f9423606
JS		 831
832 if (addr_width < BITS_PER_LONG && pfn >> addr_width)
833 /* Address beyond IOMMU's addressing capabilities. */
834 return NULL;
835
ba395927
KA		 836 parent = domain->pgd;
837
5cf0a76f 838 while (1) {
ba395927
KA		 839 void *tmp_page;
840
b026fd28 841 offset = pfn_level_offset(pfn, level);
ba395927 842 pte = &parent[offset];
5cf0a76f 843 if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte)))
6dd9a7c7 844 break;
5cf0a76f 845 if (level == *target_level)
ba395927
KA		 846 break;
847
19c239ce 848 if (!dma_pte_present(pte)) {
c85994e4
DW		 849 uint64_t pteval;
850
4c923d47 851 tmp_page = alloc_pgtable_page(domain->nid);
ba395927 852
206a73c1 853 if (!tmp_page)
ba395927 854 return NULL;
206a73c1 855
c85994e4 856 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
64de5af0 857 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
effad4b5 858 if (cmpxchg64(&pte->val, 0ULL, pteval))
c85994e4
DW		 859 /* Someone else set it while we were thinking; use theirs. */
860 free_pgtable_page(tmp_page);
effad4b5 861 else
c85994e4 862 domain_flush_cache(domain, pte, sizeof(*pte));
ba395927 863 }
5cf0a76f
DW		 864 if (level == 1)
865 break;
866
19c239ce 867 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 868 level--;
869 }
870
5cf0a76f
DW		 871 if (!*target_level)
872 *target_level = level;
873
ba395927
KA		 874 return pte;
875}
876
6dd9a7c7 877
ba395927 878/* return address's pte at specific level */
90dcfb5e
DW		 879static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
880 unsigned long pfn,
6dd9a7c7 881 int level, int *large_page)
ba395927
KA		 882{
883 struct dma_pte *parent, *pte = NULL;
884 int total = agaw_to_level(domain->agaw);
885 int offset;
886
887 parent = domain->pgd;
888 while (level <= total) {
90dcfb5e 889 offset = pfn_level_offset(pfn, total);
ba395927
KA		 890 pte = &parent[offset];
891 if (level == total)
892 return pte;
893
6dd9a7c7
YS		 894 if (!dma_pte_present(pte)) {
895 *large_page = total;
ba395927 896 break;
6dd9a7c7
YS		 897 }
898
e16922af 899 if (dma_pte_superpage(pte)) {
6dd9a7c7
YS		 900 *large_page = total;
901 return pte;
902 }
903
19c239ce 904 parent = phys_to_virt(dma_pte_addr(pte));
ba395927
KA		 905 total--;
906 }
907 return NULL;
908}
909
ba395927 910/* clear last level pte, a tlb flush should be followed */
5cf0a76f 911static void dma_pte_clear_range(struct dmar_domain *domain,
595badf5
DW		 912 unsigned long start_pfn,
913 unsigned long last_pfn)
ba395927 914{
04b18e65 915 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
6dd9a7c7 916 unsigned int large_page = 1;
310a5ab9 917 struct dma_pte *first_pte, *pte;
66eae846 918
04b18e65 919 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
595badf5 920 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 921 BUG_ON(start_pfn > last_pfn);
ba395927 922
04b18e65 923 /* we don't need lock here; nobody else touches the iova range */
59c36286 924 do {
6dd9a7c7
YS		 925 large_page = 1;
926 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page);
310a5ab9 927 if (!pte) {
6dd9a7c7 928 start_pfn = align_to_level(start_pfn + 1, large_page + 1);
310a5ab9
DW		 929 continue;
930 }
6dd9a7c7 931 do {
310a5ab9 932 dma_clear_pte(pte);
6dd9a7c7 933 start_pfn += lvl_to_nr_pages(large_page);
310a5ab9 934 pte++;
75e6bf96
DW		 935 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
936
310a5ab9
DW		 937 domain_flush_cache(domain, first_pte,
938 (void *)pte - (void *)first_pte);
59c36286
DW		 939
940 } while (start_pfn && start_pfn <= last_pfn);
ba395927
KA		 941}
942
3269ee0b
AW		 943static void dma_pte_free_level(struct dmar_domain *domain, int level,
944 struct dma_pte *pte, unsigned long pfn,
945 unsigned long start_pfn, unsigned long last_pfn)
946{
947 pfn = max(start_pfn, pfn);
948 pte = &pte[pfn_level_offset(pfn, level)];
949
950 do {
951 unsigned long level_pfn;
952 struct dma_pte *level_pte;
953
954 if (!dma_pte_present(pte) || dma_pte_superpage(pte))
955 goto next;
956
957 level_pfn = pfn & level_mask(level - 1);
958 level_pte = phys_to_virt(dma_pte_addr(pte));
959
960 if (level > 2)
961 dma_pte_free_level(domain, level - 1, level_pte,
962 level_pfn, start_pfn, last_pfn);
963
964 /* If range covers entire pagetable, free it */
965 if (!(start_pfn > level_pfn ||
08336fd2 966 last_pfn < level_pfn + level_size(level) - 1)) {
3269ee0b
AW		 967 dma_clear_pte(pte);
968 domain_flush_cache(domain, pte, sizeof(*pte));
969 free_pgtable_page(level_pte);
970 }
971next:
972 pfn += level_size(level);
973 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
974}
975
ba395927
KA		 976/* free page table pages. last level pte should already be cleared */
977static void dma_pte_free_pagetable(struct dmar_domain *domain,
d794dc9b
DW		 978 unsigned long start_pfn,
979 unsigned long last_pfn)
ba395927 980{
6660c63a 981 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
ba395927 982
6660c63a
DW		 983 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
984 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
59c36286 985 BUG_ON(start_pfn > last_pfn);
ba395927 986
d41a4adb
JL		 987 dma_pte_clear_range(domain, start_pfn, last_pfn);
988
f3a0a52f 989 /* We don't need lock here; nobody else touches the iova range */
3269ee0b
AW		 990 dma_pte_free_level(domain, agaw_to_level(domain->agaw),
991 domain->pgd, 0, start_pfn, last_pfn);
6660c63a 992
ba395927 993 /* free pgd */
d794dc9b 994 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
ba395927
KA		 995 free_pgtable_page(domain->pgd);
996 domain->pgd = NULL;
997 }
998}
999
ea8ea460
DW		 1000/* When a page at a given level is being unlinked from its parent, we don't
1001 need to *modify* it at all. All we need to do is make a list of all the
1002 pages which can be freed just as soon as we've flushed the IOTLB and we
1003 know the hardware page-walk will no longer touch them.
1004 The 'pte' argument is the *parent* PTE, pointing to the page that is to
1005 be freed. */
1006static struct page *dma_pte_list_pagetables(struct dmar_domain *domain,
1007 int level, struct dma_pte *pte,
1008 struct page *freelist)
1009{
1010 struct page *pg;
1011
1012 pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT);
1013 pg->freelist = freelist;
1014 freelist = pg;
1015
1016 if (level == 1)
1017 return freelist;
1018
adeb2590
JL		 1019 pte = page_address(pg);
1020 do {
ea8ea460
DW		 1021 if (dma_pte_present(pte) && !dma_pte_superpage(pte))
1022 freelist = dma_pte_list_pagetables(domain, level - 1,
1023 pte, freelist);
adeb2590
JL		 1024 pte++;
1025 } while (!first_pte_in_page(pte));
ea8ea460
DW		 1026
1027 return freelist;
1028}
1029
1030static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level,
1031 struct dma_pte *pte, unsigned long pfn,
1032 unsigned long start_pfn,
1033 unsigned long last_pfn,
1034 struct page *freelist)
1035{
1036 struct dma_pte *first_pte = NULL, *last_pte = NULL;
1037
1038 pfn = max(start_pfn, pfn);
1039 pte = &pte[pfn_level_offset(pfn, level)];
1040
1041 do {
1042 unsigned long level_pfn;
1043
1044 if (!dma_pte_present(pte))
1045 goto next;
1046
1047 level_pfn = pfn & level_mask(level);
1048
1049 /* If range covers entire pagetable, free it */
1050 if (start_pfn <= level_pfn &&
1051 last_pfn >= level_pfn + level_size(level) - 1) {
1052 /* These suborbinate page tables are going away entirely. Don't
1053 bother to clear them; we're just going to *free* them. */
1054 if (level > 1 && !dma_pte_superpage(pte))
1055 freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist);
1056
1057 dma_clear_pte(pte);
1058 if (!first_pte)
1059 first_pte = pte;
1060 last_pte = pte;
1061 } else if (level > 1) {
1062 /* Recurse down into a level that isn't *entirely* obsolete */
1063 freelist = dma_pte_clear_level(domain, level - 1,
1064 phys_to_virt(dma_pte_addr(pte)),
1065 level_pfn, start_pfn, last_pfn,
1066 freelist);
1067 }
1068next:
1069 pfn += level_size(level);
1070 } while (!first_pte_in_page(++pte) && pfn <= last_pfn);
1071
1072 if (first_pte)
1073 domain_flush_cache(domain, first_pte,
1074 (void *)++last_pte - (void *)first_pte);
1075
1076 return freelist;
1077}
1078
1079/* We can't just free the pages because the IOMMU may still be walking
1080 the page tables, and may have cached the intermediate levels. The
1081 pages can only be freed after the IOTLB flush has been done. */
1082struct page *domain_unmap(struct dmar_domain *domain,
1083 unsigned long start_pfn,
1084 unsigned long last_pfn)
1085{
1086 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1087 struct page *freelist = NULL;
1088
1089 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
1090 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
1091 BUG_ON(start_pfn > last_pfn);
1092
1093 /* we don't need lock here; nobody else touches the iova range */
1094 freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw),
1095 domain->pgd, 0, start_pfn, last_pfn, NULL);
1096
1097 /* free pgd */
1098 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
1099 struct page *pgd_page = virt_to_page(domain->pgd);
1100 pgd_page->freelist = freelist;
1101 freelist = pgd_page;
1102
1103 domain->pgd = NULL;
1104 }
1105
1106 return freelist;
1107}
1108
1109void dma_free_pagelist(struct page *freelist)
1110{
1111 struct page *pg;
1112
1113 while ((pg = freelist)) {
1114 freelist = pg->freelist;
1115 free_pgtable_page(page_address(pg));
1116 }
1117}
1118
ba395927
KA		 1119/* iommu handling */
1120static int iommu_alloc_root_entry(struct intel_iommu *iommu)
1121{
1122 struct root_entry *root;
1123 unsigned long flags;
1124
4c923d47 1125 root = (struct root_entry *)alloc_pgtable_page(iommu->node);
ba395927
KA		 1126 if (!root)
1127 return -ENOMEM;
1128
5b6985ce 1129 __iommu_flush_cache(iommu, root, ROOT_SIZE);
ba395927
KA		 1130
1131 spin_lock_irqsave(&iommu->lock, flags);
1132 iommu->root_entry = root;
1133 spin_unlock_irqrestore(&iommu->lock, flags);
1134
1135 return 0;
1136}
1137
ba395927
KA		 1138static void iommu_set_root_entry(struct intel_iommu *iommu)
1139{
1140 void *addr;
c416daa9 1141 u32 sts;
ba395927
KA		 1142 unsigned long flag;
1143
1144 addr = iommu->root_entry;
1145
1f5b3c3f 1146 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1147 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
1148
c416daa9 1149 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1150
1151 /* Make sure hardware complete it */
1152 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1153 readl, (sts & DMA_GSTS_RTPS), sts);
ba395927 1154
1f5b3c3f 1155 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1156}
1157
1158static void iommu_flush_write_buffer(struct intel_iommu *iommu)
1159{
1160 u32 val;
1161 unsigned long flag;
1162
9af88143 1163 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
ba395927 1164 return;
ba395927 1165
1f5b3c3f 1166 raw_spin_lock_irqsave(&iommu->register_lock, flag);
462b60f6 1167 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1168
1169 /* Make sure hardware complete it */
1170 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1171 readl, (!(val & DMA_GSTS_WBFS)), val);
ba395927 1172
1f5b3c3f 1173 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1174}
1175
1176/* return value determine if we need a write buffer flush */
4c25a2c1
DW		 1177static void __iommu_flush_context(struct intel_iommu *iommu,
1178 u16 did, u16 source_id, u8 function_mask,
1179 u64 type)
ba395927
KA		 1180{
1181 u64 val = 0;
1182 unsigned long flag;
1183
ba395927
KA		 1184 switch (type) {
1185 case DMA_CCMD_GLOBAL_INVL:
1186 val = DMA_CCMD_GLOBAL_INVL;
1187 break;
1188 case DMA_CCMD_DOMAIN_INVL:
1189 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
1190 break;
1191 case DMA_CCMD_DEVICE_INVL:
1192 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
1193 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
1194 break;
1195 default:
1196 BUG();
1197 }
1198 val |= DMA_CCMD_ICC;
1199
1f5b3c3f 1200 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1201 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
1202
1203 /* Make sure hardware complete it */
1204 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
1205 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
1206
1f5b3c3f 1207 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1208}
1209
ba395927 1210/* return value determine if we need a write buffer flush */
1f0ef2aa
DW		 1211static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
1212 u64 addr, unsigned int size_order, u64 type)
ba395927
KA		 1213{
1214 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
1215 u64 val = 0, val_iva = 0;
1216 unsigned long flag;
1217
ba395927
KA		 1218 switch (type) {
1219 case DMA_TLB_GLOBAL_FLUSH:
1220 /* global flush doesn't need set IVA_REG */
1221 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
1222 break;
1223 case DMA_TLB_DSI_FLUSH:
1224 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
1225 break;
1226 case DMA_TLB_PSI_FLUSH:
1227 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
ea8ea460 1228 /* IH bit is passed in as part of address */
ba395927
KA		 1229 val_iva = size_order | addr;
1230 break;
1231 default:
1232 BUG();
1233 }
1234 /* Note: set drain read/write */
1235#if 0
1236 /*
1237 * This is probably to be super secure.. Looks like we can
1238 * ignore it without any impact.
1239 */
1240 if (cap_read_drain(iommu->cap))
1241 val |= DMA_TLB_READ_DRAIN;
1242#endif
1243 if (cap_write_drain(iommu->cap))
1244 val |= DMA_TLB_WRITE_DRAIN;
1245
1f5b3c3f 1246 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1247 /* Note: Only uses first TLB reg currently */
1248 if (val_iva)
1249 dmar_writeq(iommu->reg + tlb_offset, val_iva);
1250 dmar_writeq(iommu->reg + tlb_offset + 8, val);
1251
1252 /* Make sure hardware complete it */
1253 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
1254 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1255
1f5b3c3f 1256 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1257
1258 /* check IOTLB invalidation granularity */
1259 if (DMA_TLB_IAIG(val) == 0)
1260 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1261 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1262 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
5b6985ce
FY		 1263 (unsigned long long)DMA_TLB_IIRG(type),
1264 (unsigned long long)DMA_TLB_IAIG(val));
ba395927
KA		 1265}
1266
64ae892b
DW		 1267static struct device_domain_info *
1268iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu,
1269 u8 bus, u8 devfn)
93a23a72
YZ		 1270{
1271 int found = 0;
1272 unsigned long flags;
1273 struct device_domain_info *info;
0bcb3e28 1274 struct pci_dev *pdev;
93a23a72
YZ		 1275
1276 if (!ecap_dev_iotlb_support(iommu->ecap))
1277 return NULL;
1278
1279 if (!iommu->qi)
1280 return NULL;
1281
1282 spin_lock_irqsave(&device_domain_lock, flags);
1283 list_for_each_entry(info, &domain->devices, link)
c3b497c6
JL		 1284 if (info->iommu == iommu && info->bus == bus &&
1285 info->devfn == devfn) {
93a23a72
YZ		 1286 found = 1;
1287 break;
1288 }
1289 spin_unlock_irqrestore(&device_domain_lock, flags);
1290
0bcb3e28 1291 if (!found || !info->dev || !dev_is_pci(info->dev))
93a23a72
YZ		 1292 return NULL;
1293
0bcb3e28
DW		 1294 pdev = to_pci_dev(info->dev);
1295
1296 if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS))
93a23a72
YZ		 1297 return NULL;
1298
0bcb3e28 1299 if (!dmar_find_matched_atsr_unit(pdev))
93a23a72
YZ		 1300 return NULL;
1301
93a23a72
YZ		 1302 return info;
1303}
1304
1305static void iommu_enable_dev_iotlb(struct device_domain_info *info)
ba395927 1306{
0bcb3e28 1307 if (!info || !dev_is_pci(info->dev))
93a23a72
YZ		 1308 return;
1309
0bcb3e28 1310 pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT);
93a23a72
YZ		 1311}
1312
1313static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1314{
0bcb3e28
DW		 1315 if (!info->dev || !dev_is_pci(info->dev) ||
1316 !pci_ats_enabled(to_pci_dev(info->dev)))
93a23a72
YZ		 1317 return;
1318
0bcb3e28 1319 pci_disable_ats(to_pci_dev(info->dev));
93a23a72
YZ		 1320}
1321
1322static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1323 u64 addr, unsigned mask)
1324{
1325 u16 sid, qdep;
1326 unsigned long flags;
1327 struct device_domain_info *info;
1328
1329 spin_lock_irqsave(&device_domain_lock, flags);
1330 list_for_each_entry(info, &domain->devices, link) {
0bcb3e28
DW		 1331 struct pci_dev *pdev;
1332 if (!info->dev || !dev_is_pci(info->dev))
1333 continue;
1334
1335 pdev = to_pci_dev(info->dev);
1336 if (!pci_ats_enabled(pdev))
93a23a72
YZ		 1337 continue;
1338
1339 sid = info->bus << 8 | info->devfn;
0bcb3e28 1340 qdep = pci_ats_queue_depth(pdev);
93a23a72
YZ		 1341 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1342 }
1343 spin_unlock_irqrestore(&device_domain_lock, flags);
1344}
1345
1f0ef2aa 1346static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
ea8ea460 1347 unsigned long pfn, unsigned int pages, int ih, int map)
ba395927 1348{
9dd2fe89 1349 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
03d6a246 1350 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
ba395927 1351
ba395927
KA		 1352 BUG_ON(pages == 0);
1353
ea8ea460
DW		 1354 if (ih)
1355 ih = 1 << 6;
ba395927 1356 /*
9dd2fe89
YZ		 1357 * Fallback to domain selective flush if no PSI support or the size is
1358 * too big.
ba395927
KA		 1359 * PSI requires page size to be 2 ^ x, and the base address is naturally
1360 * aligned to the size
1361 */
9dd2fe89
YZ		 1362 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1363 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1f0ef2aa 1364 DMA_TLB_DSI_FLUSH);
9dd2fe89 1365 else
ea8ea460 1366 iommu->flush.flush_iotlb(iommu, did, addr | ih, mask,
9dd2fe89 1367 DMA_TLB_PSI_FLUSH);
bf92df30
YZ		 1368
1369 /*
82653633
NA		 1370 * In caching mode, changes of pages from non-present to present require
1371 * flush. However, device IOTLB doesn't need to be flushed in this case.
bf92df30 1372 */
82653633 1373 if (!cap_caching_mode(iommu->cap) || !map)
93a23a72 1374 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
ba395927
KA		 1375}
1376
f8bab735 1377static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1378{
1379 u32 pmen;
1380 unsigned long flags;
1381
1f5b3c3f 1382 raw_spin_lock_irqsave(&iommu->register_lock, flags);
f8bab735 1383 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1384 pmen &= ~DMA_PMEN_EPM;
1385 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1386
1387 /* wait for the protected region status bit to clear */
1388 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1389 readl, !(pmen & DMA_PMEN_PRS), pmen);
1390
1f5b3c3f 1391 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
f8bab735 1392}
1393
2a41ccee 1394static void iommu_enable_translation(struct intel_iommu *iommu)
ba395927
KA		 1395{
1396 u32 sts;
1397 unsigned long flags;
1398
1f5b3c3f 1399 raw_spin_lock_irqsave(&iommu->register_lock, flags);
c416daa9
DW		 1400 iommu->gcmd |= DMA_GCMD_TE;
1401 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
ba395927
KA		 1402
1403 /* Make sure hardware complete it */
1404 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1405 readl, (sts & DMA_GSTS_TES), sts);
ba395927 1406
1f5b3c3f 1407 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
ba395927
KA		 1408}
1409
2a41ccee 1410static void iommu_disable_translation(struct intel_iommu *iommu)
ba395927
KA		 1411{
1412 u32 sts;
1413 unsigned long flag;
1414
1f5b3c3f 1415 raw_spin_lock_irqsave(&iommu->register_lock, flag);
ba395927
KA		 1416 iommu->gcmd &= ~DMA_GCMD_TE;
1417 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1418
1419 /* Make sure hardware complete it */
1420 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
c416daa9 1421 readl, (!(sts & DMA_GSTS_TES)), sts);
ba395927 1422
1f5b3c3f 1423 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
ba395927
KA		 1424}
1425
3460a6d9 1426
ba395927
KA		 1427static int iommu_init_domains(struct intel_iommu *iommu)
1428{
1429 unsigned long ndomains;
1430 unsigned long nlongs;
1431
1432 ndomains = cap_ndoms(iommu->cap);
852bdb04
JL		 1433 pr_debug("IOMMU%d: Number of Domains supported <%ld>\n",
1434 iommu->seq_id, ndomains);
ba395927
KA		 1435 nlongs = BITS_TO_LONGS(ndomains);
1436
94a91b50
DD		 1437 spin_lock_init(&iommu->lock);
1438
ba395927
KA		 1439 /* TBD: there might be 64K domains,
1440 * consider other allocation for future chip
1441 */
1442 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1443 if (!iommu->domain_ids) {
852bdb04
JL		 1444 pr_err("IOMMU%d: allocating domain id array failed\n",
1445 iommu->seq_id);
ba395927
KA		 1446 return -ENOMEM;
1447 }
1448 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1449 GFP_KERNEL);
1450 if (!iommu->domains) {
852bdb04
JL		 1451 pr_err("IOMMU%d: allocating domain array failed\n",
1452 iommu->seq_id);
1453 kfree(iommu->domain_ids);
1454 iommu->domain_ids = NULL;
ba395927
KA		 1455 return -ENOMEM;
1456 }
1457
1458 /*
1459 * if Caching mode is set, then invalid translations are tagged
1460 * with domainid 0. Hence we need to pre-allocate it.
1461 */
1462 if (cap_caching_mode(iommu->cap))
1463 set_bit(0, iommu->domain_ids);
1464 return 0;
1465}
ba395927 1466
a868e6b7 1467static void free_dmar_iommu(struct intel_iommu *iommu)
ba395927
KA		 1468{
1469 struct dmar_domain *domain;
2a46ddf7 1470 int i;
ba395927 1471
94a91b50 1472 if ((iommu->domains) && (iommu->domain_ids)) {
a45946ab 1473 for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) {
a4eaa86c
JL		 1474 /*
1475 * Domain id 0 is reserved for invalid translation
1476 * if hardware supports caching mode.
1477 */
1478 if (cap_caching_mode(iommu->cap) && i == 0)
1479 continue;
1480
94a91b50
DD		 1481 domain = iommu->domains[i];
1482 clear_bit(i, iommu->domain_ids);
129ad281
JL		 1483 if (domain_detach_iommu(domain, iommu) == 0 &&
1484 !domain_type_is_vm(domain))
92d03cc8 1485 domain_exit(domain);
5e98c4b1 1486 }
ba395927
KA		 1487 }
1488
1489 if (iommu->gcmd & DMA_GCMD_TE)
1490 iommu_disable_translation(iommu);
1491
ba395927
KA		 1492 kfree(iommu->domains);
1493 kfree(iommu->domain_ids);
a868e6b7
JL		 1494 iommu->domains = NULL;
1495 iommu->domain_ids = NULL;
ba395927 1496
d9630fe9
WH		 1497 g_iommus[iommu->seq_id] = NULL;
1498
ba395927
KA		 1499 /* free context mapping */
1500 free_context_table(iommu);
ba395927
KA		 1501}
1502
ab8dfe25 1503static struct dmar_domain *alloc_domain(int flags)
ba395927 1504{
92d03cc8
JL		 1505 /* domain id for virtual machine, it won't be set in context */
1506 static atomic_t vm_domid = ATOMIC_INIT(0);
ba395927 1507 struct dmar_domain *domain;
ba395927
KA		 1508
1509 domain = alloc_domain_mem();
1510 if (!domain)
1511 return NULL;
1512
ab8dfe25 1513 memset(domain, 0, sizeof(*domain));
4c923d47 1514 domain->nid = -1;
ab8dfe25 1515 domain->flags = flags;
92d03cc8
JL		 1516 spin_lock_init(&domain->iommu_lock);
1517 INIT_LIST_HEAD(&domain->devices);
ab8dfe25 1518 if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
92d03cc8 1519 domain->id = atomic_inc_return(&vm_domid);
2c2e2c38
FY		 1520
1521 return domain;
1522}
1523
fb170fb4
JL		 1524static int __iommu_attach_domain(struct dmar_domain *domain,
1525 struct intel_iommu *iommu)
2c2e2c38
FY		 1526{
1527 int num;
1528 unsigned long ndomains;
2c2e2c38 1529
ba395927 1530 ndomains = cap_ndoms(iommu->cap);
ba395927 1531 num = find_first_zero_bit(iommu->domain_ids, ndomains);
fb170fb4
JL		 1532 if (num < ndomains) {
1533 set_bit(num, iommu->domain_ids);
1534 iommu->domains[num] = domain;
1535 } else {
1536 num = -ENOSPC;
ba395927
KA		 1537 }
1538
fb170fb4
JL		 1539 return num;
1540}
1541
1542static int iommu_attach_domain(struct dmar_domain *domain,
1543 struct intel_iommu *iommu)
1544{
1545 int num;
1546 unsigned long flags;
1547
1548 spin_lock_irqsave(&iommu->lock, flags);
1549 num = __iommu_attach_domain(domain, iommu);
44bde614 1550 spin_unlock_irqrestore(&iommu->lock, flags);
fb170fb4
JL		 1551 if (num < 0)
1552 pr_err("IOMMU: no free domain ids\n");
ba395927 1553
fb170fb4 1554 return num;
ba395927
KA		 1555}
1556
44bde614
JL		 1557static int iommu_attach_vm_domain(struct dmar_domain *domain,
1558 struct intel_iommu *iommu)
1559{
1560 int num;
1561 unsigned long ndomains;
1562
1563 ndomains = cap_ndoms(iommu->cap);
1564 for_each_set_bit(num, iommu->domain_ids, ndomains)
1565 if (iommu->domains[num] == domain)
1566 return num;
1567
1568 return __iommu_attach_domain(domain, iommu);
1569}
1570
2c2e2c38
FY		 1571static void iommu_detach_domain(struct dmar_domain *domain,
1572 struct intel_iommu *iommu)
ba395927
KA		 1573{
1574 unsigned long flags;
2c2e2c38 1575 int num, ndomains;
ba395927 1576
8c11e798 1577 spin_lock_irqsave(&iommu->lock, flags);
fb170fb4
JL		 1578 if (domain_type_is_vm_or_si(domain)) {
1579 ndomains = cap_ndoms(iommu->cap);
1580 for_each_set_bit(num, iommu->domain_ids, ndomains) {
1581 if (iommu->domains[num] == domain) {
1582 clear_bit(num, iommu->domain_ids);
1583 iommu->domains[num] = NULL;
1584 break;
1585 }
2c2e2c38 1586 }
fb170fb4
JL		 1587 } else {
1588 clear_bit(domain->id, iommu->domain_ids);
1589 iommu->domains[domain->id] = NULL;
2c2e2c38 1590 }
8c11e798 1591 spin_unlock_irqrestore(&iommu->lock, flags);
ba395927
KA		 1592}
1593
fb170fb4
JL		 1594static void domain_attach_iommu(struct dmar_domain *domain,
1595 struct intel_iommu *iommu)
1596{
1597 unsigned long flags;
1598
1599 spin_lock_irqsave(&domain->iommu_lock, flags);
1600 if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) {
1601 domain->iommu_count++;
1602 if (domain->iommu_count == 1)
1603 domain->nid = iommu->node;
1604 domain_update_iommu_cap(domain);
1605 }
1606 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1607}
1608
1609static int domain_detach_iommu(struct dmar_domain *domain,
1610 struct intel_iommu *iommu)
1611{
1612 unsigned long flags;
1613 int count = INT_MAX;
1614
1615 spin_lock_irqsave(&domain->iommu_lock, flags);
1616 if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) {
1617 count = --domain->iommu_count;
1618 domain_update_iommu_cap(domain);
1619 }
1620 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1621
1622 return count;
1623}
1624
ba395927 1625static struct iova_domain reserved_iova_list;
8a443df4 1626static struct lock_class_key reserved_rbtree_key;
ba395927 1627
51a63e67 1628static int dmar_init_reserved_ranges(void)
ba395927
KA		 1629{
1630 struct pci_dev *pdev = NULL;
1631 struct iova *iova;
1632 int i;
ba395927 1633
f661197e 1634 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
ba395927 1635
8a443df4
MG		 1636 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1637 &reserved_rbtree_key);
1638
ba395927
KA		 1639 /* IOAPIC ranges shouldn't be accessed by DMA */
1640 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1641 IOVA_PFN(IOAPIC_RANGE_END));
51a63e67 1642 if (!iova) {
ba395927 1643 printk(KERN_ERR "Reserve IOAPIC range failed\n");
51a63e67
JC		 1644 return -ENODEV;
1645 }
ba395927
KA		 1646
1647 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1648 for_each_pci_dev(pdev) {
1649 struct resource *r;
1650
1651 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1652 r = &pdev->resource[i];
1653 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1654 continue;
1a4a4551
DW		 1655 iova = reserve_iova(&reserved_iova_list,
1656 IOVA_PFN(r->start),
1657 IOVA_PFN(r->end));
51a63e67 1658 if (!iova) {
ba395927 1659 printk(KERN_ERR "Reserve iova failed\n");
51a63e67
JC		 1660 return -ENODEV;
1661 }
ba395927
KA		 1662 }
1663 }
51a63e67 1664 return 0;
ba395927
KA		 1665}
1666
1667static void domain_reserve_special_ranges(struct dmar_domain *domain)
1668{
1669 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1670}
1671
1672static inline int guestwidth_to_adjustwidth(int gaw)
1673{
1674 int agaw;
1675 int r = (gaw - 12) % 9;
1676
1677 if (r == 0)
1678 agaw = gaw;
1679 else
1680 agaw = gaw + 9 - r;
1681 if (agaw > 64)
1682 agaw = 64;
1683 return agaw;
1684}
1685
1686static int domain_init(struct dmar_domain *domain, int guest_width)
1687{
1688 struct intel_iommu *iommu;
1689 int adjust_width, agaw;
1690 unsigned long sagaw;
1691
f661197e 1692 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
ba395927
KA		 1693 domain_reserve_special_ranges(domain);
1694
1695 /* calculate AGAW */
8c11e798 1696 iommu = domain_get_iommu(domain);
ba395927
KA		 1697 if (guest_width > cap_mgaw(iommu->cap))
1698 guest_width = cap_mgaw(iommu->cap);
1699 domain->gaw = guest_width;
1700 adjust_width = guestwidth_to_adjustwidth(guest_width);
1701 agaw = width_to_agaw(adjust_width);
1702 sagaw = cap_sagaw(iommu->cap);
1703 if (!test_bit(agaw, &sagaw)) {
1704 /* hardware doesn't support it, choose a bigger one */
1705 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1706 agaw = find_next_bit(&sagaw, 5, agaw);
1707 if (agaw >= 5)
1708 return -ENODEV;
1709 }
1710 domain->agaw = agaw;
ba395927 1711
8e604097
WH		 1712 if (ecap_coherent(iommu->ecap))
1713 domain->iommu_coherency = 1;
1714 else
1715 domain->iommu_coherency = 0;
1716
58c610bd
SY		 1717 if (ecap_sc_support(iommu->ecap))
1718 domain->iommu_snooping = 1;
1719 else
1720 domain->iommu_snooping = 0;
1721
214e39aa
DW		 1722 if (intel_iommu_superpage)
1723 domain->iommu_superpage = fls(cap_super_page_val(iommu->cap));
1724 else
1725 domain->iommu_superpage = 0;
1726
4c923d47 1727 domain->nid = iommu->node;
c7151a8d 1728
ba395927 1729 /* always allocate the top pgd */
4c923d47 1730 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
ba395927
KA		 1731 if (!domain->pgd)
1732 return -ENOMEM;
5b6985ce 1733 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
ba395927
KA		 1734 return 0;
1735}
1736
1737static void domain_exit(struct dmar_domain *domain)
1738{
2c2e2c38
FY		 1739 struct dmar_drhd_unit *drhd;
1740 struct intel_iommu *iommu;
ea8ea460 1741 struct page *freelist = NULL;
ba395927
KA		 1742
1743 /* Domain 0 is reserved, so dont process it */
1744 if (!domain)
1745 return;
1746
7b668357
AW		 1747 /* Flush any lazy unmaps that may reference this domain */
1748 if (!intel_iommu_strict)
1749 flush_unmaps_timeout(0);
1750
92d03cc8 1751 /* remove associated devices */
ba395927 1752 domain_remove_dev_info(domain);
92d03cc8 1753
ba395927
KA		 1754 /* destroy iovas */
1755 put_iova_domain(&domain->iovad);
ba395927 1756
ea8ea460 1757 freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
ba395927 1758
92d03cc8 1759 /* clear attached or cached domains */
0e242612 1760 rcu_read_lock();
2c2e2c38 1761 for_each_active_iommu(iommu, drhd)
fb170fb4 1762 iommu_detach_domain(domain, iommu);
0e242612 1763 rcu_read_unlock();
2c2e2c38 1764
ea8ea460
DW		 1765 dma_free_pagelist(freelist);
1766
ba395927
KA		 1767 free_domain_mem(domain);
1768}
1769
64ae892b
DW		 1770static int domain_context_mapping_one(struct dmar_domain *domain,
1771 struct intel_iommu *iommu,
1772 u8 bus, u8 devfn, int translation)
ba395927
KA		 1773{
1774 struct context_entry *context;
ba395927 1775 unsigned long flags;
ea6606b0 1776 struct dma_pte *pgd;
ea6606b0
WH		 1777 int id;
1778 int agaw;
93a23a72 1779 struct device_domain_info *info = NULL;
ba395927
KA		 1780
1781 pr_debug("Set context mapping for %02x:%02x.%d\n",
1782 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
4ed0d3e6 1783
ba395927 1784 BUG_ON(!domain->pgd);
4ed0d3e6
FY		 1785 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1786 translation != CONTEXT_TT_MULTI_LEVEL);
5331fe6f 1787
ba395927
KA		 1788 context = device_to_context_entry(iommu, bus, devfn);
1789 if (!context)
1790 return -ENOMEM;
1791 spin_lock_irqsave(&iommu->lock, flags);
c07e7d21 1792 if (context_present(context)) {
ba395927
KA		 1793 spin_unlock_irqrestore(&iommu->lock, flags);
1794 return 0;
1795 }
1796
ea6606b0
WH		 1797 id = domain->id;
1798 pgd = domain->pgd;
1799
ab8dfe25 1800 if (domain_type_is_vm_or_si(domain)) {
44bde614
JL		 1801 if (domain_type_is_vm(domain)) {
1802 id = iommu_attach_vm_domain(domain, iommu);
fb170fb4 1803 if (id < 0) {
ea6606b0 1804 spin_unlock_irqrestore(&iommu->lock, flags);
fb170fb4 1805 pr_err("IOMMU: no free domain ids\n");
ea6606b0
WH		 1806 return -EFAULT;
1807 }
ea6606b0
WH		 1808 }
1809
1810 /* Skip top levels of page tables for
1811 * iommu which has less agaw than default.
1672af11 1812 * Unnecessary for PT mode.
ea6606b0 1813 */
1672af11
CW		 1814 if (translation != CONTEXT_TT_PASS_THROUGH) {
1815 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1816 pgd = phys_to_virt(dma_pte_addr(pgd));
1817 if (!dma_pte_present(pgd)) {
1818 spin_unlock_irqrestore(&iommu->lock, flags);
1819 return -ENOMEM;
1820 }
ea6606b0
WH		 1821 }
1822 }
1823 }
1824
1825 context_set_domain_id(context, id);
4ed0d3e6 1826
93a23a72 1827 if (translation != CONTEXT_TT_PASS_THROUGH) {
64ae892b 1828 info = iommu_support_dev_iotlb(domain, iommu, bus, devfn);
93a23a72
YZ		 1829 translation = info ? CONTEXT_TT_DEV_IOTLB :
1830 CONTEXT_TT_MULTI_LEVEL;
1831 }
4ed0d3e6
FY		 1832 /*
1833 * In pass through mode, AW must be programmed to indicate the largest
1834 * AGAW value supported by hardware. And ASR is ignored by hardware.
1835 */
93a23a72 1836 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
4ed0d3e6 1837 context_set_address_width(context, iommu->msagaw);
93a23a72
YZ		 1838 else {
1839 context_set_address_root(context, virt_to_phys(pgd));
1840 context_set_address_width(context, iommu->agaw);
1841 }
4ed0d3e6
FY		 1842
1843 context_set_translation_type(context, translation);
c07e7d21
MM		 1844 context_set_fault_enable(context);
1845 context_set_present(context);
5331fe6f 1846 domain_flush_cache(domain, context, sizeof(*context));
ba395927 1847
4c25a2c1
DW		 1848 /*
1849 * It's a non-present to present mapping. If hardware doesn't cache
1850 * non-present entry we only need to flush the write-buffer. If the
1851 * _does_ cache non-present entries, then it does so in the special
1852 * domain #0, which we have to flush:
1853 */
1854 if (cap_caching_mode(iommu->cap)) {
1855 iommu->flush.flush_context(iommu, 0,
1856 (((u16)bus) << 8) | devfn,
1857 DMA_CCMD_MASK_NOBIT,
1858 DMA_CCMD_DEVICE_INVL);
18fd779a 1859 iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH);
4c25a2c1 1860 } else {
ba395927 1861 iommu_flush_write_buffer(iommu);
4c25a2c1 1862 }
93a23a72 1863 iommu_enable_dev_iotlb(info);
ba395927 1864 spin_unlock_irqrestore(&iommu->lock, flags);
c7151a8d 1865
fb170fb4
JL		 1866 domain_attach_iommu(domain, iommu);
1867
ba395927
KA		 1868 return 0;
1869}
1870
579305f7
AW		 1871struct domain_context_mapping_data {
1872 struct dmar_domain *domain;
1873 struct intel_iommu *iommu;
1874 int translation;
1875};
1876
1877static int domain_context_mapping_cb(struct pci_dev *pdev,
1878 u16 alias, void *opaque)
1879{
1880 struct domain_context_mapping_data *data = opaque;
1881
1882 return domain_context_mapping_one(data->domain, data->iommu,
1883 PCI_BUS_NUM(alias), alias & 0xff,
1884 data->translation);
1885}
1886
ba395927 1887static int
e1f167f3
DW		 1888domain_context_mapping(struct dmar_domain *domain, struct device *dev,
1889 int translation)
ba395927 1890{
64ae892b 1891 struct intel_iommu *iommu;
156baca8 1892 u8 bus, devfn;
579305f7 1893 struct domain_context_mapping_data data;
64ae892b 1894
e1f167f3 1895 iommu = device_to_iommu(dev, &bus, &devfn);
64ae892b
DW		 1896 if (!iommu)
1897 return -ENODEV;
ba395927 1898
579305f7
AW		 1899 if (!dev_is_pci(dev))
1900 return domain_context_mapping_one(domain, iommu, bus, devfn,
4ed0d3e6 1901 translation);
579305f7
AW		 1902
1903 data.domain = domain;
1904 data.iommu = iommu;
1905 data.translation = translation;
1906
1907 return pci_for_each_dma_alias(to_pci_dev(dev),
1908 &domain_context_mapping_cb, &data);
1909}
1910
1911static int domain_context_mapped_cb(struct pci_dev *pdev,
1912 u16 alias, void *opaque)
1913{
1914 struct intel_iommu *iommu = opaque;
1915
1916 return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff);
ba395927
KA		 1917}
1918
e1f167f3 1919static int domain_context_mapped(struct device *dev)
ba395927 1920{
5331fe6f 1921 struct intel_iommu *iommu;
156baca8 1922 u8 bus, devfn;
5331fe6f 1923
e1f167f3 1924 iommu = device_to_iommu(dev, &bus, &devfn);
5331fe6f
WH		 1925 if (!iommu)
1926 return -ENODEV;
ba395927 1927
579305f7
AW		 1928 if (!dev_is_pci(dev))
1929 return device_context_mapped(iommu, bus, devfn);
e1f167f3 1930
579305f7
AW		 1931 return !pci_for_each_dma_alias(to_pci_dev(dev),
1932 domain_context_mapped_cb, iommu);
ba395927
KA		 1933}
1934
f532959b
FY		 1935/* Returns a number of VTD pages, but aligned to MM page size */
1936static inline unsigned long aligned_nrpages(unsigned long host_addr,
1937 size_t size)
1938{
1939 host_addr &= ~PAGE_MASK;
1940 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1941}
1942
6dd9a7c7
YS		 1943/* Return largest possible superpage level for a given mapping */
1944static inline int hardware_largepage_caps(struct dmar_domain *domain,
1945 unsigned long iov_pfn,
1946 unsigned long phy_pfn,
1947 unsigned long pages)
1948{
1949 int support, level = 1;
1950 unsigned long pfnmerge;
1951
1952 support = domain->iommu_superpage;
1953
1954 /* To use a large page, the virtual *and* physical addresses
1955 must be aligned to 2MiB/1GiB/etc. Lower bits set in either
1956 of them will mean we have to use smaller pages. So just
1957 merge them and check both at once. */
1958 pfnmerge = iov_pfn | phy_pfn;
1959
1960 while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) {
1961 pages >>= VTD_STRIDE_SHIFT;
1962 if (!pages)
1963 break;
1964 pfnmerge >>= VTD_STRIDE_SHIFT;
1965 level++;
1966 support--;
1967 }
1968 return level;
1969}
1970
9051aa02
DW		 1971static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1972 struct scatterlist *sg, unsigned long phys_pfn,
1973 unsigned long nr_pages, int prot)
e1605495
DW		 1974{
1975 struct dma_pte *first_pte = NULL, *pte = NULL;
9051aa02 1976 phys_addr_t uninitialized_var(pteval);
e1605495 1977 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
9051aa02 1978 unsigned long sg_res;
6dd9a7c7
YS		 1979 unsigned int largepage_lvl = 0;
1980 unsigned long lvl_pages = 0;
e1605495
DW		 1981
1982 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1983
1984 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1985 return -EINVAL;
1986
1987 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1988
9051aa02
DW		 1989 if (sg)
1990 sg_res = 0;
1991 else {
1992 sg_res = nr_pages + 1;
1993 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1994 }
1995
6dd9a7c7 1996 while (nr_pages > 0) {
c85994e4
DW		 1997 uint64_t tmp;
1998
e1605495 1999 if (!sg_res) {
f532959b 2000 sg_res = aligned_nrpages(sg->offset, sg->length);
e1605495
DW		 2001 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
2002 sg->dma_length = sg->length;
2003 pteval = page_to_phys(sg_page(sg)) | prot;
6dd9a7c7 2004 phys_pfn = pteval >> VTD_PAGE_SHIFT;
e1605495 2005 }
6dd9a7c7 2006
e1605495 2007 if (!pte) {
6dd9a7c7
YS		 2008 largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res);
2009
5cf0a76f 2010 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl);
e1605495
DW		 2011 if (!pte)
2012 return -ENOMEM;
6dd9a7c7 2013 /* It is large page*/
6491d4d0 2014 if (largepage_lvl > 1) {
6dd9a7c7 2015 pteval |= DMA_PTE_LARGE_PAGE;
d41a4adb
JL		 2016 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2017 /*
2018 * Ensure that old small page tables are
2019 * removed to make room for superpage,
2020 * if they exist.
2021 */
6491d4d0 2022 dma_pte_free_pagetable(domain, iov_pfn,
d41a4adb 2023 iov_pfn + lvl_pages - 1);
6491d4d0 2024 } else {
6dd9a7c7 2025 pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE;
6491d4d0 2026 }
6dd9a7c7 2027
e1605495
DW		 2028 }
2029 /* We don't need lock here, nobody else
2030 * touches the iova range
2031 */
7766a3fb 2032 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
c85994e4 2033 if (tmp) {
1bf20f0d 2034 static int dumps = 5;
c85994e4
DW		 2035 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
2036 iov_pfn, tmp, (unsigned long long)pteval);
1bf20f0d
DW		 2037 if (dumps) {
2038 dumps--;
2039 debug_dma_dump_mappings(NULL);
2040 }
2041 WARN_ON(1);
2042 }
6dd9a7c7
YS		 2043
2044 lvl_pages = lvl_to_nr_pages(largepage_lvl);
2045
2046 BUG_ON(nr_pages < lvl_pages);
2047 BUG_ON(sg_res < lvl_pages);
2048
2049 nr_pages -= lvl_pages;
2050 iov_pfn += lvl_pages;
2051 phys_pfn += lvl_pages;
2052 pteval += lvl_pages * VTD_PAGE_SIZE;
2053 sg_res -= lvl_pages;
2054
2055 /* If the next PTE would be the first in a new page, then we
2056 need to flush the cache on the entries we've just written.
2057 And then we'll need to recalculate 'pte', so clear it and
2058 let it get set again in the if (!pte) block above.
2059
2060 If we're done (!nr_pages) we need to flush the cache too.
2061
2062 Also if we've been setting superpages, we may need to
2063 recalculate 'pte' and switch back to smaller pages for the
2064 end of the mapping, if the trailing size is not enough to
2065 use another superpage (i.e. sg_res < lvl_pages). */
e1605495 2066 pte++;
6dd9a7c7
YS		 2067 if (!nr_pages || first_pte_in_page(pte) ||
2068 (largepage_lvl > 1 && sg_res < lvl_pages)) {
e1605495
DW		 2069 domain_flush_cache(domain, first_pte,
2070 (void *)pte - (void *)first_pte);
2071 pte = NULL;
2072 }
6dd9a7c7
YS		 2073
2074 if (!sg_res && nr_pages)
e1605495
DW		 2075 sg = sg_next(sg);
2076 }
2077 return 0;
2078}
2079
9051aa02
DW		 2080static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2081 struct scatterlist *sg, unsigned long nr_pages,
2082 int prot)
ba395927 2083{
9051aa02
DW		 2084 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
2085}
6f6a00e4 2086
9051aa02
DW		 2087static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
2088 unsigned long phys_pfn, unsigned long nr_pages,
2089 int prot)
2090{
2091 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
ba395927
KA		 2092}
2093
c7151a8d 2094static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
ba395927 2095{
c7151a8d
WH		 2096 if (!iommu)
2097 return;
8c11e798
WH		 2098
2099 clear_context_table(iommu, bus, devfn);
2100 iommu->flush.flush_context(iommu, 0, 0, 0,
4c25a2c1 2101 DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2102 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
ba395927
KA		 2103}
2104
109b9b04
DW		 2105static inline void unlink_domain_info(struct device_domain_info *info)
2106{
2107 assert_spin_locked(&device_domain_lock);
2108 list_del(&info->link);
2109 list_del(&info->global);
2110 if (info->dev)
0bcb3e28 2111 info->dev->archdata.iommu = NULL;
109b9b04
DW		 2112}
2113
ba395927
KA		 2114static void domain_remove_dev_info(struct dmar_domain *domain)
2115{
3a74ca01 2116 struct device_domain_info *info, *tmp;
fb170fb4 2117 unsigned long flags;
ba395927
KA		 2118
2119 spin_lock_irqsave(&device_domain_lock, flags);
3a74ca01 2120 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
109b9b04 2121 unlink_domain_info(info);
ba395927
KA		 2122 spin_unlock_irqrestore(&device_domain_lock, flags);
2123
93a23a72 2124 iommu_disable_dev_iotlb(info);
7c7faa11 2125 iommu_detach_dev(info->iommu, info->bus, info->devfn);
ba395927 2126
ab8dfe25 2127 if (domain_type_is_vm(domain)) {
7c7faa11 2128 iommu_detach_dependent_devices(info->iommu, info->dev);
fb170fb4 2129 domain_detach_iommu(domain, info->iommu);
92d03cc8
JL		 2130 }
2131
2132 free_devinfo_mem(info);
ba395927
KA		 2133 spin_lock_irqsave(&device_domain_lock, flags);
2134 }
2135 spin_unlock_irqrestore(&device_domain_lock, flags);
2136}
2137
2138/*
2139 * find_domain
1525a29a 2140 * Note: we use struct device->archdata.iommu stores the info
ba395927 2141 */
1525a29a 2142static struct dmar_domain *find_domain(struct device *dev)
ba395927
KA		 2143{
2144 struct device_domain_info *info;
2145
2146 /* No lock here, assumes no domain exit in normal case */
1525a29a 2147 info = dev->archdata.iommu;
ba395927
KA		 2148 if (info)
2149 return info->domain;
2150 return NULL;
2151}
2152
5a8f40e8 2153static inline struct device_domain_info *
745f2586
JL		 2154dmar_search_domain_by_dev_info(int segment, int bus, int devfn)
2155{
2156 struct device_domain_info *info;
2157
2158 list_for_each_entry(info, &device_domain_list, global)
41e80dca 2159 if (info->iommu->segment == segment && info->bus == bus &&
745f2586 2160 info->devfn == devfn)
5a8f40e8 2161 return info;
745f2586
JL		 2162
2163 return NULL;
2164}
2165
5a8f40e8 2166static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu,
41e80dca 2167 int bus, int devfn,
b718cd3d
DW		 2168 struct device *dev,
2169 struct dmar_domain *domain)
745f2586 2170{
5a8f40e8 2171 struct dmar_domain *found = NULL;
745f2586
JL		 2172 struct device_domain_info *info;
2173 unsigned long flags;
2174
2175 info = alloc_devinfo_mem();
2176 if (!info)
b718cd3d 2177 return NULL;
745f2586 2178
745f2586
JL		 2179 info->bus = bus;
2180 info->devfn = devfn;
2181 info->dev = dev;
2182 info->domain = domain;
5a8f40e8 2183 info->iommu = iommu;
745f2586
JL		 2184
2185 spin_lock_irqsave(&device_domain_lock, flags);
2186 if (dev)
0bcb3e28 2187 found = find_domain(dev);
5a8f40e8
DW		 2188 else {
2189 struct device_domain_info *info2;
41e80dca 2190 info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn);
5a8f40e8
DW		 2191 if (info2)
2192 found = info2->domain;
2193 }
745f2586
JL		 2194 if (found) {
2195 spin_unlock_irqrestore(&device_domain_lock, flags);
2196 free_devinfo_mem(info);
b718cd3d
DW		 2197 /* Caller must free the original domain */
2198 return found;
745f2586
JL		 2199 }
2200
b718cd3d
DW		 2201 list_add(&info->link, &domain->devices);
2202 list_add(&info->global, &device_domain_list);
2203 if (dev)
2204 dev->archdata.iommu = info;
2205 spin_unlock_irqrestore(&device_domain_lock, flags);
2206
2207 return domain;
745f2586
JL		 2208}
2209
579305f7
AW		 2210static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque)
2211{
2212 *(u16 *)opaque = alias;
2213 return 0;
2214}
2215
ba395927 2216/* domain is initialized */
146922ec 2217static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw)
ba395927 2218{
579305f7
AW		 2219 struct dmar_domain *domain, *tmp;
2220 struct intel_iommu *iommu;
5a8f40e8 2221 struct device_domain_info *info;
579305f7 2222 u16 dma_alias;
ba395927 2223 unsigned long flags;
aa4d066a 2224 u8 bus, devfn;
ba395927 2225
146922ec 2226 domain = find_domain(dev);
ba395927
KA		 2227 if (domain)
2228 return domain;
2229
579305f7
AW		 2230 iommu = device_to_iommu(dev, &bus, &devfn);
2231 if (!iommu)
2232 return NULL;
2233
146922ec
DW		 2234 if (dev_is_pci(dev)) {
2235 struct pci_dev *pdev = to_pci_dev(dev);
276dbf99 2236
579305f7
AW		 2237 pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias);
2238
2239 spin_lock_irqsave(&device_domain_lock, flags);
2240 info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus),
2241 PCI_BUS_NUM(dma_alias),
2242 dma_alias & 0xff);
2243 if (info) {
2244 iommu = info->iommu;
2245 domain = info->domain;
5a8f40e8 2246 }
579305f7 2247 spin_unlock_irqrestore(&device_domain_lock, flags);
ba395927 2248
579305f7
AW		 2249 /* DMA alias already has a domain, uses it */
2250 if (info)
2251 goto found_domain;
2252 }
ba395927 2253
146922ec 2254 /* Allocate and initialize new domain for the device */
ab8dfe25 2255 domain = alloc_domain(0);
745f2586 2256 if (!domain)
579305f7 2257 return NULL;
44bde614
JL		 2258 domain->id = iommu_attach_domain(domain, iommu);
2259 if (domain->id < 0) {
2fe9723d 2260 free_domain_mem(domain);
579305f7 2261 return NULL;
2c2e2c38 2262 }
fb170fb4 2263 domain_attach_iommu(domain, iommu);
579305f7
AW		 2264 if (domain_init(domain, gaw)) {
2265 domain_exit(domain);
2266 return NULL;
2c2e2c38 2267 }
ba395927 2268
579305f7
AW		 2269 /* register PCI DMA alias device */
2270 if (dev_is_pci(dev)) {
2271 tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias),
2272 dma_alias & 0xff, NULL, domain);
2273
2274 if (!tmp || tmp != domain) {
2275 domain_exit(domain);
2276 domain = tmp;
2277 }
2278
b718cd3d 2279 if (!domain)
579305f7 2280 return NULL;
ba395927
KA		 2281 }
2282
2283found_domain:
579305f7
AW		 2284 tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
2285
2286 if (!tmp || tmp != domain) {
2287 domain_exit(domain);
2288 domain = tmp;
2289 }
b718cd3d
DW		 2290
2291 return domain;
ba395927
KA		 2292}
2293
2c2e2c38 2294static int iommu_identity_mapping;
e0fc7e0b
DW		 2295#define IDENTMAP_ALL 1
2296#define IDENTMAP_GFX 2
2297#define IDENTMAP_AZALIA 4
2c2e2c38 2298
b213203e
DW		 2299static int iommu_domain_identity_map(struct dmar_domain *domain,
2300 unsigned long long start,
2301 unsigned long long end)
ba395927 2302{
c5395d5c
DW		 2303 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
2304 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
2305
2306 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
2307 dma_to_mm_pfn(last_vpfn))) {
ba395927 2308 printk(KERN_ERR "IOMMU: reserve iova failed\n");
b213203e 2309 return -ENOMEM;
ba395927
KA		 2310 }
2311
c5395d5c
DW		 2312 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
2313 start, end, domain->id);
ba395927
KA		 2314 /*
2315 * RMRR range might have overlap with physical memory range,
2316 * clear it first
2317 */
c5395d5c 2318 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
ba395927 2319
c5395d5c
DW		 2320 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
2321 last_vpfn - first_vpfn + 1,
61df7443 2322 DMA_PTE_READ|DMA_PTE_WRITE);
b213203e
DW		 2323}
2324
0b9d9753 2325static int iommu_prepare_identity_map(struct device *dev,
b213203e
DW		 2326 unsigned long long start,
2327 unsigned long long end)
2328{
2329 struct dmar_domain *domain;
2330 int ret;
2331
0b9d9753 2332 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
b213203e
DW		 2333 if (!domain)
2334 return -ENOMEM;
2335
19943b0e
DW		 2336 /* For _hardware_ passthrough, don't bother. But for software
2337 passthrough, we do it anyway -- it may indicate a memory
2338 range which is reserved in E820, so which didn't get set
2339 up to start with in si_domain */
2340 if (domain == si_domain && hw_pass_through) {
2341 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2342 dev_name(dev), start, end);
19943b0e
DW		 2343 return 0;
2344 }
2345
2346 printk(KERN_INFO
2347 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
0b9d9753 2348 dev_name(dev), start, end);
2ff729f5 2349
5595b528
DW		 2350 if (end < start) {
2351 WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n"
2352 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2353 dmi_get_system_info(DMI_BIOS_VENDOR),
2354 dmi_get_system_info(DMI_BIOS_VERSION),
2355 dmi_get_system_info(DMI_PRODUCT_VERSION));
2356 ret = -EIO;
2357 goto error;
2358 }
2359
2ff729f5
DW		 2360 if (end >> agaw_to_width(domain->agaw)) {
2361 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
2362 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
2363 agaw_to_width(domain->agaw),
2364 dmi_get_system_info(DMI_BIOS_VENDOR),
2365 dmi_get_system_info(DMI_BIOS_VERSION),
2366 dmi_get_system_info(DMI_PRODUCT_VERSION));
2367 ret = -EIO;
2368 goto error;
2369 }
19943b0e 2370
b213203e 2371 ret = iommu_domain_identity_map(domain, start, end);
ba395927
KA		 2372 if (ret)
2373 goto error;
2374
2375 /* context entry init */
0b9d9753 2376 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
b213203e
DW		 2377 if (ret)
2378 goto error;
2379
2380 return 0;
2381
2382 error:
ba395927
KA		 2383 domain_exit(domain);
2384 return ret;
ba395927
KA		 2385}
2386
2387static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
0b9d9753 2388 struct device *dev)
ba395927 2389{
0b9d9753 2390 if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
ba395927 2391 return 0;
0b9d9753
DW		 2392 return iommu_prepare_identity_map(dev, rmrr->base_address,
2393 rmrr->end_address);
ba395927
KA		 2394}
2395
d3f13810 2396#ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA
49a0429e
KA		 2397static inline void iommu_prepare_isa(void)
2398{
2399 struct pci_dev *pdev;
2400 int ret;
2401
2402 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2403 if (!pdev)
2404 return;
2405
c7ab48d2 2406 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
0b9d9753 2407 ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1);
49a0429e
KA		 2408
2409 if (ret)
c7ab48d2
DW		 2410 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2411 "floppy might not work\n");
49a0429e 2412
9b27e82d 2413 pci_dev_put(pdev);
49a0429e
KA		 2414}
2415#else
2416static inline void iommu_prepare_isa(void)
2417{
2418 return;
2419}
d3f13810 2420#endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */
49a0429e 2421
2c2e2c38 2422static int md_domain_init(struct dmar_domain *domain, int guest_width);
c7ab48d2 2423
071e1374 2424static int __init si_domain_init(int hw)
2c2e2c38
FY		 2425{
2426 struct dmar_drhd_unit *drhd;
2427 struct intel_iommu *iommu;
c7ab48d2 2428 int nid, ret = 0;
44bde614 2429 bool first = true;
2c2e2c38 2430
ab8dfe25 2431 si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY);
2c2e2c38
FY		 2432 if (!si_domain)
2433 return -EFAULT;
2434
2c2e2c38
FY		 2435 for_each_active_iommu(iommu, drhd) {
2436 ret = iommu_attach_domain(si_domain, iommu);
fb170fb4 2437 if (ret < 0) {
2c2e2c38
FY		 2438 domain_exit(si_domain);
2439 return -EFAULT;
44bde614
JL		 2440 } else if (first) {
2441 si_domain->id = ret;
2442 first = false;
2443 } else if (si_domain->id != ret) {
2444 domain_exit(si_domain);
2445 return -EFAULT;
2c2e2c38 2446 }
fb170fb4 2447 domain_attach_iommu(si_domain, iommu);
2c2e2c38
FY		 2448 }
2449
2450 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2451 domain_exit(si_domain);
2452 return -EFAULT;
2453 }
2454
9544c003
JL		 2455 pr_debug("IOMMU: identity mapping domain is domain %d\n",
2456 si_domain->id);
2c2e2c38 2457
19943b0e
DW		 2458 if (hw)
2459 return 0;
2460
c7ab48d2 2461 for_each_online_node(nid) {
5dfe8660
TH		 2462 unsigned long start_pfn, end_pfn;
2463 int i;
2464
2465 for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) {
2466 ret = iommu_domain_identity_map(si_domain,
2467 PFN_PHYS(start_pfn), PFN_PHYS(end_pfn));
2468 if (ret)
2469 return ret;
2470 }
c7ab48d2
DW		 2471 }
2472
2c2e2c38
FY		 2473 return 0;
2474}
2475
9b226624 2476static int identity_mapping(struct device *dev)
2c2e2c38
FY		 2477{
2478 struct device_domain_info *info;
2479
2480 if (likely(!iommu_identity_mapping))
2481 return 0;
2482
9b226624 2483 info = dev->archdata.iommu;
cb452a40
MT		 2484 if (info && info != DUMMY_DEVICE_DOMAIN_INFO)
2485 return (info->domain == si_domain);
2c2e2c38 2486
2c2e2c38
FY		 2487 return 0;
2488}
2489
2490static int domain_add_dev_info(struct dmar_domain *domain,
5913c9bf 2491 struct device *dev, int translation)
2c2e2c38 2492{
0ac72664 2493 struct dmar_domain *ndomain;
5a8f40e8 2494 struct intel_iommu *iommu;
156baca8 2495 u8 bus, devfn;
5fe60f4e 2496 int ret;
2c2e2c38 2497
5913c9bf 2498 iommu = device_to_iommu(dev, &bus, &devfn);
5a8f40e8
DW		 2499 if (!iommu)
2500 return -ENODEV;
2501
5913c9bf 2502 ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain);
0ac72664
DW		 2503 if (ndomain != domain)
2504 return -EBUSY;
2c2e2c38 2505
5913c9bf 2506 ret = domain_context_mapping(domain, dev, translation);
e2ad23d0 2507 if (ret) {
5913c9bf 2508 domain_remove_one_dev_info(domain, dev);
e2ad23d0
DW		 2509 return ret;
2510 }
2511
2c2e2c38
FY		 2512 return 0;
2513}
2514
0b9d9753 2515static bool device_has_rmrr(struct device *dev)
ea2447f7
TM		 2516{
2517 struct dmar_rmrr_unit *rmrr;
832bd858 2518 struct device *tmp;
ea2447f7
TM		 2519 int i;
2520
0e242612 2521 rcu_read_lock();
ea2447f7 2522 for_each_rmrr_units(rmrr) {
b683b230
JL		 2523 /*
2524 * Return TRUE if this RMRR contains the device that
2525 * is passed in.
2526 */
2527 for_each_active_dev_scope(rmrr->devices,
2528 rmrr->devices_cnt, i, tmp)
0b9d9753 2529 if (tmp == dev) {
0e242612 2530 rcu_read_unlock();
ea2447f7 2531 return true;
b683b230 2532 }
ea2447f7 2533 }
0e242612 2534 rcu_read_unlock();
ea2447f7
TM		 2535 return false;
2536}
2537
3bdb2591 2538static int iommu_should_identity_map(struct device *dev, int startup)
6941af28 2539{
ea2447f7 2540
3bdb2591
DW		 2541 if (dev_is_pci(dev)) {
2542 struct pci_dev *pdev = to_pci_dev(dev);
ea2447f7 2543
3bdb2591
DW		 2544 /*
2545 * We want to prevent any device associated with an RMRR from
2546 * getting placed into the SI Domain. This is done because
2547 * problems exist when devices are moved in and out of domains
2548 * and their respective RMRR info is lost. We exempt USB devices
2549 * from this process due to their usage of RMRRs that are known
2550 * to not be needed after BIOS hand-off to OS.
2551 */
2552 if (device_has_rmrr(dev) &&
2553 (pdev->class >> 8) != PCI_CLASS_SERIAL_USB)
2554 return 0;
e0fc7e0b 2555
3bdb2591
DW		 2556 if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev))
2557 return 1;
e0fc7e0b 2558
3bdb2591
DW		 2559 if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev))
2560 return 1;
6941af28 2561
3bdb2591 2562 if (!(iommu_identity_mapping & IDENTMAP_ALL))
3dfc813d 2563 return 0;
3bdb2591
DW		 2564
2565 /*
2566 * We want to start off with all devices in the 1:1 domain, and
2567 * take them out later if we find they can't access all of memory.
2568 *
2569 * However, we can't do this for PCI devices behind bridges,
2570 * because all PCI devices behind the same bridge will end up
2571 * with the same source-id on their transactions.
2572 *
2573 * Practically speaking, we can't change things around for these
2574 * devices at run-time, because we can't be sure there'll be no
2575 * DMA transactions in flight for any of their siblings.
2576 *
2577 * So PCI devices (unless they're on the root bus) as well as
2578 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2579 * the 1:1 domain, just in _case_ one of their siblings turns out
2580 * not to be able to map all of memory.
2581 */
2582 if (!pci_is_pcie(pdev)) {
2583 if (!pci_is_root_bus(pdev->bus))
2584 return 0;
2585 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2586 return 0;
2587 } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE)
3dfc813d 2588 return 0;
3bdb2591
DW		 2589 } else {
2590 if (device_has_rmrr(dev))
2591 return 0;
2592 }
3dfc813d 2593
3bdb2591 2594 /*
3dfc813d 2595 * At boot time, we don't yet know if devices will be 64-bit capable.
3bdb2591 2596 * Assume that they will — if they turn out not to be, then we can
3dfc813d
DW		 2597 * take them out of the 1:1 domain later.
2598 */
8fcc5372
CW		 2599 if (!startup) {
2600 /*
2601 * If the device's dma_mask is less than the system's memory
2602 * size then this is not a candidate for identity mapping.
2603 */
3bdb2591 2604 u64 dma_mask = *dev->dma_mask;
8fcc5372 2605
3bdb2591
DW		 2606 if (dev->coherent_dma_mask &&
2607 dev->coherent_dma_mask < dma_mask)
2608 dma_mask = dev->coherent_dma_mask;
8fcc5372 2609
3bdb2591 2610 return dma_mask >= dma_get_required_mask(dev);
8fcc5372 2611 }
6941af28
DW		 2612
2613 return 1;
2614}
2615
cf04eee8
DW		 2616static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw)
2617{
2618 int ret;
2619
2620 if (!iommu_should_identity_map(dev, 1))
2621 return 0;
2622
2623 ret = domain_add_dev_info(si_domain, dev,
2624 hw ? CONTEXT_TT_PASS_THROUGH :
2625 CONTEXT_TT_MULTI_LEVEL);
2626 if (!ret)
2627 pr_info("IOMMU: %s identity mapping for device %s\n",
2628 hw ? "hardware" : "software", dev_name(dev));
2629 else if (ret == -ENODEV)
2630 /* device not associated with an iommu */
2631 ret = 0;
2632
2633 return ret;
2634}
2635
2636
071e1374 2637static int __init iommu_prepare_static_identity_mapping(int hw)
2c2e2c38 2638{
2c2e2c38 2639 struct pci_dev *pdev = NULL;
cf04eee8
DW		 2640 struct dmar_drhd_unit *drhd;
2641 struct intel_iommu *iommu;
2642 struct device *dev;
2643 int i;
2644 int ret = 0;
2c2e2c38 2645
19943b0e 2646 ret = si_domain_init(hw);
2c2e2c38
FY		 2647 if (ret)
2648 return -EFAULT;
2649
2c2e2c38 2650 for_each_pci_dev(pdev) {
cf04eee8
DW		 2651 ret = dev_prepare_static_identity_mapping(&pdev->dev, hw);
2652 if (ret)
2653 return ret;
2654 }
2655
2656 for_each_active_iommu(iommu, drhd)
2657 for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) {
2658 struct acpi_device_physical_node *pn;
2659 struct acpi_device *adev;
2660
2661 if (dev->bus != &acpi_bus_type)
2662 continue;
2663
2664 adev= to_acpi_device(dev);
2665 mutex_lock(&adev->physical_node_lock);
2666 list_for_each_entry(pn, &adev->physical_node_list, node) {
2667 ret = dev_prepare_static_identity_mapping(pn->dev, hw);
2668 if (ret)
2669 break;
eae460b6 2670 }
cf04eee8
DW		 2671 mutex_unlock(&adev->physical_node_lock);
2672 if (ret)
2673 return ret;
62edf5dc 2674 }
2c2e2c38
FY		 2675
2676 return 0;
2677}
2678
b779260b 2679static int __init init_dmars(void)
ba395927
KA		 2680{
2681 struct dmar_drhd_unit *drhd;
2682 struct dmar_rmrr_unit *rmrr;
832bd858 2683 struct device *dev;
ba395927 2684 struct intel_iommu *iommu;
9d783ba0 2685 int i, ret;
2c2e2c38 2686
ba395927
KA		 2687 /*
2688 * for each drhd
2689 * allocate root
2690 * initialize and program root entry to not present
2691 * endfor
2692 */
2693 for_each_drhd_unit(drhd) {
5e0d2a6f 2694 /*
2695 * lock not needed as this is only incremented in the single
2696 * threaded kernel __init code path all other access are read
2697 * only
2698 */
1b198bb0
MT		 2699 if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) {
2700 g_num_of_iommus++;
2701 continue;
2702 }
2703 printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n",
2704 IOMMU_UNITS_SUPPORTED);
5e0d2a6f 2705 }
2706
d9630fe9
WH		 2707 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2708 GFP_KERNEL);
2709 if (!g_iommus) {
2710 printk(KERN_ERR "Allocating global iommu array failed\n");
2711 ret = -ENOMEM;
2712 goto error;
2713 }
2714
80b20dd8 2715 deferred_flush = kzalloc(g_num_of_iommus *
2716 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2717 if (!deferred_flush) {
5e0d2a6f 2718 ret = -ENOMEM;
989d51fc 2719 goto free_g_iommus;
5e0d2a6f 2720 }
2721
7c919779 2722 for_each_active_iommu(iommu, drhd) {
d9630fe9 2723 g_iommus[iommu->seq_id] = iommu;
ba395927 2724
e61d98d8
SS		 2725 ret = iommu_init_domains(iommu);
2726 if (ret)
989d51fc 2727 goto free_iommu;
e61d98d8 2728
ba395927
KA		 2729 /*
2730 * TBD:
2731 * we could share the same root & context tables
25985edc 2732 * among all IOMMU's. Need to Split it later.
ba395927
KA		 2733 */
2734 ret = iommu_alloc_root_entry(iommu);
2735 if (ret) {
2736 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
989d51fc 2737 goto free_iommu;
ba395927 2738 }
4ed0d3e6 2739 if (!ecap_pass_through(iommu->ecap))
19943b0e 2740 hw_pass_through = 0;
ba395927
KA		 2741 }
2742
1531a6a6
SS		 2743 /*
2744 * Start from the sane iommu hardware state.
2745 */
7c919779 2746 for_each_active_iommu(iommu, drhd) {
1531a6a6
SS		 2747 /*
2748 * If the queued invalidation is already initialized by us
2749 * (for example, while enabling interrupt-remapping) then
2750 * we got the things already rolling from a sane state.
2751 */
2752 if (iommu->qi)
2753 continue;
2754
2755 /*
2756 * Clear any previous faults.
2757 */
2758 dmar_fault(-1, iommu);
2759 /*
2760 * Disable queued invalidation if supported and already enabled
2761 * before OS handover.
2762 */
2763 dmar_disable_qi(iommu);
2764 }
2765
7c919779 2766 for_each_active_iommu(iommu, drhd) {
a77b67d4
YS		 2767 if (dmar_enable_qi(iommu)) {
2768 /*
2769 * Queued Invalidate not enabled, use Register Based
2770 * Invalidate
2771 */
2772 iommu->flush.flush_context = __iommu_flush_context;
2773 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
680a7524 2774 printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based "
b4e0f9eb 2775 "invalidation\n",
680a7524 2776 iommu->seq_id,
b4e0f9eb 2777 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2778 } else {
2779 iommu->flush.flush_context = qi_flush_context;
2780 iommu->flush.flush_iotlb = qi_flush_iotlb;
680a7524 2781 printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued "
b4e0f9eb 2782 "invalidation\n",
680a7524 2783 iommu->seq_id,
b4e0f9eb 2784 (unsigned long long)drhd->reg_base_addr);
a77b67d4
YS		 2785 }
2786 }
2787
19943b0e 2788 if (iommu_pass_through)
e0fc7e0b
DW		 2789 iommu_identity_mapping |= IDENTMAP_ALL;
2790
d3f13810 2791#ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA
e0fc7e0b 2792 iommu_identity_mapping |= IDENTMAP_GFX;
19943b0e 2793#endif
e0fc7e0b
DW		 2794
2795 check_tylersburg_isoch();
2796
ba395927 2797 /*
19943b0e
DW		 2798 * If pass through is not set or not enabled, setup context entries for
2799 * identity mappings for rmrr, gfx, and isa and may fall back to static
2800 * identity mapping if iommu_identity_mapping is set.
ba395927 2801 */
19943b0e
DW		 2802 if (iommu_identity_mapping) {
2803 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
4ed0d3e6 2804 if (ret) {
19943b0e 2805 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
989d51fc 2806 goto free_iommu;
ba395927
KA		 2807 }
2808 }
ba395927 2809 /*
19943b0e
DW		 2810 * For each rmrr
2811 * for each dev attached to rmrr
2812 * do
2813 * locate drhd for dev, alloc domain for dev
2814 * allocate free domain
2815 * allocate page table entries for rmrr
2816 * if context not allocated for bus
2817 * allocate and init context
2818 * set present in root table for this bus
2819 * init context with domain, translation etc
2820 * endfor
2821 * endfor
ba395927 2822 */
19943b0e
DW		 2823 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2824 for_each_rmrr_units(rmrr) {
b683b230
JL		 2825 /* some BIOS lists non-exist devices in DMAR table. */
2826 for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt,
832bd858 2827 i, dev) {
0b9d9753 2828 ret = iommu_prepare_rmrr_dev(rmrr, dev);
19943b0e
DW		 2829 if (ret)
2830 printk(KERN_ERR
2831 "IOMMU: mapping reserved region failed\n");
ba395927 2832 }
4ed0d3e6 2833 }
49a0429e 2834
19943b0e
DW		 2835 iommu_prepare_isa();
2836
ba395927
KA		 2837 /*
2838 * for each drhd
2839 * enable fault log
2840 * global invalidate context cache
2841 * global invalidate iotlb
2842 * enable translation
2843 */
7c919779 2844 for_each_iommu(iommu, drhd) {
51a63e67
JC		 2845 if (drhd->ignored) {
2846 /*
2847 * we always have to disable PMRs or DMA may fail on
2848 * this device
2849 */
2850 if (force_on)
7c919779 2851 iommu_disable_protect_mem_regions(iommu);
ba395927 2852 continue;
51a63e67 2853 }
ba395927
KA		 2854
2855 iommu_flush_write_buffer(iommu);
2856
3460a6d9
KA		 2857 ret = dmar_set_interrupt(iommu);
2858 if (ret)
989d51fc 2859 goto free_iommu;
3460a6d9 2860
ba395927
KA		 2861 iommu_set_root_entry(iommu);
2862
4c25a2c1 2863 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
1f0ef2aa 2864 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2a41ccee 2865 iommu_enable_translation(iommu);
b94996c9 2866 iommu_disable_protect_mem_regions(iommu);
ba395927
KA		 2867 }
2868
2869 return 0;
989d51fc
JL		 2870
2871free_iommu:
7c919779 2872 for_each_active_iommu(iommu, drhd)
a868e6b7 2873 free_dmar_iommu(iommu);
9bdc531e 2874 kfree(deferred_flush);
989d51fc 2875free_g_iommus:
d9630fe9 2876 kfree(g_iommus);
989d51fc 2877error:
ba395927
KA		 2878 return ret;
2879}
2880
5a5e02a6 2881/* This takes a number of _MM_ pages, not VTD pages */
875764de
DW		 2882static struct iova *intel_alloc_iova(struct device *dev,
2883 struct dmar_domain *domain,
2884 unsigned long nrpages, uint64_t dma_mask)
ba395927 2885{
ba395927 2886 struct iova *iova = NULL;
ba395927 2887
875764de
DW		 2888 /* Restrict dma_mask to the width that the iommu can handle */
2889 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2890
2891 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
ba395927
KA		 2892 /*
2893 * First try to allocate an io virtual address in
284901a9 2894 * DMA_BIT_MASK(32) and if that fails then try allocating
3609801e 2895 * from higher range
ba395927 2896 */
875764de
DW		 2897 iova = alloc_iova(&domain->iovad, nrpages,
2898 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2899 if (iova)
2900 return iova;
2901 }
2902 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2903 if (unlikely(!iova)) {
2904 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
207e3592 2905 nrpages, dev_name(dev));
f76aec76
KA		 2906 return NULL;
2907 }
2908
2909 return iova;
2910}
2911
d4b709f4 2912static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev)
f76aec76
KA		 2913{
2914 struct dmar_domain *domain;
2915 int ret;
2916
d4b709f4 2917 domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
f76aec76 2918 if (!domain) {
d4b709f4
DW		 2919 printk(KERN_ERR "Allocating domain for %s failed",
2920 dev_name(dev));
4fe05bbc 2921 return NULL;
ba395927
KA		 2922 }
2923
2924 /* make sure context mapping is ok */
d4b709f4
DW		 2925 if (unlikely(!domain_context_mapped(dev))) {
2926 ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL);
f76aec76 2927 if (ret) {
d4b709f4
DW		 2928 printk(KERN_ERR "Domain context map for %s failed",
2929 dev_name(dev));
4fe05bbc 2930 return NULL;
f76aec76 2931 }
ba395927
KA		 2932 }
2933
f76aec76
KA		 2934 return domain;
2935}
2936
d4b709f4 2937static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
147202aa
DW		 2938{
2939 struct device_domain_info *info;
2940
2941 /* No lock here, assumes no domain exit in normal case */
d4b709f4 2942 info = dev->archdata.iommu;
147202aa
DW		 2943 if (likely(info))
2944 return info->domain;
2945
2946 return __get_valid_domain_for_dev(dev);
2947}
2948
3d89194a 2949static int iommu_dummy(struct device *dev)
2c2e2c38 2950{
3d89194a 2951 return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2c2e2c38
FY		 2952}
2953
ecb509ec 2954/* Check if the dev needs to go through non-identity map and unmap process.*/
73676832 2955static int iommu_no_mapping(struct device *dev)
2c2e2c38
FY		 2956{
2957 int found;
2958
3d89194a 2959 if (iommu_dummy(dev))
1e4c64c4
DW		 2960 return 1;
2961
2c2e2c38 2962 if (!iommu_identity_mapping)
1e4c64c4 2963 return 0;
2c2e2c38 2964
9b226624 2965 found = identity_mapping(dev);
2c2e2c38 2966 if (found) {
ecb509ec 2967 if (iommu_should_identity_map(dev, 0))
2c2e2c38
FY		 2968 return 1;
2969 else {
2970 /*
2971 * 32 bit DMA is removed from si_domain and fall back
2972 * to non-identity mapping.
2973 */
bf9c9eda 2974 domain_remove_one_dev_info(si_domain, dev);
2c2e2c38 2975 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
ecb509ec 2976 dev_name(dev));
2c2e2c38
FY		 2977 return 0;
2978 }
2979 } else {
2980 /*
2981 * In case of a detached 64 bit DMA device from vm, the device
2982 * is put into si_domain for identity mapping.
2983 */
ecb509ec 2984 if (iommu_should_identity_map(dev, 0)) {
2c2e2c38 2985 int ret;
5913c9bf 2986 ret = domain_add_dev_info(si_domain, dev,
5fe60f4e
DW		 2987 hw_pass_through ?
2988 CONTEXT_TT_PASS_THROUGH :
2989 CONTEXT_TT_MULTI_LEVEL);
2c2e2c38
FY		 2990 if (!ret) {
2991 printk(KERN_INFO "64bit %s uses identity mapping\n",
ecb509ec 2992 dev_name(dev));
2c2e2c38
FY		 2993 return 1;
2994 }
2995 }
2996 }
2997
1e4c64c4 2998 return 0;
2c2e2c38
FY		 2999}
3000
5040a918 3001static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr,
bb9e6d65 3002 size_t size, int dir, u64 dma_mask)
f76aec76 3003{
f76aec76 3004 struct dmar_domain *domain;
5b6985ce 3005 phys_addr_t start_paddr;
f76aec76
KA		 3006 struct iova *iova;
3007 int prot = 0;
6865f0d1 3008 int ret;
8c11e798 3009 struct intel_iommu *iommu;
33041ec0 3010 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
f76aec76
KA		 3011
3012 BUG_ON(dir == DMA_NONE);
2c2e2c38 3013
5040a918 3014 if (iommu_no_mapping(dev))
6865f0d1 3015 return paddr;
f76aec76 3016
5040a918 3017 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3018 if (!domain)
3019 return 0;
3020
8c11e798 3021 iommu = domain_get_iommu(domain);
88cb6a74 3022 size = aligned_nrpages(paddr, size);
f76aec76 3023
5040a918 3024 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask);
f76aec76
KA		 3025 if (!iova)
3026 goto error;
3027
ba395927
KA		 3028 /*
3029 * Check if DMAR supports zero-length reads on write only
3030 * mappings..
3031 */
3032 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3033 !cap_zlr(iommu->cap))
ba395927
KA		 3034 prot |= DMA_PTE_READ;
3035 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3036 prot |= DMA_PTE_WRITE;
3037 /*
6865f0d1 3038 * paddr - (paddr + size) might be partial page, we should map the whole
ba395927 3039 * page. Note: if two part of one page are separately mapped, we
6865f0d1 3040 * might have two guest_addr mapping to the same host paddr, but this
ba395927
KA		 3041 * is not a big problem
3042 */
0ab36de2 3043 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
33041ec0 3044 mm_to_dma_pfn(paddr_pfn), size, prot);
ba395927
KA		 3045 if (ret)
3046 goto error;
3047
1f0ef2aa
DW		 3048 /* it's a non-present to present mapping. Only flush if caching mode */
3049 if (cap_caching_mode(iommu->cap))
ea8ea460 3050 iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1);
1f0ef2aa 3051 else
8c11e798 3052 iommu_flush_write_buffer(iommu);
f76aec76 3053
03d6a246
DW		 3054 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
3055 start_paddr += paddr & ~PAGE_MASK;
3056 return start_paddr;
ba395927 3057
ba395927 3058error:
f76aec76
KA		 3059 if (iova)
3060 __free_iova(&domain->iovad, iova);
4cf2e75d 3061 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
5040a918 3062 dev_name(dev), size, (unsigned long long)paddr, dir);
ba395927
KA		 3063 return 0;
3064}
3065
ffbbef5c
FT		 3066static dma_addr_t intel_map_page(struct device *dev, struct page *page,
3067 unsigned long offset, size_t size,
3068 enum dma_data_direction dir,
3069 struct dma_attrs *attrs)
bb9e6d65 3070{
ffbbef5c 3071 return __intel_map_single(dev, page_to_phys(page) + offset, size,
46333e37 3072 dir, *dev->dma_mask);
bb9e6d65
FT		 3073}
3074
5e0d2a6f 3075static void flush_unmaps(void)
3076{
80b20dd8 3077 int i, j;
5e0d2a6f 3078
5e0d2a6f 3079 timer_on = 0;
3080
3081 /* just flush them all */
3082 for (i = 0; i < g_num_of_iommus; i++) {
a2bb8459
WH		 3083 struct intel_iommu *iommu = g_iommus[i];
3084 if (!iommu)
3085 continue;
c42d9f32 3086
9dd2fe89
YZ		 3087 if (!deferred_flush[i].next)
3088 continue;
3089
78d5f0f5
NA		 3090 /* In caching mode, global flushes turn emulation expensive */
3091 if (!cap_caching_mode(iommu->cap))
3092 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
93a23a72 3093 DMA_TLB_GLOBAL_FLUSH);
9dd2fe89 3094 for (j = 0; j < deferred_flush[i].next; j++) {
93a23a72
YZ		 3095 unsigned long mask;
3096 struct iova *iova = deferred_flush[i].iova[j];
78d5f0f5
NA		 3097 struct dmar_domain *domain = deferred_flush[i].domain[j];
3098
3099 /* On real hardware multiple invalidations are expensive */
3100 if (cap_caching_mode(iommu->cap))
3101 iommu_flush_iotlb_psi(iommu, domain->id,
ea8ea460
DW		 3102 iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1,
3103 !deferred_flush[i].freelist[j], 0);
78d5f0f5
NA		 3104 else {
3105 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
3106 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
3107 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
3108 }
93a23a72 3109 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
ea8ea460
DW		 3110 if (deferred_flush[i].freelist[j])
3111 dma_free_pagelist(deferred_flush[i].freelist[j]);
80b20dd8 3112 }
9dd2fe89 3113 deferred_flush[i].next = 0;
5e0d2a6f 3114 }
3115
5e0d2a6f 3116 list_size = 0;
5e0d2a6f 3117}
3118
3119static void flush_unmaps_timeout(unsigned long data)
3120{
80b20dd8 3121 unsigned long flags;
3122
3123 spin_lock_irqsave(&async_umap_flush_lock, flags);
5e0d2a6f 3124 flush_unmaps();
80b20dd8 3125 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
5e0d2a6f 3126}
3127
ea8ea460 3128static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist)
5e0d2a6f 3129{
3130 unsigned long flags;
80b20dd8 3131 int next, iommu_id;
8c11e798 3132 struct intel_iommu *iommu;
5e0d2a6f 3133
3134 spin_lock_irqsave(&async_umap_flush_lock, flags);
80b20dd8 3135 if (list_size == HIGH_WATER_MARK)
3136 flush_unmaps();
3137
8c11e798
WH		 3138 iommu = domain_get_iommu(dom);
3139 iommu_id = iommu->seq_id;
c42d9f32 3140
80b20dd8 3141 next = deferred_flush[iommu_id].next;
3142 deferred_flush[iommu_id].domain[next] = dom;
3143 deferred_flush[iommu_id].iova[next] = iova;
ea8ea460 3144 deferred_flush[iommu_id].freelist[next] = freelist;
80b20dd8 3145 deferred_flush[iommu_id].next++;
5e0d2a6f 3146
3147 if (!timer_on) {
3148 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
3149 timer_on = 1;
3150 }
3151 list_size++;
3152 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
3153}
3154
d41a4adb 3155static void intel_unmap(struct device *dev, dma_addr_t dev_addr)
ba395927 3156{
f76aec76 3157 struct dmar_domain *domain;
d794dc9b 3158 unsigned long start_pfn, last_pfn;
ba395927 3159 struct iova *iova;
8c11e798 3160 struct intel_iommu *iommu;
ea8ea460 3161 struct page *freelist;
ba395927 3162
73676832 3163 if (iommu_no_mapping(dev))
f76aec76 3164 return;
2c2e2c38 3165
1525a29a 3166 domain = find_domain(dev);
ba395927
KA		 3167 BUG_ON(!domain);
3168
8c11e798
WH		 3169 iommu = domain_get_iommu(domain);
3170
ba395927 3171 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
85b98276
DW		 3172 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
3173 (unsigned long long)dev_addr))
ba395927 3174 return;
ba395927 3175
d794dc9b
DW		 3176 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
3177 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
ba395927 3178
d794dc9b 3179 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
207e3592 3180 dev_name(dev), start_pfn, last_pfn);
ba395927 3181
ea8ea460 3182 freelist = domain_unmap(domain, start_pfn, last_pfn);
d794dc9b 3183
5e0d2a6f 3184 if (intel_iommu_strict) {
03d6a246 3185 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
ea8ea460 3186 last_pfn - start_pfn + 1, !freelist, 0);
5e0d2a6f 3187 /* free iova */
3188 __free_iova(&domain->iovad, iova);
ea8ea460 3189 dma_free_pagelist(freelist);
5e0d2a6f 3190 } else {
ea8ea460 3191 add_unmap(domain, iova, freelist);
5e0d2a6f 3192 /*
3193 * queue up the release of the unmap to save the 1/6th of the
3194 * cpu used up by the iotlb flush operation...
3195 */
5e0d2a6f 3196 }
ba395927
KA		 3197}
3198
d41a4adb
JL		 3199static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
3200 size_t size, enum dma_data_direction dir,
3201 struct dma_attrs *attrs)
3202{
3203 intel_unmap(dev, dev_addr);
3204}
3205
5040a918 3206static void *intel_alloc_coherent(struct device *dev, size_t size,
baa676fc
AP		 3207 dma_addr_t *dma_handle, gfp_t flags,
3208 struct dma_attrs *attrs)
ba395927 3209{
36746436 3210 struct page *page = NULL;
ba395927
KA		 3211 int order;
3212
5b6985ce 3213 size = PAGE_ALIGN(size);
ba395927 3214 order = get_order(size);
e8bb910d 3215
5040a918 3216 if (!iommu_no_mapping(dev))
e8bb910d 3217 flags &= ~(GFP_DMA | GFP_DMA32);
5040a918
DW		 3218 else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) {
3219 if (dev->coherent_dma_mask < DMA_BIT_MASK(32))
e8bb910d
AW		 3220 flags |= GFP_DMA;
3221 else
3222 flags |= GFP_DMA32;
3223 }
ba395927 3224
36746436
AM		 3225 if (flags & __GFP_WAIT) {
3226 unsigned int count = size >> PAGE_SHIFT;
3227
3228 page = dma_alloc_from_contiguous(dev, count, order);
3229 if (page && iommu_no_mapping(dev) &&
3230 page_to_phys(page) + size > dev->coherent_dma_mask) {
3231 dma_release_from_contiguous(dev, page, count);
3232 page = NULL;
3233 }
3234 }
3235
3236 if (!page)
3237 page = alloc_pages(flags, order);
3238 if (!page)
ba395927 3239 return NULL;
36746436 3240 memset(page_address(page), 0, size);
ba395927 3241
36746436 3242 *dma_handle = __intel_map_single(dev, page_to_phys(page), size,
bb9e6d65 3243 DMA_BIDIRECTIONAL,
5040a918 3244 dev->coherent_dma_mask);
ba395927 3245 if (*dma_handle)
36746436
AM		 3246 return page_address(page);
3247 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3248 __free_pages(page, order);
3249
ba395927
KA		 3250 return NULL;
3251}
3252
5040a918 3253static void intel_free_coherent(struct device *dev, size_t size, void *vaddr,
baa676fc 3254 dma_addr_t dma_handle, struct dma_attrs *attrs)
ba395927
KA		 3255{
3256 int order;
36746436 3257 struct page *page = virt_to_page(vaddr);
ba395927 3258
5b6985ce 3259 size = PAGE_ALIGN(size);
ba395927
KA		 3260 order = get_order(size);
3261
d41a4adb 3262 intel_unmap(dev, dma_handle);
36746436
AM		 3263 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3264 __free_pages(page, order);
ba395927
KA		 3265}
3266
5040a918 3267static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist,
d7ab5c46
FT		 3268 int nelems, enum dma_data_direction dir,
3269 struct dma_attrs *attrs)
ba395927 3270{
d41a4adb 3271 intel_unmap(dev, sglist[0].dma_address);
ba395927
KA		 3272}
3273
ba395927 3274static int intel_nontranslate_map_sg(struct device *hddev,
c03ab37c 3275 struct scatterlist *sglist, int nelems, int dir)
ba395927
KA		 3276{
3277 int i;
c03ab37c 3278 struct scatterlist *sg;
ba395927 3279
c03ab37c 3280 for_each_sg(sglist, sg, nelems, i) {
12d4d40e 3281 BUG_ON(!sg_page(sg));
4cf2e75d 3282 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
c03ab37c 3283 sg->dma_length = sg->length;
ba395927
KA		 3284 }
3285 return nelems;
3286}
3287
5040a918 3288static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems,
d7ab5c46 3289 enum dma_data_direction dir, struct dma_attrs *attrs)
ba395927 3290{
ba395927 3291 int i;
ba395927 3292 struct dmar_domain *domain;
f76aec76
KA		 3293 size_t size = 0;
3294 int prot = 0;
f76aec76
KA		 3295 struct iova *iova = NULL;
3296 int ret;
c03ab37c 3297 struct scatterlist *sg;
b536d24d 3298 unsigned long start_vpfn;
8c11e798 3299 struct intel_iommu *iommu;
ba395927
KA		 3300
3301 BUG_ON(dir == DMA_NONE);
5040a918
DW		 3302 if (iommu_no_mapping(dev))
3303 return intel_nontranslate_map_sg(dev, sglist, nelems, dir);
ba395927 3304
5040a918 3305 domain = get_valid_domain_for_dev(dev);
f76aec76
KA		 3306 if (!domain)
3307 return 0;
3308
8c11e798
WH		 3309 iommu = domain_get_iommu(domain);
3310
b536d24d 3311 for_each_sg(sglist, sg, nelems, i)
88cb6a74 3312 size += aligned_nrpages(sg->offset, sg->length);
f76aec76 3313
5040a918
DW		 3314 iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size),
3315 *dev->dma_mask);
f76aec76 3316 if (!iova) {
c03ab37c 3317 sglist->dma_length = 0;
f76aec76
KA		 3318 return 0;
3319 }
3320
3321 /*
3322 * Check if DMAR supports zero-length reads on write only
3323 * mappings..
3324 */
3325 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
8c11e798 3326 !cap_zlr(iommu->cap))
f76aec76
KA		 3327 prot |= DMA_PTE_READ;
3328 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
3329 prot |= DMA_PTE_WRITE;
3330
b536d24d 3331 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
e1605495 3332
f532959b 3333 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
e1605495 3334 if (unlikely(ret)) {
e1605495
DW		 3335 dma_pte_free_pagetable(domain, start_vpfn,
3336 start_vpfn + size - 1);
e1605495
DW		 3337 __free_iova(&domain->iovad, iova);
3338 return 0;
ba395927
KA		 3339 }
3340
1f0ef2aa
DW		 3341 /* it's a non-present to present mapping. Only flush if caching mode */
3342 if (cap_caching_mode(iommu->cap))
ea8ea460 3343 iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1);
1f0ef2aa 3344 else
8c11e798 3345 iommu_flush_write_buffer(iommu);
1f0ef2aa 3346
ba395927
KA		 3347 return nelems;
3348}
3349
dfb805e8
FT		 3350static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
3351{
3352 return !dma_addr;
3353}
3354
160c1d8e 3355struct dma_map_ops intel_dma_ops = {
baa676fc
AP		 3356 .alloc = intel_alloc_coherent,
3357 .free = intel_free_coherent,
ba395927
KA		 3358 .map_sg = intel_map_sg,
3359 .unmap_sg = intel_unmap_sg,
ffbbef5c
FT		 3360 .map_page = intel_map_page,
3361 .unmap_page = intel_unmap_page,
dfb805e8 3362 .mapping_error = intel_mapping_error,
ba395927
KA		 3363};
3364
3365static inline int iommu_domain_cache_init(void)
3366{
3367 int ret = 0;
3368
3369 iommu_domain_cache = kmem_cache_create("iommu_domain",
3370 sizeof(struct dmar_domain),
3371 0,
3372 SLAB_HWCACHE_ALIGN,
3373
3374 NULL);
3375 if (!iommu_domain_cache) {
3376 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
3377 ret = -ENOMEM;
3378 }
3379
3380 return ret;
3381}
3382
3383static inline int iommu_devinfo_cache_init(void)
3384{
3385 int ret = 0;
3386
3387 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
3388 sizeof(struct device_domain_info),
3389 0,
3390 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3391 NULL);
3392 if (!iommu_devinfo_cache) {
3393 printk(KERN_ERR "Couldn't create devinfo cache\n");
3394 ret = -ENOMEM;
3395 }
3396
3397 return ret;
3398}
3399
3400static inline int iommu_iova_cache_init(void)
3401{
3402 int ret = 0;
3403
3404 iommu_iova_cache = kmem_cache_create("iommu_iova",
3405 sizeof(struct iova),
3406 0,
3407 SLAB_HWCACHE_ALIGN,
ba395927
KA		 3408 NULL);
3409 if (!iommu_iova_cache) {
3410 printk(KERN_ERR "Couldn't create iova cache\n");
3411 ret = -ENOMEM;
3412 }
3413
3414 return ret;
3415}
3416
3417static int __init iommu_init_mempool(void)
3418{
3419 int ret;
3420 ret = iommu_iova_cache_init();
3421 if (ret)
3422 return ret;
3423
3424 ret = iommu_domain_cache_init();
3425 if (ret)
3426 goto domain_error;
3427
3428 ret = iommu_devinfo_cache_init();
3429 if (!ret)
3430 return ret;
3431
3432 kmem_cache_destroy(iommu_domain_cache);
3433domain_error:
3434 kmem_cache_destroy(iommu_iova_cache);
3435
3436 return -ENOMEM;
3437}
3438
3439static void __init iommu_exit_mempool(void)
3440{
3441 kmem_cache_destroy(iommu_devinfo_cache);
3442 kmem_cache_destroy(iommu_domain_cache);
3443 kmem_cache_destroy(iommu_iova_cache);
3444
3445}
3446
556ab45f
DW		 3447static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev)
3448{
3449 struct dmar_drhd_unit *drhd;
3450 u32 vtbar;
3451 int rc;
3452
3453 /* We know that this device on this chipset has its own IOMMU.
3454 * If we find it under a different IOMMU, then the BIOS is lying
3455 * to us. Hope that the IOMMU for this device is actually
3456 * disabled, and it needs no translation...
3457 */
3458 rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar);
3459 if (rc) {
3460 /* "can't" happen */
3461 dev_info(&pdev->dev, "failed to run vt-d quirk\n");
3462 return;
3463 }
3464 vtbar &= 0xffff0000;
3465
3466 /* we know that the this iommu should be at offset 0xa000 from vtbar */
3467 drhd = dmar_find_matched_drhd_unit(pdev);
3468 if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000,
3469 TAINT_FIRMWARE_WORKAROUND,
3470 "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n"))
3471 pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3472}
3473DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu);
3474
ba395927
KA		 3475static void __init init_no_remapping_devices(void)
3476{
3477 struct dmar_drhd_unit *drhd;
832bd858 3478 struct device *dev;
b683b230 3479 int i;
ba395927
KA		 3480
3481 for_each_drhd_unit(drhd) {
3482 if (!drhd->include_all) {
b683b230
JL		 3483 for_each_active_dev_scope(drhd->devices,
3484 drhd->devices_cnt, i, dev)
3485 break;
832bd858 3486 /* ignore DMAR unit if no devices exist */
ba395927
KA		 3487 if (i == drhd->devices_cnt)
3488 drhd->ignored = 1;
3489 }
3490 }
3491
7c919779 3492 for_each_active_drhd_unit(drhd) {
7c919779 3493 if (drhd->include_all)
ba395927
KA		 3494 continue;
3495
b683b230
JL		 3496 for_each_active_dev_scope(drhd->devices,
3497 drhd->devices_cnt, i, dev)
832bd858 3498 if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev)))
ba395927 3499 break;
ba395927
KA		 3500 if (i < drhd->devices_cnt)
3501 continue;
3502
c0771df8
DW		 3503 /* This IOMMU has *only* gfx devices. Either bypass it or
3504 set the gfx_mapped flag, as appropriate */
3505 if (dmar_map_gfx) {
3506 intel_iommu_gfx_mapped = 1;
3507 } else {
3508 drhd->ignored = 1;
b683b230
JL		 3509 for_each_active_dev_scope(drhd->devices,
3510 drhd->devices_cnt, i, dev)
832bd858 3511 dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
ba395927
KA		 3512 }
3513 }
3514}
3515
f59c7b69
FY		 3516#ifdef CONFIG_SUSPEND
3517static int init_iommu_hw(void)
3518{
3519 struct dmar_drhd_unit *drhd;
3520 struct intel_iommu *iommu = NULL;
3521
3522 for_each_active_iommu(iommu, drhd)
3523 if (iommu->qi)
3524 dmar_reenable_qi(iommu);
3525
b779260b
JC		 3526 for_each_iommu(iommu, drhd) {
3527 if (drhd->ignored) {
3528 /*
3529 * we always have to disable PMRs or DMA may fail on
3530 * this device
3531 */
3532 if (force_on)
3533 iommu_disable_protect_mem_regions(iommu);
3534 continue;
3535 }
3536
f59c7b69
FY		 3537 iommu_flush_write_buffer(iommu);
3538
3539 iommu_set_root_entry(iommu);
3540
3541 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3542 DMA_CCMD_GLOBAL_INVL);
2a41ccee
JL		 3543 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
3544 iommu_enable_translation(iommu);
b94996c9 3545 iommu_disable_protect_mem_regions(iommu);
f59c7b69
FY		 3546 }
3547
3548 return 0;
3549}
3550
3551static void iommu_flush_all(void)
3552{
3553 struct dmar_drhd_unit *drhd;
3554 struct intel_iommu *iommu;
3555
3556 for_each_active_iommu(iommu, drhd) {
3557 iommu->flush.flush_context(iommu, 0, 0, 0,
1f0ef2aa 3558 DMA_CCMD_GLOBAL_INVL);
f59c7b69 3559 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
1f0ef2aa 3560 DMA_TLB_GLOBAL_FLUSH);
f59c7b69
FY		 3561 }
3562}
3563
134fac3f 3564static int iommu_suspend(void)
f59c7b69
FY		 3565{
3566 struct dmar_drhd_unit *drhd;
3567 struct intel_iommu *iommu = NULL;
3568 unsigned long flag;
3569
3570 for_each_active_iommu(iommu, drhd) {
3571 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3572 GFP_ATOMIC);
3573 if (!iommu->iommu_state)
3574 goto nomem;
3575 }
3576
3577 iommu_flush_all();
3578
3579 for_each_active_iommu(iommu, drhd) {
3580 iommu_disable_translation(iommu);
3581
1f5b3c3f 3582 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3583
3584 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3585 readl(iommu->reg + DMAR_FECTL_REG);
3586 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3587 readl(iommu->reg + DMAR_FEDATA_REG);
3588 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3589 readl(iommu->reg + DMAR_FEADDR_REG);
3590 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3591 readl(iommu->reg + DMAR_FEUADDR_REG);
3592
1f5b3c3f 3593 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3594 }
3595 return 0;
3596
3597nomem:
3598 for_each_active_iommu(iommu, drhd)
3599 kfree(iommu->iommu_state);
3600
3601 return -ENOMEM;
3602}
3603
134fac3f 3604static void iommu_resume(void)
f59c7b69
FY		 3605{
3606 struct dmar_drhd_unit *drhd;
3607 struct intel_iommu *iommu = NULL;
3608 unsigned long flag;
3609
3610 if (init_iommu_hw()) {
b779260b
JC		 3611 if (force_on)
3612 panic("tboot: IOMMU setup failed, DMAR can not resume!\n");
3613 else
3614 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
134fac3f 3615 return;
f59c7b69
FY		 3616 }
3617
3618 for_each_active_iommu(iommu, drhd) {
3619
1f5b3c3f 3620 raw_spin_lock_irqsave(&iommu->register_lock, flag);
f59c7b69
FY		 3621
3622 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3623 iommu->reg + DMAR_FECTL_REG);
3624 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3625 iommu->reg + DMAR_FEDATA_REG);
3626 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3627 iommu->reg + DMAR_FEADDR_REG);
3628 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3629 iommu->reg + DMAR_FEUADDR_REG);
3630
1f5b3c3f 3631 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
f59c7b69
FY		 3632 }
3633
3634 for_each_active_iommu(iommu, drhd)
3635 kfree(iommu->iommu_state);
f59c7b69
FY		 3636}
3637
134fac3f 3638static struct syscore_ops iommu_syscore_ops = {
f59c7b69
FY		 3639 .resume = iommu_resume,
3640 .suspend = iommu_suspend,
3641};
3642
134fac3f 3643static void __init init_iommu_pm_ops(void)
f59c7b69 3644{
134fac3f 3645 register_syscore_ops(&iommu_syscore_ops);
f59c7b69
FY		 3646}
3647
3648#else
99592ba4 3649static inline void init_iommu_pm_ops(void) {}
f59c7b69
FY		 3650#endif /* CONFIG_PM */
3651
318fe7df
SS		 3652
3653int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header)
3654{
3655 struct acpi_dmar_reserved_memory *rmrr;
3656 struct dmar_rmrr_unit *rmrru;
3657
3658 rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL);
3659 if (!rmrru)
3660 return -ENOMEM;
3661
3662 rmrru->hdr = header;
3663 rmrr = (struct acpi_dmar_reserved_memory *)header;
3664 rmrru->base_address = rmrr->base_address;
3665 rmrru->end_address = rmrr->end_address;
2e455289
JL		 3666 rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1),
3667 ((void *)rmrr) + rmrr->header.length,
3668 &rmrru->devices_cnt);
3669 if (rmrru->devices_cnt && rmrru->devices == NULL) {
3670 kfree(rmrru);
3671 return -ENOMEM;
3672 }
318fe7df 3673
2e455289 3674 list_add(&rmrru->list, &dmar_rmrr_units);
318fe7df 3675
2e455289 3676 return 0;
318fe7df
SS		 3677}
3678
318fe7df
SS		 3679int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr)
3680{
3681 struct acpi_dmar_atsr *atsr;
3682 struct dmar_atsr_unit *atsru;
3683
3684 atsr = container_of(hdr, struct acpi_dmar_atsr, header);
3685 atsru = kzalloc(sizeof(*atsru), GFP_KERNEL);
3686 if (!atsru)
3687 return -ENOMEM;
3688
3689 atsru->hdr = hdr;
3690 atsru->include_all = atsr->flags & 0x1;
2e455289
JL		 3691 if (!atsru->include_all) {
3692 atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1),
3693 (void *)atsr + atsr->header.length,
3694 &atsru->devices_cnt);
3695 if (atsru->devices_cnt && atsru->devices == NULL) {
3696 kfree(atsru);
3697 return -ENOMEM;
3698 }
3699 }
318fe7df 3700
0e242612 3701 list_add_rcu(&atsru->list, &dmar_atsr_units);
318fe7df
SS		 3702
3703 return 0;
3704}
3705
9bdc531e
JL		 3706static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru)
3707{
3708 dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt);
3709 kfree(atsru);
3710}
3711
3712static void intel_iommu_free_dmars(void)
3713{
3714 struct dmar_rmrr_unit *rmrru, *rmrr_n;
3715 struct dmar_atsr_unit *atsru, *atsr_n;
3716
3717 list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) {
3718 list_del(&rmrru->list);
3719 dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt);
3720 kfree(rmrru);
318fe7df
SS		 3721 }
3722
9bdc531e
JL		 3723 list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) {
3724 list_del(&atsru->list);
3725 intel_iommu_free_atsr(atsru);
3726 }
318fe7df
SS		 3727}
3728
3729int dmar_find_matched_atsr_unit(struct pci_dev *dev)
3730{
b683b230 3731 int i, ret = 1;
318fe7df 3732 struct pci_bus *bus;
832bd858
DW		 3733 struct pci_dev *bridge = NULL;
3734 struct device *tmp;
318fe7df
SS		 3735 struct acpi_dmar_atsr *atsr;
3736 struct dmar_atsr_unit *atsru;
3737
3738 dev = pci_physfn(dev);
318fe7df 3739 for (bus = dev->bus; bus; bus = bus->parent) {
b5f82ddf 3740 bridge = bus->self;
318fe7df 3741 if (!bridge || !pci_is_pcie(bridge) ||
62f87c0e 3742 pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE)
318fe7df 3743 return 0;
b5f82ddf 3744 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT)
318fe7df 3745 break;
318fe7df 3746 }
b5f82ddf
JL		 3747 if (!bridge)
3748 return 0;
318fe7df 3749
0e242612 3750 rcu_read_lock();
b5f82ddf
JL		 3751 list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) {
3752 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3753 if (atsr->segment != pci_domain_nr(dev->bus))
3754 continue;
3755
b683b230 3756 for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp)
832bd858 3757 if (tmp == &bridge->dev)
b683b230 3758 goto out;
b5f82ddf
JL		 3759
3760 if (atsru->include_all)
b683b230 3761 goto out;
b5f82ddf 3762 }
b683b230
JL		 3763 ret = 0;
3764out:
0e242612 3765 rcu_read_unlock();
318fe7df 3766
b683b230 3767 return ret;
318fe7df
SS		 3768}
3769
59ce0515
JL		 3770int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info)
3771{
3772 int ret = 0;
3773 struct dmar_rmrr_unit *rmrru;
3774 struct dmar_atsr_unit *atsru;
3775 struct acpi_dmar_atsr *atsr;
3776 struct acpi_dmar_reserved_memory *rmrr;
3777
3778 if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING)
3779 return 0;
3780
3781 list_for_each_entry(rmrru, &dmar_rmrr_units, list) {
3782 rmrr = container_of(rmrru->hdr,
3783 struct acpi_dmar_reserved_memory, header);
3784 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3785 ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1),
3786 ((void *)rmrr) + rmrr->header.length,
3787 rmrr->segment, rmrru->devices,
3788 rmrru->devices_cnt);
27e24950 3789 if(ret < 0)
59ce0515
JL		 3790 return ret;
3791 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
27e24950
JL		 3792 dmar_remove_dev_scope(info, rmrr->segment,
3793 rmrru->devices, rmrru->devices_cnt);
59ce0515
JL		 3794 }
3795 }
3796
3797 list_for_each_entry(atsru, &dmar_atsr_units, list) {
3798 if (atsru->include_all)
3799 continue;
3800
3801 atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header);
3802 if (info->event == BUS_NOTIFY_ADD_DEVICE) {
3803 ret = dmar_insert_dev_scope(info, (void *)(atsr + 1),
3804 (void *)atsr + atsr->header.length,
3805 atsr->segment, atsru->devices,
3806 atsru->devices_cnt);
3807 if (ret > 0)
3808 break;
3809 else if(ret < 0)
3810 return ret;
3811 } else if (info->event == BUS_NOTIFY_DEL_DEVICE) {
3812 if (dmar_remove_dev_scope(info, atsr->segment,
3813 atsru->devices, atsru->devices_cnt))
3814 break;
3815 }
3816 }
3817
3818 return 0;
3819}
3820
99dcaded
FY		 3821/*
3822 * Here we only respond to action of unbound device from driver.
3823 *
3824 * Added device is not attached to its DMAR domain here yet. That will happen
3825 * when mapping the device to iova.
3826 */
3827static int device_notifier(struct notifier_block *nb,
3828 unsigned long action, void *data)
3829{
3830 struct device *dev = data;
99dcaded
FY		 3831 struct dmar_domain *domain;
3832
3d89194a 3833 if (iommu_dummy(dev))
44cd613c
DW		 3834 return 0;
3835
7e7dfab7
JL		 3836 if (action != BUS_NOTIFY_UNBOUND_DRIVER &&
3837 action != BUS_NOTIFY_DEL_DEVICE)
3838 return 0;
3839
1525a29a 3840 domain = find_domain(dev);
99dcaded
FY		 3841 if (!domain)
3842 return 0;
3843
3a5670e8 3844 down_read(&dmar_global_lock);
bf9c9eda 3845 domain_remove_one_dev_info(domain, dev);
ab8dfe25 3846 if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices))
7e7dfab7 3847 domain_exit(domain);
3a5670e8 3848 up_read(&dmar_global_lock);
a97590e5 3849
99dcaded
FY		 3850 return 0;
3851}
3852
3853static struct notifier_block device_nb = {
3854 .notifier_call = device_notifier,
3855};
3856
75f05569
JL		 3857static int intel_iommu_memory_notifier(struct notifier_block *nb,
3858 unsigned long val, void *v)
3859{
3860 struct memory_notify *mhp = v;
3861 unsigned long long start, end;
3862 unsigned long start_vpfn, last_vpfn;
3863
3864 switch (val) {
3865 case MEM_GOING_ONLINE:
3866 start = mhp->start_pfn << PAGE_SHIFT;
3867 end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1;
3868 if (iommu_domain_identity_map(si_domain, start, end)) {
3869 pr_warn("dmar: failed to build identity map for [%llx-%llx]\n",
3870 start, end);
3871 return NOTIFY_BAD;
3872 }
3873 break;
3874
3875 case MEM_OFFLINE:
3876 case MEM_CANCEL_ONLINE:
3877 start_vpfn = mm_to_dma_pfn(mhp->start_pfn);
3878 last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1);
3879 while (start_vpfn <= last_vpfn) {
3880 struct iova *iova;
3881 struct dmar_drhd_unit *drhd;
3882 struct intel_iommu *iommu;
ea8ea460 3883 struct page *freelist;
75f05569
JL		 3884
3885 iova = find_iova(&si_domain->iovad, start_vpfn);
3886 if (iova == NULL) {
3887 pr_debug("dmar: failed get IOVA for PFN %lx\n",
3888 start_vpfn);
3889 break;
3890 }
3891
3892 iova = split_and_remove_iova(&si_domain->iovad, iova,
3893 start_vpfn, last_vpfn);
3894 if (iova == NULL) {
3895 pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n",
3896 start_vpfn, last_vpfn);
3897 return NOTIFY_BAD;
3898 }
3899
ea8ea460
DW		 3900 freelist = domain_unmap(si_domain, iova->pfn_lo,
3901 iova->pfn_hi);
3902
75f05569
JL		 3903 rcu_read_lock();
3904 for_each_active_iommu(iommu, drhd)
3905 iommu_flush_iotlb_psi(iommu, si_domain->id,
3906 iova->pfn_lo,
ea8ea460
DW		 3907 iova->pfn_hi - iova->pfn_lo + 1,
3908 !freelist, 0);
75f05569 3909 rcu_read_unlock();
ea8ea460 3910 dma_free_pagelist(freelist);
75f05569
JL		 3911
3912 start_vpfn = iova->pfn_hi + 1;
3913 free_iova_mem(iova);
3914 }
3915 break;
3916 }
3917
3918 return NOTIFY_OK;
3919}
3920
3921static struct notifier_block intel_iommu_memory_nb = {
3922 .notifier_call = intel_iommu_memory_notifier,
3923 .priority = 0
3924};
3925
a5459cfe
AW		 3926
3927static ssize_t intel_iommu_show_version(struct device *dev,
3928 struct device_attribute *attr,
3929 char *buf)
3930{
3931 struct intel_iommu *iommu = dev_get_drvdata(dev);
3932 u32 ver = readl(iommu->reg + DMAR_VER_REG);
3933 return sprintf(buf, "%d:%d\n",
3934 DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver));
3935}
3936static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL);
3937
3938static ssize_t intel_iommu_show_address(struct device *dev,
3939 struct device_attribute *attr,
3940 char *buf)
3941{
3942 struct intel_iommu *iommu = dev_get_drvdata(dev);
3943 return sprintf(buf, "%llx\n", iommu->reg_phys);
3944}
3945static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL);
3946
3947static ssize_t intel_iommu_show_cap(struct device *dev,
3948 struct device_attribute *attr,
3949 char *buf)
3950{
3951 struct intel_iommu *iommu = dev_get_drvdata(dev);
3952 return sprintf(buf, "%llx\n", iommu->cap);
3953}
3954static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL);
3955
3956static ssize_t intel_iommu_show_ecap(struct device *dev,
3957 struct device_attribute *attr,
3958 char *buf)
3959{
3960 struct intel_iommu *iommu = dev_get_drvdata(dev);
3961 return sprintf(buf, "%llx\n", iommu->ecap);
3962}
3963static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL);
3964
3965static struct attribute *intel_iommu_attrs[] = {
3966 &dev_attr_version.attr,
3967 &dev_attr_address.attr,
3968 &dev_attr_cap.attr,
3969 &dev_attr_ecap.attr,
3970 NULL,
3971};
3972
3973static struct attribute_group intel_iommu_group = {
3974 .name = "intel-iommu",
3975 .attrs = intel_iommu_attrs,
3976};
3977
3978const struct attribute_group *intel_iommu_groups[] = {
3979 &intel_iommu_group,
3980 NULL,
3981};
3982
ba395927
KA		 3983int __init intel_iommu_init(void)
3984{
9bdc531e 3985 int ret = -ENODEV;
3a93c841 3986 struct dmar_drhd_unit *drhd;
7c919779 3987 struct intel_iommu *iommu;
ba395927 3988
a59b50e9
JC		 3989 /* VT-d is required for a TXT/tboot launch, so enforce that */
3990 force_on = tboot_force_iommu();
3991
3a5670e8
JL		 3992 if (iommu_init_mempool()) {
3993 if (force_on)
3994 panic("tboot: Failed to initialize iommu memory\n");
3995 return -ENOMEM;
3996 }
3997
3998 down_write(&dmar_global_lock);
a59b50e9
JC		 3999 if (dmar_table_init()) {
4000 if (force_on)
4001 panic("tboot: Failed to initialize DMAR table\n");
9bdc531e 4002 goto out_free_dmar;
a59b50e9 4003 }
ba395927 4004
3a93c841
TI		 4005 /*
4006 * Disable translation if already enabled prior to OS handover.
4007 */
7c919779 4008 for_each_active_iommu(iommu, drhd)
3a93c841
TI		 4009 if (iommu->gcmd & DMA_GCMD_TE)
4010 iommu_disable_translation(iommu);
3a93c841 4011
c2c7286a 4012 if (dmar_dev_scope_init() < 0) {
a59b50e9
JC		 4013 if (force_on)
4014 panic("tboot: Failed to initialize DMAR device scope\n");
9bdc531e 4015 goto out_free_dmar;
a59b50e9 4016 }
1886e8a9 4017
75f1cdf1 4018 if (no_iommu || dmar_disabled)
9bdc531e 4019 goto out_free_dmar;
2ae21010 4020
318fe7df
SS		 4021 if (list_empty(&dmar_rmrr_units))
4022 printk(KERN_INFO "DMAR: No RMRR found\n");
4023
4024 if (list_empty(&dmar_atsr_units))
4025 printk(KERN_INFO "DMAR: No ATSR found\n");
4026
51a63e67
JC		 4027 if (dmar_init_reserved_ranges()) {
4028 if (force_on)
4029 panic("tboot: Failed to reserve iommu ranges\n");
3a5670e8 4030 goto out_free_reserved_range;
51a63e67 4031 }
ba395927
KA		 4032
4033 init_no_remapping_devices();
4034
b779260b 4035 ret = init_dmars();
ba395927 4036 if (ret) {
a59b50e9
JC		 4037 if (force_on)
4038 panic("tboot: Failed to initialize DMARs\n");
ba395927 4039 printk(KERN_ERR "IOMMU: dmar init failed\n");
9bdc531e 4040 goto out_free_reserved_range;
ba395927 4041 }
3a5670e8 4042 up_write(&dmar_global_lock);
ba395927
KA		 4043 printk(KERN_INFO
4044 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
4045
5e0d2a6f 4046 init_timer(&unmap_timer);
75f1cdf1
FT		 4047#ifdef CONFIG_SWIOTLB
4048 swiotlb = 0;
4049#endif
19943b0e 4050 dma_ops = &intel_dma_ops;
4ed0d3e6 4051
134fac3f 4052 init_iommu_pm_ops();
a8bcbb0d 4053
a5459cfe
AW		 4054 for_each_active_iommu(iommu, drhd)
4055 iommu->iommu_dev = iommu_device_create(NULL, iommu,
4056 intel_iommu_groups,
4057 iommu->name);
4058
4236d97d 4059 bus_set_iommu(&pci_bus_type, &intel_iommu_ops);
99dcaded 4060 bus_register_notifier(&pci_bus_type, &device_nb);
75f05569
JL		 4061 if (si_domain && !hw_pass_through)
4062 register_memory_notifier(&intel_iommu_memory_nb);
99dcaded 4063
8bc1f85c
ED		 4064 intel_iommu_enabled = 1;
4065
ba395927 4066 return 0;
9bdc531e
JL		 4067
4068out_free_reserved_range:
4069 put_iova_domain(&reserved_iova_list);
9bdc531e
JL		 4070out_free_dmar:
4071 intel_iommu_free_dmars();
3a5670e8
JL		 4072 up_write(&dmar_global_lock);
4073 iommu_exit_mempool();
9bdc531e 4074 return ret;
ba395927 4075}
e820482c 4076
579305f7
AW		 4077static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque)
4078{
4079 struct intel_iommu *iommu = opaque;
4080
4081 iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff);
4082 return 0;
4083}
4084
4085/*
4086 * NB - intel-iommu lacks any sort of reference counting for the users of
4087 * dependent devices. If multiple endpoints have intersecting dependent
4088 * devices, unbinding the driver from any one of them will possibly leave
4089 * the others unable to operate.
4090 */
3199aa6b 4091static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
0bcb3e28 4092 struct device *dev)
3199aa6b 4093{
0bcb3e28 4094 if (!iommu || !dev || !dev_is_pci(dev))
3199aa6b
HW		 4095 return;
4096
579305f7 4097 pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu);
3199aa6b
HW		 4098}
4099
2c2e2c38 4100static void domain_remove_one_dev_info(struct dmar_domain *domain,
bf9c9eda 4101 struct device *dev)
c7151a8d 4102{
bca2b916 4103 struct device_domain_info *info, *tmp;
c7151a8d
WH		 4104 struct intel_iommu *iommu;
4105 unsigned long flags;
4106 int found = 0;
156baca8 4107 u8 bus, devfn;
c7151a8d 4108
bf9c9eda 4109 iommu = device_to_iommu(dev, &bus, &devfn);
c7151a8d
WH		 4110 if (!iommu)
4111 return;
4112
4113 spin_lock_irqsave(&device_domain_lock, flags);
bca2b916 4114 list_for_each_entry_safe(info, tmp, &domain->devices, link) {
bf9c9eda
DW		 4115 if (info->iommu == iommu && info->bus == bus &&
4116 info->devfn == devfn) {
109b9b04 4117 unlink_domain_info(info);
c7151a8d
WH		 4118 spin_unlock_irqrestore(&device_domain_lock, flags);
4119
93a23a72 4120 iommu_disable_dev_iotlb(info);
c7151a8d 4121 iommu_detach_dev(iommu, info->bus, info->devfn);
bf9c9eda 4122 iommu_detach_dependent_devices(iommu, dev);
c7151a8d
WH		 4123 free_devinfo_mem(info);
4124
4125 spin_lock_irqsave(&device_domain_lock, flags);
4126
4127 if (found)
4128 break;
4129 else
4130 continue;
4131 }
4132
4133 /* if there is no other devices under the same iommu
4134 * owned by this domain, clear this iommu in iommu_bmp
4135 * update iommu count and coherency
4136 */
8bbc4410 4137 if (info->iommu == iommu)
c7151a8d
WH		 4138 found = 1;
4139 }
4140
3e7abe25
RD		 4141 spin_unlock_irqrestore(&device_domain_lock, flags);
4142
c7151a8d 4143 if (found == 0) {
fb170fb4
JL		 4144 domain_detach_iommu(domain, iommu);
4145 if (!domain_type_is_vm_or_si(domain))
4146 iommu_detach_domain(domain, iommu);
c7151a8d 4147 }
c7151a8d
WH		 4148}
4149
2c2e2c38 4150static int md_domain_init(struct dmar_domain *domain, int guest_width)
5e98c4b1
WH		 4151{
4152 int adjust_width;
4153
4154 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
5e98c4b1
WH		 4155 domain_reserve_special_ranges(domain);
4156
4157 /* calculate AGAW */
4158 domain->gaw = guest_width;
4159 adjust_width = guestwidth_to_adjustwidth(guest_width);
4160 domain->agaw = width_to_agaw(adjust_width);
4161
5e98c4b1 4162 domain->iommu_coherency = 0;
c5b15255 4163 domain->iommu_snooping = 0;
6dd9a7c7 4164 domain->iommu_superpage = 0;
fe40f1e0 4165 domain->max_addr = 0;
5e98c4b1
WH		 4166
4167 /* always allocate the top pgd */
4c923d47 4168 domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid);
5e98c4b1
WH		 4169 if (!domain->pgd)
4170 return -ENOMEM;
4171 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
4172 return 0;
4173}
4174
5d450806 4175static int intel_iommu_domain_init(struct iommu_domain *domain)
38717946 4176{
5d450806 4177 struct dmar_domain *dmar_domain;
38717946 4178
ab8dfe25 4179 dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE);
5d450806 4180 if (!dmar_domain) {
38717946 4181 printk(KERN_ERR
5d450806
JR		 4182 "intel_iommu_domain_init: dmar_domain == NULL\n");
4183 return -ENOMEM;
38717946 4184 }
2c2e2c38 4185 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
38717946 4186 printk(KERN_ERR
5d450806 4187 "intel_iommu_domain_init() failed\n");
92d03cc8 4188 domain_exit(dmar_domain);
5d450806 4189 return -ENOMEM;
38717946 4190 }
8140a95d 4191 domain_update_iommu_cap(dmar_domain);
5d450806 4192 domain->priv = dmar_domain;
faa3d6f5 4193
8a0e715b
JR		 4194 domain->geometry.aperture_start = 0;
4195 domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw);
4196 domain->geometry.force_aperture = true;
4197
5d450806 4198 return 0;
38717946 4199}
38717946 4200
5d450806 4201static void intel_iommu_domain_destroy(struct iommu_domain *domain)
38717946 4202{
5d450806
JR		 4203 struct dmar_domain *dmar_domain = domain->priv;
4204
4205 domain->priv = NULL;
92d03cc8 4206 domain_exit(dmar_domain);
38717946 4207}
38717946 4208
4c5478c9
JR		 4209static int intel_iommu_attach_device(struct iommu_domain *domain,
4210 struct device *dev)
38717946 4211{
4c5478c9 4212 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0
WH		 4213 struct intel_iommu *iommu;
4214 int addr_width;
156baca8 4215 u8 bus, devfn;
faa3d6f5 4216
7207d8f9
DW		 4217 /* normally dev is not mapped */
4218 if (unlikely(domain_context_mapped(dev))) {
faa3d6f5
WH		 4219 struct dmar_domain *old_domain;
4220
1525a29a 4221 old_domain = find_domain(dev);
faa3d6f5 4222 if (old_domain) {
ab8dfe25 4223 if (domain_type_is_vm_or_si(dmar_domain))
bf9c9eda 4224 domain_remove_one_dev_info(old_domain, dev);
faa3d6f5
WH		 4225 else
4226 domain_remove_dev_info(old_domain);
4227 }
4228 }
4229
156baca8 4230 iommu = device_to_iommu(dev, &bus, &devfn);
fe40f1e0
WH		 4231 if (!iommu)
4232 return -ENODEV;
4233
4234 /* check if this iommu agaw is sufficient for max mapped address */
4235 addr_width = agaw_to_width(iommu->agaw);
a99c47a2
TL		 4236 if (addr_width > cap_mgaw(iommu->cap))
4237 addr_width = cap_mgaw(iommu->cap);
4238
4239 if (dmar_domain->max_addr > (1LL << addr_width)) {
4240 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4241 "sufficient for the mapped address (%llx)\n",
a99c47a2 4242 __func__, addr_width, dmar_domain->max_addr);
fe40f1e0
WH		 4243 return -EFAULT;
4244 }
a99c47a2
TL		 4245 dmar_domain->gaw = addr_width;
4246
4247 /*
4248 * Knock out extra levels of page tables if necessary
4249 */
4250 while (iommu->agaw < dmar_domain->agaw) {
4251 struct dma_pte *pte;
4252
4253 pte = dmar_domain->pgd;
4254 if (dma_pte_present(pte)) {
25cbff16
SY		 4255 dmar_domain->pgd = (struct dma_pte *)
4256 phys_to_virt(dma_pte_addr(pte));
7a661013 4257 free_pgtable_page(pte);
a99c47a2
TL		 4258 }
4259 dmar_domain->agaw--;
4260 }
fe40f1e0 4261
5913c9bf 4262 return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL);
38717946 4263}
38717946 4264
4c5478c9
JR		 4265static void intel_iommu_detach_device(struct iommu_domain *domain,
4266 struct device *dev)
38717946 4267{
4c5478c9 4268 struct dmar_domain *dmar_domain = domain->priv;
4c5478c9 4269
bf9c9eda 4270 domain_remove_one_dev_info(dmar_domain, dev);
faa3d6f5 4271}
c7151a8d 4272
b146a1c9
JR		 4273static int intel_iommu_map(struct iommu_domain *domain,
4274 unsigned long iova, phys_addr_t hpa,
5009065d 4275 size_t size, int iommu_prot)
faa3d6f5 4276{
dde57a21 4277 struct dmar_domain *dmar_domain = domain->priv;
fe40f1e0 4278 u64 max_addr;
dde57a21 4279 int prot = 0;
faa3d6f5 4280 int ret;
fe40f1e0 4281
dde57a21
JR		 4282 if (iommu_prot & IOMMU_READ)
4283 prot |= DMA_PTE_READ;
4284 if (iommu_prot & IOMMU_WRITE)
4285 prot |= DMA_PTE_WRITE;
9cf06697
SY		 4286 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
4287 prot |= DMA_PTE_SNP;
dde57a21 4288
163cc52c 4289 max_addr = iova + size;
dde57a21 4290 if (dmar_domain->max_addr < max_addr) {
fe40f1e0
WH		 4291 u64 end;
4292
4293 /* check if minimum agaw is sufficient for mapped address */
8954da1f 4294 end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1;
fe40f1e0 4295 if (end < max_addr) {
8954da1f 4296 printk(KERN_ERR "%s: iommu width (%d) is not "
fe40f1e0 4297 "sufficient for the mapped address (%llx)\n",
8954da1f 4298 __func__, dmar_domain->gaw, max_addr);
fe40f1e0
WH		 4299 return -EFAULT;
4300 }
dde57a21 4301 dmar_domain->max_addr = max_addr;
fe40f1e0 4302 }
ad051221
DW		 4303 /* Round up size to next multiple of PAGE_SIZE, if it and
4304 the low bits of hpa would take us onto the next page */
88cb6a74 4305 size = aligned_nrpages(hpa, size);
ad051221
DW		 4306 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
4307 hpa >> VTD_PAGE_SHIFT, size, prot);
faa3d6f5 4308 return ret;
38717946 4309}
38717946 4310
5009065d 4311static size_t intel_iommu_unmap(struct iommu_domain *domain,
ea8ea460 4312 unsigned long iova, size_t size)
38717946 4313{
dde57a21 4314 struct dmar_domain *dmar_domain = domain->priv;
ea8ea460
DW		 4315 struct page *freelist = NULL;
4316 struct intel_iommu *iommu;
4317 unsigned long start_pfn, last_pfn;
4318 unsigned int npages;
4319 int iommu_id, num, ndomains, level = 0;
5cf0a76f
DW		 4320
4321 /* Cope with horrid API which requires us to unmap more than the
4322 size argument if it happens to be a large-page mapping. */
4323 if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level))
4324 BUG();
4325
4326 if (size < VTD_PAGE_SIZE << level_to_offset_bits(level))
4327 size = VTD_PAGE_SIZE << level_to_offset_bits(level);
4b99d352 4328
ea8ea460
DW		 4329 start_pfn = iova >> VTD_PAGE_SHIFT;
4330 last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT;
4331
4332 freelist = domain_unmap(dmar_domain, start_pfn, last_pfn);
4333
4334 npages = last_pfn - start_pfn + 1;
4335
4336 for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) {
4337 iommu = g_iommus[iommu_id];
4338
4339 /*
4340 * find bit position of dmar_domain
4341 */
4342 ndomains = cap_ndoms(iommu->cap);
4343 for_each_set_bit(num, iommu->domain_ids, ndomains) {
4344 if (iommu->domains[num] == dmar_domain)
4345 iommu_flush_iotlb_psi(iommu, num, start_pfn,
4346 npages, !freelist, 0);
4347 }
4348
4349 }
4350
4351 dma_free_pagelist(freelist);
fe40f1e0 4352
163cc52c
DW		 4353 if (dmar_domain->max_addr == iova + size)
4354 dmar_domain->max_addr = iova;
b146a1c9 4355
5cf0a76f 4356 return size;
38717946 4357}
38717946 4358
d14d6577 4359static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
bb5547ac 4360 dma_addr_t iova)
38717946 4361{
d14d6577 4362 struct dmar_domain *dmar_domain = domain->priv;
38717946 4363 struct dma_pte *pte;
5cf0a76f 4364 int level = 0;
faa3d6f5 4365 u64 phys = 0;
38717946 4366
5cf0a76f 4367 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level);
38717946 4368 if (pte)
faa3d6f5 4369 phys = dma_pte_addr(pte);
38717946 4370
faa3d6f5 4371 return phys;
38717946 4372}
a8bcbb0d 4373
dbb9fd86
SY		 4374static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
4375 unsigned long cap)
4376{
4377 struct dmar_domain *dmar_domain = domain->priv;
4378
4379 if (cap == IOMMU_CAP_CACHE_COHERENCY)
4380 return dmar_domain->iommu_snooping;
323f99cb 4381 if (cap == IOMMU_CAP_INTR_REMAP)
95a02e97 4382 return irq_remapping_enabled;
dbb9fd86
SY		 4383
4384 return 0;
4385}
4386
abdfdde2
AW		 4387static int intel_iommu_add_device(struct device *dev)
4388{
a5459cfe 4389 struct intel_iommu *iommu;
abdfdde2 4390 struct iommu_group *group;
156baca8 4391 u8 bus, devfn;
70ae6f0d 4392
a5459cfe
AW		 4393 iommu = device_to_iommu(dev, &bus, &devfn);
4394 if (!iommu)
70ae6f0d
AW		 4395 return -ENODEV;
4396
a5459cfe 4397 iommu_device_link(iommu->iommu_dev, dev);
a4ff1fc2 4398
e17f9ff4 4399 group = iommu_group_get_for_dev(dev);
783f157b 4400
e17f9ff4
AW		 4401 if (IS_ERR(group))
4402 return PTR_ERR(group);
bcb71abe 4403
abdfdde2 4404 iommu_group_put(group);
e17f9ff4 4405 return 0;
abdfdde2 4406}
70ae6f0d 4407
abdfdde2
AW		 4408static void intel_iommu_remove_device(struct device *dev)
4409{
a5459cfe
AW		 4410 struct intel_iommu *iommu;
4411 u8 bus, devfn;
4412
4413 iommu = device_to_iommu(dev, &bus, &devfn);
4414 if (!iommu)
4415 return;
4416
abdfdde2 4417 iommu_group_remove_device(dev);
a5459cfe
AW		 4418
4419 iommu_device_unlink(iommu->iommu_dev, dev);
70ae6f0d
AW		 4420}
4421
b22f6434 4422static const struct iommu_ops intel_iommu_ops = {
a8bcbb0d
JR		 4423 .domain_init = intel_iommu_domain_init,
4424 .domain_destroy = intel_iommu_domain_destroy,
4425 .attach_dev = intel_iommu_attach_device,
4426 .detach_dev = intel_iommu_detach_device,
b146a1c9
JR		 4427 .map = intel_iommu_map,
4428 .unmap = intel_iommu_unmap,
a8bcbb0d 4429 .iova_to_phys = intel_iommu_iova_to_phys,
dbb9fd86 4430 .domain_has_cap = intel_iommu_domain_has_cap,
abdfdde2
AW		 4431 .add_device = intel_iommu_add_device,
4432 .remove_device = intel_iommu_remove_device,
6d1c56a9 4433 .pgsize_bitmap = INTEL_IOMMU_PGSIZES,
a8bcbb0d 4434};
9af88143 4435
9452618e
DV		 4436static void quirk_iommu_g4x_gfx(struct pci_dev *dev)
4437{
4438 /* G4x/GM45 integrated gfx dmar support is totally busted. */
4439 printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
4440 dmar_map_gfx = 0;
4441}
4442
4443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
4444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
4445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
4446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
4447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
4448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
4449DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
4450
d34d6517 4451static void quirk_iommu_rwbf(struct pci_dev *dev)
9af88143
DW		 4452{
4453 /*
4454 * Mobile 4 Series Chipset neglects to set RWBF capability,
210561ff 4455 * but needs it. Same seems to hold for the desktop versions.
9af88143
DW		 4456 */
4457 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
4458 rwbf_quirk = 1;
4459}
4460
4461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
210561ff
DV		 4462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
4463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
4464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
4465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
4466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
4467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
e0fc7e0b 4468
eecfd57f
AJ		 4469#define GGC 0x52
4470#define GGC_MEMORY_SIZE_MASK (0xf << 8)
4471#define GGC_MEMORY_SIZE_NONE (0x0 << 8)
4472#define GGC_MEMORY_SIZE_1M (0x1 << 8)
4473#define GGC_MEMORY_SIZE_2M (0x3 << 8)
4474#define GGC_MEMORY_VT_ENABLED (0x8 << 8)
4475#define GGC_MEMORY_SIZE_2M_VT (0x9 << 8)
4476#define GGC_MEMORY_SIZE_3M_VT (0xa << 8)
4477#define GGC_MEMORY_SIZE_4M_VT (0xb << 8)
4478
d34d6517 4479static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev)
9eecabcb
DW		 4480{
4481 unsigned short ggc;
4482
eecfd57f 4483 if (pci_read_config_word(dev, GGC, &ggc))
9eecabcb
DW		 4484 return;
4485
eecfd57f 4486 if (!(ggc & GGC_MEMORY_VT_ENABLED)) {
9eecabcb
DW		 4487 printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n");
4488 dmar_map_gfx = 0;
6fbcfb3e
DW		 4489 } else if (dmar_map_gfx) {
4490 /* we have to ensure the gfx device is idle before we flush */
4491 printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n");
4492 intel_iommu_strict = 1;
4493 }
9eecabcb
DW		 4494}
4495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt);
4496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt);
4497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt);
4498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt);
4499
e0fc7e0b
DW		 4500/* On Tylersburg chipsets, some BIOSes have been known to enable the
4501 ISOCH DMAR unit for the Azalia sound device, but not give it any
4502 TLB entries, which causes it to deadlock. Check for that. We do
4503 this in a function called from init_dmars(), instead of in a PCI
4504 quirk, because we don't want to print the obnoxious "BIOS broken"
4505 message if VT-d is actually disabled.
4506*/
4507static void __init check_tylersburg_isoch(void)
4508{
4509 struct pci_dev *pdev;
4510 uint32_t vtisochctrl;
4511
4512 /* If there's no Azalia in the system anyway, forget it. */
4513 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL);
4514 if (!pdev)
4515 return;
4516 pci_dev_put(pdev);
4517
4518 /* System Management Registers. Might be hidden, in which case
4519 we can't do the sanity check. But that's OK, because the
4520 known-broken BIOSes _don't_ actually hide it, so far. */
4521 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL);
4522 if (!pdev)
4523 return;
4524
4525 if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) {
4526 pci_dev_put(pdev);
4527 return;
4528 }
4529
4530 pci_dev_put(pdev);
4531
4532 /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */
4533 if (vtisochctrl & 1)
4534 return;
4535
4536 /* Drop all bits other than the number of TLB entries */
4537 vtisochctrl &= 0x1c;
4538
4539 /* If we have the recommended number of TLB entries (16), fine. */
4540 if (vtisochctrl == 0x10)
4541 return;
4542
4543 /* Zero TLB entries? You get to ride the short bus to school. */
4544 if (!vtisochctrl) {
4545 WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n"
4546 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
4547 dmi_get_system_info(DMI_BIOS_VENDOR),
4548 dmi_get_system_info(DMI_BIOS_VERSION),
4549 dmi_get_system_info(DMI_PRODUCT_VERSION));
4550 iommu_identity_mapping |= IDENTMAP_AZALIA;
4551 return;
4552 }
4553
4554 printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n",
4555 vtisochctrl);
4556}
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