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ba395927 | 1 | /* |
ea8ea460 | 2 | * Copyright © 2006-2014 Intel Corporation. |
ba395927 KA |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
ea8ea460 DW |
13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
14 | * Ashok Raj <ashok.raj@intel.com>, | |
15 | * Shaohua Li <shaohua.li@intel.com>, | |
16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, | |
17 | * Fenghua Yu <fenghua.yu@intel.com> | |
ba395927 KA |
18 | */ |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/bitmap.h> | |
5e0d2a6f | 22 | #include <linux/debugfs.h> |
54485c30 | 23 | #include <linux/export.h> |
ba395927 KA |
24 | #include <linux/slab.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/interrupt.h> | |
ba395927 KA |
27 | #include <linux/spinlock.h> |
28 | #include <linux/pci.h> | |
29 | #include <linux/dmar.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/mempool.h> | |
75f05569 | 32 | #include <linux/memory.h> |
5e0d2a6f | 33 | #include <linux/timer.h> |
38717946 | 34 | #include <linux/iova.h> |
5d450806 | 35 | #include <linux/iommu.h> |
38717946 | 36 | #include <linux/intel-iommu.h> |
134fac3f | 37 | #include <linux/syscore_ops.h> |
69575d38 | 38 | #include <linux/tboot.h> |
adb2fe02 | 39 | #include <linux/dmi.h> |
5cdede24 | 40 | #include <linux/pci-ats.h> |
0ee332c1 | 41 | #include <linux/memblock.h> |
8a8f422d | 42 | #include <asm/irq_remapping.h> |
ba395927 | 43 | #include <asm/cacheflush.h> |
46a7fa27 | 44 | #include <asm/iommu.h> |
ba395927 | 45 | |
078e1ee2 | 46 | #include "irq_remapping.h" |
61e015ac | 47 | #include "pci.h" |
078e1ee2 | 48 | |
5b6985ce FY |
49 | #define ROOT_SIZE VTD_PAGE_SIZE |
50 | #define CONTEXT_SIZE VTD_PAGE_SIZE | |
51 | ||
ba395927 KA |
52 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
53 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) | |
e0fc7e0b | 54 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
ba395927 KA |
55 | |
56 | #define IOAPIC_RANGE_START (0xfee00000) | |
57 | #define IOAPIC_RANGE_END (0xfeefffff) | |
58 | #define IOVA_START_ADDR (0x1000) | |
59 | ||
60 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 | |
61 | ||
4ed0d3e6 | 62 | #define MAX_AGAW_WIDTH 64 |
5c645b35 | 63 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
4ed0d3e6 | 64 | |
2ebe3151 DW |
65 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
66 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) | |
67 | ||
68 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR | |
69 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ | |
70 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ | |
71 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) | |
72 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) | |
ba395927 | 73 | |
f27be03b | 74 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
284901a9 | 75 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
6a35528a | 76 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
5e0d2a6f | 77 | |
df08cdc7 AM |
78 | /* page table handling */ |
79 | #define LEVEL_STRIDE (9) | |
80 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) | |
81 | ||
6d1c56a9 OBC |
82 | /* |
83 | * This bitmap is used to advertise the page sizes our hardware support | |
84 | * to the IOMMU core, which will then use this information to split | |
85 | * physically contiguous memory regions it is mapping into page sizes | |
86 | * that we support. | |
87 | * | |
88 | * Traditionally the IOMMU core just handed us the mappings directly, | |
89 | * after making sure the size is an order of a 4KiB page and that the | |
90 | * mapping has natural alignment. | |
91 | * | |
92 | * To retain this behavior, we currently advertise that we support | |
93 | * all page sizes that are an order of 4KiB. | |
94 | * | |
95 | * If at some point we'd like to utilize the IOMMU core's new behavior, | |
96 | * we could change this to advertise the real page sizes we support. | |
97 | */ | |
98 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) | |
99 | ||
df08cdc7 AM |
100 | static inline int agaw_to_level(int agaw) |
101 | { | |
102 | return agaw + 2; | |
103 | } | |
104 | ||
105 | static inline int agaw_to_width(int agaw) | |
106 | { | |
5c645b35 | 107 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
df08cdc7 AM |
108 | } |
109 | ||
110 | static inline int width_to_agaw(int width) | |
111 | { | |
5c645b35 | 112 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
df08cdc7 AM |
113 | } |
114 | ||
115 | static inline unsigned int level_to_offset_bits(int level) | |
116 | { | |
117 | return (level - 1) * LEVEL_STRIDE; | |
118 | } | |
119 | ||
120 | static inline int pfn_level_offset(unsigned long pfn, int level) | |
121 | { | |
122 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; | |
123 | } | |
124 | ||
125 | static inline unsigned long level_mask(int level) | |
126 | { | |
127 | return -1UL << level_to_offset_bits(level); | |
128 | } | |
129 | ||
130 | static inline unsigned long level_size(int level) | |
131 | { | |
132 | return 1UL << level_to_offset_bits(level); | |
133 | } | |
134 | ||
135 | static inline unsigned long align_to_level(unsigned long pfn, int level) | |
136 | { | |
137 | return (pfn + level_size(level) - 1) & level_mask(level); | |
138 | } | |
fd18de50 | 139 | |
6dd9a7c7 YS |
140 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
141 | { | |
5c645b35 | 142 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
6dd9a7c7 YS |
143 | } |
144 | ||
dd4e8319 DW |
145 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
146 | are never going to work. */ | |
147 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) | |
148 | { | |
149 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
150 | } | |
151 | ||
152 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) | |
153 | { | |
154 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); | |
155 | } | |
156 | static inline unsigned long page_to_dma_pfn(struct page *pg) | |
157 | { | |
158 | return mm_to_dma_pfn(page_to_pfn(pg)); | |
159 | } | |
160 | static inline unsigned long virt_to_dma_pfn(void *p) | |
161 | { | |
162 | return page_to_dma_pfn(virt_to_page(p)); | |
163 | } | |
164 | ||
d9630fe9 WH |
165 | /* global iommu list, set NULL for ignored DMAR units */ |
166 | static struct intel_iommu **g_iommus; | |
167 | ||
e0fc7e0b | 168 | static void __init check_tylersburg_isoch(void); |
9af88143 DW |
169 | static int rwbf_quirk; |
170 | ||
b779260b JC |
171 | /* |
172 | * set to 1 to panic kernel if can't successfully enable VT-d | |
173 | * (used when kernel is launched w/ TXT) | |
174 | */ | |
175 | static int force_on = 0; | |
176 | ||
46b08e1a MM |
177 | /* |
178 | * 0: Present | |
179 | * 1-11: Reserved | |
180 | * 12-63: Context Ptr (12 - (haw-1)) | |
181 | * 64-127: Reserved | |
182 | */ | |
183 | struct root_entry { | |
184 | u64 val; | |
185 | u64 rsvd1; | |
186 | }; | |
187 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) | |
188 | static inline bool root_present(struct root_entry *root) | |
189 | { | |
190 | return (root->val & 1); | |
191 | } | |
192 | static inline void set_root_present(struct root_entry *root) | |
193 | { | |
194 | root->val |= 1; | |
195 | } | |
196 | static inline void set_root_value(struct root_entry *root, unsigned long value) | |
197 | { | |
198 | root->val |= value & VTD_PAGE_MASK; | |
199 | } | |
200 | ||
201 | static inline struct context_entry * | |
202 | get_context_addr_from_root(struct root_entry *root) | |
203 | { | |
204 | return (struct context_entry *) | |
205 | (root_present(root)?phys_to_virt( | |
206 | root->val & VTD_PAGE_MASK) : | |
207 | NULL); | |
208 | } | |
209 | ||
7a8fc25e MM |
210 | /* |
211 | * low 64 bits: | |
212 | * 0: present | |
213 | * 1: fault processing disable | |
214 | * 2-3: translation type | |
215 | * 12-63: address space root | |
216 | * high 64 bits: | |
217 | * 0-2: address width | |
218 | * 3-6: aval | |
219 | * 8-23: domain id | |
220 | */ | |
221 | struct context_entry { | |
222 | u64 lo; | |
223 | u64 hi; | |
224 | }; | |
c07e7d21 MM |
225 | |
226 | static inline bool context_present(struct context_entry *context) | |
227 | { | |
228 | return (context->lo & 1); | |
229 | } | |
230 | static inline void context_set_present(struct context_entry *context) | |
231 | { | |
232 | context->lo |= 1; | |
233 | } | |
234 | ||
235 | static inline void context_set_fault_enable(struct context_entry *context) | |
236 | { | |
237 | context->lo &= (((u64)-1) << 2) | 1; | |
238 | } | |
239 | ||
c07e7d21 MM |
240 | static inline void context_set_translation_type(struct context_entry *context, |
241 | unsigned long value) | |
242 | { | |
243 | context->lo &= (((u64)-1) << 4) | 3; | |
244 | context->lo |= (value & 3) << 2; | |
245 | } | |
246 | ||
247 | static inline void context_set_address_root(struct context_entry *context, | |
248 | unsigned long value) | |
249 | { | |
250 | context->lo |= value & VTD_PAGE_MASK; | |
251 | } | |
252 | ||
253 | static inline void context_set_address_width(struct context_entry *context, | |
254 | unsigned long value) | |
255 | { | |
256 | context->hi |= value & 7; | |
257 | } | |
258 | ||
259 | static inline void context_set_domain_id(struct context_entry *context, | |
260 | unsigned long value) | |
261 | { | |
262 | context->hi |= (value & ((1 << 16) - 1)) << 8; | |
263 | } | |
264 | ||
265 | static inline void context_clear_entry(struct context_entry *context) | |
266 | { | |
267 | context->lo = 0; | |
268 | context->hi = 0; | |
269 | } | |
7a8fc25e | 270 | |
622ba12a MM |
271 | /* |
272 | * 0: readable | |
273 | * 1: writable | |
274 | * 2-6: reserved | |
275 | * 7: super page | |
9cf06697 SY |
276 | * 8-10: available |
277 | * 11: snoop behavior | |
622ba12a MM |
278 | * 12-63: Host physcial address |
279 | */ | |
280 | struct dma_pte { | |
281 | u64 val; | |
282 | }; | |
622ba12a | 283 | |
19c239ce MM |
284 | static inline void dma_clear_pte(struct dma_pte *pte) |
285 | { | |
286 | pte->val = 0; | |
287 | } | |
288 | ||
19c239ce MM |
289 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
290 | { | |
c85994e4 DW |
291 | #ifdef CONFIG_64BIT |
292 | return pte->val & VTD_PAGE_MASK; | |
293 | #else | |
294 | /* Must have a full atomic 64-bit read */ | |
1a8bd481 | 295 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
c85994e4 | 296 | #endif |
19c239ce MM |
297 | } |
298 | ||
19c239ce MM |
299 | static inline bool dma_pte_present(struct dma_pte *pte) |
300 | { | |
301 | return (pte->val & 3) != 0; | |
302 | } | |
622ba12a | 303 | |
4399c8bf AK |
304 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
305 | { | |
306 | return (pte->val & (1 << 7)); | |
307 | } | |
308 | ||
75e6bf96 DW |
309 | static inline int first_pte_in_page(struct dma_pte *pte) |
310 | { | |
311 | return !((unsigned long)pte & ~VTD_PAGE_MASK); | |
312 | } | |
313 | ||
2c2e2c38 FY |
314 | /* |
315 | * This domain is a statically identity mapping domain. | |
316 | * 1. This domain creats a static 1:1 mapping to all usable memory. | |
317 | * 2. It maps to each iommu if successful. | |
318 | * 3. Each iommu mapps to this domain if successful. | |
319 | */ | |
19943b0e DW |
320 | static struct dmar_domain *si_domain; |
321 | static int hw_pass_through = 1; | |
2c2e2c38 | 322 | |
3b5410e7 | 323 | /* devices under the same p2p bridge are owned in one domain */ |
cdc7b837 | 324 | #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0) |
3b5410e7 | 325 | |
1ce28feb WH |
326 | /* domain represents a virtual machine, more than one devices |
327 | * across iommus may be owned in one domain, e.g. kvm guest. | |
328 | */ | |
329 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1) | |
330 | ||
2c2e2c38 FY |
331 | /* si_domain contains mulitple devices */ |
332 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2) | |
333 | ||
1b198bb0 MT |
334 | /* define the limit of IOMMUs supported in each domain */ |
335 | #ifdef CONFIG_X86 | |
336 | # define IOMMU_UNITS_SUPPORTED MAX_IO_APICS | |
337 | #else | |
338 | # define IOMMU_UNITS_SUPPORTED 64 | |
339 | #endif | |
340 | ||
99126f7c MM |
341 | struct dmar_domain { |
342 | int id; /* domain id */ | |
4c923d47 | 343 | int nid; /* node id */ |
1b198bb0 MT |
344 | DECLARE_BITMAP(iommu_bmp, IOMMU_UNITS_SUPPORTED); |
345 | /* bitmap of iommus this domain uses*/ | |
99126f7c MM |
346 | |
347 | struct list_head devices; /* all devices' list */ | |
348 | struct iova_domain iovad; /* iova's that belong to this domain */ | |
349 | ||
350 | struct dma_pte *pgd; /* virtual address */ | |
99126f7c MM |
351 | int gaw; /* max guest address width */ |
352 | ||
353 | /* adjusted guest address width, 0 is level 2 30-bit */ | |
354 | int agaw; | |
355 | ||
3b5410e7 | 356 | int flags; /* flags to find out type of domain */ |
8e604097 WH |
357 | |
358 | int iommu_coherency;/* indicate coherency of iommu access */ | |
58c610bd | 359 | int iommu_snooping; /* indicate snooping control feature*/ |
c7151a8d | 360 | int iommu_count; /* reference count of iommu */ |
6dd9a7c7 YS |
361 | int iommu_superpage;/* Level of superpages supported: |
362 | 0 == 4KiB (no superpages), 1 == 2MiB, | |
363 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ | |
c7151a8d | 364 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
fe40f1e0 | 365 | u64 max_addr; /* maximum mapped address */ |
99126f7c MM |
366 | }; |
367 | ||
a647dacb MM |
368 | /* PCI domain-device relationship */ |
369 | struct device_domain_info { | |
370 | struct list_head link; /* link to domain siblings */ | |
371 | struct list_head global; /* link to global list */ | |
276dbf99 DW |
372 | int segment; /* PCI domain */ |
373 | u8 bus; /* PCI bus number */ | |
a647dacb | 374 | u8 devfn; /* PCI devfn number */ |
0bcb3e28 | 375 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
93a23a72 | 376 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
a647dacb MM |
377 | struct dmar_domain *domain; /* pointer to domain */ |
378 | }; | |
379 | ||
b94e4117 JL |
380 | struct dmar_rmrr_unit { |
381 | struct list_head list; /* list of rmrr units */ | |
382 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
383 | u64 base_address; /* reserved base address*/ | |
384 | u64 end_address; /* reserved end address */ | |
832bd858 | 385 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
386 | int devices_cnt; /* target device count */ |
387 | }; | |
388 | ||
389 | struct dmar_atsr_unit { | |
390 | struct list_head list; /* list of ATSR units */ | |
391 | struct acpi_dmar_header *hdr; /* ACPI header */ | |
832bd858 | 392 | struct dmar_dev_scope *devices; /* target devices */ |
b94e4117 JL |
393 | int devices_cnt; /* target device count */ |
394 | u8 include_all:1; /* include all ports */ | |
395 | }; | |
396 | ||
397 | static LIST_HEAD(dmar_atsr_units); | |
398 | static LIST_HEAD(dmar_rmrr_units); | |
399 | ||
400 | #define for_each_rmrr_units(rmrr) \ | |
401 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) | |
402 | ||
5e0d2a6f | 403 | static void flush_unmaps_timeout(unsigned long data); |
404 | ||
b707cb02 | 405 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
5e0d2a6f | 406 | |
80b20dd8 | 407 | #define HIGH_WATER_MARK 250 |
408 | struct deferred_flush_tables { | |
409 | int next; | |
410 | struct iova *iova[HIGH_WATER_MARK]; | |
411 | struct dmar_domain *domain[HIGH_WATER_MARK]; | |
ea8ea460 | 412 | struct page *freelist[HIGH_WATER_MARK]; |
80b20dd8 | 413 | }; |
414 | ||
415 | static struct deferred_flush_tables *deferred_flush; | |
416 | ||
5e0d2a6f | 417 | /* bitmap for indexing intel_iommus */ |
5e0d2a6f | 418 | static int g_num_of_iommus; |
419 | ||
420 | static DEFINE_SPINLOCK(async_umap_flush_lock); | |
421 | static LIST_HEAD(unmaps_to_do); | |
422 | ||
423 | static int timer_on; | |
424 | static long list_size; | |
5e0d2a6f | 425 | |
92d03cc8 | 426 | static void domain_exit(struct dmar_domain *domain); |
ba395927 | 427 | static void domain_remove_dev_info(struct dmar_domain *domain); |
b94e4117 JL |
428 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
429 | struct pci_dev *pdev); | |
92d03cc8 | 430 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 431 | struct device *dev); |
ba395927 | 432 | |
d3f13810 | 433 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
0cd5c3c8 KM |
434 | int dmar_disabled = 0; |
435 | #else | |
436 | int dmar_disabled = 1; | |
d3f13810 | 437 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
0cd5c3c8 | 438 | |
8bc1f85c ED |
439 | int intel_iommu_enabled = 0; |
440 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); | |
441 | ||
2d9e667e | 442 | static int dmar_map_gfx = 1; |
7d3b03ce | 443 | static int dmar_forcedac; |
5e0d2a6f | 444 | static int intel_iommu_strict; |
6dd9a7c7 | 445 | static int intel_iommu_superpage = 1; |
ba395927 | 446 | |
c0771df8 DW |
447 | int intel_iommu_gfx_mapped; |
448 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); | |
449 | ||
ba395927 KA |
450 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
451 | static DEFINE_SPINLOCK(device_domain_lock); | |
452 | static LIST_HEAD(device_domain_list); | |
453 | ||
a8bcbb0d JR |
454 | static struct iommu_ops intel_iommu_ops; |
455 | ||
ba395927 KA |
456 | static int __init intel_iommu_setup(char *str) |
457 | { | |
458 | if (!str) | |
459 | return -EINVAL; | |
460 | while (*str) { | |
0cd5c3c8 KM |
461 | if (!strncmp(str, "on", 2)) { |
462 | dmar_disabled = 0; | |
463 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); | |
464 | } else if (!strncmp(str, "off", 3)) { | |
ba395927 | 465 | dmar_disabled = 1; |
0cd5c3c8 | 466 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
ba395927 KA |
467 | } else if (!strncmp(str, "igfx_off", 8)) { |
468 | dmar_map_gfx = 0; | |
469 | printk(KERN_INFO | |
470 | "Intel-IOMMU: disable GFX device mapping\n"); | |
7d3b03ce | 471 | } else if (!strncmp(str, "forcedac", 8)) { |
5e0d2a6f | 472 | printk(KERN_INFO |
7d3b03ce KA |
473 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
474 | dmar_forcedac = 1; | |
5e0d2a6f | 475 | } else if (!strncmp(str, "strict", 6)) { |
476 | printk(KERN_INFO | |
477 | "Intel-IOMMU: disable batched IOTLB flush\n"); | |
478 | intel_iommu_strict = 1; | |
6dd9a7c7 YS |
479 | } else if (!strncmp(str, "sp_off", 6)) { |
480 | printk(KERN_INFO | |
481 | "Intel-IOMMU: disable supported super page\n"); | |
482 | intel_iommu_superpage = 0; | |
ba395927 KA |
483 | } |
484 | ||
485 | str += strcspn(str, ","); | |
486 | while (*str == ',') | |
487 | str++; | |
488 | } | |
489 | return 0; | |
490 | } | |
491 | __setup("intel_iommu=", intel_iommu_setup); | |
492 | ||
493 | static struct kmem_cache *iommu_domain_cache; | |
494 | static struct kmem_cache *iommu_devinfo_cache; | |
495 | static struct kmem_cache *iommu_iova_cache; | |
496 | ||
4c923d47 | 497 | static inline void *alloc_pgtable_page(int node) |
eb3fa7cb | 498 | { |
4c923d47 SS |
499 | struct page *page; |
500 | void *vaddr = NULL; | |
eb3fa7cb | 501 | |
4c923d47 SS |
502 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
503 | if (page) | |
504 | vaddr = page_address(page); | |
eb3fa7cb | 505 | return vaddr; |
ba395927 KA |
506 | } |
507 | ||
508 | static inline void free_pgtable_page(void *vaddr) | |
509 | { | |
510 | free_page((unsigned long)vaddr); | |
511 | } | |
512 | ||
513 | static inline void *alloc_domain_mem(void) | |
514 | { | |
354bb65e | 515 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
ba395927 KA |
516 | } |
517 | ||
38717946 | 518 | static void free_domain_mem(void *vaddr) |
ba395927 KA |
519 | { |
520 | kmem_cache_free(iommu_domain_cache, vaddr); | |
521 | } | |
522 | ||
523 | static inline void * alloc_devinfo_mem(void) | |
524 | { | |
354bb65e | 525 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
ba395927 KA |
526 | } |
527 | ||
528 | static inline void free_devinfo_mem(void *vaddr) | |
529 | { | |
530 | kmem_cache_free(iommu_devinfo_cache, vaddr); | |
531 | } | |
532 | ||
533 | struct iova *alloc_iova_mem(void) | |
534 | { | |
354bb65e | 535 | return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC); |
ba395927 KA |
536 | } |
537 | ||
538 | void free_iova_mem(struct iova *iova) | |
539 | { | |
540 | kmem_cache_free(iommu_iova_cache, iova); | |
541 | } | |
542 | ||
1b573683 | 543 | |
4ed0d3e6 | 544 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
1b573683 WH |
545 | { |
546 | unsigned long sagaw; | |
547 | int agaw = -1; | |
548 | ||
549 | sagaw = cap_sagaw(iommu->cap); | |
4ed0d3e6 | 550 | for (agaw = width_to_agaw(max_gaw); |
1b573683 WH |
551 | agaw >= 0; agaw--) { |
552 | if (test_bit(agaw, &sagaw)) | |
553 | break; | |
554 | } | |
555 | ||
556 | return agaw; | |
557 | } | |
558 | ||
4ed0d3e6 FY |
559 | /* |
560 | * Calculate max SAGAW for each iommu. | |
561 | */ | |
562 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) | |
563 | { | |
564 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); | |
565 | } | |
566 | ||
567 | /* | |
568 | * calculate agaw for each iommu. | |
569 | * "SAGAW" may be different across iommus, use a default agaw, and | |
570 | * get a supported less agaw for iommus that don't support the default agaw. | |
571 | */ | |
572 | int iommu_calculate_agaw(struct intel_iommu *iommu) | |
573 | { | |
574 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
575 | } | |
576 | ||
2c2e2c38 | 577 | /* This functionin only returns single iommu in a domain */ |
8c11e798 WH |
578 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
579 | { | |
580 | int iommu_id; | |
581 | ||
2c2e2c38 | 582 | /* si_domain and vm domain should not get here. */ |
1ce28feb | 583 | BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE); |
2c2e2c38 | 584 | BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY); |
1ce28feb | 585 | |
1b198bb0 | 586 | iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus); |
8c11e798 WH |
587 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
588 | return NULL; | |
589 | ||
590 | return g_iommus[iommu_id]; | |
591 | } | |
592 | ||
8e604097 WH |
593 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
594 | { | |
d0501960 DW |
595 | struct dmar_drhd_unit *drhd; |
596 | struct intel_iommu *iommu; | |
597 | int i, found = 0; | |
2e12bc29 | 598 | |
d0501960 | 599 | domain->iommu_coherency = 1; |
8e604097 | 600 | |
1b198bb0 | 601 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
d0501960 | 602 | found = 1; |
8e604097 WH |
603 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
604 | domain->iommu_coherency = 0; | |
605 | break; | |
606 | } | |
8e604097 | 607 | } |
d0501960 DW |
608 | if (found) |
609 | return; | |
610 | ||
611 | /* No hardware attached; use lowest common denominator */ | |
612 | rcu_read_lock(); | |
613 | for_each_active_iommu(iommu, drhd) { | |
614 | if (!ecap_coherent(iommu->ecap)) { | |
615 | domain->iommu_coherency = 0; | |
616 | break; | |
617 | } | |
618 | } | |
619 | rcu_read_unlock(); | |
8e604097 WH |
620 | } |
621 | ||
58c610bd SY |
622 | static void domain_update_iommu_snooping(struct dmar_domain *domain) |
623 | { | |
624 | int i; | |
625 | ||
626 | domain->iommu_snooping = 1; | |
627 | ||
1b198bb0 | 628 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
58c610bd SY |
629 | if (!ecap_sc_support(g_iommus[i]->ecap)) { |
630 | domain->iommu_snooping = 0; | |
631 | break; | |
632 | } | |
58c610bd SY |
633 | } |
634 | } | |
635 | ||
6dd9a7c7 YS |
636 | static void domain_update_iommu_superpage(struct dmar_domain *domain) |
637 | { | |
8140a95d AK |
638 | struct dmar_drhd_unit *drhd; |
639 | struct intel_iommu *iommu = NULL; | |
640 | int mask = 0xf; | |
6dd9a7c7 YS |
641 | |
642 | if (!intel_iommu_superpage) { | |
643 | domain->iommu_superpage = 0; | |
644 | return; | |
645 | } | |
646 | ||
8140a95d | 647 | /* set iommu_superpage to the smallest common denominator */ |
0e242612 | 648 | rcu_read_lock(); |
8140a95d AK |
649 | for_each_active_iommu(iommu, drhd) { |
650 | mask &= cap_super_page_val(iommu->cap); | |
6dd9a7c7 YS |
651 | if (!mask) { |
652 | break; | |
653 | } | |
654 | } | |
0e242612 JL |
655 | rcu_read_unlock(); |
656 | ||
6dd9a7c7 YS |
657 | domain->iommu_superpage = fls(mask); |
658 | } | |
659 | ||
58c610bd SY |
660 | /* Some capabilities may be different across iommus */ |
661 | static void domain_update_iommu_cap(struct dmar_domain *domain) | |
662 | { | |
663 | domain_update_iommu_coherency(domain); | |
664 | domain_update_iommu_snooping(domain); | |
6dd9a7c7 | 665 | domain_update_iommu_superpage(domain); |
58c610bd SY |
666 | } |
667 | ||
276dbf99 | 668 | static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn) |
c7151a8d WH |
669 | { |
670 | struct dmar_drhd_unit *drhd = NULL; | |
b683b230 | 671 | struct intel_iommu *iommu; |
832bd858 DW |
672 | struct device *dev; |
673 | struct pci_dev *pdev; | |
c7151a8d WH |
674 | int i; |
675 | ||
0e242612 | 676 | rcu_read_lock(); |
b683b230 | 677 | for_each_active_iommu(iommu, drhd) { |
276dbf99 DW |
678 | if (segment != drhd->segment) |
679 | continue; | |
c7151a8d | 680 | |
b683b230 JL |
681 | for_each_active_dev_scope(drhd->devices, |
682 | drhd->devices_cnt, i, dev) { | |
832bd858 DW |
683 | if (!dev_is_pci(dev)) |
684 | continue; | |
685 | pdev = to_pci_dev(dev); | |
686 | if (pdev->bus->number == bus && pdev->devfn == devfn) | |
b683b230 | 687 | goto out; |
832bd858 DW |
688 | if (pdev->subordinate && |
689 | pdev->subordinate->number <= bus && | |
690 | pdev->subordinate->busn_res.end >= bus) | |
b683b230 | 691 | goto out; |
924b6231 | 692 | } |
c7151a8d WH |
693 | |
694 | if (drhd->include_all) | |
b683b230 | 695 | goto out; |
c7151a8d | 696 | } |
b683b230 JL |
697 | iommu = NULL; |
698 | out: | |
0e242612 | 699 | rcu_read_unlock(); |
c7151a8d | 700 | |
b683b230 | 701 | return iommu; |
c7151a8d WH |
702 | } |
703 | ||
5331fe6f WH |
704 | static void domain_flush_cache(struct dmar_domain *domain, |
705 | void *addr, int size) | |
706 | { | |
707 | if (!domain->iommu_coherency) | |
708 | clflush_cache_range(addr, size); | |
709 | } | |
710 | ||
ba395927 KA |
711 | /* Gets context entry for a given bus and devfn */ |
712 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, | |
713 | u8 bus, u8 devfn) | |
714 | { | |
715 | struct root_entry *root; | |
716 | struct context_entry *context; | |
717 | unsigned long phy_addr; | |
718 | unsigned long flags; | |
719 | ||
720 | spin_lock_irqsave(&iommu->lock, flags); | |
721 | root = &iommu->root_entry[bus]; | |
722 | context = get_context_addr_from_root(root); | |
723 | if (!context) { | |
4c923d47 SS |
724 | context = (struct context_entry *) |
725 | alloc_pgtable_page(iommu->node); | |
ba395927 KA |
726 | if (!context) { |
727 | spin_unlock_irqrestore(&iommu->lock, flags); | |
728 | return NULL; | |
729 | } | |
5b6985ce | 730 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
ba395927 KA |
731 | phy_addr = virt_to_phys((void *)context); |
732 | set_root_value(root, phy_addr); | |
733 | set_root_present(root); | |
734 | __iommu_flush_cache(iommu, root, sizeof(*root)); | |
735 | } | |
736 | spin_unlock_irqrestore(&iommu->lock, flags); | |
737 | return &context[devfn]; | |
738 | } | |
739 | ||
740 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
741 | { | |
742 | struct root_entry *root; | |
743 | struct context_entry *context; | |
744 | int ret; | |
745 | unsigned long flags; | |
746 | ||
747 | spin_lock_irqsave(&iommu->lock, flags); | |
748 | root = &iommu->root_entry[bus]; | |
749 | context = get_context_addr_from_root(root); | |
750 | if (!context) { | |
751 | ret = 0; | |
752 | goto out; | |
753 | } | |
c07e7d21 | 754 | ret = context_present(&context[devfn]); |
ba395927 KA |
755 | out: |
756 | spin_unlock_irqrestore(&iommu->lock, flags); | |
757 | return ret; | |
758 | } | |
759 | ||
760 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) | |
761 | { | |
762 | struct root_entry *root; | |
763 | struct context_entry *context; | |
764 | unsigned long flags; | |
765 | ||
766 | spin_lock_irqsave(&iommu->lock, flags); | |
767 | root = &iommu->root_entry[bus]; | |
768 | context = get_context_addr_from_root(root); | |
769 | if (context) { | |
c07e7d21 | 770 | context_clear_entry(&context[devfn]); |
ba395927 KA |
771 | __iommu_flush_cache(iommu, &context[devfn], \ |
772 | sizeof(*context)); | |
773 | } | |
774 | spin_unlock_irqrestore(&iommu->lock, flags); | |
775 | } | |
776 | ||
777 | static void free_context_table(struct intel_iommu *iommu) | |
778 | { | |
779 | struct root_entry *root; | |
780 | int i; | |
781 | unsigned long flags; | |
782 | struct context_entry *context; | |
783 | ||
784 | spin_lock_irqsave(&iommu->lock, flags); | |
785 | if (!iommu->root_entry) { | |
786 | goto out; | |
787 | } | |
788 | for (i = 0; i < ROOT_ENTRY_NR; i++) { | |
789 | root = &iommu->root_entry[i]; | |
790 | context = get_context_addr_from_root(root); | |
791 | if (context) | |
792 | free_pgtable_page(context); | |
793 | } | |
794 | free_pgtable_page(iommu->root_entry); | |
795 | iommu->root_entry = NULL; | |
796 | out: | |
797 | spin_unlock_irqrestore(&iommu->lock, flags); | |
798 | } | |
799 | ||
b026fd28 | 800 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
5cf0a76f | 801 | unsigned long pfn, int *target_level) |
ba395927 | 802 | { |
b026fd28 | 803 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 KA |
804 | struct dma_pte *parent, *pte = NULL; |
805 | int level = agaw_to_level(domain->agaw); | |
4399c8bf | 806 | int offset; |
ba395927 KA |
807 | |
808 | BUG_ON(!domain->pgd); | |
f9423606 JS |
809 | |
810 | if (addr_width < BITS_PER_LONG && pfn >> addr_width) | |
811 | /* Address beyond IOMMU's addressing capabilities. */ | |
812 | return NULL; | |
813 | ||
ba395927 KA |
814 | parent = domain->pgd; |
815 | ||
5cf0a76f | 816 | while (1) { |
ba395927 KA |
817 | void *tmp_page; |
818 | ||
b026fd28 | 819 | offset = pfn_level_offset(pfn, level); |
ba395927 | 820 | pte = &parent[offset]; |
5cf0a76f | 821 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
6dd9a7c7 | 822 | break; |
5cf0a76f | 823 | if (level == *target_level) |
ba395927 KA |
824 | break; |
825 | ||
19c239ce | 826 | if (!dma_pte_present(pte)) { |
c85994e4 DW |
827 | uint64_t pteval; |
828 | ||
4c923d47 | 829 | tmp_page = alloc_pgtable_page(domain->nid); |
ba395927 | 830 | |
206a73c1 | 831 | if (!tmp_page) |
ba395927 | 832 | return NULL; |
206a73c1 | 833 | |
c85994e4 | 834 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
64de5af0 | 835 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
c85994e4 DW |
836 | if (cmpxchg64(&pte->val, 0ULL, pteval)) { |
837 | /* Someone else set it while we were thinking; use theirs. */ | |
838 | free_pgtable_page(tmp_page); | |
839 | } else { | |
840 | dma_pte_addr(pte); | |
841 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
842 | } | |
ba395927 | 843 | } |
5cf0a76f DW |
844 | if (level == 1) |
845 | break; | |
846 | ||
19c239ce | 847 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
848 | level--; |
849 | } | |
850 | ||
5cf0a76f DW |
851 | if (!*target_level) |
852 | *target_level = level; | |
853 | ||
ba395927 KA |
854 | return pte; |
855 | } | |
856 | ||
6dd9a7c7 | 857 | |
ba395927 | 858 | /* return address's pte at specific level */ |
90dcfb5e DW |
859 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
860 | unsigned long pfn, | |
6dd9a7c7 | 861 | int level, int *large_page) |
ba395927 KA |
862 | { |
863 | struct dma_pte *parent, *pte = NULL; | |
864 | int total = agaw_to_level(domain->agaw); | |
865 | int offset; | |
866 | ||
867 | parent = domain->pgd; | |
868 | while (level <= total) { | |
90dcfb5e | 869 | offset = pfn_level_offset(pfn, total); |
ba395927 KA |
870 | pte = &parent[offset]; |
871 | if (level == total) | |
872 | return pte; | |
873 | ||
6dd9a7c7 YS |
874 | if (!dma_pte_present(pte)) { |
875 | *large_page = total; | |
ba395927 | 876 | break; |
6dd9a7c7 YS |
877 | } |
878 | ||
879 | if (pte->val & DMA_PTE_LARGE_PAGE) { | |
880 | *large_page = total; | |
881 | return pte; | |
882 | } | |
883 | ||
19c239ce | 884 | parent = phys_to_virt(dma_pte_addr(pte)); |
ba395927 KA |
885 | total--; |
886 | } | |
887 | return NULL; | |
888 | } | |
889 | ||
ba395927 | 890 | /* clear last level pte, a tlb flush should be followed */ |
5cf0a76f | 891 | static void dma_pte_clear_range(struct dmar_domain *domain, |
595badf5 DW |
892 | unsigned long start_pfn, |
893 | unsigned long last_pfn) | |
ba395927 | 894 | { |
04b18e65 | 895 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
6dd9a7c7 | 896 | unsigned int large_page = 1; |
310a5ab9 | 897 | struct dma_pte *first_pte, *pte; |
66eae846 | 898 | |
04b18e65 | 899 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
595badf5 | 900 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); |
59c36286 | 901 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 902 | |
04b18e65 | 903 | /* we don't need lock here; nobody else touches the iova range */ |
59c36286 | 904 | do { |
6dd9a7c7 YS |
905 | large_page = 1; |
906 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); | |
310a5ab9 | 907 | if (!pte) { |
6dd9a7c7 | 908 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
310a5ab9 DW |
909 | continue; |
910 | } | |
6dd9a7c7 | 911 | do { |
310a5ab9 | 912 | dma_clear_pte(pte); |
6dd9a7c7 | 913 | start_pfn += lvl_to_nr_pages(large_page); |
310a5ab9 | 914 | pte++; |
75e6bf96 DW |
915 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
916 | ||
310a5ab9 DW |
917 | domain_flush_cache(domain, first_pte, |
918 | (void *)pte - (void *)first_pte); | |
59c36286 DW |
919 | |
920 | } while (start_pfn && start_pfn <= last_pfn); | |
ba395927 KA |
921 | } |
922 | ||
3269ee0b AW |
923 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
924 | struct dma_pte *pte, unsigned long pfn, | |
925 | unsigned long start_pfn, unsigned long last_pfn) | |
926 | { | |
927 | pfn = max(start_pfn, pfn); | |
928 | pte = &pte[pfn_level_offset(pfn, level)]; | |
929 | ||
930 | do { | |
931 | unsigned long level_pfn; | |
932 | struct dma_pte *level_pte; | |
933 | ||
934 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) | |
935 | goto next; | |
936 | ||
937 | level_pfn = pfn & level_mask(level - 1); | |
938 | level_pte = phys_to_virt(dma_pte_addr(pte)); | |
939 | ||
940 | if (level > 2) | |
941 | dma_pte_free_level(domain, level - 1, level_pte, | |
942 | level_pfn, start_pfn, last_pfn); | |
943 | ||
944 | /* If range covers entire pagetable, free it */ | |
945 | if (!(start_pfn > level_pfn || | |
08336fd2 | 946 | last_pfn < level_pfn + level_size(level) - 1)) { |
3269ee0b AW |
947 | dma_clear_pte(pte); |
948 | domain_flush_cache(domain, pte, sizeof(*pte)); | |
949 | free_pgtable_page(level_pte); | |
950 | } | |
951 | next: | |
952 | pfn += level_size(level); | |
953 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
954 | } | |
955 | ||
ba395927 KA |
956 | /* free page table pages. last level pte should already be cleared */ |
957 | static void dma_pte_free_pagetable(struct dmar_domain *domain, | |
d794dc9b DW |
958 | unsigned long start_pfn, |
959 | unsigned long last_pfn) | |
ba395927 | 960 | { |
6660c63a | 961 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
ba395927 | 962 | |
6660c63a DW |
963 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); |
964 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
59c36286 | 965 | BUG_ON(start_pfn > last_pfn); |
ba395927 | 966 | |
f3a0a52f | 967 | /* We don't need lock here; nobody else touches the iova range */ |
3269ee0b AW |
968 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
969 | domain->pgd, 0, start_pfn, last_pfn); | |
6660c63a | 970 | |
ba395927 | 971 | /* free pgd */ |
d794dc9b | 972 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
ba395927 KA |
973 | free_pgtable_page(domain->pgd); |
974 | domain->pgd = NULL; | |
975 | } | |
976 | } | |
977 | ||
ea8ea460 DW |
978 | /* When a page at a given level is being unlinked from its parent, we don't |
979 | need to *modify* it at all. All we need to do is make a list of all the | |
980 | pages which can be freed just as soon as we've flushed the IOTLB and we | |
981 | know the hardware page-walk will no longer touch them. | |
982 | The 'pte' argument is the *parent* PTE, pointing to the page that is to | |
983 | be freed. */ | |
984 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, | |
985 | int level, struct dma_pte *pte, | |
986 | struct page *freelist) | |
987 | { | |
988 | struct page *pg; | |
989 | ||
990 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); | |
991 | pg->freelist = freelist; | |
992 | freelist = pg; | |
993 | ||
994 | if (level == 1) | |
995 | return freelist; | |
996 | ||
997 | for (pte = page_address(pg); !first_pte_in_page(pte); pte++) { | |
998 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) | |
999 | freelist = dma_pte_list_pagetables(domain, level - 1, | |
1000 | pte, freelist); | |
1001 | } | |
1002 | ||
1003 | return freelist; | |
1004 | } | |
1005 | ||
1006 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, | |
1007 | struct dma_pte *pte, unsigned long pfn, | |
1008 | unsigned long start_pfn, | |
1009 | unsigned long last_pfn, | |
1010 | struct page *freelist) | |
1011 | { | |
1012 | struct dma_pte *first_pte = NULL, *last_pte = NULL; | |
1013 | ||
1014 | pfn = max(start_pfn, pfn); | |
1015 | pte = &pte[pfn_level_offset(pfn, level)]; | |
1016 | ||
1017 | do { | |
1018 | unsigned long level_pfn; | |
1019 | ||
1020 | if (!dma_pte_present(pte)) | |
1021 | goto next; | |
1022 | ||
1023 | level_pfn = pfn & level_mask(level); | |
1024 | ||
1025 | /* If range covers entire pagetable, free it */ | |
1026 | if (start_pfn <= level_pfn && | |
1027 | last_pfn >= level_pfn + level_size(level) - 1) { | |
1028 | /* These suborbinate page tables are going away entirely. Don't | |
1029 | bother to clear them; we're just going to *free* them. */ | |
1030 | if (level > 1 && !dma_pte_superpage(pte)) | |
1031 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); | |
1032 | ||
1033 | dma_clear_pte(pte); | |
1034 | if (!first_pte) | |
1035 | first_pte = pte; | |
1036 | last_pte = pte; | |
1037 | } else if (level > 1) { | |
1038 | /* Recurse down into a level that isn't *entirely* obsolete */ | |
1039 | freelist = dma_pte_clear_level(domain, level - 1, | |
1040 | phys_to_virt(dma_pte_addr(pte)), | |
1041 | level_pfn, start_pfn, last_pfn, | |
1042 | freelist); | |
1043 | } | |
1044 | next: | |
1045 | pfn += level_size(level); | |
1046 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); | |
1047 | ||
1048 | if (first_pte) | |
1049 | domain_flush_cache(domain, first_pte, | |
1050 | (void *)++last_pte - (void *)first_pte); | |
1051 | ||
1052 | return freelist; | |
1053 | } | |
1054 | ||
1055 | /* We can't just free the pages because the IOMMU may still be walking | |
1056 | the page tables, and may have cached the intermediate levels. The | |
1057 | pages can only be freed after the IOTLB flush has been done. */ | |
1058 | struct page *domain_unmap(struct dmar_domain *domain, | |
1059 | unsigned long start_pfn, | |
1060 | unsigned long last_pfn) | |
1061 | { | |
1062 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; | |
1063 | struct page *freelist = NULL; | |
1064 | ||
1065 | BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width); | |
1066 | BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width); | |
1067 | BUG_ON(start_pfn > last_pfn); | |
1068 | ||
1069 | /* we don't need lock here; nobody else touches the iova range */ | |
1070 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), | |
1071 | domain->pgd, 0, start_pfn, last_pfn, NULL); | |
1072 | ||
1073 | /* free pgd */ | |
1074 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { | |
1075 | struct page *pgd_page = virt_to_page(domain->pgd); | |
1076 | pgd_page->freelist = freelist; | |
1077 | freelist = pgd_page; | |
1078 | ||
1079 | domain->pgd = NULL; | |
1080 | } | |
1081 | ||
1082 | return freelist; | |
1083 | } | |
1084 | ||
1085 | void dma_free_pagelist(struct page *freelist) | |
1086 | { | |
1087 | struct page *pg; | |
1088 | ||
1089 | while ((pg = freelist)) { | |
1090 | freelist = pg->freelist; | |
1091 | free_pgtable_page(page_address(pg)); | |
1092 | } | |
1093 | } | |
1094 | ||
ba395927 KA |
1095 | /* iommu handling */ |
1096 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) | |
1097 | { | |
1098 | struct root_entry *root; | |
1099 | unsigned long flags; | |
1100 | ||
4c923d47 | 1101 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
ba395927 KA |
1102 | if (!root) |
1103 | return -ENOMEM; | |
1104 | ||
5b6985ce | 1105 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
ba395927 KA |
1106 | |
1107 | spin_lock_irqsave(&iommu->lock, flags); | |
1108 | iommu->root_entry = root; | |
1109 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1110 | ||
1111 | return 0; | |
1112 | } | |
1113 | ||
ba395927 KA |
1114 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
1115 | { | |
1116 | void *addr; | |
c416daa9 | 1117 | u32 sts; |
ba395927 KA |
1118 | unsigned long flag; |
1119 | ||
1120 | addr = iommu->root_entry; | |
1121 | ||
1f5b3c3f | 1122 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1123 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
1124 | ||
c416daa9 | 1125 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1126 | |
1127 | /* Make sure hardware complete it */ | |
1128 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1129 | readl, (sts & DMA_GSTS_RTPS), sts); |
ba395927 | 1130 | |
1f5b3c3f | 1131 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1132 | } |
1133 | ||
1134 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) | |
1135 | { | |
1136 | u32 val; | |
1137 | unsigned long flag; | |
1138 | ||
9af88143 | 1139 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
ba395927 | 1140 | return; |
ba395927 | 1141 | |
1f5b3c3f | 1142 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
462b60f6 | 1143 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
ba395927 KA |
1144 | |
1145 | /* Make sure hardware complete it */ | |
1146 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1147 | readl, (!(val & DMA_GSTS_WBFS)), val); |
ba395927 | 1148 | |
1f5b3c3f | 1149 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1150 | } |
1151 | ||
1152 | /* return value determine if we need a write buffer flush */ | |
4c25a2c1 DW |
1153 | static void __iommu_flush_context(struct intel_iommu *iommu, |
1154 | u16 did, u16 source_id, u8 function_mask, | |
1155 | u64 type) | |
ba395927 KA |
1156 | { |
1157 | u64 val = 0; | |
1158 | unsigned long flag; | |
1159 | ||
ba395927 KA |
1160 | switch (type) { |
1161 | case DMA_CCMD_GLOBAL_INVL: | |
1162 | val = DMA_CCMD_GLOBAL_INVL; | |
1163 | break; | |
1164 | case DMA_CCMD_DOMAIN_INVL: | |
1165 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); | |
1166 | break; | |
1167 | case DMA_CCMD_DEVICE_INVL: | |
1168 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) | |
1169 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); | |
1170 | break; | |
1171 | default: | |
1172 | BUG(); | |
1173 | } | |
1174 | val |= DMA_CCMD_ICC; | |
1175 | ||
1f5b3c3f | 1176 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1177 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
1178 | ||
1179 | /* Make sure hardware complete it */ | |
1180 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, | |
1181 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); | |
1182 | ||
1f5b3c3f | 1183 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1184 | } |
1185 | ||
ba395927 | 1186 | /* return value determine if we need a write buffer flush */ |
1f0ef2aa DW |
1187 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
1188 | u64 addr, unsigned int size_order, u64 type) | |
ba395927 KA |
1189 | { |
1190 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); | |
1191 | u64 val = 0, val_iva = 0; | |
1192 | unsigned long flag; | |
1193 | ||
ba395927 KA |
1194 | switch (type) { |
1195 | case DMA_TLB_GLOBAL_FLUSH: | |
1196 | /* global flush doesn't need set IVA_REG */ | |
1197 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; | |
1198 | break; | |
1199 | case DMA_TLB_DSI_FLUSH: | |
1200 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
1201 | break; | |
1202 | case DMA_TLB_PSI_FLUSH: | |
1203 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); | |
ea8ea460 | 1204 | /* IH bit is passed in as part of address */ |
ba395927 KA |
1205 | val_iva = size_order | addr; |
1206 | break; | |
1207 | default: | |
1208 | BUG(); | |
1209 | } | |
1210 | /* Note: set drain read/write */ | |
1211 | #if 0 | |
1212 | /* | |
1213 | * This is probably to be super secure.. Looks like we can | |
1214 | * ignore it without any impact. | |
1215 | */ | |
1216 | if (cap_read_drain(iommu->cap)) | |
1217 | val |= DMA_TLB_READ_DRAIN; | |
1218 | #endif | |
1219 | if (cap_write_drain(iommu->cap)) | |
1220 | val |= DMA_TLB_WRITE_DRAIN; | |
1221 | ||
1f5b3c3f | 1222 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1223 | /* Note: Only uses first TLB reg currently */ |
1224 | if (val_iva) | |
1225 | dmar_writeq(iommu->reg + tlb_offset, val_iva); | |
1226 | dmar_writeq(iommu->reg + tlb_offset + 8, val); | |
1227 | ||
1228 | /* Make sure hardware complete it */ | |
1229 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, | |
1230 | dmar_readq, (!(val & DMA_TLB_IVT)), val); | |
1231 | ||
1f5b3c3f | 1232 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1233 | |
1234 | /* check IOTLB invalidation granularity */ | |
1235 | if (DMA_TLB_IAIG(val) == 0) | |
1236 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); | |
1237 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) | |
1238 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", | |
5b6985ce FY |
1239 | (unsigned long long)DMA_TLB_IIRG(type), |
1240 | (unsigned long long)DMA_TLB_IAIG(val)); | |
ba395927 KA |
1241 | } |
1242 | ||
64ae892b DW |
1243 | static struct device_domain_info * |
1244 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, | |
1245 | u8 bus, u8 devfn) | |
93a23a72 YZ |
1246 | { |
1247 | int found = 0; | |
1248 | unsigned long flags; | |
1249 | struct device_domain_info *info; | |
0bcb3e28 | 1250 | struct pci_dev *pdev; |
93a23a72 YZ |
1251 | |
1252 | if (!ecap_dev_iotlb_support(iommu->ecap)) | |
1253 | return NULL; | |
1254 | ||
1255 | if (!iommu->qi) | |
1256 | return NULL; | |
1257 | ||
1258 | spin_lock_irqsave(&device_domain_lock, flags); | |
1259 | list_for_each_entry(info, &domain->devices, link) | |
1260 | if (info->bus == bus && info->devfn == devfn) { | |
1261 | found = 1; | |
1262 | break; | |
1263 | } | |
1264 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1265 | ||
0bcb3e28 | 1266 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1267 | return NULL; |
1268 | ||
0bcb3e28 DW |
1269 | pdev = to_pci_dev(info->dev); |
1270 | ||
1271 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) | |
93a23a72 YZ |
1272 | return NULL; |
1273 | ||
0bcb3e28 | 1274 | if (!dmar_find_matched_atsr_unit(pdev)) |
93a23a72 YZ |
1275 | return NULL; |
1276 | ||
1277 | info->iommu = iommu; | |
1278 | ||
1279 | return info; | |
1280 | } | |
1281 | ||
1282 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) | |
ba395927 | 1283 | { |
0bcb3e28 | 1284 | if (!info || !dev_is_pci(info->dev)) |
93a23a72 YZ |
1285 | return; |
1286 | ||
0bcb3e28 | 1287 | pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT); |
93a23a72 YZ |
1288 | } |
1289 | ||
1290 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) | |
1291 | { | |
0bcb3e28 DW |
1292 | if (!info->dev || !dev_is_pci(info->dev) || |
1293 | !pci_ats_enabled(to_pci_dev(info->dev))) | |
93a23a72 YZ |
1294 | return; |
1295 | ||
0bcb3e28 | 1296 | pci_disable_ats(to_pci_dev(info->dev)); |
93a23a72 YZ |
1297 | } |
1298 | ||
1299 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, | |
1300 | u64 addr, unsigned mask) | |
1301 | { | |
1302 | u16 sid, qdep; | |
1303 | unsigned long flags; | |
1304 | struct device_domain_info *info; | |
1305 | ||
1306 | spin_lock_irqsave(&device_domain_lock, flags); | |
1307 | list_for_each_entry(info, &domain->devices, link) { | |
0bcb3e28 DW |
1308 | struct pci_dev *pdev; |
1309 | if (!info->dev || !dev_is_pci(info->dev)) | |
1310 | continue; | |
1311 | ||
1312 | pdev = to_pci_dev(info->dev); | |
1313 | if (!pci_ats_enabled(pdev)) | |
93a23a72 YZ |
1314 | continue; |
1315 | ||
1316 | sid = info->bus << 8 | info->devfn; | |
0bcb3e28 | 1317 | qdep = pci_ats_queue_depth(pdev); |
93a23a72 YZ |
1318 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
1319 | } | |
1320 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
1321 | } | |
1322 | ||
1f0ef2aa | 1323 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
ea8ea460 | 1324 | unsigned long pfn, unsigned int pages, int ih, int map) |
ba395927 | 1325 | { |
9dd2fe89 | 1326 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
03d6a246 | 1327 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
ba395927 | 1328 | |
ba395927 KA |
1329 | BUG_ON(pages == 0); |
1330 | ||
ea8ea460 DW |
1331 | if (ih) |
1332 | ih = 1 << 6; | |
ba395927 | 1333 | /* |
9dd2fe89 YZ |
1334 | * Fallback to domain selective flush if no PSI support or the size is |
1335 | * too big. | |
ba395927 KA |
1336 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
1337 | * aligned to the size | |
1338 | */ | |
9dd2fe89 YZ |
1339 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
1340 | iommu->flush.flush_iotlb(iommu, did, 0, 0, | |
1f0ef2aa | 1341 | DMA_TLB_DSI_FLUSH); |
9dd2fe89 | 1342 | else |
ea8ea460 | 1343 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
9dd2fe89 | 1344 | DMA_TLB_PSI_FLUSH); |
bf92df30 YZ |
1345 | |
1346 | /* | |
82653633 NA |
1347 | * In caching mode, changes of pages from non-present to present require |
1348 | * flush. However, device IOTLB doesn't need to be flushed in this case. | |
bf92df30 | 1349 | */ |
82653633 | 1350 | if (!cap_caching_mode(iommu->cap) || !map) |
93a23a72 | 1351 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
ba395927 KA |
1352 | } |
1353 | ||
f8bab735 | 1354 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
1355 | { | |
1356 | u32 pmen; | |
1357 | unsigned long flags; | |
1358 | ||
1f5b3c3f | 1359 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
f8bab735 | 1360 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
1361 | pmen &= ~DMA_PMEN_EPM; | |
1362 | writel(pmen, iommu->reg + DMAR_PMEN_REG); | |
1363 | ||
1364 | /* wait for the protected region status bit to clear */ | |
1365 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, | |
1366 | readl, !(pmen & DMA_PMEN_PRS), pmen); | |
1367 | ||
1f5b3c3f | 1368 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
f8bab735 | 1369 | } |
1370 | ||
ba395927 KA |
1371 | static int iommu_enable_translation(struct intel_iommu *iommu) |
1372 | { | |
1373 | u32 sts; | |
1374 | unsigned long flags; | |
1375 | ||
1f5b3c3f | 1376 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
c416daa9 DW |
1377 | iommu->gcmd |= DMA_GCMD_TE; |
1378 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
ba395927 KA |
1379 | |
1380 | /* Make sure hardware complete it */ | |
1381 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1382 | readl, (sts & DMA_GSTS_TES), sts); |
ba395927 | 1383 | |
1f5b3c3f | 1384 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
ba395927 KA |
1385 | return 0; |
1386 | } | |
1387 | ||
1388 | static int iommu_disable_translation(struct intel_iommu *iommu) | |
1389 | { | |
1390 | u32 sts; | |
1391 | unsigned long flag; | |
1392 | ||
1f5b3c3f | 1393 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
ba395927 KA |
1394 | iommu->gcmd &= ~DMA_GCMD_TE; |
1395 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
1396 | ||
1397 | /* Make sure hardware complete it */ | |
1398 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
c416daa9 | 1399 | readl, (!(sts & DMA_GSTS_TES)), sts); |
ba395927 | 1400 | |
1f5b3c3f | 1401 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
ba395927 KA |
1402 | return 0; |
1403 | } | |
1404 | ||
3460a6d9 | 1405 | |
ba395927 KA |
1406 | static int iommu_init_domains(struct intel_iommu *iommu) |
1407 | { | |
1408 | unsigned long ndomains; | |
1409 | unsigned long nlongs; | |
1410 | ||
1411 | ndomains = cap_ndoms(iommu->cap); | |
852bdb04 JL |
1412 | pr_debug("IOMMU%d: Number of Domains supported <%ld>\n", |
1413 | iommu->seq_id, ndomains); | |
ba395927 KA |
1414 | nlongs = BITS_TO_LONGS(ndomains); |
1415 | ||
94a91b50 DD |
1416 | spin_lock_init(&iommu->lock); |
1417 | ||
ba395927 KA |
1418 | /* TBD: there might be 64K domains, |
1419 | * consider other allocation for future chip | |
1420 | */ | |
1421 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); | |
1422 | if (!iommu->domain_ids) { | |
852bdb04 JL |
1423 | pr_err("IOMMU%d: allocating domain id array failed\n", |
1424 | iommu->seq_id); | |
ba395927 KA |
1425 | return -ENOMEM; |
1426 | } | |
1427 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), | |
1428 | GFP_KERNEL); | |
1429 | if (!iommu->domains) { | |
852bdb04 JL |
1430 | pr_err("IOMMU%d: allocating domain array failed\n", |
1431 | iommu->seq_id); | |
1432 | kfree(iommu->domain_ids); | |
1433 | iommu->domain_ids = NULL; | |
ba395927 KA |
1434 | return -ENOMEM; |
1435 | } | |
1436 | ||
1437 | /* | |
1438 | * if Caching mode is set, then invalid translations are tagged | |
1439 | * with domainid 0. Hence we need to pre-allocate it. | |
1440 | */ | |
1441 | if (cap_caching_mode(iommu->cap)) | |
1442 | set_bit(0, iommu->domain_ids); | |
1443 | return 0; | |
1444 | } | |
ba395927 | 1445 | |
a868e6b7 | 1446 | static void free_dmar_iommu(struct intel_iommu *iommu) |
ba395927 KA |
1447 | { |
1448 | struct dmar_domain *domain; | |
5ced12af | 1449 | int i, count; |
c7151a8d | 1450 | unsigned long flags; |
ba395927 | 1451 | |
94a91b50 | 1452 | if ((iommu->domains) && (iommu->domain_ids)) { |
a45946ab | 1453 | for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) { |
a4eaa86c JL |
1454 | /* |
1455 | * Domain id 0 is reserved for invalid translation | |
1456 | * if hardware supports caching mode. | |
1457 | */ | |
1458 | if (cap_caching_mode(iommu->cap) && i == 0) | |
1459 | continue; | |
1460 | ||
94a91b50 DD |
1461 | domain = iommu->domains[i]; |
1462 | clear_bit(i, iommu->domain_ids); | |
1463 | ||
1464 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
5ced12af JL |
1465 | count = --domain->iommu_count; |
1466 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
92d03cc8 JL |
1467 | if (count == 0) |
1468 | domain_exit(domain); | |
5e98c4b1 | 1469 | } |
ba395927 KA |
1470 | } |
1471 | ||
1472 | if (iommu->gcmd & DMA_GCMD_TE) | |
1473 | iommu_disable_translation(iommu); | |
1474 | ||
ba395927 KA |
1475 | kfree(iommu->domains); |
1476 | kfree(iommu->domain_ids); | |
a868e6b7 JL |
1477 | iommu->domains = NULL; |
1478 | iommu->domain_ids = NULL; | |
ba395927 | 1479 | |
d9630fe9 WH |
1480 | g_iommus[iommu->seq_id] = NULL; |
1481 | ||
ba395927 KA |
1482 | /* free context mapping */ |
1483 | free_context_table(iommu); | |
ba395927 KA |
1484 | } |
1485 | ||
92d03cc8 | 1486 | static struct dmar_domain *alloc_domain(bool vm) |
ba395927 | 1487 | { |
92d03cc8 JL |
1488 | /* domain id for virtual machine, it won't be set in context */ |
1489 | static atomic_t vm_domid = ATOMIC_INIT(0); | |
ba395927 | 1490 | struct dmar_domain *domain; |
ba395927 KA |
1491 | |
1492 | domain = alloc_domain_mem(); | |
1493 | if (!domain) | |
1494 | return NULL; | |
1495 | ||
4c923d47 | 1496 | domain->nid = -1; |
92d03cc8 | 1497 | domain->iommu_count = 0; |
1b198bb0 | 1498 | memset(domain->iommu_bmp, 0, sizeof(domain->iommu_bmp)); |
2c2e2c38 | 1499 | domain->flags = 0; |
92d03cc8 JL |
1500 | spin_lock_init(&domain->iommu_lock); |
1501 | INIT_LIST_HEAD(&domain->devices); | |
1502 | if (vm) { | |
1503 | domain->id = atomic_inc_return(&vm_domid); | |
1504 | domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE; | |
1505 | } | |
2c2e2c38 FY |
1506 | |
1507 | return domain; | |
1508 | } | |
1509 | ||
1510 | static int iommu_attach_domain(struct dmar_domain *domain, | |
1511 | struct intel_iommu *iommu) | |
1512 | { | |
1513 | int num; | |
1514 | unsigned long ndomains; | |
1515 | unsigned long flags; | |
1516 | ||
ba395927 KA |
1517 | ndomains = cap_ndoms(iommu->cap); |
1518 | ||
1519 | spin_lock_irqsave(&iommu->lock, flags); | |
2c2e2c38 | 1520 | |
ba395927 KA |
1521 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
1522 | if (num >= ndomains) { | |
1523 | spin_unlock_irqrestore(&iommu->lock, flags); | |
ba395927 | 1524 | printk(KERN_ERR "IOMMU: no free domain ids\n"); |
2c2e2c38 | 1525 | return -ENOMEM; |
ba395927 KA |
1526 | } |
1527 | ||
ba395927 | 1528 | domain->id = num; |
9ebd682e | 1529 | domain->iommu_count++; |
2c2e2c38 | 1530 | set_bit(num, iommu->domain_ids); |
1b198bb0 | 1531 | set_bit(iommu->seq_id, domain->iommu_bmp); |
ba395927 KA |
1532 | iommu->domains[num] = domain; |
1533 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1534 | ||
2c2e2c38 | 1535 | return 0; |
ba395927 KA |
1536 | } |
1537 | ||
2c2e2c38 FY |
1538 | static void iommu_detach_domain(struct dmar_domain *domain, |
1539 | struct intel_iommu *iommu) | |
ba395927 KA |
1540 | { |
1541 | unsigned long flags; | |
2c2e2c38 | 1542 | int num, ndomains; |
ba395927 | 1543 | |
8c11e798 | 1544 | spin_lock_irqsave(&iommu->lock, flags); |
2c2e2c38 | 1545 | ndomains = cap_ndoms(iommu->cap); |
a45946ab | 1546 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
2c2e2c38 | 1547 | if (iommu->domains[num] == domain) { |
92d03cc8 JL |
1548 | clear_bit(num, iommu->domain_ids); |
1549 | iommu->domains[num] = NULL; | |
2c2e2c38 FY |
1550 | break; |
1551 | } | |
2c2e2c38 | 1552 | } |
8c11e798 | 1553 | spin_unlock_irqrestore(&iommu->lock, flags); |
ba395927 KA |
1554 | } |
1555 | ||
1556 | static struct iova_domain reserved_iova_list; | |
8a443df4 | 1557 | static struct lock_class_key reserved_rbtree_key; |
ba395927 | 1558 | |
51a63e67 | 1559 | static int dmar_init_reserved_ranges(void) |
ba395927 KA |
1560 | { |
1561 | struct pci_dev *pdev = NULL; | |
1562 | struct iova *iova; | |
1563 | int i; | |
ba395927 | 1564 | |
f661197e | 1565 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
ba395927 | 1566 | |
8a443df4 MG |
1567 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
1568 | &reserved_rbtree_key); | |
1569 | ||
ba395927 KA |
1570 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
1571 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), | |
1572 | IOVA_PFN(IOAPIC_RANGE_END)); | |
51a63e67 | 1573 | if (!iova) { |
ba395927 | 1574 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
51a63e67 JC |
1575 | return -ENODEV; |
1576 | } | |
ba395927 KA |
1577 | |
1578 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ | |
1579 | for_each_pci_dev(pdev) { | |
1580 | struct resource *r; | |
1581 | ||
1582 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1583 | r = &pdev->resource[i]; | |
1584 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) | |
1585 | continue; | |
1a4a4551 DW |
1586 | iova = reserve_iova(&reserved_iova_list, |
1587 | IOVA_PFN(r->start), | |
1588 | IOVA_PFN(r->end)); | |
51a63e67 | 1589 | if (!iova) { |
ba395927 | 1590 | printk(KERN_ERR "Reserve iova failed\n"); |
51a63e67 JC |
1591 | return -ENODEV; |
1592 | } | |
ba395927 KA |
1593 | } |
1594 | } | |
51a63e67 | 1595 | return 0; |
ba395927 KA |
1596 | } |
1597 | ||
1598 | static void domain_reserve_special_ranges(struct dmar_domain *domain) | |
1599 | { | |
1600 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); | |
1601 | } | |
1602 | ||
1603 | static inline int guestwidth_to_adjustwidth(int gaw) | |
1604 | { | |
1605 | int agaw; | |
1606 | int r = (gaw - 12) % 9; | |
1607 | ||
1608 | if (r == 0) | |
1609 | agaw = gaw; | |
1610 | else | |
1611 | agaw = gaw + 9 - r; | |
1612 | if (agaw > 64) | |
1613 | agaw = 64; | |
1614 | return agaw; | |
1615 | } | |
1616 | ||
1617 | static int domain_init(struct dmar_domain *domain, int guest_width) | |
1618 | { | |
1619 | struct intel_iommu *iommu; | |
1620 | int adjust_width, agaw; | |
1621 | unsigned long sagaw; | |
1622 | ||
f661197e | 1623 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
ba395927 KA |
1624 | domain_reserve_special_ranges(domain); |
1625 | ||
1626 | /* calculate AGAW */ | |
8c11e798 | 1627 | iommu = domain_get_iommu(domain); |
ba395927 KA |
1628 | if (guest_width > cap_mgaw(iommu->cap)) |
1629 | guest_width = cap_mgaw(iommu->cap); | |
1630 | domain->gaw = guest_width; | |
1631 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
1632 | agaw = width_to_agaw(adjust_width); | |
1633 | sagaw = cap_sagaw(iommu->cap); | |
1634 | if (!test_bit(agaw, &sagaw)) { | |
1635 | /* hardware doesn't support it, choose a bigger one */ | |
1636 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); | |
1637 | agaw = find_next_bit(&sagaw, 5, agaw); | |
1638 | if (agaw >= 5) | |
1639 | return -ENODEV; | |
1640 | } | |
1641 | domain->agaw = agaw; | |
ba395927 | 1642 | |
8e604097 WH |
1643 | if (ecap_coherent(iommu->ecap)) |
1644 | domain->iommu_coherency = 1; | |
1645 | else | |
1646 | domain->iommu_coherency = 0; | |
1647 | ||
58c610bd SY |
1648 | if (ecap_sc_support(iommu->ecap)) |
1649 | domain->iommu_snooping = 1; | |
1650 | else | |
1651 | domain->iommu_snooping = 0; | |
1652 | ||
214e39aa DW |
1653 | if (intel_iommu_superpage) |
1654 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); | |
1655 | else | |
1656 | domain->iommu_superpage = 0; | |
1657 | ||
4c923d47 | 1658 | domain->nid = iommu->node; |
c7151a8d | 1659 | |
ba395927 | 1660 | /* always allocate the top pgd */ |
4c923d47 | 1661 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
ba395927 KA |
1662 | if (!domain->pgd) |
1663 | return -ENOMEM; | |
5b6985ce | 1664 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
ba395927 KA |
1665 | return 0; |
1666 | } | |
1667 | ||
1668 | static void domain_exit(struct dmar_domain *domain) | |
1669 | { | |
2c2e2c38 FY |
1670 | struct dmar_drhd_unit *drhd; |
1671 | struct intel_iommu *iommu; | |
ea8ea460 | 1672 | struct page *freelist = NULL; |
ba395927 KA |
1673 | |
1674 | /* Domain 0 is reserved, so dont process it */ | |
1675 | if (!domain) | |
1676 | return; | |
1677 | ||
7b668357 AW |
1678 | /* Flush any lazy unmaps that may reference this domain */ |
1679 | if (!intel_iommu_strict) | |
1680 | flush_unmaps_timeout(0); | |
1681 | ||
92d03cc8 | 1682 | /* remove associated devices */ |
ba395927 | 1683 | domain_remove_dev_info(domain); |
92d03cc8 | 1684 | |
ba395927 KA |
1685 | /* destroy iovas */ |
1686 | put_iova_domain(&domain->iovad); | |
ba395927 | 1687 | |
ea8ea460 | 1688 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
ba395927 | 1689 | |
92d03cc8 | 1690 | /* clear attached or cached domains */ |
0e242612 | 1691 | rcu_read_lock(); |
2c2e2c38 | 1692 | for_each_active_iommu(iommu, drhd) |
92d03cc8 JL |
1693 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1694 | test_bit(iommu->seq_id, domain->iommu_bmp)) | |
2c2e2c38 | 1695 | iommu_detach_domain(domain, iommu); |
0e242612 | 1696 | rcu_read_unlock(); |
2c2e2c38 | 1697 | |
ea8ea460 DW |
1698 | dma_free_pagelist(freelist); |
1699 | ||
ba395927 KA |
1700 | free_domain_mem(domain); |
1701 | } | |
1702 | ||
64ae892b DW |
1703 | static int domain_context_mapping_one(struct dmar_domain *domain, |
1704 | struct intel_iommu *iommu, | |
1705 | u8 bus, u8 devfn, int translation) | |
ba395927 KA |
1706 | { |
1707 | struct context_entry *context; | |
ba395927 | 1708 | unsigned long flags; |
ea6606b0 WH |
1709 | struct dma_pte *pgd; |
1710 | unsigned long num; | |
1711 | unsigned long ndomains; | |
1712 | int id; | |
1713 | int agaw; | |
93a23a72 | 1714 | struct device_domain_info *info = NULL; |
ba395927 KA |
1715 | |
1716 | pr_debug("Set context mapping for %02x:%02x.%d\n", | |
1717 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
4ed0d3e6 | 1718 | |
ba395927 | 1719 | BUG_ON(!domain->pgd); |
4ed0d3e6 FY |
1720 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
1721 | translation != CONTEXT_TT_MULTI_LEVEL); | |
5331fe6f | 1722 | |
ba395927 KA |
1723 | context = device_to_context_entry(iommu, bus, devfn); |
1724 | if (!context) | |
1725 | return -ENOMEM; | |
1726 | spin_lock_irqsave(&iommu->lock, flags); | |
c07e7d21 | 1727 | if (context_present(context)) { |
ba395927 KA |
1728 | spin_unlock_irqrestore(&iommu->lock, flags); |
1729 | return 0; | |
1730 | } | |
1731 | ||
ea6606b0 WH |
1732 | id = domain->id; |
1733 | pgd = domain->pgd; | |
1734 | ||
2c2e2c38 FY |
1735 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
1736 | domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) { | |
ea6606b0 WH |
1737 | int found = 0; |
1738 | ||
1739 | /* find an available domain id for this device in iommu */ | |
1740 | ndomains = cap_ndoms(iommu->cap); | |
a45946ab | 1741 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
ea6606b0 WH |
1742 | if (iommu->domains[num] == domain) { |
1743 | id = num; | |
1744 | found = 1; | |
1745 | break; | |
1746 | } | |
ea6606b0 WH |
1747 | } |
1748 | ||
1749 | if (found == 0) { | |
1750 | num = find_first_zero_bit(iommu->domain_ids, ndomains); | |
1751 | if (num >= ndomains) { | |
1752 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1753 | printk(KERN_ERR "IOMMU: no free domain ids\n"); | |
1754 | return -EFAULT; | |
1755 | } | |
1756 | ||
1757 | set_bit(num, iommu->domain_ids); | |
1758 | iommu->domains[num] = domain; | |
1759 | id = num; | |
1760 | } | |
1761 | ||
1762 | /* Skip top levels of page tables for | |
1763 | * iommu which has less agaw than default. | |
1672af11 | 1764 | * Unnecessary for PT mode. |
ea6606b0 | 1765 | */ |
1672af11 CW |
1766 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
1767 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { | |
1768 | pgd = phys_to_virt(dma_pte_addr(pgd)); | |
1769 | if (!dma_pte_present(pgd)) { | |
1770 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1771 | return -ENOMEM; | |
1772 | } | |
ea6606b0 WH |
1773 | } |
1774 | } | |
1775 | } | |
1776 | ||
1777 | context_set_domain_id(context, id); | |
4ed0d3e6 | 1778 | |
93a23a72 | 1779 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
64ae892b | 1780 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
93a23a72 YZ |
1781 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
1782 | CONTEXT_TT_MULTI_LEVEL; | |
1783 | } | |
4ed0d3e6 FY |
1784 | /* |
1785 | * In pass through mode, AW must be programmed to indicate the largest | |
1786 | * AGAW value supported by hardware. And ASR is ignored by hardware. | |
1787 | */ | |
93a23a72 | 1788 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
4ed0d3e6 | 1789 | context_set_address_width(context, iommu->msagaw); |
93a23a72 YZ |
1790 | else { |
1791 | context_set_address_root(context, virt_to_phys(pgd)); | |
1792 | context_set_address_width(context, iommu->agaw); | |
1793 | } | |
4ed0d3e6 FY |
1794 | |
1795 | context_set_translation_type(context, translation); | |
c07e7d21 MM |
1796 | context_set_fault_enable(context); |
1797 | context_set_present(context); | |
5331fe6f | 1798 | domain_flush_cache(domain, context, sizeof(*context)); |
ba395927 | 1799 | |
4c25a2c1 DW |
1800 | /* |
1801 | * It's a non-present to present mapping. If hardware doesn't cache | |
1802 | * non-present entry we only need to flush the write-buffer. If the | |
1803 | * _does_ cache non-present entries, then it does so in the special | |
1804 | * domain #0, which we have to flush: | |
1805 | */ | |
1806 | if (cap_caching_mode(iommu->cap)) { | |
1807 | iommu->flush.flush_context(iommu, 0, | |
1808 | (((u16)bus) << 8) | devfn, | |
1809 | DMA_CCMD_MASK_NOBIT, | |
1810 | DMA_CCMD_DEVICE_INVL); | |
82653633 | 1811 | iommu->flush.flush_iotlb(iommu, domain->id, 0, 0, DMA_TLB_DSI_FLUSH); |
4c25a2c1 | 1812 | } else { |
ba395927 | 1813 | iommu_flush_write_buffer(iommu); |
4c25a2c1 | 1814 | } |
93a23a72 | 1815 | iommu_enable_dev_iotlb(info); |
ba395927 | 1816 | spin_unlock_irqrestore(&iommu->lock, flags); |
c7151a8d WH |
1817 | |
1818 | spin_lock_irqsave(&domain->iommu_lock, flags); | |
1b198bb0 | 1819 | if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) { |
c7151a8d | 1820 | domain->iommu_count++; |
4c923d47 SS |
1821 | if (domain->iommu_count == 1) |
1822 | domain->nid = iommu->node; | |
58c610bd | 1823 | domain_update_iommu_cap(domain); |
c7151a8d WH |
1824 | } |
1825 | spin_unlock_irqrestore(&domain->iommu_lock, flags); | |
ba395927 KA |
1826 | return 0; |
1827 | } | |
1828 | ||
1829 | static int | |
4ed0d3e6 FY |
1830 | domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev, |
1831 | int translation) | |
ba395927 KA |
1832 | { |
1833 | int ret; | |
1834 | struct pci_dev *tmp, *parent; | |
64ae892b DW |
1835 | struct intel_iommu *iommu; |
1836 | ||
1837 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, | |
1838 | pdev->devfn); | |
1839 | if (!iommu) | |
1840 | return -ENODEV; | |
ba395927 | 1841 | |
64ae892b | 1842 | ret = domain_context_mapping_one(domain, iommu, |
4ed0d3e6 FY |
1843 | pdev->bus->number, pdev->devfn, |
1844 | translation); | |
ba395927 KA |
1845 | if (ret) |
1846 | return ret; | |
1847 | ||
1848 | /* dependent device mapping */ | |
1849 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1850 | if (!tmp) | |
1851 | return 0; | |
1852 | /* Secondary interface's bus number and devfn 0 */ | |
1853 | parent = pdev->bus->self; | |
1854 | while (parent != tmp) { | |
64ae892b | 1855 | ret = domain_context_mapping_one(domain, iommu, |
276dbf99 | 1856 | parent->bus->number, |
4ed0d3e6 | 1857 | parent->devfn, translation); |
ba395927 KA |
1858 | if (ret) |
1859 | return ret; | |
1860 | parent = parent->bus->self; | |
1861 | } | |
45e829ea | 1862 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
64ae892b | 1863 | return domain_context_mapping_one(domain, iommu, |
4ed0d3e6 FY |
1864 | tmp->subordinate->number, 0, |
1865 | translation); | |
ba395927 | 1866 | else /* this is a legacy PCI bridge */ |
64ae892b | 1867 | return domain_context_mapping_one(domain, iommu, |
276dbf99 | 1868 | tmp->bus->number, |
4ed0d3e6 FY |
1869 | tmp->devfn, |
1870 | translation); | |
ba395927 KA |
1871 | } |
1872 | ||
5331fe6f | 1873 | static int domain_context_mapped(struct pci_dev *pdev) |
ba395927 KA |
1874 | { |
1875 | int ret; | |
1876 | struct pci_dev *tmp, *parent; | |
5331fe6f WH |
1877 | struct intel_iommu *iommu; |
1878 | ||
276dbf99 DW |
1879 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
1880 | pdev->devfn); | |
5331fe6f WH |
1881 | if (!iommu) |
1882 | return -ENODEV; | |
ba395927 | 1883 | |
276dbf99 | 1884 | ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn); |
ba395927 KA |
1885 | if (!ret) |
1886 | return ret; | |
1887 | /* dependent device mapping */ | |
1888 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
1889 | if (!tmp) | |
1890 | return ret; | |
1891 | /* Secondary interface's bus number and devfn 0 */ | |
1892 | parent = pdev->bus->self; | |
1893 | while (parent != tmp) { | |
8c11e798 | 1894 | ret = device_context_mapped(iommu, parent->bus->number, |
276dbf99 | 1895 | parent->devfn); |
ba395927 KA |
1896 | if (!ret) |
1897 | return ret; | |
1898 | parent = parent->bus->self; | |
1899 | } | |
5f4d91a1 | 1900 | if (pci_is_pcie(tmp)) |
276dbf99 DW |
1901 | return device_context_mapped(iommu, tmp->subordinate->number, |
1902 | 0); | |
ba395927 | 1903 | else |
276dbf99 DW |
1904 | return device_context_mapped(iommu, tmp->bus->number, |
1905 | tmp->devfn); | |
ba395927 KA |
1906 | } |
1907 | ||
f532959b FY |
1908 | /* Returns a number of VTD pages, but aligned to MM page size */ |
1909 | static inline unsigned long aligned_nrpages(unsigned long host_addr, | |
1910 | size_t size) | |
1911 | { | |
1912 | host_addr &= ~PAGE_MASK; | |
1913 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; | |
1914 | } | |
1915 | ||
6dd9a7c7 YS |
1916 | /* Return largest possible superpage level for a given mapping */ |
1917 | static inline int hardware_largepage_caps(struct dmar_domain *domain, | |
1918 | unsigned long iov_pfn, | |
1919 | unsigned long phy_pfn, | |
1920 | unsigned long pages) | |
1921 | { | |
1922 | int support, level = 1; | |
1923 | unsigned long pfnmerge; | |
1924 | ||
1925 | support = domain->iommu_superpage; | |
1926 | ||
1927 | /* To use a large page, the virtual *and* physical addresses | |
1928 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either | |
1929 | of them will mean we have to use smaller pages. So just | |
1930 | merge them and check both at once. */ | |
1931 | pfnmerge = iov_pfn | phy_pfn; | |
1932 | ||
1933 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { | |
1934 | pages >>= VTD_STRIDE_SHIFT; | |
1935 | if (!pages) | |
1936 | break; | |
1937 | pfnmerge >>= VTD_STRIDE_SHIFT; | |
1938 | level++; | |
1939 | support--; | |
1940 | } | |
1941 | return level; | |
1942 | } | |
1943 | ||
9051aa02 DW |
1944 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
1945 | struct scatterlist *sg, unsigned long phys_pfn, | |
1946 | unsigned long nr_pages, int prot) | |
e1605495 DW |
1947 | { |
1948 | struct dma_pte *first_pte = NULL, *pte = NULL; | |
9051aa02 | 1949 | phys_addr_t uninitialized_var(pteval); |
e1605495 | 1950 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
9051aa02 | 1951 | unsigned long sg_res; |
6dd9a7c7 YS |
1952 | unsigned int largepage_lvl = 0; |
1953 | unsigned long lvl_pages = 0; | |
e1605495 DW |
1954 | |
1955 | BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width); | |
1956 | ||
1957 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) | |
1958 | return -EINVAL; | |
1959 | ||
1960 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; | |
1961 | ||
9051aa02 DW |
1962 | if (sg) |
1963 | sg_res = 0; | |
1964 | else { | |
1965 | sg_res = nr_pages + 1; | |
1966 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; | |
1967 | } | |
1968 | ||
6dd9a7c7 | 1969 | while (nr_pages > 0) { |
c85994e4 DW |
1970 | uint64_t tmp; |
1971 | ||
e1605495 | 1972 | if (!sg_res) { |
f532959b | 1973 | sg_res = aligned_nrpages(sg->offset, sg->length); |
e1605495 DW |
1974 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
1975 | sg->dma_length = sg->length; | |
1976 | pteval = page_to_phys(sg_page(sg)) | prot; | |
6dd9a7c7 | 1977 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
e1605495 | 1978 | } |
6dd9a7c7 | 1979 | |
e1605495 | 1980 | if (!pte) { |
6dd9a7c7 YS |
1981 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
1982 | ||
5cf0a76f | 1983 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
e1605495 DW |
1984 | if (!pte) |
1985 | return -ENOMEM; | |
6dd9a7c7 | 1986 | /* It is large page*/ |
6491d4d0 | 1987 | if (largepage_lvl > 1) { |
6dd9a7c7 | 1988 | pteval |= DMA_PTE_LARGE_PAGE; |
6491d4d0 WD |
1989 | /* Ensure that old small page tables are removed to make room |
1990 | for superpage, if they exist. */ | |
1991 | dma_pte_clear_range(domain, iov_pfn, | |
1992 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); | |
1993 | dma_pte_free_pagetable(domain, iov_pfn, | |
1994 | iov_pfn + lvl_to_nr_pages(largepage_lvl) - 1); | |
1995 | } else { | |
6dd9a7c7 | 1996 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
6491d4d0 | 1997 | } |
6dd9a7c7 | 1998 | |
e1605495 DW |
1999 | } |
2000 | /* We don't need lock here, nobody else | |
2001 | * touches the iova range | |
2002 | */ | |
7766a3fb | 2003 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
c85994e4 | 2004 | if (tmp) { |
1bf20f0d | 2005 | static int dumps = 5; |
c85994e4 DW |
2006 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
2007 | iov_pfn, tmp, (unsigned long long)pteval); | |
1bf20f0d DW |
2008 | if (dumps) { |
2009 | dumps--; | |
2010 | debug_dma_dump_mappings(NULL); | |
2011 | } | |
2012 | WARN_ON(1); | |
2013 | } | |
6dd9a7c7 YS |
2014 | |
2015 | lvl_pages = lvl_to_nr_pages(largepage_lvl); | |
2016 | ||
2017 | BUG_ON(nr_pages < lvl_pages); | |
2018 | BUG_ON(sg_res < lvl_pages); | |
2019 | ||
2020 | nr_pages -= lvl_pages; | |
2021 | iov_pfn += lvl_pages; | |
2022 | phys_pfn += lvl_pages; | |
2023 | pteval += lvl_pages * VTD_PAGE_SIZE; | |
2024 | sg_res -= lvl_pages; | |
2025 | ||
2026 | /* If the next PTE would be the first in a new page, then we | |
2027 | need to flush the cache on the entries we've just written. | |
2028 | And then we'll need to recalculate 'pte', so clear it and | |
2029 | let it get set again in the if (!pte) block above. | |
2030 | ||
2031 | If we're done (!nr_pages) we need to flush the cache too. | |
2032 | ||
2033 | Also if we've been setting superpages, we may need to | |
2034 | recalculate 'pte' and switch back to smaller pages for the | |
2035 | end of the mapping, if the trailing size is not enough to | |
2036 | use another superpage (i.e. sg_res < lvl_pages). */ | |
e1605495 | 2037 | pte++; |
6dd9a7c7 YS |
2038 | if (!nr_pages || first_pte_in_page(pte) || |
2039 | (largepage_lvl > 1 && sg_res < lvl_pages)) { | |
e1605495 DW |
2040 | domain_flush_cache(domain, first_pte, |
2041 | (void *)pte - (void *)first_pte); | |
2042 | pte = NULL; | |
2043 | } | |
6dd9a7c7 YS |
2044 | |
2045 | if (!sg_res && nr_pages) | |
e1605495 DW |
2046 | sg = sg_next(sg); |
2047 | } | |
2048 | return 0; | |
2049 | } | |
2050 | ||
9051aa02 DW |
2051 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2052 | struct scatterlist *sg, unsigned long nr_pages, | |
2053 | int prot) | |
ba395927 | 2054 | { |
9051aa02 DW |
2055 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
2056 | } | |
6f6a00e4 | 2057 | |
9051aa02 DW |
2058 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
2059 | unsigned long phys_pfn, unsigned long nr_pages, | |
2060 | int prot) | |
2061 | { | |
2062 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); | |
ba395927 KA |
2063 | } |
2064 | ||
c7151a8d | 2065 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
ba395927 | 2066 | { |
c7151a8d WH |
2067 | if (!iommu) |
2068 | return; | |
8c11e798 WH |
2069 | |
2070 | clear_context_table(iommu, bus, devfn); | |
2071 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
4c25a2c1 | 2072 | DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2073 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
ba395927 KA |
2074 | } |
2075 | ||
109b9b04 DW |
2076 | static inline void unlink_domain_info(struct device_domain_info *info) |
2077 | { | |
2078 | assert_spin_locked(&device_domain_lock); | |
2079 | list_del(&info->link); | |
2080 | list_del(&info->global); | |
2081 | if (info->dev) | |
0bcb3e28 | 2082 | info->dev->archdata.iommu = NULL; |
109b9b04 DW |
2083 | } |
2084 | ||
ba395927 KA |
2085 | static void domain_remove_dev_info(struct dmar_domain *domain) |
2086 | { | |
2087 | struct device_domain_info *info; | |
92d03cc8 | 2088 | unsigned long flags, flags2; |
c7151a8d | 2089 | struct intel_iommu *iommu; |
ba395927 KA |
2090 | |
2091 | spin_lock_irqsave(&device_domain_lock, flags); | |
2092 | while (!list_empty(&domain->devices)) { | |
2093 | info = list_entry(domain->devices.next, | |
2094 | struct device_domain_info, link); | |
109b9b04 | 2095 | unlink_domain_info(info); |
ba395927 KA |
2096 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2097 | ||
93a23a72 | 2098 | iommu_disable_dev_iotlb(info); |
276dbf99 | 2099 | iommu = device_to_iommu(info->segment, info->bus, info->devfn); |
c7151a8d | 2100 | iommu_detach_dev(iommu, info->bus, info->devfn); |
ba395927 | 2101 | |
92d03cc8 JL |
2102 | if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) { |
2103 | iommu_detach_dependent_devices(iommu, info->dev); | |
2104 | /* clear this iommu in iommu_bmp, update iommu count | |
2105 | * and capabilities | |
2106 | */ | |
2107 | spin_lock_irqsave(&domain->iommu_lock, flags2); | |
2108 | if (test_and_clear_bit(iommu->seq_id, | |
2109 | domain->iommu_bmp)) { | |
2110 | domain->iommu_count--; | |
2111 | domain_update_iommu_cap(domain); | |
2112 | } | |
2113 | spin_unlock_irqrestore(&domain->iommu_lock, flags2); | |
2114 | } | |
2115 | ||
2116 | free_devinfo_mem(info); | |
ba395927 KA |
2117 | spin_lock_irqsave(&device_domain_lock, flags); |
2118 | } | |
2119 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2120 | } | |
2121 | ||
2122 | /* | |
2123 | * find_domain | |
1525a29a | 2124 | * Note: we use struct device->archdata.iommu stores the info |
ba395927 | 2125 | */ |
1525a29a | 2126 | static struct dmar_domain *find_domain(struct device *dev) |
ba395927 KA |
2127 | { |
2128 | struct device_domain_info *info; | |
2129 | ||
2130 | /* No lock here, assumes no domain exit in normal case */ | |
1525a29a | 2131 | info = dev->archdata.iommu; |
ba395927 KA |
2132 | if (info) |
2133 | return info->domain; | |
2134 | return NULL; | |
2135 | } | |
2136 | ||
745f2586 JL |
2137 | static inline struct dmar_domain * |
2138 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) | |
2139 | { | |
2140 | struct device_domain_info *info; | |
2141 | ||
2142 | list_for_each_entry(info, &device_domain_list, global) | |
2143 | if (info->segment == segment && info->bus == bus && | |
2144 | info->devfn == devfn) | |
2145 | return info->domain; | |
2146 | ||
2147 | return NULL; | |
2148 | } | |
2149 | ||
b718cd3d DW |
2150 | static struct dmar_domain *dmar_insert_dev_info(int segment, int bus, int devfn, |
2151 | struct device *dev, | |
2152 | struct dmar_domain *domain) | |
745f2586 | 2153 | { |
b718cd3d | 2154 | struct dmar_domain *found; |
745f2586 JL |
2155 | struct device_domain_info *info; |
2156 | unsigned long flags; | |
2157 | ||
2158 | info = alloc_devinfo_mem(); | |
2159 | if (!info) | |
b718cd3d | 2160 | return NULL; |
745f2586 JL |
2161 | |
2162 | info->segment = segment; | |
2163 | info->bus = bus; | |
2164 | info->devfn = devfn; | |
2165 | info->dev = dev; | |
2166 | info->domain = domain; | |
2167 | if (!dev) | |
2168 | domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES; | |
2169 | ||
2170 | spin_lock_irqsave(&device_domain_lock, flags); | |
2171 | if (dev) | |
0bcb3e28 | 2172 | found = find_domain(dev); |
745f2586 JL |
2173 | else |
2174 | found = dmar_search_domain_by_dev_info(segment, bus, devfn); | |
2175 | if (found) { | |
2176 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2177 | free_devinfo_mem(info); | |
b718cd3d DW |
2178 | /* Caller must free the original domain */ |
2179 | return found; | |
745f2586 JL |
2180 | } |
2181 | ||
b718cd3d DW |
2182 | list_add(&info->link, &domain->devices); |
2183 | list_add(&info->global, &device_domain_list); | |
2184 | if (dev) | |
2185 | dev->archdata.iommu = info; | |
2186 | spin_unlock_irqrestore(&device_domain_lock, flags); | |
2187 | ||
2188 | return domain; | |
745f2586 JL |
2189 | } |
2190 | ||
ba395927 KA |
2191 | /* domain is initialized */ |
2192 | static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw) | |
2193 | { | |
e85bb5d4 | 2194 | struct dmar_domain *domain, *free = NULL; |
ba395927 KA |
2195 | struct intel_iommu *iommu; |
2196 | struct dmar_drhd_unit *drhd; | |
ba395927 KA |
2197 | struct pci_dev *dev_tmp; |
2198 | unsigned long flags; | |
2199 | int bus = 0, devfn = 0; | |
276dbf99 | 2200 | int segment; |
ba395927 | 2201 | |
1525a29a | 2202 | domain = find_domain(&pdev->dev); |
ba395927 KA |
2203 | if (domain) |
2204 | return domain; | |
2205 | ||
276dbf99 DW |
2206 | segment = pci_domain_nr(pdev->bus); |
2207 | ||
ba395927 KA |
2208 | dev_tmp = pci_find_upstream_pcie_bridge(pdev); |
2209 | if (dev_tmp) { | |
5f4d91a1 | 2210 | if (pci_is_pcie(dev_tmp)) { |
ba395927 KA |
2211 | bus = dev_tmp->subordinate->number; |
2212 | devfn = 0; | |
2213 | } else { | |
2214 | bus = dev_tmp->bus->number; | |
2215 | devfn = dev_tmp->devfn; | |
2216 | } | |
2217 | spin_lock_irqsave(&device_domain_lock, flags); | |
745f2586 | 2218 | domain = dmar_search_domain_by_dev_info(segment, bus, devfn); |
ba395927 KA |
2219 | spin_unlock_irqrestore(&device_domain_lock, flags); |
2220 | /* pcie-pci bridge already has a domain, uses it */ | |
745f2586 | 2221 | if (domain) |
ba395927 | 2222 | goto found_domain; |
ba395927 KA |
2223 | } |
2224 | ||
ba395927 KA |
2225 | drhd = dmar_find_matched_drhd_unit(pdev); |
2226 | if (!drhd) { | |
2227 | printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n", | |
2228 | pci_name(pdev)); | |
2229 | return NULL; | |
2230 | } | |
2231 | iommu = drhd->iommu; | |
2232 | ||
745f2586 | 2233 | /* Allocate and intialize new domain for the device */ |
92d03cc8 | 2234 | domain = alloc_domain(false); |
745f2586 JL |
2235 | if (!domain) |
2236 | goto error; | |
2237 | if (iommu_attach_domain(domain, iommu)) { | |
2fe9723d | 2238 | free_domain_mem(domain); |
ba395927 | 2239 | goto error; |
2c2e2c38 | 2240 | } |
e85bb5d4 JL |
2241 | free = domain; |
2242 | if (domain_init(domain, gaw)) | |
ba395927 | 2243 | goto error; |
ba395927 KA |
2244 | |
2245 | /* register pcie-to-pci device */ | |
2246 | if (dev_tmp) { | |
b718cd3d DW |
2247 | domain = dmar_insert_dev_info(segment, bus, devfn, NULL, domain); |
2248 | if (!domain) | |
ba395927 | 2249 | goto error; |
ba395927 KA |
2250 | } |
2251 | ||
2252 | found_domain: | |
b718cd3d DW |
2253 | domain = dmar_insert_dev_info(segment, pdev->bus->number, pdev->devfn, |
2254 | &pdev->dev, domain); | |
ba395927 | 2255 | error: |
b718cd3d | 2256 | if (free != domain) |
e85bb5d4 | 2257 | domain_exit(free); |
b718cd3d DW |
2258 | |
2259 | return domain; | |
ba395927 KA |
2260 | } |
2261 | ||
2c2e2c38 | 2262 | static int iommu_identity_mapping; |
e0fc7e0b DW |
2263 | #define IDENTMAP_ALL 1 |
2264 | #define IDENTMAP_GFX 2 | |
2265 | #define IDENTMAP_AZALIA 4 | |
2c2e2c38 | 2266 | |
b213203e DW |
2267 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
2268 | unsigned long long start, | |
2269 | unsigned long long end) | |
ba395927 | 2270 | { |
c5395d5c DW |
2271 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
2272 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; | |
2273 | ||
2274 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), | |
2275 | dma_to_mm_pfn(last_vpfn))) { | |
ba395927 | 2276 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
b213203e | 2277 | return -ENOMEM; |
ba395927 KA |
2278 | } |
2279 | ||
c5395d5c DW |
2280 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
2281 | start, end, domain->id); | |
ba395927 KA |
2282 | /* |
2283 | * RMRR range might have overlap with physical memory range, | |
2284 | * clear it first | |
2285 | */ | |
c5395d5c | 2286 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
ba395927 | 2287 | |
c5395d5c DW |
2288 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
2289 | last_vpfn - first_vpfn + 1, | |
61df7443 | 2290 | DMA_PTE_READ|DMA_PTE_WRITE); |
b213203e DW |
2291 | } |
2292 | ||
2293 | static int iommu_prepare_identity_map(struct pci_dev *pdev, | |
2294 | unsigned long long start, | |
2295 | unsigned long long end) | |
2296 | { | |
2297 | struct dmar_domain *domain; | |
2298 | int ret; | |
2299 | ||
c7ab48d2 | 2300 | domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
b213203e DW |
2301 | if (!domain) |
2302 | return -ENOMEM; | |
2303 | ||
19943b0e DW |
2304 | /* For _hardware_ passthrough, don't bother. But for software |
2305 | passthrough, we do it anyway -- it may indicate a memory | |
2306 | range which is reserved in E820, so which didn't get set | |
2307 | up to start with in si_domain */ | |
2308 | if (domain == si_domain && hw_pass_through) { | |
2309 | printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", | |
2310 | pci_name(pdev), start, end); | |
2311 | return 0; | |
2312 | } | |
2313 | ||
2314 | printk(KERN_INFO | |
2315 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", | |
2316 | pci_name(pdev), start, end); | |
2ff729f5 | 2317 | |
5595b528 DW |
2318 | if (end < start) { |
2319 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" | |
2320 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2321 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2322 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2323 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2324 | ret = -EIO; | |
2325 | goto error; | |
2326 | } | |
2327 | ||
2ff729f5 DW |
2328 | if (end >> agaw_to_width(domain->agaw)) { |
2329 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" | |
2330 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
2331 | agaw_to_width(domain->agaw), | |
2332 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
2333 | dmi_get_system_info(DMI_BIOS_VERSION), | |
2334 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
2335 | ret = -EIO; | |
2336 | goto error; | |
2337 | } | |
19943b0e | 2338 | |
b213203e | 2339 | ret = iommu_domain_identity_map(domain, start, end); |
ba395927 KA |
2340 | if (ret) |
2341 | goto error; | |
2342 | ||
2343 | /* context entry init */ | |
4ed0d3e6 | 2344 | ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
b213203e DW |
2345 | if (ret) |
2346 | goto error; | |
2347 | ||
2348 | return 0; | |
2349 | ||
2350 | error: | |
ba395927 KA |
2351 | domain_exit(domain); |
2352 | return ret; | |
ba395927 KA |
2353 | } |
2354 | ||
2355 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, | |
2356 | struct pci_dev *pdev) | |
2357 | { | |
358dd8ac | 2358 | if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
ba395927 KA |
2359 | return 0; |
2360 | return iommu_prepare_identity_map(pdev, rmrr->base_address, | |
70e535d1 | 2361 | rmrr->end_address); |
ba395927 KA |
2362 | } |
2363 | ||
d3f13810 | 2364 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
49a0429e KA |
2365 | static inline void iommu_prepare_isa(void) |
2366 | { | |
2367 | struct pci_dev *pdev; | |
2368 | int ret; | |
2369 | ||
2370 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
2371 | if (!pdev) | |
2372 | return; | |
2373 | ||
c7ab48d2 | 2374 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
70e535d1 | 2375 | ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024 - 1); |
49a0429e KA |
2376 | |
2377 | if (ret) | |
c7ab48d2 DW |
2378 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
2379 | "floppy might not work\n"); | |
49a0429e KA |
2380 | |
2381 | } | |
2382 | #else | |
2383 | static inline void iommu_prepare_isa(void) | |
2384 | { | |
2385 | return; | |
2386 | } | |
d3f13810 | 2387 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
49a0429e | 2388 | |
2c2e2c38 | 2389 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
c7ab48d2 | 2390 | |
071e1374 | 2391 | static int __init si_domain_init(int hw) |
2c2e2c38 FY |
2392 | { |
2393 | struct dmar_drhd_unit *drhd; | |
2394 | struct intel_iommu *iommu; | |
c7ab48d2 | 2395 | int nid, ret = 0; |
2c2e2c38 | 2396 | |
92d03cc8 | 2397 | si_domain = alloc_domain(false); |
2c2e2c38 FY |
2398 | if (!si_domain) |
2399 | return -EFAULT; | |
2400 | ||
92d03cc8 JL |
2401 | si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY; |
2402 | ||
2c2e2c38 FY |
2403 | for_each_active_iommu(iommu, drhd) { |
2404 | ret = iommu_attach_domain(si_domain, iommu); | |
2405 | if (ret) { | |
2406 | domain_exit(si_domain); | |
2407 | return -EFAULT; | |
2408 | } | |
2409 | } | |
2410 | ||
2411 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { | |
2412 | domain_exit(si_domain); | |
2413 | return -EFAULT; | |
2414 | } | |
2415 | ||
9544c003 JL |
2416 | pr_debug("IOMMU: identity mapping domain is domain %d\n", |
2417 | si_domain->id); | |
2c2e2c38 | 2418 | |
19943b0e DW |
2419 | if (hw) |
2420 | return 0; | |
2421 | ||
c7ab48d2 | 2422 | for_each_online_node(nid) { |
5dfe8660 TH |
2423 | unsigned long start_pfn, end_pfn; |
2424 | int i; | |
2425 | ||
2426 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { | |
2427 | ret = iommu_domain_identity_map(si_domain, | |
2428 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); | |
2429 | if (ret) | |
2430 | return ret; | |
2431 | } | |
c7ab48d2 DW |
2432 | } |
2433 | ||
2c2e2c38 FY |
2434 | return 0; |
2435 | } | |
2436 | ||
2c2e2c38 FY |
2437 | static int identity_mapping(struct pci_dev *pdev) |
2438 | { | |
2439 | struct device_domain_info *info; | |
2440 | ||
2441 | if (likely(!iommu_identity_mapping)) | |
2442 | return 0; | |
2443 | ||
cb452a40 MT |
2444 | info = pdev->dev.archdata.iommu; |
2445 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) | |
2446 | return (info->domain == si_domain); | |
2c2e2c38 | 2447 | |
2c2e2c38 FY |
2448 | return 0; |
2449 | } | |
2450 | ||
2451 | static int domain_add_dev_info(struct dmar_domain *domain, | |
5fe60f4e DW |
2452 | struct pci_dev *pdev, |
2453 | int translation) | |
2c2e2c38 | 2454 | { |
0ac72664 | 2455 | struct dmar_domain *ndomain; |
5fe60f4e | 2456 | int ret; |
2c2e2c38 | 2457 | |
0ac72664 DW |
2458 | ndomain = dmar_insert_dev_info(pci_domain_nr(pdev->bus), |
2459 | pdev->bus->number, pdev->devfn, | |
2460 | &pdev->dev, domain); | |
2461 | if (ndomain != domain) | |
2462 | return -EBUSY; | |
2c2e2c38 | 2463 | |
e2ad23d0 DW |
2464 | ret = domain_context_mapping(domain, pdev, translation); |
2465 | if (ret) { | |
e2f8c5f6 | 2466 | domain_remove_one_dev_info(domain, pdev); |
e2ad23d0 DW |
2467 | return ret; |
2468 | } | |
2469 | ||
2c2e2c38 FY |
2470 | return 0; |
2471 | } | |
2472 | ||
ea2447f7 TM |
2473 | static bool device_has_rmrr(struct pci_dev *dev) |
2474 | { | |
2475 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2476 | struct device *tmp; |
ea2447f7 TM |
2477 | int i; |
2478 | ||
0e242612 | 2479 | rcu_read_lock(); |
ea2447f7 | 2480 | for_each_rmrr_units(rmrr) { |
b683b230 JL |
2481 | /* |
2482 | * Return TRUE if this RMRR contains the device that | |
2483 | * is passed in. | |
2484 | */ | |
2485 | for_each_active_dev_scope(rmrr->devices, | |
2486 | rmrr->devices_cnt, i, tmp) | |
832bd858 | 2487 | if (tmp == &dev->dev) { |
0e242612 | 2488 | rcu_read_unlock(); |
ea2447f7 | 2489 | return true; |
b683b230 | 2490 | } |
ea2447f7 | 2491 | } |
0e242612 | 2492 | rcu_read_unlock(); |
ea2447f7 TM |
2493 | return false; |
2494 | } | |
2495 | ||
6941af28 DW |
2496 | static int iommu_should_identity_map(struct pci_dev *pdev, int startup) |
2497 | { | |
ea2447f7 TM |
2498 | |
2499 | /* | |
2500 | * We want to prevent any device associated with an RMRR from | |
2501 | * getting placed into the SI Domain. This is done because | |
2502 | * problems exist when devices are moved in and out of domains | |
2503 | * and their respective RMRR info is lost. We exempt USB devices | |
2504 | * from this process due to their usage of RMRRs that are known | |
2505 | * to not be needed after BIOS hand-off to OS. | |
2506 | */ | |
2507 | if (device_has_rmrr(pdev) && | |
2508 | (pdev->class >> 8) != PCI_CLASS_SERIAL_USB) | |
2509 | return 0; | |
2510 | ||
e0fc7e0b DW |
2511 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
2512 | return 1; | |
2513 | ||
2514 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) | |
2515 | return 1; | |
2516 | ||
2517 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) | |
2518 | return 0; | |
6941af28 | 2519 | |
3dfc813d DW |
2520 | /* |
2521 | * We want to start off with all devices in the 1:1 domain, and | |
2522 | * take them out later if we find they can't access all of memory. | |
2523 | * | |
2524 | * However, we can't do this for PCI devices behind bridges, | |
2525 | * because all PCI devices behind the same bridge will end up | |
2526 | * with the same source-id on their transactions. | |
2527 | * | |
2528 | * Practically speaking, we can't change things around for these | |
2529 | * devices at run-time, because we can't be sure there'll be no | |
2530 | * DMA transactions in flight for any of their siblings. | |
2531 | * | |
2532 | * So PCI devices (unless they're on the root bus) as well as | |
2533 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of | |
2534 | * the 1:1 domain, just in _case_ one of their siblings turns out | |
2535 | * not to be able to map all of memory. | |
2536 | */ | |
5f4d91a1 | 2537 | if (!pci_is_pcie(pdev)) { |
3dfc813d DW |
2538 | if (!pci_is_root_bus(pdev->bus)) |
2539 | return 0; | |
2540 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) | |
2541 | return 0; | |
62f87c0e | 2542 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) |
3dfc813d DW |
2543 | return 0; |
2544 | ||
2545 | /* | |
2546 | * At boot time, we don't yet know if devices will be 64-bit capable. | |
2547 | * Assume that they will -- if they turn out not to be, then we can | |
2548 | * take them out of the 1:1 domain later. | |
2549 | */ | |
8fcc5372 CW |
2550 | if (!startup) { |
2551 | /* | |
2552 | * If the device's dma_mask is less than the system's memory | |
2553 | * size then this is not a candidate for identity mapping. | |
2554 | */ | |
2555 | u64 dma_mask = pdev->dma_mask; | |
2556 | ||
2557 | if (pdev->dev.coherent_dma_mask && | |
2558 | pdev->dev.coherent_dma_mask < dma_mask) | |
2559 | dma_mask = pdev->dev.coherent_dma_mask; | |
2560 | ||
2561 | return dma_mask >= dma_get_required_mask(&pdev->dev); | |
2562 | } | |
6941af28 DW |
2563 | |
2564 | return 1; | |
2565 | } | |
2566 | ||
071e1374 | 2567 | static int __init iommu_prepare_static_identity_mapping(int hw) |
2c2e2c38 | 2568 | { |
2c2e2c38 FY |
2569 | struct pci_dev *pdev = NULL; |
2570 | int ret; | |
2571 | ||
19943b0e | 2572 | ret = si_domain_init(hw); |
2c2e2c38 FY |
2573 | if (ret) |
2574 | return -EFAULT; | |
2575 | ||
2c2e2c38 | 2576 | for_each_pci_dev(pdev) { |
6941af28 | 2577 | if (iommu_should_identity_map(pdev, 1)) { |
5fe60f4e | 2578 | ret = domain_add_dev_info(si_domain, pdev, |
eae460b6 MT |
2579 | hw ? CONTEXT_TT_PASS_THROUGH : |
2580 | CONTEXT_TT_MULTI_LEVEL); | |
2581 | if (ret) { | |
2582 | /* device not associated with an iommu */ | |
2583 | if (ret == -ENODEV) | |
2584 | continue; | |
62edf5dc | 2585 | return ret; |
eae460b6 MT |
2586 | } |
2587 | pr_info("IOMMU: %s identity mapping for device %s\n", | |
2588 | hw ? "hardware" : "software", pci_name(pdev)); | |
62edf5dc | 2589 | } |
2c2e2c38 FY |
2590 | } |
2591 | ||
2592 | return 0; | |
2593 | } | |
2594 | ||
b779260b | 2595 | static int __init init_dmars(void) |
ba395927 KA |
2596 | { |
2597 | struct dmar_drhd_unit *drhd; | |
2598 | struct dmar_rmrr_unit *rmrr; | |
832bd858 | 2599 | struct device *dev; |
ba395927 | 2600 | struct intel_iommu *iommu; |
9d783ba0 | 2601 | int i, ret; |
2c2e2c38 | 2602 | |
ba395927 KA |
2603 | /* |
2604 | * for each drhd | |
2605 | * allocate root | |
2606 | * initialize and program root entry to not present | |
2607 | * endfor | |
2608 | */ | |
2609 | for_each_drhd_unit(drhd) { | |
5e0d2a6f | 2610 | /* |
2611 | * lock not needed as this is only incremented in the single | |
2612 | * threaded kernel __init code path all other access are read | |
2613 | * only | |
2614 | */ | |
1b198bb0 MT |
2615 | if (g_num_of_iommus < IOMMU_UNITS_SUPPORTED) { |
2616 | g_num_of_iommus++; | |
2617 | continue; | |
2618 | } | |
2619 | printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n", | |
2620 | IOMMU_UNITS_SUPPORTED); | |
5e0d2a6f | 2621 | } |
2622 | ||
d9630fe9 WH |
2623 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
2624 | GFP_KERNEL); | |
2625 | if (!g_iommus) { | |
2626 | printk(KERN_ERR "Allocating global iommu array failed\n"); | |
2627 | ret = -ENOMEM; | |
2628 | goto error; | |
2629 | } | |
2630 | ||
80b20dd8 | 2631 | deferred_flush = kzalloc(g_num_of_iommus * |
2632 | sizeof(struct deferred_flush_tables), GFP_KERNEL); | |
2633 | if (!deferred_flush) { | |
5e0d2a6f | 2634 | ret = -ENOMEM; |
989d51fc | 2635 | goto free_g_iommus; |
5e0d2a6f | 2636 | } |
2637 | ||
7c919779 | 2638 | for_each_active_iommu(iommu, drhd) { |
d9630fe9 | 2639 | g_iommus[iommu->seq_id] = iommu; |
ba395927 | 2640 | |
e61d98d8 SS |
2641 | ret = iommu_init_domains(iommu); |
2642 | if (ret) | |
989d51fc | 2643 | goto free_iommu; |
e61d98d8 | 2644 | |
ba395927 KA |
2645 | /* |
2646 | * TBD: | |
2647 | * we could share the same root & context tables | |
25985edc | 2648 | * among all IOMMU's. Need to Split it later. |
ba395927 KA |
2649 | */ |
2650 | ret = iommu_alloc_root_entry(iommu); | |
2651 | if (ret) { | |
2652 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); | |
989d51fc | 2653 | goto free_iommu; |
ba395927 | 2654 | } |
4ed0d3e6 | 2655 | if (!ecap_pass_through(iommu->ecap)) |
19943b0e | 2656 | hw_pass_through = 0; |
ba395927 KA |
2657 | } |
2658 | ||
1531a6a6 SS |
2659 | /* |
2660 | * Start from the sane iommu hardware state. | |
2661 | */ | |
7c919779 | 2662 | for_each_active_iommu(iommu, drhd) { |
1531a6a6 SS |
2663 | /* |
2664 | * If the queued invalidation is already initialized by us | |
2665 | * (for example, while enabling interrupt-remapping) then | |
2666 | * we got the things already rolling from a sane state. | |
2667 | */ | |
2668 | if (iommu->qi) | |
2669 | continue; | |
2670 | ||
2671 | /* | |
2672 | * Clear any previous faults. | |
2673 | */ | |
2674 | dmar_fault(-1, iommu); | |
2675 | /* | |
2676 | * Disable queued invalidation if supported and already enabled | |
2677 | * before OS handover. | |
2678 | */ | |
2679 | dmar_disable_qi(iommu); | |
2680 | } | |
2681 | ||
7c919779 | 2682 | for_each_active_iommu(iommu, drhd) { |
a77b67d4 YS |
2683 | if (dmar_enable_qi(iommu)) { |
2684 | /* | |
2685 | * Queued Invalidate not enabled, use Register Based | |
2686 | * Invalidate | |
2687 | */ | |
2688 | iommu->flush.flush_context = __iommu_flush_context; | |
2689 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; | |
680a7524 | 2690 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " |
b4e0f9eb | 2691 | "invalidation\n", |
680a7524 | 2692 | iommu->seq_id, |
b4e0f9eb | 2693 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2694 | } else { |
2695 | iommu->flush.flush_context = qi_flush_context; | |
2696 | iommu->flush.flush_iotlb = qi_flush_iotlb; | |
680a7524 | 2697 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " |
b4e0f9eb | 2698 | "invalidation\n", |
680a7524 | 2699 | iommu->seq_id, |
b4e0f9eb | 2700 | (unsigned long long)drhd->reg_base_addr); |
a77b67d4 YS |
2701 | } |
2702 | } | |
2703 | ||
19943b0e | 2704 | if (iommu_pass_through) |
e0fc7e0b DW |
2705 | iommu_identity_mapping |= IDENTMAP_ALL; |
2706 | ||
d3f13810 | 2707 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
e0fc7e0b | 2708 | iommu_identity_mapping |= IDENTMAP_GFX; |
19943b0e | 2709 | #endif |
e0fc7e0b DW |
2710 | |
2711 | check_tylersburg_isoch(); | |
2712 | ||
ba395927 | 2713 | /* |
19943b0e DW |
2714 | * If pass through is not set or not enabled, setup context entries for |
2715 | * identity mappings for rmrr, gfx, and isa and may fall back to static | |
2716 | * identity mapping if iommu_identity_mapping is set. | |
ba395927 | 2717 | */ |
19943b0e DW |
2718 | if (iommu_identity_mapping) { |
2719 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); | |
4ed0d3e6 | 2720 | if (ret) { |
19943b0e | 2721 | printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); |
989d51fc | 2722 | goto free_iommu; |
ba395927 KA |
2723 | } |
2724 | } | |
ba395927 | 2725 | /* |
19943b0e DW |
2726 | * For each rmrr |
2727 | * for each dev attached to rmrr | |
2728 | * do | |
2729 | * locate drhd for dev, alloc domain for dev | |
2730 | * allocate free domain | |
2731 | * allocate page table entries for rmrr | |
2732 | * if context not allocated for bus | |
2733 | * allocate and init context | |
2734 | * set present in root table for this bus | |
2735 | * init context with domain, translation etc | |
2736 | * endfor | |
2737 | * endfor | |
ba395927 | 2738 | */ |
19943b0e DW |
2739 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
2740 | for_each_rmrr_units(rmrr) { | |
b683b230 JL |
2741 | /* some BIOS lists non-exist devices in DMAR table. */ |
2742 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, | |
832bd858 DW |
2743 | i, dev) { |
2744 | if (!dev_is_pci(dev)) | |
2745 | continue; | |
2746 | ret = iommu_prepare_rmrr_dev(rmrr, to_pci_dev(dev)); | |
19943b0e DW |
2747 | if (ret) |
2748 | printk(KERN_ERR | |
2749 | "IOMMU: mapping reserved region failed\n"); | |
ba395927 | 2750 | } |
4ed0d3e6 | 2751 | } |
49a0429e | 2752 | |
19943b0e DW |
2753 | iommu_prepare_isa(); |
2754 | ||
ba395927 KA |
2755 | /* |
2756 | * for each drhd | |
2757 | * enable fault log | |
2758 | * global invalidate context cache | |
2759 | * global invalidate iotlb | |
2760 | * enable translation | |
2761 | */ | |
7c919779 | 2762 | for_each_iommu(iommu, drhd) { |
51a63e67 JC |
2763 | if (drhd->ignored) { |
2764 | /* | |
2765 | * we always have to disable PMRs or DMA may fail on | |
2766 | * this device | |
2767 | */ | |
2768 | if (force_on) | |
7c919779 | 2769 | iommu_disable_protect_mem_regions(iommu); |
ba395927 | 2770 | continue; |
51a63e67 | 2771 | } |
ba395927 KA |
2772 | |
2773 | iommu_flush_write_buffer(iommu); | |
2774 | ||
3460a6d9 KA |
2775 | ret = dmar_set_interrupt(iommu); |
2776 | if (ret) | |
989d51fc | 2777 | goto free_iommu; |
3460a6d9 | 2778 | |
ba395927 KA |
2779 | iommu_set_root_entry(iommu); |
2780 | ||
4c25a2c1 | 2781 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
1f0ef2aa | 2782 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
f8bab735 | 2783 | |
ba395927 KA |
2784 | ret = iommu_enable_translation(iommu); |
2785 | if (ret) | |
989d51fc | 2786 | goto free_iommu; |
b94996c9 DW |
2787 | |
2788 | iommu_disable_protect_mem_regions(iommu); | |
ba395927 KA |
2789 | } |
2790 | ||
2791 | return 0; | |
989d51fc JL |
2792 | |
2793 | free_iommu: | |
7c919779 | 2794 | for_each_active_iommu(iommu, drhd) |
a868e6b7 | 2795 | free_dmar_iommu(iommu); |
9bdc531e | 2796 | kfree(deferred_flush); |
989d51fc | 2797 | free_g_iommus: |
d9630fe9 | 2798 | kfree(g_iommus); |
989d51fc | 2799 | error: |
ba395927 KA |
2800 | return ret; |
2801 | } | |
2802 | ||
5a5e02a6 | 2803 | /* This takes a number of _MM_ pages, not VTD pages */ |
875764de DW |
2804 | static struct iova *intel_alloc_iova(struct device *dev, |
2805 | struct dmar_domain *domain, | |
2806 | unsigned long nrpages, uint64_t dma_mask) | |
ba395927 | 2807 | { |
ba395927 | 2808 | struct pci_dev *pdev = to_pci_dev(dev); |
ba395927 | 2809 | struct iova *iova = NULL; |
ba395927 | 2810 | |
875764de DW |
2811 | /* Restrict dma_mask to the width that the iommu can handle */ |
2812 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); | |
2813 | ||
2814 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { | |
ba395927 KA |
2815 | /* |
2816 | * First try to allocate an io virtual address in | |
284901a9 | 2817 | * DMA_BIT_MASK(32) and if that fails then try allocating |
3609801e | 2818 | * from higher range |
ba395927 | 2819 | */ |
875764de DW |
2820 | iova = alloc_iova(&domain->iovad, nrpages, |
2821 | IOVA_PFN(DMA_BIT_MASK(32)), 1); | |
2822 | if (iova) | |
2823 | return iova; | |
2824 | } | |
2825 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); | |
2826 | if (unlikely(!iova)) { | |
2827 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", | |
2828 | nrpages, pci_name(pdev)); | |
f76aec76 KA |
2829 | return NULL; |
2830 | } | |
2831 | ||
2832 | return iova; | |
2833 | } | |
2834 | ||
147202aa | 2835 | static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev) |
f76aec76 KA |
2836 | { |
2837 | struct dmar_domain *domain; | |
2838 | int ret; | |
2839 | ||
2840 | domain = get_domain_for_dev(pdev, | |
2841 | DEFAULT_DOMAIN_ADDRESS_WIDTH); | |
2842 | if (!domain) { | |
2843 | printk(KERN_ERR | |
2844 | "Allocating domain for %s failed", pci_name(pdev)); | |
4fe05bbc | 2845 | return NULL; |
ba395927 KA |
2846 | } |
2847 | ||
2848 | /* make sure context mapping is ok */ | |
5331fe6f | 2849 | if (unlikely(!domain_context_mapped(pdev))) { |
4ed0d3e6 FY |
2850 | ret = domain_context_mapping(domain, pdev, |
2851 | CONTEXT_TT_MULTI_LEVEL); | |
f76aec76 KA |
2852 | if (ret) { |
2853 | printk(KERN_ERR | |
2854 | "Domain context map for %s failed", | |
2855 | pci_name(pdev)); | |
4fe05bbc | 2856 | return NULL; |
f76aec76 | 2857 | } |
ba395927 KA |
2858 | } |
2859 | ||
f76aec76 KA |
2860 | return domain; |
2861 | } | |
2862 | ||
147202aa DW |
2863 | static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev) |
2864 | { | |
2865 | struct device_domain_info *info; | |
2866 | ||
2867 | /* No lock here, assumes no domain exit in normal case */ | |
2868 | info = dev->dev.archdata.iommu; | |
2869 | if (likely(info)) | |
2870 | return info->domain; | |
2871 | ||
2872 | return __get_valid_domain_for_dev(dev); | |
2873 | } | |
2874 | ||
3d89194a | 2875 | static int iommu_dummy(struct device *dev) |
2c2e2c38 | 2876 | { |
3d89194a | 2877 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
2c2e2c38 FY |
2878 | } |
2879 | ||
2880 | /* Check if the pdev needs to go through non-identity map and unmap process.*/ | |
73676832 | 2881 | static int iommu_no_mapping(struct device *dev) |
2c2e2c38 | 2882 | { |
73676832 | 2883 | struct pci_dev *pdev; |
2c2e2c38 FY |
2884 | int found; |
2885 | ||
dbad0864 | 2886 | if (unlikely(!dev_is_pci(dev))) |
73676832 DW |
2887 | return 1; |
2888 | ||
3d89194a | 2889 | if (iommu_dummy(dev)) |
1e4c64c4 DW |
2890 | return 1; |
2891 | ||
2c2e2c38 | 2892 | if (!iommu_identity_mapping) |
1e4c64c4 | 2893 | return 0; |
2c2e2c38 | 2894 | |
3d89194a | 2895 | pdev = to_pci_dev(dev); |
2c2e2c38 FY |
2896 | found = identity_mapping(pdev); |
2897 | if (found) { | |
6941af28 | 2898 | if (iommu_should_identity_map(pdev, 0)) |
2c2e2c38 FY |
2899 | return 1; |
2900 | else { | |
2901 | /* | |
2902 | * 32 bit DMA is removed from si_domain and fall back | |
2903 | * to non-identity mapping. | |
2904 | */ | |
2905 | domain_remove_one_dev_info(si_domain, pdev); | |
2906 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", | |
2907 | pci_name(pdev)); | |
2908 | return 0; | |
2909 | } | |
2910 | } else { | |
2911 | /* | |
2912 | * In case of a detached 64 bit DMA device from vm, the device | |
2913 | * is put into si_domain for identity mapping. | |
2914 | */ | |
6941af28 | 2915 | if (iommu_should_identity_map(pdev, 0)) { |
2c2e2c38 | 2916 | int ret; |
5fe60f4e DW |
2917 | ret = domain_add_dev_info(si_domain, pdev, |
2918 | hw_pass_through ? | |
2919 | CONTEXT_TT_PASS_THROUGH : | |
2920 | CONTEXT_TT_MULTI_LEVEL); | |
2c2e2c38 FY |
2921 | if (!ret) { |
2922 | printk(KERN_INFO "64bit %s uses identity mapping\n", | |
2923 | pci_name(pdev)); | |
2924 | return 1; | |
2925 | } | |
2926 | } | |
2927 | } | |
2928 | ||
1e4c64c4 | 2929 | return 0; |
2c2e2c38 FY |
2930 | } |
2931 | ||
bb9e6d65 FT |
2932 | static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr, |
2933 | size_t size, int dir, u64 dma_mask) | |
f76aec76 KA |
2934 | { |
2935 | struct pci_dev *pdev = to_pci_dev(hwdev); | |
f76aec76 | 2936 | struct dmar_domain *domain; |
5b6985ce | 2937 | phys_addr_t start_paddr; |
f76aec76 KA |
2938 | struct iova *iova; |
2939 | int prot = 0; | |
6865f0d1 | 2940 | int ret; |
8c11e798 | 2941 | struct intel_iommu *iommu; |
33041ec0 | 2942 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
f76aec76 KA |
2943 | |
2944 | BUG_ON(dir == DMA_NONE); | |
2c2e2c38 | 2945 | |
73676832 | 2946 | if (iommu_no_mapping(hwdev)) |
6865f0d1 | 2947 | return paddr; |
f76aec76 KA |
2948 | |
2949 | domain = get_valid_domain_for_dev(pdev); | |
2950 | if (!domain) | |
2951 | return 0; | |
2952 | ||
8c11e798 | 2953 | iommu = domain_get_iommu(domain); |
88cb6a74 | 2954 | size = aligned_nrpages(paddr, size); |
f76aec76 | 2955 | |
c681d0ba | 2956 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), dma_mask); |
f76aec76 KA |
2957 | if (!iova) |
2958 | goto error; | |
2959 | ||
ba395927 KA |
2960 | /* |
2961 | * Check if DMAR supports zero-length reads on write only | |
2962 | * mappings.. | |
2963 | */ | |
2964 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 2965 | !cap_zlr(iommu->cap)) |
ba395927 KA |
2966 | prot |= DMA_PTE_READ; |
2967 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
2968 | prot |= DMA_PTE_WRITE; | |
2969 | /* | |
6865f0d1 | 2970 | * paddr - (paddr + size) might be partial page, we should map the whole |
ba395927 | 2971 | * page. Note: if two part of one page are separately mapped, we |
6865f0d1 | 2972 | * might have two guest_addr mapping to the same host paddr, but this |
ba395927 KA |
2973 | * is not a big problem |
2974 | */ | |
0ab36de2 | 2975 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
33041ec0 | 2976 | mm_to_dma_pfn(paddr_pfn), size, prot); |
ba395927 KA |
2977 | if (ret) |
2978 | goto error; | |
2979 | ||
1f0ef2aa DW |
2980 | /* it's a non-present to present mapping. Only flush if caching mode */ |
2981 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 2982 | iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1); |
1f0ef2aa | 2983 | else |
8c11e798 | 2984 | iommu_flush_write_buffer(iommu); |
f76aec76 | 2985 | |
03d6a246 DW |
2986 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
2987 | start_paddr += paddr & ~PAGE_MASK; | |
2988 | return start_paddr; | |
ba395927 | 2989 | |
ba395927 | 2990 | error: |
f76aec76 KA |
2991 | if (iova) |
2992 | __free_iova(&domain->iovad, iova); | |
4cf2e75d | 2993 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
5b6985ce | 2994 | pci_name(pdev), size, (unsigned long long)paddr, dir); |
ba395927 KA |
2995 | return 0; |
2996 | } | |
2997 | ||
ffbbef5c FT |
2998 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
2999 | unsigned long offset, size_t size, | |
3000 | enum dma_data_direction dir, | |
3001 | struct dma_attrs *attrs) | |
bb9e6d65 | 3002 | { |
ffbbef5c FT |
3003 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
3004 | dir, to_pci_dev(dev)->dma_mask); | |
bb9e6d65 FT |
3005 | } |
3006 | ||
5e0d2a6f | 3007 | static void flush_unmaps(void) |
3008 | { | |
80b20dd8 | 3009 | int i, j; |
5e0d2a6f | 3010 | |
5e0d2a6f | 3011 | timer_on = 0; |
3012 | ||
3013 | /* just flush them all */ | |
3014 | for (i = 0; i < g_num_of_iommus; i++) { | |
a2bb8459 WH |
3015 | struct intel_iommu *iommu = g_iommus[i]; |
3016 | if (!iommu) | |
3017 | continue; | |
c42d9f32 | 3018 | |
9dd2fe89 YZ |
3019 | if (!deferred_flush[i].next) |
3020 | continue; | |
3021 | ||
78d5f0f5 NA |
3022 | /* In caching mode, global flushes turn emulation expensive */ |
3023 | if (!cap_caching_mode(iommu->cap)) | |
3024 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, | |
93a23a72 | 3025 | DMA_TLB_GLOBAL_FLUSH); |
9dd2fe89 | 3026 | for (j = 0; j < deferred_flush[i].next; j++) { |
93a23a72 YZ |
3027 | unsigned long mask; |
3028 | struct iova *iova = deferred_flush[i].iova[j]; | |
78d5f0f5 NA |
3029 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
3030 | ||
3031 | /* On real hardware multiple invalidations are expensive */ | |
3032 | if (cap_caching_mode(iommu->cap)) | |
3033 | iommu_flush_iotlb_psi(iommu, domain->id, | |
ea8ea460 DW |
3034 | iova->pfn_lo, iova->pfn_hi - iova->pfn_lo + 1, |
3035 | !deferred_flush[i].freelist[j], 0); | |
78d5f0f5 NA |
3036 | else { |
3037 | mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1)); | |
3038 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], | |
3039 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); | |
3040 | } | |
93a23a72 | 3041 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
ea8ea460 DW |
3042 | if (deferred_flush[i].freelist[j]) |
3043 | dma_free_pagelist(deferred_flush[i].freelist[j]); | |
80b20dd8 | 3044 | } |
9dd2fe89 | 3045 | deferred_flush[i].next = 0; |
5e0d2a6f | 3046 | } |
3047 | ||
5e0d2a6f | 3048 | list_size = 0; |
5e0d2a6f | 3049 | } |
3050 | ||
3051 | static void flush_unmaps_timeout(unsigned long data) | |
3052 | { | |
80b20dd8 | 3053 | unsigned long flags; |
3054 | ||
3055 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
5e0d2a6f | 3056 | flush_unmaps(); |
80b20dd8 | 3057 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
5e0d2a6f | 3058 | } |
3059 | ||
ea8ea460 | 3060 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
5e0d2a6f | 3061 | { |
3062 | unsigned long flags; | |
80b20dd8 | 3063 | int next, iommu_id; |
8c11e798 | 3064 | struct intel_iommu *iommu; |
5e0d2a6f | 3065 | |
3066 | spin_lock_irqsave(&async_umap_flush_lock, flags); | |
80b20dd8 | 3067 | if (list_size == HIGH_WATER_MARK) |
3068 | flush_unmaps(); | |
3069 | ||
8c11e798 WH |
3070 | iommu = domain_get_iommu(dom); |
3071 | iommu_id = iommu->seq_id; | |
c42d9f32 | 3072 | |
80b20dd8 | 3073 | next = deferred_flush[iommu_id].next; |
3074 | deferred_flush[iommu_id].domain[next] = dom; | |
3075 | deferred_flush[iommu_id].iova[next] = iova; | |
ea8ea460 | 3076 | deferred_flush[iommu_id].freelist[next] = freelist; |
80b20dd8 | 3077 | deferred_flush[iommu_id].next++; |
5e0d2a6f | 3078 | |
3079 | if (!timer_on) { | |
3080 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); | |
3081 | timer_on = 1; | |
3082 | } | |
3083 | list_size++; | |
3084 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); | |
3085 | } | |
3086 | ||
ffbbef5c FT |
3087 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
3088 | size_t size, enum dma_data_direction dir, | |
3089 | struct dma_attrs *attrs) | |
ba395927 | 3090 | { |
ba395927 | 3091 | struct pci_dev *pdev = to_pci_dev(dev); |
f76aec76 | 3092 | struct dmar_domain *domain; |
d794dc9b | 3093 | unsigned long start_pfn, last_pfn; |
ba395927 | 3094 | struct iova *iova; |
8c11e798 | 3095 | struct intel_iommu *iommu; |
ea8ea460 | 3096 | struct page *freelist; |
ba395927 | 3097 | |
73676832 | 3098 | if (iommu_no_mapping(dev)) |
f76aec76 | 3099 | return; |
2c2e2c38 | 3100 | |
1525a29a | 3101 | domain = find_domain(dev); |
ba395927 KA |
3102 | BUG_ON(!domain); |
3103 | ||
8c11e798 WH |
3104 | iommu = domain_get_iommu(domain); |
3105 | ||
ba395927 | 3106 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
85b98276 DW |
3107 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
3108 | (unsigned long long)dev_addr)) | |
ba395927 | 3109 | return; |
ba395927 | 3110 | |
d794dc9b DW |
3111 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3112 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
ba395927 | 3113 | |
d794dc9b DW |
3114 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
3115 | pci_name(pdev), start_pfn, last_pfn); | |
ba395927 | 3116 | |
ea8ea460 | 3117 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
d794dc9b | 3118 | |
5e0d2a6f | 3119 | if (intel_iommu_strict) { |
03d6a246 | 3120 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
ea8ea460 | 3121 | last_pfn - start_pfn + 1, !freelist, 0); |
5e0d2a6f | 3122 | /* free iova */ |
3123 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3124 | dma_free_pagelist(freelist); |
5e0d2a6f | 3125 | } else { |
ea8ea460 | 3126 | add_unmap(domain, iova, freelist); |
5e0d2a6f | 3127 | /* |
3128 | * queue up the release of the unmap to save the 1/6th of the | |
3129 | * cpu used up by the iotlb flush operation... | |
3130 | */ | |
5e0d2a6f | 3131 | } |
ba395927 KA |
3132 | } |
3133 | ||
d7ab5c46 | 3134 | static void *intel_alloc_coherent(struct device *hwdev, size_t size, |
baa676fc AP |
3135 | dma_addr_t *dma_handle, gfp_t flags, |
3136 | struct dma_attrs *attrs) | |
ba395927 KA |
3137 | { |
3138 | void *vaddr; | |
3139 | int order; | |
3140 | ||
5b6985ce | 3141 | size = PAGE_ALIGN(size); |
ba395927 | 3142 | order = get_order(size); |
e8bb910d AW |
3143 | |
3144 | if (!iommu_no_mapping(hwdev)) | |
3145 | flags &= ~(GFP_DMA | GFP_DMA32); | |
3146 | else if (hwdev->coherent_dma_mask < dma_get_required_mask(hwdev)) { | |
3147 | if (hwdev->coherent_dma_mask < DMA_BIT_MASK(32)) | |
3148 | flags |= GFP_DMA; | |
3149 | else | |
3150 | flags |= GFP_DMA32; | |
3151 | } | |
ba395927 KA |
3152 | |
3153 | vaddr = (void *)__get_free_pages(flags, order); | |
3154 | if (!vaddr) | |
3155 | return NULL; | |
3156 | memset(vaddr, 0, size); | |
3157 | ||
bb9e6d65 FT |
3158 | *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size, |
3159 | DMA_BIDIRECTIONAL, | |
3160 | hwdev->coherent_dma_mask); | |
ba395927 KA |
3161 | if (*dma_handle) |
3162 | return vaddr; | |
3163 | free_pages((unsigned long)vaddr, order); | |
3164 | return NULL; | |
3165 | } | |
3166 | ||
d7ab5c46 | 3167 | static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr, |
baa676fc | 3168 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
ba395927 KA |
3169 | { |
3170 | int order; | |
3171 | ||
5b6985ce | 3172 | size = PAGE_ALIGN(size); |
ba395927 KA |
3173 | order = get_order(size); |
3174 | ||
0db9b7ae | 3175 | intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL); |
ba395927 KA |
3176 | free_pages((unsigned long)vaddr, order); |
3177 | } | |
3178 | ||
d7ab5c46 FT |
3179 | static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist, |
3180 | int nelems, enum dma_data_direction dir, | |
3181 | struct dma_attrs *attrs) | |
ba395927 | 3182 | { |
ba395927 | 3183 | struct dmar_domain *domain; |
d794dc9b | 3184 | unsigned long start_pfn, last_pfn; |
f76aec76 | 3185 | struct iova *iova; |
8c11e798 | 3186 | struct intel_iommu *iommu; |
ea8ea460 | 3187 | struct page *freelist; |
ba395927 | 3188 | |
73676832 | 3189 | if (iommu_no_mapping(hwdev)) |
ba395927 KA |
3190 | return; |
3191 | ||
1525a29a | 3192 | domain = find_domain(hwdev); |
8c11e798 WH |
3193 | BUG_ON(!domain); |
3194 | ||
3195 | iommu = domain_get_iommu(domain); | |
ba395927 | 3196 | |
c03ab37c | 3197 | iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address)); |
85b98276 DW |
3198 | if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n", |
3199 | (unsigned long long)sglist[0].dma_address)) | |
f76aec76 | 3200 | return; |
f76aec76 | 3201 | |
d794dc9b DW |
3202 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
3203 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; | |
f76aec76 | 3204 | |
ea8ea460 | 3205 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
f76aec76 | 3206 | |
acea0018 DW |
3207 | if (intel_iommu_strict) { |
3208 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, | |
ea8ea460 | 3209 | last_pfn - start_pfn + 1, !freelist, 0); |
acea0018 DW |
3210 | /* free iova */ |
3211 | __free_iova(&domain->iovad, iova); | |
ea8ea460 | 3212 | dma_free_pagelist(freelist); |
acea0018 | 3213 | } else { |
ea8ea460 | 3214 | add_unmap(domain, iova, freelist); |
acea0018 DW |
3215 | /* |
3216 | * queue up the release of the unmap to save the 1/6th of the | |
3217 | * cpu used up by the iotlb flush operation... | |
3218 | */ | |
3219 | } | |
ba395927 KA |
3220 | } |
3221 | ||
ba395927 | 3222 | static int intel_nontranslate_map_sg(struct device *hddev, |
c03ab37c | 3223 | struct scatterlist *sglist, int nelems, int dir) |
ba395927 KA |
3224 | { |
3225 | int i; | |
c03ab37c | 3226 | struct scatterlist *sg; |
ba395927 | 3227 | |
c03ab37c | 3228 | for_each_sg(sglist, sg, nelems, i) { |
12d4d40e | 3229 | BUG_ON(!sg_page(sg)); |
4cf2e75d | 3230 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
c03ab37c | 3231 | sg->dma_length = sg->length; |
ba395927 KA |
3232 | } |
3233 | return nelems; | |
3234 | } | |
3235 | ||
d7ab5c46 FT |
3236 | static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems, |
3237 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
ba395927 | 3238 | { |
ba395927 | 3239 | int i; |
ba395927 KA |
3240 | struct pci_dev *pdev = to_pci_dev(hwdev); |
3241 | struct dmar_domain *domain; | |
f76aec76 KA |
3242 | size_t size = 0; |
3243 | int prot = 0; | |
f76aec76 KA |
3244 | struct iova *iova = NULL; |
3245 | int ret; | |
c03ab37c | 3246 | struct scatterlist *sg; |
b536d24d | 3247 | unsigned long start_vpfn; |
8c11e798 | 3248 | struct intel_iommu *iommu; |
ba395927 KA |
3249 | |
3250 | BUG_ON(dir == DMA_NONE); | |
73676832 | 3251 | if (iommu_no_mapping(hwdev)) |
c03ab37c | 3252 | return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir); |
ba395927 | 3253 | |
f76aec76 KA |
3254 | domain = get_valid_domain_for_dev(pdev); |
3255 | if (!domain) | |
3256 | return 0; | |
3257 | ||
8c11e798 WH |
3258 | iommu = domain_get_iommu(domain); |
3259 | ||
b536d24d | 3260 | for_each_sg(sglist, sg, nelems, i) |
88cb6a74 | 3261 | size += aligned_nrpages(sg->offset, sg->length); |
f76aec76 | 3262 | |
5a5e02a6 DW |
3263 | iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size), |
3264 | pdev->dma_mask); | |
f76aec76 | 3265 | if (!iova) { |
c03ab37c | 3266 | sglist->dma_length = 0; |
f76aec76 KA |
3267 | return 0; |
3268 | } | |
3269 | ||
3270 | /* | |
3271 | * Check if DMAR supports zero-length reads on write only | |
3272 | * mappings.. | |
3273 | */ | |
3274 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ | |
8c11e798 | 3275 | !cap_zlr(iommu->cap)) |
f76aec76 KA |
3276 | prot |= DMA_PTE_READ; |
3277 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) | |
3278 | prot |= DMA_PTE_WRITE; | |
3279 | ||
b536d24d | 3280 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
e1605495 | 3281 | |
f532959b | 3282 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
e1605495 DW |
3283 | if (unlikely(ret)) { |
3284 | /* clear the page */ | |
3285 | dma_pte_clear_range(domain, start_vpfn, | |
3286 | start_vpfn + size - 1); | |
3287 | /* free page tables */ | |
3288 | dma_pte_free_pagetable(domain, start_vpfn, | |
3289 | start_vpfn + size - 1); | |
3290 | /* free iova */ | |
3291 | __free_iova(&domain->iovad, iova); | |
3292 | return 0; | |
ba395927 KA |
3293 | } |
3294 | ||
1f0ef2aa DW |
3295 | /* it's a non-present to present mapping. Only flush if caching mode */ |
3296 | if (cap_caching_mode(iommu->cap)) | |
ea8ea460 | 3297 | iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1); |
1f0ef2aa | 3298 | else |
8c11e798 | 3299 | iommu_flush_write_buffer(iommu); |
1f0ef2aa | 3300 | |
ba395927 KA |
3301 | return nelems; |
3302 | } | |
3303 | ||
dfb805e8 FT |
3304 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
3305 | { | |
3306 | return !dma_addr; | |
3307 | } | |
3308 | ||
160c1d8e | 3309 | struct dma_map_ops intel_dma_ops = { |
baa676fc AP |
3310 | .alloc = intel_alloc_coherent, |
3311 | .free = intel_free_coherent, | |
ba395927 KA |
3312 | .map_sg = intel_map_sg, |
3313 | .unmap_sg = intel_unmap_sg, | |
ffbbef5c FT |
3314 | .map_page = intel_map_page, |
3315 | .unmap_page = intel_unmap_page, | |
dfb805e8 | 3316 | .mapping_error = intel_mapping_error, |
ba395927 KA |
3317 | }; |
3318 | ||
3319 | static inline int iommu_domain_cache_init(void) | |
3320 | { | |
3321 | int ret = 0; | |
3322 | ||
3323 | iommu_domain_cache = kmem_cache_create("iommu_domain", | |
3324 | sizeof(struct dmar_domain), | |
3325 | 0, | |
3326 | SLAB_HWCACHE_ALIGN, | |
3327 | ||
3328 | NULL); | |
3329 | if (!iommu_domain_cache) { | |
3330 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); | |
3331 | ret = -ENOMEM; | |
3332 | } | |
3333 | ||
3334 | return ret; | |
3335 | } | |
3336 | ||
3337 | static inline int iommu_devinfo_cache_init(void) | |
3338 | { | |
3339 | int ret = 0; | |
3340 | ||
3341 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", | |
3342 | sizeof(struct device_domain_info), | |
3343 | 0, | |
3344 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3345 | NULL); |
3346 | if (!iommu_devinfo_cache) { | |
3347 | printk(KERN_ERR "Couldn't create devinfo cache\n"); | |
3348 | ret = -ENOMEM; | |
3349 | } | |
3350 | ||
3351 | return ret; | |
3352 | } | |
3353 | ||
3354 | static inline int iommu_iova_cache_init(void) | |
3355 | { | |
3356 | int ret = 0; | |
3357 | ||
3358 | iommu_iova_cache = kmem_cache_create("iommu_iova", | |
3359 | sizeof(struct iova), | |
3360 | 0, | |
3361 | SLAB_HWCACHE_ALIGN, | |
ba395927 KA |
3362 | NULL); |
3363 | if (!iommu_iova_cache) { | |
3364 | printk(KERN_ERR "Couldn't create iova cache\n"); | |
3365 | ret = -ENOMEM; | |
3366 | } | |
3367 | ||
3368 | return ret; | |
3369 | } | |
3370 | ||
3371 | static int __init iommu_init_mempool(void) | |
3372 | { | |
3373 | int ret; | |
3374 | ret = iommu_iova_cache_init(); | |
3375 | if (ret) | |
3376 | return ret; | |
3377 | ||
3378 | ret = iommu_domain_cache_init(); | |
3379 | if (ret) | |
3380 | goto domain_error; | |
3381 | ||
3382 | ret = iommu_devinfo_cache_init(); | |
3383 | if (!ret) | |
3384 | return ret; | |
3385 | ||
3386 | kmem_cache_destroy(iommu_domain_cache); | |
3387 | domain_error: | |
3388 | kmem_cache_destroy(iommu_iova_cache); | |
3389 | ||
3390 | return -ENOMEM; | |
3391 | } | |
3392 | ||
3393 | static void __init iommu_exit_mempool(void) | |
3394 | { | |
3395 | kmem_cache_destroy(iommu_devinfo_cache); | |
3396 | kmem_cache_destroy(iommu_domain_cache); | |
3397 | kmem_cache_destroy(iommu_iova_cache); | |
3398 | ||
3399 | } | |
3400 | ||
556ab45f DW |
3401 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
3402 | { | |
3403 | struct dmar_drhd_unit *drhd; | |
3404 | u32 vtbar; | |
3405 | int rc; | |
3406 | ||
3407 | /* We know that this device on this chipset has its own IOMMU. | |
3408 | * If we find it under a different IOMMU, then the BIOS is lying | |
3409 | * to us. Hope that the IOMMU for this device is actually | |
3410 | * disabled, and it needs no translation... | |
3411 | */ | |
3412 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); | |
3413 | if (rc) { | |
3414 | /* "can't" happen */ | |
3415 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); | |
3416 | return; | |
3417 | } | |
3418 | vtbar &= 0xffff0000; | |
3419 | ||
3420 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ | |
3421 | drhd = dmar_find_matched_drhd_unit(pdev); | |
3422 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, | |
3423 | TAINT_FIRMWARE_WORKAROUND, | |
3424 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) | |
3425 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; | |
3426 | } | |
3427 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); | |
3428 | ||
ba395927 KA |
3429 | static void __init init_no_remapping_devices(void) |
3430 | { | |
3431 | struct dmar_drhd_unit *drhd; | |
832bd858 | 3432 | struct device *dev; |
b683b230 | 3433 | int i; |
ba395927 KA |
3434 | |
3435 | for_each_drhd_unit(drhd) { | |
3436 | if (!drhd->include_all) { | |
b683b230 JL |
3437 | for_each_active_dev_scope(drhd->devices, |
3438 | drhd->devices_cnt, i, dev) | |
3439 | break; | |
832bd858 | 3440 | /* ignore DMAR unit if no devices exist */ |
ba395927 KA |
3441 | if (i == drhd->devices_cnt) |
3442 | drhd->ignored = 1; | |
3443 | } | |
3444 | } | |
3445 | ||
7c919779 | 3446 | for_each_active_drhd_unit(drhd) { |
7c919779 | 3447 | if (drhd->include_all) |
ba395927 KA |
3448 | continue; |
3449 | ||
b683b230 JL |
3450 | for_each_active_dev_scope(drhd->devices, |
3451 | drhd->devices_cnt, i, dev) | |
832bd858 | 3452 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
ba395927 | 3453 | break; |
ba395927 KA |
3454 | if (i < drhd->devices_cnt) |
3455 | continue; | |
3456 | ||
c0771df8 DW |
3457 | /* This IOMMU has *only* gfx devices. Either bypass it or |
3458 | set the gfx_mapped flag, as appropriate */ | |
3459 | if (dmar_map_gfx) { | |
3460 | intel_iommu_gfx_mapped = 1; | |
3461 | } else { | |
3462 | drhd->ignored = 1; | |
b683b230 JL |
3463 | for_each_active_dev_scope(drhd->devices, |
3464 | drhd->devices_cnt, i, dev) | |
832bd858 | 3465 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
ba395927 KA |
3466 | } |
3467 | } | |
3468 | } | |
3469 | ||
f59c7b69 FY |
3470 | #ifdef CONFIG_SUSPEND |
3471 | static int init_iommu_hw(void) | |
3472 | { | |
3473 | struct dmar_drhd_unit *drhd; | |
3474 | struct intel_iommu *iommu = NULL; | |
3475 | ||
3476 | for_each_active_iommu(iommu, drhd) | |
3477 | if (iommu->qi) | |
3478 | dmar_reenable_qi(iommu); | |
3479 | ||
b779260b JC |
3480 | for_each_iommu(iommu, drhd) { |
3481 | if (drhd->ignored) { | |
3482 | /* | |
3483 | * we always have to disable PMRs or DMA may fail on | |
3484 | * this device | |
3485 | */ | |
3486 | if (force_on) | |
3487 | iommu_disable_protect_mem_regions(iommu); | |
3488 | continue; | |
3489 | } | |
3490 | ||
f59c7b69 FY |
3491 | iommu_flush_write_buffer(iommu); |
3492 | ||
3493 | iommu_set_root_entry(iommu); | |
3494 | ||
3495 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3496 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3497 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3498 | DMA_TLB_GLOBAL_FLUSH); |
b779260b JC |
3499 | if (iommu_enable_translation(iommu)) |
3500 | return 1; | |
b94996c9 | 3501 | iommu_disable_protect_mem_regions(iommu); |
f59c7b69 FY |
3502 | } |
3503 | ||
3504 | return 0; | |
3505 | } | |
3506 | ||
3507 | static void iommu_flush_all(void) | |
3508 | { | |
3509 | struct dmar_drhd_unit *drhd; | |
3510 | struct intel_iommu *iommu; | |
3511 | ||
3512 | for_each_active_iommu(iommu, drhd) { | |
3513 | iommu->flush.flush_context(iommu, 0, 0, 0, | |
1f0ef2aa | 3514 | DMA_CCMD_GLOBAL_INVL); |
f59c7b69 | 3515 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
1f0ef2aa | 3516 | DMA_TLB_GLOBAL_FLUSH); |
f59c7b69 FY |
3517 | } |
3518 | } | |
3519 | ||
134fac3f | 3520 | static int iommu_suspend(void) |
f59c7b69 FY |
3521 | { |
3522 | struct dmar_drhd_unit *drhd; | |
3523 | struct intel_iommu *iommu = NULL; | |
3524 | unsigned long flag; | |
3525 | ||
3526 | for_each_active_iommu(iommu, drhd) { | |
3527 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, | |
3528 | GFP_ATOMIC); | |
3529 | if (!iommu->iommu_state) | |
3530 | goto nomem; | |
3531 | } | |
3532 | ||
3533 | iommu_flush_all(); | |
3534 | ||
3535 | for_each_active_iommu(iommu, drhd) { | |
3536 | iommu_disable_translation(iommu); | |
3537 | ||
1f5b3c3f | 3538 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3539 | |
3540 | iommu->iommu_state[SR_DMAR_FECTL_REG] = | |
3541 | readl(iommu->reg + DMAR_FECTL_REG); | |
3542 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = | |
3543 | readl(iommu->reg + DMAR_FEDATA_REG); | |
3544 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = | |
3545 | readl(iommu->reg + DMAR_FEADDR_REG); | |
3546 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = | |
3547 | readl(iommu->reg + DMAR_FEUADDR_REG); | |
3548 | ||
1f5b3c3f | 3549 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3550 | } |
3551 | return 0; | |
3552 | ||
3553 | nomem: | |
3554 | for_each_active_iommu(iommu, drhd) | |
3555 | kfree(iommu->iommu_state); | |
3556 | ||
3557 | return -ENOMEM; | |
3558 | } | |
3559 | ||
134fac3f | 3560 | static void iommu_resume(void) |
f59c7b69 FY |
3561 | { |
3562 | struct dmar_drhd_unit *drhd; | |
3563 | struct intel_iommu *iommu = NULL; | |
3564 | unsigned long flag; | |
3565 | ||
3566 | if (init_iommu_hw()) { | |
b779260b JC |
3567 | if (force_on) |
3568 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); | |
3569 | else | |
3570 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); | |
134fac3f | 3571 | return; |
f59c7b69 FY |
3572 | } |
3573 | ||
3574 | for_each_active_iommu(iommu, drhd) { | |
3575 | ||
1f5b3c3f | 3576 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
f59c7b69 FY |
3577 | |
3578 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], | |
3579 | iommu->reg + DMAR_FECTL_REG); | |
3580 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], | |
3581 | iommu->reg + DMAR_FEDATA_REG); | |
3582 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], | |
3583 | iommu->reg + DMAR_FEADDR_REG); | |
3584 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], | |
3585 | iommu->reg + DMAR_FEUADDR_REG); | |
3586 | ||
1f5b3c3f | 3587 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
f59c7b69 FY |
3588 | } |
3589 | ||
3590 | for_each_active_iommu(iommu, drhd) | |
3591 | kfree(iommu->iommu_state); | |
f59c7b69 FY |
3592 | } |
3593 | ||
134fac3f | 3594 | static struct syscore_ops iommu_syscore_ops = { |
f59c7b69 FY |
3595 | .resume = iommu_resume, |
3596 | .suspend = iommu_suspend, | |
3597 | }; | |
3598 | ||
134fac3f | 3599 | static void __init init_iommu_pm_ops(void) |
f59c7b69 | 3600 | { |
134fac3f | 3601 | register_syscore_ops(&iommu_syscore_ops); |
f59c7b69 FY |
3602 | } |
3603 | ||
3604 | #else | |
99592ba4 | 3605 | static inline void init_iommu_pm_ops(void) {} |
f59c7b69 FY |
3606 | #endif /* CONFIG_PM */ |
3607 | ||
318fe7df SS |
3608 | |
3609 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header) | |
3610 | { | |
3611 | struct acpi_dmar_reserved_memory *rmrr; | |
3612 | struct dmar_rmrr_unit *rmrru; | |
3613 | ||
3614 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); | |
3615 | if (!rmrru) | |
3616 | return -ENOMEM; | |
3617 | ||
3618 | rmrru->hdr = header; | |
3619 | rmrr = (struct acpi_dmar_reserved_memory *)header; | |
3620 | rmrru->base_address = rmrr->base_address; | |
3621 | rmrru->end_address = rmrr->end_address; | |
2e455289 JL |
3622 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
3623 | ((void *)rmrr) + rmrr->header.length, | |
3624 | &rmrru->devices_cnt); | |
3625 | if (rmrru->devices_cnt && rmrru->devices == NULL) { | |
3626 | kfree(rmrru); | |
3627 | return -ENOMEM; | |
3628 | } | |
318fe7df | 3629 | |
2e455289 | 3630 | list_add(&rmrru->list, &dmar_rmrr_units); |
318fe7df | 3631 | |
2e455289 | 3632 | return 0; |
318fe7df SS |
3633 | } |
3634 | ||
318fe7df SS |
3635 | int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr) |
3636 | { | |
3637 | struct acpi_dmar_atsr *atsr; | |
3638 | struct dmar_atsr_unit *atsru; | |
3639 | ||
3640 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); | |
3641 | atsru = kzalloc(sizeof(*atsru), GFP_KERNEL); | |
3642 | if (!atsru) | |
3643 | return -ENOMEM; | |
3644 | ||
3645 | atsru->hdr = hdr; | |
3646 | atsru->include_all = atsr->flags & 0x1; | |
2e455289 JL |
3647 | if (!atsru->include_all) { |
3648 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), | |
3649 | (void *)atsr + atsr->header.length, | |
3650 | &atsru->devices_cnt); | |
3651 | if (atsru->devices_cnt && atsru->devices == NULL) { | |
3652 | kfree(atsru); | |
3653 | return -ENOMEM; | |
3654 | } | |
3655 | } | |
318fe7df | 3656 | |
0e242612 | 3657 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
318fe7df SS |
3658 | |
3659 | return 0; | |
3660 | } | |
3661 | ||
9bdc531e JL |
3662 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
3663 | { | |
3664 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); | |
3665 | kfree(atsru); | |
3666 | } | |
3667 | ||
3668 | static void intel_iommu_free_dmars(void) | |
3669 | { | |
3670 | struct dmar_rmrr_unit *rmrru, *rmrr_n; | |
3671 | struct dmar_atsr_unit *atsru, *atsr_n; | |
3672 | ||
3673 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { | |
3674 | list_del(&rmrru->list); | |
3675 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); | |
3676 | kfree(rmrru); | |
318fe7df SS |
3677 | } |
3678 | ||
9bdc531e JL |
3679 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
3680 | list_del(&atsru->list); | |
3681 | intel_iommu_free_atsr(atsru); | |
3682 | } | |
318fe7df SS |
3683 | } |
3684 | ||
3685 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) | |
3686 | { | |
b683b230 | 3687 | int i, ret = 1; |
318fe7df | 3688 | struct pci_bus *bus; |
832bd858 DW |
3689 | struct pci_dev *bridge = NULL; |
3690 | struct device *tmp; | |
318fe7df SS |
3691 | struct acpi_dmar_atsr *atsr; |
3692 | struct dmar_atsr_unit *atsru; | |
3693 | ||
3694 | dev = pci_physfn(dev); | |
318fe7df | 3695 | for (bus = dev->bus; bus; bus = bus->parent) { |
b5f82ddf | 3696 | bridge = bus->self; |
318fe7df | 3697 | if (!bridge || !pci_is_pcie(bridge) || |
62f87c0e | 3698 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
318fe7df | 3699 | return 0; |
b5f82ddf | 3700 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
318fe7df | 3701 | break; |
318fe7df | 3702 | } |
b5f82ddf JL |
3703 | if (!bridge) |
3704 | return 0; | |
318fe7df | 3705 | |
0e242612 | 3706 | rcu_read_lock(); |
b5f82ddf JL |
3707 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
3708 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3709 | if (atsr->segment != pci_domain_nr(dev->bus)) | |
3710 | continue; | |
3711 | ||
b683b230 | 3712 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
832bd858 | 3713 | if (tmp == &bridge->dev) |
b683b230 | 3714 | goto out; |
b5f82ddf JL |
3715 | |
3716 | if (atsru->include_all) | |
b683b230 | 3717 | goto out; |
b5f82ddf | 3718 | } |
b683b230 JL |
3719 | ret = 0; |
3720 | out: | |
0e242612 | 3721 | rcu_read_unlock(); |
318fe7df | 3722 | |
b683b230 | 3723 | return ret; |
318fe7df SS |
3724 | } |
3725 | ||
59ce0515 JL |
3726 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
3727 | { | |
3728 | int ret = 0; | |
3729 | struct dmar_rmrr_unit *rmrru; | |
3730 | struct dmar_atsr_unit *atsru; | |
3731 | struct acpi_dmar_atsr *atsr; | |
3732 | struct acpi_dmar_reserved_memory *rmrr; | |
3733 | ||
3734 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) | |
3735 | return 0; | |
3736 | ||
3737 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { | |
3738 | rmrr = container_of(rmrru->hdr, | |
3739 | struct acpi_dmar_reserved_memory, header); | |
3740 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3741 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), | |
3742 | ((void *)rmrr) + rmrr->header.length, | |
3743 | rmrr->segment, rmrru->devices, | |
3744 | rmrru->devices_cnt); | |
3745 | if (ret > 0) | |
3746 | break; | |
3747 | else if(ret < 0) | |
3748 | return ret; | |
3749 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
3750 | if (dmar_remove_dev_scope(info, rmrr->segment, | |
3751 | rmrru->devices, rmrru->devices_cnt)) | |
3752 | break; | |
3753 | } | |
3754 | } | |
3755 | ||
3756 | list_for_each_entry(atsru, &dmar_atsr_units, list) { | |
3757 | if (atsru->include_all) | |
3758 | continue; | |
3759 | ||
3760 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); | |
3761 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { | |
3762 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), | |
3763 | (void *)atsr + atsr->header.length, | |
3764 | atsr->segment, atsru->devices, | |
3765 | atsru->devices_cnt); | |
3766 | if (ret > 0) | |
3767 | break; | |
3768 | else if(ret < 0) | |
3769 | return ret; | |
3770 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { | |
3771 | if (dmar_remove_dev_scope(info, atsr->segment, | |
3772 | atsru->devices, atsru->devices_cnt)) | |
3773 | break; | |
3774 | } | |
3775 | } | |
3776 | ||
3777 | return 0; | |
3778 | } | |
3779 | ||
99dcaded FY |
3780 | /* |
3781 | * Here we only respond to action of unbound device from driver. | |
3782 | * | |
3783 | * Added device is not attached to its DMAR domain here yet. That will happen | |
3784 | * when mapping the device to iova. | |
3785 | */ | |
3786 | static int device_notifier(struct notifier_block *nb, | |
3787 | unsigned long action, void *data) | |
3788 | { | |
3789 | struct device *dev = data; | |
3790 | struct pci_dev *pdev = to_pci_dev(dev); | |
3791 | struct dmar_domain *domain; | |
3792 | ||
3d89194a | 3793 | if (iommu_dummy(dev)) |
44cd613c DW |
3794 | return 0; |
3795 | ||
7e7dfab7 JL |
3796 | if (action != BUS_NOTIFY_UNBOUND_DRIVER && |
3797 | action != BUS_NOTIFY_DEL_DEVICE) | |
3798 | return 0; | |
3799 | ||
1525a29a | 3800 | domain = find_domain(dev); |
99dcaded FY |
3801 | if (!domain) |
3802 | return 0; | |
3803 | ||
3a5670e8 | 3804 | down_read(&dmar_global_lock); |
7e7dfab7 JL |
3805 | domain_remove_one_dev_info(domain, pdev); |
3806 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && | |
3807 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) && | |
3808 | list_empty(&domain->devices)) | |
3809 | domain_exit(domain); | |
3a5670e8 | 3810 | up_read(&dmar_global_lock); |
a97590e5 | 3811 | |
99dcaded FY |
3812 | return 0; |
3813 | } | |
3814 | ||
3815 | static struct notifier_block device_nb = { | |
3816 | .notifier_call = device_notifier, | |
3817 | }; | |
3818 | ||
75f05569 JL |
3819 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
3820 | unsigned long val, void *v) | |
3821 | { | |
3822 | struct memory_notify *mhp = v; | |
3823 | unsigned long long start, end; | |
3824 | unsigned long start_vpfn, last_vpfn; | |
3825 | ||
3826 | switch (val) { | |
3827 | case MEM_GOING_ONLINE: | |
3828 | start = mhp->start_pfn << PAGE_SHIFT; | |
3829 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; | |
3830 | if (iommu_domain_identity_map(si_domain, start, end)) { | |
3831 | pr_warn("dmar: failed to build identity map for [%llx-%llx]\n", | |
3832 | start, end); | |
3833 | return NOTIFY_BAD; | |
3834 | } | |
3835 | break; | |
3836 | ||
3837 | case MEM_OFFLINE: | |
3838 | case MEM_CANCEL_ONLINE: | |
3839 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); | |
3840 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); | |
3841 | while (start_vpfn <= last_vpfn) { | |
3842 | struct iova *iova; | |
3843 | struct dmar_drhd_unit *drhd; | |
3844 | struct intel_iommu *iommu; | |
ea8ea460 | 3845 | struct page *freelist; |
75f05569 JL |
3846 | |
3847 | iova = find_iova(&si_domain->iovad, start_vpfn); | |
3848 | if (iova == NULL) { | |
3849 | pr_debug("dmar: failed get IOVA for PFN %lx\n", | |
3850 | start_vpfn); | |
3851 | break; | |
3852 | } | |
3853 | ||
3854 | iova = split_and_remove_iova(&si_domain->iovad, iova, | |
3855 | start_vpfn, last_vpfn); | |
3856 | if (iova == NULL) { | |
3857 | pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n", | |
3858 | start_vpfn, last_vpfn); | |
3859 | return NOTIFY_BAD; | |
3860 | } | |
3861 | ||
ea8ea460 DW |
3862 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
3863 | iova->pfn_hi); | |
3864 | ||
75f05569 JL |
3865 | rcu_read_lock(); |
3866 | for_each_active_iommu(iommu, drhd) | |
3867 | iommu_flush_iotlb_psi(iommu, si_domain->id, | |
3868 | iova->pfn_lo, | |
ea8ea460 DW |
3869 | iova->pfn_hi - iova->pfn_lo + 1, |
3870 | !freelist, 0); | |
75f05569 | 3871 | rcu_read_unlock(); |
ea8ea460 | 3872 | dma_free_pagelist(freelist); |
75f05569 JL |
3873 | |
3874 | start_vpfn = iova->pfn_hi + 1; | |
3875 | free_iova_mem(iova); | |
3876 | } | |
3877 | break; | |
3878 | } | |
3879 | ||
3880 | return NOTIFY_OK; | |
3881 | } | |
3882 | ||
3883 | static struct notifier_block intel_iommu_memory_nb = { | |
3884 | .notifier_call = intel_iommu_memory_notifier, | |
3885 | .priority = 0 | |
3886 | }; | |
3887 | ||
ba395927 KA |
3888 | int __init intel_iommu_init(void) |
3889 | { | |
9bdc531e | 3890 | int ret = -ENODEV; |
3a93c841 | 3891 | struct dmar_drhd_unit *drhd; |
7c919779 | 3892 | struct intel_iommu *iommu; |
ba395927 | 3893 | |
a59b50e9 JC |
3894 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
3895 | force_on = tboot_force_iommu(); | |
3896 | ||
3a5670e8 JL |
3897 | if (iommu_init_mempool()) { |
3898 | if (force_on) | |
3899 | panic("tboot: Failed to initialize iommu memory\n"); | |
3900 | return -ENOMEM; | |
3901 | } | |
3902 | ||
3903 | down_write(&dmar_global_lock); | |
a59b50e9 JC |
3904 | if (dmar_table_init()) { |
3905 | if (force_on) | |
3906 | panic("tboot: Failed to initialize DMAR table\n"); | |
9bdc531e | 3907 | goto out_free_dmar; |
a59b50e9 | 3908 | } |
ba395927 | 3909 | |
3a93c841 TI |
3910 | /* |
3911 | * Disable translation if already enabled prior to OS handover. | |
3912 | */ | |
7c919779 | 3913 | for_each_active_iommu(iommu, drhd) |
3a93c841 TI |
3914 | if (iommu->gcmd & DMA_GCMD_TE) |
3915 | iommu_disable_translation(iommu); | |
3a93c841 | 3916 | |
c2c7286a | 3917 | if (dmar_dev_scope_init() < 0) { |
a59b50e9 JC |
3918 | if (force_on) |
3919 | panic("tboot: Failed to initialize DMAR device scope\n"); | |
9bdc531e | 3920 | goto out_free_dmar; |
a59b50e9 | 3921 | } |
1886e8a9 | 3922 | |
75f1cdf1 | 3923 | if (no_iommu || dmar_disabled) |
9bdc531e | 3924 | goto out_free_dmar; |
2ae21010 | 3925 | |
318fe7df SS |
3926 | if (list_empty(&dmar_rmrr_units)) |
3927 | printk(KERN_INFO "DMAR: No RMRR found\n"); | |
3928 | ||
3929 | if (list_empty(&dmar_atsr_units)) | |
3930 | printk(KERN_INFO "DMAR: No ATSR found\n"); | |
3931 | ||
51a63e67 JC |
3932 | if (dmar_init_reserved_ranges()) { |
3933 | if (force_on) | |
3934 | panic("tboot: Failed to reserve iommu ranges\n"); | |
3a5670e8 | 3935 | goto out_free_reserved_range; |
51a63e67 | 3936 | } |
ba395927 KA |
3937 | |
3938 | init_no_remapping_devices(); | |
3939 | ||
b779260b | 3940 | ret = init_dmars(); |
ba395927 | 3941 | if (ret) { |
a59b50e9 JC |
3942 | if (force_on) |
3943 | panic("tboot: Failed to initialize DMARs\n"); | |
ba395927 | 3944 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
9bdc531e | 3945 | goto out_free_reserved_range; |
ba395927 | 3946 | } |
3a5670e8 | 3947 | up_write(&dmar_global_lock); |
ba395927 KA |
3948 | printk(KERN_INFO |
3949 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); | |
3950 | ||
5e0d2a6f | 3951 | init_timer(&unmap_timer); |
75f1cdf1 FT |
3952 | #ifdef CONFIG_SWIOTLB |
3953 | swiotlb = 0; | |
3954 | #endif | |
19943b0e | 3955 | dma_ops = &intel_dma_ops; |
4ed0d3e6 | 3956 | |
134fac3f | 3957 | init_iommu_pm_ops(); |
a8bcbb0d | 3958 | |
4236d97d | 3959 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
99dcaded | 3960 | bus_register_notifier(&pci_bus_type, &device_nb); |
75f05569 JL |
3961 | if (si_domain && !hw_pass_through) |
3962 | register_memory_notifier(&intel_iommu_memory_nb); | |
99dcaded | 3963 | |
8bc1f85c ED |
3964 | intel_iommu_enabled = 1; |
3965 | ||
ba395927 | 3966 | return 0; |
9bdc531e JL |
3967 | |
3968 | out_free_reserved_range: | |
3969 | put_iova_domain(&reserved_iova_list); | |
9bdc531e JL |
3970 | out_free_dmar: |
3971 | intel_iommu_free_dmars(); | |
3a5670e8 JL |
3972 | up_write(&dmar_global_lock); |
3973 | iommu_exit_mempool(); | |
9bdc531e | 3974 | return ret; |
ba395927 | 3975 | } |
e820482c | 3976 | |
3199aa6b | 3977 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
0bcb3e28 | 3978 | struct device *dev) |
3199aa6b | 3979 | { |
0bcb3e28 | 3980 | struct pci_dev *tmp, *parent, *pdev; |
3199aa6b | 3981 | |
0bcb3e28 | 3982 | if (!iommu || !dev || !dev_is_pci(dev)) |
3199aa6b HW |
3983 | return; |
3984 | ||
0bcb3e28 DW |
3985 | pdev = to_pci_dev(dev); |
3986 | ||
3199aa6b HW |
3987 | /* dependent device detach */ |
3988 | tmp = pci_find_upstream_pcie_bridge(pdev); | |
3989 | /* Secondary interface's bus number and devfn 0 */ | |
3990 | if (tmp) { | |
3991 | parent = pdev->bus->self; | |
3992 | while (parent != tmp) { | |
3993 | iommu_detach_dev(iommu, parent->bus->number, | |
276dbf99 | 3994 | parent->devfn); |
3199aa6b HW |
3995 | parent = parent->bus->self; |
3996 | } | |
45e829ea | 3997 | if (pci_is_pcie(tmp)) /* this is a PCIe-to-PCI bridge */ |
3199aa6b HW |
3998 | iommu_detach_dev(iommu, |
3999 | tmp->subordinate->number, 0); | |
4000 | else /* this is a legacy PCI bridge */ | |
276dbf99 DW |
4001 | iommu_detach_dev(iommu, tmp->bus->number, |
4002 | tmp->devfn); | |
3199aa6b HW |
4003 | } |
4004 | } | |
4005 | ||
2c2e2c38 | 4006 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
c7151a8d WH |
4007 | struct pci_dev *pdev) |
4008 | { | |
bca2b916 | 4009 | struct device_domain_info *info, *tmp; |
c7151a8d WH |
4010 | struct intel_iommu *iommu; |
4011 | unsigned long flags; | |
4012 | int found = 0; | |
c7151a8d | 4013 | |
276dbf99 DW |
4014 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
4015 | pdev->devfn); | |
c7151a8d WH |
4016 | if (!iommu) |
4017 | return; | |
4018 | ||
4019 | spin_lock_irqsave(&device_domain_lock, flags); | |
bca2b916 | 4020 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
8519dc44 MH |
4021 | if (info->segment == pci_domain_nr(pdev->bus) && |
4022 | info->bus == pdev->bus->number && | |
c7151a8d | 4023 | info->devfn == pdev->devfn) { |
109b9b04 | 4024 | unlink_domain_info(info); |
c7151a8d WH |
4025 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4026 | ||
93a23a72 | 4027 | iommu_disable_dev_iotlb(info); |
c7151a8d | 4028 | iommu_detach_dev(iommu, info->bus, info->devfn); |
0bcb3e28 | 4029 | iommu_detach_dependent_devices(iommu, &pdev->dev); |
c7151a8d WH |
4030 | free_devinfo_mem(info); |
4031 | ||
4032 | spin_lock_irqsave(&device_domain_lock, flags); | |
4033 | ||
4034 | if (found) | |
4035 | break; | |
4036 | else | |
4037 | continue; | |
4038 | } | |
4039 | ||
4040 | /* if there is no other devices under the same iommu | |
4041 | * owned by this domain, clear this iommu in iommu_bmp | |
4042 | * update iommu count and coherency | |
4043 | */ | |
276dbf99 DW |
4044 | if (iommu == device_to_iommu(info->segment, info->bus, |
4045 | info->devfn)) | |
c7151a8d WH |
4046 | found = 1; |
4047 | } | |
4048 | ||
3e7abe25 RD |
4049 | spin_unlock_irqrestore(&device_domain_lock, flags); |
4050 | ||
c7151a8d WH |
4051 | if (found == 0) { |
4052 | unsigned long tmp_flags; | |
4053 | spin_lock_irqsave(&domain->iommu_lock, tmp_flags); | |
1b198bb0 | 4054 | clear_bit(iommu->seq_id, domain->iommu_bmp); |
c7151a8d | 4055 | domain->iommu_count--; |
58c610bd | 4056 | domain_update_iommu_cap(domain); |
c7151a8d | 4057 | spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags); |
a97590e5 | 4058 | |
9b4554b2 AW |
4059 | if (!(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE) && |
4060 | !(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)) { | |
4061 | spin_lock_irqsave(&iommu->lock, tmp_flags); | |
4062 | clear_bit(domain->id, iommu->domain_ids); | |
4063 | iommu->domains[domain->id] = NULL; | |
4064 | spin_unlock_irqrestore(&iommu->lock, tmp_flags); | |
4065 | } | |
c7151a8d | 4066 | } |
c7151a8d WH |
4067 | } |
4068 | ||
2c2e2c38 | 4069 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
5e98c4b1 WH |
4070 | { |
4071 | int adjust_width; | |
4072 | ||
4073 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); | |
5e98c4b1 WH |
4074 | domain_reserve_special_ranges(domain); |
4075 | ||
4076 | /* calculate AGAW */ | |
4077 | domain->gaw = guest_width; | |
4078 | adjust_width = guestwidth_to_adjustwidth(guest_width); | |
4079 | domain->agaw = width_to_agaw(adjust_width); | |
4080 | ||
5e98c4b1 | 4081 | domain->iommu_coherency = 0; |
c5b15255 | 4082 | domain->iommu_snooping = 0; |
6dd9a7c7 | 4083 | domain->iommu_superpage = 0; |
fe40f1e0 | 4084 | domain->max_addr = 0; |
4c923d47 | 4085 | domain->nid = -1; |
5e98c4b1 WH |
4086 | |
4087 | /* always allocate the top pgd */ | |
4c923d47 | 4088 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
5e98c4b1 WH |
4089 | if (!domain->pgd) |
4090 | return -ENOMEM; | |
4091 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); | |
4092 | return 0; | |
4093 | } | |
4094 | ||
5d450806 | 4095 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
38717946 | 4096 | { |
5d450806 | 4097 | struct dmar_domain *dmar_domain; |
38717946 | 4098 | |
92d03cc8 | 4099 | dmar_domain = alloc_domain(true); |
5d450806 | 4100 | if (!dmar_domain) { |
38717946 | 4101 | printk(KERN_ERR |
5d450806 JR |
4102 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
4103 | return -ENOMEM; | |
38717946 | 4104 | } |
2c2e2c38 | 4105 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
38717946 | 4106 | printk(KERN_ERR |
5d450806 | 4107 | "intel_iommu_domain_init() failed\n"); |
92d03cc8 | 4108 | domain_exit(dmar_domain); |
5d450806 | 4109 | return -ENOMEM; |
38717946 | 4110 | } |
8140a95d | 4111 | domain_update_iommu_cap(dmar_domain); |
5d450806 | 4112 | domain->priv = dmar_domain; |
faa3d6f5 | 4113 | |
8a0e715b JR |
4114 | domain->geometry.aperture_start = 0; |
4115 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); | |
4116 | domain->geometry.force_aperture = true; | |
4117 | ||
5d450806 | 4118 | return 0; |
38717946 | 4119 | } |
38717946 | 4120 | |
5d450806 | 4121 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
38717946 | 4122 | { |
5d450806 JR |
4123 | struct dmar_domain *dmar_domain = domain->priv; |
4124 | ||
4125 | domain->priv = NULL; | |
92d03cc8 | 4126 | domain_exit(dmar_domain); |
38717946 | 4127 | } |
38717946 | 4128 | |
4c5478c9 JR |
4129 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
4130 | struct device *dev) | |
38717946 | 4131 | { |
4c5478c9 JR |
4132 | struct dmar_domain *dmar_domain = domain->priv; |
4133 | struct pci_dev *pdev = to_pci_dev(dev); | |
fe40f1e0 WH |
4134 | struct intel_iommu *iommu; |
4135 | int addr_width; | |
faa3d6f5 WH |
4136 | |
4137 | /* normally pdev is not mapped */ | |
4138 | if (unlikely(domain_context_mapped(pdev))) { | |
4139 | struct dmar_domain *old_domain; | |
4140 | ||
1525a29a | 4141 | old_domain = find_domain(dev); |
faa3d6f5 | 4142 | if (old_domain) { |
2c2e2c38 FY |
4143 | if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE || |
4144 | dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) | |
4145 | domain_remove_one_dev_info(old_domain, pdev); | |
faa3d6f5 WH |
4146 | else |
4147 | domain_remove_dev_info(old_domain); | |
4148 | } | |
4149 | } | |
4150 | ||
276dbf99 DW |
4151 | iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number, |
4152 | pdev->devfn); | |
fe40f1e0 WH |
4153 | if (!iommu) |
4154 | return -ENODEV; | |
4155 | ||
4156 | /* check if this iommu agaw is sufficient for max mapped address */ | |
4157 | addr_width = agaw_to_width(iommu->agaw); | |
a99c47a2 TL |
4158 | if (addr_width > cap_mgaw(iommu->cap)) |
4159 | addr_width = cap_mgaw(iommu->cap); | |
4160 | ||
4161 | if (dmar_domain->max_addr > (1LL << addr_width)) { | |
4162 | printk(KERN_ERR "%s: iommu width (%d) is not " | |
fe40f1e0 | 4163 | "sufficient for the mapped address (%llx)\n", |
a99c47a2 | 4164 | __func__, addr_width, dmar_domain->max_addr); |
fe40f1e0 WH |
4165 | return -EFAULT; |
4166 | } | |
a99c47a2 TL |
4167 | dmar_domain->gaw = addr_width; |
4168 | ||
4169 | /* | |
4170 | * Knock out extra levels of page tables if necessary | |
4171 | */ | |
4172 | while (iommu->agaw < dmar_domain->agaw) { | |
4173 | struct dma_pte *pte; | |
4174 | ||
4175 | pte = dmar_domain->pgd; | |
4176 | if (dma_pte_present(pte)) { | |
25cbff16 SY |
4177 | dmar_domain->pgd = (struct dma_pte *) |
4178 | phys_to_virt(dma_pte_addr(pte)); | |
7a661013 | 4179 | free_pgtable_page(pte); |
a99c47a2 TL |
4180 | } |
4181 | dmar_domain->agaw--; | |
4182 | } | |
fe40f1e0 | 4183 | |
5fe60f4e | 4184 | return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL); |
38717946 | 4185 | } |
38717946 | 4186 | |
4c5478c9 JR |
4187 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
4188 | struct device *dev) | |
38717946 | 4189 | { |
4c5478c9 JR |
4190 | struct dmar_domain *dmar_domain = domain->priv; |
4191 | struct pci_dev *pdev = to_pci_dev(dev); | |
4192 | ||
2c2e2c38 | 4193 | domain_remove_one_dev_info(dmar_domain, pdev); |
faa3d6f5 | 4194 | } |
c7151a8d | 4195 | |
b146a1c9 JR |
4196 | static int intel_iommu_map(struct iommu_domain *domain, |
4197 | unsigned long iova, phys_addr_t hpa, | |
5009065d | 4198 | size_t size, int iommu_prot) |
faa3d6f5 | 4199 | { |
dde57a21 | 4200 | struct dmar_domain *dmar_domain = domain->priv; |
fe40f1e0 | 4201 | u64 max_addr; |
dde57a21 | 4202 | int prot = 0; |
faa3d6f5 | 4203 | int ret; |
fe40f1e0 | 4204 | |
dde57a21 JR |
4205 | if (iommu_prot & IOMMU_READ) |
4206 | prot |= DMA_PTE_READ; | |
4207 | if (iommu_prot & IOMMU_WRITE) | |
4208 | prot |= DMA_PTE_WRITE; | |
9cf06697 SY |
4209 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
4210 | prot |= DMA_PTE_SNP; | |
dde57a21 | 4211 | |
163cc52c | 4212 | max_addr = iova + size; |
dde57a21 | 4213 | if (dmar_domain->max_addr < max_addr) { |
fe40f1e0 WH |
4214 | u64 end; |
4215 | ||
4216 | /* check if minimum agaw is sufficient for mapped address */ | |
8954da1f | 4217 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
fe40f1e0 | 4218 | if (end < max_addr) { |
8954da1f | 4219 | printk(KERN_ERR "%s: iommu width (%d) is not " |
fe40f1e0 | 4220 | "sufficient for the mapped address (%llx)\n", |
8954da1f | 4221 | __func__, dmar_domain->gaw, max_addr); |
fe40f1e0 WH |
4222 | return -EFAULT; |
4223 | } | |
dde57a21 | 4224 | dmar_domain->max_addr = max_addr; |
fe40f1e0 | 4225 | } |
ad051221 DW |
4226 | /* Round up size to next multiple of PAGE_SIZE, if it and |
4227 | the low bits of hpa would take us onto the next page */ | |
88cb6a74 | 4228 | size = aligned_nrpages(hpa, size); |
ad051221 DW |
4229 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
4230 | hpa >> VTD_PAGE_SHIFT, size, prot); | |
faa3d6f5 | 4231 | return ret; |
38717946 | 4232 | } |
38717946 | 4233 | |
5009065d | 4234 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
ea8ea460 | 4235 | unsigned long iova, size_t size) |
38717946 | 4236 | { |
dde57a21 | 4237 | struct dmar_domain *dmar_domain = domain->priv; |
ea8ea460 DW |
4238 | struct page *freelist = NULL; |
4239 | struct intel_iommu *iommu; | |
4240 | unsigned long start_pfn, last_pfn; | |
4241 | unsigned int npages; | |
4242 | int iommu_id, num, ndomains, level = 0; | |
5cf0a76f DW |
4243 | |
4244 | /* Cope with horrid API which requires us to unmap more than the | |
4245 | size argument if it happens to be a large-page mapping. */ | |
4246 | if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)) | |
4247 | BUG(); | |
4248 | ||
4249 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) | |
4250 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); | |
4b99d352 | 4251 | |
ea8ea460 DW |
4252 | start_pfn = iova >> VTD_PAGE_SHIFT; |
4253 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; | |
4254 | ||
4255 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); | |
4256 | ||
4257 | npages = last_pfn - start_pfn + 1; | |
4258 | ||
4259 | for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) { | |
4260 | iommu = g_iommus[iommu_id]; | |
4261 | ||
4262 | /* | |
4263 | * find bit position of dmar_domain | |
4264 | */ | |
4265 | ndomains = cap_ndoms(iommu->cap); | |
4266 | for_each_set_bit(num, iommu->domain_ids, ndomains) { | |
4267 | if (iommu->domains[num] == dmar_domain) | |
4268 | iommu_flush_iotlb_psi(iommu, num, start_pfn, | |
4269 | npages, !freelist, 0); | |
4270 | } | |
4271 | ||
4272 | } | |
4273 | ||
4274 | dma_free_pagelist(freelist); | |
fe40f1e0 | 4275 | |
163cc52c DW |
4276 | if (dmar_domain->max_addr == iova + size) |
4277 | dmar_domain->max_addr = iova; | |
b146a1c9 | 4278 | |
5cf0a76f | 4279 | return size; |
38717946 | 4280 | } |
38717946 | 4281 | |
d14d6577 | 4282 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
bb5547ac | 4283 | dma_addr_t iova) |
38717946 | 4284 | { |
d14d6577 | 4285 | struct dmar_domain *dmar_domain = domain->priv; |
38717946 | 4286 | struct dma_pte *pte; |
5cf0a76f | 4287 | int level = 0; |
faa3d6f5 | 4288 | u64 phys = 0; |
38717946 | 4289 | |
5cf0a76f | 4290 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
38717946 | 4291 | if (pte) |
faa3d6f5 | 4292 | phys = dma_pte_addr(pte); |
38717946 | 4293 | |
faa3d6f5 | 4294 | return phys; |
38717946 | 4295 | } |
a8bcbb0d | 4296 | |
dbb9fd86 SY |
4297 | static int intel_iommu_domain_has_cap(struct iommu_domain *domain, |
4298 | unsigned long cap) | |
4299 | { | |
4300 | struct dmar_domain *dmar_domain = domain->priv; | |
4301 | ||
4302 | if (cap == IOMMU_CAP_CACHE_COHERENCY) | |
4303 | return dmar_domain->iommu_snooping; | |
323f99cb | 4304 | if (cap == IOMMU_CAP_INTR_REMAP) |
95a02e97 | 4305 | return irq_remapping_enabled; |
dbb9fd86 SY |
4306 | |
4307 | return 0; | |
4308 | } | |
4309 | ||
783f157b | 4310 | #define REQ_ACS_FLAGS (PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF) |
70ae6f0d | 4311 | |
abdfdde2 AW |
4312 | static int intel_iommu_add_device(struct device *dev) |
4313 | { | |
4314 | struct pci_dev *pdev = to_pci_dev(dev); | |
3da4af0a | 4315 | struct pci_dev *bridge, *dma_pdev = NULL; |
abdfdde2 AW |
4316 | struct iommu_group *group; |
4317 | int ret; | |
70ae6f0d | 4318 | |
abdfdde2 AW |
4319 | if (!device_to_iommu(pci_domain_nr(pdev->bus), |
4320 | pdev->bus->number, pdev->devfn)) | |
70ae6f0d AW |
4321 | return -ENODEV; |
4322 | ||
4323 | bridge = pci_find_upstream_pcie_bridge(pdev); | |
4324 | if (bridge) { | |
abdfdde2 AW |
4325 | if (pci_is_pcie(bridge)) |
4326 | dma_pdev = pci_get_domain_bus_and_slot( | |
4327 | pci_domain_nr(pdev->bus), | |
4328 | bridge->subordinate->number, 0); | |
3da4af0a | 4329 | if (!dma_pdev) |
abdfdde2 AW |
4330 | dma_pdev = pci_dev_get(bridge); |
4331 | } else | |
4332 | dma_pdev = pci_dev_get(pdev); | |
4333 | ||
a4ff1fc2 | 4334 | /* Account for quirked devices */ |
783f157b AW |
4335 | swap_pci_ref(&dma_pdev, pci_get_dma_source(dma_pdev)); |
4336 | ||
a4ff1fc2 AW |
4337 | /* |
4338 | * If it's a multifunction device that does not support our | |
c14d2690 AW |
4339 | * required ACS flags, add to the same group as lowest numbered |
4340 | * function that also does not suport the required ACS flags. | |
a4ff1fc2 | 4341 | */ |
783f157b | 4342 | if (dma_pdev->multifunction && |
c14d2690 AW |
4343 | !pci_acs_enabled(dma_pdev, REQ_ACS_FLAGS)) { |
4344 | u8 i, slot = PCI_SLOT(dma_pdev->devfn); | |
4345 | ||
4346 | for (i = 0; i < 8; i++) { | |
4347 | struct pci_dev *tmp; | |
4348 | ||
4349 | tmp = pci_get_slot(dma_pdev->bus, PCI_DEVFN(slot, i)); | |
4350 | if (!tmp) | |
4351 | continue; | |
4352 | ||
4353 | if (!pci_acs_enabled(tmp, REQ_ACS_FLAGS)) { | |
4354 | swap_pci_ref(&dma_pdev, tmp); | |
4355 | break; | |
4356 | } | |
4357 | pci_dev_put(tmp); | |
4358 | } | |
4359 | } | |
783f157b | 4360 | |
a4ff1fc2 AW |
4361 | /* |
4362 | * Devices on the root bus go through the iommu. If that's not us, | |
4363 | * find the next upstream device and test ACS up to the root bus. | |
4364 | * Finding the next device may require skipping virtual buses. | |
4365 | */ | |
783f157b | 4366 | while (!pci_is_root_bus(dma_pdev->bus)) { |
a4ff1fc2 AW |
4367 | struct pci_bus *bus = dma_pdev->bus; |
4368 | ||
4369 | while (!bus->self) { | |
4370 | if (!pci_is_root_bus(bus)) | |
4371 | bus = bus->parent; | |
4372 | else | |
4373 | goto root_bus; | |
4374 | } | |
4375 | ||
4376 | if (pci_acs_path_enabled(bus->self, NULL, REQ_ACS_FLAGS)) | |
783f157b AW |
4377 | break; |
4378 | ||
a4ff1fc2 | 4379 | swap_pci_ref(&dma_pdev, pci_dev_get(bus->self)); |
783f157b AW |
4380 | } |
4381 | ||
a4ff1fc2 | 4382 | root_bus: |
abdfdde2 AW |
4383 | group = iommu_group_get(&dma_pdev->dev); |
4384 | pci_dev_put(dma_pdev); | |
4385 | if (!group) { | |
4386 | group = iommu_group_alloc(); | |
4387 | if (IS_ERR(group)) | |
4388 | return PTR_ERR(group); | |
70ae6f0d AW |
4389 | } |
4390 | ||
abdfdde2 | 4391 | ret = iommu_group_add_device(group, dev); |
bcb71abe | 4392 | |
abdfdde2 AW |
4393 | iommu_group_put(group); |
4394 | return ret; | |
4395 | } | |
70ae6f0d | 4396 | |
abdfdde2 AW |
4397 | static void intel_iommu_remove_device(struct device *dev) |
4398 | { | |
4399 | iommu_group_remove_device(dev); | |
70ae6f0d AW |
4400 | } |
4401 | ||
a8bcbb0d JR |
4402 | static struct iommu_ops intel_iommu_ops = { |
4403 | .domain_init = intel_iommu_domain_init, | |
4404 | .domain_destroy = intel_iommu_domain_destroy, | |
4405 | .attach_dev = intel_iommu_attach_device, | |
4406 | .detach_dev = intel_iommu_detach_device, | |
b146a1c9 JR |
4407 | .map = intel_iommu_map, |
4408 | .unmap = intel_iommu_unmap, | |
a8bcbb0d | 4409 | .iova_to_phys = intel_iommu_iova_to_phys, |
dbb9fd86 | 4410 | .domain_has_cap = intel_iommu_domain_has_cap, |
abdfdde2 AW |
4411 | .add_device = intel_iommu_add_device, |
4412 | .remove_device = intel_iommu_remove_device, | |
6d1c56a9 | 4413 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
a8bcbb0d | 4414 | }; |
9af88143 | 4415 | |
9452618e DV |
4416 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
4417 | { | |
4418 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ | |
4419 | printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); | |
4420 | dmar_map_gfx = 0; | |
4421 | } | |
4422 | ||
4423 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); | |
4424 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); | |
4425 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); | |
4426 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); | |
4427 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); | |
4428 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); | |
4429 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); | |
4430 | ||
d34d6517 | 4431 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
9af88143 DW |
4432 | { |
4433 | /* | |
4434 | * Mobile 4 Series Chipset neglects to set RWBF capability, | |
210561ff | 4435 | * but needs it. Same seems to hold for the desktop versions. |
9af88143 DW |
4436 | */ |
4437 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); | |
4438 | rwbf_quirk = 1; | |
4439 | } | |
4440 | ||
4441 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); | |
210561ff DV |
4442 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
4443 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); | |
4444 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); | |
4445 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); | |
4446 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); | |
4447 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); | |
e0fc7e0b | 4448 | |
eecfd57f AJ |
4449 | #define GGC 0x52 |
4450 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) | |
4451 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) | |
4452 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) | |
4453 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) | |
4454 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) | |
4455 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) | |
4456 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) | |
4457 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) | |
4458 | ||
d34d6517 | 4459 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
9eecabcb DW |
4460 | { |
4461 | unsigned short ggc; | |
4462 | ||
eecfd57f | 4463 | if (pci_read_config_word(dev, GGC, &ggc)) |
9eecabcb DW |
4464 | return; |
4465 | ||
eecfd57f | 4466 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
9eecabcb DW |
4467 | printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
4468 | dmar_map_gfx = 0; | |
6fbcfb3e DW |
4469 | } else if (dmar_map_gfx) { |
4470 | /* we have to ensure the gfx device is idle before we flush */ | |
4471 | printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); | |
4472 | intel_iommu_strict = 1; | |
4473 | } | |
9eecabcb DW |
4474 | } |
4475 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); | |
4476 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); | |
4477 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); | |
4478 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); | |
4479 | ||
e0fc7e0b DW |
4480 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
4481 | ISOCH DMAR unit for the Azalia sound device, but not give it any | |
4482 | TLB entries, which causes it to deadlock. Check for that. We do | |
4483 | this in a function called from init_dmars(), instead of in a PCI | |
4484 | quirk, because we don't want to print the obnoxious "BIOS broken" | |
4485 | message if VT-d is actually disabled. | |
4486 | */ | |
4487 | static void __init check_tylersburg_isoch(void) | |
4488 | { | |
4489 | struct pci_dev *pdev; | |
4490 | uint32_t vtisochctrl; | |
4491 | ||
4492 | /* If there's no Azalia in the system anyway, forget it. */ | |
4493 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); | |
4494 | if (!pdev) | |
4495 | return; | |
4496 | pci_dev_put(pdev); | |
4497 | ||
4498 | /* System Management Registers. Might be hidden, in which case | |
4499 | we can't do the sanity check. But that's OK, because the | |
4500 | known-broken BIOSes _don't_ actually hide it, so far. */ | |
4501 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); | |
4502 | if (!pdev) | |
4503 | return; | |
4504 | ||
4505 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { | |
4506 | pci_dev_put(pdev); | |
4507 | return; | |
4508 | } | |
4509 | ||
4510 | pci_dev_put(pdev); | |
4511 | ||
4512 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ | |
4513 | if (vtisochctrl & 1) | |
4514 | return; | |
4515 | ||
4516 | /* Drop all bits other than the number of TLB entries */ | |
4517 | vtisochctrl &= 0x1c; | |
4518 | ||
4519 | /* If we have the recommended number of TLB entries (16), fine. */ | |
4520 | if (vtisochctrl == 0x10) | |
4521 | return; | |
4522 | ||
4523 | /* Zero TLB entries? You get to ride the short bus to school. */ | |
4524 | if (!vtisochctrl) { | |
4525 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" | |
4526 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", | |
4527 | dmi_get_system_info(DMI_BIOS_VENDOR), | |
4528 | dmi_get_system_info(DMI_BIOS_VERSION), | |
4529 | dmi_get_system_info(DMI_PRODUCT_VERSION)); | |
4530 | iommu_identity_mapping |= IDENTMAP_AZALIA; | |
4531 | return; | |
4532 | } | |
4533 | ||
4534 | printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", | |
4535 | vtisochctrl); | |
4536 | } |