]>
Commit | Line | Data |
---|---|---|
5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
ad3ad3f6 | 9 | #include <asm/io_apic.h> |
17483a1f | 10 | #include <asm/smp.h> |
6d652ea1 | 11 | #include <asm/cpu.h> |
38717946 | 12 | #include <linux/intel-iommu.h> |
46f06b72 | 13 | #include <acpi/acpi.h> |
736baef4 | 14 | #include <asm/intr_remapping.h> |
f007e99c | 15 | #include <asm/pci-direct.h> |
ad3ad3f6 | 16 | |
736baef4 JR |
17 | #include "intr_remapping.h" |
18 | ||
eef93fdb JR |
19 | struct ioapic_scope { |
20 | struct intel_iommu *iommu; | |
21 | unsigned int id; | |
22 | unsigned int bus; /* PCI bus number */ | |
23 | unsigned int devfn; /* PCI devfn number */ | |
24 | }; | |
25 | ||
26 | struct hpet_scope { | |
27 | struct intel_iommu *iommu; | |
28 | u8 id; | |
29 | unsigned int bus; | |
30 | unsigned int devfn; | |
31 | }; | |
32 | ||
33 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
34 | ||
ad3ad3f6 | 35 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b SS |
36 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
37 | static int ir_ioapic_num, ir_hpet_num; | |
d1423d56 | 38 | |
96f8e98b | 39 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 40 | |
e420dfb4 YL |
41 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
42 | { | |
dced35ae | 43 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
349d6767 | 44 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
45 | } |
46 | ||
b6fcb33a SS |
47 | int get_irte(int irq, struct irte *entry) |
48 | { | |
d585d060 | 49 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 50 | unsigned long flags; |
d585d060 | 51 | int index; |
b6fcb33a | 52 | |
d585d060 | 53 | if (!entry || !irq_iommu) |
b6fcb33a SS |
54 | return -1; |
55 | ||
96f8e98b | 56 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 57 | |
e420dfb4 YL |
58 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
59 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 60 | |
96f8e98b | 61 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
62 | return 0; |
63 | } | |
64 | ||
65 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
66 | { | |
67 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 68 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a SS |
69 | u16 index, start_index; |
70 | unsigned int mask = 0; | |
4c5502b1 | 71 | unsigned long flags; |
b6fcb33a SS |
72 | int i; |
73 | ||
d585d060 | 74 | if (!count || !irq_iommu) |
e420dfb4 | 75 | return -1; |
e420dfb4 | 76 | |
b6fcb33a SS |
77 | /* |
78 | * start the IRTE search from index 0. | |
79 | */ | |
80 | index = start_index = 0; | |
81 | ||
82 | if (count > 1) { | |
83 | count = __roundup_pow_of_two(count); | |
84 | mask = ilog2(count); | |
85 | } | |
86 | ||
87 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
88 | printk(KERN_ERR | |
89 | "Requested mask %x exceeds the max invalidation handle" | |
90 | " mask value %Lx\n", mask, | |
91 | ecap_max_handle_mask(iommu->ecap)); | |
92 | return -1; | |
93 | } | |
94 | ||
96f8e98b | 95 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
96 | do { |
97 | for (i = index; i < index + count; i++) | |
98 | if (table->base[i].present) | |
99 | break; | |
100 | /* empty index found */ | |
101 | if (i == index + count) | |
102 | break; | |
103 | ||
104 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
105 | ||
106 | if (index == start_index) { | |
96f8e98b | 107 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
108 | printk(KERN_ERR "can't allocate an IRTE\n"); |
109 | return -1; | |
110 | } | |
111 | } while (1); | |
112 | ||
113 | for (i = index; i < index + count; i++) | |
114 | table->base[i].present = 1; | |
115 | ||
e420dfb4 YL |
116 | irq_iommu->iommu = iommu; |
117 | irq_iommu->irte_index = index; | |
118 | irq_iommu->sub_handle = 0; | |
119 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 120 | |
96f8e98b | 121 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
122 | |
123 | return index; | |
124 | } | |
125 | ||
704126ad | 126 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
127 | { |
128 | struct qi_desc desc; | |
129 | ||
130 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
131 | | QI_IEC_SELECTIVE; | |
132 | desc.high = 0; | |
133 | ||
704126ad | 134 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
135 | } |
136 | ||
137 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
138 | { | |
d585d060 | 139 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 140 | unsigned long flags; |
d585d060 | 141 | int index; |
b6fcb33a | 142 | |
d585d060 | 143 | if (!irq_iommu) |
b6fcb33a | 144 | return -1; |
b6fcb33a | 145 | |
96f8e98b | 146 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
147 | *sub_handle = irq_iommu->sub_handle; |
148 | index = irq_iommu->irte_index; | |
96f8e98b | 149 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
150 | return index; |
151 | } | |
152 | ||
153 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
154 | { | |
d585d060 | 155 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 156 | unsigned long flags; |
e420dfb4 | 157 | |
d585d060 | 158 | if (!irq_iommu) |
0b8f1efa | 159 | return -1; |
d585d060 | 160 | |
96f8e98b | 161 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 162 | |
e420dfb4 YL |
163 | irq_iommu->iommu = iommu; |
164 | irq_iommu->irte_index = index; | |
165 | irq_iommu->sub_handle = subhandle; | |
166 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 167 | |
96f8e98b | 168 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
169 | |
170 | return 0; | |
171 | } | |
172 | ||
b6fcb33a SS |
173 | int modify_irte(int irq, struct irte *irte_modified) |
174 | { | |
d585d060 | 175 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 176 | struct intel_iommu *iommu; |
4c5502b1 | 177 | unsigned long flags; |
d585d060 TG |
178 | struct irte *irte; |
179 | int rc, index; | |
b6fcb33a | 180 | |
d585d060 | 181 | if (!irq_iommu) |
b6fcb33a | 182 | return -1; |
d585d060 | 183 | |
96f8e98b | 184 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 185 | |
e420dfb4 | 186 | iommu = irq_iommu->iommu; |
b6fcb33a | 187 | |
e420dfb4 | 188 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
189 | irte = &iommu->ir_table->base[index]; |
190 | ||
c513b67e LT |
191 | set_64bit(&irte->low, irte_modified->low); |
192 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
193 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
194 | ||
704126ad | 195 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 196 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
197 | |
198 | return rc; | |
b6fcb33a SS |
199 | } |
200 | ||
20f3097b SS |
201 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
202 | { | |
203 | int i; | |
204 | ||
205 | for (i = 0; i < MAX_HPET_TBS; i++) | |
206 | if (ir_hpet[i].id == hpet_id) | |
207 | return ir_hpet[i].iommu; | |
208 | return NULL; | |
209 | } | |
210 | ||
89027d35 SS |
211 | struct intel_iommu *map_ioapic_to_ir(int apic) |
212 | { | |
213 | int i; | |
214 | ||
215 | for (i = 0; i < MAX_IO_APICS; i++) | |
216 | if (ir_ioapic[i].id == apic) | |
217 | return ir_ioapic[i].iommu; | |
218 | return NULL; | |
219 | } | |
220 | ||
75c46fa6 SS |
221 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
222 | { | |
223 | struct dmar_drhd_unit *drhd; | |
224 | ||
225 | drhd = dmar_find_matched_drhd_unit(dev); | |
226 | if (!drhd) | |
227 | return NULL; | |
228 | ||
229 | return drhd->iommu; | |
230 | } | |
231 | ||
c4658b4e WH |
232 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
233 | { | |
234 | struct irte *start, *entry, *end; | |
235 | struct intel_iommu *iommu; | |
236 | int index; | |
237 | ||
238 | if (irq_iommu->sub_handle) | |
239 | return 0; | |
240 | ||
241 | iommu = irq_iommu->iommu; | |
242 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
243 | ||
244 | start = iommu->ir_table->base + index; | |
245 | end = start + (1 << irq_iommu->irte_mask); | |
246 | ||
247 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
248 | set_64bit(&entry->low, 0); |
249 | set_64bit(&entry->high, 0); | |
c4658b4e WH |
250 | } |
251 | ||
252 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
253 | } | |
254 | ||
b6fcb33a SS |
255 | int free_irte(int irq) |
256 | { | |
d585d060 | 257 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 258 | unsigned long flags; |
d585d060 | 259 | int rc; |
b6fcb33a | 260 | |
d585d060 | 261 | if (!irq_iommu) |
b6fcb33a | 262 | return -1; |
d585d060 | 263 | |
96f8e98b | 264 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 265 | |
c4658b4e | 266 | rc = clear_entries(irq_iommu); |
b6fcb33a | 267 | |
e420dfb4 YL |
268 | irq_iommu->iommu = NULL; |
269 | irq_iommu->irte_index = 0; | |
270 | irq_iommu->sub_handle = 0; | |
271 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 272 | |
96f8e98b | 273 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 274 | |
704126ad | 275 | return rc; |
b6fcb33a SS |
276 | } |
277 | ||
f007e99c WH |
278 | /* |
279 | * source validation type | |
280 | */ | |
281 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 282 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
283 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
284 | ||
285 | /* | |
286 | * source-id qualifier | |
287 | */ | |
288 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
289 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
290 | * the third least significant bit | |
291 | */ | |
292 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
293 | * the second and third least significant bits | |
294 | */ | |
295 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
296 | * the least three significant bits | |
297 | */ | |
298 | ||
299 | /* | |
300 | * set SVT, SQ and SID fields of irte to verify | |
301 | * source ids of interrupt requests | |
302 | */ | |
303 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
304 | unsigned int sq, unsigned int sid) | |
305 | { | |
d1423d56 CW |
306 | if (disable_sourceid_checking) |
307 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
308 | irte->svt = svt; |
309 | irte->sq = sq; | |
310 | irte->sid = sid; | |
311 | } | |
312 | ||
313 | int set_ioapic_sid(struct irte *irte, int apic) | |
314 | { | |
315 | int i; | |
316 | u16 sid = 0; | |
317 | ||
318 | if (!irte) | |
319 | return -1; | |
320 | ||
321 | for (i = 0; i < MAX_IO_APICS; i++) { | |
322 | if (ir_ioapic[i].id == apic) { | |
323 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
324 | break; | |
325 | } | |
326 | } | |
327 | ||
328 | if (sid == 0) { | |
329 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
330 | return -1; | |
331 | } | |
332 | ||
333 | set_irte_sid(irte, 1, 0, sid); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
20f3097b SS |
338 | int set_hpet_sid(struct irte *irte, u8 id) |
339 | { | |
340 | int i; | |
341 | u16 sid = 0; | |
342 | ||
343 | if (!irte) | |
344 | return -1; | |
345 | ||
346 | for (i = 0; i < MAX_HPET_TBS; i++) { | |
347 | if (ir_hpet[i].id == id) { | |
348 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; | |
349 | break; | |
350 | } | |
351 | } | |
352 | ||
353 | if (sid == 0) { | |
354 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
355 | return -1; | |
356 | } | |
357 | ||
358 | /* | |
359 | * Should really use SQ_ALL_16. Some platforms are broken. | |
360 | * While we figure out the right quirks for these broken platforms, use | |
361 | * SQ_13_IGNORE_3 for now. | |
362 | */ | |
363 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
f007e99c WH |
368 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
369 | { | |
370 | struct pci_dev *bridge; | |
371 | ||
372 | if (!irte || !dev) | |
373 | return -1; | |
374 | ||
375 | /* PCIe device or Root Complex integrated PCI device */ | |
5f4d91a1 | 376 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
f007e99c WH |
377 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
378 | (dev->bus->number << 8) | dev->devfn); | |
379 | return 0; | |
380 | } | |
381 | ||
382 | bridge = pci_find_upstream_pcie_bridge(dev); | |
383 | if (bridge) { | |
45e829ea | 384 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
f007e99c WH |
385 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
386 | (bridge->bus->number << 8) | dev->bus->number); | |
387 | else /* this is a legacy PCI bridge */ | |
388 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
389 | (bridge->bus->number << 8) | bridge->devfn); | |
390 | } | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
2ae21010 SS |
395 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
396 | { | |
397 | u64 addr; | |
c416daa9 | 398 | u32 sts; |
2ae21010 SS |
399 | unsigned long flags; |
400 | ||
401 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
402 | ||
1f5b3c3f | 403 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
404 | |
405 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
406 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
407 | ||
408 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 409 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 410 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
411 | |
412 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
413 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 414 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
415 | |
416 | /* | |
417 | * global invalidation of interrupt entry cache before enabling | |
418 | * interrupt-remapping. | |
419 | */ | |
420 | qi_global_iec(iommu); | |
421 | ||
1f5b3c3f | 422 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
423 | |
424 | /* Enable interrupt-remapping */ | |
2ae21010 | 425 | iommu->gcmd |= DMA_GCMD_IRE; |
c416daa9 | 426 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
427 | |
428 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
429 | readl, (sts & DMA_GSTS_IRES), sts); | |
430 | ||
1f5b3c3f | 431 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
432 | } |
433 | ||
434 | ||
736baef4 | 435 | static int intel_setup_intr_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
436 | { |
437 | struct ir_table *ir_table; | |
438 | struct page *pages; | |
439 | ||
440 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 441 | GFP_ATOMIC); |
2ae21010 SS |
442 | |
443 | if (!iommu->ir_table) | |
444 | return -ENOMEM; | |
445 | ||
824cd75b SS |
446 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
447 | INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
448 | |
449 | if (!pages) { | |
450 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
451 | INTR_REMAP_PAGE_ORDER); | |
452 | kfree(iommu->ir_table); | |
453 | return -ENOMEM; | |
454 | } | |
455 | ||
456 | ir_table->base = page_address(pages); | |
457 | ||
458 | iommu_set_intr_remapping(iommu, mode); | |
459 | return 0; | |
460 | } | |
461 | ||
eba67e5d SS |
462 | /* |
463 | * Disable Interrupt Remapping. | |
464 | */ | |
b24696bc | 465 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
466 | { |
467 | unsigned long flags; | |
468 | u32 sts; | |
469 | ||
470 | if (!ecap_ir_support(iommu->ecap)) | |
471 | return; | |
472 | ||
b24696bc FY |
473 | /* |
474 | * global invalidation of interrupt entry cache before disabling | |
475 | * interrupt-remapping. | |
476 | */ | |
477 | qi_global_iec(iommu); | |
478 | ||
1f5b3c3f | 479 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
480 | |
481 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
482 | if (!(sts & DMA_GSTS_IRES)) | |
483 | goto end; | |
484 | ||
485 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
486 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
487 | ||
488 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
489 | readl, !(sts & DMA_GSTS_IRES), sts); | |
490 | ||
491 | end: | |
1f5b3c3f | 492 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
493 | } |
494 | ||
41750d31 SS |
495 | static int __init dmar_x2apic_optout(void) |
496 | { | |
497 | struct acpi_table_dmar *dmar; | |
498 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
499 | if (!dmar || no_x2apic_optout) | |
500 | return 0; | |
501 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
502 | } | |
503 | ||
736baef4 | 504 | static int __init intel_intr_remapping_supported(void) |
93758238 WH |
505 | { |
506 | struct dmar_drhd_unit *drhd; | |
507 | ||
03ea8155 WH |
508 | if (disable_intremap) |
509 | return 0; | |
510 | ||
074835f0 YS |
511 | if (!dmar_ir_support()) |
512 | return 0; | |
513 | ||
93758238 WH |
514 | for_each_drhd_unit(drhd) { |
515 | struct intel_iommu *iommu = drhd->iommu; | |
516 | ||
517 | if (!ecap_ir_support(iommu->ecap)) | |
518 | return 0; | |
519 | } | |
520 | ||
521 | return 1; | |
522 | } | |
523 | ||
736baef4 | 524 | static int __init intel_enable_intr_remapping(void) |
2ae21010 SS |
525 | { |
526 | struct dmar_drhd_unit *drhd; | |
527 | int setup = 0; | |
41750d31 | 528 | int eim = 0; |
2ae21010 | 529 | |
e936d077 YS |
530 | if (parse_ioapics_under_ir() != 1) { |
531 | printk(KERN_INFO "Not enable interrupt remapping\n"); | |
532 | return -1; | |
533 | } | |
534 | ||
41750d31 SS |
535 | if (x2apic_supported()) { |
536 | eim = !dmar_x2apic_optout(); | |
537 | WARN(!eim, KERN_WARNING | |
538 | "Your BIOS is broken and requested that x2apic be disabled\n" | |
539 | "This will leave your machine vulnerable to irq-injection attacks\n" | |
540 | "Use 'intremap=no_x2apic_optout' to override BIOS request\n"); | |
541 | } | |
542 | ||
1531a6a6 SS |
543 | for_each_drhd_unit(drhd) { |
544 | struct intel_iommu *iommu = drhd->iommu; | |
545 | ||
34aaaa94 HW |
546 | /* |
547 | * If the queued invalidation is already initialized, | |
548 | * shouldn't disable it. | |
549 | */ | |
550 | if (iommu->qi) | |
551 | continue; | |
552 | ||
1531a6a6 SS |
553 | /* |
554 | * Clear previous faults. | |
555 | */ | |
556 | dmar_fault(-1, iommu); | |
557 | ||
558 | /* | |
559 | * Disable intr remapping and queued invalidation, if already | |
560 | * enabled prior to OS handover. | |
561 | */ | |
b24696bc | 562 | iommu_disable_intr_remapping(iommu); |
1531a6a6 SS |
563 | |
564 | dmar_disable_qi(iommu); | |
565 | } | |
566 | ||
2ae21010 SS |
567 | /* |
568 | * check for the Interrupt-remapping support | |
569 | */ | |
570 | for_each_drhd_unit(drhd) { | |
571 | struct intel_iommu *iommu = drhd->iommu; | |
572 | ||
573 | if (!ecap_ir_support(iommu->ecap)) | |
574 | continue; | |
575 | ||
576 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
577 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
578 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
579 | return -1; | |
580 | } | |
581 | } | |
582 | ||
583 | /* | |
584 | * Enable queued invalidation for all the DRHD's. | |
585 | */ | |
586 | for_each_drhd_unit(drhd) { | |
587 | int ret; | |
588 | struct intel_iommu *iommu = drhd->iommu; | |
589 | ret = dmar_enable_qi(iommu); | |
590 | ||
591 | if (ret) { | |
592 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
593 | " invalidation, ecap %Lx, ret %d\n", | |
594 | drhd->reg_base_addr, iommu->ecap, ret); | |
595 | return -1; | |
596 | } | |
597 | } | |
598 | ||
599 | /* | |
600 | * Setup Interrupt-remapping for all the DRHD's now. | |
601 | */ | |
602 | for_each_drhd_unit(drhd) { | |
603 | struct intel_iommu *iommu = drhd->iommu; | |
604 | ||
605 | if (!ecap_ir_support(iommu->ecap)) | |
606 | continue; | |
607 | ||
736baef4 | 608 | if (intel_setup_intr_remapping(iommu, eim)) |
2ae21010 SS |
609 | goto error; |
610 | ||
611 | setup = 1; | |
612 | } | |
613 | ||
614 | if (!setup) | |
615 | goto error; | |
616 | ||
617 | intr_remapping_enabled = 1; | |
41750d31 | 618 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 619 | |
41750d31 | 620 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
621 | |
622 | error: | |
623 | /* | |
624 | * handle error condition gracefully here! | |
625 | */ | |
626 | return -1; | |
627 | } | |
ad3ad3f6 | 628 | |
20f3097b SS |
629 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
630 | struct intel_iommu *iommu) | |
631 | { | |
632 | struct acpi_dmar_pci_path *path; | |
633 | u8 bus; | |
634 | int count; | |
635 | ||
636 | bus = scope->bus; | |
637 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
638 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
639 | / sizeof(struct acpi_dmar_pci_path); | |
640 | ||
641 | while (--count > 0) { | |
642 | /* | |
643 | * Access PCI directly due to the PCI | |
644 | * subsystem isn't initialized yet. | |
645 | */ | |
646 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
647 | PCI_SECONDARY_BUS); | |
648 | path++; | |
649 | } | |
650 | ir_hpet[ir_hpet_num].bus = bus; | |
651 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
652 | ir_hpet[ir_hpet_num].iommu = iommu; | |
653 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; | |
654 | ir_hpet_num++; | |
655 | } | |
656 | ||
f007e99c WH |
657 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
658 | struct intel_iommu *iommu) | |
659 | { | |
660 | struct acpi_dmar_pci_path *path; | |
661 | u8 bus; | |
662 | int count; | |
663 | ||
664 | bus = scope->bus; | |
665 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
666 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
667 | / sizeof(struct acpi_dmar_pci_path); | |
668 | ||
669 | while (--count > 0) { | |
670 | /* | |
671 | * Access PCI directly due to the PCI | |
672 | * subsystem isn't initialized yet. | |
673 | */ | |
674 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
675 | PCI_SECONDARY_BUS); | |
676 | path++; | |
677 | } | |
678 | ||
679 | ir_ioapic[ir_ioapic_num].bus = bus; | |
680 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
681 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
682 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
683 | ir_ioapic_num++; | |
684 | } | |
685 | ||
20f3097b SS |
686 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
687 | struct intel_iommu *iommu) | |
ad3ad3f6 SS |
688 | { |
689 | struct acpi_dmar_hardware_unit *drhd; | |
690 | struct acpi_dmar_device_scope *scope; | |
691 | void *start, *end; | |
692 | ||
693 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
694 | ||
695 | start = (void *)(drhd + 1); | |
696 | end = ((void *)drhd) + header->length; | |
697 | ||
698 | while (start < end) { | |
699 | scope = start; | |
700 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
701 | if (ir_ioapic_num == MAX_IO_APICS) { | |
702 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
703 | return -1; | |
704 | } | |
705 | ||
680a7524 YL |
706 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
707 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, | |
708 | drhd->address, iommu->seq_id); | |
ad3ad3f6 | 709 | |
f007e99c | 710 | ir_parse_one_ioapic_scope(scope, iommu); |
20f3097b SS |
711 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
712 | if (ir_hpet_num == MAX_HPET_TBS) { | |
713 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); | |
714 | return -1; | |
715 | } | |
716 | ||
717 | printk(KERN_INFO "HPET id %d under DRHD base" | |
718 | " 0x%Lx\n", scope->enumeration_id, | |
719 | drhd->address); | |
720 | ||
721 | ir_parse_one_hpet_scope(scope, iommu); | |
ad3ad3f6 SS |
722 | } |
723 | start += scope->length; | |
724 | } | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | /* | |
730 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
731 | * hardware unit. | |
732 | */ | |
733 | int __init parse_ioapics_under_ir(void) | |
734 | { | |
735 | struct dmar_drhd_unit *drhd; | |
736 | int ir_supported = 0; | |
737 | ||
738 | for_each_drhd_unit(drhd) { | |
739 | struct intel_iommu *iommu = drhd->iommu; | |
740 | ||
741 | if (ecap_ir_support(iommu->ecap)) { | |
20f3097b | 742 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
743 | return -1; |
744 | ||
745 | ir_supported = 1; | |
746 | } | |
747 | } | |
748 | ||
749 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
750 | printk(KERN_WARNING | |
751 | "Not all IO-APIC's listed under remapping hardware\n"); | |
752 | return -1; | |
753 | } | |
754 | ||
755 | return ir_supported; | |
756 | } | |
b24696bc | 757 | |
61ed26e3 | 758 | int __init ir_dev_scope_init(void) |
c2c7286a SS |
759 | { |
760 | if (!intr_remapping_enabled) | |
761 | return 0; | |
762 | ||
763 | return dmar_dev_scope_init(); | |
764 | } | |
765 | rootfs_initcall(ir_dev_scope_init); | |
766 | ||
4f3d8b67 | 767 | static void disable_intr_remapping(void) |
b24696bc FY |
768 | { |
769 | struct dmar_drhd_unit *drhd; | |
770 | struct intel_iommu *iommu = NULL; | |
771 | ||
772 | /* | |
773 | * Disable Interrupt-remapping for all the DRHD's now. | |
774 | */ | |
775 | for_each_iommu(iommu, drhd) { | |
776 | if (!ecap_ir_support(iommu->ecap)) | |
777 | continue; | |
778 | ||
779 | iommu_disable_intr_remapping(iommu); | |
780 | } | |
781 | } | |
782 | ||
4f3d8b67 | 783 | static int reenable_intr_remapping(int eim) |
b24696bc FY |
784 | { |
785 | struct dmar_drhd_unit *drhd; | |
786 | int setup = 0; | |
787 | struct intel_iommu *iommu = NULL; | |
788 | ||
789 | for_each_iommu(iommu, drhd) | |
790 | if (iommu->qi) | |
791 | dmar_reenable_qi(iommu); | |
792 | ||
793 | /* | |
794 | * Setup Interrupt-remapping for all the DRHD's now. | |
795 | */ | |
796 | for_each_iommu(iommu, drhd) { | |
797 | if (!ecap_ir_support(iommu->ecap)) | |
798 | continue; | |
799 | ||
800 | /* Set up interrupt remapping for iommu.*/ | |
801 | iommu_set_intr_remapping(iommu, eim); | |
802 | setup = 1; | |
803 | } | |
804 | ||
805 | if (!setup) | |
806 | goto error; | |
807 | ||
808 | return 0; | |
809 | ||
810 | error: | |
811 | /* | |
812 | * handle error condition gracefully here! | |
813 | */ | |
814 | return -1; | |
815 | } | |
816 | ||
736baef4 JR |
817 | struct irq_remap_ops intel_irq_remap_ops = { |
818 | .supported = intel_intr_remapping_supported, | |
819 | .hardware_init = dmar_table_init, | |
820 | .hardware_enable = intel_enable_intr_remapping, | |
4f3d8b67 JR |
821 | .hardware_disable = disable_intr_remapping, |
822 | .hardware_reenable = reenable_intr_remapping, | |
823 | .enable_faulting = enable_drhd_fault_handling, | |
736baef4 | 824 | }; |