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Commit | Line | Data |
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5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
ad3ad3f6 | 9 | #include <asm/io_apic.h> |
17483a1f | 10 | #include <asm/smp.h> |
6d652ea1 | 11 | #include <asm/cpu.h> |
38717946 | 12 | #include <linux/intel-iommu.h> |
46f06b72 | 13 | #include <acpi/acpi.h> |
736baef4 | 14 | #include <asm/intr_remapping.h> |
f007e99c | 15 | #include <asm/pci-direct.h> |
ad3ad3f6 | 16 | |
736baef4 JR |
17 | #include "intr_remapping.h" |
18 | ||
eef93fdb JR |
19 | struct ioapic_scope { |
20 | struct intel_iommu *iommu; | |
21 | unsigned int id; | |
22 | unsigned int bus; /* PCI bus number */ | |
23 | unsigned int devfn; /* PCI devfn number */ | |
24 | }; | |
25 | ||
26 | struct hpet_scope { | |
27 | struct intel_iommu *iommu; | |
28 | u8 id; | |
29 | unsigned int bus; | |
30 | unsigned int devfn; | |
31 | }; | |
32 | ||
33 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
0c3f173a | 34 | #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) |
eef93fdb | 35 | |
ad3ad3f6 | 36 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b SS |
37 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
38 | static int ir_ioapic_num, ir_hpet_num; | |
d1423d56 | 39 | |
96f8e98b | 40 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 41 | |
e420dfb4 YL |
42 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
43 | { | |
dced35ae | 44 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
349d6767 | 45 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
46 | } |
47 | ||
b6fcb33a SS |
48 | int get_irte(int irq, struct irte *entry) |
49 | { | |
d585d060 | 50 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 51 | unsigned long flags; |
d585d060 | 52 | int index; |
b6fcb33a | 53 | |
d585d060 | 54 | if (!entry || !irq_iommu) |
b6fcb33a SS |
55 | return -1; |
56 | ||
96f8e98b | 57 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 58 | |
e420dfb4 YL |
59 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
60 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 61 | |
96f8e98b | 62 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
63 | return 0; |
64 | } | |
65 | ||
66 | int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) | |
67 | { | |
68 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 69 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a SS |
70 | u16 index, start_index; |
71 | unsigned int mask = 0; | |
4c5502b1 | 72 | unsigned long flags; |
b6fcb33a SS |
73 | int i; |
74 | ||
d585d060 | 75 | if (!count || !irq_iommu) |
e420dfb4 | 76 | return -1; |
e420dfb4 | 77 | |
b6fcb33a SS |
78 | /* |
79 | * start the IRTE search from index 0. | |
80 | */ | |
81 | index = start_index = 0; | |
82 | ||
83 | if (count > 1) { | |
84 | count = __roundup_pow_of_two(count); | |
85 | mask = ilog2(count); | |
86 | } | |
87 | ||
88 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
89 | printk(KERN_ERR | |
90 | "Requested mask %x exceeds the max invalidation handle" | |
91 | " mask value %Lx\n", mask, | |
92 | ecap_max_handle_mask(iommu->ecap)); | |
93 | return -1; | |
94 | } | |
95 | ||
96f8e98b | 96 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
97 | do { |
98 | for (i = index; i < index + count; i++) | |
99 | if (table->base[i].present) | |
100 | break; | |
101 | /* empty index found */ | |
102 | if (i == index + count) | |
103 | break; | |
104 | ||
105 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
106 | ||
107 | if (index == start_index) { | |
96f8e98b | 108 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
109 | printk(KERN_ERR "can't allocate an IRTE\n"); |
110 | return -1; | |
111 | } | |
112 | } while (1); | |
113 | ||
114 | for (i = index; i < index + count; i++) | |
115 | table->base[i].present = 1; | |
116 | ||
e420dfb4 YL |
117 | irq_iommu->iommu = iommu; |
118 | irq_iommu->irte_index = index; | |
119 | irq_iommu->sub_handle = 0; | |
120 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 121 | |
96f8e98b | 122 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
123 | |
124 | return index; | |
125 | } | |
126 | ||
704126ad | 127 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
128 | { |
129 | struct qi_desc desc; | |
130 | ||
131 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
132 | | QI_IEC_SELECTIVE; | |
133 | desc.high = 0; | |
134 | ||
704126ad | 135 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
136 | } |
137 | ||
138 | int map_irq_to_irte_handle(int irq, u16 *sub_handle) | |
139 | { | |
d585d060 | 140 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 141 | unsigned long flags; |
d585d060 | 142 | int index; |
b6fcb33a | 143 | |
d585d060 | 144 | if (!irq_iommu) |
b6fcb33a | 145 | return -1; |
b6fcb33a | 146 | |
96f8e98b | 147 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
148 | *sub_handle = irq_iommu->sub_handle; |
149 | index = irq_iommu->irte_index; | |
96f8e98b | 150 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
151 | return index; |
152 | } | |
153 | ||
154 | int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) | |
155 | { | |
d585d060 | 156 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 157 | unsigned long flags; |
e420dfb4 | 158 | |
d585d060 | 159 | if (!irq_iommu) |
0b8f1efa | 160 | return -1; |
d585d060 | 161 | |
96f8e98b | 162 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 163 | |
e420dfb4 YL |
164 | irq_iommu->iommu = iommu; |
165 | irq_iommu->irte_index = index; | |
166 | irq_iommu->sub_handle = subhandle; | |
167 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 168 | |
96f8e98b | 169 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
170 | |
171 | return 0; | |
172 | } | |
173 | ||
b6fcb33a SS |
174 | int modify_irte(int irq, struct irte *irte_modified) |
175 | { | |
d585d060 | 176 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 177 | struct intel_iommu *iommu; |
4c5502b1 | 178 | unsigned long flags; |
d585d060 TG |
179 | struct irte *irte; |
180 | int rc, index; | |
b6fcb33a | 181 | |
d585d060 | 182 | if (!irq_iommu) |
b6fcb33a | 183 | return -1; |
d585d060 | 184 | |
96f8e98b | 185 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 186 | |
e420dfb4 | 187 | iommu = irq_iommu->iommu; |
b6fcb33a | 188 | |
e420dfb4 | 189 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
190 | irte = &iommu->ir_table->base[index]; |
191 | ||
c513b67e LT |
192 | set_64bit(&irte->low, irte_modified->low); |
193 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
194 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
195 | ||
704126ad | 196 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 197 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
198 | |
199 | return rc; | |
b6fcb33a SS |
200 | } |
201 | ||
20f3097b SS |
202 | struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
203 | { | |
204 | int i; | |
205 | ||
206 | for (i = 0; i < MAX_HPET_TBS; i++) | |
207 | if (ir_hpet[i].id == hpet_id) | |
208 | return ir_hpet[i].iommu; | |
209 | return NULL; | |
210 | } | |
211 | ||
89027d35 SS |
212 | struct intel_iommu *map_ioapic_to_ir(int apic) |
213 | { | |
214 | int i; | |
215 | ||
216 | for (i = 0; i < MAX_IO_APICS; i++) | |
217 | if (ir_ioapic[i].id == apic) | |
218 | return ir_ioapic[i].iommu; | |
219 | return NULL; | |
220 | } | |
221 | ||
75c46fa6 SS |
222 | struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
223 | { | |
224 | struct dmar_drhd_unit *drhd; | |
225 | ||
226 | drhd = dmar_find_matched_drhd_unit(dev); | |
227 | if (!drhd) | |
228 | return NULL; | |
229 | ||
230 | return drhd->iommu; | |
231 | } | |
232 | ||
c4658b4e WH |
233 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
234 | { | |
235 | struct irte *start, *entry, *end; | |
236 | struct intel_iommu *iommu; | |
237 | int index; | |
238 | ||
239 | if (irq_iommu->sub_handle) | |
240 | return 0; | |
241 | ||
242 | iommu = irq_iommu->iommu; | |
243 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
244 | ||
245 | start = iommu->ir_table->base + index; | |
246 | end = start + (1 << irq_iommu->irte_mask); | |
247 | ||
248 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
249 | set_64bit(&entry->low, 0); |
250 | set_64bit(&entry->high, 0); | |
c4658b4e WH |
251 | } |
252 | ||
253 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
254 | } | |
255 | ||
9d619f65 | 256 | static int free_irte(int irq) |
b6fcb33a | 257 | { |
d585d060 | 258 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 259 | unsigned long flags; |
d585d060 | 260 | int rc; |
b6fcb33a | 261 | |
d585d060 | 262 | if (!irq_iommu) |
b6fcb33a | 263 | return -1; |
d585d060 | 264 | |
96f8e98b | 265 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 266 | |
c4658b4e | 267 | rc = clear_entries(irq_iommu); |
b6fcb33a | 268 | |
e420dfb4 YL |
269 | irq_iommu->iommu = NULL; |
270 | irq_iommu->irte_index = 0; | |
271 | irq_iommu->sub_handle = 0; | |
272 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 273 | |
96f8e98b | 274 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 275 | |
704126ad | 276 | return rc; |
b6fcb33a SS |
277 | } |
278 | ||
f007e99c WH |
279 | /* |
280 | * source validation type | |
281 | */ | |
282 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 283 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
284 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
285 | ||
286 | /* | |
287 | * source-id qualifier | |
288 | */ | |
289 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
290 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
291 | * the third least significant bit | |
292 | */ | |
293 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
294 | * the second and third least significant bits | |
295 | */ | |
296 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
297 | * the least three significant bits | |
298 | */ | |
299 | ||
300 | /* | |
301 | * set SVT, SQ and SID fields of irte to verify | |
302 | * source ids of interrupt requests | |
303 | */ | |
304 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
305 | unsigned int sq, unsigned int sid) | |
306 | { | |
d1423d56 CW |
307 | if (disable_sourceid_checking) |
308 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
309 | irte->svt = svt; |
310 | irte->sq = sq; | |
311 | irte->sid = sid; | |
312 | } | |
313 | ||
314 | int set_ioapic_sid(struct irte *irte, int apic) | |
315 | { | |
316 | int i; | |
317 | u16 sid = 0; | |
318 | ||
319 | if (!irte) | |
320 | return -1; | |
321 | ||
322 | for (i = 0; i < MAX_IO_APICS; i++) { | |
323 | if (ir_ioapic[i].id == apic) { | |
324 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
325 | break; | |
326 | } | |
327 | } | |
328 | ||
329 | if (sid == 0) { | |
330 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
331 | return -1; | |
332 | } | |
333 | ||
334 | set_irte_sid(irte, 1, 0, sid); | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
20f3097b SS |
339 | int set_hpet_sid(struct irte *irte, u8 id) |
340 | { | |
341 | int i; | |
342 | u16 sid = 0; | |
343 | ||
344 | if (!irte) | |
345 | return -1; | |
346 | ||
347 | for (i = 0; i < MAX_HPET_TBS; i++) { | |
348 | if (ir_hpet[i].id == id) { | |
349 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; | |
350 | break; | |
351 | } | |
352 | } | |
353 | ||
354 | if (sid == 0) { | |
355 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
356 | return -1; | |
357 | } | |
358 | ||
359 | /* | |
360 | * Should really use SQ_ALL_16. Some platforms are broken. | |
361 | * While we figure out the right quirks for these broken platforms, use | |
362 | * SQ_13_IGNORE_3 for now. | |
363 | */ | |
364 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
365 | ||
366 | return 0; | |
367 | } | |
368 | ||
f007e99c WH |
369 | int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
370 | { | |
371 | struct pci_dev *bridge; | |
372 | ||
373 | if (!irte || !dev) | |
374 | return -1; | |
375 | ||
376 | /* PCIe device or Root Complex integrated PCI device */ | |
5f4d91a1 | 377 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
f007e99c WH |
378 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
379 | (dev->bus->number << 8) | dev->devfn); | |
380 | return 0; | |
381 | } | |
382 | ||
383 | bridge = pci_find_upstream_pcie_bridge(dev); | |
384 | if (bridge) { | |
45e829ea | 385 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
f007e99c WH |
386 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
387 | (bridge->bus->number << 8) | dev->bus->number); | |
388 | else /* this is a legacy PCI bridge */ | |
389 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
390 | (bridge->bus->number << 8) | bridge->devfn); | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
2ae21010 SS |
396 | static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode) |
397 | { | |
398 | u64 addr; | |
c416daa9 | 399 | u32 sts; |
2ae21010 SS |
400 | unsigned long flags; |
401 | ||
402 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
403 | ||
1f5b3c3f | 404 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
405 | |
406 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
407 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
408 | ||
409 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 410 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 411 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
412 | |
413 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
414 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 415 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
416 | |
417 | /* | |
418 | * global invalidation of interrupt entry cache before enabling | |
419 | * interrupt-remapping. | |
420 | */ | |
421 | qi_global_iec(iommu); | |
422 | ||
1f5b3c3f | 423 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
424 | |
425 | /* Enable interrupt-remapping */ | |
2ae21010 | 426 | iommu->gcmd |= DMA_GCMD_IRE; |
c416daa9 | 427 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
428 | |
429 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
430 | readl, (sts & DMA_GSTS_IRES), sts); | |
431 | ||
1f5b3c3f | 432 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
433 | } |
434 | ||
435 | ||
736baef4 | 436 | static int intel_setup_intr_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
437 | { |
438 | struct ir_table *ir_table; | |
439 | struct page *pages; | |
440 | ||
441 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 442 | GFP_ATOMIC); |
2ae21010 SS |
443 | |
444 | if (!iommu->ir_table) | |
445 | return -ENOMEM; | |
446 | ||
824cd75b SS |
447 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
448 | INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
449 | |
450 | if (!pages) { | |
451 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
452 | INTR_REMAP_PAGE_ORDER); | |
453 | kfree(iommu->ir_table); | |
454 | return -ENOMEM; | |
455 | } | |
456 | ||
457 | ir_table->base = page_address(pages); | |
458 | ||
459 | iommu_set_intr_remapping(iommu, mode); | |
460 | return 0; | |
461 | } | |
462 | ||
eba67e5d SS |
463 | /* |
464 | * Disable Interrupt Remapping. | |
465 | */ | |
b24696bc | 466 | static void iommu_disable_intr_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
467 | { |
468 | unsigned long flags; | |
469 | u32 sts; | |
470 | ||
471 | if (!ecap_ir_support(iommu->ecap)) | |
472 | return; | |
473 | ||
b24696bc FY |
474 | /* |
475 | * global invalidation of interrupt entry cache before disabling | |
476 | * interrupt-remapping. | |
477 | */ | |
478 | qi_global_iec(iommu); | |
479 | ||
1f5b3c3f | 480 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
481 | |
482 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
483 | if (!(sts & DMA_GSTS_IRES)) | |
484 | goto end; | |
485 | ||
486 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
487 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
488 | ||
489 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
490 | readl, !(sts & DMA_GSTS_IRES), sts); | |
491 | ||
492 | end: | |
1f5b3c3f | 493 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
494 | } |
495 | ||
41750d31 SS |
496 | static int __init dmar_x2apic_optout(void) |
497 | { | |
498 | struct acpi_table_dmar *dmar; | |
499 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
500 | if (!dmar || no_x2apic_optout) | |
501 | return 0; | |
502 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
503 | } | |
504 | ||
736baef4 | 505 | static int __init intel_intr_remapping_supported(void) |
93758238 WH |
506 | { |
507 | struct dmar_drhd_unit *drhd; | |
508 | ||
03ea8155 WH |
509 | if (disable_intremap) |
510 | return 0; | |
511 | ||
074835f0 YS |
512 | if (!dmar_ir_support()) |
513 | return 0; | |
514 | ||
93758238 WH |
515 | for_each_drhd_unit(drhd) { |
516 | struct intel_iommu *iommu = drhd->iommu; | |
517 | ||
518 | if (!ecap_ir_support(iommu->ecap)) | |
519 | return 0; | |
520 | } | |
521 | ||
522 | return 1; | |
523 | } | |
524 | ||
736baef4 | 525 | static int __init intel_enable_intr_remapping(void) |
2ae21010 SS |
526 | { |
527 | struct dmar_drhd_unit *drhd; | |
528 | int setup = 0; | |
41750d31 | 529 | int eim = 0; |
2ae21010 | 530 | |
e936d077 YS |
531 | if (parse_ioapics_under_ir() != 1) { |
532 | printk(KERN_INFO "Not enable interrupt remapping\n"); | |
533 | return -1; | |
534 | } | |
535 | ||
41750d31 SS |
536 | if (x2apic_supported()) { |
537 | eim = !dmar_x2apic_optout(); | |
538 | WARN(!eim, KERN_WARNING | |
539 | "Your BIOS is broken and requested that x2apic be disabled\n" | |
540 | "This will leave your machine vulnerable to irq-injection attacks\n" | |
541 | "Use 'intremap=no_x2apic_optout' to override BIOS request\n"); | |
542 | } | |
543 | ||
1531a6a6 SS |
544 | for_each_drhd_unit(drhd) { |
545 | struct intel_iommu *iommu = drhd->iommu; | |
546 | ||
34aaaa94 HW |
547 | /* |
548 | * If the queued invalidation is already initialized, | |
549 | * shouldn't disable it. | |
550 | */ | |
551 | if (iommu->qi) | |
552 | continue; | |
553 | ||
1531a6a6 SS |
554 | /* |
555 | * Clear previous faults. | |
556 | */ | |
557 | dmar_fault(-1, iommu); | |
558 | ||
559 | /* | |
560 | * Disable intr remapping and queued invalidation, if already | |
561 | * enabled prior to OS handover. | |
562 | */ | |
b24696bc | 563 | iommu_disable_intr_remapping(iommu); |
1531a6a6 SS |
564 | |
565 | dmar_disable_qi(iommu); | |
566 | } | |
567 | ||
2ae21010 SS |
568 | /* |
569 | * check for the Interrupt-remapping support | |
570 | */ | |
571 | for_each_drhd_unit(drhd) { | |
572 | struct intel_iommu *iommu = drhd->iommu; | |
573 | ||
574 | if (!ecap_ir_support(iommu->ecap)) | |
575 | continue; | |
576 | ||
577 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
578 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
579 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
580 | return -1; | |
581 | } | |
582 | } | |
583 | ||
584 | /* | |
585 | * Enable queued invalidation for all the DRHD's. | |
586 | */ | |
587 | for_each_drhd_unit(drhd) { | |
588 | int ret; | |
589 | struct intel_iommu *iommu = drhd->iommu; | |
590 | ret = dmar_enable_qi(iommu); | |
591 | ||
592 | if (ret) { | |
593 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
594 | " invalidation, ecap %Lx, ret %d\n", | |
595 | drhd->reg_base_addr, iommu->ecap, ret); | |
596 | return -1; | |
597 | } | |
598 | } | |
599 | ||
600 | /* | |
601 | * Setup Interrupt-remapping for all the DRHD's now. | |
602 | */ | |
603 | for_each_drhd_unit(drhd) { | |
604 | struct intel_iommu *iommu = drhd->iommu; | |
605 | ||
606 | if (!ecap_ir_support(iommu->ecap)) | |
607 | continue; | |
608 | ||
736baef4 | 609 | if (intel_setup_intr_remapping(iommu, eim)) |
2ae21010 SS |
610 | goto error; |
611 | ||
612 | setup = 1; | |
613 | } | |
614 | ||
615 | if (!setup) | |
616 | goto error; | |
617 | ||
618 | intr_remapping_enabled = 1; | |
41750d31 | 619 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 620 | |
41750d31 | 621 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
622 | |
623 | error: | |
624 | /* | |
625 | * handle error condition gracefully here! | |
626 | */ | |
627 | return -1; | |
628 | } | |
ad3ad3f6 | 629 | |
20f3097b SS |
630 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
631 | struct intel_iommu *iommu) | |
632 | { | |
633 | struct acpi_dmar_pci_path *path; | |
634 | u8 bus; | |
635 | int count; | |
636 | ||
637 | bus = scope->bus; | |
638 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
639 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
640 | / sizeof(struct acpi_dmar_pci_path); | |
641 | ||
642 | while (--count > 0) { | |
643 | /* | |
644 | * Access PCI directly due to the PCI | |
645 | * subsystem isn't initialized yet. | |
646 | */ | |
647 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
648 | PCI_SECONDARY_BUS); | |
649 | path++; | |
650 | } | |
651 | ir_hpet[ir_hpet_num].bus = bus; | |
652 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
653 | ir_hpet[ir_hpet_num].iommu = iommu; | |
654 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; | |
655 | ir_hpet_num++; | |
656 | } | |
657 | ||
f007e99c WH |
658 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
659 | struct intel_iommu *iommu) | |
660 | { | |
661 | struct acpi_dmar_pci_path *path; | |
662 | u8 bus; | |
663 | int count; | |
664 | ||
665 | bus = scope->bus; | |
666 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
667 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
668 | / sizeof(struct acpi_dmar_pci_path); | |
669 | ||
670 | while (--count > 0) { | |
671 | /* | |
672 | * Access PCI directly due to the PCI | |
673 | * subsystem isn't initialized yet. | |
674 | */ | |
675 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
676 | PCI_SECONDARY_BUS); | |
677 | path++; | |
678 | } | |
679 | ||
680 | ir_ioapic[ir_ioapic_num].bus = bus; | |
681 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
682 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
683 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
684 | ir_ioapic_num++; | |
685 | } | |
686 | ||
20f3097b SS |
687 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
688 | struct intel_iommu *iommu) | |
ad3ad3f6 SS |
689 | { |
690 | struct acpi_dmar_hardware_unit *drhd; | |
691 | struct acpi_dmar_device_scope *scope; | |
692 | void *start, *end; | |
693 | ||
694 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
695 | ||
696 | start = (void *)(drhd + 1); | |
697 | end = ((void *)drhd) + header->length; | |
698 | ||
699 | while (start < end) { | |
700 | scope = start; | |
701 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
702 | if (ir_ioapic_num == MAX_IO_APICS) { | |
703 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
704 | return -1; | |
705 | } | |
706 | ||
680a7524 YL |
707 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
708 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, | |
709 | drhd->address, iommu->seq_id); | |
ad3ad3f6 | 710 | |
f007e99c | 711 | ir_parse_one_ioapic_scope(scope, iommu); |
20f3097b SS |
712 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
713 | if (ir_hpet_num == MAX_HPET_TBS) { | |
714 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); | |
715 | return -1; | |
716 | } | |
717 | ||
718 | printk(KERN_INFO "HPET id %d under DRHD base" | |
719 | " 0x%Lx\n", scope->enumeration_id, | |
720 | drhd->address); | |
721 | ||
722 | ir_parse_one_hpet_scope(scope, iommu); | |
ad3ad3f6 SS |
723 | } |
724 | start += scope->length; | |
725 | } | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
730 | /* | |
731 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
732 | * hardware unit. | |
733 | */ | |
734 | int __init parse_ioapics_under_ir(void) | |
735 | { | |
736 | struct dmar_drhd_unit *drhd; | |
737 | int ir_supported = 0; | |
738 | ||
739 | for_each_drhd_unit(drhd) { | |
740 | struct intel_iommu *iommu = drhd->iommu; | |
741 | ||
742 | if (ecap_ir_support(iommu->ecap)) { | |
20f3097b | 743 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
744 | return -1; |
745 | ||
746 | ir_supported = 1; | |
747 | } | |
748 | } | |
749 | ||
750 | if (ir_supported && ir_ioapic_num != nr_ioapics) { | |
751 | printk(KERN_WARNING | |
752 | "Not all IO-APIC's listed under remapping hardware\n"); | |
753 | return -1; | |
754 | } | |
755 | ||
756 | return ir_supported; | |
757 | } | |
b24696bc | 758 | |
61ed26e3 | 759 | int __init ir_dev_scope_init(void) |
c2c7286a SS |
760 | { |
761 | if (!intr_remapping_enabled) | |
762 | return 0; | |
763 | ||
764 | return dmar_dev_scope_init(); | |
765 | } | |
766 | rootfs_initcall(ir_dev_scope_init); | |
767 | ||
4f3d8b67 | 768 | static void disable_intr_remapping(void) |
b24696bc FY |
769 | { |
770 | struct dmar_drhd_unit *drhd; | |
771 | struct intel_iommu *iommu = NULL; | |
772 | ||
773 | /* | |
774 | * Disable Interrupt-remapping for all the DRHD's now. | |
775 | */ | |
776 | for_each_iommu(iommu, drhd) { | |
777 | if (!ecap_ir_support(iommu->ecap)) | |
778 | continue; | |
779 | ||
780 | iommu_disable_intr_remapping(iommu); | |
781 | } | |
782 | } | |
783 | ||
4f3d8b67 | 784 | static int reenable_intr_remapping(int eim) |
b24696bc FY |
785 | { |
786 | struct dmar_drhd_unit *drhd; | |
787 | int setup = 0; | |
788 | struct intel_iommu *iommu = NULL; | |
789 | ||
790 | for_each_iommu(iommu, drhd) | |
791 | if (iommu->qi) | |
792 | dmar_reenable_qi(iommu); | |
793 | ||
794 | /* | |
795 | * Setup Interrupt-remapping for all the DRHD's now. | |
796 | */ | |
797 | for_each_iommu(iommu, drhd) { | |
798 | if (!ecap_ir_support(iommu->ecap)) | |
799 | continue; | |
800 | ||
801 | /* Set up interrupt remapping for iommu.*/ | |
802 | iommu_set_intr_remapping(iommu, eim); | |
803 | setup = 1; | |
804 | } | |
805 | ||
806 | if (!setup) | |
807 | goto error; | |
808 | ||
809 | return 0; | |
810 | ||
811 | error: | |
812 | /* | |
813 | * handle error condition gracefully here! | |
814 | */ | |
815 | return -1; | |
816 | } | |
817 | ||
0c3f173a JR |
818 | static void prepare_irte(struct irte *irte, int vector, |
819 | unsigned int dest) | |
820 | { | |
821 | memset(irte, 0, sizeof(*irte)); | |
822 | ||
823 | irte->present = 1; | |
824 | irte->dst_mode = apic->irq_dest_mode; | |
825 | /* | |
826 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
827 | * actual level or edge trigger will be setup in the IO-APIC | |
828 | * RTE. This will help simplify level triggered irq migration. | |
829 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
830 | * irq migration in the presence of interrupt-remapping. | |
831 | */ | |
832 | irte->trigger_mode = 0; | |
833 | irte->dlvry_mode = apic->irq_delivery_mode; | |
834 | irte->vector = vector; | |
835 | irte->dest_id = IRTE_DEST(dest); | |
836 | irte->redir_hint = 1; | |
837 | } | |
838 | ||
839 | static int intel_setup_ioapic_entry(int irq, | |
840 | struct IO_APIC_route_entry *route_entry, | |
841 | unsigned int destination, int vector, | |
842 | struct io_apic_irq_attr *attr) | |
843 | { | |
844 | int ioapic_id = mpc_ioapic_id(attr->ioapic); | |
845 | struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id); | |
846 | struct IR_IO_APIC_route_entry *entry; | |
847 | struct irte irte; | |
848 | int index; | |
849 | ||
850 | if (!iommu) { | |
851 | pr_warn("No mapping iommu for ioapic %d\n", ioapic_id); | |
852 | return -ENODEV; | |
853 | } | |
854 | ||
855 | entry = (struct IR_IO_APIC_route_entry *)route_entry; | |
856 | ||
857 | index = alloc_irte(iommu, irq, 1); | |
858 | if (index < 0) { | |
859 | pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id); | |
860 | return -ENOMEM; | |
861 | } | |
862 | ||
863 | prepare_irte(&irte, vector, destination); | |
864 | ||
865 | /* Set source-id of interrupt request */ | |
866 | set_ioapic_sid(&irte, ioapic_id); | |
867 | ||
868 | modify_irte(irq, &irte); | |
869 | ||
870 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " | |
871 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
872 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
873 | "Avail:%X Vector:%02X Dest:%08X " | |
874 | "SID:%04X SQ:%X SVT:%X)\n", | |
875 | attr->ioapic, irte.present, irte.fpd, irte.dst_mode, | |
876 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, | |
877 | irte.avail, irte.vector, irte.dest_id, | |
878 | irte.sid, irte.sq, irte.svt); | |
879 | ||
880 | memset(entry, 0, sizeof(*entry)); | |
881 | ||
882 | entry->index2 = (index >> 15) & 0x1; | |
883 | entry->zero = 0; | |
884 | entry->format = 1; | |
885 | entry->index = (index & 0x7fff); | |
886 | /* | |
887 | * IO-APIC RTE will be configured with virtual vector. | |
888 | * irq handler will do the explicit EOI to the io-apic. | |
889 | */ | |
890 | entry->vector = attr->ioapic_pin; | |
891 | entry->mask = 0; /* enable IRQ */ | |
892 | entry->trigger = attr->trigger; | |
893 | entry->polarity = attr->polarity; | |
894 | ||
895 | /* Mask level triggered irqs. | |
896 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
897 | */ | |
898 | if (attr->trigger) | |
899 | entry->mask = 1; | |
900 | ||
901 | return 0; | |
902 | } | |
903 | ||
4c1bad6a JR |
904 | /* |
905 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
906 | * | |
907 | * For both level and edge triggered, irq migration is a simple atomic | |
908 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
909 | * | |
910 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
911 | * updated vector information), by using a virtual vector (io-apic pin number). | |
912 | * Real vector that is used for interrupting cpu will be coming from | |
913 | * the interrupt-remapping table entry. | |
914 | * | |
915 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
916 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
917 | */ | |
918 | static int | |
919 | intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
920 | bool force) | |
921 | { | |
922 | struct irq_cfg *cfg = data->chip_data; | |
923 | unsigned int dest, irq = data->irq; | |
924 | struct irte irte; | |
925 | ||
926 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
927 | return -EINVAL; | |
928 | ||
929 | if (get_irte(irq, &irte)) | |
930 | return -EBUSY; | |
931 | ||
932 | if (assign_irq_vector(irq, cfg, mask)) | |
933 | return -EBUSY; | |
934 | ||
935 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); | |
936 | ||
937 | irte.vector = cfg->vector; | |
938 | irte.dest_id = IRTE_DEST(dest); | |
939 | ||
940 | /* | |
941 | * Atomically updates the IRTE with the new destination, vector | |
942 | * and flushes the interrupt entry cache. | |
943 | */ | |
944 | modify_irte(irq, &irte); | |
945 | ||
946 | /* | |
947 | * After this point, all the interrupts will start arriving | |
948 | * at the new destination. So, time to cleanup the previous | |
949 | * vector allocation. | |
950 | */ | |
951 | if (cfg->move_in_progress) | |
952 | send_cleanup_vector(cfg); | |
953 | ||
954 | cpumask_copy(data->affinity, mask); | |
955 | return 0; | |
956 | } | |
0c3f173a | 957 | |
736baef4 JR |
958 | struct irq_remap_ops intel_irq_remap_ops = { |
959 | .supported = intel_intr_remapping_supported, | |
960 | .hardware_init = dmar_table_init, | |
961 | .hardware_enable = intel_enable_intr_remapping, | |
4f3d8b67 JR |
962 | .hardware_disable = disable_intr_remapping, |
963 | .hardware_reenable = reenable_intr_remapping, | |
964 | .enable_faulting = enable_drhd_fault_handling, | |
0c3f173a | 965 | .setup_ioapic_entry = intel_setup_ioapic_entry, |
4c1bad6a | 966 | .set_affinity = intel_ioapic_set_affinity, |
9d619f65 | 967 | .free_irq = free_irte, |
736baef4 | 968 | }; |