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Commit | Line | Data |
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5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
ad3ad3f6 | 9 | #include <asm/io_apic.h> |
17483a1f | 10 | #include <asm/smp.h> |
6d652ea1 | 11 | #include <asm/cpu.h> |
38717946 | 12 | #include <linux/intel-iommu.h> |
46f06b72 | 13 | #include <acpi/acpi.h> |
8a8f422d | 14 | #include <asm/irq_remapping.h> |
f007e99c | 15 | #include <asm/pci-direct.h> |
5e2b930b | 16 | #include <asm/msidef.h> |
ad3ad3f6 | 17 | |
8a8f422d | 18 | #include "irq_remapping.h" |
736baef4 | 19 | |
eef93fdb JR |
20 | struct ioapic_scope { |
21 | struct intel_iommu *iommu; | |
22 | unsigned int id; | |
23 | unsigned int bus; /* PCI bus number */ | |
24 | unsigned int devfn; /* PCI devfn number */ | |
25 | }; | |
26 | ||
27 | struct hpet_scope { | |
28 | struct intel_iommu *iommu; | |
29 | u8 id; | |
30 | unsigned int bus; | |
31 | unsigned int devfn; | |
32 | }; | |
33 | ||
34 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) | |
0c3f173a | 35 | #define IRTE_DEST(dest) ((x2apic_mode) ? dest : dest << 8) |
eef93fdb | 36 | |
ad3ad3f6 | 37 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b SS |
38 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
39 | static int ir_ioapic_num, ir_hpet_num; | |
d1423d56 | 40 | |
96f8e98b | 41 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
d585d060 | 42 | |
e420dfb4 YL |
43 | static struct irq_2_iommu *irq_2_iommu(unsigned int irq) |
44 | { | |
dced35ae | 45 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
349d6767 | 46 | return cfg ? &cfg->irq_2_iommu : NULL; |
0b8f1efa YL |
47 | } |
48 | ||
b6fcb33a SS |
49 | int get_irte(int irq, struct irte *entry) |
50 | { | |
d585d060 | 51 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 52 | unsigned long flags; |
d585d060 | 53 | int index; |
b6fcb33a | 54 | |
d585d060 | 55 | if (!entry || !irq_iommu) |
b6fcb33a SS |
56 | return -1; |
57 | ||
96f8e98b | 58 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 59 | |
e420dfb4 YL |
60 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
61 | *entry = *(irq_iommu->iommu->ir_table->base + index); | |
b6fcb33a | 62 | |
96f8e98b | 63 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
64 | return 0; |
65 | } | |
66 | ||
263b5e86 | 67 | static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count) |
b6fcb33a SS |
68 | { |
69 | struct ir_table *table = iommu->ir_table; | |
d585d060 | 70 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
9b1b0e42 | 71 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
b6fcb33a SS |
72 | u16 index, start_index; |
73 | unsigned int mask = 0; | |
4c5502b1 | 74 | unsigned long flags; |
b6fcb33a SS |
75 | int i; |
76 | ||
d585d060 | 77 | if (!count || !irq_iommu) |
e420dfb4 | 78 | return -1; |
e420dfb4 | 79 | |
b6fcb33a SS |
80 | /* |
81 | * start the IRTE search from index 0. | |
82 | */ | |
83 | index = start_index = 0; | |
84 | ||
85 | if (count > 1) { | |
86 | count = __roundup_pow_of_two(count); | |
87 | mask = ilog2(count); | |
88 | } | |
89 | ||
90 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
91 | printk(KERN_ERR | |
92 | "Requested mask %x exceeds the max invalidation handle" | |
93 | " mask value %Lx\n", mask, | |
94 | ecap_max_handle_mask(iommu->ecap)); | |
95 | return -1; | |
96 | } | |
97 | ||
96f8e98b | 98 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a SS |
99 | do { |
100 | for (i = index; i < index + count; i++) | |
101 | if (table->base[i].present) | |
102 | break; | |
103 | /* empty index found */ | |
104 | if (i == index + count) | |
105 | break; | |
106 | ||
107 | index = (index + count) % INTR_REMAP_TABLE_ENTRIES; | |
108 | ||
109 | if (index == start_index) { | |
96f8e98b | 110 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
111 | printk(KERN_ERR "can't allocate an IRTE\n"); |
112 | return -1; | |
113 | } | |
114 | } while (1); | |
115 | ||
116 | for (i = index; i < index + count; i++) | |
117 | table->base[i].present = 1; | |
118 | ||
9b1b0e42 | 119 | cfg->remapped = 1; |
e420dfb4 YL |
120 | irq_iommu->iommu = iommu; |
121 | irq_iommu->irte_index = index; | |
122 | irq_iommu->sub_handle = 0; | |
123 | irq_iommu->irte_mask = mask; | |
b6fcb33a | 124 | |
96f8e98b | 125 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
126 | |
127 | return index; | |
128 | } | |
129 | ||
704126ad | 130 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
131 | { |
132 | struct qi_desc desc; | |
133 | ||
134 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
135 | | QI_IEC_SELECTIVE; | |
136 | desc.high = 0; | |
137 | ||
704126ad | 138 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
139 | } |
140 | ||
263b5e86 | 141 | static int map_irq_to_irte_handle(int irq, u16 *sub_handle) |
b6fcb33a | 142 | { |
d585d060 | 143 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 144 | unsigned long flags; |
d585d060 | 145 | int index; |
b6fcb33a | 146 | |
d585d060 | 147 | if (!irq_iommu) |
b6fcb33a | 148 | return -1; |
b6fcb33a | 149 | |
96f8e98b | 150 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
e420dfb4 YL |
151 | *sub_handle = irq_iommu->sub_handle; |
152 | index = irq_iommu->irte_index; | |
96f8e98b | 153 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
154 | return index; |
155 | } | |
156 | ||
263b5e86 | 157 | static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle) |
b6fcb33a | 158 | { |
d585d060 | 159 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
9b1b0e42 | 160 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
4c5502b1 | 161 | unsigned long flags; |
e420dfb4 | 162 | |
d585d060 | 163 | if (!irq_iommu) |
0b8f1efa | 164 | return -1; |
d585d060 | 165 | |
96f8e98b | 166 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
0b8f1efa | 167 | |
9b1b0e42 | 168 | cfg->remapped = 1; |
e420dfb4 YL |
169 | irq_iommu->iommu = iommu; |
170 | irq_iommu->irte_index = index; | |
171 | irq_iommu->sub_handle = subhandle; | |
172 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 173 | |
96f8e98b | 174 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
175 | |
176 | return 0; | |
177 | } | |
178 | ||
263b5e86 | 179 | static int modify_irte(int irq, struct irte *irte_modified) |
b6fcb33a | 180 | { |
d585d060 | 181 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
b6fcb33a | 182 | struct intel_iommu *iommu; |
4c5502b1 | 183 | unsigned long flags; |
d585d060 TG |
184 | struct irte *irte; |
185 | int rc, index; | |
b6fcb33a | 186 | |
d585d060 | 187 | if (!irq_iommu) |
b6fcb33a | 188 | return -1; |
d585d060 | 189 | |
96f8e98b | 190 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 191 | |
e420dfb4 | 192 | iommu = irq_iommu->iommu; |
b6fcb33a | 193 | |
e420dfb4 | 194 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
195 | irte = &iommu->ir_table->base[index]; |
196 | ||
c513b67e LT |
197 | set_64bit(&irte->low, irte_modified->low); |
198 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
199 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
200 | ||
704126ad | 201 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 202 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
203 | |
204 | return rc; | |
b6fcb33a SS |
205 | } |
206 | ||
263b5e86 | 207 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
208 | { |
209 | int i; | |
210 | ||
211 | for (i = 0; i < MAX_HPET_TBS; i++) | |
212 | if (ir_hpet[i].id == hpet_id) | |
213 | return ir_hpet[i].iommu; | |
214 | return NULL; | |
215 | } | |
216 | ||
263b5e86 | 217 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
218 | { |
219 | int i; | |
220 | ||
221 | for (i = 0; i < MAX_IO_APICS; i++) | |
222 | if (ir_ioapic[i].id == apic) | |
223 | return ir_ioapic[i].iommu; | |
224 | return NULL; | |
225 | } | |
226 | ||
263b5e86 | 227 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
228 | { |
229 | struct dmar_drhd_unit *drhd; | |
230 | ||
231 | drhd = dmar_find_matched_drhd_unit(dev); | |
232 | if (!drhd) | |
233 | return NULL; | |
234 | ||
235 | return drhd->iommu; | |
236 | } | |
237 | ||
c4658b4e WH |
238 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
239 | { | |
240 | struct irte *start, *entry, *end; | |
241 | struct intel_iommu *iommu; | |
242 | int index; | |
243 | ||
244 | if (irq_iommu->sub_handle) | |
245 | return 0; | |
246 | ||
247 | iommu = irq_iommu->iommu; | |
248 | index = irq_iommu->irte_index + irq_iommu->sub_handle; | |
249 | ||
250 | start = iommu->ir_table->base + index; | |
251 | end = start + (1 << irq_iommu->irte_mask); | |
252 | ||
253 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
254 | set_64bit(&entry->low, 0); |
255 | set_64bit(&entry->high, 0); | |
c4658b4e WH |
256 | } |
257 | ||
258 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
259 | } | |
260 | ||
9d619f65 | 261 | static int free_irte(int irq) |
b6fcb33a | 262 | { |
d585d060 | 263 | struct irq_2_iommu *irq_iommu = irq_2_iommu(irq); |
4c5502b1 | 264 | unsigned long flags; |
d585d060 | 265 | int rc; |
b6fcb33a | 266 | |
d585d060 | 267 | if (!irq_iommu) |
b6fcb33a | 268 | return -1; |
d585d060 | 269 | |
96f8e98b | 270 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 271 | |
c4658b4e | 272 | rc = clear_entries(irq_iommu); |
b6fcb33a | 273 | |
e420dfb4 YL |
274 | irq_iommu->iommu = NULL; |
275 | irq_iommu->irte_index = 0; | |
276 | irq_iommu->sub_handle = 0; | |
277 | irq_iommu->irte_mask = 0; | |
b6fcb33a | 278 | |
96f8e98b | 279 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a | 280 | |
704126ad | 281 | return rc; |
b6fcb33a SS |
282 | } |
283 | ||
f007e99c WH |
284 | /* |
285 | * source validation type | |
286 | */ | |
287 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 288 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
289 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
290 | ||
291 | /* | |
292 | * source-id qualifier | |
293 | */ | |
294 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
295 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
296 | * the third least significant bit | |
297 | */ | |
298 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
299 | * the second and third least significant bits | |
300 | */ | |
301 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
302 | * the least three significant bits | |
303 | */ | |
304 | ||
305 | /* | |
306 | * set SVT, SQ and SID fields of irte to verify | |
307 | * source ids of interrupt requests | |
308 | */ | |
309 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
310 | unsigned int sq, unsigned int sid) | |
311 | { | |
d1423d56 CW |
312 | if (disable_sourceid_checking) |
313 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
314 | irte->svt = svt; |
315 | irte->sq = sq; | |
316 | irte->sid = sid; | |
317 | } | |
318 | ||
263b5e86 | 319 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
320 | { |
321 | int i; | |
322 | u16 sid = 0; | |
323 | ||
324 | if (!irte) | |
325 | return -1; | |
326 | ||
327 | for (i = 0; i < MAX_IO_APICS; i++) { | |
328 | if (ir_ioapic[i].id == apic) { | |
329 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; | |
330 | break; | |
331 | } | |
332 | } | |
333 | ||
334 | if (sid == 0) { | |
335 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
336 | return -1; | |
337 | } | |
338 | ||
339 | set_irte_sid(irte, 1, 0, sid); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
263b5e86 | 344 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
345 | { |
346 | int i; | |
347 | u16 sid = 0; | |
348 | ||
349 | if (!irte) | |
350 | return -1; | |
351 | ||
352 | for (i = 0; i < MAX_HPET_TBS; i++) { | |
353 | if (ir_hpet[i].id == id) { | |
354 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; | |
355 | break; | |
356 | } | |
357 | } | |
358 | ||
359 | if (sid == 0) { | |
360 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
361 | return -1; | |
362 | } | |
363 | ||
364 | /* | |
365 | * Should really use SQ_ALL_16. Some platforms are broken. | |
366 | * While we figure out the right quirks for these broken platforms, use | |
367 | * SQ_13_IGNORE_3 for now. | |
368 | */ | |
369 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
263b5e86 | 374 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c WH |
375 | { |
376 | struct pci_dev *bridge; | |
377 | ||
378 | if (!irte || !dev) | |
379 | return -1; | |
380 | ||
381 | /* PCIe device or Root Complex integrated PCI device */ | |
5f4d91a1 | 382 | if (pci_is_pcie(dev) || !dev->bus->parent) { |
f007e99c WH |
383 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, |
384 | (dev->bus->number << 8) | dev->devfn); | |
385 | return 0; | |
386 | } | |
387 | ||
388 | bridge = pci_find_upstream_pcie_bridge(dev); | |
389 | if (bridge) { | |
45e829ea | 390 | if (pci_is_pcie(bridge))/* this is a PCIe-to-PCI/PCIX bridge */ |
f007e99c WH |
391 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, |
392 | (bridge->bus->number << 8) | dev->bus->number); | |
393 | else /* this is a legacy PCI bridge */ | |
394 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
395 | (bridge->bus->number << 8) | bridge->devfn); | |
396 | } | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
95a02e97 | 401 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
402 | { |
403 | u64 addr; | |
c416daa9 | 404 | u32 sts; |
2ae21010 SS |
405 | unsigned long flags; |
406 | ||
407 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
408 | ||
1f5b3c3f | 409 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
410 | |
411 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
412 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
413 | ||
414 | /* Set interrupt-remapping table pointer */ | |
161fde08 | 415 | iommu->gcmd |= DMA_GCMD_SIRTP; |
c416daa9 | 416 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
417 | |
418 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
419 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 420 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
421 | |
422 | /* | |
423 | * global invalidation of interrupt entry cache before enabling | |
424 | * interrupt-remapping. | |
425 | */ | |
426 | qi_global_iec(iommu); | |
427 | ||
1f5b3c3f | 428 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
429 | |
430 | /* Enable interrupt-remapping */ | |
2ae21010 | 431 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 432 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 433 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
434 | |
435 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
436 | readl, (sts & DMA_GSTS_IRES), sts); | |
437 | ||
af8d102f AL |
438 | /* |
439 | * With CFI clear in the Global Command register, we should be | |
440 | * protected from dangerous (i.e. compatibility) interrupts | |
441 | * regardless of x2apic status. Check just to be sure. | |
442 | */ | |
443 | if (sts & DMA_GSTS_CFIS) | |
444 | WARN(1, KERN_WARNING | |
445 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
446 | "you are vulnerable to IRQ injection.\n"); | |
447 | ||
1f5b3c3f | 448 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
449 | } |
450 | ||
451 | ||
95a02e97 | 452 | static int intel_setup_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
453 | { |
454 | struct ir_table *ir_table; | |
455 | struct page *pages; | |
456 | ||
457 | ir_table = iommu->ir_table = kzalloc(sizeof(struct ir_table), | |
fa4b57cc | 458 | GFP_ATOMIC); |
2ae21010 SS |
459 | |
460 | if (!iommu->ir_table) | |
461 | return -ENOMEM; | |
462 | ||
824cd75b SS |
463 | pages = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, |
464 | INTR_REMAP_PAGE_ORDER); | |
2ae21010 SS |
465 | |
466 | if (!pages) { | |
467 | printk(KERN_ERR "failed to allocate pages of order %d\n", | |
468 | INTR_REMAP_PAGE_ORDER); | |
469 | kfree(iommu->ir_table); | |
470 | return -ENOMEM; | |
471 | } | |
472 | ||
473 | ir_table->base = page_address(pages); | |
474 | ||
95a02e97 | 475 | iommu_set_irq_remapping(iommu, mode); |
2ae21010 SS |
476 | return 0; |
477 | } | |
478 | ||
eba67e5d SS |
479 | /* |
480 | * Disable Interrupt Remapping. | |
481 | */ | |
95a02e97 | 482 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
483 | { |
484 | unsigned long flags; | |
485 | u32 sts; | |
486 | ||
487 | if (!ecap_ir_support(iommu->ecap)) | |
488 | return; | |
489 | ||
b24696bc FY |
490 | /* |
491 | * global invalidation of interrupt entry cache before disabling | |
492 | * interrupt-remapping. | |
493 | */ | |
494 | qi_global_iec(iommu); | |
495 | ||
1f5b3c3f | 496 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
497 | |
498 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
499 | if (!(sts & DMA_GSTS_IRES)) | |
500 | goto end; | |
501 | ||
502 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
503 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
504 | ||
505 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
506 | readl, !(sts & DMA_GSTS_IRES), sts); | |
507 | ||
508 | end: | |
1f5b3c3f | 509 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
510 | } |
511 | ||
41750d31 SS |
512 | static int __init dmar_x2apic_optout(void) |
513 | { | |
514 | struct acpi_table_dmar *dmar; | |
515 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
516 | if (!dmar || no_x2apic_optout) | |
517 | return 0; | |
518 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
519 | } | |
520 | ||
95a02e97 | 521 | static int __init intel_irq_remapping_supported(void) |
93758238 WH |
522 | { |
523 | struct dmar_drhd_unit *drhd; | |
524 | ||
95a02e97 | 525 | if (disable_irq_remap) |
03ea8155 | 526 | return 0; |
03bbcb2e NH |
527 | if (irq_remap_broken) { |
528 | WARN_TAINT(1, TAINT_FIRMWARE_WORKAROUND, | |
529 | "This system BIOS has enabled interrupt remapping\n" | |
530 | "on a chipset that contains an erratum making that\n" | |
531 | "feature unstable. To maintain system stability\n" | |
532 | "interrupt remapping is being disabled. Please\n" | |
533 | "contact your BIOS vendor for an update\n"); | |
534 | disable_irq_remap = 1; | |
535 | return 0; | |
536 | } | |
03ea8155 | 537 | |
074835f0 YS |
538 | if (!dmar_ir_support()) |
539 | return 0; | |
540 | ||
93758238 WH |
541 | for_each_drhd_unit(drhd) { |
542 | struct intel_iommu *iommu = drhd->iommu; | |
543 | ||
544 | if (!ecap_ir_support(iommu->ecap)) | |
545 | return 0; | |
546 | } | |
547 | ||
548 | return 1; | |
549 | } | |
550 | ||
95a02e97 | 551 | static int __init intel_enable_irq_remapping(void) |
2ae21010 SS |
552 | { |
553 | struct dmar_drhd_unit *drhd; | |
af8d102f | 554 | bool x2apic_present; |
2ae21010 | 555 | int setup = 0; |
41750d31 | 556 | int eim = 0; |
2ae21010 | 557 | |
af8d102f AL |
558 | x2apic_present = x2apic_supported(); |
559 | ||
e936d077 YS |
560 | if (parse_ioapics_under_ir() != 1) { |
561 | printk(KERN_INFO "Not enable interrupt remapping\n"); | |
af8d102f | 562 | goto error; |
e936d077 YS |
563 | } |
564 | ||
af8d102f | 565 | if (x2apic_present) { |
41750d31 | 566 | eim = !dmar_x2apic_optout(); |
af8d102f AL |
567 | if (!eim) |
568 | printk(KERN_WARNING | |
569 | "Your BIOS is broken and requested that x2apic be disabled.\n" | |
570 | "This will slightly decrease performance.\n" | |
571 | "Use 'intremap=no_x2apic_optout' to override BIOS request.\n"); | |
41750d31 SS |
572 | } |
573 | ||
1531a6a6 SS |
574 | for_each_drhd_unit(drhd) { |
575 | struct intel_iommu *iommu = drhd->iommu; | |
576 | ||
34aaaa94 HW |
577 | /* |
578 | * If the queued invalidation is already initialized, | |
579 | * shouldn't disable it. | |
580 | */ | |
581 | if (iommu->qi) | |
582 | continue; | |
583 | ||
1531a6a6 SS |
584 | /* |
585 | * Clear previous faults. | |
586 | */ | |
587 | dmar_fault(-1, iommu); | |
588 | ||
589 | /* | |
590 | * Disable intr remapping and queued invalidation, if already | |
591 | * enabled prior to OS handover. | |
592 | */ | |
95a02e97 | 593 | iommu_disable_irq_remapping(iommu); |
1531a6a6 SS |
594 | |
595 | dmar_disable_qi(iommu); | |
596 | } | |
597 | ||
2ae21010 SS |
598 | /* |
599 | * check for the Interrupt-remapping support | |
600 | */ | |
601 | for_each_drhd_unit(drhd) { | |
602 | struct intel_iommu *iommu = drhd->iommu; | |
603 | ||
604 | if (!ecap_ir_support(iommu->ecap)) | |
605 | continue; | |
606 | ||
607 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
608 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
609 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
af8d102f | 610 | goto error; |
2ae21010 SS |
611 | } |
612 | } | |
613 | ||
614 | /* | |
615 | * Enable queued invalidation for all the DRHD's. | |
616 | */ | |
617 | for_each_drhd_unit(drhd) { | |
618 | int ret; | |
619 | struct intel_iommu *iommu = drhd->iommu; | |
620 | ret = dmar_enable_qi(iommu); | |
621 | ||
622 | if (ret) { | |
623 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
624 | " invalidation, ecap %Lx, ret %d\n", | |
625 | drhd->reg_base_addr, iommu->ecap, ret); | |
af8d102f | 626 | goto error; |
2ae21010 SS |
627 | } |
628 | } | |
629 | ||
630 | /* | |
631 | * Setup Interrupt-remapping for all the DRHD's now. | |
632 | */ | |
633 | for_each_drhd_unit(drhd) { | |
634 | struct intel_iommu *iommu = drhd->iommu; | |
635 | ||
636 | if (!ecap_ir_support(iommu->ecap)) | |
637 | continue; | |
638 | ||
95a02e97 | 639 | if (intel_setup_irq_remapping(iommu, eim)) |
2ae21010 SS |
640 | goto error; |
641 | ||
642 | setup = 1; | |
643 | } | |
644 | ||
645 | if (!setup) | |
646 | goto error; | |
647 | ||
95a02e97 | 648 | irq_remapping_enabled = 1; |
afcc8a40 JR |
649 | |
650 | /* | |
651 | * VT-d has a different layout for IO-APIC entries when | |
652 | * interrupt remapping is enabled. So it needs a special routine | |
653 | * to print IO-APIC entries for debugging purposes too. | |
654 | */ | |
655 | x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries; | |
656 | ||
41750d31 | 657 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 658 | |
41750d31 | 659 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
660 | |
661 | error: | |
662 | /* | |
663 | * handle error condition gracefully here! | |
664 | */ | |
af8d102f AL |
665 | |
666 | if (x2apic_present) | |
d01140df | 667 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); |
af8d102f | 668 | |
2ae21010 SS |
669 | return -1; |
670 | } | |
ad3ad3f6 | 671 | |
20f3097b SS |
672 | static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
673 | struct intel_iommu *iommu) | |
674 | { | |
675 | struct acpi_dmar_pci_path *path; | |
676 | u8 bus; | |
677 | int count; | |
678 | ||
679 | bus = scope->bus; | |
680 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
681 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
682 | / sizeof(struct acpi_dmar_pci_path); | |
683 | ||
684 | while (--count > 0) { | |
685 | /* | |
686 | * Access PCI directly due to the PCI | |
687 | * subsystem isn't initialized yet. | |
688 | */ | |
689 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
690 | PCI_SECONDARY_BUS); | |
691 | path++; | |
692 | } | |
693 | ir_hpet[ir_hpet_num].bus = bus; | |
694 | ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
695 | ir_hpet[ir_hpet_num].iommu = iommu; | |
696 | ir_hpet[ir_hpet_num].id = scope->enumeration_id; | |
697 | ir_hpet_num++; | |
698 | } | |
699 | ||
f007e99c WH |
700 | static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
701 | struct intel_iommu *iommu) | |
702 | { | |
703 | struct acpi_dmar_pci_path *path; | |
704 | u8 bus; | |
705 | int count; | |
706 | ||
707 | bus = scope->bus; | |
708 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
709 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
710 | / sizeof(struct acpi_dmar_pci_path); | |
711 | ||
712 | while (--count > 0) { | |
713 | /* | |
714 | * Access PCI directly due to the PCI | |
715 | * subsystem isn't initialized yet. | |
716 | */ | |
717 | bus = read_pci_config_byte(bus, path->dev, path->fn, | |
718 | PCI_SECONDARY_BUS); | |
719 | path++; | |
720 | } | |
721 | ||
722 | ir_ioapic[ir_ioapic_num].bus = bus; | |
723 | ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn); | |
724 | ir_ioapic[ir_ioapic_num].iommu = iommu; | |
725 | ir_ioapic[ir_ioapic_num].id = scope->enumeration_id; | |
726 | ir_ioapic_num++; | |
727 | } | |
728 | ||
20f3097b SS |
729 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
730 | struct intel_iommu *iommu) | |
ad3ad3f6 SS |
731 | { |
732 | struct acpi_dmar_hardware_unit *drhd; | |
733 | struct acpi_dmar_device_scope *scope; | |
734 | void *start, *end; | |
735 | ||
736 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
737 | ||
738 | start = (void *)(drhd + 1); | |
739 | end = ((void *)drhd) + header->length; | |
740 | ||
741 | while (start < end) { | |
742 | scope = start; | |
743 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) { | |
744 | if (ir_ioapic_num == MAX_IO_APICS) { | |
745 | printk(KERN_WARNING "Exceeded Max IO APICS\n"); | |
746 | return -1; | |
747 | } | |
748 | ||
680a7524 YL |
749 | printk(KERN_INFO "IOAPIC id %d under DRHD base " |
750 | " 0x%Lx IOMMU %d\n", scope->enumeration_id, | |
751 | drhd->address, iommu->seq_id); | |
ad3ad3f6 | 752 | |
f007e99c | 753 | ir_parse_one_ioapic_scope(scope, iommu); |
20f3097b SS |
754 | } else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) { |
755 | if (ir_hpet_num == MAX_HPET_TBS) { | |
756 | printk(KERN_WARNING "Exceeded Max HPET blocks\n"); | |
757 | return -1; | |
758 | } | |
759 | ||
760 | printk(KERN_INFO "HPET id %d under DRHD base" | |
761 | " 0x%Lx\n", scope->enumeration_id, | |
762 | drhd->address); | |
763 | ||
764 | ir_parse_one_hpet_scope(scope, iommu); | |
ad3ad3f6 SS |
765 | } |
766 | start += scope->length; | |
767 | } | |
768 | ||
769 | return 0; | |
770 | } | |
771 | ||
772 | /* | |
773 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
774 | * hardware unit. | |
775 | */ | |
776 | int __init parse_ioapics_under_ir(void) | |
777 | { | |
778 | struct dmar_drhd_unit *drhd; | |
779 | int ir_supported = 0; | |
32ab31e0 | 780 | int ioapic_idx; |
ad3ad3f6 SS |
781 | |
782 | for_each_drhd_unit(drhd) { | |
783 | struct intel_iommu *iommu = drhd->iommu; | |
784 | ||
785 | if (ecap_ir_support(iommu->ecap)) { | |
20f3097b | 786 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
787 | return -1; |
788 | ||
789 | ir_supported = 1; | |
790 | } | |
791 | } | |
792 | ||
32ab31e0 SF |
793 | if (!ir_supported) |
794 | return 0; | |
795 | ||
796 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
797 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
798 | if (!map_ioapic_to_ir(ioapic_id)) { | |
799 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
800 | "interrupt remapping will be disabled\n", | |
801 | ioapic_id); | |
802 | return -1; | |
803 | } | |
ad3ad3f6 SS |
804 | } |
805 | ||
32ab31e0 | 806 | return 1; |
ad3ad3f6 | 807 | } |
b24696bc | 808 | |
61ed26e3 | 809 | int __init ir_dev_scope_init(void) |
c2c7286a | 810 | { |
95a02e97 | 811 | if (!irq_remapping_enabled) |
c2c7286a SS |
812 | return 0; |
813 | ||
814 | return dmar_dev_scope_init(); | |
815 | } | |
816 | rootfs_initcall(ir_dev_scope_init); | |
817 | ||
95a02e97 | 818 | static void disable_irq_remapping(void) |
b24696bc FY |
819 | { |
820 | struct dmar_drhd_unit *drhd; | |
821 | struct intel_iommu *iommu = NULL; | |
822 | ||
823 | /* | |
824 | * Disable Interrupt-remapping for all the DRHD's now. | |
825 | */ | |
826 | for_each_iommu(iommu, drhd) { | |
827 | if (!ecap_ir_support(iommu->ecap)) | |
828 | continue; | |
829 | ||
95a02e97 | 830 | iommu_disable_irq_remapping(iommu); |
b24696bc FY |
831 | } |
832 | } | |
833 | ||
95a02e97 | 834 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
835 | { |
836 | struct dmar_drhd_unit *drhd; | |
837 | int setup = 0; | |
838 | struct intel_iommu *iommu = NULL; | |
839 | ||
840 | for_each_iommu(iommu, drhd) | |
841 | if (iommu->qi) | |
842 | dmar_reenable_qi(iommu); | |
843 | ||
844 | /* | |
845 | * Setup Interrupt-remapping for all the DRHD's now. | |
846 | */ | |
847 | for_each_iommu(iommu, drhd) { | |
848 | if (!ecap_ir_support(iommu->ecap)) | |
849 | continue; | |
850 | ||
851 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 852 | iommu_set_irq_remapping(iommu, eim); |
b24696bc FY |
853 | setup = 1; |
854 | } | |
855 | ||
856 | if (!setup) | |
857 | goto error; | |
858 | ||
859 | return 0; | |
860 | ||
861 | error: | |
862 | /* | |
863 | * handle error condition gracefully here! | |
864 | */ | |
865 | return -1; | |
866 | } | |
867 | ||
0c3f173a JR |
868 | static void prepare_irte(struct irte *irte, int vector, |
869 | unsigned int dest) | |
870 | { | |
871 | memset(irte, 0, sizeof(*irte)); | |
872 | ||
873 | irte->present = 1; | |
874 | irte->dst_mode = apic->irq_dest_mode; | |
875 | /* | |
876 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
877 | * actual level or edge trigger will be setup in the IO-APIC | |
878 | * RTE. This will help simplify level triggered irq migration. | |
879 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
880 | * irq migration in the presence of interrupt-remapping. | |
881 | */ | |
882 | irte->trigger_mode = 0; | |
883 | irte->dlvry_mode = apic->irq_delivery_mode; | |
884 | irte->vector = vector; | |
885 | irte->dest_id = IRTE_DEST(dest); | |
886 | irte->redir_hint = 1; | |
887 | } | |
888 | ||
889 | static int intel_setup_ioapic_entry(int irq, | |
890 | struct IO_APIC_route_entry *route_entry, | |
891 | unsigned int destination, int vector, | |
892 | struct io_apic_irq_attr *attr) | |
893 | { | |
894 | int ioapic_id = mpc_ioapic_id(attr->ioapic); | |
895 | struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id); | |
896 | struct IR_IO_APIC_route_entry *entry; | |
897 | struct irte irte; | |
898 | int index; | |
899 | ||
900 | if (!iommu) { | |
901 | pr_warn("No mapping iommu for ioapic %d\n", ioapic_id); | |
902 | return -ENODEV; | |
903 | } | |
904 | ||
905 | entry = (struct IR_IO_APIC_route_entry *)route_entry; | |
906 | ||
907 | index = alloc_irte(iommu, irq, 1); | |
908 | if (index < 0) { | |
909 | pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id); | |
910 | return -ENOMEM; | |
911 | } | |
912 | ||
913 | prepare_irte(&irte, vector, destination); | |
914 | ||
915 | /* Set source-id of interrupt request */ | |
916 | set_ioapic_sid(&irte, ioapic_id); | |
917 | ||
918 | modify_irte(irq, &irte); | |
919 | ||
920 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " | |
921 | "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " | |
922 | "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " | |
923 | "Avail:%X Vector:%02X Dest:%08X " | |
924 | "SID:%04X SQ:%X SVT:%X)\n", | |
925 | attr->ioapic, irte.present, irte.fpd, irte.dst_mode, | |
926 | irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, | |
927 | irte.avail, irte.vector, irte.dest_id, | |
928 | irte.sid, irte.sq, irte.svt); | |
929 | ||
930 | memset(entry, 0, sizeof(*entry)); | |
931 | ||
932 | entry->index2 = (index >> 15) & 0x1; | |
933 | entry->zero = 0; | |
934 | entry->format = 1; | |
935 | entry->index = (index & 0x7fff); | |
936 | /* | |
937 | * IO-APIC RTE will be configured with virtual vector. | |
938 | * irq handler will do the explicit EOI to the io-apic. | |
939 | */ | |
940 | entry->vector = attr->ioapic_pin; | |
941 | entry->mask = 0; /* enable IRQ */ | |
942 | entry->trigger = attr->trigger; | |
943 | entry->polarity = attr->polarity; | |
944 | ||
945 | /* Mask level triggered irqs. | |
946 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. | |
947 | */ | |
948 | if (attr->trigger) | |
949 | entry->mask = 1; | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
4c1bad6a JR |
954 | /* |
955 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
956 | * | |
957 | * For both level and edge triggered, irq migration is a simple atomic | |
958 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
959 | * | |
960 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
961 | * updated vector information), by using a virtual vector (io-apic pin number). | |
962 | * Real vector that is used for interrupting cpu will be coming from | |
963 | * the interrupt-remapping table entry. | |
964 | * | |
965 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
966 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
967 | */ | |
968 | static int | |
969 | intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
970 | bool force) | |
971 | { | |
972 | struct irq_cfg *cfg = data->chip_data; | |
973 | unsigned int dest, irq = data->irq; | |
974 | struct irte irte; | |
ff164324 | 975 | int err; |
4c1bad6a | 976 | |
7eb9ae07 SS |
977 | if (!config_enabled(CONFIG_SMP)) |
978 | return -EINVAL; | |
979 | ||
4c1bad6a JR |
980 | if (!cpumask_intersects(mask, cpu_online_mask)) |
981 | return -EINVAL; | |
982 | ||
983 | if (get_irte(irq, &irte)) | |
984 | return -EBUSY; | |
985 | ||
ff164324 AG |
986 | err = assign_irq_vector(irq, cfg, mask); |
987 | if (err) | |
988 | return err; | |
4c1bad6a | 989 | |
ff164324 AG |
990 | err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest); |
991 | if (err) { | |
ed88bed8 | 992 | if (assign_irq_vector(irq, cfg, data->affinity)) |
ff164324 AG |
993 | pr_err("Failed to recover vector for irq %d\n", irq); |
994 | return err; | |
995 | } | |
4c1bad6a JR |
996 | |
997 | irte.vector = cfg->vector; | |
998 | irte.dest_id = IRTE_DEST(dest); | |
999 | ||
1000 | /* | |
1001 | * Atomically updates the IRTE with the new destination, vector | |
1002 | * and flushes the interrupt entry cache. | |
1003 | */ | |
1004 | modify_irte(irq, &irte); | |
1005 | ||
1006 | /* | |
1007 | * After this point, all the interrupts will start arriving | |
1008 | * at the new destination. So, time to cleanup the previous | |
1009 | * vector allocation. | |
1010 | */ | |
1011 | if (cfg->move_in_progress) | |
1012 | send_cleanup_vector(cfg); | |
1013 | ||
1014 | cpumask_copy(data->affinity, mask); | |
1015 | return 0; | |
1016 | } | |
0c3f173a | 1017 | |
5e2b930b JR |
1018 | static void intel_compose_msi_msg(struct pci_dev *pdev, |
1019 | unsigned int irq, unsigned int dest, | |
1020 | struct msi_msg *msg, u8 hpet_id) | |
1021 | { | |
1022 | struct irq_cfg *cfg; | |
1023 | struct irte irte; | |
c558df4a | 1024 | u16 sub_handle = 0; |
5e2b930b JR |
1025 | int ir_index; |
1026 | ||
1027 | cfg = irq_get_chip_data(irq); | |
1028 | ||
1029 | ir_index = map_irq_to_irte_handle(irq, &sub_handle); | |
1030 | BUG_ON(ir_index == -1); | |
1031 | ||
1032 | prepare_irte(&irte, cfg->vector, dest); | |
1033 | ||
1034 | /* Set source-id of interrupt request */ | |
1035 | if (pdev) | |
1036 | set_msi_sid(&irte, pdev); | |
1037 | else | |
1038 | set_hpet_sid(&irte, hpet_id); | |
1039 | ||
1040 | modify_irte(irq, &irte); | |
1041 | ||
1042 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1043 | msg->data = sub_handle; | |
1044 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1045 | MSI_ADDR_IR_SHV | | |
1046 | MSI_ADDR_IR_INDEX1(ir_index) | | |
1047 | MSI_ADDR_IR_INDEX2(ir_index); | |
1048 | } | |
1049 | ||
1050 | /* | |
1051 | * Map the PCI dev to the corresponding remapping hardware unit | |
1052 | * and allocate 'nvec' consecutive interrupt-remapping table entries | |
1053 | * in it. | |
1054 | */ | |
1055 | static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec) | |
1056 | { | |
1057 | struct intel_iommu *iommu; | |
1058 | int index; | |
1059 | ||
1060 | iommu = map_dev_to_ir(dev); | |
1061 | if (!iommu) { | |
1062 | printk(KERN_ERR | |
1063 | "Unable to map PCI %s to iommu\n", pci_name(dev)); | |
1064 | return -ENOENT; | |
1065 | } | |
1066 | ||
1067 | index = alloc_irte(iommu, irq, nvec); | |
1068 | if (index < 0) { | |
1069 | printk(KERN_ERR | |
1070 | "Unable to allocate %d IRTE for PCI %s\n", nvec, | |
1071 | pci_name(dev)); | |
1072 | return -ENOSPC; | |
1073 | } | |
1074 | return index; | |
1075 | } | |
1076 | ||
1077 | static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq, | |
1078 | int index, int sub_handle) | |
1079 | { | |
1080 | struct intel_iommu *iommu; | |
1081 | ||
1082 | iommu = map_dev_to_ir(pdev); | |
1083 | if (!iommu) | |
1084 | return -ENOENT; | |
1085 | /* | |
1086 | * setup the mapping between the irq and the IRTE | |
1087 | * base index, the sub_handle pointing to the | |
1088 | * appropriate interrupt remap table entry. | |
1089 | */ | |
1090 | set_irte_irq(irq, iommu, index, sub_handle); | |
1091 | ||
1092 | return 0; | |
1093 | } | |
1094 | ||
1095 | static int intel_setup_hpet_msi(unsigned int irq, unsigned int id) | |
1096 | { | |
1097 | struct intel_iommu *iommu = map_hpet_to_ir(id); | |
1098 | int index; | |
1099 | ||
1100 | if (!iommu) | |
1101 | return -1; | |
1102 | ||
1103 | index = alloc_irte(iommu, irq, 1); | |
1104 | if (index < 0) | |
1105 | return -1; | |
1106 | ||
1107 | return 0; | |
1108 | } | |
1109 | ||
736baef4 | 1110 | struct irq_remap_ops intel_irq_remap_ops = { |
95a02e97 SS |
1111 | .supported = intel_irq_remapping_supported, |
1112 | .prepare = dmar_table_init, | |
1113 | .enable = intel_enable_irq_remapping, | |
1114 | .disable = disable_irq_remapping, | |
1115 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 1116 | .enable_faulting = enable_drhd_fault_handling, |
0c3f173a | 1117 | .setup_ioapic_entry = intel_setup_ioapic_entry, |
4c1bad6a | 1118 | .set_affinity = intel_ioapic_set_affinity, |
9d619f65 | 1119 | .free_irq = free_irte, |
5e2b930b JR |
1120 | .compose_msi_msg = intel_compose_msi_msg, |
1121 | .msi_alloc_irq = intel_msi_alloc_irq, | |
1122 | .msi_setup_irq = intel_msi_setup_irq, | |
1123 | .setup_hpet_msi = intel_setup_hpet_msi, | |
736baef4 | 1124 | }; |