]>
Commit | Line | Data |
---|---|---|
5aeecaf4 | 1 | #include <linux/interrupt.h> |
ad3ad3f6 | 2 | #include <linux/dmar.h> |
2ae21010 | 3 | #include <linux/spinlock.h> |
5a0e3ad6 | 4 | #include <linux/slab.h> |
2ae21010 | 5 | #include <linux/jiffies.h> |
20f3097b | 6 | #include <linux/hpet.h> |
2ae21010 | 7 | #include <linux/pci.h> |
b6fcb33a | 8 | #include <linux/irq.h> |
8b48463f LZ |
9 | #include <linux/intel-iommu.h> |
10 | #include <linux/acpi.h> | |
b106ee63 | 11 | #include <linux/irqdomain.h> |
ad3ad3f6 | 12 | #include <asm/io_apic.h> |
17483a1f | 13 | #include <asm/smp.h> |
6d652ea1 | 14 | #include <asm/cpu.h> |
8a8f422d | 15 | #include <asm/irq_remapping.h> |
f007e99c | 16 | #include <asm/pci-direct.h> |
5e2b930b | 17 | #include <asm/msidef.h> |
ad3ad3f6 | 18 | |
8a8f422d | 19 | #include "irq_remapping.h" |
736baef4 | 20 | |
eef93fdb JR |
21 | struct ioapic_scope { |
22 | struct intel_iommu *iommu; | |
23 | unsigned int id; | |
24 | unsigned int bus; /* PCI bus number */ | |
25 | unsigned int devfn; /* PCI devfn number */ | |
26 | }; | |
27 | ||
28 | struct hpet_scope { | |
29 | struct intel_iommu *iommu; | |
30 | u8 id; | |
31 | unsigned int bus; | |
32 | unsigned int devfn; | |
33 | }; | |
34 | ||
b106ee63 JL |
35 | struct intel_ir_data { |
36 | struct irq_2_iommu irq_2_iommu; | |
37 | struct irte irte_entry; | |
38 | union { | |
39 | struct msi_msg msi_entry; | |
40 | }; | |
41 | }; | |
42 | ||
eef93fdb | 43 | #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0) |
13d09b66 | 44 | #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8) |
eef93fdb | 45 | |
13d09b66 | 46 | static int __read_mostly eim_mode; |
ad3ad3f6 | 47 | static struct ioapic_scope ir_ioapic[MAX_IO_APICS]; |
20f3097b | 48 | static struct hpet_scope ir_hpet[MAX_HPET_TBS]; |
d1423d56 | 49 | |
3a5670e8 JL |
50 | /* |
51 | * Lock ordering: | |
52 | * ->dmar_global_lock | |
53 | * ->irq_2_ir_lock | |
54 | * ->qi->q_lock | |
55 | * ->iommu->register_lock | |
56 | * Note: | |
57 | * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called | |
58 | * in single-threaded environment with interrupt disabled, so no need to tabke | |
59 | * the dmar_global_lock. | |
60 | */ | |
96f8e98b | 61 | static DEFINE_RAW_SPINLOCK(irq_2_ir_lock); |
b106ee63 | 62 | static struct irq_domain_ops intel_ir_domain_ops; |
d585d060 | 63 | |
694835dc JL |
64 | static int __init parse_ioapics_under_ir(void); |
65 | ||
8dedf4cf JL |
66 | static int alloc_irte(struct intel_iommu *iommu, int irq, |
67 | struct irq_2_iommu *irq_iommu, u16 count) | |
b6fcb33a SS |
68 | { |
69 | struct ir_table *table = iommu->ir_table; | |
b6fcb33a | 70 | unsigned int mask = 0; |
4c5502b1 | 71 | unsigned long flags; |
9f4c7448 | 72 | int index; |
b6fcb33a | 73 | |
d585d060 | 74 | if (!count || !irq_iommu) |
e420dfb4 | 75 | return -1; |
e420dfb4 | 76 | |
b6fcb33a SS |
77 | if (count > 1) { |
78 | count = __roundup_pow_of_two(count); | |
79 | mask = ilog2(count); | |
80 | } | |
81 | ||
82 | if (mask > ecap_max_handle_mask(iommu->ecap)) { | |
83 | printk(KERN_ERR | |
84 | "Requested mask %x exceeds the max invalidation handle" | |
85 | " mask value %Lx\n", mask, | |
86 | ecap_max_handle_mask(iommu->ecap)); | |
87 | return -1; | |
88 | } | |
89 | ||
96f8e98b | 90 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
360eb3c5 JL |
91 | index = bitmap_find_free_region(table->bitmap, |
92 | INTR_REMAP_TABLE_ENTRIES, mask); | |
93 | if (index < 0) { | |
94 | pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id); | |
95 | } else { | |
360eb3c5 JL |
96 | irq_iommu->iommu = iommu; |
97 | irq_iommu->irte_index = index; | |
98 | irq_iommu->sub_handle = 0; | |
99 | irq_iommu->irte_mask = mask; | |
100 | } | |
96f8e98b | 101 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
b6fcb33a SS |
102 | |
103 | return index; | |
104 | } | |
105 | ||
704126ad | 106 | static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask) |
b6fcb33a SS |
107 | { |
108 | struct qi_desc desc; | |
109 | ||
110 | desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask) | |
111 | | QI_IEC_SELECTIVE; | |
112 | desc.high = 0; | |
113 | ||
704126ad | 114 | return qi_submit_sync(&desc, iommu); |
b6fcb33a SS |
115 | } |
116 | ||
8dedf4cf JL |
117 | static int modify_irte(struct irq_2_iommu *irq_iommu, |
118 | struct irte *irte_modified) | |
b6fcb33a | 119 | { |
b6fcb33a | 120 | struct intel_iommu *iommu; |
4c5502b1 | 121 | unsigned long flags; |
d585d060 TG |
122 | struct irte *irte; |
123 | int rc, index; | |
b6fcb33a | 124 | |
d585d060 | 125 | if (!irq_iommu) |
b6fcb33a | 126 | return -1; |
d585d060 | 127 | |
96f8e98b | 128 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); |
b6fcb33a | 129 | |
e420dfb4 | 130 | iommu = irq_iommu->iommu; |
b6fcb33a | 131 | |
e420dfb4 | 132 | index = irq_iommu->irte_index + irq_iommu->sub_handle; |
b6fcb33a SS |
133 | irte = &iommu->ir_table->base[index]; |
134 | ||
c513b67e LT |
135 | set_64bit(&irte->low, irte_modified->low); |
136 | set_64bit(&irte->high, irte_modified->high); | |
b6fcb33a SS |
137 | __iommu_flush_cache(iommu, irte, sizeof(*irte)); |
138 | ||
704126ad | 139 | rc = qi_flush_iec(iommu, index, 0); |
96f8e98b | 140 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); |
704126ad YZ |
141 | |
142 | return rc; | |
b6fcb33a SS |
143 | } |
144 | ||
263b5e86 | 145 | static struct intel_iommu *map_hpet_to_ir(u8 hpet_id) |
20f3097b SS |
146 | { |
147 | int i; | |
148 | ||
149 | for (i = 0; i < MAX_HPET_TBS; i++) | |
a7a3dad9 | 150 | if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu) |
20f3097b SS |
151 | return ir_hpet[i].iommu; |
152 | return NULL; | |
153 | } | |
154 | ||
263b5e86 | 155 | static struct intel_iommu *map_ioapic_to_ir(int apic) |
89027d35 SS |
156 | { |
157 | int i; | |
158 | ||
159 | for (i = 0; i < MAX_IO_APICS; i++) | |
a7a3dad9 | 160 | if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu) |
89027d35 SS |
161 | return ir_ioapic[i].iommu; |
162 | return NULL; | |
163 | } | |
164 | ||
263b5e86 | 165 | static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev) |
75c46fa6 SS |
166 | { |
167 | struct dmar_drhd_unit *drhd; | |
168 | ||
169 | drhd = dmar_find_matched_drhd_unit(dev); | |
170 | if (!drhd) | |
171 | return NULL; | |
172 | ||
173 | return drhd->iommu; | |
174 | } | |
175 | ||
c4658b4e WH |
176 | static int clear_entries(struct irq_2_iommu *irq_iommu) |
177 | { | |
178 | struct irte *start, *entry, *end; | |
179 | struct intel_iommu *iommu; | |
180 | int index; | |
181 | ||
182 | if (irq_iommu->sub_handle) | |
183 | return 0; | |
184 | ||
185 | iommu = irq_iommu->iommu; | |
8dedf4cf | 186 | index = irq_iommu->irte_index; |
c4658b4e WH |
187 | |
188 | start = iommu->ir_table->base + index; | |
189 | end = start + (1 << irq_iommu->irte_mask); | |
190 | ||
191 | for (entry = start; entry < end; entry++) { | |
c513b67e LT |
192 | set_64bit(&entry->low, 0); |
193 | set_64bit(&entry->high, 0); | |
c4658b4e | 194 | } |
360eb3c5 JL |
195 | bitmap_release_region(iommu->ir_table->bitmap, index, |
196 | irq_iommu->irte_mask); | |
c4658b4e WH |
197 | |
198 | return qi_flush_iec(iommu, index, irq_iommu->irte_mask); | |
199 | } | |
200 | ||
f007e99c WH |
201 | /* |
202 | * source validation type | |
203 | */ | |
204 | #define SVT_NO_VERIFY 0x0 /* no verification is required */ | |
25985edc | 205 | #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */ |
f007e99c WH |
206 | #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */ |
207 | ||
208 | /* | |
209 | * source-id qualifier | |
210 | */ | |
211 | #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */ | |
212 | #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore | |
213 | * the third least significant bit | |
214 | */ | |
215 | #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore | |
216 | * the second and third least significant bits | |
217 | */ | |
218 | #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore | |
219 | * the least three significant bits | |
220 | */ | |
221 | ||
222 | /* | |
223 | * set SVT, SQ and SID fields of irte to verify | |
224 | * source ids of interrupt requests | |
225 | */ | |
226 | static void set_irte_sid(struct irte *irte, unsigned int svt, | |
227 | unsigned int sq, unsigned int sid) | |
228 | { | |
d1423d56 CW |
229 | if (disable_sourceid_checking) |
230 | svt = SVT_NO_VERIFY; | |
f007e99c WH |
231 | irte->svt = svt; |
232 | irte->sq = sq; | |
233 | irte->sid = sid; | |
234 | } | |
235 | ||
263b5e86 | 236 | static int set_ioapic_sid(struct irte *irte, int apic) |
f007e99c WH |
237 | { |
238 | int i; | |
239 | u16 sid = 0; | |
240 | ||
241 | if (!irte) | |
242 | return -1; | |
243 | ||
3a5670e8 | 244 | down_read(&dmar_global_lock); |
f007e99c | 245 | for (i = 0; i < MAX_IO_APICS; i++) { |
a7a3dad9 | 246 | if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) { |
f007e99c WH |
247 | sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn; |
248 | break; | |
249 | } | |
250 | } | |
3a5670e8 | 251 | up_read(&dmar_global_lock); |
f007e99c WH |
252 | |
253 | if (sid == 0) { | |
254 | pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic); | |
255 | return -1; | |
256 | } | |
257 | ||
2fe2c602 | 258 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid); |
f007e99c WH |
259 | |
260 | return 0; | |
261 | } | |
262 | ||
263b5e86 | 263 | static int set_hpet_sid(struct irte *irte, u8 id) |
20f3097b SS |
264 | { |
265 | int i; | |
266 | u16 sid = 0; | |
267 | ||
268 | if (!irte) | |
269 | return -1; | |
270 | ||
3a5670e8 | 271 | down_read(&dmar_global_lock); |
20f3097b | 272 | for (i = 0; i < MAX_HPET_TBS; i++) { |
a7a3dad9 | 273 | if (ir_hpet[i].iommu && ir_hpet[i].id == id) { |
20f3097b SS |
274 | sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn; |
275 | break; | |
276 | } | |
277 | } | |
3a5670e8 | 278 | up_read(&dmar_global_lock); |
20f3097b SS |
279 | |
280 | if (sid == 0) { | |
281 | pr_warning("Failed to set source-id of HPET block (%d)\n", id); | |
282 | return -1; | |
283 | } | |
284 | ||
285 | /* | |
286 | * Should really use SQ_ALL_16. Some platforms are broken. | |
287 | * While we figure out the right quirks for these broken platforms, use | |
288 | * SQ_13_IGNORE_3 for now. | |
289 | */ | |
290 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
579305f7 AW |
295 | struct set_msi_sid_data { |
296 | struct pci_dev *pdev; | |
297 | u16 alias; | |
298 | }; | |
299 | ||
300 | static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque) | |
301 | { | |
302 | struct set_msi_sid_data *data = opaque; | |
303 | ||
304 | data->pdev = pdev; | |
305 | data->alias = alias; | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
263b5e86 | 310 | static int set_msi_sid(struct irte *irte, struct pci_dev *dev) |
f007e99c | 311 | { |
579305f7 | 312 | struct set_msi_sid_data data; |
f007e99c WH |
313 | |
314 | if (!irte || !dev) | |
315 | return -1; | |
316 | ||
579305f7 | 317 | pci_for_each_dma_alias(dev, set_msi_sid_cb, &data); |
f007e99c | 318 | |
579305f7 AW |
319 | /* |
320 | * DMA alias provides us with a PCI device and alias. The only case | |
321 | * where the it will return an alias on a different bus than the | |
322 | * device is the case of a PCIe-to-PCI bridge, where the alias is for | |
323 | * the subordinate bus. In this case we can only verify the bus. | |
324 | * | |
325 | * If the alias device is on a different bus than our source device | |
326 | * then we have a topology based alias, use it. | |
327 | * | |
328 | * Otherwise, the alias is for a device DMA quirk and we cannot | |
329 | * assume that MSI uses the same requester ID. Therefore use the | |
330 | * original device. | |
331 | */ | |
332 | if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number) | |
333 | set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16, | |
334 | PCI_DEVID(PCI_BUS_NUM(data.alias), | |
335 | dev->bus->number)); | |
336 | else if (data.pdev->bus->number != dev->bus->number) | |
337 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias); | |
338 | else | |
339 | set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, | |
340 | PCI_DEVID(dev->bus->number, dev->devfn)); | |
f007e99c WH |
341 | |
342 | return 0; | |
343 | } | |
344 | ||
95a02e97 | 345 | static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode) |
2ae21010 SS |
346 | { |
347 | u64 addr; | |
c416daa9 | 348 | u32 sts; |
2ae21010 SS |
349 | unsigned long flags; |
350 | ||
351 | addr = virt_to_phys((void *)iommu->ir_table->base); | |
352 | ||
1f5b3c3f | 353 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
354 | |
355 | dmar_writeq(iommu->reg + DMAR_IRTA_REG, | |
356 | (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE); | |
357 | ||
358 | /* Set interrupt-remapping table pointer */ | |
f63ef690 | 359 | writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
360 | |
361 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
362 | readl, (sts & DMA_GSTS_IRTPS), sts); | |
1f5b3c3f | 363 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
364 | |
365 | /* | |
366 | * global invalidation of interrupt entry cache before enabling | |
367 | * interrupt-remapping. | |
368 | */ | |
369 | qi_global_iec(iommu); | |
370 | ||
1f5b3c3f | 371 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
2ae21010 SS |
372 | |
373 | /* Enable interrupt-remapping */ | |
2ae21010 | 374 | iommu->gcmd |= DMA_GCMD_IRE; |
af8d102f | 375 | iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */ |
c416daa9 | 376 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
2ae21010 SS |
377 | |
378 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
379 | readl, (sts & DMA_GSTS_IRES), sts); | |
380 | ||
af8d102f AL |
381 | /* |
382 | * With CFI clear in the Global Command register, we should be | |
383 | * protected from dangerous (i.e. compatibility) interrupts | |
384 | * regardless of x2apic status. Check just to be sure. | |
385 | */ | |
386 | if (sts & DMA_GSTS_CFIS) | |
387 | WARN(1, KERN_WARNING | |
388 | "Compatibility-format IRQs enabled despite intr remapping;\n" | |
389 | "you are vulnerable to IRQ injection.\n"); | |
390 | ||
1f5b3c3f | 391 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
2ae21010 SS |
392 | } |
393 | ||
a7a3dad9 | 394 | static int intel_setup_irq_remapping(struct intel_iommu *iommu) |
2ae21010 SS |
395 | { |
396 | struct ir_table *ir_table; | |
397 | struct page *pages; | |
360eb3c5 | 398 | unsigned long *bitmap; |
2ae21010 | 399 | |
a7a3dad9 JL |
400 | if (iommu->ir_table) |
401 | return 0; | |
2ae21010 | 402 | |
e3a981d6 | 403 | ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL); |
a7a3dad9 | 404 | if (!ir_table) |
2ae21010 SS |
405 | return -ENOMEM; |
406 | ||
e3a981d6 | 407 | pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO, |
824cd75b | 408 | INTR_REMAP_PAGE_ORDER); |
2ae21010 | 409 | if (!pages) { |
360eb3c5 JL |
410 | pr_err("IR%d: failed to allocate pages of order %d\n", |
411 | iommu->seq_id, INTR_REMAP_PAGE_ORDER); | |
a7a3dad9 | 412 | goto out_free_table; |
2ae21010 SS |
413 | } |
414 | ||
360eb3c5 JL |
415 | bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES), |
416 | sizeof(long), GFP_ATOMIC); | |
417 | if (bitmap == NULL) { | |
418 | pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id); | |
a7a3dad9 | 419 | goto out_free_pages; |
360eb3c5 JL |
420 | } |
421 | ||
b106ee63 JL |
422 | iommu->ir_domain = irq_domain_add_hierarchy(arch_get_ir_parent_domain(), |
423 | 0, INTR_REMAP_TABLE_ENTRIES, | |
424 | NULL, &intel_ir_domain_ops, | |
425 | iommu); | |
426 | if (!iommu->ir_domain) { | |
427 | pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); | |
428 | goto out_free_bitmap; | |
429 | } | |
430 | iommu->ir_msi_domain = arch_create_msi_irq_domain(iommu->ir_domain); | |
431 | ||
2ae21010 | 432 | ir_table->base = page_address(pages); |
360eb3c5 | 433 | ir_table->bitmap = bitmap; |
a7a3dad9 | 434 | iommu->ir_table = ir_table; |
2ae21010 | 435 | return 0; |
a7a3dad9 | 436 | |
b106ee63 JL |
437 | out_free_bitmap: |
438 | kfree(bitmap); | |
a7a3dad9 JL |
439 | out_free_pages: |
440 | __free_pages(pages, INTR_REMAP_PAGE_ORDER); | |
441 | out_free_table: | |
442 | kfree(ir_table); | |
443 | return -ENOMEM; | |
444 | } | |
445 | ||
446 | static void intel_teardown_irq_remapping(struct intel_iommu *iommu) | |
447 | { | |
448 | if (iommu && iommu->ir_table) { | |
b106ee63 JL |
449 | if (iommu->ir_msi_domain) { |
450 | irq_domain_remove(iommu->ir_msi_domain); | |
451 | iommu->ir_msi_domain = NULL; | |
452 | } | |
453 | if (iommu->ir_domain) { | |
454 | irq_domain_remove(iommu->ir_domain); | |
455 | iommu->ir_domain = NULL; | |
456 | } | |
a7a3dad9 JL |
457 | free_pages((unsigned long)iommu->ir_table->base, |
458 | INTR_REMAP_PAGE_ORDER); | |
459 | kfree(iommu->ir_table->bitmap); | |
460 | kfree(iommu->ir_table); | |
461 | iommu->ir_table = NULL; | |
462 | } | |
2ae21010 SS |
463 | } |
464 | ||
eba67e5d SS |
465 | /* |
466 | * Disable Interrupt Remapping. | |
467 | */ | |
95a02e97 | 468 | static void iommu_disable_irq_remapping(struct intel_iommu *iommu) |
eba67e5d SS |
469 | { |
470 | unsigned long flags; | |
471 | u32 sts; | |
472 | ||
473 | if (!ecap_ir_support(iommu->ecap)) | |
474 | return; | |
475 | ||
b24696bc FY |
476 | /* |
477 | * global invalidation of interrupt entry cache before disabling | |
478 | * interrupt-remapping. | |
479 | */ | |
480 | qi_global_iec(iommu); | |
481 | ||
1f5b3c3f | 482 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
eba67e5d SS |
483 | |
484 | sts = dmar_readq(iommu->reg + DMAR_GSTS_REG); | |
485 | if (!(sts & DMA_GSTS_IRES)) | |
486 | goto end; | |
487 | ||
488 | iommu->gcmd &= ~DMA_GCMD_IRE; | |
489 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); | |
490 | ||
491 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, | |
492 | readl, !(sts & DMA_GSTS_IRES), sts); | |
493 | ||
494 | end: | |
1f5b3c3f | 495 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
eba67e5d SS |
496 | } |
497 | ||
41750d31 SS |
498 | static int __init dmar_x2apic_optout(void) |
499 | { | |
500 | struct acpi_table_dmar *dmar; | |
501 | dmar = (struct acpi_table_dmar *)dmar_tbl; | |
502 | if (!dmar || no_x2apic_optout) | |
503 | return 0; | |
504 | return dmar->flags & DMAR_X2APIC_OPT_OUT; | |
505 | } | |
506 | ||
11190302 TG |
507 | static void __init intel_cleanup_irq_remapping(void) |
508 | { | |
509 | struct dmar_drhd_unit *drhd; | |
510 | struct intel_iommu *iommu; | |
511 | ||
512 | for_each_iommu(iommu, drhd) { | |
513 | if (ecap_ir_support(iommu->ecap)) { | |
514 | iommu_disable_irq_remapping(iommu); | |
515 | intel_teardown_irq_remapping(iommu); | |
516 | } | |
517 | } | |
518 | ||
519 | if (x2apic_supported()) | |
520 | pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n"); | |
521 | } | |
522 | ||
523 | static int __init intel_prepare_irq_remapping(void) | |
2ae21010 SS |
524 | { |
525 | struct dmar_drhd_unit *drhd; | |
7c919779 | 526 | struct intel_iommu *iommu; |
2ae21010 | 527 | |
2966d956 JL |
528 | if (irq_remap_broken) { |
529 | printk(KERN_WARNING | |
530 | "This system BIOS has enabled interrupt remapping\n" | |
531 | "on a chipset that contains an erratum making that\n" | |
532 | "feature unstable. To maintain system stability\n" | |
533 | "interrupt remapping is being disabled. Please\n" | |
534 | "contact your BIOS vendor for an update\n"); | |
535 | add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); | |
2966d956 JL |
536 | return -ENODEV; |
537 | } | |
538 | ||
11190302 | 539 | if (dmar_table_init() < 0) |
2966d956 JL |
540 | return -ENODEV; |
541 | ||
542 | if (!dmar_ir_support()) | |
543 | return -ENODEV; | |
af8d102f | 544 | |
e936d077 | 545 | if (parse_ioapics_under_ir() != 1) { |
11190302 | 546 | printk(KERN_INFO "Not enabling interrupt remapping\n"); |
af8d102f | 547 | goto error; |
e936d077 YS |
548 | } |
549 | ||
69cf1d8a | 550 | /* First make sure all IOMMUs support IRQ remapping */ |
2966d956 | 551 | for_each_iommu(iommu, drhd) |
69cf1d8a JR |
552 | if (!ecap_ir_support(iommu->ecap)) |
553 | goto error; | |
554 | ||
555 | /* Do the allocations early */ | |
556 | for_each_iommu(iommu, drhd) | |
557 | if (intel_setup_irq_remapping(iommu)) | |
11190302 | 558 | goto error; |
69cf1d8a | 559 | |
11190302 | 560 | return 0; |
2966d956 | 561 | |
11190302 TG |
562 | error: |
563 | intel_cleanup_irq_remapping(); | |
2966d956 | 564 | return -ENODEV; |
11190302 TG |
565 | } |
566 | ||
567 | static int __init intel_enable_irq_remapping(void) | |
568 | { | |
569 | struct dmar_drhd_unit *drhd; | |
570 | struct intel_iommu *iommu; | |
2f119c78 | 571 | bool setup = false; |
11190302 TG |
572 | int eim = 0; |
573 | ||
574 | if (x2apic_supported()) { | |
41750d31 | 575 | eim = !dmar_x2apic_optout(); |
af8d102f AL |
576 | if (!eim) |
577 | printk(KERN_WARNING | |
578 | "Your BIOS is broken and requested that x2apic be disabled.\n" | |
579 | "This will slightly decrease performance.\n" | |
580 | "Use 'intremap=no_x2apic_optout' to override BIOS request.\n"); | |
41750d31 SS |
581 | } |
582 | ||
7c919779 | 583 | for_each_iommu(iommu, drhd) { |
34aaaa94 HW |
584 | /* |
585 | * If the queued invalidation is already initialized, | |
586 | * shouldn't disable it. | |
587 | */ | |
588 | if (iommu->qi) | |
589 | continue; | |
590 | ||
1531a6a6 SS |
591 | /* |
592 | * Clear previous faults. | |
593 | */ | |
594 | dmar_fault(-1, iommu); | |
595 | ||
596 | /* | |
597 | * Disable intr remapping and queued invalidation, if already | |
598 | * enabled prior to OS handover. | |
599 | */ | |
95a02e97 | 600 | iommu_disable_irq_remapping(iommu); |
1531a6a6 SS |
601 | |
602 | dmar_disable_qi(iommu); | |
603 | } | |
604 | ||
2ae21010 SS |
605 | /* |
606 | * check for the Interrupt-remapping support | |
607 | */ | |
69cf1d8a | 608 | for_each_iommu(iommu, drhd) |
2ae21010 SS |
609 | if (eim && !ecap_eim_support(iommu->ecap)) { |
610 | printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, " | |
611 | " ecap %Lx\n", drhd->reg_base_addr, iommu->ecap); | |
13d09b66 | 612 | eim = 0; |
2ae21010 | 613 | } |
13d09b66 JL |
614 | eim_mode = eim; |
615 | if (eim) | |
616 | pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n"); | |
2ae21010 SS |
617 | |
618 | /* | |
619 | * Enable queued invalidation for all the DRHD's. | |
620 | */ | |
7c919779 JL |
621 | for_each_iommu(iommu, drhd) { |
622 | int ret = dmar_enable_qi(iommu); | |
2ae21010 SS |
623 | |
624 | if (ret) { | |
625 | printk(KERN_ERR "DRHD %Lx: failed to enable queued, " | |
626 | " invalidation, ecap %Lx, ret %d\n", | |
627 | drhd->reg_base_addr, iommu->ecap, ret); | |
af8d102f | 628 | goto error; |
2ae21010 SS |
629 | } |
630 | } | |
631 | ||
632 | /* | |
633 | * Setup Interrupt-remapping for all the DRHD's now. | |
634 | */ | |
7c919779 | 635 | for_each_iommu(iommu, drhd) { |
a7a3dad9 | 636 | iommu_set_irq_remapping(iommu, eim); |
2f119c78 | 637 | setup = true; |
2ae21010 SS |
638 | } |
639 | ||
640 | if (!setup) | |
641 | goto error; | |
642 | ||
95a02e97 | 643 | irq_remapping_enabled = 1; |
afcc8a40 | 644 | |
41750d31 | 645 | pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic"); |
2ae21010 | 646 | |
41750d31 | 647 | return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE; |
2ae21010 SS |
648 | |
649 | error: | |
11190302 | 650 | intel_cleanup_irq_remapping(); |
2ae21010 SS |
651 | return -1; |
652 | } | |
ad3ad3f6 | 653 | |
a7a3dad9 JL |
654 | static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope, |
655 | struct intel_iommu *iommu, | |
656 | struct acpi_dmar_hardware_unit *drhd) | |
20f3097b SS |
657 | { |
658 | struct acpi_dmar_pci_path *path; | |
659 | u8 bus; | |
a7a3dad9 | 660 | int count, free = -1; |
20f3097b SS |
661 | |
662 | bus = scope->bus; | |
663 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
664 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
665 | / sizeof(struct acpi_dmar_pci_path); | |
666 | ||
667 | while (--count > 0) { | |
668 | /* | |
669 | * Access PCI directly due to the PCI | |
670 | * subsystem isn't initialized yet. | |
671 | */ | |
fa5f508f | 672 | bus = read_pci_config_byte(bus, path->device, path->function, |
20f3097b SS |
673 | PCI_SECONDARY_BUS); |
674 | path++; | |
675 | } | |
a7a3dad9 JL |
676 | |
677 | for (count = 0; count < MAX_HPET_TBS; count++) { | |
678 | if (ir_hpet[count].iommu == iommu && | |
679 | ir_hpet[count].id == scope->enumeration_id) | |
680 | return 0; | |
681 | else if (ir_hpet[count].iommu == NULL && free == -1) | |
682 | free = count; | |
683 | } | |
684 | if (free == -1) { | |
685 | pr_warn("Exceeded Max HPET blocks\n"); | |
686 | return -ENOSPC; | |
687 | } | |
688 | ||
689 | ir_hpet[free].iommu = iommu; | |
690 | ir_hpet[free].id = scope->enumeration_id; | |
691 | ir_hpet[free].bus = bus; | |
692 | ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function); | |
693 | pr_info("HPET id %d under DRHD base 0x%Lx\n", | |
694 | scope->enumeration_id, drhd->address); | |
695 | ||
696 | return 0; | |
20f3097b SS |
697 | } |
698 | ||
a7a3dad9 JL |
699 | static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope, |
700 | struct intel_iommu *iommu, | |
701 | struct acpi_dmar_hardware_unit *drhd) | |
f007e99c WH |
702 | { |
703 | struct acpi_dmar_pci_path *path; | |
704 | u8 bus; | |
a7a3dad9 | 705 | int count, free = -1; |
f007e99c WH |
706 | |
707 | bus = scope->bus; | |
708 | path = (struct acpi_dmar_pci_path *)(scope + 1); | |
709 | count = (scope->length - sizeof(struct acpi_dmar_device_scope)) | |
710 | / sizeof(struct acpi_dmar_pci_path); | |
711 | ||
712 | while (--count > 0) { | |
713 | /* | |
714 | * Access PCI directly due to the PCI | |
715 | * subsystem isn't initialized yet. | |
716 | */ | |
fa5f508f | 717 | bus = read_pci_config_byte(bus, path->device, path->function, |
f007e99c WH |
718 | PCI_SECONDARY_BUS); |
719 | path++; | |
720 | } | |
721 | ||
a7a3dad9 JL |
722 | for (count = 0; count < MAX_IO_APICS; count++) { |
723 | if (ir_ioapic[count].iommu == iommu && | |
724 | ir_ioapic[count].id == scope->enumeration_id) | |
725 | return 0; | |
726 | else if (ir_ioapic[count].iommu == NULL && free == -1) | |
727 | free = count; | |
728 | } | |
729 | if (free == -1) { | |
730 | pr_warn("Exceeded Max IO APICS\n"); | |
731 | return -ENOSPC; | |
732 | } | |
733 | ||
734 | ir_ioapic[free].bus = bus; | |
735 | ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function); | |
736 | ir_ioapic[free].iommu = iommu; | |
737 | ir_ioapic[free].id = scope->enumeration_id; | |
738 | pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n", | |
739 | scope->enumeration_id, drhd->address, iommu->seq_id); | |
740 | ||
741 | return 0; | |
f007e99c WH |
742 | } |
743 | ||
20f3097b SS |
744 | static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header, |
745 | struct intel_iommu *iommu) | |
ad3ad3f6 | 746 | { |
a7a3dad9 | 747 | int ret = 0; |
ad3ad3f6 SS |
748 | struct acpi_dmar_hardware_unit *drhd; |
749 | struct acpi_dmar_device_scope *scope; | |
750 | void *start, *end; | |
751 | ||
752 | drhd = (struct acpi_dmar_hardware_unit *)header; | |
ad3ad3f6 SS |
753 | start = (void *)(drhd + 1); |
754 | end = ((void *)drhd) + header->length; | |
755 | ||
a7a3dad9 | 756 | while (start < end && ret == 0) { |
ad3ad3f6 | 757 | scope = start; |
a7a3dad9 JL |
758 | if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC) |
759 | ret = ir_parse_one_ioapic_scope(scope, iommu, drhd); | |
760 | else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) | |
761 | ret = ir_parse_one_hpet_scope(scope, iommu, drhd); | |
762 | start += scope->length; | |
763 | } | |
ad3ad3f6 | 764 | |
a7a3dad9 JL |
765 | return ret; |
766 | } | |
20f3097b | 767 | |
a7a3dad9 JL |
768 | static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu) |
769 | { | |
770 | int i; | |
20f3097b | 771 | |
a7a3dad9 JL |
772 | for (i = 0; i < MAX_HPET_TBS; i++) |
773 | if (ir_hpet[i].iommu == iommu) | |
774 | ir_hpet[i].iommu = NULL; | |
ad3ad3f6 | 775 | |
a7a3dad9 JL |
776 | for (i = 0; i < MAX_IO_APICS; i++) |
777 | if (ir_ioapic[i].iommu == iommu) | |
778 | ir_ioapic[i].iommu = NULL; | |
ad3ad3f6 SS |
779 | } |
780 | ||
781 | /* | |
782 | * Finds the assocaition between IOAPIC's and its Interrupt-remapping | |
783 | * hardware unit. | |
784 | */ | |
694835dc | 785 | static int __init parse_ioapics_under_ir(void) |
ad3ad3f6 SS |
786 | { |
787 | struct dmar_drhd_unit *drhd; | |
7c919779 | 788 | struct intel_iommu *iommu; |
2f119c78 | 789 | bool ir_supported = false; |
32ab31e0 | 790 | int ioapic_idx; |
ad3ad3f6 | 791 | |
7c919779 | 792 | for_each_iommu(iommu, drhd) |
ad3ad3f6 | 793 | if (ecap_ir_support(iommu->ecap)) { |
20f3097b | 794 | if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu)) |
ad3ad3f6 SS |
795 | return -1; |
796 | ||
2f119c78 | 797 | ir_supported = true; |
ad3ad3f6 | 798 | } |
ad3ad3f6 | 799 | |
32ab31e0 SF |
800 | if (!ir_supported) |
801 | return 0; | |
802 | ||
803 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { | |
804 | int ioapic_id = mpc_ioapic_id(ioapic_idx); | |
805 | if (!map_ioapic_to_ir(ioapic_id)) { | |
806 | pr_err(FW_BUG "ioapic %d has no mapping iommu, " | |
807 | "interrupt remapping will be disabled\n", | |
808 | ioapic_id); | |
809 | return -1; | |
810 | } | |
ad3ad3f6 SS |
811 | } |
812 | ||
32ab31e0 | 813 | return 1; |
ad3ad3f6 | 814 | } |
b24696bc | 815 | |
6a7885c4 | 816 | static int __init ir_dev_scope_init(void) |
c2c7286a | 817 | { |
3a5670e8 JL |
818 | int ret; |
819 | ||
95a02e97 | 820 | if (!irq_remapping_enabled) |
c2c7286a SS |
821 | return 0; |
822 | ||
3a5670e8 JL |
823 | down_write(&dmar_global_lock); |
824 | ret = dmar_dev_scope_init(); | |
825 | up_write(&dmar_global_lock); | |
826 | ||
827 | return ret; | |
c2c7286a SS |
828 | } |
829 | rootfs_initcall(ir_dev_scope_init); | |
830 | ||
95a02e97 | 831 | static void disable_irq_remapping(void) |
b24696bc FY |
832 | { |
833 | struct dmar_drhd_unit *drhd; | |
834 | struct intel_iommu *iommu = NULL; | |
835 | ||
836 | /* | |
837 | * Disable Interrupt-remapping for all the DRHD's now. | |
838 | */ | |
839 | for_each_iommu(iommu, drhd) { | |
840 | if (!ecap_ir_support(iommu->ecap)) | |
841 | continue; | |
842 | ||
95a02e97 | 843 | iommu_disable_irq_remapping(iommu); |
b24696bc FY |
844 | } |
845 | } | |
846 | ||
95a02e97 | 847 | static int reenable_irq_remapping(int eim) |
b24696bc FY |
848 | { |
849 | struct dmar_drhd_unit *drhd; | |
2f119c78 | 850 | bool setup = false; |
b24696bc FY |
851 | struct intel_iommu *iommu = NULL; |
852 | ||
853 | for_each_iommu(iommu, drhd) | |
854 | if (iommu->qi) | |
855 | dmar_reenable_qi(iommu); | |
856 | ||
857 | /* | |
858 | * Setup Interrupt-remapping for all the DRHD's now. | |
859 | */ | |
860 | for_each_iommu(iommu, drhd) { | |
861 | if (!ecap_ir_support(iommu->ecap)) | |
862 | continue; | |
863 | ||
864 | /* Set up interrupt remapping for iommu.*/ | |
95a02e97 | 865 | iommu_set_irq_remapping(iommu, eim); |
2f119c78 | 866 | setup = true; |
b24696bc FY |
867 | } |
868 | ||
869 | if (!setup) | |
870 | goto error; | |
871 | ||
872 | return 0; | |
873 | ||
874 | error: | |
875 | /* | |
876 | * handle error condition gracefully here! | |
877 | */ | |
878 | return -1; | |
879 | } | |
880 | ||
3c6e5675 | 881 | static void prepare_irte(struct irte *irte, int vector, unsigned int dest) |
0c3f173a JR |
882 | { |
883 | memset(irte, 0, sizeof(*irte)); | |
884 | ||
885 | irte->present = 1; | |
886 | irte->dst_mode = apic->irq_dest_mode; | |
887 | /* | |
888 | * Trigger mode in the IRTE will always be edge, and for IO-APIC, the | |
889 | * actual level or edge trigger will be setup in the IO-APIC | |
890 | * RTE. This will help simplify level triggered irq migration. | |
891 | * For more details, see the comments (in io_apic.c) explainig IO-APIC | |
892 | * irq migration in the presence of interrupt-remapping. | |
893 | */ | |
894 | irte->trigger_mode = 0; | |
895 | irte->dlvry_mode = apic->irq_delivery_mode; | |
896 | irte->vector = vector; | |
897 | irte->dest_id = IRTE_DEST(dest); | |
898 | irte->redir_hint = 1; | |
899 | } | |
900 | ||
b106ee63 JL |
901 | static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info) |
902 | { | |
903 | struct intel_iommu *iommu = NULL; | |
904 | ||
905 | if (!info) | |
906 | return NULL; | |
907 | ||
908 | switch (info->type) { | |
909 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
910 | iommu = map_ioapic_to_ir(info->ioapic_id); | |
911 | break; | |
912 | case X86_IRQ_ALLOC_TYPE_HPET: | |
913 | iommu = map_hpet_to_ir(info->hpet_id); | |
914 | break; | |
915 | case X86_IRQ_ALLOC_TYPE_MSI: | |
916 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
917 | iommu = map_dev_to_ir(info->msi_dev); | |
918 | break; | |
919 | default: | |
920 | BUG_ON(1); | |
921 | break; | |
922 | } | |
923 | ||
924 | return iommu ? iommu->ir_domain : NULL; | |
925 | } | |
926 | ||
927 | static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info) | |
928 | { | |
929 | struct intel_iommu *iommu; | |
930 | ||
931 | if (!info) | |
932 | return NULL; | |
933 | ||
934 | switch (info->type) { | |
935 | case X86_IRQ_ALLOC_TYPE_MSI: | |
936 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
937 | iommu = map_dev_to_ir(info->msi_dev); | |
938 | if (iommu) | |
939 | return iommu->ir_msi_domain; | |
940 | break; | |
941 | default: | |
942 | break; | |
943 | } | |
944 | ||
945 | return NULL; | |
946 | } | |
947 | ||
736baef4 | 948 | struct irq_remap_ops intel_irq_remap_ops = { |
11190302 | 949 | .prepare = intel_prepare_irq_remapping, |
95a02e97 SS |
950 | .enable = intel_enable_irq_remapping, |
951 | .disable = disable_irq_remapping, | |
952 | .reenable = reenable_irq_remapping, | |
4f3d8b67 | 953 | .enable_faulting = enable_drhd_fault_handling, |
b106ee63 JL |
954 | .get_ir_irq_domain = intel_get_ir_irq_domain, |
955 | .get_irq_domain = intel_get_irq_domain, | |
956 | }; | |
957 | ||
958 | /* | |
959 | * Migrate the IO-APIC irq in the presence of intr-remapping. | |
960 | * | |
961 | * For both level and edge triggered, irq migration is a simple atomic | |
962 | * update(of vector and cpu destination) of IRTE and flush the hardware cache. | |
963 | * | |
964 | * For level triggered, we eliminate the io-apic RTE modification (with the | |
965 | * updated vector information), by using a virtual vector (io-apic pin number). | |
966 | * Real vector that is used for interrupting cpu will be coming from | |
967 | * the interrupt-remapping table entry. | |
968 | * | |
969 | * As the migration is a simple atomic update of IRTE, the same mechanism | |
970 | * is used to migrate MSI irq's in the presence of interrupt-remapping. | |
971 | */ | |
972 | static int | |
973 | intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
974 | bool force) | |
975 | { | |
976 | struct intel_ir_data *ir_data = data->chip_data; | |
977 | struct irte *irte = &ir_data->irte_entry; | |
978 | struct irq_cfg *cfg = irqd_cfg(data); | |
979 | struct irq_data *parent = data->parent_data; | |
980 | int ret; | |
981 | ||
982 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
983 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
984 | return ret; | |
985 | ||
986 | /* | |
987 | * Atomically updates the IRTE with the new destination, vector | |
988 | * and flushes the interrupt entry cache. | |
989 | */ | |
990 | irte->vector = cfg->vector; | |
991 | irte->dest_id = IRTE_DEST(cfg->dest_apicid); | |
992 | modify_irte(&ir_data->irq_2_iommu, irte); | |
993 | ||
994 | /* | |
995 | * After this point, all the interrupts will start arriving | |
996 | * at the new destination. So, time to cleanup the previous | |
997 | * vector allocation. | |
998 | */ | |
999 | if (cfg->move_in_progress) | |
1000 | send_cleanup_vector(cfg); | |
1001 | ||
1002 | return IRQ_SET_MASK_OK_DONE; | |
1003 | } | |
1004 | ||
1005 | static void intel_ir_compose_msi_msg(struct irq_data *irq_data, | |
1006 | struct msi_msg *msg) | |
1007 | { | |
1008 | struct intel_ir_data *ir_data = irq_data->chip_data; | |
1009 | ||
1010 | *msg = ir_data->msi_entry; | |
1011 | } | |
1012 | ||
1013 | static struct irq_chip intel_ir_chip = { | |
1014 | .irq_ack = ir_ack_apic_edge, | |
1015 | .irq_set_affinity = intel_ir_set_affinity, | |
1016 | .irq_compose_msi_msg = intel_ir_compose_msi_msg, | |
1017 | }; | |
1018 | ||
1019 | static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data, | |
1020 | struct irq_cfg *irq_cfg, | |
1021 | struct irq_alloc_info *info, | |
1022 | int index, int sub_handle) | |
1023 | { | |
1024 | struct IR_IO_APIC_route_entry *entry; | |
1025 | struct irte *irte = &data->irte_entry; | |
1026 | struct msi_msg *msg = &data->msi_entry; | |
1027 | ||
1028 | prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid); | |
1029 | switch (info->type) { | |
1030 | case X86_IRQ_ALLOC_TYPE_IOAPIC: | |
1031 | /* Set source-id of interrupt request */ | |
1032 | set_ioapic_sid(irte, info->ioapic_id); | |
1033 | apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", | |
1034 | info->ioapic_id, irte->present, irte->fpd, | |
1035 | irte->dst_mode, irte->redir_hint, | |
1036 | irte->trigger_mode, irte->dlvry_mode, | |
1037 | irte->avail, irte->vector, irte->dest_id, | |
1038 | irte->sid, irte->sq, irte->svt); | |
1039 | ||
1040 | entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry; | |
1041 | info->ioapic_entry = NULL; | |
1042 | memset(entry, 0, sizeof(*entry)); | |
1043 | entry->index2 = (index >> 15) & 0x1; | |
1044 | entry->zero = 0; | |
1045 | entry->format = 1; | |
1046 | entry->index = (index & 0x7fff); | |
1047 | /* | |
1048 | * IO-APIC RTE will be configured with virtual vector. | |
1049 | * irq handler will do the explicit EOI to the io-apic. | |
1050 | */ | |
1051 | entry->vector = info->ioapic_pin; | |
1052 | entry->mask = 0; /* enable IRQ */ | |
1053 | entry->trigger = info->ioapic_trigger; | |
1054 | entry->polarity = info->ioapic_polarity; | |
1055 | if (info->ioapic_trigger) | |
1056 | entry->mask = 1; /* Mask level triggered irqs. */ | |
1057 | break; | |
1058 | ||
1059 | case X86_IRQ_ALLOC_TYPE_HPET: | |
1060 | case X86_IRQ_ALLOC_TYPE_MSI: | |
1061 | case X86_IRQ_ALLOC_TYPE_MSIX: | |
1062 | if (info->type == X86_IRQ_ALLOC_TYPE_HPET) | |
1063 | set_hpet_sid(irte, info->hpet_id); | |
1064 | else | |
1065 | set_msi_sid(irte, info->msi_dev); | |
1066 | ||
1067 | msg->address_hi = MSI_ADDR_BASE_HI; | |
1068 | msg->data = sub_handle; | |
1069 | msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | | |
1070 | MSI_ADDR_IR_SHV | | |
1071 | MSI_ADDR_IR_INDEX1(index) | | |
1072 | MSI_ADDR_IR_INDEX2(index); | |
1073 | break; | |
1074 | ||
1075 | default: | |
1076 | BUG_ON(1); | |
1077 | break; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | static void intel_free_irq_resources(struct irq_domain *domain, | |
1082 | unsigned int virq, unsigned int nr_irqs) | |
1083 | { | |
1084 | struct irq_data *irq_data; | |
1085 | struct intel_ir_data *data; | |
1086 | struct irq_2_iommu *irq_iommu; | |
1087 | unsigned long flags; | |
1088 | int i; | |
1089 | ||
1090 | for (i = 0; i < nr_irqs; i++) { | |
1091 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1092 | if (irq_data && irq_data->chip_data) { | |
1093 | data = irq_data->chip_data; | |
1094 | irq_iommu = &data->irq_2_iommu; | |
1095 | raw_spin_lock_irqsave(&irq_2_ir_lock, flags); | |
1096 | clear_entries(irq_iommu); | |
1097 | raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags); | |
1098 | irq_domain_reset_irq_data(irq_data); | |
1099 | kfree(data); | |
1100 | } | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | static int intel_irq_remapping_alloc(struct irq_domain *domain, | |
1105 | unsigned int virq, unsigned int nr_irqs, | |
1106 | void *arg) | |
1107 | { | |
1108 | struct intel_iommu *iommu = domain->host_data; | |
1109 | struct irq_alloc_info *info = arg; | |
1110 | struct intel_ir_data *data; | |
1111 | struct irq_data *irq_data; | |
1112 | struct irq_cfg *irq_cfg; | |
1113 | int i, ret, index; | |
1114 | ||
1115 | if (!info || !iommu) | |
1116 | return -EINVAL; | |
1117 | if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI && | |
1118 | info->type != X86_IRQ_ALLOC_TYPE_MSIX) | |
1119 | return -EINVAL; | |
1120 | ||
1121 | /* | |
1122 | * With IRQ remapping enabled, don't need contiguous CPU vectors | |
1123 | * to support multiple MSI interrupts. | |
1124 | */ | |
1125 | if (info->type == X86_IRQ_ALLOC_TYPE_MSI) | |
1126 | info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
1127 | ||
1128 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); | |
1129 | if (ret < 0) | |
1130 | return ret; | |
1131 | ||
1132 | ret = -ENOMEM; | |
1133 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1134 | if (!data) | |
1135 | goto out_free_parent; | |
1136 | ||
1137 | down_read(&dmar_global_lock); | |
1138 | index = alloc_irte(iommu, virq, &data->irq_2_iommu, nr_irqs); | |
1139 | up_read(&dmar_global_lock); | |
1140 | if (index < 0) { | |
1141 | pr_warn("Failed to allocate IRTE\n"); | |
1142 | kfree(data); | |
1143 | goto out_free_parent; | |
1144 | } | |
1145 | ||
1146 | for (i = 0; i < nr_irqs; i++) { | |
1147 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
1148 | irq_cfg = irqd_cfg(irq_data); | |
1149 | if (!irq_data || !irq_cfg) { | |
1150 | ret = -EINVAL; | |
1151 | goto out_free_data; | |
1152 | } | |
1153 | ||
1154 | if (i > 0) { | |
1155 | data = kzalloc(sizeof(*data), GFP_KERNEL); | |
1156 | if (!data) | |
1157 | goto out_free_data; | |
1158 | } | |
1159 | irq_data->hwirq = (index << 16) + i; | |
1160 | irq_data->chip_data = data; | |
1161 | irq_data->chip = &intel_ir_chip; | |
1162 | intel_irq_remapping_prepare_irte(data, irq_cfg, info, index, i); | |
1163 | irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT); | |
1164 | } | |
1165 | return 0; | |
1166 | ||
1167 | out_free_data: | |
1168 | intel_free_irq_resources(domain, virq, i); | |
1169 | out_free_parent: | |
1170 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1171 | return ret; | |
1172 | } | |
1173 | ||
1174 | static void intel_irq_remapping_free(struct irq_domain *domain, | |
1175 | unsigned int virq, unsigned int nr_irqs) | |
1176 | { | |
1177 | intel_free_irq_resources(domain, virq, nr_irqs); | |
1178 | irq_domain_free_irqs_common(domain, virq, nr_irqs); | |
1179 | } | |
1180 | ||
1181 | static void intel_irq_remapping_activate(struct irq_domain *domain, | |
1182 | struct irq_data *irq_data) | |
1183 | { | |
1184 | struct intel_ir_data *data = irq_data->chip_data; | |
1185 | ||
1186 | modify_irte(&data->irq_2_iommu, &data->irte_entry); | |
1187 | } | |
1188 | ||
1189 | static void intel_irq_remapping_deactivate(struct irq_domain *domain, | |
1190 | struct irq_data *irq_data) | |
1191 | { | |
1192 | struct intel_ir_data *data = irq_data->chip_data; | |
1193 | struct irte entry; | |
1194 | ||
1195 | memset(&entry, 0, sizeof(entry)); | |
1196 | modify_irte(&data->irq_2_iommu, &entry); | |
1197 | } | |
1198 | ||
1199 | static struct irq_domain_ops intel_ir_domain_ops = { | |
1200 | .alloc = intel_irq_remapping_alloc, | |
1201 | .free = intel_irq_remapping_free, | |
1202 | .activate = intel_irq_remapping_activate, | |
1203 | .deactivate = intel_irq_remapping_deactivate, | |
736baef4 | 1204 | }; |
6b197249 | 1205 | |
a7a3dad9 JL |
1206 | /* |
1207 | * Support of Interrupt Remapping Unit Hotplug | |
1208 | */ | |
1209 | static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu) | |
1210 | { | |
1211 | int ret; | |
1212 | int eim = x2apic_enabled(); | |
1213 | ||
1214 | if (eim && !ecap_eim_support(iommu->ecap)) { | |
1215 | pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n", | |
1216 | iommu->reg_phys, iommu->ecap); | |
1217 | return -ENODEV; | |
1218 | } | |
1219 | ||
1220 | if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) { | |
1221 | pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n", | |
1222 | iommu->reg_phys); | |
1223 | return -ENODEV; | |
1224 | } | |
1225 | ||
1226 | /* TODO: check all IOAPICs are covered by IOMMU */ | |
1227 | ||
1228 | /* Setup Interrupt-remapping now. */ | |
1229 | ret = intel_setup_irq_remapping(iommu); | |
1230 | if (ret) { | |
1231 | pr_err("DRHD %Lx: failed to allocate resource\n", | |
1232 | iommu->reg_phys); | |
1233 | ir_remove_ioapic_hpet_scope(iommu); | |
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | if (!iommu->qi) { | |
1238 | /* Clear previous faults. */ | |
1239 | dmar_fault(-1, iommu); | |
1240 | iommu_disable_irq_remapping(iommu); | |
1241 | dmar_disable_qi(iommu); | |
1242 | } | |
1243 | ||
1244 | /* Enable queued invalidation */ | |
1245 | ret = dmar_enable_qi(iommu); | |
1246 | if (!ret) { | |
1247 | iommu_set_irq_remapping(iommu, eim); | |
1248 | } else { | |
1249 | pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n", | |
1250 | iommu->reg_phys, iommu->ecap, ret); | |
1251 | intel_teardown_irq_remapping(iommu); | |
1252 | ir_remove_ioapic_hpet_scope(iommu); | |
1253 | } | |
1254 | ||
1255 | return ret; | |
1256 | } | |
1257 | ||
6b197249 JL |
1258 | int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert) |
1259 | { | |
a7a3dad9 JL |
1260 | int ret = 0; |
1261 | struct intel_iommu *iommu = dmaru->iommu; | |
1262 | ||
1263 | if (!irq_remapping_enabled) | |
1264 | return 0; | |
1265 | if (iommu == NULL) | |
1266 | return -EINVAL; | |
1267 | if (!ecap_ir_support(iommu->ecap)) | |
1268 | return 0; | |
1269 | ||
1270 | if (insert) { | |
1271 | if (!iommu->ir_table) | |
1272 | ret = dmar_ir_add(dmaru, iommu); | |
1273 | } else { | |
1274 | if (iommu->ir_table) { | |
1275 | if (!bitmap_empty(iommu->ir_table->bitmap, | |
1276 | INTR_REMAP_TABLE_ENTRIES)) { | |
1277 | ret = -EBUSY; | |
1278 | } else { | |
1279 | iommu_disable_irq_remapping(iommu); | |
1280 | intel_teardown_irq_remapping(iommu); | |
1281 | ir_remove_ioapic_hpet_scope(iommu); | |
1282 | } | |
1283 | } | |
1284 | } | |
1285 | ||
1286 | return ret; | |
6b197249 | 1287 | } |